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KVM: x86: cleanup SIGBUS handlers
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c
AS		 29#include "hyperv.h"
30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
022c62cb 42#include "exec/ioport.h"
73aa529a 43#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
68bfd0ad 46#include "migration/migration.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
c0532a76
MT		 67#ifndef BUS_MCEERR_AR
68#define BUS_MCEERR_AR 4
69#endif
70#ifndef BUS_MCEERR_AO
71#define BUS_MCEERR_AO 5
72#endif
73
94a8d39a
JK		 74const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
75 KVM_CAP_INFO(SET_TSS_ADDR),
76 KVM_CAP_INFO(EXT_CPUID),
77 KVM_CAP_INFO(MP_STATE),
78 KVM_CAP_LAST_INFO
79};
25d2e361 80
c3a3a7d3
JK		 81static bool has_msr_star;
82static bool has_msr_hsave_pa;
c9b8f6b6 83static bool has_msr_tsc_aux;
f28558d3 84static bool has_msr_tsc_adjust;
aa82ba54 85static bool has_msr_tsc_deadline;
df67696e 86static bool has_msr_feature_control;
21e87c46 87static bool has_msr_misc_enable;
fc12d72e 88static bool has_msr_smbase;
79e9ebeb 89static bool has_msr_bndcfgs;
25d2e361 90static int lm_capable_kernel;
7bc3d711 91static bool has_msr_hv_hypercall;
f2a53c9e 92static bool has_msr_hv_crash;
744b8a94 93static bool has_msr_hv_reset;
8c145d7c 94static bool has_msr_hv_vpindex;
46eb8f98 95static bool has_msr_hv_runtime;
866eea9a 96static bool has_msr_hv_synic;
ff99aa64 97static bool has_msr_hv_stimer;
18cd2c17 98static bool has_msr_xss;
b827df58 99
0d894367
PB		 100static bool has_msr_architectural_pmu;
101static uint32_t num_architectural_pmu_counters;
102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
6053a86f
MT		 121bool kvm_has_adjust_clock_stable(void)
122{
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126}
127
1d31f66b
PM		 128bool kvm_allows_irq0_override(void)
129{
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131}
132
fb506e70
RK		 133static bool kvm_x2apic_api_set_flags(uint64_t flags)
134{
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138}
139
e391c009 140#define MEMORIZE(fn, _result) \
2a138ec3 141 ({ \
2a138ec3
RK		 142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
e391c009
IM		 151static bool has_x2apic_api;
152
153bool kvm_has_x2apic_api(void)
154{
155 return has_x2apic_api;
156}
157
fb506e70
RK		 158bool kvm_enable_x2apic(void)
159{
2a138ec3
RK		 160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
fb506e70
RK		 164}
165
0fd7e098
LL		 166static int kvm_get_tsc(CPUState *cs)
167{
168 X86CPU *cpu = X86_CPU(cs);
169 CPUX86State *env = &cpu->env;
170 struct {
171 struct kvm_msrs info;
172 struct kvm_msr_entry entries[1];
173 } msr_data;
174 int ret;
175
176 if (env->tsc_valid) {
177 return 0;
178 }
179
180 msr_data.info.nmsrs = 1;
181 msr_data.entries[0].index = MSR_IA32_TSC;
182 env->tsc_valid = !runstate_is_running();
183
184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
185 if (ret < 0) {
186 return ret;
187 }
188
48e1a45c 189 assert(ret == 1);
0fd7e098
LL		 190 env->tsc = msr_data.entries[0].data;
191 return 0;
192}
193
14e6fe12 194static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 195{
0fd7e098
LL		 196 kvm_get_tsc(cpu);
197}
198
199void kvm_synchronize_all_tsc(void)
200{
201 CPUState *cpu;
202
203 if (kvm_enabled()) {
204 CPU_FOREACH(cpu) {
14e6fe12 205 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 206 }
207 }
208}
209
b827df58
AK		 210static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
211{
212 struct kvm_cpuid2 *cpuid;
213 int r, size;
214
215 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 216 cpuid = g_malloc0(size);
b827df58
AK		 217 cpuid->nent = max;
218 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 219 if (r == 0 && cpuid->nent >= max) {
220 r = -E2BIG;
221 }
b827df58
AK		 222 if (r < 0) {
223 if (r == -E2BIG) {
7267c094 224 g_free(cpuid);
b827df58
AK		 225 return NULL;
226 } else {
227 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
228 strerror(-r));
229 exit(1);
230 }
231 }
232 return cpuid;
233}
234
dd87f8a6
EH		 235/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
236 * for all entries.
237 */
238static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
239{
240 struct kvm_cpuid2 *cpuid;
241 int max = 1;
494e95e9
CP		 242
243 if (cpuid_cache != NULL) {
244 return cpuid_cache;
245 }
dd87f8a6
EH		 246 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
247 max *= 2;
248 }
494e95e9 249 cpuid_cache = cpuid;
dd87f8a6
EH		 250 return cpuid;
251}
252
a443bc34 253static const struct kvm_para_features {
0c31b744
GC		 254 int cap;
255 int feature;
256} para_features[] = {
257 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
258 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
259 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 260 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 261};
262
ba9bc59e 263static int get_para_features(KVMState *s)
0c31b744
GC		 264{
265 int i, features = 0;
266
8e03c100 267 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 268 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 269 features |= (1 << para_features[i].feature);
270 }
271 }
272
273 return features;
274}
0c31b744
GC		 275
276
829ae2f9
EH		 277/* Returns the value for a specific register on the cpuid entry
278 */
279static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
280{
281 uint32_t ret = 0;
282 switch (reg) {
283 case R_EAX:
284 ret = entry->eax;
285 break;
286 case R_EBX:
287 ret = entry->ebx;
288 break;
289 case R_ECX:
290 ret = entry->ecx;
291 break;
292 case R_EDX:
293 ret = entry->edx;
294 break;
295 }
296 return ret;
297}
298
4fb73f1d
EH		 299/* Find matching entry for function/index on kvm_cpuid2 struct
300 */
301static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
302 uint32_t function,
303 uint32_t index)
304{
305 int i;
306 for (i = 0; i < cpuid->nent; ++i) {
307 if (cpuid->entries[i].function == function &&
308 cpuid->entries[i].index == index) {
309 return &cpuid->entries[i];
310 }
311 }
312 /* not found: */
313 return NULL;
314}
315
ba9bc59e 316uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 317 uint32_t index, int reg)
b827df58
AK		 318{
319 struct kvm_cpuid2 *cpuid;
b827df58
AK		 320 uint32_t ret = 0;
321 uint32_t cpuid_1_edx;
8c723b79 322 bool found = false;
b827df58 323
dd87f8a6 324 cpuid = get_supported_cpuid(s);
b827df58 325
4fb73f1d
EH		 326 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
327 if (entry) {
328 found = true;
329 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 330 }
331
7b46e5ce
EH		 332 /* Fixups for the data returned by KVM, below */
333
c2acb022
EH		 334 if (function == 1 && reg == R_EDX) {
335 /* KVM before 2.6.30 misreports the following features */
336 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 337 } else if (function == 1 && reg == R_ECX) {
338 /* We can set the hypervisor flag, even if KVM does not return it on
339 * GET_SUPPORTED_CPUID
340 */
341 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 342 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
343 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
344 * and the irqchip is in the kernel.
345 */
346 if (kvm_irqchip_in_kernel() &&
347 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
348 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
349 }
41e5e76d
EH		 350
351 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
352 * without the in-kernel irqchip
353 */
354 if (!kvm_irqchip_in_kernel()) {
355 ret &= ~CPUID_EXT_X2APIC;
b827df58 356 }
28b8e4d0
JK		 357 } else if (function == 6 && reg == R_EAX) {
358 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 359 } else if (function == 0x80000001 && reg == R_EDX) {
360 /* On Intel, kvm returns cpuid according to the Intel spec,
361 * so add missing bits according to the AMD spec:
362 */
363 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
364 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 365 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
366 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
367 * be enabled without the in-kernel irqchip
368 */
369 if (!kvm_irqchip_in_kernel()) {
370 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
371 }
b827df58
AK		 372 }
373
0c31b744 374 /* fallback for older kernels */
8c723b79 375 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 376 ret = get_para_features(s);
b9bec74b 377 }
0c31b744
GC		 378
379 return ret;
bb0300dc 380}
bb0300dc 381
3c85e74f
HY		 382typedef struct HWPoisonPage {
383 ram_addr_t ram_addr;
384 QLIST_ENTRY(HWPoisonPage) list;
385} HWPoisonPage;
386
387static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
388 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
389
390static void kvm_unpoison_all(void *param)
391{
392 HWPoisonPage *page, *next_page;
393
394 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
395 QLIST_REMOVE(page, list);
396 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 397 g_free(page);
3c85e74f
HY		 398 }
399}
400
3c85e74f
HY		 401static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
402{
403 HWPoisonPage *page;
404
405 QLIST_FOREACH(page, &hwpoison_page_list, list) {
406 if (page->ram_addr == ram_addr) {
407 return;
408 }
409 }
ab3ad07f 410 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 411 page->ram_addr = ram_addr;
412 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
413}
414
e7701825
MT		 415static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
416 int *max_banks)
417{
418 int r;
419
14a09518 420 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 421 if (r > 0) {
422 *max_banks = r;
423 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
424 }
425 return -ENOSYS;
426}
427
bee615d4 428static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 429{
87f8b626 430 CPUState *cs = CPU(cpu);
bee615d4 431 CPUX86State *env = &cpu->env;
c34d440a
JK		 432 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
433 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
434 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 435 int flags = 0;
e7701825 436
c34d440a
JK		 437 if (code == BUS_MCEERR_AR) {
438 status |= MCI_STATUS_AR | 0x134;
439 mcg_status |= MCG_STATUS_EIPV;
440 } else {
441 status |= 0xc0;
442 mcg_status |= MCG_STATUS_RIPV;
419fb20a 443 }
87f8b626
AR		 444
445 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
446 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
447 * guest kernel back into env->mcg_ext_ctl.
448 */
449 cpu_synchronize_state(cs);
450 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
451 mcg_status |= MCG_STATUS_LMCE;
452 flags = 0;
453 }
454
8c5cf3b6 455 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 456 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 457}
419fb20a
JK		 458
459static void hardware_memory_error(void)
460{
461 fprintf(stderr, "Hardware memory error!\n");
462 exit(1);
463}
464
20d695a9 465int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 466{
20d695a9
AF		 467 X86CPU *cpu = X86_CPU(c);
468 CPUX86State *env = &cpu->env;
419fb20a 469 ram_addr_t ram_addr;
a8170e5e 470 hwaddr paddr;
419fb20a 471
20e0ff59
PB		 472 if (code != BUS_MCEERR_AR && code != BUS_MCEERR_AO) {
473 return 1;
474 }
475
476 /* Because the MCE happened while running the VCPU, KVM could have
477 * injected action required MCEs too. Action optional MCEs should
478 * be delivered to the main thread, which qemu_init_sigbus identifies
479 * as the "early kill" thread, but if we get one for whatever reason
480 * we just handle it just like the main thread would.
481 */
482 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 483 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 484 if (ram_addr != RAM_ADDR_INVALID &&
485 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
486 kvm_hwpoison_page_add(ram_addr);
487 kvm_mce_inject(cpu, paddr, code);
419fb20a 488 return 0;
419fb20a 489 }
20e0ff59
PB		 490
491 fprintf(stderr, "Hardware memory error for memory used by "
492 "QEMU itself instead of guest system!\n");
419fb20a 493 }
20e0ff59
PB		 494
495 if (code == BUS_MCEERR_AR) {
496 hardware_memory_error();
497 }
498
499 /* Hope we are lucky for AO MCE */
419fb20a
JK		 500 return 0;
501}
502
503int kvm_arch_on_sigbus(int code, void *addr)
504{
182735ef
AF		 505 X86CPU *cpu = X86_CPU(first_cpu);
506
20e0ff59
PB		 507 if (code != BUS_MCEERR_AR && code != BUS_MCEERR_AO) {
508 return 1;
509 }
510
511 if (code == BUS_MCEERR_AR) {
512 hardware_memory_error();
513 }
514
515 /* Hope we are lucky for AO MCE */
516 if ((cpu->env.mcg_cap & MCG_SER_P) && addr) {
419fb20a 517 ram_addr_t ram_addr;
a8170e5e 518 hwaddr paddr;
419fb20a 519
07bdaa41 520 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 521 if (ram_addr != RAM_ADDR_INVALID &&
522 kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
523 addr, &paddr)) {
524 kvm_hwpoison_page_add(ram_addr);
525 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
419fb20a 526 }
20e0ff59
PB		 527
528 fprintf(stderr, "Hardware memory error for memory used by "
529 "QEMU itself instead of guest system!: %p\n", addr);
419fb20a
JK		 530 }
531 return 0;
532}
e7701825 533
1bc22652 534static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 535{
1bc22652
AF		 536 CPUX86State *env = &cpu->env;
537
ab443475
JK		 538 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
539 unsigned int bank, bank_num = env->mcg_cap & 0xff;
540 struct kvm_x86_mce mce;
541
542 env->exception_injected = -1;
543
544 /*
545 * There must be at least one bank in use if an MCE is pending.
546 * Find it and use its values for the event injection.
547 */
548 for (bank = 0; bank < bank_num; bank++) {
549 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
550 break;
551 }
552 }
553 assert(bank < bank_num);
554
555 mce.bank = bank;
556 mce.status = env->mce_banks[bank * 4 + 1];
557 mce.mcg_status = env->mcg_status;
558 mce.addr = env->mce_banks[bank * 4 + 2];
559 mce.misc = env->mce_banks[bank * 4 + 3];
560
1bc22652 561 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 562 }
ab443475
JK		 563 return 0;
564}
565
1dfb4dd9 566static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 567{
317ac620 568 CPUX86State *env = opaque;
b8cc45d6
GC		 569
570 if (running) {
571 env->tsc_valid = false;
572 }
573}
574
83b17af5 575unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 576{
83b17af5 577 X86CPU *cpu = X86_CPU(cs);
7e72a45c 578 return cpu->apic_id;
b164e48e
EH		 579}
580
92067bf4
IM		 581#ifndef KVM_CPUID_SIGNATURE_NEXT
582#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
583#endif
584
585static bool hyperv_hypercall_available(X86CPU *cpu)
586{
587 return cpu->hyperv_vapic ||
588 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
589}
590
591static bool hyperv_enabled(X86CPU *cpu)
592{
7bc3d711
PB		 593 CPUState *cs = CPU(cpu);
594 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
595 (hyperv_hypercall_available(cpu) ||
48a5f3bc 596 cpu->hyperv_time ||
f2a53c9e 597 cpu->hyperv_relaxed_timing ||
744b8a94 598 cpu->hyperv_crash ||
8c145d7c 599 cpu->hyperv_reset ||
46eb8f98 600 cpu->hyperv_vpindex ||
866eea9a 601 cpu->hyperv_runtime ||
ff99aa64
AS		 602 cpu->hyperv_synic ||
603 cpu->hyperv_stimer);
92067bf4
IM		 604}
605
5031283d
HZ		 606static int kvm_arch_set_tsc_khz(CPUState *cs)
607{
608 X86CPU *cpu = X86_CPU(cs);
609 CPUX86State *env = &cpu->env;
610 int r;
611
612 if (!env->tsc_khz) {
613 return 0;
614 }
615
616 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
617 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
618 -ENOTSUP;
619 if (r < 0) {
620 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
621 * TSC frequency doesn't match the one we want.
622 */
623 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
624 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
625 -ENOTSUP;
626 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
627 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 628 "VM (%" PRId64 " kHz) and host (%d kHz), "
629 "and TSC scaling unavailable",
630 env->tsc_khz, cur_freq);
5031283d
HZ		 631 return r;
632 }
633 }
634
635 return 0;
636}
637
c35bd19a
EY		 638static int hyperv_handle_properties(CPUState *cs)
639{
640 X86CPU *cpu = X86_CPU(cs);
641 CPUX86State *env = &cpu->env;
642
3ddcd2ed
EH		 643 if (cpu->hyperv_time &&
644 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
645 cpu->hyperv_time = false;
646 }
647
c35bd19a
EY		 648 if (cpu->hyperv_relaxed_timing) {
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
650 }
651 if (cpu->hyperv_vapic) {
652 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 654 }
3ddcd2ed 655 if (cpu->hyperv_time) {
c35bd19a
EY		 656 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
657 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
658 env->features[FEAT_HYPERV_EAX] |= 0x200;
c35bd19a
EY		 659 }
660 if (cpu->hyperv_crash && has_msr_hv_crash) {
661 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
662 }
663 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
664 if (cpu->hyperv_reset && has_msr_hv_reset) {
665 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
666 }
667 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
668 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
669 }
670 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
671 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
672 }
673 if (cpu->hyperv_synic) {
674 int sint;
675
676 if (!has_msr_hv_synic ||
677 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
678 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
679 return -ENOSYS;
680 }
681
682 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
683 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
684 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
685 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
686 }
687 }
688 if (cpu->hyperv_stimer) {
689 if (!has_msr_hv_stimer) {
690 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
691 return -ENOSYS;
692 }
693 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
694 }
695 return 0;
696}
697
68bfd0ad
MT		 698static Error *invtsc_mig_blocker;
699
f8bb0565 700#define KVM_MAX_CPUID_ENTRIES 100
0893d460 701
20d695a9 702int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 703{
704 struct {
486bd5a2 705 struct kvm_cpuid2 cpuid;
f8bb0565 706 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 707 } QEMU_PACKED cpuid_data;
20d695a9
AF		 708 X86CPU *cpu = X86_CPU(cs);
709 CPUX86State *env = &cpu->env;
486bd5a2 710 uint32_t limit, i, j, cpuid_i;
a33609ca 711 uint32_t unused;
bb0300dc 712 struct kvm_cpuid_entry2 *c;
bb0300dc 713 uint32_t signature[3];
234cc647 714 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 715 int r;
fe44dc91 716 Error *local_err = NULL;
05330448 717
ef4cbe14
SW		 718 memset(&cpuid_data, 0, sizeof(cpuid_data));
719
05330448
AL		 720 cpuid_i = 0;
721
bb0300dc 722 /* Paravirtualization CPUIDs */
234cc647
PB		 723 if (hyperv_enabled(cpu)) {
724 c = &cpuid_data.entries[cpuid_i++];
725 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 726 if (!cpu->hyperv_vendor_id) {
727 memcpy(signature, "Microsoft Hv", 12);
728 } else {
729 size_t len = strlen(cpu->hyperv_vendor_id);
730
731 if (len > 12) {
732 error_report("hv-vendor-id truncated to 12 characters");
733 len = 12;
734 }
735 memset(signature, 0, 12);
736 memcpy(signature, cpu->hyperv_vendor_id, len);
737 }
eab70139 738 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 739 c->ebx = signature[0];
740 c->ecx = signature[1];
741 c->edx = signature[2];
0c31b744 742
234cc647
PB		 743 c = &cpuid_data.entries[cpuid_i++];
744 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 745 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
746 c->eax = signature[0];
234cc647
PB		 747 c->ebx = 0;
748 c->ecx = 0;
749 c->edx = 0;
eab70139
VR		 750
751 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 752 c->function = HYPERV_CPUID_VERSION;
753 c->eax = 0x00001bbc;
754 c->ebx = 0x00060001;
755
756 c = &cpuid_data.entries[cpuid_i++];
eab70139 757 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 758 r = hyperv_handle_properties(cs);
759 if (r) {
760 return r;
46eb8f98 761 }
c35bd19a
EY		 762 c->eax = env->features[FEAT_HYPERV_EAX];
763 c->ebx = env->features[FEAT_HYPERV_EBX];
764 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 765
eab70139 766 c = &cpuid_data.entries[cpuid_i++];
eab70139 767 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 768 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 769 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
770 }
2d5aa872 771 if (cpu->hyperv_vapic) {
eab70139
VR		 772 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
773 }
92067bf4 774 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 775
776 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 777 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
778 c->eax = 0x40;
779 c->ebx = 0x40;
780
234cc647 781 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 782 has_msr_hv_hypercall = true;
eab70139
VR		 783 }
784
f522d2ac
AW		 785 if (cpu->expose_kvm) {
786 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
787 c = &cpuid_data.entries[cpuid_i++];
788 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 789 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 790 c->ebx = signature[0];
791 c->ecx = signature[1];
792 c->edx = signature[2];
234cc647 793
f522d2ac
AW		 794 c = &cpuid_data.entries[cpuid_i++];
795 c->function = KVM_CPUID_FEATURES | kvm_base;
796 c->eax = env->features[FEAT_KVM];
f522d2ac 797 }
917367aa 798
a33609ca 799 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 800
801 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 802 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
803 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
804 abort();
805 }
bb0300dc 806 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 807
808 switch (i) {
a36b1029
AL		 809 case 2: {
810 /* Keep reading function 2 till all the input is received */
811 int times;
812
a36b1029 813 c->function = i;
a33609ca
AL		 814 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
815 KVM_CPUID_FLAG_STATE_READ_NEXT;
816 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
817 times = c->eax & 0xff;
a36b1029
AL		 818
819 for (j = 1; j < times; ++j) {
f8bb0565
IM		 820 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
821 fprintf(stderr, "cpuid_data is full, no space for "
822 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
823 abort();
824 }
a33609ca 825 c = &cpuid_data.entries[cpuid_i++];
a36b1029 826 c->function = i;
a33609ca
AL		 827 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 829 }
830 break;
831 }
486bd5a2
AL		 832 case 4:
833 case 0xb:
834 case 0xd:
835 for (j = 0; ; j++) {
31e8c696
AP		 836 if (i == 0xd && j == 64) {
837 break;
838 }
486bd5a2
AL		 839 c->function = i;
840 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
841 c->index = j;
a33609ca 842 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 843
b9bec74b 844 if (i == 4 && c->eax == 0) {
486bd5a2 845 break;
b9bec74b
JK		 846 }
847 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 848 break;
b9bec74b
JK		 849 }
850 if (i == 0xd && c->eax == 0) {
31e8c696 851 continue;
b9bec74b 852 }
f8bb0565
IM		 853 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
854 fprintf(stderr, "cpuid_data is full, no space for "
855 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
856 abort();
857 }
a33609ca 858 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 859 }
860 break;
861 default:
486bd5a2 862 c->function = i;
a33609ca
AL		 863 c->flags = 0;
864 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 865 break;
866 }
05330448 867 }
0d894367
PB		 868
869 if (limit >= 0x0a) {
870 uint32_t ver;
871
872 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
873 if ((ver & 0xff) > 0) {
874 has_msr_architectural_pmu = true;
875 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
876
877 /* Shouldn't be more than 32, since that's the number of bits
878 * available in EBX to tell us _which_ counters are available.
879 * Play it safe.
880 */
881 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
882 num_architectural_pmu_counters = MAX_GP_COUNTERS;
883 }
884 }
885 }
886
a33609ca 887 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 888
889 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 890 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
891 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
892 abort();
893 }
bb0300dc 894 c = &cpuid_data.entries[cpuid_i++];
05330448 895
05330448 896 c->function = i;
a33609ca
AL		 897 c->flags = 0;
898 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 899 }
900
b3baa152
BW		 901 /* Call Centaur's CPUID instructions they are supported. */
902 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 903 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
904
905 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 906 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
907 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
908 abort();
909 }
b3baa152
BW		 910 c = &cpuid_data.entries[cpuid_i++];
911
912 c->function = i;
913 c->flags = 0;
914 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
915 }
916 }
917
05330448
AL		 918 cpuid_data.cpuid.nent = cpuid_i;
919
e7701825 920 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 921 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 922 (CPUID_MCE | CPUID_MCA)
a60f24b5 923 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 924 uint64_t mcg_cap, unsupported_caps;
e7701825 925 int banks;
32a42024 926 int ret;
e7701825 927
a60f24b5 928 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 929 if (ret < 0) {
930 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
931 return ret;
e7701825 932 }
75d49497 933
2590f15b 934 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 935 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 936 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 937 return -ENOTSUP;
75d49497 938 }
49b69cbf 939
5120901a
EH		 940 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
941 if (unsupported_caps) {
87f8b626
AR		 942 if (unsupported_caps & MCG_LMCE_P) {
943 error_report("kvm: LMCE not supported");
944 return -ENOTSUP;
945 }
5120901a
EH		 946 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
947 unsupported_caps);
948 }
949
2590f15b
EH		 950 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
951 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 952 if (ret < 0) {
953 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
954 return ret;
955 }
e7701825 956 }
e7701825 957
b8cc45d6
GC		 958 qemu_add_vm_change_state_handler(cpu_update_state, env);
959
df67696e
LJ		 960 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
961 if (c) {
962 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
963 !!(c->ecx & CPUID_EXT_SMX);
964 }
965
87f8b626
AR		 966 if (env->mcg_cap & MCG_LMCE_P) {
967 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
968 }
969
d99569d9
EH		 970 if (!env->user_tsc_khz) {
971 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
972 invtsc_mig_blocker == NULL) {
973 /* for migration */
974 error_setg(&invtsc_mig_blocker,
975 "State blocked by non-migratable CPU device"
976 " (invtsc flag)");
fe44dc91
AA		 977 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
978 if (local_err) {
979 error_report_err(local_err);
980 error_free(invtsc_mig_blocker);
981 goto fail;
982 }
d99569d9
EH		 983 /* for savevm */
984 vmstate_x86_cpu.unmigratable = 1;
985 }
68bfd0ad
MT		 986 }
987
5031283d
HZ		 988 r = kvm_arch_set_tsc_khz(cs);
989 if (r < 0) {
fe44dc91 990 goto fail;
e7429073 991 }
e7429073 992
bcffbeeb
HZ		 993 /* vcpu's TSC frequency is either specified by user, or following
994 * the value used by KVM if the former is not present. In the
995 * latter case, we query it from KVM and record in env->tsc_khz,
996 * so that vcpu's TSC frequency can be migrated later via this field.
997 */
998 if (!env->tsc_khz) {
999 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1000 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1001 -ENOTSUP;
1002 if (r > 0) {
1003 env->tsc_khz = r;
1004 }
1005 }
1006
9954a158
PDJ		 1007 if (cpu->vmware_cpuid_freq
1008 /* Guests depend on 0x40000000 to detect this feature, so only expose
1009 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1010 && cpu->expose_kvm
1011 && kvm_base == KVM_CPUID_SIGNATURE
1012 /* TSC clock must be stable and known for this feature. */
1013 && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
1014 || env->user_tsc_khz != 0)
1015 && env->tsc_khz != 0) {
1016
1017 c = &cpuid_data.entries[cpuid_i++];
1018 c->function = KVM_CPUID_SIGNATURE | 0x10;
1019 c->eax = env->tsc_khz;
1020 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1021 * APIC_BUS_CYCLE_NS */
1022 c->ebx = 1000000;
1023 c->ecx = c->edx = 0;
1024
1025 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1026 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1027 }
1028
1029 cpuid_data.cpuid.nent = cpuid_i;
1030
1031 cpuid_data.cpuid.padding = 0;
1032 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1033 if (r) {
1034 goto fail;
1035 }
1036
28143b40 1037 if (has_xsave) {
fabacc0f
JK		 1038 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1039 }
d71b62a1 1040 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1041
273c515c
PB		 1042 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1043 has_msr_tsc_aux = false;
1044 }
d1ae67f6 1045
e7429073 1046 return 0;
fe44dc91
AA		 1047
1048 fail:
1049 migrate_del_blocker(invtsc_mig_blocker);
1050 return r;
05330448
AL		 1051}
1052
50a2c6e5 1053void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1054{
20d695a9 1055 CPUX86State *env = &cpu->env;
dd673288 1056
e73223a5 1057 env->exception_injected = -1;
0e607a80 1058 env->interrupt_injected = -1;
1a5e9d2f 1059 env->xcr0 = 1;
ddced198 1060 if (kvm_irqchip_in_kernel()) {
dd673288 1061 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1062 KVM_MP_STATE_UNINITIALIZED;
1063 } else {
1064 env->mp_state = KVM_MP_STATE_RUNNABLE;
1065 }
caa5af0f
JK		 1066}
1067
e0723c45
PB		 1068void kvm_arch_do_init_vcpu(X86CPU *cpu)
1069{
1070 CPUX86State *env = &cpu->env;
1071
1072 /* APs get directly into wait-for-SIPI state. */
1073 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1074 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1075 }
1076}
1077
c3a3a7d3 1078static int kvm_get_supported_msrs(KVMState *s)
05330448 1079{
75b10c43 1080 static int kvm_supported_msrs;
c3a3a7d3 1081 int ret = 0;
05330448
AL		 1082
1083 /* first time */
75b10c43 1084 if (kvm_supported_msrs == 0) {
05330448
AL		 1085 struct kvm_msr_list msr_list, *kvm_msr_list;
1086
75b10c43 1087 kvm_supported_msrs = -1;
05330448
AL		 1088
1089 /* Obtain MSR list from KVM. These are the MSRs that we must
1090 * save/restore */
4c9f7372 1091 msr_list.nmsrs = 0;
c3a3a7d3 1092 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1093 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1094 return ret;
6fb6d245 1095 }
d9db889f
JK		 1096 /* Old kernel modules had a bug and could write beyond the provided
1097 memory. Allocate at least a safe amount of 1K. */
7267c094 1098 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1099 msr_list.nmsrs *
1100 sizeof(msr_list.indices[0])));
05330448 1101
55308450 1102 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1103 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1104 if (ret >= 0) {
1105 int i;
1106
1107 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1108 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1109 has_msr_star = true;
75b10c43
MT		 1110 continue;
1111 }
1112 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1113 has_msr_hsave_pa = true;
75b10c43 1114 continue;
05330448 1115 }
c9b8f6b6
AS		 1116 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1117 has_msr_tsc_aux = true;
1118 continue;
1119 }
f28558d3
WA		 1120 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1121 has_msr_tsc_adjust = true;
1122 continue;
1123 }
aa82ba54
LJ		 1124 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1125 has_msr_tsc_deadline = true;
1126 continue;
1127 }
fc12d72e
PB		 1128 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1129 has_msr_smbase = true;
1130 continue;
1131 }
21e87c46
AK		 1132 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1133 has_msr_misc_enable = true;
1134 continue;
1135 }
79e9ebeb
LJ		 1136 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1137 has_msr_bndcfgs = true;
1138 continue;
1139 }
18cd2c17
WL		 1140 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1141 has_msr_xss = true;
1142 continue;
1143 }
f2a53c9e
AS		 1144 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1145 has_msr_hv_crash = true;
1146 continue;
1147 }
744b8a94
AS		 1148 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1149 has_msr_hv_reset = true;
1150 continue;
1151 }
8c145d7c
AS		 1152 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1153 has_msr_hv_vpindex = true;
1154 continue;
1155 }
46eb8f98
AS		 1156 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1157 has_msr_hv_runtime = true;
1158 continue;
1159 }
866eea9a
AS		 1160 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1161 has_msr_hv_synic = true;
1162 continue;
1163 }
ff99aa64
AS		 1164 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1165 has_msr_hv_stimer = true;
1166 continue;
1167 }
05330448
AL		 1168 }
1169 }
1170
7267c094 1171 g_free(kvm_msr_list);
05330448
AL		 1172 }
1173
c3a3a7d3 1174 return ret;
05330448
AL		 1175}
1176
6410848b
PB		 1177static Notifier smram_machine_done;
1178static KVMMemoryListener smram_listener;
1179static AddressSpace smram_address_space;
1180static MemoryRegion smram_as_root;
1181static MemoryRegion smram_as_mem;
1182
1183static void register_smram_listener(Notifier *n, void *unused)
1184{
1185 MemoryRegion *smram =
1186 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1187
1188 /* Outer container... */
1189 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1190 memory_region_set_enabled(&smram_as_root, true);
1191
1192 /* ... with two regions inside: normal system memory with low
1193 * priority, and...
1194 */
1195 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1196 get_system_memory(), 0, ~0ull);
1197 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1198 memory_region_set_enabled(&smram_as_mem, true);
1199
1200 if (smram) {
1201 /* ... SMRAM with higher priority */
1202 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1203 memory_region_set_enabled(smram, true);
1204 }
1205
1206 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1207 kvm_memory_listener_register(kvm_state, &smram_listener,
1208 &smram_address_space, 1);
1209}
1210
b16565b3 1211int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1212{
11076198 1213 uint64_t identity_base = 0xfffbc000;
39d6960a 1214 uint64_t shadow_mem;
20420430 1215 int ret;
25d2e361 1216 struct utsname utsname;
20420430 1217
28143b40
TH		 1218#ifdef KVM_CAP_XSAVE
1219 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1220#endif
1221
1222#ifdef KVM_CAP_XCRS
1223 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1224#endif
1225
1226#ifdef KVM_CAP_PIT_STATE2
1227 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1228#endif
1229
c3a3a7d3 1230 ret = kvm_get_supported_msrs(s);
20420430 1231 if (ret < 0) {
20420430
SY		 1232 return ret;
1233 }
25d2e361
MT		 1234
1235 uname(&utsname);
1236 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1237
4c5b10b7 1238 /*
11076198
JK		 1239 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1240 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1241 * Since these must be part of guest physical memory, we need to allocate
1242 * them, both by setting their start addresses in the kernel and by
1243 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1244 *
1245 * Older KVM versions may not support setting the identity map base. In
1246 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1247 * size.
4c5b10b7 1248 */
11076198
JK		 1249 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1250 /* Allows up to 16M BIOSes. */
1251 identity_base = 0xfeffc000;
1252
1253 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1254 if (ret < 0) {
1255 return ret;
1256 }
4c5b10b7 1257 }
e56ff191 1258
11076198
JK		 1259 /* Set TSS base one page after EPT identity map. */
1260 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1261 if (ret < 0) {
1262 return ret;
1263 }
1264
11076198
JK		 1265 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1266 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1267 if (ret < 0) {
11076198 1268 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1269 return ret;
1270 }
3c85e74f 1271 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1272
4689b77b 1273 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1274 if (shadow_mem != -1) {
1275 shadow_mem /= 4096;
1276 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1277 if (ret < 0) {
1278 return ret;
39d6960a
JK		 1279 }
1280 }
6410848b
PB		 1281
1282 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1283 smram_machine_done.notify = register_smram_listener;
1284 qemu_add_machine_init_done_notifier(&smram_machine_done);
1285 }
11076198 1286 return 0;
05330448 1287}
b9bec74b 1288
05330448
AL		 1289static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1290{
1291 lhs->selector = rhs->selector;
1292 lhs->base = rhs->base;
1293 lhs->limit = rhs->limit;
1294 lhs->type = 3;
1295 lhs->present = 1;
1296 lhs->dpl = 3;
1297 lhs->db = 0;
1298 lhs->s = 1;
1299 lhs->l = 0;
1300 lhs->g = 0;
1301 lhs->avl = 0;
1302 lhs->unusable = 0;
1303}
1304
1305static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1306{
1307 unsigned flags = rhs->flags;
1308 lhs->selector = rhs->selector;
1309 lhs->base = rhs->base;
1310 lhs->limit = rhs->limit;
1311 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1312 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1313 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1314 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1315 lhs->s = (flags & DESC_S_MASK) != 0;
1316 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1317 lhs->g = (flags & DESC_G_MASK) != 0;
1318 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1319 lhs->unusable = !lhs->present;
7e680753 1320 lhs->padding = 0;
05330448
AL		 1321}
1322
1323static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1324{
1325 lhs->selector = rhs->selector;
1326 lhs->base = rhs->base;
1327 lhs->limit = rhs->limit;
4cae9c97
MC		 1328 if (rhs->unusable) {
1329 lhs->flags = 0;
1330 } else {
1331 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1332 (rhs->present * DESC_P_MASK) |
1333 (rhs->dpl << DESC_DPL_SHIFT) |
1334 (rhs->db << DESC_B_SHIFT) |
1335 (rhs->s * DESC_S_MASK) |
1336 (rhs->l << DESC_L_SHIFT) |
1337 (rhs->g * DESC_G_MASK) |
1338 (rhs->avl * DESC_AVL_MASK);
1339 }
05330448
AL		 1340}
1341
1342static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1343{
b9bec74b 1344 if (set) {
05330448 1345 *kvm_reg = *qemu_reg;
b9bec74b 1346 } else {
05330448 1347 *qemu_reg = *kvm_reg;
b9bec74b 1348 }
05330448
AL		 1349}
1350
1bc22652 1351static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1352{
1bc22652 1353 CPUX86State *env = &cpu->env;
05330448
AL		 1354 struct kvm_regs regs;
1355 int ret = 0;
1356
1357 if (!set) {
1bc22652 1358 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1359 if (ret < 0) {
05330448 1360 return ret;
b9bec74b 1361 }
05330448
AL		 1362 }
1363
1364 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1365 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1366 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1367 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1368 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1369 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1370 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1371 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1372#ifdef TARGET_X86_64
1373 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1374 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1375 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1376 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1377 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1378 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1379 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1380 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1381#endif
1382
1383 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1384 kvm_getput_reg(&regs.rip, &env->eip, set);
1385
b9bec74b 1386 if (set) {
1bc22652 1387 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1388 }
05330448
AL		 1389
1390 return ret;
1391}
1392
1bc22652 1393static int kvm_put_fpu(X86CPU *cpu)
05330448 1394{
1bc22652 1395 CPUX86State *env = &cpu->env;
05330448
AL		 1396 struct kvm_fpu fpu;
1397 int i;
1398
1399 memset(&fpu, 0, sizeof fpu);
1400 fpu.fsw = env->fpus & ~(7 << 11);
1401 fpu.fsw |= (env->fpstt & 7) << 11;
1402 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1403 fpu.last_opcode = env->fpop;
1404 fpu.last_ip = env->fpip;
1405 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1406 for (i = 0; i < 8; ++i) {
1407 fpu.ftwx |= (!env->fptags[i]) << i;
1408 }
05330448 1409 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1410 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1411 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1412 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1413 }
05330448
AL		 1414 fpu.mxcsr = env->mxcsr;
1415
1bc22652 1416 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1417}
1418
6b42494b
JK		 1419#define XSAVE_FCW_FSW 0
1420#define XSAVE_FTW_FOP 1
f1665b21
SY		 1421#define XSAVE_CWD_RIP 2
1422#define XSAVE_CWD_RDP 4
1423#define XSAVE_MXCSR 6
1424#define XSAVE_ST_SPACE 8
1425#define XSAVE_XMM_SPACE 40
1426#define XSAVE_XSTATE_BV 128
1427#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1428#define XSAVE_BNDREGS 240
1429#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1430#define XSAVE_OPMASK 272
1431#define XSAVE_ZMM_Hi256 288
1432#define XSAVE_Hi16_ZMM 416
f74eefe0 1433#define XSAVE_PKRU 672
f1665b21 1434
b503717d
EH		 1435#define XSAVE_BYTE_OFFSET(word_offset) \
1436 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1437
1438#define ASSERT_OFFSET(word_offset, field) \
1439 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1440 offsetof(X86XSaveArea, field))
1441
1442ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1443ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1444ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1445ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1446ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1447ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1448ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1449ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1450ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1451ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1452ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1453ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1454ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1455ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1456ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1457
1bc22652 1458static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1459{
1bc22652 1460 CPUX86State *env = &cpu->env;
86cd2ea0 1461 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1462 uint16_t cwd, swd, twd;
9be38598 1463 int i;
f1665b21 1464
28143b40 1465 if (!has_xsave) {
1bc22652 1466 return kvm_put_fpu(cpu);
b9bec74b 1467 }
f1665b21 1468
f1665b21 1469 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1470 twd = 0;
f1665b21
SY		 1471 swd = env->fpus & ~(7 << 11);
1472 swd |= (env->fpstt & 7) << 11;
1473 cwd = env->fpuc;
b9bec74b 1474 for (i = 0; i < 8; ++i) {
f1665b21 1475 twd |= (!env->fptags[i]) << i;
b9bec74b 1476 }
86cd2ea0
EH		 1477 xsave->legacy.fcw = cwd;
1478 xsave->legacy.fsw = swd;
1479 xsave->legacy.ftw = twd;
1480 xsave->legacy.fpop = env->fpop;
1481 xsave->legacy.fpip = env->fpip;
1482 xsave->legacy.fpdp = env->fpdp;
1483 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1484 sizeof env->fpregs);
86cd2ea0
EH		 1485 xsave->legacy.mxcsr = env->mxcsr;
1486 xsave->header.xstate_bv = env->xstate_bv;
1487 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1488 sizeof env->bnd_regs);
86cd2ea0
EH		 1489 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1490 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1491 sizeof env->opmask_regs);
bee81887 1492
86cd2ea0
EH		 1493 for (i = 0; i < CPU_NB_REGS; i++) {
1494 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1495 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1496 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1497 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1498 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1499 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1500 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1501 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1502 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1503 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1504 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1505 }
1506
9aecd6f8 1507#ifdef TARGET_X86_64
86cd2ea0 1508 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1509 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1510 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1511#endif
9be38598 1512 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1513}
1514
1bc22652 1515static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1516{
1bc22652 1517 CPUX86State *env = &cpu->env;
bdfc8480 1518 struct kvm_xcrs xcrs = {};
f1665b21 1519
28143b40 1520 if (!has_xcrs) {
f1665b21 1521 return 0;
b9bec74b 1522 }
f1665b21
SY		 1523
1524 xcrs.nr_xcrs = 1;
1525 xcrs.flags = 0;
1526 xcrs.xcrs[0].xcr = 0;
1527 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1528 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1529}
1530
1bc22652 1531static int kvm_put_sregs(X86CPU *cpu)
05330448 1532{
1bc22652 1533 CPUX86State *env = &cpu->env;
05330448
AL		 1534 struct kvm_sregs sregs;
1535
0e607a80
JK		 1536 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1537 if (env->interrupt_injected >= 0) {
1538 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1539 (uint64_t)1 << (env->interrupt_injected % 64);
1540 }
05330448
AL		 1541
1542 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1543 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1544 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1545 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1546 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1547 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1548 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1549 } else {
b9bec74b
JK		 1550 set_seg(&sregs.cs, &env->segs[R_CS]);
1551 set_seg(&sregs.ds, &env->segs[R_DS]);
1552 set_seg(&sregs.es, &env->segs[R_ES]);
1553 set_seg(&sregs.fs, &env->segs[R_FS]);
1554 set_seg(&sregs.gs, &env->segs[R_GS]);
1555 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1556 }
1557
1558 set_seg(&sregs.tr, &env->tr);
1559 set_seg(&sregs.ldt, &env->ldt);
1560
1561 sregs.idt.limit = env->idt.limit;
1562 sregs.idt.base = env->idt.base;
7e680753 1563 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1564 sregs.gdt.limit = env->gdt.limit;
1565 sregs.gdt.base = env->gdt.base;
7e680753 1566 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1567
1568 sregs.cr0 = env->cr[0];
1569 sregs.cr2 = env->cr[2];
1570 sregs.cr3 = env->cr[3];
1571 sregs.cr4 = env->cr[4];
1572
02e51483
CF		 1573 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1574 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1575
1576 sregs.efer = env->efer;
1577
1bc22652 1578 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1579}
1580
d71b62a1
EH		 1581static void kvm_msr_buf_reset(X86CPU *cpu)
1582{
1583 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1584}
1585
9c600a84
EH		 1586static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1587{
1588 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1589 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1590 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1591
1592 assert((void *)(entry + 1) <= limit);
1593
1abc2cae
EH		 1594 entry->index = index;
1595 entry->reserved = 0;
1596 entry->data = value;
9c600a84
EH		 1597 msrs->nmsrs++;
1598}
1599
73e1b8f2
PB		 1600static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1601{
1602 kvm_msr_buf_reset(cpu);
1603 kvm_msr_entry_add(cpu, index, value);
1604
1605 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1606}
1607
f8d9ccf8
DDAG		 1608void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1609{
1610 int ret;
1611
1612 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1613 assert(ret == 1);
1614}
1615
7477cd38
MT		 1616static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1617{
1618 CPUX86State *env = &cpu->env;
48e1a45c 1619 int ret;
7477cd38
MT		 1620
1621 if (!has_msr_tsc_deadline) {
1622 return 0;
1623 }
1624
73e1b8f2 1625 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1626 if (ret < 0) {
1627 return ret;
1628 }
1629
1630 assert(ret == 1);
1631 return 0;
7477cd38
MT		 1632}
1633
6bdf863d
JK		 1634/*
1635 * Provide a separate write service for the feature control MSR in order to
1636 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1637 * before writing any other state because forcibly leaving nested mode
1638 * invalidates the VCPU state.
1639 */
1640static int kvm_put_msr_feature_control(X86CPU *cpu)
1641{
48e1a45c
PB		 1642 int ret;
1643
1644 if (!has_msr_feature_control) {
1645 return 0;
1646 }
6bdf863d 1647
73e1b8f2
PB		 1648 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1649 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1650 if (ret < 0) {
1651 return ret;
1652 }
1653
1654 assert(ret == 1);
1655 return 0;
6bdf863d
JK		 1656}
1657
1bc22652 1658static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1659{
1bc22652 1660 CPUX86State *env = &cpu->env;
9c600a84 1661 int i;
48e1a45c 1662 int ret;
05330448 1663
d71b62a1
EH		 1664 kvm_msr_buf_reset(cpu);
1665
9c600a84
EH		 1666 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1667 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1668 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1669 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1670 if (has_msr_star) {
9c600a84 1671 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1672 }
c3a3a7d3 1673 if (has_msr_hsave_pa) {
9c600a84 1674 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1675 }
c9b8f6b6 1676 if (has_msr_tsc_aux) {
9c600a84 1677 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1678 }
f28558d3 1679 if (has_msr_tsc_adjust) {
9c600a84 1680 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1681 }
21e87c46 1682 if (has_msr_misc_enable) {
9c600a84 1683 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1684 env->msr_ia32_misc_enable);
1685 }
fc12d72e 1686 if (has_msr_smbase) {
9c600a84 1687 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1688 }
439d19f2 1689 if (has_msr_bndcfgs) {
9c600a84 1690 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1691 }
18cd2c17 1692 if (has_msr_xss) {
9c600a84 1693 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1694 }
05330448 1695#ifdef TARGET_X86_64
25d2e361 1696 if (lm_capable_kernel) {
9c600a84
EH		 1697 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1698 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1699 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1700 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1701 }
05330448 1702#endif
ff5c186b 1703 /*
0d894367
PB		 1704 * The following MSRs have side effects on the guest or are too heavy
1705 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1706 */
1707 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1708 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1709 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1710 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1711 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1712 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1713 }
55c911a5 1714 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1715 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1716 }
55c911a5 1717 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1718 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1719 }
0d894367
PB		 1720 if (has_msr_architectural_pmu) {
1721 /* Stop the counter. */
9c600a84
EH		 1722 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1723 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1724
1725 /* Set the counter values. */
1726 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1727 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1728 env->msr_fixed_counters[i]);
1729 }
1730 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1731 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1732 env->msr_gp_counters[i]);
9c600a84 1733 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1734 env->msr_gp_evtsel[i]);
1735 }
9c600a84 1736 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1737 env->msr_global_status);
9c600a84 1738 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1739 env->msr_global_ovf_ctrl);
1740
1741 /* Now start the PMU. */
9c600a84 1742 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1743 env->msr_fixed_ctr_ctrl);
9c600a84 1744 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1745 env->msr_global_ctrl);
1746 }
7bc3d711 1747 if (has_msr_hv_hypercall) {
9c600a84 1748 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1749 env->msr_hv_guest_os_id);
9c600a84 1750 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1751 env->msr_hv_hypercall);
eab70139 1752 }
2d5aa872 1753 if (cpu->hyperv_vapic) {
9c600a84 1754 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1755 env->msr_hv_vapic);
eab70139 1756 }
3ddcd2ed 1757 if (cpu->hyperv_time) {
9c600a84 1758 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1759 }
f2a53c9e
AS		 1760 if (has_msr_hv_crash) {
1761 int j;
1762
1763 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1764 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1765 env->msr_hv_crash_params[j]);
1766
9c600a84 1767 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1768 HV_X64_MSR_CRASH_CTL_NOTIFY);
1769 }
46eb8f98 1770 if (has_msr_hv_runtime) {
9c600a84 1771 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1772 }
866eea9a
AS		 1773 if (cpu->hyperv_synic) {
1774 int j;
1775
9c600a84 1776 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1777 env->msr_hv_synic_control);
9c600a84 1778 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1779 env->msr_hv_synic_version);
9c600a84 1780 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1781 env->msr_hv_synic_evt_page);
9c600a84 1782 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1783 env->msr_hv_synic_msg_page);
1784
1785 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1786 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1787 env->msr_hv_synic_sint[j]);
1788 }
1789 }
ff99aa64
AS		 1790 if (has_msr_hv_stimer) {
1791 int j;
1792
1793 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1794 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1795 env->msr_hv_stimer_config[j]);
1796 }
1797
1798 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1799 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1800 env->msr_hv_stimer_count[j]);
1801 }
1802 }
1eabfce6 1803 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1804 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1805
9c600a84
EH		 1806 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1807 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1808 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1809 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1810 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1811 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1812 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1813 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1814 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1815 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1816 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1817 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1818 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1819 /* The CPU GPs if we write to a bit above the physical limit of
1820 * the host CPU (and KVM emulates that)
1821 */
1822 uint64_t mask = env->mtrr_var[i].mask;
1823 mask &= phys_mask;
1824
9c600a84
EH		 1825 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1826 env->mtrr_var[i].base);
112dad69 1827 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1828 }
1829 }
6bdf863d
JK		 1830
1831 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1832 * kvm_put_msr_feature_control. */
ea643051 1833 }
57780495 1834 if (env->mcg_cap) {
d8da8574 1835 int i;
b9bec74b 1836
9c600a84
EH		 1837 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1838 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1839 if (has_msr_mcg_ext_ctl) {
1840 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1841 }
c34d440a 1842 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1843 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1844 }
1845 }
1a03675d 1846
d71b62a1 1847 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1848 if (ret < 0) {
1849 return ret;
1850 }
05330448 1851
9c600a84 1852 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1853 return 0;
05330448
AL		 1854}
1855
1856
1bc22652 1857static int kvm_get_fpu(X86CPU *cpu)
05330448 1858{
1bc22652 1859 CPUX86State *env = &cpu->env;
05330448
AL		 1860 struct kvm_fpu fpu;
1861 int i, ret;
1862
1bc22652 1863 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1864 if (ret < 0) {
05330448 1865 return ret;
b9bec74b 1866 }
05330448
AL		 1867
1868 env->fpstt = (fpu.fsw >> 11) & 7;
1869 env->fpus = fpu.fsw;
1870 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1871 env->fpop = fpu.last_opcode;
1872 env->fpip = fpu.last_ip;
1873 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1874 for (i = 0; i < 8; ++i) {
1875 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1876 }
05330448 1877 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1878 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1879 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1880 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1881 }
05330448
AL		 1882 env->mxcsr = fpu.mxcsr;
1883
1884 return 0;
1885}
1886
1bc22652 1887static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1888{
1bc22652 1889 CPUX86State *env = &cpu->env;
86cd2ea0 1890 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1891 int ret, i;
42cc8fa6 1892 uint16_t cwd, swd, twd;
f1665b21 1893
28143b40 1894 if (!has_xsave) {
1bc22652 1895 return kvm_get_fpu(cpu);
b9bec74b 1896 }
f1665b21 1897
1bc22652 1898 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1899 if (ret < 0) {
f1665b21 1900 return ret;
0f53994f 1901 }
f1665b21 1902
86cd2ea0
EH		 1903 cwd = xsave->legacy.fcw;
1904 swd = xsave->legacy.fsw;
1905 twd = xsave->legacy.ftw;
1906 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1907 env->fpstt = (swd >> 11) & 7;
1908 env->fpus = swd;
1909 env->fpuc = cwd;
b9bec74b 1910 for (i = 0; i < 8; ++i) {
f1665b21 1911 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1912 }
86cd2ea0
EH		 1913 env->fpip = xsave->legacy.fpip;
1914 env->fpdp = xsave->legacy.fpdp;
1915 env->mxcsr = xsave->legacy.mxcsr;
1916 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1917 sizeof env->fpregs);
86cd2ea0
EH		 1918 env->xstate_bv = xsave->header.xstate_bv;
1919 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1920 sizeof env->bnd_regs);
86cd2ea0
EH		 1921 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1922 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1923 sizeof env->opmask_regs);
bee81887 1924
86cd2ea0
EH		 1925 for (i = 0; i < CPU_NB_REGS; i++) {
1926 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1927 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1928 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1929 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1930 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1931 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1932 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1933 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1934 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1935 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1936 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1937 }
1938
9aecd6f8 1939#ifdef TARGET_X86_64
86cd2ea0 1940 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1941 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1942 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1943#endif
f1665b21 1944 return 0;
f1665b21
SY		 1945}
1946
1bc22652 1947static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1948{
1bc22652 1949 CPUX86State *env = &cpu->env;
f1665b21
SY		 1950 int i, ret;
1951 struct kvm_xcrs xcrs;
1952
28143b40 1953 if (!has_xcrs) {
f1665b21 1954 return 0;
b9bec74b 1955 }
f1665b21 1956
1bc22652 1957 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1958 if (ret < 0) {
f1665b21 1959 return ret;
b9bec74b 1960 }
f1665b21 1961
b9bec74b 1962 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1963 /* Only support xcr0 now */
0fd53fec
PB		 1964 if (xcrs.xcrs[i].xcr == 0) {
1965 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1966 break;
1967 }
b9bec74b 1968 }
f1665b21 1969 return 0;
f1665b21
SY		 1970}
1971
1bc22652 1972static int kvm_get_sregs(X86CPU *cpu)
05330448 1973{
1bc22652 1974 CPUX86State *env = &cpu->env;
05330448
AL		 1975 struct kvm_sregs sregs;
1976 uint32_t hflags;
0e607a80 1977 int bit, i, ret;
05330448 1978
1bc22652 1979 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1980 if (ret < 0) {
05330448 1981 return ret;
b9bec74b 1982 }
05330448 1983
0e607a80
JK		 1984 /* There can only be one pending IRQ set in the bitmap at a time, so try
1985 to find it and save its number instead (-1 for none). */
1986 env->interrupt_injected = -1;
1987 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1988 if (sregs.interrupt_bitmap[i]) {
1989 bit = ctz64(sregs.interrupt_bitmap[i]);
1990 env->interrupt_injected = i * 64 + bit;
1991 break;
1992 }
1993 }
05330448
AL		 1994
1995 get_seg(&env->segs[R_CS], &sregs.cs);
1996 get_seg(&env->segs[R_DS], &sregs.ds);
1997 get_seg(&env->segs[R_ES], &sregs.es);
1998 get_seg(&env->segs[R_FS], &sregs.fs);
1999 get_seg(&env->segs[R_GS], &sregs.gs);
2000 get_seg(&env->segs[R_SS], &sregs.ss);
2001
2002 get_seg(&env->tr, &sregs.tr);
2003 get_seg(&env->ldt, &sregs.ldt);
2004
2005 env->idt.limit = sregs.idt.limit;
2006 env->idt.base = sregs.idt.base;
2007 env->gdt.limit = sregs.gdt.limit;
2008 env->gdt.base = sregs.gdt.base;
2009
2010 env->cr[0] = sregs.cr0;
2011 env->cr[2] = sregs.cr2;
2012 env->cr[3] = sregs.cr3;
2013 env->cr[4] = sregs.cr4;
2014
05330448 2015 env->efer = sregs.efer;
cce47516
JK		 2016
2017 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 2018
b9bec74b
JK		 2019#define HFLAG_COPY_MASK \
2020 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
2021 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
2022 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
2023 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 2024
19dc85db
RH		 2025 hflags = env->hflags & HFLAG_COPY_MASK;
2026 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 2027 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2028 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 2029 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 2030 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 2031
2032 if (env->cr[4] & CR4_OSFXSR_MASK) {
2033 hflags |= HF_OSFXSR_MASK;
2034 }
05330448
AL		 2035
2036 if (env->efer & MSR_EFER_LMA) {
2037 hflags |= HF_LMA_MASK;
2038 }
2039
2040 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2041 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2042 } else {
2043 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 2044 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 2045 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 2046 (DESC_B_SHIFT - HF_SS32_SHIFT);
2047 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2048 !(hflags & HF_CS32_MASK)) {
2049 hflags |= HF_ADDSEG_MASK;
2050 } else {
2051 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2052 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2053 }
05330448 2054 }
19dc85db 2055 env->hflags = hflags;
05330448
AL		 2056
2057 return 0;
2058}
2059
1bc22652 2060static int kvm_get_msrs(X86CPU *cpu)
05330448 2061{
1bc22652 2062 CPUX86State *env = &cpu->env;
d71b62a1 2063 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2064 int ret, i;
fcc35e7c 2065 uint64_t mtrr_top_bits;
05330448 2066
d71b62a1
EH		 2067 kvm_msr_buf_reset(cpu);
2068
9c600a84
EH		 2069 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2070 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2071 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2072 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2073 if (has_msr_star) {
9c600a84 2074 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2075 }
c3a3a7d3 2076 if (has_msr_hsave_pa) {
9c600a84 2077 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2078 }
c9b8f6b6 2079 if (has_msr_tsc_aux) {
9c600a84 2080 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2081 }
f28558d3 2082 if (has_msr_tsc_adjust) {
9c600a84 2083 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2084 }
aa82ba54 2085 if (has_msr_tsc_deadline) {
9c600a84 2086 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2087 }
21e87c46 2088 if (has_msr_misc_enable) {
9c600a84 2089 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2090 }
fc12d72e 2091 if (has_msr_smbase) {
9c600a84 2092 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2093 }
df67696e 2094 if (has_msr_feature_control) {
9c600a84 2095 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2096 }
79e9ebeb 2097 if (has_msr_bndcfgs) {
9c600a84 2098 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2099 }
18cd2c17 2100 if (has_msr_xss) {
9c600a84 2101 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2102 }
2103
b8cc45d6
GC		 2104
2105 if (!env->tsc_valid) {
9c600a84 2106 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2107 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2108 }
2109
05330448 2110#ifdef TARGET_X86_64
25d2e361 2111 if (lm_capable_kernel) {
9c600a84
EH		 2112 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2113 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2114 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2115 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2116 }
05330448 2117#endif
9c600a84
EH		 2118 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2119 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2120 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2121 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2122 }
55c911a5 2123 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2124 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2125 }
55c911a5 2126 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2127 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2128 }
0d894367 2129 if (has_msr_architectural_pmu) {
9c600a84
EH		 2130 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2131 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2132 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2133 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2134 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2135 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2136 }
2137 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2138 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2139 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2140 }
2141 }
1a03675d 2142
57780495 2143 if (env->mcg_cap) {
9c600a84
EH		 2144 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2145 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2146 if (has_msr_mcg_ext_ctl) {
2147 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2148 }
b9bec74b 2149 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2150 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2151 }
57780495 2152 }
57780495 2153
1c90ef26 2154 if (has_msr_hv_hypercall) {
9c600a84
EH		 2155 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2156 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2157 }
2d5aa872 2158 if (cpu->hyperv_vapic) {
9c600a84 2159 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2160 }
3ddcd2ed 2161 if (cpu->hyperv_time) {
9c600a84 2162 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2163 }
f2a53c9e
AS		 2164 if (has_msr_hv_crash) {
2165 int j;
2166
2167 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2168 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2169 }
2170 }
46eb8f98 2171 if (has_msr_hv_runtime) {
9c600a84 2172 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2173 }
866eea9a
AS		 2174 if (cpu->hyperv_synic) {
2175 uint32_t msr;
2176
9c600a84
EH		 2177 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2178 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2179 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2180 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2181 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2182 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2183 }
2184 }
ff99aa64
AS		 2185 if (has_msr_hv_stimer) {
2186 uint32_t msr;
2187
2188 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2189 msr++) {
9c600a84 2190 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2191 }
2192 }
1eabfce6 2193 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2194 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2195 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2196 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2197 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2198 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2199 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2200 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2201 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2202 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2203 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2204 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2205 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2206 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2207 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2208 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2209 }
2210 }
5ef68987 2211
d71b62a1 2212 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2213 if (ret < 0) {
05330448 2214 return ret;
b9bec74b 2215 }
05330448 2216
9c600a84 2217 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2218 /*
2219 * MTRR masks: Each mask consists of 5 parts
2220 * a 10..0: must be zero
2221 * b 11 : valid bit
2222 * c n-1.12: actual mask bits
2223 * d 51..n: reserved must be zero
2224 * e 63.52: reserved must be zero
2225 *
2226 * 'n' is the number of physical bits supported by the CPU and is
2227 * apparently always <= 52. We know our 'n' but don't know what
2228 * the destinations 'n' is; it might be smaller, in which case
2229 * it masks (c) on loading. It might be larger, in which case
2230 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2231 * we're migrating to.
2232 */
2233
2234 if (cpu->fill_mtrr_mask) {
2235 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2236 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2237 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2238 } else {
2239 mtrr_top_bits = 0;
2240 }
2241
05330448 2242 for (i = 0; i < ret; i++) {
0d894367
PB		 2243 uint32_t index = msrs[i].index;
2244 switch (index) {
05330448
AL		 2245 case MSR_IA32_SYSENTER_CS:
2246 env->sysenter_cs = msrs[i].data;
2247 break;
2248 case MSR_IA32_SYSENTER_ESP:
2249 env->sysenter_esp = msrs[i].data;
2250 break;
2251 case MSR_IA32_SYSENTER_EIP:
2252 env->sysenter_eip = msrs[i].data;
2253 break;
0c03266a
JK		 2254 case MSR_PAT:
2255 env->pat = msrs[i].data;
2256 break;
05330448
AL		 2257 case MSR_STAR:
2258 env->star = msrs[i].data;
2259 break;
2260#ifdef TARGET_X86_64
2261 case MSR_CSTAR:
2262 env->cstar = msrs[i].data;
2263 break;
2264 case MSR_KERNELGSBASE:
2265 env->kernelgsbase = msrs[i].data;
2266 break;
2267 case MSR_FMASK:
2268 env->fmask = msrs[i].data;
2269 break;
2270 case MSR_LSTAR:
2271 env->lstar = msrs[i].data;
2272 break;
2273#endif
2274 case MSR_IA32_TSC:
2275 env->tsc = msrs[i].data;
2276 break;
c9b8f6b6
AS		 2277 case MSR_TSC_AUX:
2278 env->tsc_aux = msrs[i].data;
2279 break;
f28558d3
WA		 2280 case MSR_TSC_ADJUST:
2281 env->tsc_adjust = msrs[i].data;
2282 break;
aa82ba54
LJ		 2283 case MSR_IA32_TSCDEADLINE:
2284 env->tsc_deadline = msrs[i].data;
2285 break;
aa851e36
MT		 2286 case MSR_VM_HSAVE_PA:
2287 env->vm_hsave = msrs[i].data;
2288 break;
1a03675d
GC		 2289 case MSR_KVM_SYSTEM_TIME:
2290 env->system_time_msr = msrs[i].data;
2291 break;
2292 case MSR_KVM_WALL_CLOCK:
2293 env->wall_clock_msr = msrs[i].data;
2294 break;
57780495
MT		 2295 case MSR_MCG_STATUS:
2296 env->mcg_status = msrs[i].data;
2297 break;
2298 case MSR_MCG_CTL:
2299 env->mcg_ctl = msrs[i].data;
2300 break;
87f8b626
AR		 2301 case MSR_MCG_EXT_CTL:
2302 env->mcg_ext_ctl = msrs[i].data;
2303 break;
21e87c46
AK		 2304 case MSR_IA32_MISC_ENABLE:
2305 env->msr_ia32_misc_enable = msrs[i].data;
2306 break;
fc12d72e
PB		 2307 case MSR_IA32_SMBASE:
2308 env->smbase = msrs[i].data;
2309 break;
0779caeb
ACL		 2310 case MSR_IA32_FEATURE_CONTROL:
2311 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2312 break;
79e9ebeb
LJ		 2313 case MSR_IA32_BNDCFGS:
2314 env->msr_bndcfgs = msrs[i].data;
2315 break;
18cd2c17
WL		 2316 case MSR_IA32_XSS:
2317 env->xss = msrs[i].data;
2318 break;
57780495 2319 default:
57780495
MT		 2320 if (msrs[i].index >= MSR_MC0_CTL &&
2321 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2322 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2323 }
d8da8574 2324 break;
f6584ee2
GN		 2325 case MSR_KVM_ASYNC_PF_EN:
2326 env->async_pf_en_msr = msrs[i].data;
2327 break;
bc9a839d
MT		 2328 case MSR_KVM_PV_EOI_EN:
2329 env->pv_eoi_en_msr = msrs[i].data;
2330 break;
917367aa
MT		 2331 case MSR_KVM_STEAL_TIME:
2332 env->steal_time_msr = msrs[i].data;
2333 break;
0d894367
PB		 2334 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2335 env->msr_fixed_ctr_ctrl = msrs[i].data;
2336 break;
2337 case MSR_CORE_PERF_GLOBAL_CTRL:
2338 env->msr_global_ctrl = msrs[i].data;
2339 break;
2340 case MSR_CORE_PERF_GLOBAL_STATUS:
2341 env->msr_global_status = msrs[i].data;
2342 break;
2343 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2344 env->msr_global_ovf_ctrl = msrs[i].data;
2345 break;
2346 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2347 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2348 break;
2349 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2350 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2351 break;
2352 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2353 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2354 break;
1c90ef26
VR		 2355 case HV_X64_MSR_HYPERCALL:
2356 env->msr_hv_hypercall = msrs[i].data;
2357 break;
2358 case HV_X64_MSR_GUEST_OS_ID:
2359 env->msr_hv_guest_os_id = msrs[i].data;
2360 break;
5ef68987
VR		 2361 case HV_X64_MSR_APIC_ASSIST_PAGE:
2362 env->msr_hv_vapic = msrs[i].data;
2363 break;
48a5f3bc
VR		 2364 case HV_X64_MSR_REFERENCE_TSC:
2365 env->msr_hv_tsc = msrs[i].data;
2366 break;
f2a53c9e
AS		 2367 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2368 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2369 break;
46eb8f98
AS		 2370 case HV_X64_MSR_VP_RUNTIME:
2371 env->msr_hv_runtime = msrs[i].data;
2372 break;
866eea9a
AS		 2373 case HV_X64_MSR_SCONTROL:
2374 env->msr_hv_synic_control = msrs[i].data;
2375 break;
2376 case HV_X64_MSR_SVERSION:
2377 env->msr_hv_synic_version = msrs[i].data;
2378 break;
2379 case HV_X64_MSR_SIEFP:
2380 env->msr_hv_synic_evt_page = msrs[i].data;
2381 break;
2382 case HV_X64_MSR_SIMP:
2383 env->msr_hv_synic_msg_page = msrs[i].data;
2384 break;
2385 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2386 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2387 break;
2388 case HV_X64_MSR_STIMER0_CONFIG:
2389 case HV_X64_MSR_STIMER1_CONFIG:
2390 case HV_X64_MSR_STIMER2_CONFIG:
2391 case HV_X64_MSR_STIMER3_CONFIG:
2392 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2393 msrs[i].data;
2394 break;
2395 case HV_X64_MSR_STIMER0_COUNT:
2396 case HV_X64_MSR_STIMER1_COUNT:
2397 case HV_X64_MSR_STIMER2_COUNT:
2398 case HV_X64_MSR_STIMER3_COUNT:
2399 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2400 msrs[i].data;
866eea9a 2401 break;
d1ae67f6
AW		 2402 case MSR_MTRRdefType:
2403 env->mtrr_deftype = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix64K_00000:
2406 env->mtrr_fixed[0] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix16K_80000:
2409 env->mtrr_fixed[1] = msrs[i].data;
2410 break;
2411 case MSR_MTRRfix16K_A0000:
2412 env->mtrr_fixed[2] = msrs[i].data;
2413 break;
2414 case MSR_MTRRfix4K_C0000:
2415 env->mtrr_fixed[3] = msrs[i].data;
2416 break;
2417 case MSR_MTRRfix4K_C8000:
2418 env->mtrr_fixed[4] = msrs[i].data;
2419 break;
2420 case MSR_MTRRfix4K_D0000:
2421 env->mtrr_fixed[5] = msrs[i].data;
2422 break;
2423 case MSR_MTRRfix4K_D8000:
2424 env->mtrr_fixed[6] = msrs[i].data;
2425 break;
2426 case MSR_MTRRfix4K_E0000:
2427 env->mtrr_fixed[7] = msrs[i].data;
2428 break;
2429 case MSR_MTRRfix4K_E8000:
2430 env->mtrr_fixed[8] = msrs[i].data;
2431 break;
2432 case MSR_MTRRfix4K_F0000:
2433 env->mtrr_fixed[9] = msrs[i].data;
2434 break;
2435 case MSR_MTRRfix4K_F8000:
2436 env->mtrr_fixed[10] = msrs[i].data;
2437 break;
2438 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2439 if (index & 1) {
fcc35e7c
DDAG		 2440 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2441 mtrr_top_bits;
d1ae67f6
AW		 2442 } else {
2443 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2444 }
2445 break;
05330448
AL		 2446 }
2447 }
2448
2449 return 0;
2450}
2451
1bc22652 2452static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2453{
1bc22652 2454 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2455
1bc22652 2456 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2457}
2458
23d02d9b 2459static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2460{
259186a7 2461 CPUState *cs = CPU(cpu);
23d02d9b 2462 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2463 struct kvm_mp_state mp_state;
2464 int ret;
2465
259186a7 2466 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2467 if (ret < 0) {
2468 return ret;
2469 }
2470 env->mp_state = mp_state.mp_state;
c14750e8 2471 if (kvm_irqchip_in_kernel()) {
259186a7 2472 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2473 }
9bdbe550
HB		 2474 return 0;
2475}
2476
1bc22652 2477static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2478{
02e51483 2479 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2480 struct kvm_lapic_state kapic;
2481 int ret;
2482
3d4b2649 2483 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2484 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2485 if (ret < 0) {
2486 return ret;
2487 }
2488
2489 kvm_get_apic_state(apic, &kapic);
2490 }
2491 return 0;
2492}
2493
1bc22652 2494static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2495{
fc12d72e 2496 CPUState *cs = CPU(cpu);
1bc22652 2497 CPUX86State *env = &cpu->env;
076796f8 2498 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2499
2500 if (!kvm_has_vcpu_events()) {
2501 return 0;
2502 }
2503
31827373
JK		 2504 events.exception.injected = (env->exception_injected >= 0);
2505 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2506 events.exception.has_error_code = env->has_error_code;
2507 events.exception.error_code = env->error_code;
7e680753 2508 events.exception.pad = 0;
a0fb002c
JK		 2509
2510 events.interrupt.injected = (env->interrupt_injected >= 0);
2511 events.interrupt.nr = env->interrupt_injected;
2512 events.interrupt.soft = env->soft_interrupt;
2513
2514 events.nmi.injected = env->nmi_injected;
2515 events.nmi.pending = env->nmi_pending;
2516 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2517 events.nmi.pad = 0;
a0fb002c
JK		 2518
2519 events.sipi_vector = env->sipi_vector;
68c6efe0 2520 events.flags = 0;
a0fb002c 2521
fc12d72e
PB		 2522 if (has_msr_smbase) {
2523 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2524 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2525 if (kvm_irqchip_in_kernel()) {
2526 /* As soon as these are moved to the kernel, remove them
2527 * from cs->interrupt_request.
2528 */
2529 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2530 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2531 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2532 } else {
2533 /* Keep these in cs->interrupt_request. */
2534 events.smi.pending = 0;
2535 events.smi.latched_init = 0;
2536 }
2537 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2538 }
2539
ea643051
JK		 2540 if (level >= KVM_PUT_RESET_STATE) {
2541 events.flags |=
2542 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2543 }
aee028b9 2544
1bc22652 2545 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2546}
2547
1bc22652 2548static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2549{
1bc22652 2550 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2551 struct kvm_vcpu_events events;
2552 int ret;
2553
2554 if (!kvm_has_vcpu_events()) {
2555 return 0;
2556 }
2557
fc12d72e 2558 memset(&events, 0, sizeof(events));
1bc22652 2559 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2560 if (ret < 0) {
2561 return ret;
2562 }
31827373 2563 env->exception_injected =
a0fb002c
JK		 2564 events.exception.injected ? events.exception.nr : -1;
2565 env->has_error_code = events.exception.has_error_code;
2566 env->error_code = events.exception.error_code;
2567
2568 env->interrupt_injected =
2569 events.interrupt.injected ? events.interrupt.nr : -1;
2570 env->soft_interrupt = events.interrupt.soft;
2571
2572 env->nmi_injected = events.nmi.injected;
2573 env->nmi_pending = events.nmi.pending;
2574 if (events.nmi.masked) {
2575 env->hflags2 |= HF2_NMI_MASK;
2576 } else {
2577 env->hflags2 &= ~HF2_NMI_MASK;
2578 }
2579
fc12d72e
PB		 2580 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2581 if (events.smi.smm) {
2582 env->hflags |= HF_SMM_MASK;
2583 } else {
2584 env->hflags &= ~HF_SMM_MASK;
2585 }
2586 if (events.smi.pending) {
2587 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2588 } else {
2589 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2590 }
2591 if (events.smi.smm_inside_nmi) {
2592 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2593 } else {
2594 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2595 }
2596 if (events.smi.latched_init) {
2597 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2598 } else {
2599 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2600 }
2601 }
2602
a0fb002c 2603 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2604
2605 return 0;
2606}
2607
1bc22652 2608static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2609{
ed2803da 2610 CPUState *cs = CPU(cpu);
1bc22652 2611 CPUX86State *env = &cpu->env;
b0b1d690 2612 int ret = 0;
b0b1d690
JK		 2613 unsigned long reinject_trap = 0;
2614
2615 if (!kvm_has_vcpu_events()) {
2616 if (env->exception_injected == 1) {
2617 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2618 } else if (env->exception_injected == 3) {
2619 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2620 }
2621 env->exception_injected = -1;
2622 }
2623
2624 /*
2625 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2626 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2627 * by updating the debug state once again if single-stepping is on.
2628 * Another reason to call kvm_update_guest_debug here is a pending debug
2629 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2630 * reinject them via SET_GUEST_DEBUG.
2631 */
2632 if (reinject_trap ||
ed2803da 2633 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2634 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2635 }
b0b1d690
JK		 2636 return ret;
2637}
2638
1bc22652 2639static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2640{
1bc22652 2641 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2642 struct kvm_debugregs dbgregs;
2643 int i;
2644
2645 if (!kvm_has_debugregs()) {
2646 return 0;
2647 }
2648
2649 for (i = 0; i < 4; i++) {
2650 dbgregs.db[i] = env->dr[i];
2651 }
2652 dbgregs.dr6 = env->dr[6];
2653 dbgregs.dr7 = env->dr[7];
2654 dbgregs.flags = 0;
2655
1bc22652 2656 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2657}
2658
1bc22652 2659static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2660{
1bc22652 2661 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2662 struct kvm_debugregs dbgregs;
2663 int i, ret;
2664
2665 if (!kvm_has_debugregs()) {
2666 return 0;
2667 }
2668
1bc22652 2669 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2670 if (ret < 0) {
b9bec74b 2671 return ret;
ff44f1a3
JK		 2672 }
2673 for (i = 0; i < 4; i++) {
2674 env->dr[i] = dbgregs.db[i];
2675 }
2676 env->dr[4] = env->dr[6] = dbgregs.dr6;
2677 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2678
2679 return 0;
2680}
2681
20d695a9 2682int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2683{
20d695a9 2684 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2685 int ret;
2686
2fa45344 2687 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2688
48e1a45c 2689 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2690 ret = kvm_put_msr_feature_control(x86_cpu);
2691 if (ret < 0) {
2692 return ret;
2693 }
2694 }
2695
36f96c4b
HZ		 2696 if (level == KVM_PUT_FULL_STATE) {
2697 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2698 * because TSC frequency mismatch shouldn't abort migration,
2699 * unless the user explicitly asked for a more strict TSC
2700 * setting (e.g. using an explicit "tsc-freq" option).
2701 */
2702 kvm_arch_set_tsc_khz(cpu);
2703 }
2704
1bc22652 2705 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2706 if (ret < 0) {
05330448 2707 return ret;
b9bec74b 2708 }
1bc22652 2709 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2710 if (ret < 0) {
f1665b21 2711 return ret;
b9bec74b 2712 }
1bc22652 2713 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2714 if (ret < 0) {
05330448 2715 return ret;
b9bec74b 2716 }
1bc22652 2717 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2718 if (ret < 0) {
05330448 2719 return ret;
b9bec74b 2720 }
ab443475 2721 /* must be before kvm_put_msrs */
1bc22652 2722 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2723 if (ret < 0) {
2724 return ret;
2725 }
1bc22652 2726 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2727 if (ret < 0) {
05330448 2728 return ret;
b9bec74b 2729 }
ea643051 2730 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2731 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2732 if (ret < 0) {
680c1c6f
JK		 2733 return ret;
2734 }
ea643051 2735 }
7477cd38
MT		 2736
2737 ret = kvm_put_tscdeadline_msr(x86_cpu);
2738 if (ret < 0) {
2739 return ret;
2740 }
2741
1bc22652 2742 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2743 if (ret < 0) {
a0fb002c 2744 return ret;
b9bec74b 2745 }
1bc22652 2746 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2747 if (ret < 0) {
b0b1d690 2748 return ret;
b9bec74b 2749 }
b0b1d690 2750 /* must be last */
1bc22652 2751 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2752 if (ret < 0) {
ff44f1a3 2753 return ret;
b9bec74b 2754 }
05330448
AL		 2755 return 0;
2756}
2757
20d695a9 2758int kvm_arch_get_registers(CPUState *cs)
05330448 2759{
20d695a9 2760 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2761 int ret;
2762
20d695a9 2763 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2764
1bc22652 2765 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2766 if (ret < 0) {
f4f1110e 2767 goto out;
b9bec74b 2768 }
1bc22652 2769 ret = kvm_get_xsave(cpu);
b9bec74b 2770 if (ret < 0) {
f4f1110e 2771 goto out;
b9bec74b 2772 }
1bc22652 2773 ret = kvm_get_xcrs(cpu);
b9bec74b 2774 if (ret < 0) {
f4f1110e 2775 goto out;
b9bec74b 2776 }
1bc22652 2777 ret = kvm_get_sregs(cpu);
b9bec74b 2778 if (ret < 0) {
f4f1110e 2779 goto out;
b9bec74b 2780 }
1bc22652 2781 ret = kvm_get_msrs(cpu);
b9bec74b 2782 if (ret < 0) {
f4f1110e 2783 goto out;
b9bec74b 2784 }
23d02d9b 2785 ret = kvm_get_mp_state(cpu);
b9bec74b 2786 if (ret < 0) {
f4f1110e 2787 goto out;
b9bec74b 2788 }
1bc22652 2789 ret = kvm_get_apic(cpu);
680c1c6f 2790 if (ret < 0) {
f4f1110e 2791 goto out;
680c1c6f 2792 }
1bc22652 2793 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2794 if (ret < 0) {
f4f1110e 2795 goto out;
b9bec74b 2796 }
1bc22652 2797 ret = kvm_get_debugregs(cpu);
b9bec74b 2798 if (ret < 0) {
f4f1110e 2799 goto out;
b9bec74b 2800 }
f4f1110e
RH		 2801 ret = 0;
2802 out:
2803 cpu_sync_bndcs_hflags(&cpu->env);
2804 return ret;
05330448
AL		 2805}
2806
20d695a9 2807void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2808{
20d695a9
AF		 2809 X86CPU *x86_cpu = X86_CPU(cpu);
2810 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2811 int ret;
2812
276ce815 2813 /* Inject NMI */
fc12d72e
PB		 2814 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2815 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2816 qemu_mutex_lock_iothread();
2817 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2818 qemu_mutex_unlock_iothread();
2819 DPRINTF("injected NMI\n");
2820 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2821 if (ret < 0) {
2822 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2823 strerror(-ret));
2824 }
2825 }
2826 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2827 qemu_mutex_lock_iothread();
2828 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2829 qemu_mutex_unlock_iothread();
2830 DPRINTF("injected SMI\n");
2831 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2832 if (ret < 0) {
2833 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2834 strerror(-ret));
2835 }
ce377af3 2836 }
276ce815
LJ		 2837 }
2838
15eafc2e 2839 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2840 qemu_mutex_lock_iothread();
2841 }
2842
e0723c45
PB		 2843 /* Force the VCPU out of its inner loop to process any INIT requests
2844 * or (for userspace APIC, but it is cheap to combine the checks here)
2845 * pending TPR access reports.
2846 */
2847 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2848 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2849 !(env->hflags & HF_SMM_MASK)) {
2850 cpu->exit_request = 1;
2851 }
2852 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2853 cpu->exit_request = 1;
2854 }
e0723c45 2855 }
05330448 2856
15eafc2e 2857 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2858 /* Try to inject an interrupt if the guest can accept it */
2859 if (run->ready_for_interrupt_injection &&
259186a7 2860 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2861 (env->eflags & IF_MASK)) {
2862 int irq;
2863
259186a7 2864 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2865 irq = cpu_get_pic_interrupt(env);
2866 if (irq >= 0) {
2867 struct kvm_interrupt intr;
2868
2869 intr.irq = irq;
db1669bc 2870 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2871 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2872 if (ret < 0) {
2873 fprintf(stderr,
2874 "KVM: injection failed, interrupt lost (%s)\n",
2875 strerror(-ret));
2876 }
db1669bc
JK		 2877 }
2878 }
05330448 2879
db1669bc
JK		 2880 /* If we have an interrupt but the guest is not ready to receive an
2881 * interrupt, request an interrupt window exit. This will
2882 * cause a return to userspace as soon as the guest is ready to
2883 * receive interrupts. */
259186a7 2884 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2885 run->request_interrupt_window = 1;
2886 } else {
2887 run->request_interrupt_window = 0;
2888 }
2889
2890 DPRINTF("setting tpr\n");
02e51483 2891 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2892
2893 qemu_mutex_unlock_iothread();
db1669bc 2894 }
05330448
AL		 2895}
2896
4c663752 2897MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2898{
20d695a9
AF		 2899 X86CPU *x86_cpu = X86_CPU(cpu);
2900 CPUX86State *env = &x86_cpu->env;
2901
fc12d72e
PB		 2902 if (run->flags & KVM_RUN_X86_SMM) {
2903 env->hflags |= HF_SMM_MASK;
2904 } else {
f5c052b9 2905 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2906 }
b9bec74b 2907 if (run->if_flag) {
05330448 2908 env->eflags |= IF_MASK;
b9bec74b 2909 } else {
05330448 2910 env->eflags &= ~IF_MASK;
b9bec74b 2911 }
4b8523ee
JK		 2912
2913 /* We need to protect the apic state against concurrent accesses from
2914 * different threads in case the userspace irqchip is used. */
2915 if (!kvm_irqchip_in_kernel()) {
2916 qemu_mutex_lock_iothread();
2917 }
02e51483
CF		 2918 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2919 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2920 if (!kvm_irqchip_in_kernel()) {
2921 qemu_mutex_unlock_iothread();
2922 }
f794aa4a 2923 return cpu_get_mem_attrs(env);
05330448
AL		 2924}
2925
20d695a9 2926int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2927{
20d695a9
AF		 2928 X86CPU *cpu = X86_CPU(cs);
2929 CPUX86State *env = &cpu->env;
232fc23b 2930
259186a7 2931 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2932 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2933 assert(env->mcg_cap);
2934
259186a7 2935 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2936
dd1750d7 2937 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2938
2939 if (env->exception_injected == EXCP08_DBLE) {
2940 /* this means triple fault */
2941 qemu_system_reset_request();
fcd7d003 2942 cs->exit_request = 1;
ab443475
JK		 2943 return 0;
2944 }
2945 env->exception_injected = EXCP12_MCHK;
2946 env->has_error_code = 0;
2947
259186a7 2948 cs->halted = 0;
ab443475
JK		 2949 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2950 env->mp_state = KVM_MP_STATE_RUNNABLE;
2951 }
2952 }
2953
fc12d72e
PB		 2954 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2955 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2956 kvm_cpu_synchronize_state(cs);
2957 do_cpu_init(cpu);
2958 }
2959
db1669bc
JK		 2960 if (kvm_irqchip_in_kernel()) {
2961 return 0;
2962 }
2963
259186a7
AF		 2964 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2965 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2966 apic_poll_irq(cpu->apic_state);
5d62c43a 2967 }
259186a7 2968 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2969 (env->eflags & IF_MASK)) ||
259186a7
AF		 2970 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2971 cs->halted = 0;
6792a57b 2972 }
259186a7 2973 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2974 kvm_cpu_synchronize_state(cs);
232fc23b 2975 do_cpu_sipi(cpu);
0af691d7 2976 }
259186a7
AF		 2977 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2978 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2979 kvm_cpu_synchronize_state(cs);
02e51483 2980 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2981 env->tpr_access_type);
2982 }
0af691d7 2983
259186a7 2984 return cs->halted;
0af691d7
MT		 2985}
2986
839b5630 2987static int kvm_handle_halt(X86CPU *cpu)
05330448 2988{
259186a7 2989 CPUState *cs = CPU(cpu);
839b5630
AF		 2990 CPUX86State *env = &cpu->env;
2991
259186a7 2992 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2993 (env->eflags & IF_MASK)) &&
259186a7
AF		 2994 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2995 cs->halted = 1;
bb4ea393 2996 return EXCP_HLT;
05330448
AL		 2997 }
2998
bb4ea393 2999 return 0;
05330448
AL		 3000}
3001
f7575c96 3002static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3003{
f7575c96
AF		 3004 CPUState *cs = CPU(cpu);
3005 struct kvm_run *run = cs->kvm_run;
d362e757 3006
02e51483 3007 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3008 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3009 : TPR_ACCESS_READ);
3010 return 1;
3011}
3012
f17ec444 3013int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3014{
38972938 3015 static const uint8_t int3 = 0xcc;
64bf3f4e 3016
f17ec444
AF		 3017 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3018 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3019 return -EINVAL;
b9bec74b 3020 }
e22a25c9
AL		 3021 return 0;
3022}
3023
f17ec444 3024int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3025{
3026 uint8_t int3;
3027
f17ec444
AF		 3028 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3029 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3030 return -EINVAL;
b9bec74b 3031 }
e22a25c9
AL		 3032 return 0;
3033}
3034
3035static struct {
3036 target_ulong addr;
3037 int len;
3038 int type;
3039} hw_breakpoint[4];
3040
3041static int nb_hw_breakpoint;
3042
3043static int find_hw_breakpoint(target_ulong addr, int len, int type)
3044{
3045 int n;
3046
b9bec74b 3047 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3048 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3049 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3050 return n;
b9bec74b
JK		 3051 }
3052 }
e22a25c9
AL		 3053 return -1;
3054}
3055
3056int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3057 target_ulong len, int type)
3058{
3059 switch (type) {
3060 case GDB_BREAKPOINT_HW:
3061 len = 1;
3062 break;
3063 case GDB_WATCHPOINT_WRITE:
3064 case GDB_WATCHPOINT_ACCESS:
3065 switch (len) {
3066 case 1:
3067 break;
3068 case 2:
3069 case 4:
3070 case 8:
b9bec74b 3071 if (addr & (len - 1)) {
e22a25c9 3072 return -EINVAL;
b9bec74b 3073 }
e22a25c9
AL		 3074 break;
3075 default:
3076 return -EINVAL;
3077 }
3078 break;
3079 default:
3080 return -ENOSYS;
3081 }
3082
b9bec74b 3083 if (nb_hw_breakpoint == 4) {
e22a25c9 3084 return -ENOBUFS;
b9bec74b
JK		 3085 }
3086 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3087 return -EEXIST;
b9bec74b 3088 }
e22a25c9
AL		 3089 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3090 hw_breakpoint[nb_hw_breakpoint].len = len;
3091 hw_breakpoint[nb_hw_breakpoint].type = type;
3092 nb_hw_breakpoint++;
3093
3094 return 0;
3095}
3096
3097int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3098 target_ulong len, int type)
3099{
3100 int n;
3101
3102 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3103 if (n < 0) {
e22a25c9 3104 return -ENOENT;
b9bec74b 3105 }
e22a25c9
AL		 3106 nb_hw_breakpoint--;
3107 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3108
3109 return 0;
3110}
3111
3112void kvm_arch_remove_all_hw_breakpoints(void)
3113{
3114 nb_hw_breakpoint = 0;
3115}
3116
3117static CPUWatchpoint hw_watchpoint;
3118
a60f24b5 3119static int kvm_handle_debug(X86CPU *cpu,
48405526 3120 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3121{
ed2803da 3122 CPUState *cs = CPU(cpu);
a60f24b5 3123 CPUX86State *env = &cpu->env;
f2574737 3124 int ret = 0;
e22a25c9
AL		 3125 int n;
3126
3127 if (arch_info->exception == 1) {
3128 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3129 if (cs->singlestep_enabled) {
f2574737 3130 ret = EXCP_DEBUG;
b9bec74b 3131 }
e22a25c9 3132 } else {
b9bec74b
JK		 3133 for (n = 0; n < 4; n++) {
3134 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3135 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3136 case 0x0:
f2574737 3137 ret = EXCP_DEBUG;
e22a25c9
AL		 3138 break;
3139 case 0x1:
f2574737 3140 ret = EXCP_DEBUG;
ff4700b0 3141 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3142 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3143 hw_watchpoint.flags = BP_MEM_WRITE;
3144 break;
3145 case 0x3:
f2574737 3146 ret = EXCP_DEBUG;
ff4700b0 3147 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3148 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3149 hw_watchpoint.flags = BP_MEM_ACCESS;
3150 break;
3151 }
b9bec74b
JK		 3152 }
3153 }
e22a25c9 3154 }
ff4700b0 3155 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3156 ret = EXCP_DEBUG;
b9bec74b 3157 }
f2574737 3158 if (ret == 0) {
ff4700b0 3159 cpu_synchronize_state(cs);
48405526 3160 assert(env->exception_injected == -1);
b0b1d690 3161
f2574737 3162 /* pass to guest */
48405526
BS		 3163 env->exception_injected = arch_info->exception;
3164 env->has_error_code = 0;
b0b1d690 3165 }
e22a25c9 3166
f2574737 3167 return ret;
e22a25c9
AL		 3168}
3169
20d695a9 3170void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3171{
3172 const uint8_t type_code[] = {
3173 [GDB_BREAKPOINT_HW] = 0x0,
3174 [GDB_WATCHPOINT_WRITE] = 0x1,
3175 [GDB_WATCHPOINT_ACCESS] = 0x3
3176 };
3177 const uint8_t len_code[] = {
3178 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3179 };
3180 int n;
3181
a60f24b5 3182 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3183 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3184 }
e22a25c9
AL		 3185 if (nb_hw_breakpoint > 0) {
3186 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3187 dbg->arch.debugreg[7] = 0x0600;
3188 for (n = 0; n < nb_hw_breakpoint; n++) {
3189 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3190 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3191 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3192 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3193 }
3194 }
3195}
4513d923 3196
2a4dac83
JK		 3197static bool host_supports_vmx(void)
3198{
3199 uint32_t ecx, unused;
3200
3201 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3202 return ecx & CPUID_EXT_VMX;
3203}
3204
3205#define VMX_INVALID_GUEST_STATE 0x80000021
3206
20d695a9 3207int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3208{
20d695a9 3209 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3210 uint64_t code;
3211 int ret;
3212
3213 switch (run->exit_reason) {
3214 case KVM_EXIT_HLT:
3215 DPRINTF("handle_hlt\n");
4b8523ee 3216 qemu_mutex_lock_iothread();
839b5630 3217 ret = kvm_handle_halt(cpu);
4b8523ee 3218 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3219 break;
3220 case KVM_EXIT_SET_TPR:
3221 ret = 0;
3222 break;
d362e757 3223 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3224 qemu_mutex_lock_iothread();
f7575c96 3225 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3226 qemu_mutex_unlock_iothread();
d362e757 3227 break;
2a4dac83
JK		 3228 case KVM_EXIT_FAIL_ENTRY:
3229 code = run->fail_entry.hardware_entry_failure_reason;
3230 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3231 code);
3232 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3233 fprintf(stderr,
12619721 3234 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3235 "unrestricted mode\n"
3236 "support, the failure can be most likely due to the guest "
3237 "entering an invalid\n"
3238 "state for Intel VT. For example, the guest maybe running "
3239 "in big real mode\n"
3240 "which is not supported on less recent Intel processors."
3241 "\n\n");
3242 }
3243 ret = -1;
3244 break;
3245 case KVM_EXIT_EXCEPTION:
3246 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3247 run->ex.exception, run->ex.error_code);
3248 ret = -1;
3249 break;
f2574737
JK		 3250 case KVM_EXIT_DEBUG:
3251 DPRINTF("kvm_exit_debug\n");
4b8523ee 3252 qemu_mutex_lock_iothread();
a60f24b5 3253 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3254 qemu_mutex_unlock_iothread();
f2574737 3255 break;
50efe82c
AS		 3256 case KVM_EXIT_HYPERV:
3257 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3258 break;
15eafc2e
PB		 3259 case KVM_EXIT_IOAPIC_EOI:
3260 ioapic_eoi_broadcast(run->eoi.vector);
3261 ret = 0;
3262 break;
2a4dac83
JK		 3263 default:
3264 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3265 ret = -1;
3266 break;
3267 }
3268
3269 return ret;
3270}
3271
20d695a9 3272bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3273{
20d695a9
AF		 3274 X86CPU *cpu = X86_CPU(cs);
3275 CPUX86State *env = &cpu->env;
3276
dd1750d7 3277 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3278 return !(env->cr[0] & CR0_PE_MASK) ||
3279 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3280}
84b058d7
JK		 3281
3282void kvm_arch_init_irq_routing(KVMState *s)
3283{
3284 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3285 /* If kernel can't do irq routing, interrupt source
3286 * override 0->2 cannot be set up as required by HPET.
3287 * So we have to disable it.
3288 */
3289 no_hpet = 1;
3290 }
cc7e0ddf 3291 /* We know at this point that we're using the in-kernel
614e41bc 3292 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3293 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3294 */
614e41bc 3295 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3296 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3297
3298 if (kvm_irqchip_is_split()) {
3299 int i;
3300
3301 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3302 MSI routes for signaling interrupts to the local apics. */
3303 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3304 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3305 error_report("Could not enable split IRQ mode.");
3306 exit(1);
3307 }
3308 }
3309 }
3310}
3311
3312int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3313{
3314 int ret;
3315 if (machine_kernel_irqchip_split(ms)) {
3316 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3317 if (ret) {
df3c286c 3318 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3319 strerror(-ret));
3320 exit(1);
3321 } else {
3322 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3323 kvm_split_irqchip = true;
3324 return 1;
3325 }
3326 } else {
3327 return 0;
3328 }
84b058d7 3329}
b139bd30
JK		 3330
3331/* Classic KVM device assignment interface. Will remain x86 only. */
3332int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3333 uint32_t flags, uint32_t *dev_id)
3334{
3335 struct kvm_assigned_pci_dev dev_data = {
3336 .segnr = dev_addr->domain,
3337 .busnr = dev_addr->bus,
3338 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3339 .flags = flags,
3340 };
3341 int ret;
3342
3343 dev_data.assigned_dev_id =
3344 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3345
3346 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3347 if (ret < 0) {
3348 return ret;
3349 }
3350
3351 *dev_id = dev_data.assigned_dev_id;
3352
3353 return 0;
3354}
3355
3356int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3357{
3358 struct kvm_assigned_pci_dev dev_data = {
3359 .assigned_dev_id = dev_id,
3360 };
3361
3362 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3363}
3364
3365static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3366 uint32_t irq_type, uint32_t guest_irq)
3367{
3368 struct kvm_assigned_irq assigned_irq = {
3369 .assigned_dev_id = dev_id,
3370 .guest_irq = guest_irq,
3371 .flags = irq_type,
3372 };
3373
3374 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3375 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3376 } else {
3377 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3378 }
3379}
3380
3381int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3382 uint32_t guest_irq)
3383{
3384 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3385 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3386
3387 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3388}
3389
3390int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3391{
3392 struct kvm_assigned_pci_dev dev_data = {
3393 .assigned_dev_id = dev_id,
3394 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3395 };
3396
3397 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3398}
3399
3400static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3401 uint32_t type)
3402{
3403 struct kvm_assigned_irq assigned_irq = {
3404 .assigned_dev_id = dev_id,
3405 .flags = type,
3406 };
3407
3408 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3409}
3410
3411int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3412{
3413 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3414 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3415}
3416
3417int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3418{
3419 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3420 KVM_DEV_IRQ_GUEST_MSI, virq);
3421}
3422
3423int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3424{
3425 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3426 KVM_DEV_IRQ_HOST_MSI);
3427}
3428
3429bool kvm_device_msix_supported(KVMState *s)
3430{
3431 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3432 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3433 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3434}
3435
3436int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3437 uint32_t nr_vectors)
3438{
3439 struct kvm_assigned_msix_nr msix_nr = {
3440 .assigned_dev_id = dev_id,
3441 .entry_nr = nr_vectors,
3442 };
3443
3444 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3445}
3446
3447int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3448 int virq)
3449{
3450 struct kvm_assigned_msix_entry msix_entry = {
3451 .assigned_dev_id = dev_id,
3452 .gsi = virq,
3453 .entry = vector,
3454 };
3455
3456 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3457}
3458
3459int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3460{
3461 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3462 KVM_DEV_IRQ_GUEST_MSIX, 0);
3463}
3464
3465int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3466{
3467 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3468 KVM_DEV_IRQ_HOST_MSIX);
3469}
9e03a040
FB		 3470
3471int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3472 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3473{
8b5ed7df
PX		 3474 X86IOMMUState *iommu = x86_iommu_get_default();
3475
3476 if (iommu) {
3477 int ret;
3478 MSIMessage src, dst;
3479 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3480
3481 src.address = route->u.msi.address_hi;
3482 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3483 src.address |= route->u.msi.address_lo;
3484 src.data = route->u.msi.data;
3485
3486 ret = class->int_remap(iommu, &src, &dst, dev ? \
3487 pci_requester_id(dev) : \
3488 X86_IOMMU_SID_INVALID);
3489 if (ret) {
3490 trace_kvm_x86_fixup_msi_error(route->gsi);
3491 return 1;
3492 }
3493
3494 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3495 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3496 route->u.msi.data = dst.data;
3497 }
3498
9e03a040
FB		 3499 return 0;
3500}
1850b6b7 3501
38d87493
PX		 3502typedef struct MSIRouteEntry MSIRouteEntry;
3503
3504struct MSIRouteEntry {
3505 PCIDevice *dev; /* Device pointer */
3506 int vector; /* MSI/MSIX vector index */
3507 int virq; /* Virtual IRQ index */
3508 QLIST_ENTRY(MSIRouteEntry) list;
3509};
3510
3511/* List of used GSI routes */
3512static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3513 QLIST_HEAD_INITIALIZER(msi_route_list);
3514
e1d4fb2d
PX		 3515static void kvm_update_msi_routes_all(void *private, bool global,
3516 uint32_t index, uint32_t mask)
3517{
3518 int cnt = 0;
3519 MSIRouteEntry *entry;
3520 MSIMessage msg;
3521 /* TODO: explicit route update */
3522 QLIST_FOREACH(entry, &msi_route_list, list) {
3523 cnt++;
3524 msg = pci_get_msi_message(entry->dev, entry->vector);
3525 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3526 msg, entry->dev);
3527 }
3f1fea0f 3528 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3529 trace_kvm_x86_update_msi_routes(cnt);
3530}
3531
38d87493
PX		 3532int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3533 int vector, PCIDevice *dev)
3534{
e1d4fb2d 3535 static bool notify_list_inited = false;
38d87493
PX		 3536 MSIRouteEntry *entry;
3537
3538 if (!dev) {
3539 /* These are (possibly) IOAPIC routes only used for split
3540 * kernel irqchip mode, while what we are housekeeping are
3541 * PCI devices only. */
3542 return 0;
3543 }
3544
3545 entry = g_new0(MSIRouteEntry, 1);
3546 entry->dev = dev;
3547 entry->vector = vector;
3548 entry->virq = route->gsi;
3549 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3550
3551 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3552
3553 if (!notify_list_inited) {
3554 /* For the first time we do add route, add ourselves into
3555 * IOMMU's IEC notify list if needed. */
3556 X86IOMMUState *iommu = x86_iommu_get_default();
3557 if (iommu) {
3558 x86_iommu_iec_register_notifier(iommu,
3559 kvm_update_msi_routes_all,
3560 NULL);
3561 }
3562 notify_list_inited = true;
3563 }
38d87493
PX		 3564 return 0;
3565}
3566
3567int kvm_arch_release_virq_post(int virq)
3568{
3569 MSIRouteEntry *entry, *next;
3570 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3571 if (entry->virq == virq) {
3572 trace_kvm_x86_remove_msi_route(virq);
3573 QLIST_REMOVE(entry, list);
3574 break;
3575 }
3576 }
9e03a040
FB		 3577 return 0;
3578}
1850b6b7
EA		 3579
3580int kvm_arch_msi_data_to_gsi(uint32_t data)
3581{
3582 abort();
3583}
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