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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
b253149b | 27 | #include <asm/mwait.h> |
389d1fb1 | 28 | #include <asm/i387.h> |
1361b83a | 29 | #include <asm/fpu-internal.h> |
66cb5917 | 30 | #include <asm/debugreg.h> |
90e24014 RW |
31 | #include <asm/nmi.h> |
32 | ||
45046892 TG |
33 | /* |
34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
36 | * so they are allowed to end up in the .data..cacheline_aligned | |
37 | * section. Since TSS's are completely CPU-local, we want them | |
38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
39 | */ | |
277d5b40 | 40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; |
45046892 | 41 | |
90e24014 RW |
42 | #ifdef CONFIG_X86_64 |
43 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
44 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
45 | ||
46 | void idle_notifier_register(struct notifier_block *n) | |
47 | { | |
48 | atomic_notifier_chain_register(&idle_notifier, n); | |
49 | } | |
50 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
51 | ||
52 | void idle_notifier_unregister(struct notifier_block *n) | |
53 | { | |
54 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
55 | } | |
56 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
57 | #endif | |
c1e3b377 | 58 | |
aa283f49 | 59 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 60 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 61 | |
55ccf3fe SS |
62 | /* |
63 | * this gets called so that we can store lazy state into memory and copy the | |
64 | * current task into the new thread. | |
65 | */ | |
61c4628b SS |
66 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
67 | { | |
68 | *dst = *src; | |
f1853505 | 69 | |
dc56c0f9 | 70 | dst->thread.fpu_counter = 0; |
5e23fee2 ON |
71 | dst->thread.fpu.has_fpu = 0; |
72 | dst->thread.fpu.last_cpu = ~0; | |
73 | dst->thread.fpu.state = NULL; | |
f1853505 ON |
74 | if (tsk_used_math(src)) { |
75 | int err = fpu_alloc(&dst->thread.fpu); | |
76 | if (err) | |
77 | return err; | |
304bceda | 78 | fpu_copy(dst, src); |
aa283f49 | 79 | } |
61c4628b SS |
80 | return 0; |
81 | } | |
82 | ||
aa283f49 | 83 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 84 | { |
86603283 | 85 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
86 | } |
87 | ||
38e7c572 | 88 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 89 | { |
38e7c572 | 90 | free_thread_xstate(tsk); |
61c4628b SS |
91 | } |
92 | ||
93 | void arch_task_cache_init(void) | |
94 | { | |
95 | task_xstate_cachep = | |
96 | kmem_cache_create("task_xstate", xstate_size, | |
97 | __alignof__(union thread_xstate), | |
2dff4405 | 98 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
7496d645 | 99 | setup_xstate_comp(); |
61c4628b | 100 | } |
7f424a8b | 101 | |
389d1fb1 JF |
102 | /* |
103 | * Free current thread data structures etc.. | |
104 | */ | |
105 | void exit_thread(void) | |
106 | { | |
107 | struct task_struct *me = current; | |
108 | struct thread_struct *t = &me->thread; | |
250981e6 | 109 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 110 | |
250981e6 | 111 | if (bp) { |
389d1fb1 JF |
112 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
113 | ||
389d1fb1 JF |
114 | t->io_bitmap_ptr = NULL; |
115 | clear_thread_flag(TIF_IO_BITMAP); | |
116 | /* | |
117 | * Careful, clear this in the TSS too: | |
118 | */ | |
119 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
120 | t->io_bitmap_max = 0; | |
121 | put_cpu(); | |
250981e6 | 122 | kfree(bp); |
389d1fb1 | 123 | } |
1dcc8d7b SS |
124 | |
125 | drop_fpu(me); | |
389d1fb1 JF |
126 | } |
127 | ||
128 | void flush_thread(void) | |
129 | { | |
130 | struct task_struct *tsk = current; | |
131 | ||
24f1e32c | 132 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 133 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
304bceda SS |
134 | drop_init_fpu(tsk); |
135 | /* | |
136 | * Free the FPU state for non xsave platforms. They get reallocated | |
137 | * lazily at the first use. | |
138 | */ | |
5d2bd700 | 139 | if (!use_eager_fpu()) |
304bceda | 140 | free_thread_xstate(tsk); |
389d1fb1 JF |
141 | } |
142 | ||
143 | static void hard_disable_TSC(void) | |
144 | { | |
145 | write_cr4(read_cr4() | X86_CR4_TSD); | |
146 | } | |
147 | ||
148 | void disable_TSC(void) | |
149 | { | |
150 | preempt_disable(); | |
151 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
152 | /* | |
153 | * Must flip the CPU state synchronously with | |
154 | * TIF_NOTSC in the current running context. | |
155 | */ | |
156 | hard_disable_TSC(); | |
157 | preempt_enable(); | |
158 | } | |
159 | ||
160 | static void hard_enable_TSC(void) | |
161 | { | |
162 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
163 | } | |
164 | ||
165 | static void enable_TSC(void) | |
166 | { | |
167 | preempt_disable(); | |
168 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
169 | /* | |
170 | * Must flip the CPU state synchronously with | |
171 | * TIF_NOTSC in the current running context. | |
172 | */ | |
173 | hard_enable_TSC(); | |
174 | preempt_enable(); | |
175 | } | |
176 | ||
177 | int get_tsc_mode(unsigned long adr) | |
178 | { | |
179 | unsigned int val; | |
180 | ||
181 | if (test_thread_flag(TIF_NOTSC)) | |
182 | val = PR_TSC_SIGSEGV; | |
183 | else | |
184 | val = PR_TSC_ENABLE; | |
185 | ||
186 | return put_user(val, (unsigned int __user *)adr); | |
187 | } | |
188 | ||
189 | int set_tsc_mode(unsigned int val) | |
190 | { | |
191 | if (val == PR_TSC_SIGSEGV) | |
192 | disable_TSC(); | |
193 | else if (val == PR_TSC_ENABLE) | |
194 | enable_TSC(); | |
195 | else | |
196 | return -EINVAL; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
202 | struct tss_struct *tss) | |
203 | { | |
204 | struct thread_struct *prev, *next; | |
205 | ||
206 | prev = &prev_p->thread; | |
207 | next = &next_p->thread; | |
208 | ||
ea8e61b7 PZ |
209 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
210 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
211 | unsigned long debugctl = get_debugctlmsr(); | |
212 | ||
213 | debugctl &= ~DEBUGCTLMSR_BTF; | |
214 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
215 | debugctl |= DEBUGCTLMSR_BTF; | |
216 | ||
217 | update_debugctlmsr(debugctl); | |
218 | } | |
389d1fb1 | 219 | |
389d1fb1 JF |
220 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
221 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
222 | /* prev and next are different */ | |
223 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
224 | hard_disable_TSC(); | |
225 | else | |
226 | hard_enable_TSC(); | |
227 | } | |
228 | ||
229 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
230 | /* | |
231 | * Copy the relevant range of the IO bitmap. | |
232 | * Normally this is 128 bytes or less: | |
233 | */ | |
234 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
235 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
236 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
237 | /* | |
238 | * Clear any possible leftover bits: | |
239 | */ | |
240 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
241 | } | |
7c68af6e | 242 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
243 | } |
244 | ||
00dba564 TG |
245 | /* |
246 | * Idle related variables and functions | |
247 | */ | |
d1896049 | 248 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
249 | EXPORT_SYMBOL(boot_option_idle_override); |
250 | ||
a476bda3 | 251 | static void (*x86_idle)(void); |
00dba564 | 252 | |
90e24014 RW |
253 | #ifndef CONFIG_SMP |
254 | static inline void play_dead(void) | |
255 | { | |
256 | BUG(); | |
257 | } | |
258 | #endif | |
259 | ||
260 | #ifdef CONFIG_X86_64 | |
261 | void enter_idle(void) | |
262 | { | |
c6ae41e7 | 263 | this_cpu_write(is_idle, 1); |
90e24014 RW |
264 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
265 | } | |
266 | ||
267 | static void __exit_idle(void) | |
268 | { | |
269 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
270 | return; | |
271 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
272 | } | |
273 | ||
274 | /* Called from interrupts to signify idle end */ | |
275 | void exit_idle(void) | |
276 | { | |
277 | /* idle loop has pid 0 */ | |
278 | if (current->pid) | |
279 | return; | |
280 | __exit_idle(); | |
281 | } | |
282 | #endif | |
283 | ||
7d1a9417 TG |
284 | void arch_cpu_idle_enter(void) |
285 | { | |
286 | local_touch_nmi(); | |
287 | enter_idle(); | |
288 | } | |
90e24014 | 289 | |
7d1a9417 TG |
290 | void arch_cpu_idle_exit(void) |
291 | { | |
292 | __exit_idle(); | |
293 | } | |
90e24014 | 294 | |
7d1a9417 TG |
295 | void arch_cpu_idle_dead(void) |
296 | { | |
297 | play_dead(); | |
298 | } | |
90e24014 | 299 | |
7d1a9417 TG |
300 | /* |
301 | * Called from the generic idle code. | |
302 | */ | |
303 | void arch_cpu_idle(void) | |
304 | { | |
16f8b05a | 305 | x86_idle(); |
90e24014 RW |
306 | } |
307 | ||
00dba564 | 308 | /* |
7d1a9417 | 309 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
310 | */ |
311 | void default_idle(void) | |
312 | { | |
4d0e42cc | 313 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 314 | safe_halt(); |
4d0e42cc | 315 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 316 | } |
60b8b1de | 317 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
318 | EXPORT_SYMBOL(default_idle); |
319 | #endif | |
320 | ||
6a377ddc LB |
321 | #ifdef CONFIG_XEN |
322 | bool xen_set_default_idle(void) | |
e5fd47bf | 323 | { |
a476bda3 | 324 | bool ret = !!x86_idle; |
e5fd47bf | 325 | |
a476bda3 | 326 | x86_idle = default_idle; |
e5fd47bf KRW |
327 | |
328 | return ret; | |
329 | } | |
6a377ddc | 330 | #endif |
d3ec5cae IV |
331 | void stop_this_cpu(void *dummy) |
332 | { | |
333 | local_irq_disable(); | |
334 | /* | |
335 | * Remove this CPU: | |
336 | */ | |
4f062896 | 337 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
338 | disable_local_APIC(); |
339 | ||
27be4570 LB |
340 | for (;;) |
341 | halt(); | |
7f424a8b PZ |
342 | } |
343 | ||
02c68a02 LB |
344 | bool amd_e400_c1e_detected; |
345 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 346 | |
02c68a02 | 347 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 348 | |
02c68a02 | 349 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 350 | { |
02c68a02 LB |
351 | if (amd_e400_c1e_mask != NULL) |
352 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
353 | } |
354 | ||
aa276e1c | 355 | /* |
02c68a02 | 356 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
357 | * pending message MSR. If we detect C1E, then we handle it the same |
358 | * way as C3 power states (local apic timer and TSC stop) | |
359 | */ | |
02c68a02 | 360 | static void amd_e400_idle(void) |
aa276e1c | 361 | { |
02c68a02 | 362 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
363 | u32 lo, hi; |
364 | ||
365 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 366 | |
aa276e1c | 367 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 368 | amd_e400_c1e_detected = true; |
40fb1715 | 369 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 370 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 371 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
372 | } |
373 | } | |
374 | ||
02c68a02 | 375 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
376 | int cpu = smp_processor_id(); |
377 | ||
02c68a02 LB |
378 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
379 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 380 | /* |
f833bab8 | 381 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 382 | */ |
aa276e1c TG |
383 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
384 | &cpu); | |
c767a54b | 385 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
386 | } |
387 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 388 | |
aa276e1c | 389 | default_idle(); |
0beefa20 TG |
390 | |
391 | /* | |
392 | * The switch back from broadcast mode needs to be | |
393 | * called with interrupts disabled. | |
394 | */ | |
ea811747 PZ |
395 | local_irq_disable(); |
396 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
397 | local_irq_enable(); | |
aa276e1c TG |
398 | } else |
399 | default_idle(); | |
400 | } | |
401 | ||
b253149b LB |
402 | /* |
403 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
404 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
405 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
406 | * | |
407 | * Some AMD machines are the opposite, they depend on using HALT. | |
408 | * | |
409 | * So for default C1, which is used during boot until cpuidle loads, | |
410 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
411 | */ | |
412 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
413 | { | |
414 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
415 | return 0; | |
416 | ||
417 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
418 | return 0; | |
419 | ||
420 | return 1; | |
421 | } | |
422 | ||
423 | /* | |
424 | * MONITOR/MWAIT with no hints, used for default default C1 state. | |
425 | * This invokes MWAIT with interrutps enabled and no flags, | |
426 | * which is backwards compatible with the original MWAIT implementation. | |
427 | */ | |
428 | ||
429 | static void mwait_idle(void) | |
430 | { | |
431 | if (!need_resched()) { | |
432 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) | |
433 | clflush((void *)¤t_thread_info()->flags); | |
434 | ||
435 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
436 | smp_mb(); | |
437 | if (!need_resched()) | |
438 | __sti_mwait(0, 0); | |
439 | else | |
440 | local_irq_enable(); | |
441 | } else | |
442 | local_irq_enable(); | |
443 | } | |
444 | ||
148f9bb8 | 445 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 446 | { |
3e5095d1 | 447 | #ifdef CONFIG_SMP |
7d1a9417 | 448 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 449 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 450 | #endif |
7d1a9417 | 451 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
452 | return; |
453 | ||
7d7dc116 | 454 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 455 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 456 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 457 | x86_idle = amd_e400_idle; |
b253149b LB |
458 | } else if (prefer_mwait_c1_over_halt(c)) { |
459 | pr_info("using mwait in idle threads\n"); | |
460 | x86_idle = mwait_idle; | |
6ddd2a27 | 461 | } else |
a476bda3 | 462 | x86_idle = default_idle; |
7f424a8b PZ |
463 | } |
464 | ||
02c68a02 | 465 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 466 | { |
02c68a02 | 467 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 468 | if (x86_idle == amd_e400_idle) |
02c68a02 | 469 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
470 | } |
471 | ||
7f424a8b PZ |
472 | static int __init idle_setup(char *str) |
473 | { | |
ab6bc3e3 CG |
474 | if (!str) |
475 | return -EINVAL; | |
476 | ||
7f424a8b | 477 | if (!strcmp(str, "poll")) { |
c767a54b | 478 | pr_info("using polling idle threads\n"); |
d1896049 | 479 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 480 | cpu_idle_poll_ctrl(true); |
d1896049 | 481 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
482 | /* |
483 | * When the boot option of idle=halt is added, halt is | |
484 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
485 | * won't be used again. | |
486 | * To continue to load the CPU idle driver, don't touch | |
487 | * the boot_option_idle_override. | |
488 | */ | |
a476bda3 | 489 | x86_idle = default_idle; |
d1896049 | 490 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
491 | } else if (!strcmp(str, "nomwait")) { |
492 | /* | |
493 | * If the boot option of "idle=nomwait" is added, | |
494 | * it means that mwait will be disabled for CPU C2/C3 | |
495 | * states. In such case it won't touch the variable | |
496 | * of boot_option_idle_override. | |
497 | */ | |
d1896049 | 498 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 499 | } else |
7f424a8b PZ |
500 | return -1; |
501 | ||
7f424a8b PZ |
502 | return 0; |
503 | } | |
504 | early_param("idle", idle_setup); | |
505 | ||
9d62dcdf AW |
506 | unsigned long arch_align_stack(unsigned long sp) |
507 | { | |
508 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
509 | sp -= get_random_int() % 8192; | |
510 | return sp & ~0xf; | |
511 | } | |
512 | ||
513 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
514 | { | |
515 | unsigned long range_end = mm->brk + 0x02000000; | |
516 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
517 | } | |
518 |