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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
1353ebb4 JF |
56 | void __init check_bugs(void) |
57 | { | |
58 | identify_boot_cpu(); | |
55a36b65 | 59 | |
483ec3c6 TG |
60 | /* |
61 | * identify_boot_cpu() initialized SMT support information, let the | |
62 | * core code know. | |
63 | */ | |
ade31b9e | 64 | cpu_smt_check_topology_early(); |
483ec3c6 | 65 | |
62a67e12 BP |
66 | if (!IS_ENABLED(CONFIG_SMP)) { |
67 | pr_info("CPU: "); | |
68 | print_cpu_info(&boot_cpu_data); | |
69 | } | |
70 | ||
296b454a KRW |
71 | /* |
72 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
73 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
74 | * init code as it is not enumerated and depends on the family. | |
296b454a | 75 | */ |
50f9b919 | 76 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
77 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
78 | ||
e5f984ed TG |
79 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
80 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
81 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
82 | ||
da285121 DW |
83 | /* Select the proper spectre mitigation before patching alternatives */ |
84 | spectre_v2_select_mitigation(); | |
85 | ||
e63490c8 KRW |
86 | /* |
87 | * Select proper mitigation for any exposure to the Speculative Store | |
88 | * Bypass vulnerability. | |
89 | */ | |
90 | ssb_select_mitigation(); | |
91 | ||
05516ad8 AK |
92 | l1tf_select_mitigation(); |
93 | ||
62a67e12 | 94 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
95 | /* |
96 | * Check whether we are able to run this kernel safely on SMP. | |
97 | * | |
98 | * - i386 is no longer supported. | |
99 | * - In order to run on anything without a TSC, we need to be | |
100 | * compiled for a i486. | |
101 | */ | |
102 | if (boot_cpu_data.x86 < 4) | |
103 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
104 | ||
bfe4bb15 MV |
105 | init_utsname()->machine[1] = |
106 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 107 | alternative_instructions(); |
304bceda | 108 | |
4d164092 | 109 | fpu__init_check_bugs(); |
62a67e12 BP |
110 | #else /* CONFIG_X86_64 */ |
111 | alternative_instructions(); | |
112 | ||
113 | /* | |
114 | * Make sure the first 2MB area is not mapped by huge pages | |
115 | * There are typically fixed size MTRRs in there and overlapping | |
116 | * MTRRs into large pages causes slow downs. | |
117 | * | |
118 | * Right now we don't do that with gbpages because there seems | |
119 | * very little benefit for that case. | |
120 | */ | |
121 | if (!direct_gbpages) | |
122 | set_memory_4k((unsigned long)__va(0), 1); | |
123 | #endif | |
1353ebb4 | 124 | } |
61dc0f55 | 125 | |
12376b62 BP |
126 | void |
127 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 128 | { |
e5f984ed | 129 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 130 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 131 | |
50f9b919 | 132 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 133 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
134 | /* |
135 | * Restrict guest_spec_ctrl to supported values. Clear the | |
136 | * modifiable bits in the host base value and or the | |
137 | * modifiable bits from the guest value. | |
138 | */ | |
139 | guestval = hostval & ~x86_spec_ctrl_mask; | |
140 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
141 | ||
12376b62 | 142 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
143 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
144 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 145 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 146 | |
e5f984ed TG |
147 | if (hostval != guestval) { |
148 | msrval = setguest ? guestval : hostval; | |
149 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
150 | } |
151 | } | |
1238ed31 TG |
152 | |
153 | /* | |
154 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
155 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
156 | */ | |
157 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
158 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
159 | return; | |
160 | ||
161 | /* | |
162 | * If the host has SSBD mitigation enabled, force it in the host's | |
163 | * virtual MSR value. If its not permanently enabled, evaluate | |
164 | * current's TIF_SSBD thread flag. | |
165 | */ | |
166 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
167 | hostval = SPEC_CTRL_SSBD; | |
168 | else | |
169 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
170 | ||
171 | /* Sanitize the guest value */ | |
172 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
173 | ||
174 | if (hostval != guestval) { | |
175 | unsigned long tif; | |
176 | ||
177 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
178 | ssbd_spec_ctrl_to_tif(hostval); | |
179 | ||
8fce7184 | 180 | speculation_ctrl_update(tif); |
1238ed31 | 181 | } |
19fff03f | 182 | } |
12376b62 | 183 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 184 | |
8fe36c9d | 185 | static void x86_amd_ssb_disable(void) |
c37b94dd | 186 | { |
8fe36c9d | 187 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 188 | |
65e02bbd TL |
189 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
190 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
191 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
192 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
193 | } | |
194 | ||
aef0bebc TG |
195 | #undef pr_fmt |
196 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
197 | ||
198 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
199 | SPECTRE_V2_NONE; | |
200 | ||
d280282b | 201 | #ifdef RETPOLINE |
bb3c2578 TG |
202 | static bool spectre_v2_bad_module; |
203 | ||
d280282b AK |
204 | bool retpoline_module_ok(bool has_retpoline) |
205 | { | |
206 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
207 | return true; | |
208 | ||
c8b8e109 | 209 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
210 | spectre_v2_bad_module = true; |
211 | return false; | |
212 | } | |
bb3c2578 TG |
213 | |
214 | static inline const char *spectre_v2_module_string(void) | |
215 | { | |
216 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
217 | } | |
218 | #else | |
219 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 220 | #endif |
da285121 | 221 | |
da285121 DW |
222 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
223 | { | |
224 | int len = strlen(opt); | |
225 | ||
226 | return len == arglen && !strncmp(arg, opt, len); | |
227 | } | |
228 | ||
aef0bebc TG |
229 | /* The kernel command line selection for spectre v2 */ |
230 | enum spectre_v2_mitigation_cmd { | |
231 | SPECTRE_V2_CMD_NONE, | |
232 | SPECTRE_V2_CMD_AUTO, | |
233 | SPECTRE_V2_CMD_FORCE, | |
234 | SPECTRE_V2_CMD_RETPOLINE, | |
235 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
236 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
237 | }; | |
238 | ||
239 | static const char *spectre_v2_strings[] = { | |
240 | [SPECTRE_V2_NONE] = "Vulnerable", | |
241 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
242 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
243 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
244 | }; | |
245 | ||
17c33e7c KA |
246 | static const struct { |
247 | const char *option; | |
248 | enum spectre_v2_mitigation_cmd cmd; | |
249 | bool secure; | |
250 | } mitigation_options[] = { | |
aef0bebc TG |
251 | { "off", SPECTRE_V2_CMD_NONE, false }, |
252 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
253 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
254 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
255 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
256 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
257 | }; |
258 | ||
aef0bebc TG |
259 | static void __init spec2_print_if_insecure(const char *reason) |
260 | { | |
261 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
262 | pr_info("%s selected on command line.\n", reason); | |
263 | } | |
264 | ||
265 | static void __init spec2_print_if_secure(const char *reason) | |
266 | { | |
267 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
268 | pr_info("%s selected on command line.\n", reason); | |
269 | } | |
270 | ||
da285121 DW |
271 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
272 | { | |
aef0bebc | 273 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 274 | char arg[20]; |
17c33e7c | 275 | int ret, i; |
17c33e7c KA |
276 | |
277 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
278 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 279 | |
4e8e955a TC |
280 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
281 | if (ret < 0) | |
282 | return SPECTRE_V2_CMD_AUTO; | |
283 | ||
284 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
285 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
286 | continue; | |
287 | cmd = mitigation_options[i].cmd; | |
288 | break; | |
289 | } | |
290 | ||
291 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
292 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
293 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
294 | } |
295 | ||
17c33e7c KA |
296 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
297 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
298 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
299 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 300 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 301 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
302 | } |
303 | ||
304 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
305 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
306 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
307 | return SPECTRE_V2_CMD_AUTO; | |
308 | } | |
309 | ||
310 | if (mitigation_options[i].secure) | |
311 | spec2_print_if_secure(mitigation_options[i].option); | |
312 | else | |
313 | spec2_print_if_insecure(mitigation_options[i].option); | |
314 | ||
315 | return cmd; | |
da285121 DW |
316 | } |
317 | ||
318 | static void __init spectre_v2_select_mitigation(void) | |
319 | { | |
320 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
321 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
322 | ||
323 | /* | |
324 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
325 | * then nothing to do. | |
326 | */ | |
327 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
328 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
329 | return; | |
330 | ||
331 | switch (cmd) { | |
332 | case SPECTRE_V2_CMD_NONE: | |
333 | return; | |
334 | ||
335 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 336 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
337 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
338 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
339 | /* Force it so VMEXIT will restore correctly */ | |
340 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
341 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
342 | goto specv2_set_mode; | |
343 | } | |
d0f293e0 DL |
344 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
345 | goto retpoline_auto; | |
346 | break; | |
da285121 DW |
347 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
348 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
349 | goto retpoline_amd; | |
350 | break; | |
351 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
352 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
353 | goto retpoline_generic; | |
354 | break; | |
355 | case SPECTRE_V2_CMD_RETPOLINE: | |
356 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
357 | goto retpoline_auto; | |
358 | break; | |
359 | } | |
713f1b95 | 360 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
361 | return; |
362 | ||
363 | retpoline_auto: | |
364 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
365 | retpoline_amd: | |
366 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 367 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
368 | goto retpoline_generic; |
369 | } | |
51dd01b5 | 370 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
371 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
372 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
373 | } else { | |
374 | retpoline_generic: | |
51dd01b5 | 375 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
376 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
377 | } | |
378 | ||
1044fde9 | 379 | specv2_set_mode: |
da285121 DW |
380 | spectre_v2_enabled = mode; |
381 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
382 | |
383 | /* | |
14623a43 JK |
384 | * If spectre v2 protection has been enabled, unconditionally fill |
385 | * RSB during a context switch; this protects against two independent | |
386 | * issues: | |
c995efd5 | 387 | * |
14623a43 JK |
388 | * - RSB underflow (and switch to BTB) on Skylake+ |
389 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 390 | */ |
14623a43 JK |
391 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
392 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 DW |
393 | |
394 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
581abf91 DW |
395 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
396 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
713f1b95 | 397 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
bd12e896 | 398 | } |
390b99c3 DW |
399 | |
400 | /* | |
401 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
402 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
403 | * speculation around firmware calls only when Enhanced IBRS isn't | |
404 | * supported. | |
405 | * | |
406 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
407 | * the user might select retpoline on the kernel command line and if | |
408 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
409 | * enable IBRS around firmware calls. | |
390b99c3 | 410 | */ |
1044fde9 | 411 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
412 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
413 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
414 | } | |
7011f443 JK |
415 | |
416 | /* Enable STIBP if appropriate */ | |
417 | arch_smt_update(); | |
da285121 DW |
418 | } |
419 | ||
aef0bebc TG |
420 | static bool stibp_needed(void) |
421 | { | |
422 | if (spectre_v2_enabled == SPECTRE_V2_NONE) | |
423 | return false; | |
424 | ||
425 | /* Enhanced IBRS makes using STIBP unnecessary. */ | |
426 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
427 | return false; | |
428 | ||
429 | if (!boot_cpu_has(X86_FEATURE_STIBP)) | |
430 | return false; | |
431 | ||
432 | return true; | |
433 | } | |
434 | ||
435 | static void update_stibp_msr(void *info) | |
436 | { | |
437 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
438 | } | |
439 | ||
440 | void arch_smt_update(void) | |
441 | { | |
442 | u64 mask; | |
443 | ||
444 | if (!stibp_needed()) | |
445 | return; | |
446 | ||
447 | mutex_lock(&spec_ctrl_mutex); | |
448 | ||
449 | mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; | |
450 | if (sched_smt_active()) | |
451 | mask |= SPEC_CTRL_STIBP; | |
452 | ||
453 | if (mask != x86_spec_ctrl_base) { | |
454 | pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", | |
455 | mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); | |
456 | x86_spec_ctrl_base = mask; | |
457 | on_each_cpu(update_stibp_msr, NULL, 1); | |
458 | } | |
459 | mutex_unlock(&spec_ctrl_mutex); | |
460 | } | |
461 | ||
e63490c8 KRW |
462 | #undef pr_fmt |
463 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
464 | ||
b5e6d77d | 465 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
466 | |
467 | /* The kernel command line selection */ | |
468 | enum ssb_mitigation_cmd { | |
469 | SPEC_STORE_BYPASS_CMD_NONE, | |
470 | SPEC_STORE_BYPASS_CMD_AUTO, | |
471 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 472 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 473 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
474 | }; |
475 | ||
476 | static const char *ssb_strings[] = { | |
477 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
574dcf89 | 478 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
479 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
480 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
481 | }; |
482 | ||
483 | static const struct { | |
484 | const char *option; | |
485 | enum ssb_mitigation_cmd cmd; | |
486 | } ssb_mitigation_options[] = { | |
c7416003 KC |
487 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
488 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
489 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
490 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
491 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
492 | }; |
493 | ||
494 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
495 | { | |
496 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
497 | char arg[20]; | |
498 | int ret, i; | |
499 | ||
500 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
501 | return SPEC_STORE_BYPASS_CMD_NONE; | |
502 | } else { | |
503 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
504 | arg, sizeof(arg)); | |
505 | if (ret < 0) | |
506 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
507 | ||
508 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
509 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
510 | continue; | |
511 | ||
512 | cmd = ssb_mitigation_options[i].cmd; | |
513 | break; | |
514 | } | |
515 | ||
516 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
517 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
518 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
519 | } | |
520 | } | |
521 | ||
522 | return cmd; | |
523 | } | |
524 | ||
dbe3009d | 525 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
526 | { |
527 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
528 | enum ssb_mitigation_cmd cmd; | |
529 | ||
8fe36c9d | 530 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
531 | return mode; |
532 | ||
533 | cmd = ssb_parse_cmdline(); | |
534 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
535 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
536 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
537 | return mode; | |
538 | ||
539 | switch (cmd) { | |
540 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
541 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
542 | /* | |
543 | * Choose prctl+seccomp as the default mode if seccomp is | |
544 | * enabled. | |
545 | */ | |
546 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
547 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
548 | else | |
549 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 550 | break; |
e63490c8 KRW |
551 | case SPEC_STORE_BYPASS_CMD_ON: |
552 | mode = SPEC_STORE_BYPASS_DISABLE; | |
553 | break; | |
574dcf89 TG |
554 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
555 | mode = SPEC_STORE_BYPASS_PRCTL; | |
556 | break; | |
e63490c8 KRW |
557 | case SPEC_STORE_BYPASS_CMD_NONE: |
558 | break; | |
559 | } | |
560 | ||
23b9eab9 KRW |
561 | /* |
562 | * We have three CPU feature flags that are in play here: | |
563 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 564 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
565 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
566 | */ | |
574dcf89 | 567 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 568 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 569 | /* |
3b881627 KRW |
570 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
571 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 572 | */ |
5005c716 TL |
573 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
574 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 575 | x86_amd_ssb_disable(); |
5005c716 | 576 | } else { |
8fe36c9d | 577 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 578 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 579 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
580 | } |
581 | } | |
582 | ||
e63490c8 KRW |
583 | return mode; |
584 | } | |
585 | ||
043d480e | 586 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
587 | { |
588 | ssb_mode = __ssb_select_mitigation(); | |
589 | ||
590 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
591 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
592 | } | |
593 | ||
da285121 | 594 | #undef pr_fmt |
c7416003 | 595 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 596 | |
199bfed2 | 597 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
574dcf89 | 598 | { |
733f4234 | 599 | bool update; |
574dcf89 | 600 | |
c7416003 KC |
601 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
602 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
603 | return -ENXIO; |
604 | ||
733f4234 TG |
605 | switch (ctrl) { |
606 | case PR_SPEC_ENABLE: | |
607 | /* If speculation is force disabled, enable is not allowed */ | |
608 | if (task_spec_ssb_force_disable(task)) | |
609 | return -EPERM; | |
610 | task_clear_spec_ssb_disable(task); | |
8fe36c9d | 611 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
612 | break; |
613 | case PR_SPEC_DISABLE: | |
614 | task_set_spec_ssb_disable(task); | |
8fe36c9d | 615 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
616 | break; |
617 | case PR_SPEC_FORCE_DISABLE: | |
618 | task_set_spec_ssb_disable(task); | |
619 | task_set_spec_ssb_force_disable(task); | |
8fe36c9d | 620 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
621 | break; |
622 | default: | |
623 | return -ERANGE; | |
624 | } | |
574dcf89 | 625 | |
199bfed2 KC |
626 | /* |
627 | * If being set on non-current task, delay setting the CPU | |
628 | * mitigation until it is next scheduled. | |
629 | */ | |
733f4234 | 630 | if (task == current && update) |
8fce7184 | 631 | speculation_ctrl_update_current(); |
574dcf89 TG |
632 | |
633 | return 0; | |
634 | } | |
635 | ||
5b38e244 TG |
636 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
637 | unsigned long ctrl) | |
638 | { | |
639 | switch (which) { | |
640 | case PR_SPEC_STORE_BYPASS: | |
641 | return ssb_prctl_set(task, ctrl); | |
642 | default: | |
643 | return -ENODEV; | |
644 | } | |
645 | } | |
646 | ||
647 | #ifdef CONFIG_SECCOMP | |
648 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
649 | { | |
c7416003 KC |
650 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
651 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
652 | } |
653 | #endif | |
654 | ||
199bfed2 | 655 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
656 | { |
657 | switch (ssb_mode) { | |
658 | case SPEC_STORE_BYPASS_DISABLE: | |
659 | return PR_SPEC_DISABLE; | |
c7416003 | 660 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 661 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
662 | if (task_spec_ssb_force_disable(task)) |
663 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
664 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
665 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
666 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
667 | default: | |
668 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
669 | return PR_SPEC_ENABLE; | |
670 | return PR_SPEC_NOT_AFFECTED; | |
671 | } | |
672 | } | |
673 | ||
199bfed2 | 674 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
675 | { |
676 | switch (which) { | |
677 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 678 | return ssb_prctl_get(task); |
574dcf89 TG |
679 | default: |
680 | return -ENODEV; | |
681 | } | |
682 | } | |
683 | ||
23b9eab9 KRW |
684 | void x86_spec_ctrl_setup_ap(void) |
685 | { | |
50f9b919 | 686 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 687 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
688 | |
689 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 690 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
691 | } |
692 | ||
73ca9f47 KRW |
693 | #undef pr_fmt |
694 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 695 | |
24fcb53c JK |
696 | /* Default mitigation for L1TF-affected CPUs */ |
697 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 698 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
699 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
700 | ||
522c7bed | 701 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
702 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
703 | #endif | |
704 | ||
f1f016ed AK |
705 | /* |
706 | * These CPUs all support 44bits physical address space internally in the | |
707 | * cache but CPUID can report a smaller number of physical address bits. | |
708 | * | |
709 | * The L1TF mitigation uses the top most address bit for the inversion of | |
710 | * non present PTEs. When the installed memory reaches into the top most | |
711 | * address bit due to memory holes, which has been observed on machines | |
712 | * which report 36bits physical address bits and have 32G RAM installed, | |
713 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
714 | * This is a false positive because the mitigation is still possible due to | |
715 | * the fact that the cache uses 44bit internally. Use the cache bits | |
716 | * instead of the reported physical bits and adjust them on the affected | |
717 | * machines to 44bit if the reported bits are less than 44. | |
718 | */ | |
719 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
720 | { | |
721 | if (c->x86 != 6) | |
722 | return; | |
723 | ||
724 | switch (c->x86_model) { | |
725 | case INTEL_FAM6_NEHALEM: | |
726 | case INTEL_FAM6_WESTMERE: | |
727 | case INTEL_FAM6_SANDYBRIDGE: | |
728 | case INTEL_FAM6_IVYBRIDGE: | |
729 | case INTEL_FAM6_HASWELL_CORE: | |
730 | case INTEL_FAM6_HASWELL_ULT: | |
731 | case INTEL_FAM6_HASWELL_GT3E: | |
732 | case INTEL_FAM6_BROADWELL_CORE: | |
733 | case INTEL_FAM6_BROADWELL_GT3E: | |
734 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
735 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
736 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
737 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
738 | if (c->x86_cache_bits < 44) | |
739 | c->x86_cache_bits = 44; | |
740 | break; | |
741 | } | |
742 | } | |
743 | ||
73ca9f47 KRW |
744 | static void __init l1tf_select_mitigation(void) |
745 | { | |
746 | u64 half_pa; | |
747 | ||
748 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
749 | return; | |
750 | ||
f1f016ed AK |
751 | override_cache_bits(&boot_cpu_data); |
752 | ||
24fcb53c JK |
753 | switch (l1tf_mitigation) { |
754 | case L1TF_MITIGATION_OFF: | |
755 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
756 | case L1TF_MITIGATION_FLUSH: | |
757 | break; | |
758 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
759 | case L1TF_MITIGATION_FULL: | |
760 | cpu_smt_disable(false); | |
761 | break; | |
762 | case L1TF_MITIGATION_FULL_FORCE: | |
763 | cpu_smt_disable(true); | |
764 | break; | |
765 | } | |
766 | ||
73ca9f47 KRW |
767 | #if CONFIG_PGTABLE_LEVELS == 2 |
768 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
769 | return; | |
770 | #endif | |
771 | ||
73ca9f47 KRW |
772 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
773 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
774 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
775 | return; | |
776 | } | |
777 | ||
778 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
779 | } | |
24fcb53c JK |
780 | |
781 | static int __init l1tf_cmdline(char *str) | |
782 | { | |
783 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
784 | return 0; | |
785 | ||
786 | if (!str) | |
787 | return -EINVAL; | |
788 | ||
789 | if (!strcmp(str, "off")) | |
790 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
791 | else if (!strcmp(str, "flush,nowarn")) | |
792 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
793 | else if (!strcmp(str, "flush")) | |
794 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
795 | else if (!strcmp(str, "flush,nosmt")) | |
796 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
797 | else if (!strcmp(str, "full")) | |
798 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
799 | else if (!strcmp(str, "full,force")) | |
800 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
801 | ||
802 | return 0; | |
803 | } | |
804 | early_param("l1tf", l1tf_cmdline); | |
805 | ||
73ca9f47 KRW |
806 | #undef pr_fmt |
807 | ||
61dc0f55 | 808 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 809 | |
b9cfedcd TG |
810 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
811 | ||
812 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
813 | static const char *l1tf_vmx_states[] = { | |
1ead4979 TG |
814 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
815 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
816 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
817 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
818 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 819 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
820 | }; |
821 | ||
822 | static ssize_t l1tf_show_state(char *buf) | |
823 | { | |
824 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
825 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
826 | ||
3899f7b1 PB |
827 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
828 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 829 | sched_smt_active())) { |
3899f7b1 PB |
830 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
831 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 832 | } |
3899f7b1 PB |
833 | |
834 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
835 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 836 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
837 | } |
838 | #else | |
839 | static ssize_t l1tf_show_state(char *buf) | |
840 | { | |
841 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
842 | } | |
843 | #endif | |
844 | ||
2daa53e8 TC |
845 | static char *stibp_state(void) |
846 | { | |
4a8d91c8 TC |
847 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
848 | return ""; | |
849 | ||
2daa53e8 TC |
850 | if (x86_spec_ctrl_base & SPEC_CTRL_STIBP) |
851 | return ", STIBP"; | |
852 | else | |
853 | return ""; | |
854 | } | |
855 | ||
856 | static char *ibpb_state(void) | |
857 | { | |
858 | if (boot_cpu_has(X86_FEATURE_USE_IBPB)) | |
859 | return ", IBPB"; | |
860 | else | |
861 | return ""; | |
862 | } | |
863 | ||
ace051d5 | 864 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 865 | char *buf, unsigned int bug) |
61dc0f55 | 866 | { |
d2b8fc2d | 867 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 868 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
869 | |
870 | switch (bug) { | |
871 | case X86_BUG_CPU_MELTDOWN: | |
872 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
873 | return sprintf(buf, "Mitigation: PTI\n"); | |
874 | ||
875 | break; | |
876 | ||
877 | case X86_BUG_SPECTRE_V1: | |
878 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
879 | ||
880 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 881 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 882 | ibpb_state(), |
d2b8fc2d | 883 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 884 | stibp_state(), |
5e2fafd5 | 885 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
886 | spectre_v2_module_string()); |
887 | ||
e63490c8 KRW |
888 | case X86_BUG_SPEC_STORE_BYPASS: |
889 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
890 | ||
05516ad8 AK |
891 | case X86_BUG_L1TF: |
892 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 893 | return l1tf_show_state(buf); |
05516ad8 | 894 | break; |
d2b8fc2d KRW |
895 | default: |
896 | break; | |
897 | } | |
898 | ||
61dc0f55 TG |
899 | return sprintf(buf, "Vulnerable\n"); |
900 | } | |
901 | ||
d2b8fc2d KRW |
902 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
903 | { | |
904 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
905 | } | |
906 | ||
713f1b95 | 907 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 908 | { |
d2b8fc2d | 909 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
910 | } |
911 | ||
713f1b95 | 912 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 913 | { |
d2b8fc2d | 914 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 915 | } |
d7de9182 KRW |
916 | |
917 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
918 | { | |
919 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
920 | } | |
05516ad8 AK |
921 | |
922 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
923 | { | |
924 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
925 | } | |
61dc0f55 | 926 | #endif |