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KVM: x86: Pending interrupt may be delivered after INIT
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
16a96021
MT		 109static bool backwards_tsc_observed = false;
110
18863bdd
AK		 111#define KVM_NR_SHARED_MSRS 16
112
113struct kvm_shared_msrs_global {
114 int nr;
2bf78fa7 115 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118struct kvm_shared_msrs {
119 struct user_return_notifier urn;
120 bool registered;
2bf78fa7
SY		 121 struct kvm_shared_msr_values {
122 u64 host;
123 u64 curr;
124 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 128static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 129
417bc304 130struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 131 { "pf_fixed", VCPU_STAT(pf_fixed) },
132 { "pf_guest", VCPU_STAT(pf_guest) },
133 { "tlb_flush", VCPU_STAT(tlb_flush) },
134 { "invlpg", VCPU_STAT(invlpg) },
135 { "exits", VCPU_STAT(exits) },
136 { "io_exits", VCPU_STAT(io_exits) },
137 { "mmio_exits", VCPU_STAT(mmio_exits) },
138 { "signal_exits", VCPU_STAT(signal_exits) },
139 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 140 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 141 { "halt_exits", VCPU_STAT(halt_exits) },
142 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 143 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 144 { "request_irq", VCPU_STAT(request_irq_exits) },
145 { "irq_exits", VCPU_STAT(irq_exits) },
146 { "host_state_reload", VCPU_STAT(host_state_reload) },
147 { "efer_reload", VCPU_STAT(efer_reload) },
148 { "fpu_reload", VCPU_STAT(fpu_reload) },
149 { "insn_emulation", VCPU_STAT(insn_emulation) },
150 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 151 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 152 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 153 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
154 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
155 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
156 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
157 { "mmu_flooded", VM_STAT(mmu_flooded) },
158 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 159 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 160 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 161 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 162 { "largepages", VM_STAT(lpages) },
417bc304
HB		 163 { NULL }
164};
165
2acf923e
DC		 166u64 __read_mostly host_xcr0;
167
b6785def 168static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 169
af585b92
GN		 170static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171{
172 int i;
173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
174 vcpu->arch.apf.gfns[i] = ~0;
175}
176
18863bdd
AK		 177static void kvm_on_user_return(struct user_return_notifier *urn)
178{
179 unsigned slot;
18863bdd
AK		 180 struct kvm_shared_msrs *locals
181 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 182 struct kvm_shared_msr_values *values;
18863bdd
AK		 183
184 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 185 values = &locals->values[slot];
186 if (values->host != values->curr) {
187 wrmsrl(shared_msrs_global.msrs[slot], values->host);
188 values->curr = values->host;
18863bdd
AK		 189 }
190 }
191 locals->registered = false;
192 user_return_notifier_unregister(urn);
193}
194
2bf78fa7 195static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 196{
18863bdd 197 u64 value;
013f6a5d
MT		 198 unsigned int cpu = smp_processor_id();
199 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 200
2bf78fa7
SY		 201 /* only read, and nobody should modify it at this time,
202 * so don't need lock */
203 if (slot >= shared_msrs_global.nr) {
204 printk(KERN_ERR "kvm: invalid MSR slot!");
205 return;
206 }
207 rdmsrl_safe(msr, &value);
208 smsr->values[slot].host = value;
209 smsr->values[slot].curr = value;
210}
211
212void kvm_define_shared_msr(unsigned slot, u32 msr)
213{
18863bdd
AK		 214 if (slot >= shared_msrs_global.nr)
215 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 216 shared_msrs_global.msrs[slot] = msr;
217 /* we need ensured the shared_msr_global have been updated */
218 smp_wmb();
18863bdd
AK		 219}
220EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
221
222static void kvm_shared_msr_cpu_online(void)
223{
224 unsigned i;
18863bdd
AK		 225
226 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 227 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 228}
229
d5696725 230void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 231{
013f6a5d
MT		 232 unsigned int cpu = smp_processor_id();
233 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 234
2bf78fa7 235 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 236 return;
2bf78fa7
SY		 237 smsr->values[slot].curr = value;
238 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 239 if (!smsr->registered) {
240 smsr->urn.on_user_return = kvm_on_user_return;
241 user_return_notifier_register(&smsr->urn);
242 smsr->registered = true;
243 }
244}
245EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
246
3548bab5
AK		 247static void drop_user_return_notifiers(void *ignore)
248{
013f6a5d
MT		 249 unsigned int cpu = smp_processor_id();
250 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 251
252 if (smsr->registered)
253 kvm_on_user_return(&smsr->urn);
254}
255
6866b83e
CO		 256u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
257{
8a5a87d9 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
58cb628d
JK		 262int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
263{
264 u64 old_state = vcpu->arch.apic_base &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 new_state = msr_info->data &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
269 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
270
271 if (!msr_info->host_initiated &&
272 ((msr_info->data & reserved_bits) != 0 ||
273 new_state == X2APIC_ENABLE ||
274 (new_state == MSR_IA32_APICBASE_ENABLE &&
275 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
276 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
277 old_state == 0)))
278 return 1;
279
280 kvm_lapic_set_base(vcpu, msr_info->data);
281 return 0;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_set_apic_base);
284
2605fc21 285asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 286{
287 /* Fault while not rebooting. We want the trace. */
288 BUG();
289}
290EXPORT_SYMBOL_GPL(kvm_spurious_fault);
291
3fd28fce
ED		 292#define EXCPT_BENIGN 0
293#define EXCPT_CONTRIBUTORY 1
294#define EXCPT_PF 2
295
296static int exception_class(int vector)
297{
298 switch (vector) {
299 case PF_VECTOR:
300 return EXCPT_PF;
301 case DE_VECTOR:
302 case TS_VECTOR:
303 case NP_VECTOR:
304 case SS_VECTOR:
305 case GP_VECTOR:
306 return EXCPT_CONTRIBUTORY;
307 default:
308 break;
309 }
310 return EXCPT_BENIGN;
311}
312
313static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 314 unsigned nr, bool has_error, u32 error_code,
315 bool reinject)
3fd28fce
ED		 316{
317 u32 prev_nr;
318 int class1, class2;
319
3842d135
AK		 320 kvm_make_request(KVM_REQ_EVENT, vcpu);
321
3fd28fce
ED		 322 if (!vcpu->arch.exception.pending) {
323 queue:
324 vcpu->arch.exception.pending = true;
325 vcpu->arch.exception.has_error_code = has_error;
326 vcpu->arch.exception.nr = nr;
327 vcpu->arch.exception.error_code = error_code;
3f0fd292 328 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 329 return;
330 }
331
332 /* to check exception */
333 prev_nr = vcpu->arch.exception.nr;
334 if (prev_nr == DF_VECTOR) {
335 /* triple fault -> shutdown */
a8eeb04a 336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 337 return;
338 }
339 class1 = exception_class(prev_nr);
340 class2 = exception_class(nr);
341 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
342 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
343 /* generate double fault per SDM Table 5-5 */
344 vcpu->arch.exception.pending = true;
345 vcpu->arch.exception.has_error_code = true;
346 vcpu->arch.exception.nr = DF_VECTOR;
347 vcpu->arch.exception.error_code = 0;
348 } else
349 /* replace previous exception with a new one in a hope
350 that instruction re-execution will regenerate lost
351 exception */
352 goto queue;
353}
354
298101da
AK		 355void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
356{
ce7ddec4 357 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 358}
359EXPORT_SYMBOL_GPL(kvm_queue_exception);
360
ce7ddec4
JR		 361void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
362{
363 kvm_multiple_exception(vcpu, nr, false, 0, true);
364}
365EXPORT_SYMBOL_GPL(kvm_requeue_exception);
366
db8fcefa 367void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 368{
db8fcefa
AP		 369 if (err)
370 kvm_inject_gp(vcpu, 0);
371 else
372 kvm_x86_ops->skip_emulated_instruction(vcpu);
373}
374EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 375
6389ee94 376void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 377{
378 ++vcpu->stat.pf_guest;
6389ee94
AK		 379 vcpu->arch.cr2 = fault->address;
380 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 381}
27d6c865 382EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 383
6389ee94 384void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 385{
6389ee94
AK		 386 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
387 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 388 else
6389ee94 389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 390}
391
3419ffc8
SY		 392void kvm_inject_nmi(struct kvm_vcpu *vcpu)
393{
7460fb4a
AK		 394 atomic_inc(&vcpu->arch.nmi_queued);
395 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 396}
397EXPORT_SYMBOL_GPL(kvm_inject_nmi);
398
298101da
AK		 399void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
400{
ce7ddec4 401 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 402}
403EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
404
ce7ddec4
JR		 405void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
406{
407 kvm_multiple_exception(vcpu, nr, true, error_code, true);
408}
409EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
410
0a79b009
AK		 411/*
412 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
413 * a #GP and return false.
414 */
415bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 416{
0a79b009
AK		 417 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
418 return true;
419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
420 return false;
298101da 421}
0a79b009 422EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 423
ec92fe44
JR		 424/*
425 * This function will be used to read from the physical memory of the currently
426 * running guest. The difference to kvm_read_guest_page is that this function
427 * can read from guest physical or from the guest's guest physical memory.
428 */
429int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
430 gfn_t ngfn, void *data, int offset, int len,
431 u32 access)
432{
433 gfn_t real_gfn;
434 gpa_t ngpa;
435
436 ngpa = gfn_to_gpa(ngfn);
437 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
438 if (real_gfn == UNMAPPED_GVA)
439 return -EFAULT;
440
441 real_gfn = gpa_to_gfn(real_gfn);
442
443 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
444}
445EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
446
3d06b8bf
JR		 447int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
448 void *data, int offset, int len, u32 access)
449{
450 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
451 data, offset, len, access);
452}
453
a03490ed
CO		 454/*
455 * Load the pae pdptrs. Return true is they are all valid.
456 */
ff03a073 457int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 458{
459 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
460 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
461 int i;
462 int ret;
ff03a073 463 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 464
ff03a073
JR		 465 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
466 offset * sizeof(u64), sizeof(pdpte),
467 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 468 if (ret < 0) {
469 ret = 0;
470 goto out;
471 }
472 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 473 if (is_present_gpte(pdpte[i]) &&
20c466b5 474 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 475 ret = 0;
476 goto out;
477 }
478 }
479 ret = 1;
480
ff03a073 481 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail);
484 __set_bit(VCPU_EXREG_PDPTR,
485 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 486out:
a03490ed
CO		 487
488 return ret;
489}
cc4b6871 490EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 491
d835dfec
AK		 492static bool pdptrs_changed(struct kvm_vcpu *vcpu)
493{
ff03a073 494 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 495 bool changed = true;
3d06b8bf
JR		 496 int offset;
497 gfn_t gfn;
d835dfec
AK		 498 int r;
499
500 if (is_long_mode(vcpu) || !is_pae(vcpu))
501 return false;
502
6de4f3ad
AK		 503 if (!test_bit(VCPU_EXREG_PDPTR,
504 (unsigned long *)&vcpu->arch.regs_avail))
505 return true;
506
9f8fe504
AK		 507 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
508 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 509 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
510 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 511 if (r < 0)
512 goto out;
ff03a073 513 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 514out:
d835dfec
AK		 515
516 return changed;
517}
518
49a9b07e 519int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 520{
aad82703
SY		 521 unsigned long old_cr0 = kvm_read_cr0(vcpu);
522 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
523 X86_CR0_CD | X86_CR0_NW;
524
f9a48e6a
AK		 525 cr0 |= X86_CR0_ET;
526
ab344828 527#ifdef CONFIG_X86_64
0f12244f
GN		 528 if (cr0 & 0xffffffff00000000UL)
529 return 1;
ab344828
GN		 530#endif
531
532 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 533
0f12244f
GN		 534 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
535 return 1;
a03490ed 536
0f12244f
GN		 537 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
538 return 1;
a03490ed
CO		 539
540 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
541#ifdef CONFIG_X86_64
f6801dff 542 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 543 int cs_db, cs_l;
544
0f12244f
GN		 545 if (!is_pae(vcpu))
546 return 1;
a03490ed 547 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 548 if (cs_l)
549 return 1;
a03490ed
CO		 550 } else
551#endif
ff03a073 552 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 553 kvm_read_cr3(vcpu)))
0f12244f 554 return 1;
a03490ed
CO		 555 }
556
ad756a16
MJ		 557 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
558 return 1;
559
a03490ed 560 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 561
d170c419 562 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 563 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 564 kvm_async_pf_hash_reset(vcpu);
565 }
e5f3f027 566
aad82703
SY		 567 if ((cr0 ^ old_cr0) & update_bits)
568 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 569 return 0;
570}
2d3ad1f4 571EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 572
2d3ad1f4 573void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 574{
49a9b07e 575 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 578
42bdf991
MT		 579static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
580{
581 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
582 !vcpu->guest_xcr0_loaded) {
583 /* kvm_set_xcr() also depends on this */
584 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
585 vcpu->guest_xcr0_loaded = 1;
586 }
587}
588
589static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
590{
591 if (vcpu->guest_xcr0_loaded) {
592 if (vcpu->arch.xcr0 != host_xcr0)
593 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
594 vcpu->guest_xcr0_loaded = 0;
595 }
596}
597
2acf923e
DC		 598int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599{
56c103ec
LJ		 600 u64 xcr0 = xcr;
601 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 602 u64 valid_bits;
2acf923e
DC		 603
604 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
605 if (index != XCR_XFEATURE_ENABLED_MASK)
606 return 1;
2acf923e
DC		 607 if (!(xcr0 & XSTATE_FP))
608 return 1;
609 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
610 return 1;
46c34cb0
PB		 611
612 /*
613 * Do not allow the guest to set bits that we do not support
614 * saving. However, xcr0 bit 0 is always set, even if the
615 * emulated CPU does not support XSAVE (see fx_init).
616 */
617 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
618 if (xcr0 & ~valid_bits)
2acf923e 619 return 1;
46c34cb0 620
390bd528
LJ		 621 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
622 return 1;
623
42bdf991 624 kvm_put_guest_xcr0(vcpu);
2acf923e 625 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 626
627 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
628 kvm_update_cpuid(vcpu);
2acf923e
DC		 629 return 0;
630}
631
632int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
633{
764bcbc5
Z		 634 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
635 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 636 kvm_inject_gp(vcpu, 0);
637 return 1;
638 }
639 return 0;
640}
641EXPORT_SYMBOL_GPL(kvm_set_xcr);
642
a83b29c6 643int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 644{
fc78f519 645 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 646 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
647 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 648 if (cr4 & CR4_RESERVED_BITS)
649 return 1;
a03490ed 650
2acf923e
DC		 651 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
652 return 1;
653
c68b734f
YW		 654 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
655 return 1;
656
97ec8c06
FW		 657 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
658 return 1;
659
afcbf13f 660 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 661 return 1;
662
a03490ed 663 if (is_long_mode(vcpu)) {
0f12244f
GN		 664 if (!(cr4 & X86_CR4_PAE))
665 return 1;
a2edf57f
AK		 666 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
667 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 668 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
0f12244f
GN		 670 return 1;
671
ad756a16
MJ		 672 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
673 if (!guest_cpuid_has_pcid(vcpu))
674 return 1;
675
676 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
677 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
678 return 1;
679 }
680
5e1746d6 681 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 682 return 1;
a03490ed 683
ad756a16
MJ		 684 if (((cr4 ^ old_cr4) & pdptr_bits) ||
685 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 686 kvm_mmu_reset_context(vcpu);
0f12244f 687
97ec8c06
FW		 688 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
689 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
690
2acf923e 691 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 692 kvm_update_cpuid(vcpu);
2acf923e 693
0f12244f
GN		 694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 697
2390218b 698int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 699{
9f8fe504 700 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 701 kvm_mmu_sync_roots(vcpu);
d835dfec 702 kvm_mmu_flush_tlb(vcpu);
0f12244f 703 return 0;
d835dfec
AK		 704 }
705
a03490ed 706 if (is_long_mode(vcpu)) {
d9f89b88
JK		 707 if (cr3 & CR3_L_MODE_RESERVED_BITS)
708 return 1;
709 } else if (is_pae(vcpu) && is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 711 return 1;
a03490ed 712
0f12244f 713 vcpu->arch.cr3 = cr3;
aff48baa 714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 715 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 716 return 0;
717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 719
eea1cff9 720int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 721{
0f12244f
GN		 722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
a03490ed
CO		 724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
ad312c7c 727 vcpu->arch.cr8 = cr8;
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 731
2d3ad1f4 732unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 733{
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
ad312c7c 737 return vcpu->arch.cr8;
a03490ed 738}
2d3ad1f4 739EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 740
73aaf249
JK		 741static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742{
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745}
746
c8639010
JK		 747static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748{
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 756 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
757 if (dr7 & DR7_BP_EN_MASK)
758 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 759}
760
338dbc97 761static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 762{
763 switch (dr) {
764 case 0 ... 3:
765 vcpu->arch.db[dr] = val;
766 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
767 vcpu->arch.eff_db[dr] = val;
768 break;
769 case 4:
338dbc97
GN		 770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
771 return 1; /* #UD */
020df079
GN		 772 /* fall through */
773 case 6:
338dbc97
GN		 774 if (val & 0xffffffff00000000ULL)
775 return -1; /* #GP */
020df079 776 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 777 kvm_update_dr6(vcpu);
020df079
GN		 778 break;
779 case 5:
338dbc97
GN		 780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 return 1; /* #UD */
020df079
GN		 782 /* fall through */
783 default: /* 7 */
338dbc97
GN		 784 if (val & 0xffffffff00000000ULL)
785 return -1; /* #GP */
020df079 786 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 787 kvm_update_dr7(vcpu);
020df079
GN		 788 break;
789 }
790
791 return 0;
792}
338dbc97
GN		 793
794int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
795{
796 int res;
797
798 res = __kvm_set_dr(vcpu, dr, val);
799 if (res > 0)
800 kvm_queue_exception(vcpu, UD_VECTOR);
801 else if (res < 0)
802 kvm_inject_gp(vcpu, 0);
803
804 return res;
805}
020df079
GN		 806EXPORT_SYMBOL_GPL(kvm_set_dr);
807
338dbc97 808static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 809{
810 switch (dr) {
811 case 0 ... 3:
812 *val = vcpu->arch.db[dr];
813 break;
814 case 4:
338dbc97 815 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 816 return 1;
020df079
GN		 817 /* fall through */
818 case 6:
73aaf249
JK		 819 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
820 *val = vcpu->arch.dr6;
821 else
822 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 823 break;
824 case 5:
338dbc97 825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 826 return 1;
020df079
GN		 827 /* fall through */
828 default: /* 7 */
829 *val = vcpu->arch.dr7;
830 break;
831 }
832
833 return 0;
834}
338dbc97
GN		 835
836int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
837{
838 if (_kvm_get_dr(vcpu, dr, val)) {
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 return 1;
841 }
842 return 0;
843}
020df079
GN		 844EXPORT_SYMBOL_GPL(kvm_get_dr);
845
022cd0e8
AK		 846bool kvm_rdpmc(struct kvm_vcpu *vcpu)
847{
848 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
849 u64 data;
850 int err;
851
852 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
853 if (err)
854 return err;
855 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
856 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
857 return err;
858}
859EXPORT_SYMBOL_GPL(kvm_rdpmc);
860
043405e1
CO		 861/*
862 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
863 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
864 *
865 * This list is modified at module load time to reflect the
e3267cbb
GC		 866 * capabilities of the host cpu. This capabilities test skips MSRs that are
867 * kvm-specific. Those are put in the beginning of the list.
043405e1 868 */
e3267cbb 869
e984097b 870#define KVM_SAVE_MSRS_BEGIN 12
043405e1 871static u32 msrs_to_save[] = {
e3267cbb 872 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 873 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 874 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 875 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 876 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 877 MSR_KVM_PV_EOI_EN,
043405e1 878 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 879 MSR_STAR,
043405e1
CO		 880#ifdef CONFIG_X86_64
881 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
882#endif
b3897a49 883 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 884 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 885};
886
887static unsigned num_msrs_to_save;
888
f1d24831 889static const u32 emulated_msrs[] = {
ba904635 890 MSR_IA32_TSC_ADJUST,
a3e06bbe 891 MSR_IA32_TSCDEADLINE,
043405e1 892 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 893 MSR_IA32_MCG_STATUS,
894 MSR_IA32_MCG_CTL,
043405e1
CO		 895};
896
384bb783 897bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 898{
b69e8cae 899 if (efer & efer_reserved_bits)
384bb783 900 return false;
15c4a640 901
1b2fd70c
AG		 902 if (efer & EFER_FFXSR) {
903 struct kvm_cpuid_entry2 *feat;
904
905 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 906 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 907 return false;
1b2fd70c
AG		 908 }
909
d8017474
AG		 910 if (efer & EFER_SVME) {
911 struct kvm_cpuid_entry2 *feat;
912
913 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 914 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 915 return false;
d8017474
AG		 916 }
917
384bb783
JK		 918 return true;
919}
920EXPORT_SYMBOL_GPL(kvm_valid_efer);
921
922static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
923{
924 u64 old_efer = vcpu->arch.efer;
925
926 if (!kvm_valid_efer(vcpu, efer))
927 return 1;
928
929 if (is_paging(vcpu)
930 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
931 return 1;
932
15c4a640 933 efer &= ~EFER_LMA;
f6801dff 934 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 935
a3d204e2
SY		 936 kvm_x86_ops->set_efer(vcpu, efer);
937
aad82703
SY		 938 /* Update reserved bits */
939 if ((efer ^ old_efer) & EFER_NX)
940 kvm_mmu_reset_context(vcpu);
941
b69e8cae 942 return 0;
15c4a640
CO		 943}
944
f2b4b7dd
JR		 945void kvm_enable_efer_bits(u64 mask)
946{
947 efer_reserved_bits &= ~mask;
948}
949EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
950
951
15c4a640
CO		 952/*
953 * Writes msr value into into the appropriate "register".
954 * Returns 0 on success, non-0 otherwise.
955 * Assumes vcpu_load() was already called.
956 */
8fe8ab46 957int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 958{
8fe8ab46 959 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 960}
961
313a3dc7
CO		 962/*
963 * Adapt set_msr() to msr_io()'s calling convention
964 */
965static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
966{
8fe8ab46
WA		 967 struct msr_data msr;
968
969 msr.data = *data;
970 msr.index = index;
971 msr.host_initiated = true;
972 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 973}
974
16e8d74d
MT		 975#ifdef CONFIG_X86_64
976struct pvclock_gtod_data {
977 seqcount_t seq;
978
979 struct { /* extract of a clocksource struct */
980 int vclock_mode;
981 cycle_t cycle_last;
982 cycle_t mask;
983 u32 mult;
984 u32 shift;
985 } clock;
986
987 /* open coded 'struct timespec' */
988 u64 monotonic_time_snsec;
989 time_t monotonic_time_sec;
990};
991
992static struct pvclock_gtod_data pvclock_gtod_data;
993
994static void update_pvclock_gtod(struct timekeeper *tk)
995{
996 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
997
998 write_seqcount_begin(&vdata->seq);
999
1000 /* copy pvclock gtod data */
1001 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1002 vdata->clock.cycle_last = tk->clock->cycle_last;
1003 vdata->clock.mask = tk->clock->mask;
1004 vdata->clock.mult = tk->mult;
1005 vdata->clock.shift = tk->shift;
1006
1007 vdata->monotonic_time_sec = tk->xtime_sec
1008 + tk->wall_to_monotonic.tv_sec;
1009 vdata->monotonic_time_snsec = tk->xtime_nsec
1010 + (tk->wall_to_monotonic.tv_nsec
1011 << tk->shift);
1012 while (vdata->monotonic_time_snsec >=
1013 (((u64)NSEC_PER_SEC) << tk->shift)) {
1014 vdata->monotonic_time_snsec -=
1015 ((u64)NSEC_PER_SEC) << tk->shift;
1016 vdata->monotonic_time_sec++;
1017 }
1018
1019 write_seqcount_end(&vdata->seq);
1020}
1021#endif
1022
1023
18068523
GOC		 1024static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1025{
9ed3c444
AK		 1026 int version;
1027 int r;
50d0a0f9 1028 struct pvclock_wall_clock wc;
923de3cf 1029 struct timespec boot;
18068523
GOC		 1030
1031 if (!wall_clock)
1032 return;
1033
9ed3c444
AK		 1034 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1035 if (r)
1036 return;
1037
1038 if (version & 1)
1039 ++version; /* first time write, random junk */
1040
1041 ++version;
18068523 1042
18068523
GOC		 1043 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1044
50d0a0f9
GH		 1045 /*
1046 * The guest calculates current wall clock time by adding
34c238a1 1047 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1048 * wall clock specified here. guest system time equals host
1049 * system time for us, thus we must fill in host boot time here.
1050 */
923de3cf 1051 getboottime(&boot);
50d0a0f9 1052
4b648665
BR		 1053 if (kvm->arch.kvmclock_offset) {
1054 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1055 boot = timespec_sub(boot, ts);
1056 }
50d0a0f9
GH		 1057 wc.sec = boot.tv_sec;
1058 wc.nsec = boot.tv_nsec;
1059 wc.version = version;
18068523
GOC		 1060
1061 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1062
1063 version++;
1064 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1065}
1066
50d0a0f9
GH		 1067static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1068{
1069 uint32_t quotient, remainder;
1070
1071 /* Don't try to replace with do_div(), this one calculates
1072 * "(dividend << 32) / divisor" */
1073 __asm__ ( "divl %4"
1074 : "=a" (quotient), "=d" (remainder)
1075 : "0" (0), "1" (dividend), "r" (divisor) );
1076 return quotient;
1077}
1078
5f4e3f88
ZA		 1079static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1080 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1081{
5f4e3f88 1082 uint64_t scaled64;
50d0a0f9
GH		 1083 int32_t shift = 0;
1084 uint64_t tps64;
1085 uint32_t tps32;
1086
5f4e3f88
ZA		 1087 tps64 = base_khz * 1000LL;
1088 scaled64 = scaled_khz * 1000LL;
50933623 1089 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1090 tps64 >>= 1;
1091 shift--;
1092 }
1093
1094 tps32 = (uint32_t)tps64;
50933623
JK		 1095 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1096 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1097 scaled64 >>= 1;
1098 else
1099 tps32 <<= 1;
50d0a0f9
GH		 1100 shift++;
1101 }
1102
5f4e3f88
ZA		 1103 *pshift = shift;
1104 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1105
5f4e3f88
ZA		 1106 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1107 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1108}
1109
759379dd
ZA		 1110static inline u64 get_kernel_ns(void)
1111{
1112 struct timespec ts;
1113
759379dd
ZA		 1114 ktime_get_ts(&ts);
1115 monotonic_to_bootbased(&ts);
1116 return timespec_to_ns(&ts);
50d0a0f9
GH		 1117}
1118
d828199e 1119#ifdef CONFIG_X86_64
16e8d74d 1120static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1121#endif
16e8d74d 1122
c8076604 1123static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1124unsigned long max_tsc_khz;
c8076604 1125
cc578287 1126static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1127{
cc578287
ZA		 1128 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1129 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1130}
1131
cc578287 1132static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1133{
cc578287
ZA		 1134 u64 v = (u64)khz * (1000000 + ppm);
1135 do_div(v, 1000000);
1136 return v;
1e993611
JR		 1137}
1138
cc578287 1139static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1140{
cc578287
ZA		 1141 u32 thresh_lo, thresh_hi;
1142 int use_scaling = 0;
217fc9cf 1143
03ba32ca
MT		 1144 /* tsc_khz can be zero if TSC calibration fails */
1145 if (this_tsc_khz == 0)
1146 return;
1147
c285545f
ZA		 1148 /* Compute a scale to convert nanoseconds in TSC cycles */
1149 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1150 &vcpu->arch.virtual_tsc_shift,
1151 &vcpu->arch.virtual_tsc_mult);
1152 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1153
1154 /*
1155 * Compute the variation in TSC rate which is acceptable
1156 * within the range of tolerance and decide if the
1157 * rate being applied is within that bounds of the hardware
1158 * rate. If so, no scaling or compensation need be done.
1159 */
1160 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1161 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1162 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1163 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1164 use_scaling = 1;
1165 }
1166 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1167}
1168
1169static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1170{
e26101b1 1171 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1172 vcpu->arch.virtual_tsc_mult,
1173 vcpu->arch.virtual_tsc_shift);
e26101b1 1174 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1175 return tsc;
1176}
1177
b48aa97e
MT		 1178void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1179{
1180#ifdef CONFIG_X86_64
1181 bool vcpus_matched;
1182 bool do_request = false;
1183 struct kvm_arch *ka = &vcpu->kvm->arch;
1184 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1185
1186 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1187 atomic_read(&vcpu->kvm->online_vcpus));
1188
1189 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1190 if (!ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (!vcpus_matched && ka->use_master_clock)
1194 do_request = 1;
1195
1196 if (do_request)
1197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1198
1199 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1200 atomic_read(&vcpu->kvm->online_vcpus),
1201 ka->use_master_clock, gtod->clock.vclock_mode);
1202#endif
1203}
1204
ba904635
WA		 1205static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1206{
1207 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1208 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1209}
1210
8fe8ab46 1211void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1212{
1213 struct kvm *kvm = vcpu->kvm;
f38e098f 1214 u64 offset, ns, elapsed;
99e3e30a 1215 unsigned long flags;
02626b6a 1216 s64 usdiff;
b48aa97e 1217 bool matched;
0d3da0d2 1218 bool already_matched;
8fe8ab46 1219 u64 data = msr->data;
99e3e30a 1220
038f8c11 1221 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1222 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1223 ns = get_kernel_ns();
f38e098f 1224 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1225
03ba32ca 1226 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1227 int faulted = 0;
1228
03ba32ca
MT		 1229 /* n.b - signed multiplication and division required */
1230 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1231#ifdef CONFIG_X86_64
03ba32ca 1232 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1233#else
03ba32ca 1234 /* do_div() only does unsigned */
8915aa27
MT		 1235 asm("1: idivl %[divisor]\n"
1236 "2: xor %%edx, %%edx\n"
1237 " movl $0, %[faulted]\n"
1238 "3:\n"
1239 ".section .fixup,\"ax\"\n"
1240 "4: movl $1, %[faulted]\n"
1241 " jmp 3b\n"
1242 ".previous\n"
1243
1244 _ASM_EXTABLE(1b, 4b)
1245
1246 : "=A"(usdiff), [faulted] "=r" (faulted)
1247 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1248
5d3cb0f6 1249#endif
03ba32ca
MT		 1250 do_div(elapsed, 1000);
1251 usdiff -= elapsed;
1252 if (usdiff < 0)
1253 usdiff = -usdiff;
8915aa27
MT		 1254
1255 /* idivl overflow => difference is larger than USEC_PER_SEC */
1256 if (faulted)
1257 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1258 } else
1259 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1260
1261 /*
5d3cb0f6
ZA		 1262 * Special case: TSC write with a small delta (1 second) of virtual
1263 * cycle time against real time is interpreted as an attempt to
1264 * synchronize the CPU.
1265 *
1266 * For a reliable TSC, we can match TSC offsets, and for an unstable
1267 * TSC, we add elapsed time in this computation. We could let the
1268 * compensation code attempt to catch up if we fall behind, but
1269 * it's better to try to match offsets from the beginning.
1270 */
02626b6a 1271 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1272 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1273 if (!check_tsc_unstable()) {
e26101b1 1274 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1275 pr_debug("kvm: matched tsc offset for %llu\n", data);
1276 } else {
857e4099 1277 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1278 data += delta;
1279 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1280 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1281 }
b48aa97e 1282 matched = true;
0d3da0d2 1283 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1284 } else {
1285 /*
1286 * We split periods of matched TSC writes into generations.
1287 * For each generation, we track the original measured
1288 * nanosecond time, offset, and write, so if TSCs are in
1289 * sync, we can match exact offset, and if not, we can match
4a969980 1290 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1291 *
1292 * These values are tracked in kvm->arch.cur_xxx variables.
1293 */
1294 kvm->arch.cur_tsc_generation++;
1295 kvm->arch.cur_tsc_nsec = ns;
1296 kvm->arch.cur_tsc_write = data;
1297 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1298 matched = false;
0d3da0d2 1299 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1300 kvm->arch.cur_tsc_generation, data);
f38e098f 1301 }
e26101b1
ZA		 1302
1303 /*
1304 * We also track th most recent recorded KHZ, write and time to
1305 * allow the matching interval to be extended at each write.
1306 */
f38e098f
ZA		 1307 kvm->arch.last_tsc_nsec = ns;
1308 kvm->arch.last_tsc_write = data;
5d3cb0f6 1309 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1310
b183aa58 1311 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1312
1313 /* Keep track of which generation this VCPU has synchronized to */
1314 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1315 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1316 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1317
ba904635
WA		 1318 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1319 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1320 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1321 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1322
1323 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1324 if (!matched) {
b48aa97e 1325 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1326 } else if (!already_matched) {
1327 kvm->arch.nr_vcpus_matched_tsc++;
1328 }
b48aa97e
MT		 1329
1330 kvm_track_tsc_matching(vcpu);
1331 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1332}
e26101b1 1333
99e3e30a
ZA		 1334EXPORT_SYMBOL_GPL(kvm_write_tsc);
1335
d828199e
MT		 1336#ifdef CONFIG_X86_64
1337
1338static cycle_t read_tsc(void)
1339{
1340 cycle_t ret;
1341 u64 last;
1342
1343 /*
1344 * Empirically, a fence (of type that depends on the CPU)
1345 * before rdtsc is enough to ensure that rdtsc is ordered
1346 * with respect to loads. The various CPU manuals are unclear
1347 * as to whether rdtsc can be reordered with later loads,
1348 * but no one has ever seen it happen.
1349 */
1350 rdtsc_barrier();
1351 ret = (cycle_t)vget_cycles();
1352
1353 last = pvclock_gtod_data.clock.cycle_last;
1354
1355 if (likely(ret >= last))
1356 return ret;
1357
1358 /*
1359 * GCC likes to generate cmov here, but this branch is extremely
1360 * predictable (it's just a funciton of time and the likely is
1361 * very likely) and there's a data dependence, so force GCC
1362 * to generate a branch instead. I don't barrier() because
1363 * we don't actually need a barrier, and if this function
1364 * ever gets inlined it will generate worse code.
1365 */
1366 asm volatile ("");
1367 return last;
1368}
1369
1370static inline u64 vgettsc(cycle_t *cycle_now)
1371{
1372 long v;
1373 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1374
1375 *cycle_now = read_tsc();
1376
1377 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1378 return v * gtod->clock.mult;
1379}
1380
1381static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1382{
1383 unsigned long seq;
1384 u64 ns;
1385 int mode;
1386 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1387
1388 ts->tv_nsec = 0;
1389 do {
1390 seq = read_seqcount_begin(&gtod->seq);
1391 mode = gtod->clock.vclock_mode;
1392 ts->tv_sec = gtod->monotonic_time_sec;
1393 ns = gtod->monotonic_time_snsec;
1394 ns += vgettsc(cycle_now);
1395 ns >>= gtod->clock.shift;
1396 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1397 timespec_add_ns(ts, ns);
1398
1399 return mode;
1400}
1401
1402/* returns true if host is using tsc clocksource */
1403static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1404{
1405 struct timespec ts;
1406
1407 /* checked again under seqlock below */
1408 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1409 return false;
1410
1411 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1412 return false;
1413
1414 monotonic_to_bootbased(&ts);
1415 *kernel_ns = timespec_to_ns(&ts);
1416
1417 return true;
1418}
1419#endif
1420
1421/*
1422 *
b48aa97e
MT		 1423 * Assuming a stable TSC across physical CPUS, and a stable TSC
1424 * across virtual CPUs, the following condition is possible.
1425 * Each numbered line represents an event visible to both
d828199e
MT		 1426 * CPUs at the next numbered event.
1427 *
1428 * "timespecX" represents host monotonic time. "tscX" represents
1429 * RDTSC value.
1430 *
1431 * VCPU0 on CPU0 | VCPU1 on CPU1
1432 *
1433 * 1. read timespec0,tsc0
1434 * 2. | timespec1 = timespec0 + N
1435 * | tsc1 = tsc0 + M
1436 * 3. transition to guest | transition to guest
1437 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1438 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1439 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1440 *
1441 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1442 *
1443 * - ret0 < ret1
1444 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1445 * ...
1446 * - 0 < N - M => M < N
1447 *
1448 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1449 * always the case (the difference between two distinct xtime instances
1450 * might be smaller then the difference between corresponding TSC reads,
1451 * when updating guest vcpus pvclock areas).
1452 *
1453 * To avoid that problem, do not allow visibility of distinct
1454 * system_timestamp/tsc_timestamp values simultaneously: use a master
1455 * copy of host monotonic time values. Update that master copy
1456 * in lockstep.
1457 *
b48aa97e 1458 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1459 *
1460 */
1461
1462static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1463{
1464#ifdef CONFIG_X86_64
1465 struct kvm_arch *ka = &kvm->arch;
1466 int vclock_mode;
b48aa97e
MT		 1467 bool host_tsc_clocksource, vcpus_matched;
1468
1469 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1470 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1471
1472 /*
1473 * If the host uses TSC clock, then passthrough TSC as stable
1474 * to the guest.
1475 */
b48aa97e 1476 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1477 &ka->master_kernel_ns,
1478 &ka->master_cycle_now);
1479
16a96021
MT		 1480 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1481 && !backwards_tsc_observed;
b48aa97e 1482
d828199e
MT		 1483 if (ka->use_master_clock)
1484 atomic_set(&kvm_guest_has_master_clock, 1);
1485
1486 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1487 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1488 vcpus_matched);
d828199e
MT		 1489#endif
1490}
1491
2e762ff7
MT		 1492static void kvm_gen_update_masterclock(struct kvm *kvm)
1493{
1494#ifdef CONFIG_X86_64
1495 int i;
1496 struct kvm_vcpu *vcpu;
1497 struct kvm_arch *ka = &kvm->arch;
1498
1499 spin_lock(&ka->pvclock_gtod_sync_lock);
1500 kvm_make_mclock_inprogress_request(kvm);
1501 /* no guest entries from this point */
1502 pvclock_update_vm_gtod_copy(kvm);
1503
1504 kvm_for_each_vcpu(i, vcpu, kvm)
1505 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1506
1507 /* guest entries allowed */
1508 kvm_for_each_vcpu(i, vcpu, kvm)
1509 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1510
1511 spin_unlock(&ka->pvclock_gtod_sync_lock);
1512#endif
1513}
1514
34c238a1 1515static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1516{
d828199e 1517 unsigned long flags, this_tsc_khz;
18068523 1518 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1519 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1520 s64 kernel_ns;
d828199e 1521 u64 tsc_timestamp, host_tsc;
0b79459b 1522 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1523 u8 pvclock_flags;
d828199e
MT		 1524 bool use_master_clock;
1525
1526 kernel_ns = 0;
1527 host_tsc = 0;
18068523 1528
d828199e
MT		 1529 /*
1530 * If the host uses TSC clock, then passthrough TSC as stable
1531 * to the guest.
1532 */
1533 spin_lock(&ka->pvclock_gtod_sync_lock);
1534 use_master_clock = ka->use_master_clock;
1535 if (use_master_clock) {
1536 host_tsc = ka->master_cycle_now;
1537 kernel_ns = ka->master_kernel_ns;
1538 }
1539 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1540
1541 /* Keep irq disabled to prevent changes to the clock */
1542 local_irq_save(flags);
1543 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1544 if (unlikely(this_tsc_khz == 0)) {
1545 local_irq_restore(flags);
1546 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1547 return 1;
1548 }
d828199e
MT		 1549 if (!use_master_clock) {
1550 host_tsc = native_read_tsc();
1551 kernel_ns = get_kernel_ns();
1552 }
1553
1554 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1555
c285545f
ZA		 1556 /*
1557 * We may have to catch up the TSC to match elapsed wall clock
1558 * time for two reasons, even if kvmclock is used.
1559 * 1) CPU could have been running below the maximum TSC rate
1560 * 2) Broken TSC compensation resets the base at each VCPU
1561 * entry to avoid unknown leaps of TSC even when running
1562 * again on the same CPU. This may cause apparent elapsed
1563 * time to disappear, and the guest to stand still or run
1564 * very slowly.
1565 */
1566 if (vcpu->tsc_catchup) {
1567 u64 tsc = compute_guest_tsc(v, kernel_ns);
1568 if (tsc > tsc_timestamp) {
f1e2b260 1569 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1570 tsc_timestamp = tsc;
1571 }
50d0a0f9
GH		 1572 }
1573
18068523
GOC		 1574 local_irq_restore(flags);
1575
0b79459b 1576 if (!vcpu->pv_time_enabled)
c285545f 1577 return 0;
18068523 1578
e48672fa 1579 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1580 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1581 &vcpu->hv_clock.tsc_shift,
1582 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1583 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1584 }
1585
1586 /* With all the info we got, fill in the values */
1d5f066e 1587 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1588 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1589 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1590
18068523
GOC		 1591 /*
1592 * The interface expects us to write an even number signaling that the
1593 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1594 * state, we just increase by 2 at the end.
18068523 1595 */
50d0a0f9 1596 vcpu->hv_clock.version += 2;
18068523 1597
0b79459b
AH		 1598 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1599 &guest_hv_clock, sizeof(guest_hv_clock))))
1600 return 0;
78c0337a
MT		 1601
1602 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1603 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1604
1605 if (vcpu->pvclock_set_guest_stopped_request) {
1606 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1607 vcpu->pvclock_set_guest_stopped_request = false;
1608 }
1609
d828199e
MT		 1610 /* If the host uses TSC clocksource, then it is stable */
1611 if (use_master_clock)
1612 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1613
78c0337a
MT		 1614 vcpu->hv_clock.flags = pvclock_flags;
1615
0b79459b
AH		 1616 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1617 &vcpu->hv_clock,
1618 sizeof(vcpu->hv_clock));
8cfdc000 1619 return 0;
c8076604
GH		 1620}
1621
0061d53d
MT		 1622/*
1623 * kvmclock updates which are isolated to a given vcpu, such as
1624 * vcpu->cpu migration, should not allow system_timestamp from
1625 * the rest of the vcpus to remain static. Otherwise ntp frequency
1626 * correction applies to one vcpu's system_timestamp but not
1627 * the others.
1628 *
1629 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1630 * We need to rate-limit these requests though, as they can
1631 * considerably slow guests that have a large number of vcpus.
1632 * The time for a remote vcpu to update its kvmclock is bound
1633 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1634 */
1635
7e44e449
AJ		 1636#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1637
1638static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1639{
1640 int i;
7e44e449
AJ		 1641 struct delayed_work *dwork = to_delayed_work(work);
1642 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1643 kvmclock_update_work);
1644 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1645 struct kvm_vcpu *vcpu;
1646
1647 kvm_for_each_vcpu(i, vcpu, kvm) {
1648 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1649 kvm_vcpu_kick(vcpu);
1650 }
1651}
1652
7e44e449
AJ		 1653static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1654{
1655 struct kvm *kvm = v->kvm;
1656
1657 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1658 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1659 KVMCLOCK_UPDATE_DELAY);
1660}
1661
332967a3
AJ		 1662#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1663
1664static void kvmclock_sync_fn(struct work_struct *work)
1665{
1666 struct delayed_work *dwork = to_delayed_work(work);
1667 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1668 kvmclock_sync_work);
1669 struct kvm *kvm = container_of(ka, struct kvm, arch);
1670
1671 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1672 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1673 KVMCLOCK_SYNC_PERIOD);
1674}
1675
9ba075a6
AK		 1676static bool msr_mtrr_valid(unsigned msr)
1677{
1678 switch (msr) {
1679 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1680 case MSR_MTRRfix64K_00000:
1681 case MSR_MTRRfix16K_80000:
1682 case MSR_MTRRfix16K_A0000:
1683 case MSR_MTRRfix4K_C0000:
1684 case MSR_MTRRfix4K_C8000:
1685 case MSR_MTRRfix4K_D0000:
1686 case MSR_MTRRfix4K_D8000:
1687 case MSR_MTRRfix4K_E0000:
1688 case MSR_MTRRfix4K_E8000:
1689 case MSR_MTRRfix4K_F0000:
1690 case MSR_MTRRfix4K_F8000:
1691 case MSR_MTRRdefType:
1692 case MSR_IA32_CR_PAT:
1693 return true;
1694 case 0x2f8:
1695 return true;
1696 }
1697 return false;
1698}
1699
d6289b93
MT		 1700static bool valid_pat_type(unsigned t)
1701{
1702 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1703}
1704
1705static bool valid_mtrr_type(unsigned t)
1706{
1707 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1708}
1709
1710static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1711{
1712 int i;
1713
1714 if (!msr_mtrr_valid(msr))
1715 return false;
1716
1717 if (msr == MSR_IA32_CR_PAT) {
1718 for (i = 0; i < 8; i++)
1719 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1720 return false;
1721 return true;
1722 } else if (msr == MSR_MTRRdefType) {
1723 if (data & ~0xcff)
1724 return false;
1725 return valid_mtrr_type(data & 0xff);
1726 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1727 for (i = 0; i < 8 ; i++)
1728 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1729 return false;
1730 return true;
1731 }
1732
1733 /* variable MTRRs */
1734 return valid_mtrr_type(data & 0xff);
1735}
1736
9ba075a6
AK		 1737static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1738{
0bed3b56
SY		 1739 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1740
d6289b93 1741 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1742 return 1;
1743
0bed3b56
SY		 1744 if (msr == MSR_MTRRdefType) {
1745 vcpu->arch.mtrr_state.def_type = data;
1746 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1747 } else if (msr == MSR_MTRRfix64K_00000)
1748 p[0] = data;
1749 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1750 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1751 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1752 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1753 else if (msr == MSR_IA32_CR_PAT)
1754 vcpu->arch.pat = data;
1755 else { /* Variable MTRRs */
1756 int idx, is_mtrr_mask;
1757 u64 *pt;
1758
1759 idx = (msr - 0x200) / 2;
1760 is_mtrr_mask = msr - 0x200 - 2 * idx;
1761 if (!is_mtrr_mask)
1762 pt =
1763 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1764 else
1765 pt =
1766 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1767 *pt = data;
1768 }
1769
1770 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1771 return 0;
1772}
15c4a640 1773
890ca9ae 1774static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1775{
890ca9ae
HY		 1776 u64 mcg_cap = vcpu->arch.mcg_cap;
1777 unsigned bank_num = mcg_cap & 0xff;
1778
15c4a640 1779 switch (msr) {
15c4a640 1780 case MSR_IA32_MCG_STATUS:
890ca9ae 1781 vcpu->arch.mcg_status = data;
15c4a640 1782 break;
c7ac679c 1783 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1784 if (!(mcg_cap & MCG_CTL_P))
1785 return 1;
1786 if (data != 0 && data != ~(u64)0)
1787 return -1;
1788 vcpu->arch.mcg_ctl = data;
1789 break;
1790 default:
1791 if (msr >= MSR_IA32_MC0_CTL &&
1792 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1793 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1794 /* only 0 or all 1s can be written to IA32_MCi_CTL
1795 * some Linux kernels though clear bit 10 in bank 4 to
1796 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1797 * this to avoid an uncatched #GP in the guest
1798 */
890ca9ae 1799 if ((offset & 0x3) == 0 &&
114be429 1800 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1801 return -1;
1802 vcpu->arch.mce_banks[offset] = data;
1803 break;
1804 }
1805 return 1;
1806 }
1807 return 0;
1808}
1809
ffde22ac
ES		 1810static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1811{
1812 struct kvm *kvm = vcpu->kvm;
1813 int lm = is_long_mode(vcpu);
1814 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1815 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1816 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1817 : kvm->arch.xen_hvm_config.blob_size_32;
1818 u32 page_num = data & ~PAGE_MASK;
1819 u64 page_addr = data & PAGE_MASK;
1820 u8 *page;
1821 int r;
1822
1823 r = -E2BIG;
1824 if (page_num >= blob_size)
1825 goto out;
1826 r = -ENOMEM;
ff5c2c03
SL		 1827 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1828 if (IS_ERR(page)) {
1829 r = PTR_ERR(page);
ffde22ac 1830 goto out;
ff5c2c03 1831 }
ffde22ac
ES		 1832 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1833 goto out_free;
1834 r = 0;
1835out_free:
1836 kfree(page);
1837out:
1838 return r;
1839}
1840
55cd8e5a
GN		 1841static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1842{
1843 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1844}
1845
1846static bool kvm_hv_msr_partition_wide(u32 msr)
1847{
1848 bool r = false;
1849 switch (msr) {
1850 case HV_X64_MSR_GUEST_OS_ID:
1851 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1852 case HV_X64_MSR_REFERENCE_TSC:
1853 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1854 r = true;
1855 break;
1856 }
1857
1858 return r;
1859}
1860
1861static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1862{
1863 struct kvm *kvm = vcpu->kvm;
1864
1865 switch (msr) {
1866 case HV_X64_MSR_GUEST_OS_ID:
1867 kvm->arch.hv_guest_os_id = data;
1868 /* setting guest os id to zero disables hypercall page */
1869 if (!kvm->arch.hv_guest_os_id)
1870 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1871 break;
1872 case HV_X64_MSR_HYPERCALL: {
1873 u64 gfn;
1874 unsigned long addr;
1875 u8 instructions[4];
1876
1877 /* if guest os id is not set hypercall should remain disabled */
1878 if (!kvm->arch.hv_guest_os_id)
1879 break;
1880 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1881 kvm->arch.hv_hypercall = data;
1882 break;
1883 }
1884 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1885 addr = gfn_to_hva(kvm, gfn);
1886 if (kvm_is_error_hva(addr))
1887 return 1;
1888 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1889 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1890 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1891 return 1;
1892 kvm->arch.hv_hypercall = data;
b94b64c9 1893 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1894 break;
1895 }
e984097b
VR		 1896 case HV_X64_MSR_REFERENCE_TSC: {
1897 u64 gfn;
1898 HV_REFERENCE_TSC_PAGE tsc_ref;
1899 memset(&tsc_ref, 0, sizeof(tsc_ref));
1900 kvm->arch.hv_tsc_page = data;
1901 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1902 break;
1903 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1904 if (kvm_write_guest(kvm, data,
1905 &tsc_ref, sizeof(tsc_ref)))
1906 return 1;
1907 mark_page_dirty(kvm, gfn);
1908 break;
1909 }
55cd8e5a 1910 default:
a737f256
CD		 1911 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1912 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1913 return 1;
1914 }
1915 return 0;
1916}
1917
1918static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1919{
10388a07
GN		 1920 switch (msr) {
1921 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1922 u64 gfn;
10388a07 1923 unsigned long addr;
55cd8e5a 1924
10388a07
GN		 1925 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1926 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1927 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1928 return 1;
10388a07
GN		 1929 break;
1930 }
b3af1e88
VR		 1931 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1932 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1933 if (kvm_is_error_hva(addr))
1934 return 1;
8b0cedff 1935 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1936 return 1;
1937 vcpu->arch.hv_vapic = data;
b3af1e88 1938 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1939 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1940 return 1;
10388a07
GN		 1941 break;
1942 }
1943 case HV_X64_MSR_EOI:
1944 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1945 case HV_X64_MSR_ICR:
1946 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1947 case HV_X64_MSR_TPR:
1948 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1949 default:
a737f256
CD		 1950 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1951 "data 0x%llx\n", msr, data);
10388a07
GN		 1952 return 1;
1953 }
1954
1955 return 0;
55cd8e5a
GN		 1956}
1957
344d9588
GN		 1958static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1959{
1960 gpa_t gpa = data & ~0x3f;
1961
4a969980 1962 /* Bits 2:5 are reserved, Should be zero */
6adba527 1963 if (data & 0x3c)
344d9588
GN		 1964 return 1;
1965
1966 vcpu->arch.apf.msr_val = data;
1967
1968 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1969 kvm_clear_async_pf_completion_queue(vcpu);
1970 kvm_async_pf_hash_reset(vcpu);
1971 return 0;
1972 }
1973
8f964525
AH		 1974 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1975 sizeof(u32)))
344d9588
GN		 1976 return 1;
1977
6adba527 1978 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1979 kvm_async_pf_wakeup_all(vcpu);
1980 return 0;
1981}
1982
12f9a48f
GC		 1983static void kvmclock_reset(struct kvm_vcpu *vcpu)
1984{
0b79459b 1985 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1986}
1987
c9aaa895
GC		 1988static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1989{
1990 u64 delta;
1991
1992 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1993 return;
1994
1995 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1996 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1997 vcpu->arch.st.accum_steal = delta;
1998}
1999
2000static void record_steal_time(struct kvm_vcpu *vcpu)
2001{
2002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2003 return;
2004
2005 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2006 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2007 return;
2008
2009 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2010 vcpu->arch.st.steal.version += 2;
2011 vcpu->arch.st.accum_steal = 0;
2012
2013 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2014 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2015}
2016
8fe8ab46 2017int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2018{
5753785f 2019 bool pr = false;
8fe8ab46
WA		 2020 u32 msr = msr_info->index;
2021 u64 data = msr_info->data;
5753785f 2022
15c4a640 2023 switch (msr) {
2e32b719
BP		 2024 case MSR_AMD64_NB_CFG:
2025 case MSR_IA32_UCODE_REV:
2026 case MSR_IA32_UCODE_WRITE:
2027 case MSR_VM_HSAVE_PA:
2028 case MSR_AMD64_PATCH_LOADER:
2029 case MSR_AMD64_BU_CFG2:
2030 break;
2031
15c4a640 2032 case MSR_EFER:
b69e8cae 2033 return set_efer(vcpu, data);
8f1589d9
AP		 2034 case MSR_K7_HWCR:
2035 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2036 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2037 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2038 if (data != 0) {
a737f256
CD		 2039 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2040 data);
8f1589d9
AP		 2041 return 1;
2042 }
15c4a640 2043 break;
f7c6d140
AP		 2044 case MSR_FAM10H_MMIO_CONF_BASE:
2045 if (data != 0) {
a737f256
CD		 2046 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2047 "0x%llx\n", data);
f7c6d140
AP		 2048 return 1;
2049 }
15c4a640 2050 break;
b5e2fec0
AG		 2051 case MSR_IA32_DEBUGCTLMSR:
2052 if (!data) {
2053 /* We support the non-activated case already */
2054 break;
2055 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2056 /* Values other than LBR and BTF are vendor-specific,
2057 thus reserved and should throw a #GP */
2058 return 1;
2059 }
a737f256
CD		 2060 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2061 __func__, data);
b5e2fec0 2062 break;
9ba075a6
AK		 2063 case 0x200 ... 0x2ff:
2064 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2065 case MSR_IA32_APICBASE:
58cb628d 2066 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2067 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2068 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2069 case MSR_IA32_TSCDEADLINE:
2070 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2071 break;
ba904635
WA		 2072 case MSR_IA32_TSC_ADJUST:
2073 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2074 if (!msr_info->host_initiated) {
2075 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2076 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2077 }
2078 vcpu->arch.ia32_tsc_adjust_msr = data;
2079 }
2080 break;
15c4a640 2081 case MSR_IA32_MISC_ENABLE:
ad312c7c 2082 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2083 break;
11c6bffa 2084 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2085 case MSR_KVM_WALL_CLOCK:
2086 vcpu->kvm->arch.wall_clock = data;
2087 kvm_write_wall_clock(vcpu->kvm, data);
2088 break;
11c6bffa 2089 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2090 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2091 u64 gpa_offset;
12f9a48f 2092 kvmclock_reset(vcpu);
18068523
GOC		 2093
2094 vcpu->arch.time = data;
0061d53d 2095 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2096
2097 /* we verify if the enable bit is set... */
2098 if (!(data & 1))
2099 break;
2100
0b79459b 2101 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2102
0b79459b 2103 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2104 &vcpu->arch.pv_time, data & ~1ULL,
2105 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2106 vcpu->arch.pv_time_enabled = false;
2107 else
2108 vcpu->arch.pv_time_enabled = true;
32cad84f 2109
18068523
GOC		 2110 break;
2111 }
344d9588
GN		 2112 case MSR_KVM_ASYNC_PF_EN:
2113 if (kvm_pv_enable_async_pf(vcpu, data))
2114 return 1;
2115 break;
c9aaa895
GC		 2116 case MSR_KVM_STEAL_TIME:
2117
2118 if (unlikely(!sched_info_on()))
2119 return 1;
2120
2121 if (data & KVM_STEAL_RESERVED_MASK)
2122 return 1;
2123
2124 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2125 data & KVM_STEAL_VALID_BITS,
2126 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2127 return 1;
2128
2129 vcpu->arch.st.msr_val = data;
2130
2131 if (!(data & KVM_MSR_ENABLED))
2132 break;
2133
2134 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2135
2136 preempt_disable();
2137 accumulate_steal_time(vcpu);
2138 preempt_enable();
2139
2140 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2141
2142 break;
ae7a2a3f
MT		 2143 case MSR_KVM_PV_EOI_EN:
2144 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2145 return 1;
2146 break;
c9aaa895 2147
890ca9ae
HY		 2148 case MSR_IA32_MCG_CTL:
2149 case MSR_IA32_MCG_STATUS:
2150 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2151 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2152
2153 /* Performance counters are not protected by a CPUID bit,
2154 * so we should check all of them in the generic path for the sake of
2155 * cross vendor migration.
2156 * Writing a zero into the event select MSRs disables them,
2157 * which we perfectly emulate ;-). Any other value should be at least
2158 * reported, some guests depend on them.
2159 */
71db6023
AP		 2160 case MSR_K7_EVNTSEL0:
2161 case MSR_K7_EVNTSEL1:
2162 case MSR_K7_EVNTSEL2:
2163 case MSR_K7_EVNTSEL3:
2164 if (data != 0)
a737f256
CD		 2165 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2166 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2167 break;
2168 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2169 * so we ignore writes to make it happy.
2170 */
71db6023
AP		 2171 case MSR_K7_PERFCTR0:
2172 case MSR_K7_PERFCTR1:
2173 case MSR_K7_PERFCTR2:
2174 case MSR_K7_PERFCTR3:
a737f256
CD		 2175 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2176 "0x%x data 0x%llx\n", msr, data);
71db6023 2177 break;
5753785f
GN		 2178 case MSR_P6_PERFCTR0:
2179 case MSR_P6_PERFCTR1:
2180 pr = true;
2181 case MSR_P6_EVNTSEL0:
2182 case MSR_P6_EVNTSEL1:
2183 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2184 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2185
2186 if (pr || data != 0)
a737f256
CD		 2187 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2188 "0x%x data 0x%llx\n", msr, data);
5753785f 2189 break;
84e0cefa
JS		 2190 case MSR_K7_CLK_CTL:
2191 /*
2192 * Ignore all writes to this no longer documented MSR.
2193 * Writes are only relevant for old K7 processors,
2194 * all pre-dating SVM, but a recommended workaround from
4a969980 2195 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2196 * affected processor models on the command line, hence
2197 * the need to ignore the workaround.
2198 */
2199 break;
55cd8e5a
GN		 2200 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2201 if (kvm_hv_msr_partition_wide(msr)) {
2202 int r;
2203 mutex_lock(&vcpu->kvm->lock);
2204 r = set_msr_hyperv_pw(vcpu, msr, data);
2205 mutex_unlock(&vcpu->kvm->lock);
2206 return r;
2207 } else
2208 return set_msr_hyperv(vcpu, msr, data);
2209 break;
91c9c3ed 2210 case MSR_IA32_BBL_CR_CTL3:
2211 /* Drop writes to this legacy MSR -- see rdmsr
2212 * counterpart for further detail.
2213 */
a737f256 2214 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2215 break;
2b036c6b
BO		 2216 case MSR_AMD64_OSVW_ID_LENGTH:
2217 if (!guest_cpuid_has_osvw(vcpu))
2218 return 1;
2219 vcpu->arch.osvw.length = data;
2220 break;
2221 case MSR_AMD64_OSVW_STATUS:
2222 if (!guest_cpuid_has_osvw(vcpu))
2223 return 1;
2224 vcpu->arch.osvw.status = data;
2225 break;
15c4a640 2226 default:
ffde22ac
ES		 2227 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2228 return xen_hvm_config(vcpu, data);
f5132b01 2229 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2230 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2231 if (!ignore_msrs) {
a737f256
CD		 2232 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2233 msr, data);
ed85c068
AP		 2234 return 1;
2235 } else {
a737f256
CD		 2236 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2237 msr, data);
ed85c068
AP		 2238 break;
2239 }
15c4a640
CO		 2240 }
2241 return 0;
2242}
2243EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2244
2245
2246/*
2247 * Reads an msr value (of 'msr_index') into 'pdata'.
2248 * Returns 0 on success, non-0 otherwise.
2249 * Assumes vcpu_load() was already called.
2250 */
2251int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2252{
2253 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2254}
2255
9ba075a6
AK		 2256static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2257{
0bed3b56
SY		 2258 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2259
9ba075a6
AK		 2260 if (!msr_mtrr_valid(msr))
2261 return 1;
2262
0bed3b56
SY		 2263 if (msr == MSR_MTRRdefType)
2264 *pdata = vcpu->arch.mtrr_state.def_type +
2265 (vcpu->arch.mtrr_state.enabled << 10);
2266 else if (msr == MSR_MTRRfix64K_00000)
2267 *pdata = p[0];
2268 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2269 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2270 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2271 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2272 else if (msr == MSR_IA32_CR_PAT)
2273 *pdata = vcpu->arch.pat;
2274 else { /* Variable MTRRs */
2275 int idx, is_mtrr_mask;
2276 u64 *pt;
2277
2278 idx = (msr - 0x200) / 2;
2279 is_mtrr_mask = msr - 0x200 - 2 * idx;
2280 if (!is_mtrr_mask)
2281 pt =
2282 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2283 else
2284 pt =
2285 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2286 *pdata = *pt;
2287 }
2288
9ba075a6
AK		 2289 return 0;
2290}
2291
890ca9ae 2292static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2293{
2294 u64 data;
890ca9ae
HY		 2295 u64 mcg_cap = vcpu->arch.mcg_cap;
2296 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2297
2298 switch (msr) {
15c4a640
CO		 2299 case MSR_IA32_P5_MC_ADDR:
2300 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2301 data = 0;
2302 break;
15c4a640 2303 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2304 data = vcpu->arch.mcg_cap;
2305 break;
c7ac679c 2306 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2307 if (!(mcg_cap & MCG_CTL_P))
2308 return 1;
2309 data = vcpu->arch.mcg_ctl;
2310 break;
2311 case MSR_IA32_MCG_STATUS:
2312 data = vcpu->arch.mcg_status;
2313 break;
2314 default:
2315 if (msr >= MSR_IA32_MC0_CTL &&
2316 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2317 u32 offset = msr - MSR_IA32_MC0_CTL;
2318 data = vcpu->arch.mce_banks[offset];
2319 break;
2320 }
2321 return 1;
2322 }
2323 *pdata = data;
2324 return 0;
2325}
2326
55cd8e5a
GN		 2327static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2328{
2329 u64 data = 0;
2330 struct kvm *kvm = vcpu->kvm;
2331
2332 switch (msr) {
2333 case HV_X64_MSR_GUEST_OS_ID:
2334 data = kvm->arch.hv_guest_os_id;
2335 break;
2336 case HV_X64_MSR_HYPERCALL:
2337 data = kvm->arch.hv_hypercall;
2338 break;
e984097b
VR		 2339 case HV_X64_MSR_TIME_REF_COUNT: {
2340 data =
2341 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2342 break;
2343 }
2344 case HV_X64_MSR_REFERENCE_TSC:
2345 data = kvm->arch.hv_tsc_page;
2346 break;
55cd8e5a 2347 default:
a737f256 2348 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2349 return 1;
2350 }
2351
2352 *pdata = data;
2353 return 0;
2354}
2355
2356static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2357{
2358 u64 data = 0;
2359
2360 switch (msr) {
2361 case HV_X64_MSR_VP_INDEX: {
2362 int r;
2363 struct kvm_vcpu *v;
684851a1
TY		 2364 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2365 if (v == vcpu) {
55cd8e5a 2366 data = r;
684851a1
TY		 2367 break;
2368 }
2369 }
55cd8e5a
GN		 2370 break;
2371 }
10388a07
GN		 2372 case HV_X64_MSR_EOI:
2373 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2374 case HV_X64_MSR_ICR:
2375 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2376 case HV_X64_MSR_TPR:
2377 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2378 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2379 data = vcpu->arch.hv_vapic;
2380 break;
55cd8e5a 2381 default:
a737f256 2382 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2383 return 1;
2384 }
2385 *pdata = data;
2386 return 0;
2387}
2388
890ca9ae
HY		 2389int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2390{
2391 u64 data;
2392
2393 switch (msr) {
890ca9ae 2394 case MSR_IA32_PLATFORM_ID:
15c4a640 2395 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2396 case MSR_IA32_DEBUGCTLMSR:
2397 case MSR_IA32_LASTBRANCHFROMIP:
2398 case MSR_IA32_LASTBRANCHTOIP:
2399 case MSR_IA32_LASTINTFROMIP:
2400 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2401 case MSR_K8_SYSCFG:
2402 case MSR_K7_HWCR:
61a6bd67 2403 case MSR_VM_HSAVE_PA:
9e699624 2404 case MSR_K7_EVNTSEL0:
1f3ee616 2405 case MSR_K7_PERFCTR0:
1fdbd48c 2406 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2407 case MSR_AMD64_NB_CFG:
f7c6d140 2408 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2409 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2410 data = 0;
2411 break;
5753785f
GN		 2412 case MSR_P6_PERFCTR0:
2413 case MSR_P6_PERFCTR1:
2414 case MSR_P6_EVNTSEL0:
2415 case MSR_P6_EVNTSEL1:
2416 if (kvm_pmu_msr(vcpu, msr))
2417 return kvm_pmu_get_msr(vcpu, msr, pdata);
2418 data = 0;
2419 break;
742bc670
MT		 2420 case MSR_IA32_UCODE_REV:
2421 data = 0x100000000ULL;
2422 break;
9ba075a6
AK		 2423 case MSR_MTRRcap:
2424 data = 0x500 | KVM_NR_VAR_MTRR;
2425 break;
2426 case 0x200 ... 0x2ff:
2427 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2428 case 0xcd: /* fsb frequency */
2429 data = 3;
2430 break;
7b914098
JS		 2431 /*
2432 * MSR_EBC_FREQUENCY_ID
2433 * Conservative value valid for even the basic CPU models.
2434 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2435 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2436 * and 266MHz for model 3, or 4. Set Core Clock
2437 * Frequency to System Bus Frequency Ratio to 1 (bits
2438 * 31:24) even though these are only valid for CPU
2439 * models > 2, however guests may end up dividing or
2440 * multiplying by zero otherwise.
2441 */
2442 case MSR_EBC_FREQUENCY_ID:
2443 data = 1 << 24;
2444 break;
15c4a640
CO		 2445 case MSR_IA32_APICBASE:
2446 data = kvm_get_apic_base(vcpu);
2447 break;
0105d1a5
GN		 2448 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2449 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2450 break;
a3e06bbe
LJ		 2451 case MSR_IA32_TSCDEADLINE:
2452 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2453 break;
ba904635
WA		 2454 case MSR_IA32_TSC_ADJUST:
2455 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2456 break;
15c4a640 2457 case MSR_IA32_MISC_ENABLE:
ad312c7c 2458 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2459 break;
847f0ad8
AG		 2460 case MSR_IA32_PERF_STATUS:
2461 /* TSC increment by tick */
2462 data = 1000ULL;
2463 /* CPU multiplier */
2464 data |= (((uint64_t)4ULL) << 40);
2465 break;
15c4a640 2466 case MSR_EFER:
f6801dff 2467 data = vcpu->arch.efer;
15c4a640 2468 break;
18068523 2469 case MSR_KVM_WALL_CLOCK:
11c6bffa 2470 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2471 data = vcpu->kvm->arch.wall_clock;
2472 break;
2473 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2474 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2475 data = vcpu->arch.time;
2476 break;
344d9588
GN		 2477 case MSR_KVM_ASYNC_PF_EN:
2478 data = vcpu->arch.apf.msr_val;
2479 break;
c9aaa895
GC		 2480 case MSR_KVM_STEAL_TIME:
2481 data = vcpu->arch.st.msr_val;
2482 break;
1d92128f
MT		 2483 case MSR_KVM_PV_EOI_EN:
2484 data = vcpu->arch.pv_eoi.msr_val;
2485 break;
890ca9ae
HY		 2486 case MSR_IA32_P5_MC_ADDR:
2487 case MSR_IA32_P5_MC_TYPE:
2488 case MSR_IA32_MCG_CAP:
2489 case MSR_IA32_MCG_CTL:
2490 case MSR_IA32_MCG_STATUS:
2491 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2492 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2493 case MSR_K7_CLK_CTL:
2494 /*
2495 * Provide expected ramp-up count for K7. All other
2496 * are set to zero, indicating minimum divisors for
2497 * every field.
2498 *
2499 * This prevents guest kernels on AMD host with CPU
2500 * type 6, model 8 and higher from exploding due to
2501 * the rdmsr failing.
2502 */
2503 data = 0x20000000;
2504 break;
55cd8e5a
GN		 2505 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2506 if (kvm_hv_msr_partition_wide(msr)) {
2507 int r;
2508 mutex_lock(&vcpu->kvm->lock);
2509 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2510 mutex_unlock(&vcpu->kvm->lock);
2511 return r;
2512 } else
2513 return get_msr_hyperv(vcpu, msr, pdata);
2514 break;
91c9c3ed 2515 case MSR_IA32_BBL_CR_CTL3:
2516 /* This legacy MSR exists but isn't fully documented in current
2517 * silicon. It is however accessed by winxp in very narrow
2518 * scenarios where it sets bit #19, itself documented as
2519 * a "reserved" bit. Best effort attempt to source coherent
2520 * read data here should the balance of the register be
2521 * interpreted by the guest:
2522 *
2523 * L2 cache control register 3: 64GB range, 256KB size,
2524 * enabled, latency 0x1, configured
2525 */
2526 data = 0xbe702111;
2527 break;
2b036c6b
BO		 2528 case MSR_AMD64_OSVW_ID_LENGTH:
2529 if (!guest_cpuid_has_osvw(vcpu))
2530 return 1;
2531 data = vcpu->arch.osvw.length;
2532 break;
2533 case MSR_AMD64_OSVW_STATUS:
2534 if (!guest_cpuid_has_osvw(vcpu))
2535 return 1;
2536 data = vcpu->arch.osvw.status;
2537 break;
15c4a640 2538 default:
f5132b01
GN		 2539 if (kvm_pmu_msr(vcpu, msr))
2540 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2541 if (!ignore_msrs) {
a737f256 2542 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2543 return 1;
2544 } else {
a737f256 2545 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2546 data = 0;
2547 }
2548 break;
15c4a640
CO		 2549 }
2550 *pdata = data;
2551 return 0;
2552}
2553EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2554
313a3dc7
CO		 2555/*
2556 * Read or write a bunch of msrs. All parameters are kernel addresses.
2557 *
2558 * @return number of msrs set successfully.
2559 */
2560static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2561 struct kvm_msr_entry *entries,
2562 int (*do_msr)(struct kvm_vcpu *vcpu,
2563 unsigned index, u64 *data))
2564{
f656ce01 2565 int i, idx;
313a3dc7 2566
f656ce01 2567 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2568 for (i = 0; i < msrs->nmsrs; ++i)
2569 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2570 break;
f656ce01 2571 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2572
313a3dc7
CO		 2573 return i;
2574}
2575
2576/*
2577 * Read or write a bunch of msrs. Parameters are user addresses.
2578 *
2579 * @return number of msrs set successfully.
2580 */
2581static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2582 int (*do_msr)(struct kvm_vcpu *vcpu,
2583 unsigned index, u64 *data),
2584 int writeback)
2585{
2586 struct kvm_msrs msrs;
2587 struct kvm_msr_entry *entries;
2588 int r, n;
2589 unsigned size;
2590
2591 r = -EFAULT;
2592 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2593 goto out;
2594
2595 r = -E2BIG;
2596 if (msrs.nmsrs >= MAX_IO_MSRS)
2597 goto out;
2598
313a3dc7 2599 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2600 entries = memdup_user(user_msrs->entries, size);
2601 if (IS_ERR(entries)) {
2602 r = PTR_ERR(entries);
313a3dc7 2603 goto out;
ff5c2c03 2604 }
313a3dc7
CO		 2605
2606 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2607 if (r < 0)
2608 goto out_free;
2609
2610 r = -EFAULT;
2611 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2612 goto out_free;
2613
2614 r = n;
2615
2616out_free:
7a73c028 2617 kfree(entries);
313a3dc7
CO		 2618out:
2619 return r;
2620}
2621
018d00d2
ZX		 2622int kvm_dev_ioctl_check_extension(long ext)
2623{
2624 int r;
2625
2626 switch (ext) {
2627 case KVM_CAP_IRQCHIP:
2628 case KVM_CAP_HLT:
2629 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2630 case KVM_CAP_SET_TSS_ADDR:
07716717 2631 case KVM_CAP_EXT_CPUID:
9c15bb1d 2632 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2633 case KVM_CAP_CLOCKSOURCE:
7837699f 2634 case KVM_CAP_PIT:
a28e4f5a 2635 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2636 case KVM_CAP_MP_STATE:
ed848624 2637 case KVM_CAP_SYNC_MMU:
a355c85c 2638 case KVM_CAP_USER_NMI:
52d939a0 2639 case KVM_CAP_REINJECT_CONTROL:
4925663a 2640 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2641 case KVM_CAP_IRQFD:
d34e6b17 2642 case KVM_CAP_IOEVENTFD:
f848a5a8 2643 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2644 case KVM_CAP_PIT2:
e9f42757 2645 case KVM_CAP_PIT_STATE2:
b927a3ce 2646 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2647 case KVM_CAP_XEN_HVM:
afbcf7ab 2648 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2649 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2650 case KVM_CAP_HYPERV:
10388a07 2651 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2652 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2653 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2654 case KVM_CAP_DEBUGREGS:
d2be1651 2655 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2656 case KVM_CAP_XSAVE:
344d9588 2657 case KVM_CAP_ASYNC_PF:
92a1f12d 2658 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2659 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2660 case KVM_CAP_READONLY_MEM:
5f66b620 2661 case KVM_CAP_HYPERV_TIME:
100943c5 2662 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2663#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2664 case KVM_CAP_ASSIGN_DEV_IRQ:
2665 case KVM_CAP_PCI_2_3:
2666#endif
018d00d2
ZX		 2667 r = 1;
2668 break;
542472b5
LV		 2669 case KVM_CAP_COALESCED_MMIO:
2670 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2671 break;
774ead3a
AK		 2672 case KVM_CAP_VAPIC:
2673 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2674 break;
f725230a 2675 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2676 r = KVM_SOFT_MAX_VCPUS;
2677 break;
2678 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2679 r = KVM_MAX_VCPUS;
2680 break;
a988b910 2681 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2682 r = KVM_USER_MEM_SLOTS;
a988b910 2683 break;
a68a6a72
MT		 2684 case KVM_CAP_PV_MMU: /* obsolete */
2685 r = 0;
2f333bcb 2686 break;
4cee4b72 2687#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2688 case KVM_CAP_IOMMU:
a1b60c1c 2689 r = iommu_present(&pci_bus_type);
62c476c7 2690 break;
4cee4b72 2691#endif
890ca9ae
HY		 2692 case KVM_CAP_MCE:
2693 r = KVM_MAX_MCE_BANKS;
2694 break;
2d5b5a66
SY		 2695 case KVM_CAP_XCRS:
2696 r = cpu_has_xsave;
2697 break;
92a1f12d
JR		 2698 case KVM_CAP_TSC_CONTROL:
2699 r = kvm_has_tsc_control;
2700 break;
4d25a066
JK		 2701 case KVM_CAP_TSC_DEADLINE_TIMER:
2702 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2703 break;
018d00d2
ZX		 2704 default:
2705 r = 0;
2706 break;
2707 }
2708 return r;
2709
2710}
2711
043405e1
CO		 2712long kvm_arch_dev_ioctl(struct file *filp,
2713 unsigned int ioctl, unsigned long arg)
2714{
2715 void __user *argp = (void __user *)arg;
2716 long r;
2717
2718 switch (ioctl) {
2719 case KVM_GET_MSR_INDEX_LIST: {
2720 struct kvm_msr_list __user *user_msr_list = argp;
2721 struct kvm_msr_list msr_list;
2722 unsigned n;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2726 goto out;
2727 n = msr_list.nmsrs;
2728 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2729 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2730 goto out;
2731 r = -E2BIG;
e125e7b6 2732 if (n < msr_list.nmsrs)
043405e1
CO		 2733 goto out;
2734 r = -EFAULT;
2735 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2736 num_msrs_to_save * sizeof(u32)))
2737 goto out;
e125e7b6 2738 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2739 &emulated_msrs,
2740 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2741 goto out;
2742 r = 0;
2743 break;
2744 }
9c15bb1d
BP		 2745 case KVM_GET_SUPPORTED_CPUID:
2746 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2747 struct kvm_cpuid2 __user *cpuid_arg = argp;
2748 struct kvm_cpuid2 cpuid;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2752 goto out;
9c15bb1d
BP		 2753
2754 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2755 ioctl);
674eea0f
AK		 2756 if (r)
2757 goto out;
2758
2759 r = -EFAULT;
2760 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2761 goto out;
2762 r = 0;
2763 break;
2764 }
890ca9ae
HY		 2765 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2766 u64 mce_cap;
2767
2768 mce_cap = KVM_MCE_CAP_SUPPORTED;
2769 r = -EFAULT;
2770 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2771 goto out;
2772 r = 0;
2773 break;
2774 }
043405e1
CO		 2775 default:
2776 r = -EINVAL;
2777 }
2778out:
2779 return r;
2780}
2781
f5f48ee1
SY		 2782static void wbinvd_ipi(void *garbage)
2783{
2784 wbinvd();
2785}
2786
2787static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2788{
e0f0bbc5 2789 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2790}
2791
313a3dc7
CO		 2792void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2793{
f5f48ee1
SY		 2794 /* Address WBINVD may be executed by guest */
2795 if (need_emulate_wbinvd(vcpu)) {
2796 if (kvm_x86_ops->has_wbinvd_exit())
2797 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2798 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2799 smp_call_function_single(vcpu->cpu,
2800 wbinvd_ipi, NULL, 1);
2801 }
2802
313a3dc7 2803 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2804
0dd6a6ed
ZA		 2805 /* Apply any externally detected TSC adjustments (due to suspend) */
2806 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2807 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2808 vcpu->arch.tsc_offset_adjustment = 0;
2809 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2810 }
8f6055cb 2811
48434c20 2812 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2813 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2814 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2815 if (tsc_delta < 0)
2816 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2817 if (check_tsc_unstable()) {
b183aa58
ZA		 2818 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2819 vcpu->arch.last_guest_tsc);
2820 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2821 vcpu->arch.tsc_catchup = 1;
c285545f 2822 }
d98d07ca
MT		 2823 /*
2824 * On a host with synchronized TSC, there is no need to update
2825 * kvmclock on vcpu->cpu migration
2826 */
2827 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2828 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2829 if (vcpu->cpu != cpu)
2830 kvm_migrate_timers(vcpu);
e48672fa 2831 vcpu->cpu = cpu;
6b7d7e76 2832 }
c9aaa895
GC		 2833
2834 accumulate_steal_time(vcpu);
2835 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2836}
2837
2838void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2839{
02daab21 2840 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2841 kvm_put_guest_fpu(vcpu);
6f526ec5 2842 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2843}
2844
313a3dc7
CO		 2845static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2846 struct kvm_lapic_state *s)
2847{
5a71785d 2848 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2849 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2850
2851 return 0;
2852}
2853
2854static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2855 struct kvm_lapic_state *s)
2856{
64eb0620 2857 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2858 update_cr8_intercept(vcpu);
313a3dc7
CO		 2859
2860 return 0;
2861}
2862
f77bc6a4
ZX		 2863static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2864 struct kvm_interrupt *irq)
2865{
02cdb50f 2866 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2867 return -EINVAL;
2868 if (irqchip_in_kernel(vcpu->kvm))
2869 return -ENXIO;
f77bc6a4 2870
66fd3f7f 2871 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2872 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2873
f77bc6a4
ZX		 2874 return 0;
2875}
2876
c4abb7c9
JK		 2877static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2878{
c4abb7c9 2879 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2880
2881 return 0;
2882}
2883
b209749f
AK		 2884static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2885 struct kvm_tpr_access_ctl *tac)
2886{
2887 if (tac->flags)
2888 return -EINVAL;
2889 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2890 return 0;
2891}
2892
890ca9ae
HY		 2893static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2894 u64 mcg_cap)
2895{
2896 int r;
2897 unsigned bank_num = mcg_cap & 0xff, bank;
2898
2899 r = -EINVAL;
a9e38c3e 2900 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2901 goto out;
2902 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2903 goto out;
2904 r = 0;
2905 vcpu->arch.mcg_cap = mcg_cap;
2906 /* Init IA32_MCG_CTL to all 1s */
2907 if (mcg_cap & MCG_CTL_P)
2908 vcpu->arch.mcg_ctl = ~(u64)0;
2909 /* Init IA32_MCi_CTL to all 1s */
2910 for (bank = 0; bank < bank_num; bank++)
2911 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2912out:
2913 return r;
2914}
2915
2916static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2917 struct kvm_x86_mce *mce)
2918{
2919 u64 mcg_cap = vcpu->arch.mcg_cap;
2920 unsigned bank_num = mcg_cap & 0xff;
2921 u64 *banks = vcpu->arch.mce_banks;
2922
2923 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2924 return -EINVAL;
2925 /*
2926 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2927 * reporting is disabled
2928 */
2929 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2930 vcpu->arch.mcg_ctl != ~(u64)0)
2931 return 0;
2932 banks += 4 * mce->bank;
2933 /*
2934 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2935 * reporting is disabled for the bank
2936 */
2937 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2938 return 0;
2939 if (mce->status & MCI_STATUS_UC) {
2940 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2941 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2942 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2943 return 0;
2944 }
2945 if (banks[1] & MCI_STATUS_VAL)
2946 mce->status |= MCI_STATUS_OVER;
2947 banks[2] = mce->addr;
2948 banks[3] = mce->misc;
2949 vcpu->arch.mcg_status = mce->mcg_status;
2950 banks[1] = mce->status;
2951 kvm_queue_exception(vcpu, MC_VECTOR);
2952 } else if (!(banks[1] & MCI_STATUS_VAL)
2953 || !(banks[1] & MCI_STATUS_UC)) {
2954 if (banks[1] & MCI_STATUS_VAL)
2955 mce->status |= MCI_STATUS_OVER;
2956 banks[2] = mce->addr;
2957 banks[3] = mce->misc;
2958 banks[1] = mce->status;
2959 } else
2960 banks[1] |= MCI_STATUS_OVER;
2961 return 0;
2962}
2963
3cfc3092
JK		 2964static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2965 struct kvm_vcpu_events *events)
2966{
7460fb4a 2967 process_nmi(vcpu);
03b82a30
JK		 2968 events->exception.injected =
2969 vcpu->arch.exception.pending &&
2970 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2971 events->exception.nr = vcpu->arch.exception.nr;
2972 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2973 events->exception.pad = 0;
3cfc3092
JK		 2974 events->exception.error_code = vcpu->arch.exception.error_code;
2975
03b82a30
JK		 2976 events->interrupt.injected =
2977 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2978 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2979 events->interrupt.soft = 0;
48005f64
JK		 2980 events->interrupt.shadow =
2981 kvm_x86_ops->get_interrupt_shadow(vcpu,
2982 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2983
2984 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2985 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2986 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2987 events->nmi.pad = 0;
3cfc3092 2988
66450a21 2989 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2990
dab4b911 2991 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2992 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2993 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2994}
2995
2996static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2997 struct kvm_vcpu_events *events)
2998{
dab4b911 2999 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3000 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3001 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3002 return -EINVAL;
3003
7460fb4a 3004 process_nmi(vcpu);
3cfc3092
JK		 3005 vcpu->arch.exception.pending = events->exception.injected;
3006 vcpu->arch.exception.nr = events->exception.nr;
3007 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3008 vcpu->arch.exception.error_code = events->exception.error_code;
3009
3010 vcpu->arch.interrupt.pending = events->interrupt.injected;
3011 vcpu->arch.interrupt.nr = events->interrupt.nr;
3012 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3013 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3014 kvm_x86_ops->set_interrupt_shadow(vcpu,
3015 events->interrupt.shadow);
3cfc3092
JK		 3016
3017 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3018 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3019 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3020 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3021
66450a21
JK		 3022 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3023 kvm_vcpu_has_lapic(vcpu))
3024 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3025
3842d135
AK		 3026 kvm_make_request(KVM_REQ_EVENT, vcpu);
3027
3cfc3092
JK		 3028 return 0;
3029}
3030
a1efbe77
JK		 3031static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3032 struct kvm_debugregs *dbgregs)
3033{
73aaf249
JK		 3034 unsigned long val;
3035
a1efbe77 3036 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3037 _kvm_get_dr(vcpu, 6, &val);
3038 dbgregs->dr6 = val;
a1efbe77
JK		 3039 dbgregs->dr7 = vcpu->arch.dr7;
3040 dbgregs->flags = 0;
97e69aa6 3041 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3042}
3043
3044static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3045 struct kvm_debugregs *dbgregs)
3046{
3047 if (dbgregs->flags)
3048 return -EINVAL;
3049
a1efbe77
JK		 3050 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3051 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3052 kvm_update_dr6(vcpu);
a1efbe77 3053 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3054 kvm_update_dr7(vcpu);
a1efbe77 3055
a1efbe77
JK		 3056 return 0;
3057}
3058
2d5b5a66
SY		 3059static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3060 struct kvm_xsave *guest_xsave)
3061{
4344ee98 3062 if (cpu_has_xsave) {
2d5b5a66
SY		 3063 memcpy(guest_xsave->region,
3064 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3065 vcpu->arch.guest_xstate_size);
3066 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3067 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3068 } else {
2d5b5a66
SY		 3069 memcpy(guest_xsave->region,
3070 &vcpu->arch.guest_fpu.state->fxsave,
3071 sizeof(struct i387_fxsave_struct));
3072 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3073 XSTATE_FPSSE;
3074 }
3075}
3076
3077static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3078 struct kvm_xsave *guest_xsave)
3079{
3080 u64 xstate_bv =
3081 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3082
d7876f1b
PB		 3083 if (cpu_has_xsave) {
3084 /*
3085 * Here we allow setting states that are not present in
3086 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3087 * with old userspace.
3088 */
4ff41732 3089 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3090 return -EINVAL;
2d5b5a66 3091 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3092 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3093 } else {
2d5b5a66
SY		 3094 if (xstate_bv & ~XSTATE_FPSSE)
3095 return -EINVAL;
3096 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3097 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3098 }
3099 return 0;
3100}
3101
3102static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3103 struct kvm_xcrs *guest_xcrs)
3104{
3105 if (!cpu_has_xsave) {
3106 guest_xcrs->nr_xcrs = 0;
3107 return;
3108 }
3109
3110 guest_xcrs->nr_xcrs = 1;
3111 guest_xcrs->flags = 0;
3112 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3113 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3114}
3115
3116static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3117 struct kvm_xcrs *guest_xcrs)
3118{
3119 int i, r = 0;
3120
3121 if (!cpu_has_xsave)
3122 return -EINVAL;
3123
3124 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3125 return -EINVAL;
3126
3127 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3128 /* Only support XCR0 currently */
c67a04cb 3129 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3130 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3131 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3132 break;
3133 }
3134 if (r)
3135 r = -EINVAL;
3136 return r;
3137}
3138
1c0b28c2
EM		 3139/*
3140 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3141 * stopped by the hypervisor. This function will be called from the host only.
3142 * EINVAL is returned when the host attempts to set the flag for a guest that
3143 * does not support pv clocks.
3144 */
3145static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3146{
0b79459b 3147 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3148 return -EINVAL;
51d59c6b 3149 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3150 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3151 return 0;
3152}
3153
313a3dc7
CO		 3154long kvm_arch_vcpu_ioctl(struct file *filp,
3155 unsigned int ioctl, unsigned long arg)
3156{
3157 struct kvm_vcpu *vcpu = filp->private_data;
3158 void __user *argp = (void __user *)arg;
3159 int r;
d1ac91d8
AK		 3160 union {
3161 struct kvm_lapic_state *lapic;
3162 struct kvm_xsave *xsave;
3163 struct kvm_xcrs *xcrs;
3164 void *buffer;
3165 } u;
3166
3167 u.buffer = NULL;
313a3dc7
CO		 3168 switch (ioctl) {
3169 case KVM_GET_LAPIC: {
2204ae3c
MT		 3170 r = -EINVAL;
3171 if (!vcpu->arch.apic)
3172 goto out;
d1ac91d8 3173 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3174
b772ff36 3175 r = -ENOMEM;
d1ac91d8 3176 if (!u.lapic)
b772ff36 3177 goto out;
d1ac91d8 3178 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3179 if (r)
3180 goto out;
3181 r = -EFAULT;
d1ac91d8 3182 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3183 goto out;
3184 r = 0;
3185 break;
3186 }
3187 case KVM_SET_LAPIC: {
2204ae3c
MT		 3188 r = -EINVAL;
3189 if (!vcpu->arch.apic)
3190 goto out;
ff5c2c03 3191 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3192 if (IS_ERR(u.lapic))
3193 return PTR_ERR(u.lapic);
ff5c2c03 3194
d1ac91d8 3195 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3196 break;
3197 }
f77bc6a4
ZX		 3198 case KVM_INTERRUPT: {
3199 struct kvm_interrupt irq;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&irq, argp, sizeof irq))
3203 goto out;
3204 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3205 break;
3206 }
c4abb7c9
JK		 3207 case KVM_NMI: {
3208 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3209 break;
3210 }
313a3dc7
CO		 3211 case KVM_SET_CPUID: {
3212 struct kvm_cpuid __user *cpuid_arg = argp;
3213 struct kvm_cpuid cpuid;
3214
3215 r = -EFAULT;
3216 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3217 goto out;
3218 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3219 break;
3220 }
07716717
DK		 3221 case KVM_SET_CPUID2: {
3222 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223 struct kvm_cpuid2 cpuid;
3224
3225 r = -EFAULT;
3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227 goto out;
3228 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3229 cpuid_arg->entries);
07716717
DK		 3230 break;
3231 }
3232 case KVM_GET_CPUID2: {
3233 struct kvm_cpuid2 __user *cpuid_arg = argp;
3234 struct kvm_cpuid2 cpuid;
3235
3236 r = -EFAULT;
3237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3238 goto out;
3239 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3240 cpuid_arg->entries);
07716717
DK		 3241 if (r)
3242 goto out;
3243 r = -EFAULT;
3244 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3245 goto out;
3246 r = 0;
3247 break;
3248 }
313a3dc7
CO		 3249 case KVM_GET_MSRS:
3250 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3251 break;
3252 case KVM_SET_MSRS:
3253 r = msr_io(vcpu, argp, do_set_msr, 0);
3254 break;
b209749f
AK		 3255 case KVM_TPR_ACCESS_REPORTING: {
3256 struct kvm_tpr_access_ctl tac;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&tac, argp, sizeof tac))
3260 goto out;
3261 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3262 if (r)
3263 goto out;
3264 r = -EFAULT;
3265 if (copy_to_user(argp, &tac, sizeof tac))
3266 goto out;
3267 r = 0;
3268 break;
3269 };
b93463aa
AK		 3270 case KVM_SET_VAPIC_ADDR: {
3271 struct kvm_vapic_addr va;
3272
3273 r = -EINVAL;
3274 if (!irqchip_in_kernel(vcpu->kvm))
3275 goto out;
3276 r = -EFAULT;
3277 if (copy_from_user(&va, argp, sizeof va))
3278 goto out;
fda4e2e8 3279 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3280 break;
3281 }
890ca9ae
HY		 3282 case KVM_X86_SETUP_MCE: {
3283 u64 mcg_cap;
3284
3285 r = -EFAULT;
3286 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3287 goto out;
3288 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3289 break;
3290 }
3291 case KVM_X86_SET_MCE: {
3292 struct kvm_x86_mce mce;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&mce, argp, sizeof mce))
3296 goto out;
3297 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3298 break;
3299 }
3cfc3092
JK		 3300 case KVM_GET_VCPU_EVENTS: {
3301 struct kvm_vcpu_events events;
3302
3303 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3304
3305 r = -EFAULT;
3306 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3307 break;
3308 r = 0;
3309 break;
3310 }
3311 case KVM_SET_VCPU_EVENTS: {
3312 struct kvm_vcpu_events events;
3313
3314 r = -EFAULT;
3315 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3316 break;
3317
3318 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3319 break;
3320 }
a1efbe77
JK		 3321 case KVM_GET_DEBUGREGS: {
3322 struct kvm_debugregs dbgregs;
3323
3324 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3325
3326 r = -EFAULT;
3327 if (copy_to_user(argp, &dbgregs,
3328 sizeof(struct kvm_debugregs)))
3329 break;
3330 r = 0;
3331 break;
3332 }
3333 case KVM_SET_DEBUGREGS: {
3334 struct kvm_debugregs dbgregs;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&dbgregs, argp,
3338 sizeof(struct kvm_debugregs)))
3339 break;
3340
3341 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3342 break;
3343 }
2d5b5a66 3344 case KVM_GET_XSAVE: {
d1ac91d8 3345 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3346 r = -ENOMEM;
d1ac91d8 3347 if (!u.xsave)
2d5b5a66
SY		 3348 break;
3349
d1ac91d8 3350 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3351
3352 r = -EFAULT;
d1ac91d8 3353 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3354 break;
3355 r = 0;
3356 break;
3357 }
3358 case KVM_SET_XSAVE: {
ff5c2c03 3359 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3360 if (IS_ERR(u.xsave))
3361 return PTR_ERR(u.xsave);
2d5b5a66 3362
d1ac91d8 3363 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3364 break;
3365 }
3366 case KVM_GET_XCRS: {
d1ac91d8 3367 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3368 r = -ENOMEM;
d1ac91d8 3369 if (!u.xcrs)
2d5b5a66
SY		 3370 break;
3371
d1ac91d8 3372 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3373
3374 r = -EFAULT;
d1ac91d8 3375 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3376 sizeof(struct kvm_xcrs)))
3377 break;
3378 r = 0;
3379 break;
3380 }
3381 case KVM_SET_XCRS: {
ff5c2c03 3382 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3383 if (IS_ERR(u.xcrs))
3384 return PTR_ERR(u.xcrs);
2d5b5a66 3385
d1ac91d8 3386 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3387 break;
3388 }
92a1f12d
JR		 3389 case KVM_SET_TSC_KHZ: {
3390 u32 user_tsc_khz;
3391
3392 r = -EINVAL;
92a1f12d
JR		 3393 user_tsc_khz = (u32)arg;
3394
3395 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3396 goto out;
3397
cc578287
ZA		 3398 if (user_tsc_khz == 0)
3399 user_tsc_khz = tsc_khz;
3400
3401 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3402
3403 r = 0;
3404 goto out;
3405 }
3406 case KVM_GET_TSC_KHZ: {
cc578287 3407 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3408 goto out;
3409 }
1c0b28c2
EM		 3410 case KVM_KVMCLOCK_CTRL: {
3411 r = kvm_set_guest_paused(vcpu);
3412 goto out;
3413 }
313a3dc7
CO		 3414 default:
3415 r = -EINVAL;
3416 }
3417out:
d1ac91d8 3418 kfree(u.buffer);
313a3dc7
CO		 3419 return r;
3420}
3421
5b1c1493
CO		 3422int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3423{
3424 return VM_FAULT_SIGBUS;
3425}
3426
1fe779f8
CO		 3427static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3428{
3429 int ret;
3430
3431 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3432 return -EINVAL;
1fe779f8
CO		 3433 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3434 return ret;
3435}
3436
b927a3ce
SY		 3437static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3438 u64 ident_addr)
3439{
3440 kvm->arch.ept_identity_map_addr = ident_addr;
3441 return 0;
3442}
3443
1fe779f8
CO		 3444static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3445 u32 kvm_nr_mmu_pages)
3446{
3447 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3448 return -EINVAL;
3449
79fac95e 3450 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3451
3452 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3453 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3454
79fac95e 3455 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3456 return 0;
3457}
3458
3459static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3460{
39de71ec 3461 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3462}
3463
1fe779f8
CO		 3464static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3465{
3466 int r;
3467
3468 r = 0;
3469 switch (chip->chip_id) {
3470 case KVM_IRQCHIP_PIC_MASTER:
3471 memcpy(&chip->chip.pic,
3472 &pic_irqchip(kvm)->pics[0],
3473 sizeof(struct kvm_pic_state));
3474 break;
3475 case KVM_IRQCHIP_PIC_SLAVE:
3476 memcpy(&chip->chip.pic,
3477 &pic_irqchip(kvm)->pics[1],
3478 sizeof(struct kvm_pic_state));
3479 break;
3480 case KVM_IRQCHIP_IOAPIC:
eba0226b 3481 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3482 break;
3483 default:
3484 r = -EINVAL;
3485 break;
3486 }
3487 return r;
3488}
3489
3490static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3491{
3492 int r;
3493
3494 r = 0;
3495 switch (chip->chip_id) {
3496 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3497 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3498 memcpy(&pic_irqchip(kvm)->pics[0],
3499 &chip->chip.pic,
3500 sizeof(struct kvm_pic_state));
f4f51050 3501 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 break;
3503 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3504 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3505 memcpy(&pic_irqchip(kvm)->pics[1],
3506 &chip->chip.pic,
3507 sizeof(struct kvm_pic_state));
f4f51050 3508 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3509 break;
3510 case KVM_IRQCHIP_IOAPIC:
eba0226b 3511 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3512 break;
3513 default:
3514 r = -EINVAL;
3515 break;
3516 }
3517 kvm_pic_update_irq(pic_irqchip(kvm));
3518 return r;
3519}
3520
e0f63cb9
SY		 3521static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3522{
3523 int r = 0;
3524
894a9c55 3525 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3526 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3527 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3528 return r;
3529}
3530
3531static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3532{
3533 int r = 0;
3534
894a9c55 3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3536 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3537 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3538 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3539 return r;
3540}
3541
3542static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3543{
3544 int r = 0;
3545
3546 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3547 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3548 sizeof(ps->channels));
3549 ps->flags = kvm->arch.vpit->pit_state.flags;
3550 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3551 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3552 return r;
3553}
3554
3555static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3556{
3557 int r = 0, start = 0;
3558 u32 prev_legacy, cur_legacy;
3559 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3560 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3561 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3562 if (!prev_legacy && cur_legacy)
3563 start = 1;
3564 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3565 sizeof(kvm->arch.vpit->pit_state.channels));
3566 kvm->arch.vpit->pit_state.flags = ps->flags;
3567 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3569 return r;
3570}
3571
52d939a0
MT		 3572static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3573 struct kvm_reinject_control *control)
3574{
3575 if (!kvm->arch.vpit)
3576 return -ENXIO;
894a9c55 3577 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3578 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3579 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3580 return 0;
3581}
3582
95d4c16c 3583/**
60c34612
TY		 3584 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3585 * @kvm: kvm instance
3586 * @log: slot id and address to which we copy the log
95d4c16c 3587 *
60c34612
TY		 3588 * We need to keep it in mind that VCPU threads can write to the bitmap
3589 * concurrently. So, to avoid losing data, we keep the following order for
3590 * each bit:
95d4c16c 3591 *
60c34612
TY		 3592 * 1. Take a snapshot of the bit and clear it if needed.
3593 * 2. Write protect the corresponding page.
3594 * 3. Flush TLB's if needed.
3595 * 4. Copy the snapshot to the userspace.
95d4c16c 3596 *
60c34612
TY		 3597 * Between 2 and 3, the guest may write to the page using the remaining TLB
3598 * entry. This is not a problem because the page will be reported dirty at
3599 * step 4 using the snapshot taken before and step 3 ensures that successive
3600 * writes will be logged for the next call.
5bb064dc 3601 */
60c34612 3602int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3603{
7850ac54 3604 int r;
5bb064dc 3605 struct kvm_memory_slot *memslot;
60c34612
TY		 3606 unsigned long n, i;
3607 unsigned long *dirty_bitmap;
3608 unsigned long *dirty_bitmap_buffer;
3609 bool is_dirty = false;
5bb064dc 3610
79fac95e 3611 mutex_lock(&kvm->slots_lock);
5bb064dc 3612
b050b015 3613 r = -EINVAL;
bbacc0c1 3614 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3615 goto out;
3616
28a37544 3617 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3618
3619 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3620 r = -ENOENT;
60c34612 3621 if (!dirty_bitmap)
b050b015
MT		 3622 goto out;
3623
87bf6e7d 3624 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3625
60c34612
TY		 3626 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3627 memset(dirty_bitmap_buffer, 0, n);
b050b015 3628
60c34612 3629 spin_lock(&kvm->mmu_lock);
b050b015 3630
60c34612
TY		 3631 for (i = 0; i < n / sizeof(long); i++) {
3632 unsigned long mask;
3633 gfn_t offset;
cdfca7b3 3634
60c34612
TY		 3635 if (!dirty_bitmap[i])
3636 continue;
b050b015 3637
60c34612 3638 is_dirty = true;
914ebccd 3639
60c34612
TY		 3640 mask = xchg(&dirty_bitmap[i], 0);
3641 dirty_bitmap_buffer[i] = mask;
edde99ce 3642
60c34612
TY		 3643 offset = i * BITS_PER_LONG;
3644 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3645 }
60c34612
TY		 3646
3647 spin_unlock(&kvm->mmu_lock);
3648
198c74f4
XG		 3649 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3650 lockdep_assert_held(&kvm->slots_lock);
3651
3652 /*
3653 * All the TLBs can be flushed out of mmu lock, see the comments in
3654 * kvm_mmu_slot_remove_write_access().
3655 */
3656 if (is_dirty)
3657 kvm_flush_remote_tlbs(kvm);
3658
60c34612
TY		 3659 r = -EFAULT;
3660 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3661 goto out;
b050b015 3662
5bb064dc
ZX		 3663 r = 0;
3664out:
79fac95e 3665 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3666 return r;
3667}
3668
aa2fbe6d
YZ		 3669int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3670 bool line_status)
23d43cf9
CD		 3671{
3672 if (!irqchip_in_kernel(kvm))
3673 return -ENXIO;
3674
3675 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3676 irq_event->irq, irq_event->level,
3677 line_status);
23d43cf9
CD		 3678 return 0;
3679}
3680
1fe779f8
CO		 3681long kvm_arch_vm_ioctl(struct file *filp,
3682 unsigned int ioctl, unsigned long arg)
3683{
3684 struct kvm *kvm = filp->private_data;
3685 void __user *argp = (void __user *)arg;
367e1319 3686 int r = -ENOTTY;
f0d66275
DH		 3687 /*
3688 * This union makes it completely explicit to gcc-3.x
3689 * that these two variables' stack usage should be
3690 * combined, not added together.
3691 */
3692 union {
3693 struct kvm_pit_state ps;
e9f42757 3694 struct kvm_pit_state2 ps2;
c5ff41ce 3695 struct kvm_pit_config pit_config;
f0d66275 3696 } u;
1fe779f8
CO		 3697
3698 switch (ioctl) {
3699 case KVM_SET_TSS_ADDR:
3700 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3701 break;
b927a3ce
SY		 3702 case KVM_SET_IDENTITY_MAP_ADDR: {
3703 u64 ident_addr;
3704
3705 r = -EFAULT;
3706 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3707 goto out;
3708 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3709 break;
3710 }
1fe779f8
CO		 3711 case KVM_SET_NR_MMU_PAGES:
3712 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3713 break;
3714 case KVM_GET_NR_MMU_PAGES:
3715 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3716 break;
3ddea128
MT		 3717 case KVM_CREATE_IRQCHIP: {
3718 struct kvm_pic *vpic;
3719
3720 mutex_lock(&kvm->lock);
3721 r = -EEXIST;
3722 if (kvm->arch.vpic)
3723 goto create_irqchip_unlock;
3e515705
AK		 3724 r = -EINVAL;
3725 if (atomic_read(&kvm->online_vcpus))
3726 goto create_irqchip_unlock;
1fe779f8 3727 r = -ENOMEM;
3ddea128
MT		 3728 vpic = kvm_create_pic(kvm);
3729 if (vpic) {
1fe779f8
CO		 3730 r = kvm_ioapic_init(kvm);
3731 if (r) {
175504cd 3732 mutex_lock(&kvm->slots_lock);
72bb2fcd 3733 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3734 &vpic->dev_master);
3735 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3736 &vpic->dev_slave);
3737 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3738 &vpic->dev_eclr);
175504cd 3739 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3740 kfree(vpic);
3741 goto create_irqchip_unlock;
1fe779f8
CO		 3742 }
3743 } else
3ddea128
MT		 3744 goto create_irqchip_unlock;
3745 smp_wmb();
3746 kvm->arch.vpic = vpic;
3747 smp_wmb();
399ec807
AK		 3748 r = kvm_setup_default_irq_routing(kvm);
3749 if (r) {
175504cd 3750 mutex_lock(&kvm->slots_lock);
3ddea128 3751 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3752 kvm_ioapic_destroy(kvm);
3753 kvm_destroy_pic(kvm);
3ddea128 3754 mutex_unlock(&kvm->irq_lock);
175504cd 3755 mutex_unlock(&kvm->slots_lock);
399ec807 3756 }
3ddea128
MT		 3757 create_irqchip_unlock:
3758 mutex_unlock(&kvm->lock);
1fe779f8 3759 break;
3ddea128 3760 }
7837699f 3761 case KVM_CREATE_PIT:
c5ff41ce
JK		 3762 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3763 goto create_pit;
3764 case KVM_CREATE_PIT2:
3765 r = -EFAULT;
3766 if (copy_from_user(&u.pit_config, argp,
3767 sizeof(struct kvm_pit_config)))
3768 goto out;
3769 create_pit:
79fac95e 3770 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3771 r = -EEXIST;
3772 if (kvm->arch.vpit)
3773 goto create_pit_unlock;
7837699f 3774 r = -ENOMEM;
c5ff41ce 3775 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3776 if (kvm->arch.vpit)
3777 r = 0;
269e05e4 3778 create_pit_unlock:
79fac95e 3779 mutex_unlock(&kvm->slots_lock);
7837699f 3780 break;
1fe779f8
CO		 3781 case KVM_GET_IRQCHIP: {
3782 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3783 struct kvm_irqchip *chip;
1fe779f8 3784
ff5c2c03
SL		 3785 chip = memdup_user(argp, sizeof(*chip));
3786 if (IS_ERR(chip)) {
3787 r = PTR_ERR(chip);
1fe779f8 3788 goto out;
ff5c2c03
SL		 3789 }
3790
1fe779f8
CO		 3791 r = -ENXIO;
3792 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3793 goto get_irqchip_out;
3794 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3795 if (r)
f0d66275 3796 goto get_irqchip_out;
1fe779f8 3797 r = -EFAULT;
f0d66275
DH		 3798 if (copy_to_user(argp, chip, sizeof *chip))
3799 goto get_irqchip_out;
1fe779f8 3800 r = 0;
f0d66275
DH		 3801 get_irqchip_out:
3802 kfree(chip);
1fe779f8
CO		 3803 break;
3804 }
3805 case KVM_SET_IRQCHIP: {
3806 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3807 struct kvm_irqchip *chip;
1fe779f8 3808
ff5c2c03
SL		 3809 chip = memdup_user(argp, sizeof(*chip));
3810 if (IS_ERR(chip)) {
3811 r = PTR_ERR(chip);
1fe779f8 3812 goto out;
ff5c2c03
SL		 3813 }
3814
1fe779f8
CO		 3815 r = -ENXIO;
3816 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3817 goto set_irqchip_out;
3818 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3819 if (r)
f0d66275 3820 goto set_irqchip_out;
1fe779f8 3821 r = 0;
f0d66275
DH		 3822 set_irqchip_out:
3823 kfree(chip);
1fe779f8
CO		 3824 break;
3825 }
e0f63cb9 3826 case KVM_GET_PIT: {
e0f63cb9 3827 r = -EFAULT;
f0d66275 3828 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3829 goto out;
3830 r = -ENXIO;
3831 if (!kvm->arch.vpit)
3832 goto out;
f0d66275 3833 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3834 if (r)
3835 goto out;
3836 r = -EFAULT;
f0d66275 3837 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3838 goto out;
3839 r = 0;
3840 break;
3841 }
3842 case KVM_SET_PIT: {
e0f63cb9 3843 r = -EFAULT;
f0d66275 3844 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3845 goto out;
3846 r = -ENXIO;
3847 if (!kvm->arch.vpit)
3848 goto out;
f0d66275 3849 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3850 break;
3851 }
e9f42757
BK		 3852 case KVM_GET_PIT2: {
3853 r = -ENXIO;
3854 if (!kvm->arch.vpit)
3855 goto out;
3856 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3857 if (r)
3858 goto out;
3859 r = -EFAULT;
3860 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3861 goto out;
3862 r = 0;
3863 break;
3864 }
3865 case KVM_SET_PIT2: {
3866 r = -EFAULT;
3867 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3868 goto out;
3869 r = -ENXIO;
3870 if (!kvm->arch.vpit)
3871 goto out;
3872 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3873 break;
3874 }
52d939a0
MT		 3875 case KVM_REINJECT_CONTROL: {
3876 struct kvm_reinject_control control;
3877 r = -EFAULT;
3878 if (copy_from_user(&control, argp, sizeof(control)))
3879 goto out;
3880 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3881 break;
3882 }
ffde22ac
ES		 3883 case KVM_XEN_HVM_CONFIG: {
3884 r = -EFAULT;
3885 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3886 sizeof(struct kvm_xen_hvm_config)))
3887 goto out;
3888 r = -EINVAL;
3889 if (kvm->arch.xen_hvm_config.flags)
3890 goto out;
3891 r = 0;
3892 break;
3893 }
afbcf7ab 3894 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3895 struct kvm_clock_data user_ns;
3896 u64 now_ns;
3897 s64 delta;
3898
3899 r = -EFAULT;
3900 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3901 goto out;
3902
3903 r = -EINVAL;
3904 if (user_ns.flags)
3905 goto out;
3906
3907 r = 0;
395c6b0a 3908 local_irq_disable();
759379dd 3909 now_ns = get_kernel_ns();
afbcf7ab 3910 delta = user_ns.clock - now_ns;
395c6b0a 3911 local_irq_enable();
afbcf7ab 3912 kvm->arch.kvmclock_offset = delta;
2e762ff7 3913 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3914 break;
3915 }
3916 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3917 struct kvm_clock_data user_ns;
3918 u64 now_ns;
3919
395c6b0a 3920 local_irq_disable();
759379dd 3921 now_ns = get_kernel_ns();
afbcf7ab 3922 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3923 local_irq_enable();
afbcf7ab 3924 user_ns.flags = 0;
97e69aa6 3925 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3926
3927 r = -EFAULT;
3928 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3929 goto out;
3930 r = 0;
3931 break;
3932 }
3933
1fe779f8
CO		 3934 default:
3935 ;
3936 }
3937out:
3938 return r;
3939}
3940
a16b043c 3941static void kvm_init_msr_list(void)
043405e1
CO		 3942{
3943 u32 dummy[2];
3944 unsigned i, j;
3945
e3267cbb
GC		 3946 /* skip the first msrs in the list. KVM-specific */
3947 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3948 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3949 continue;
93c4adc7
PB		 3950
3951 /*
3952 * Even MSRs that are valid in the host may not be exposed
3953 * to the guests in some cases. We could work around this
3954 * in VMX with the generic MSR save/load machinery, but it
3955 * is not really worthwhile since it will really only
3956 * happen with nested virtualization.
3957 */
3958 switch (msrs_to_save[i]) {
3959 case MSR_IA32_BNDCFGS:
3960 if (!kvm_x86_ops->mpx_supported())
3961 continue;
3962 break;
3963 default:
3964 break;
3965 }
3966
043405e1
CO		 3967 if (j < i)
3968 msrs_to_save[j] = msrs_to_save[i];
3969 j++;
3970 }
3971 num_msrs_to_save = j;
3972}
3973
bda9020e
MT		 3974static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3975 const void *v)
bbd9b64e 3976{
70252a10
AK		 3977 int handled = 0;
3978 int n;
3979
3980 do {
3981 n = min(len, 8);
3982 if (!(vcpu->arch.apic &&
3983 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3984 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3985 break;
3986 handled += n;
3987 addr += n;
3988 len -= n;
3989 v += n;
3990 } while (len);
bbd9b64e 3991
70252a10 3992 return handled;
bbd9b64e
CO		 3993}
3994
bda9020e 3995static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3996{
70252a10
AK		 3997 int handled = 0;
3998 int n;
3999
4000 do {
4001 n = min(len, 8);
4002 if (!(vcpu->arch.apic &&
4003 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4004 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4005 break;
4006 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4007 handled += n;
4008 addr += n;
4009 len -= n;
4010 v += n;
4011 } while (len);
bbd9b64e 4012
70252a10 4013 return handled;
bbd9b64e
CO		 4014}
4015
2dafc6c2
GN		 4016static void kvm_set_segment(struct kvm_vcpu *vcpu,
4017 struct kvm_segment *var, int seg)
4018{
4019 kvm_x86_ops->set_segment(vcpu, var, seg);
4020}
4021
4022void kvm_get_segment(struct kvm_vcpu *vcpu,
4023 struct kvm_segment *var, int seg)
4024{
4025 kvm_x86_ops->get_segment(vcpu, var, seg);
4026}
4027
e459e322 4028gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4029{
4030 gpa_t t_gpa;
ab9ae313 4031 struct x86_exception exception;
02f59dc9
JR		 4032
4033 BUG_ON(!mmu_is_nested(vcpu));
4034
4035 /* NPT walks are always user-walks */
4036 access |= PFERR_USER_MASK;
ab9ae313 4037 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4038
4039 return t_gpa;
4040}
4041
ab9ae313
AK		 4042gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4043 struct x86_exception *exception)
1871c602
GN		 4044{
4045 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4046 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4047}
4048
ab9ae313
AK		 4049 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4050 struct x86_exception *exception)
1871c602
GN		 4051{
4052 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4053 access |= PFERR_FETCH_MASK;
ab9ae313 4054 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4055}
4056
ab9ae313
AK		 4057gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4058 struct x86_exception *exception)
1871c602
GN		 4059{
4060 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4061 access |= PFERR_WRITE_MASK;
ab9ae313 4062 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4063}
4064
4065/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4066gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4067 struct x86_exception *exception)
1871c602 4068{
ab9ae313 4069 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4070}
4071
4072static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4073 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4074 struct x86_exception *exception)
bbd9b64e
CO		 4075{
4076 void *data = val;
10589a46 4077 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4078
4079 while (bytes) {
14dfe855 4080 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4081 exception);
bbd9b64e 4082 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4083 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4084 int ret;
4085
bcc55cba 4086 if (gpa == UNMAPPED_GVA)
ab9ae313 4087 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4088 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4089 if (ret < 0) {
c3cd7ffa 4090 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4091 goto out;
4092 }
bbd9b64e 4093
77c2002e
IE		 4094 bytes -= toread;
4095 data += toread;
4096 addr += toread;
bbd9b64e 4097 }
10589a46 4098out:
10589a46 4099 return r;
bbd9b64e 4100}
77c2002e 4101
1871c602 4102/* used for instruction fetching */
0f65dd70
AK		 4103static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4104 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4105 struct x86_exception *exception)
1871c602 4106{
0f65dd70 4107 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4108 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4109
1871c602 4110 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4111 access | PFERR_FETCH_MASK,
4112 exception);
1871c602
GN		 4113}
4114
064aea77 4115int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4116 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4117 struct x86_exception *exception)
1871c602 4118{
0f65dd70 4119 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4120 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4121
1871c602 4122 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4123 exception);
1871c602 4124}
064aea77 4125EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4126
0f65dd70
AK		 4127static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4128 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4129 struct x86_exception *exception)
1871c602 4130{
0f65dd70 4131 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4132 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4133}
4134
6a4d7550 4135int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4136 gva_t addr, void *val,
2dafc6c2 4137 unsigned int bytes,
bcc55cba 4138 struct x86_exception *exception)
77c2002e 4139{
0f65dd70 4140 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4141 void *data = val;
4142 int r = X86EMUL_CONTINUE;
4143
4144 while (bytes) {
14dfe855
JR		 4145 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4146 PFERR_WRITE_MASK,
ab9ae313 4147 exception);
77c2002e
IE		 4148 unsigned offset = addr & (PAGE_SIZE-1);
4149 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4150 int ret;
4151
bcc55cba 4152 if (gpa == UNMAPPED_GVA)
ab9ae313 4153 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4154 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4155 if (ret < 0) {
c3cd7ffa 4156 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4157 goto out;
4158 }
4159
4160 bytes -= towrite;
4161 data += towrite;
4162 addr += towrite;
4163 }
4164out:
4165 return r;
4166}
6a4d7550 4167EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4168
af7cc7d1
XG		 4169static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4170 gpa_t *gpa, struct x86_exception *exception,
4171 bool write)
4172{
97d64b78
AK		 4173 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4174 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4175
97d64b78 4176 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4177 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4178 vcpu->arch.access, access)) {
bebb106a
XG		 4179 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4180 (gva & (PAGE_SIZE - 1));
4f022648 4181 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4182 return 1;
4183 }
4184
af7cc7d1
XG		 4185 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4186
4187 if (*gpa == UNMAPPED_GVA)
4188 return -1;
4189
4190 /* For APIC access vmexit */
4191 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4192 return 1;
4193
4f022648
XG		 4194 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4195 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4196 return 1;
4f022648 4197 }
bebb106a 4198
af7cc7d1
XG		 4199 return 0;
4200}
4201
3200f405 4202int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4203 const void *val, int bytes)
bbd9b64e
CO		 4204{
4205 int ret;
4206
4207 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4208 if (ret < 0)
bbd9b64e 4209 return 0;
f57f2ef5 4210 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4211 return 1;
4212}
4213
77d197b2
XG		 4214struct read_write_emulator_ops {
4215 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4216 int bytes);
4217 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4218 void *val, int bytes);
4219 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4220 int bytes, void *val);
4221 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4222 void *val, int bytes);
4223 bool write;
4224};
4225
4226static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4227{
4228 if (vcpu->mmio_read_completed) {
77d197b2 4229 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4230 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4231 vcpu->mmio_read_completed = 0;
4232 return 1;
4233 }
4234
4235 return 0;
4236}
4237
4238static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4239 void *val, int bytes)
4240{
4241 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4242}
4243
4244static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4245 void *val, int bytes)
4246{
4247 return emulator_write_phys(vcpu, gpa, val, bytes);
4248}
4249
4250static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4251{
4252 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4253 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4254}
4255
4256static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4257 void *val, int bytes)
4258{
4259 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4260 return X86EMUL_IO_NEEDED;
4261}
4262
4263static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4264 void *val, int bytes)
4265{
f78146b0
AK		 4266 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4267
87da7e66 4268 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4269 return X86EMUL_CONTINUE;
4270}
4271
0fbe9b0b 4272static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4273 .read_write_prepare = read_prepare,
4274 .read_write_emulate = read_emulate,
4275 .read_write_mmio = vcpu_mmio_read,
4276 .read_write_exit_mmio = read_exit_mmio,
4277};
4278
0fbe9b0b 4279static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4280 .read_write_emulate = write_emulate,
4281 .read_write_mmio = write_mmio,
4282 .read_write_exit_mmio = write_exit_mmio,
4283 .write = true,
4284};
4285
22388a3c
XG		 4286static int emulator_read_write_onepage(unsigned long addr, void *val,
4287 unsigned int bytes,
4288 struct x86_exception *exception,
4289 struct kvm_vcpu *vcpu,
0fbe9b0b 4290 const struct read_write_emulator_ops *ops)
bbd9b64e 4291{
af7cc7d1
XG		 4292 gpa_t gpa;
4293 int handled, ret;
22388a3c 4294 bool write = ops->write;
f78146b0 4295 struct kvm_mmio_fragment *frag;
10589a46 4296
22388a3c 4297 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4298
af7cc7d1 4299 if (ret < 0)
bbd9b64e 4300 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4301
4302 /* For APIC access vmexit */
af7cc7d1 4303 if (ret)
bbd9b64e
CO		 4304 goto mmio;
4305
22388a3c 4306 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4307 return X86EMUL_CONTINUE;
4308
4309mmio:
4310 /*
4311 * Is this MMIO handled locally?
4312 */
22388a3c 4313 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4314 if (handled == bytes)
bbd9b64e 4315 return X86EMUL_CONTINUE;
bbd9b64e 4316
70252a10
AK		 4317 gpa += handled;
4318 bytes -= handled;
4319 val += handled;
4320
87da7e66
XG		 4321 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4322 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4323 frag->gpa = gpa;
4324 frag->data = val;
4325 frag->len = bytes;
f78146b0 4326 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4327}
4328
22388a3c
XG		 4329int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4330 void *val, unsigned int bytes,
4331 struct x86_exception *exception,
0fbe9b0b 4332 const struct read_write_emulator_ops *ops)
bbd9b64e 4333{
0f65dd70 4334 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4335 gpa_t gpa;
4336 int rc;
4337
4338 if (ops->read_write_prepare &&
4339 ops->read_write_prepare(vcpu, val, bytes))
4340 return X86EMUL_CONTINUE;
4341
4342 vcpu->mmio_nr_fragments = 0;
0f65dd70 4343
bbd9b64e
CO		 4344 /* Crossing a page boundary? */
4345 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4346 int now;
bbd9b64e
CO		 4347
4348 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4349 rc = emulator_read_write_onepage(addr, val, now, exception,
4350 vcpu, ops);
4351
bbd9b64e
CO		 4352 if (rc != X86EMUL_CONTINUE)
4353 return rc;
4354 addr += now;
4355 val += now;
4356 bytes -= now;
4357 }
22388a3c 4358
f78146b0
AK		 4359 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4360 vcpu, ops);
4361 if (rc != X86EMUL_CONTINUE)
4362 return rc;
4363
4364 if (!vcpu->mmio_nr_fragments)
4365 return rc;
4366
4367 gpa = vcpu->mmio_fragments[0].gpa;
4368
4369 vcpu->mmio_needed = 1;
4370 vcpu->mmio_cur_fragment = 0;
4371
87da7e66 4372 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4373 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4374 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4375 vcpu->run->mmio.phys_addr = gpa;
4376
4377 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4378}
4379
4380static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4381 unsigned long addr,
4382 void *val,
4383 unsigned int bytes,
4384 struct x86_exception *exception)
4385{
4386 return emulator_read_write(ctxt, addr, val, bytes,
4387 exception, &read_emultor);
4388}
4389
4390int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4391 unsigned long addr,
4392 const void *val,
4393 unsigned int bytes,
4394 struct x86_exception *exception)
4395{
4396 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4397 exception, &write_emultor);
bbd9b64e 4398}
bbd9b64e 4399
daea3e73
AK		 4400#define CMPXCHG_TYPE(t, ptr, old, new) \
4401 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4402
4403#ifdef CONFIG_X86_64
4404# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4405#else
4406# define CMPXCHG64(ptr, old, new) \
9749a6c0 4407 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4408#endif
4409
0f65dd70
AK		 4410static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4411 unsigned long addr,
bbd9b64e
CO		 4412 const void *old,
4413 const void *new,
4414 unsigned int bytes,
0f65dd70 4415 struct x86_exception *exception)
bbd9b64e 4416{
0f65dd70 4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4418 gpa_t gpa;
4419 struct page *page;
4420 char *kaddr;
4421 bool exchanged;
2bacc55c 4422
daea3e73
AK		 4423 /* guests cmpxchg8b have to be emulated atomically */
4424 if (bytes > 8 || (bytes & (bytes - 1)))
4425 goto emul_write;
10589a46 4426
daea3e73 4427 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4428
daea3e73
AK		 4429 if (gpa == UNMAPPED_GVA ||
4430 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4431 goto emul_write;
2bacc55c 4432
daea3e73
AK		 4433 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4434 goto emul_write;
72dc67a6 4435
daea3e73 4436 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4437 if (is_error_page(page))
c19b8bd6 4438 goto emul_write;
72dc67a6 4439
8fd75e12 4440 kaddr = kmap_atomic(page);
daea3e73
AK		 4441 kaddr += offset_in_page(gpa);
4442 switch (bytes) {
4443 case 1:
4444 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4445 break;
4446 case 2:
4447 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4448 break;
4449 case 4:
4450 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4451 break;
4452 case 8:
4453 exchanged = CMPXCHG64(kaddr, old, new);
4454 break;
4455 default:
4456 BUG();
2bacc55c 4457 }
8fd75e12 4458 kunmap_atomic(kaddr);
daea3e73
AK		 4459 kvm_release_page_dirty(page);
4460
4461 if (!exchanged)
4462 return X86EMUL_CMPXCHG_FAILED;
4463
d3714010 4464 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4465 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4466
4467 return X86EMUL_CONTINUE;
4a5f48f6 4468
3200f405 4469emul_write:
daea3e73 4470 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4471
0f65dd70 4472 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4473}
4474
cf8f70bf
GN		 4475static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4476{
4477 /* TODO: String I/O for in kernel device */
4478 int r;
4479
4480 if (vcpu->arch.pio.in)
4481 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4482 vcpu->arch.pio.size, pd);
4483 else
4484 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4485 vcpu->arch.pio.port, vcpu->arch.pio.size,
4486 pd);
4487 return r;
4488}
4489
6f6fbe98
XG		 4490static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4491 unsigned short port, void *val,
4492 unsigned int count, bool in)
cf8f70bf 4493{
cf8f70bf 4494 vcpu->arch.pio.port = port;
6f6fbe98 4495 vcpu->arch.pio.in = in;
7972995b 4496 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4497 vcpu->arch.pio.size = size;
4498
4499 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4500 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4501 return 1;
4502 }
4503
4504 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4505 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4506 vcpu->run->io.size = size;
4507 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4508 vcpu->run->io.count = count;
4509 vcpu->run->io.port = port;
4510
4511 return 0;
4512}
4513
6f6fbe98
XG		 4514static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4515 int size, unsigned short port, void *val,
4516 unsigned int count)
cf8f70bf 4517{
ca1d4a9e 4518 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4519 int ret;
ca1d4a9e 4520
6f6fbe98
XG		 4521 if (vcpu->arch.pio.count)
4522 goto data_avail;
cf8f70bf 4523
6f6fbe98
XG		 4524 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4525 if (ret) {
4526data_avail:
4527 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4528 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4529 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4530 return 1;
4531 }
4532
cf8f70bf
GN		 4533 return 0;
4534}
4535
6f6fbe98
XG		 4536static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4537 int size, unsigned short port,
4538 const void *val, unsigned int count)
4539{
4540 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4541
4542 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4543 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4544 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4545}
4546
bbd9b64e
CO		 4547static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4548{
4549 return kvm_x86_ops->get_segment_base(vcpu, seg);
4550}
4551
3cb16fe7 4552static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4553{
3cb16fe7 4554 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4555}
4556
f5f48ee1
SY		 4557int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4558{
4559 if (!need_emulate_wbinvd(vcpu))
4560 return X86EMUL_CONTINUE;
4561
4562 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4563 int cpu = get_cpu();
4564
4565 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4566 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4567 wbinvd_ipi, NULL, 1);
2eec7343 4568 put_cpu();
f5f48ee1 4569 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4570 } else
4571 wbinvd();
f5f48ee1
SY		 4572 return X86EMUL_CONTINUE;
4573}
4574EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4575
bcaf5cc5
AK		 4576static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4577{
4578 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4579}
4580
717746e3 4581int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4582{
717746e3 4583 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4584}
4585
717746e3 4586int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4587{
338dbc97 4588
717746e3 4589 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4590}
4591
52a46617 4592static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4593{
52a46617 4594 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4595}
4596
717746e3 4597static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4598{
717746e3 4599 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4600 unsigned long value;
4601
4602 switch (cr) {
4603 case 0:
4604 value = kvm_read_cr0(vcpu);
4605 break;
4606 case 2:
4607 value = vcpu->arch.cr2;
4608 break;
4609 case 3:
9f8fe504 4610 value = kvm_read_cr3(vcpu);
52a46617
GN		 4611 break;
4612 case 4:
4613 value = kvm_read_cr4(vcpu);
4614 break;
4615 case 8:
4616 value = kvm_get_cr8(vcpu);
4617 break;
4618 default:
a737f256 4619 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4620 return 0;
4621 }
4622
4623 return value;
4624}
4625
717746e3 4626static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4627{
717746e3 4628 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4629 int res = 0;
4630
52a46617
GN		 4631 switch (cr) {
4632 case 0:
49a9b07e 4633 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4634 break;
4635 case 2:
4636 vcpu->arch.cr2 = val;
4637 break;
4638 case 3:
2390218b 4639 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4640 break;
4641 case 4:
a83b29c6 4642 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4643 break;
4644 case 8:
eea1cff9 4645 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4646 break;
4647 default:
a737f256 4648 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4649 res = -1;
52a46617 4650 }
0f12244f
GN		 4651
4652 return res;
52a46617
GN		 4653}
4654
717746e3 4655static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4656{
717746e3 4657 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4658}
4659
4bff1e86 4660static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4661{
4bff1e86 4662 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4663}
4664
4bff1e86 4665static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4666{
4bff1e86 4667 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4668}
4669
1ac9d0cf
AK		 4670static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4671{
4672 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4673}
4674
4675static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4676{
4677 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4678}
4679
4bff1e86
AK		 4680static unsigned long emulator_get_cached_segment_base(
4681 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4682{
4bff1e86 4683 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4684}
4685
1aa36616
AK		 4686static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4687 struct desc_struct *desc, u32 *base3,
4688 int seg)
2dafc6c2
GN		 4689{
4690 struct kvm_segment var;
4691
4bff1e86 4692 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4693 *selector = var.selector;
2dafc6c2 4694
378a8b09
GN		 4695 if (var.unusable) {
4696 memset(desc, 0, sizeof(*desc));
2dafc6c2 4697 return false;
378a8b09 4698 }
2dafc6c2
GN		 4699
4700 if (var.g)
4701 var.limit >>= 12;
4702 set_desc_limit(desc, var.limit);
4703 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4704#ifdef CONFIG_X86_64
4705 if (base3)
4706 *base3 = var.base >> 32;
4707#endif
2dafc6c2
GN		 4708 desc->type = var.type;
4709 desc->s = var.s;
4710 desc->dpl = var.dpl;
4711 desc->p = var.present;
4712 desc->avl = var.avl;
4713 desc->l = var.l;
4714 desc->d = var.db;
4715 desc->g = var.g;
4716
4717 return true;
4718}
4719
1aa36616
AK		 4720static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4721 struct desc_struct *desc, u32 base3,
4722 int seg)
2dafc6c2 4723{
4bff1e86 4724 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4725 struct kvm_segment var;
4726
1aa36616 4727 var.selector = selector;
2dafc6c2 4728 var.base = get_desc_base(desc);
5601d05b
GN		 4729#ifdef CONFIG_X86_64
4730 var.base |= ((u64)base3) << 32;
4731#endif
2dafc6c2
GN		 4732 var.limit = get_desc_limit(desc);
4733 if (desc->g)
4734 var.limit = (var.limit << 12) | 0xfff;
4735 var.type = desc->type;
2dafc6c2
GN		 4736 var.dpl = desc->dpl;
4737 var.db = desc->d;
4738 var.s = desc->s;
4739 var.l = desc->l;
4740 var.g = desc->g;
4741 var.avl = desc->avl;
4742 var.present = desc->p;
4743 var.unusable = !var.present;
4744 var.padding = 0;
4745
4746 kvm_set_segment(vcpu, &var, seg);
4747 return;
4748}
4749
717746e3
AK		 4750static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4751 u32 msr_index, u64 *pdata)
4752{
4753 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4754}
4755
4756static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4757 u32 msr_index, u64 data)
4758{
8fe8ab46
WA		 4759 struct msr_data msr;
4760
4761 msr.data = data;
4762 msr.index = msr_index;
4763 msr.host_initiated = false;
4764 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4765}
4766
67f4d428
NA		 4767static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4768 u32 pmc)
4769{
4770 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4771}
4772
222d21aa
AK		 4773static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4774 u32 pmc, u64 *pdata)
4775{
4776 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4777}
4778
6c3287f7
AK		 4779static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4780{
4781 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4782}
4783
5037f6f3
AK		 4784static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4785{
4786 preempt_disable();
5197b808 4787 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4788 /*
4789 * CR0.TS may reference the host fpu state, not the guest fpu state,
4790 * so it may be clear at this point.
4791 */
4792 clts();
4793}
4794
4795static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4796{
4797 preempt_enable();
4798}
4799
2953538e 4800static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4801 struct x86_instruction_info *info,
c4f035c6
AK		 4802 enum x86_intercept_stage stage)
4803{
2953538e 4804 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4805}
4806
0017f93a 4807static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4808 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4809{
0017f93a 4810 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4811}
4812
dd856efa
AK		 4813static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4814{
4815 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4816}
4817
4818static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4819{
4820 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4821}
4822
0225fb50 4823static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4824 .read_gpr = emulator_read_gpr,
4825 .write_gpr = emulator_write_gpr,
1871c602 4826 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4827 .write_std = kvm_write_guest_virt_system,
1871c602 4828 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4829 .read_emulated = emulator_read_emulated,
4830 .write_emulated = emulator_write_emulated,
4831 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4832 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4833 .pio_in_emulated = emulator_pio_in_emulated,
4834 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4835 .get_segment = emulator_get_segment,
4836 .set_segment = emulator_set_segment,
5951c442 4837 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4838 .get_gdt = emulator_get_gdt,
160ce1f1 4839 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4840 .set_gdt = emulator_set_gdt,
4841 .set_idt = emulator_set_idt,
52a46617
GN		 4842 .get_cr = emulator_get_cr,
4843 .set_cr = emulator_set_cr,
9c537244 4844 .cpl = emulator_get_cpl,
35aa5375
GN		 4845 .get_dr = emulator_get_dr,
4846 .set_dr = emulator_set_dr,
717746e3
AK		 4847 .set_msr = emulator_set_msr,
4848 .get_msr = emulator_get_msr,
67f4d428 4849 .check_pmc = emulator_check_pmc,
222d21aa 4850 .read_pmc = emulator_read_pmc,
6c3287f7 4851 .halt = emulator_halt,
bcaf5cc5 4852 .wbinvd = emulator_wbinvd,
d6aa1000 4853 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4854 .get_fpu = emulator_get_fpu,
4855 .put_fpu = emulator_put_fpu,
c4f035c6 4856 .intercept = emulator_intercept,
bdb42f5a 4857 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4858};
4859
95cb2295
GN		 4860static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4861{
4862 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4863 /*
4864 * an sti; sti; sequence only disable interrupts for the first
4865 * instruction. So, if the last instruction, be it emulated or
4866 * not, left the system with the INT_STI flag enabled, it
4867 * means that the last instruction is an sti. We should not
4868 * leave the flag on in this case. The same goes for mov ss
4869 */
4870 if (!(int_shadow & mask))
4871 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4872}
4873
54b8486f
GN		 4874static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4875{
4876 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4877 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4878 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4879 else if (ctxt->exception.error_code_valid)
4880 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4881 ctxt->exception.error_code);
54b8486f 4882 else
da9cb575 4883 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4884}
4885
dd856efa 4886static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4887{
1ce19dc1
BP		 4888 memset(&ctxt->opcode_len, 0,
4889 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4890
9dac77fa
AK		 4891 ctxt->fetch.start = 0;
4892 ctxt->fetch.end = 0;
4893 ctxt->io_read.pos = 0;
4894 ctxt->io_read.end = 0;
4895 ctxt->mem_read.pos = 0;
4896 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4897}
4898
8ec4722d
MG		 4899static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4900{
adf52235 4901 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4902 int cs_db, cs_l;
4903
8ec4722d
MG		 4904 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4905
adf52235
TY		 4906 ctxt->eflags = kvm_get_rflags(vcpu);
4907 ctxt->eip = kvm_rip_read(vcpu);
4908 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4909 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4910 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4911 cs_db ? X86EMUL_MODE_PROT32 :
4912 X86EMUL_MODE_PROT16;
4913 ctxt->guest_mode = is_guest_mode(vcpu);
4914
dd856efa 4915 init_decode_cache(ctxt);
7ae441ea 4916 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4917}
4918
71f9833b 4919int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4920{
9d74191a 4921 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4922 int ret;
4923
4924 init_emulate_ctxt(vcpu);
4925
9dac77fa
AK		 4926 ctxt->op_bytes = 2;
4927 ctxt->ad_bytes = 2;
4928 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4929 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4930
4931 if (ret != X86EMUL_CONTINUE)
4932 return EMULATE_FAIL;
4933
9dac77fa 4934 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4935 kvm_rip_write(vcpu, ctxt->eip);
4936 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4937
4938 if (irq == NMI_VECTOR)
7460fb4a 4939 vcpu->arch.nmi_pending = 0;
63995653
MG		 4940 else
4941 vcpu->arch.interrupt.pending = false;
4942
4943 return EMULATE_DONE;
4944}
4945EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4946
6d77dbfc
GN		 4947static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4948{
fc3a9157
JR		 4949 int r = EMULATE_DONE;
4950
6d77dbfc
GN		 4951 ++vcpu->stat.insn_emulation_fail;
4952 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4953 if (!is_guest_mode(vcpu)) {
4954 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4955 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4956 vcpu->run->internal.ndata = 0;
4957 r = EMULATE_FAIL;
4958 }
6d77dbfc 4959 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4960
4961 return r;
6d77dbfc
GN		 4962}
4963
93c05d3e 4964static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4965 bool write_fault_to_shadow_pgtable,
4966 int emulation_type)
a6f177ef 4967{
95b3cf69 4968 gpa_t gpa = cr2;
8e3d9d06 4969 pfn_t pfn;
a6f177ef 4970
991eebf9
GN		 4971 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4972 return false;
4973
95b3cf69
XG		 4974 if (!vcpu->arch.mmu.direct_map) {
4975 /*
4976 * Write permission should be allowed since only
4977 * write access need to be emulated.
4978 */
4979 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4980
95b3cf69
XG		 4981 /*
4982 * If the mapping is invalid in guest, let cpu retry
4983 * it to generate fault.
4984 */
4985 if (gpa == UNMAPPED_GVA)
4986 return true;
4987 }
a6f177ef 4988
8e3d9d06
XG		 4989 /*
4990 * Do not retry the unhandleable instruction if it faults on the
4991 * readonly host memory, otherwise it will goto a infinite loop:
4992 * retry instruction -> write #PF -> emulation fail -> retry
4993 * instruction -> ...
4994 */
4995 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4996
4997 /*
4998 * If the instruction failed on the error pfn, it can not be fixed,
4999 * report the error to userspace.
5000 */
5001 if (is_error_noslot_pfn(pfn))
5002 return false;
5003
5004 kvm_release_pfn_clean(pfn);
5005
5006 /* The instructions are well-emulated on direct mmu. */
5007 if (vcpu->arch.mmu.direct_map) {
5008 unsigned int indirect_shadow_pages;
5009
5010 spin_lock(&vcpu->kvm->mmu_lock);
5011 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5012 spin_unlock(&vcpu->kvm->mmu_lock);
5013
5014 if (indirect_shadow_pages)
5015 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5016
a6f177ef 5017 return true;
8e3d9d06 5018 }
a6f177ef 5019
95b3cf69
XG		 5020 /*
5021 * if emulation was due to access to shadowed page table
5022 * and it failed try to unshadow page and re-enter the
5023 * guest to let CPU execute the instruction.
5024 */
5025 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5026
5027 /*
5028 * If the access faults on its page table, it can not
5029 * be fixed by unprotecting shadow page and it should
5030 * be reported to userspace.
5031 */
5032 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5033}
5034
1cb3f3ae
XG		 5035static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5036 unsigned long cr2, int emulation_type)
5037{
5038 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5039 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5040
5041 last_retry_eip = vcpu->arch.last_retry_eip;
5042 last_retry_addr = vcpu->arch.last_retry_addr;
5043
5044 /*
5045 * If the emulation is caused by #PF and it is non-page_table
5046 * writing instruction, it means the VM-EXIT is caused by shadow
5047 * page protected, we can zap the shadow page and retry this
5048 * instruction directly.
5049 *
5050 * Note: if the guest uses a non-page-table modifying instruction
5051 * on the PDE that points to the instruction, then we will unmap
5052 * the instruction and go to an infinite loop. So, we cache the
5053 * last retried eip and the last fault address, if we meet the eip
5054 * and the address again, we can break out of the potential infinite
5055 * loop.
5056 */
5057 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5058
5059 if (!(emulation_type & EMULTYPE_RETRY))
5060 return false;
5061
5062 if (x86_page_table_writing_insn(ctxt))
5063 return false;
5064
5065 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5066 return false;
5067
5068 vcpu->arch.last_retry_eip = ctxt->eip;
5069 vcpu->arch.last_retry_addr = cr2;
5070
5071 if (!vcpu->arch.mmu.direct_map)
5072 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5073
22368028 5074 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5075
5076 return true;
5077}
5078
716d51ab
GN		 5079static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5080static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5081
4a1e10d5
PB		 5082static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5083 unsigned long *db)
5084{
5085 u32 dr6 = 0;
5086 int i;
5087 u32 enable, rwlen;
5088
5089 enable = dr7;
5090 rwlen = dr7 >> 16;
5091 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5092 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5093 dr6 |= (1 << i);
5094 return dr6;
5095}
5096
663f4c61
PB		 5097static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5098{
5099 struct kvm_run *kvm_run = vcpu->run;
5100
5101 /*
5102 * Use the "raw" value to see if TF was passed to the processor.
5103 * Note that the new value of the flags has not been saved yet.
5104 *
5105 * This is correct even for TF set by the guest, because "the
5106 * processor will not generate this exception after the instruction
5107 * that sets the TF flag".
5108 */
5109 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5110
5111 if (unlikely(rflags & X86_EFLAGS_TF)) {
5112 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5113 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5114 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5115 kvm_run->debug.arch.exception = DB_VECTOR;
5116 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5117 *r = EMULATE_USER_EXIT;
5118 } else {
5119 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5120 /*
5121 * "Certain debug exceptions may clear bit 0-3. The
5122 * remaining contents of the DR6 register are never
5123 * cleared by the processor".
5124 */
5125 vcpu->arch.dr6 &= ~15;
5126 vcpu->arch.dr6 |= DR6_BS;
5127 kvm_queue_exception(vcpu, DB_VECTOR);
5128 }
5129 }
5130}
5131
4a1e10d5
PB		 5132static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5133{
5134 struct kvm_run *kvm_run = vcpu->run;
5135 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5136 u32 dr6 = 0;
5137
5138 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5139 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5140 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5141 vcpu->arch.guest_debug_dr7,
5142 vcpu->arch.eff_db);
5143
5144 if (dr6 != 0) {
5145 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5146 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5147 get_segment_base(vcpu, VCPU_SREG_CS);
5148
5149 kvm_run->debug.arch.exception = DB_VECTOR;
5150 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5151 *r = EMULATE_USER_EXIT;
5152 return true;
5153 }
5154 }
5155
5156 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5157 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5158 vcpu->arch.dr7,
5159 vcpu->arch.db);
5160
5161 if (dr6 != 0) {
5162 vcpu->arch.dr6 &= ~15;
5163 vcpu->arch.dr6 |= dr6;
5164 kvm_queue_exception(vcpu, DB_VECTOR);
5165 *r = EMULATE_DONE;
5166 return true;
5167 }
5168 }
5169
5170 return false;
5171}
5172
51d8b661
AP		 5173int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5174 unsigned long cr2,
dc25e89e
AP		 5175 int emulation_type,
5176 void *insn,
5177 int insn_len)
bbd9b64e 5178{
95cb2295 5179 int r;
9d74191a 5180 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5181 bool writeback = true;
93c05d3e 5182 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5183
93c05d3e
XG		 5184 /*
5185 * Clear write_fault_to_shadow_pgtable here to ensure it is
5186 * never reused.
5187 */
5188 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5189 kvm_clear_exception_queue(vcpu);
8d7d8102 5190
571008da 5191 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5192 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5193
5194 /*
5195 * We will reenter on the same instruction since
5196 * we do not set complete_userspace_io. This does not
5197 * handle watchpoints yet, those would be handled in
5198 * the emulate_ops.
5199 */
5200 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5201 return r;
5202
9d74191a
TY		 5203 ctxt->interruptibility = 0;
5204 ctxt->have_exception = false;
5205 ctxt->perm_ok = false;
bbd9b64e 5206
b51e974f 5207 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5208
9d74191a 5209 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5210
e46479f8 5211 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5212 ++vcpu->stat.insn_emulation;
1d2887e2 5213 if (r != EMULATION_OK) {
4005996e
AK		 5214 if (emulation_type & EMULTYPE_TRAP_UD)
5215 return EMULATE_FAIL;
991eebf9
GN		 5216 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5217 emulation_type))
bbd9b64e 5218 return EMULATE_DONE;
6d77dbfc
GN		 5219 if (emulation_type & EMULTYPE_SKIP)
5220 return EMULATE_FAIL;
5221 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5222 }
5223 }
5224
ba8afb6b 5225 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5226 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5227 return EMULATE_DONE;
5228 }
5229
1cb3f3ae
XG		 5230 if (retry_instruction(ctxt, cr2, emulation_type))
5231 return EMULATE_DONE;
5232
7ae441ea 5233 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5234 changes registers values during IO operation */
7ae441ea
GN		 5235 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5236 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5237 emulator_invalidate_register_cache(ctxt);
7ae441ea 5238 }
4d2179e1 5239
5cd21917 5240restart:
9d74191a 5241 r = x86_emulate_insn(ctxt);
bbd9b64e 5242
775fde86
JR		 5243 if (r == EMULATION_INTERCEPTED)
5244 return EMULATE_DONE;
5245
d2ddd1c4 5246 if (r == EMULATION_FAILED) {
991eebf9
GN		 5247 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5248 emulation_type))
c3cd7ffa
GN		 5249 return EMULATE_DONE;
5250
6d77dbfc 5251 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5252 }
5253
9d74191a 5254 if (ctxt->have_exception) {
54b8486f 5255 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5256 r = EMULATE_DONE;
5257 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5258 if (!vcpu->arch.pio.in) {
5259 /* FIXME: return into emulator if single-stepping. */
3457e419 5260 vcpu->arch.pio.count = 0;
0912c977 5261 } else {
7ae441ea 5262 writeback = false;
716d51ab
GN		 5263 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5264 }
ac0a48c3 5265 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5266 } else if (vcpu->mmio_needed) {
5267 if (!vcpu->mmio_is_write)
5268 writeback = false;
ac0a48c3 5269 r = EMULATE_USER_EXIT;
716d51ab 5270 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5271 } else if (r == EMULATION_RESTART)
5cd21917 5272 goto restart;
d2ddd1c4
GN		 5273 else
5274 r = EMULATE_DONE;
f850e2e6 5275
7ae441ea 5276 if (writeback) {
9d74191a 5277 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5278 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5279 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5280 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5281 if (r == EMULATE_DONE)
5282 kvm_vcpu_check_singlestep(vcpu, &r);
5283 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5284 } else
5285 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5286
5287 return r;
de7d789a 5288}
51d8b661 5289EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5290
cf8f70bf 5291int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5292{
cf8f70bf 5293 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5294 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5295 size, port, &val, 1);
cf8f70bf 5296 /* do not return to emulator after return from userspace */
7972995b 5297 vcpu->arch.pio.count = 0;
de7d789a
CO		 5298 return ret;
5299}
cf8f70bf 5300EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5301
8cfdc000
ZA		 5302static void tsc_bad(void *info)
5303{
0a3aee0d 5304 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5305}
5306
5307static void tsc_khz_changed(void *data)
c8076604 5308{
8cfdc000
ZA		 5309 struct cpufreq_freqs *freq = data;
5310 unsigned long khz = 0;
5311
5312 if (data)
5313 khz = freq->new;
5314 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5315 khz = cpufreq_quick_get(raw_smp_processor_id());
5316 if (!khz)
5317 khz = tsc_khz;
0a3aee0d 5318 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5319}
5320
c8076604
GH		 5321static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5322 void *data)
5323{
5324 struct cpufreq_freqs *freq = data;
5325 struct kvm *kvm;
5326 struct kvm_vcpu *vcpu;
5327 int i, send_ipi = 0;
5328
8cfdc000
ZA		 5329 /*
5330 * We allow guests to temporarily run on slowing clocks,
5331 * provided we notify them after, or to run on accelerating
5332 * clocks, provided we notify them before. Thus time never
5333 * goes backwards.
5334 *
5335 * However, we have a problem. We can't atomically update
5336 * the frequency of a given CPU from this function; it is
5337 * merely a notifier, which can be called from any CPU.
5338 * Changing the TSC frequency at arbitrary points in time
5339 * requires a recomputation of local variables related to
5340 * the TSC for each VCPU. We must flag these local variables
5341 * to be updated and be sure the update takes place with the
5342 * new frequency before any guests proceed.
5343 *
5344 * Unfortunately, the combination of hotplug CPU and frequency
5345 * change creates an intractable locking scenario; the order
5346 * of when these callouts happen is undefined with respect to
5347 * CPU hotplug, and they can race with each other. As such,
5348 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5349 * undefined; you can actually have a CPU frequency change take
5350 * place in between the computation of X and the setting of the
5351 * variable. To protect against this problem, all updates of
5352 * the per_cpu tsc_khz variable are done in an interrupt
5353 * protected IPI, and all callers wishing to update the value
5354 * must wait for a synchronous IPI to complete (which is trivial
5355 * if the caller is on the CPU already). This establishes the
5356 * necessary total order on variable updates.
5357 *
5358 * Note that because a guest time update may take place
5359 * anytime after the setting of the VCPU's request bit, the
5360 * correct TSC value must be set before the request. However,
5361 * to ensure the update actually makes it to any guest which
5362 * starts running in hardware virtualization between the set
5363 * and the acquisition of the spinlock, we must also ping the
5364 * CPU after setting the request bit.
5365 *
5366 */
5367
c8076604
GH		 5368 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5369 return 0;
5370 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5371 return 0;
8cfdc000
ZA		 5372
5373 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5374
2f303b74 5375 spin_lock(&kvm_lock);
c8076604 5376 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5377 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5378 if (vcpu->cpu != freq->cpu)
5379 continue;
c285545f 5380 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5381 if (vcpu->cpu != smp_processor_id())
8cfdc000 5382 send_ipi = 1;
c8076604
GH		 5383 }
5384 }
2f303b74 5385 spin_unlock(&kvm_lock);
c8076604
GH		 5386
5387 if (freq->old < freq->new && send_ipi) {
5388 /*
5389 * We upscale the frequency. Must make the guest
5390 * doesn't see old kvmclock values while running with
5391 * the new frequency, otherwise we risk the guest sees
5392 * time go backwards.
5393 *
5394 * In case we update the frequency for another cpu
5395 * (which might be in guest context) send an interrupt
5396 * to kick the cpu out of guest context. Next time
5397 * guest context is entered kvmclock will be updated,
5398 * so the guest will not see stale values.
5399 */
8cfdc000 5400 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5401 }
5402 return 0;
5403}
5404
5405static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5406 .notifier_call = kvmclock_cpufreq_notifier
5407};
5408
5409static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5410 unsigned long action, void *hcpu)
5411{
5412 unsigned int cpu = (unsigned long)hcpu;
5413
5414 switch (action) {
5415 case CPU_ONLINE:
5416 case CPU_DOWN_FAILED:
5417 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5418 break;
5419 case CPU_DOWN_PREPARE:
5420 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5421 break;
5422 }
5423 return NOTIFY_OK;
5424}
5425
5426static struct notifier_block kvmclock_cpu_notifier_block = {
5427 .notifier_call = kvmclock_cpu_notifier,
5428 .priority = -INT_MAX
c8076604
GH		 5429};
5430
b820cc0c
ZA		 5431static void kvm_timer_init(void)
5432{
5433 int cpu;
5434
c285545f 5435 max_tsc_khz = tsc_khz;
460dd42e
SB		 5436
5437 cpu_notifier_register_begin();
b820cc0c 5438 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5439#ifdef CONFIG_CPU_FREQ
5440 struct cpufreq_policy policy;
5441 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5442 cpu = get_cpu();
5443 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5444 if (policy.cpuinfo.max_freq)
5445 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5446 put_cpu();
c285545f 5447#endif
b820cc0c
ZA		 5448 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5449 CPUFREQ_TRANSITION_NOTIFIER);
5450 }
c285545f 5451 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5452 for_each_online_cpu(cpu)
5453 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5454
5455 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5456 cpu_notifier_register_done();
5457
b820cc0c
ZA		 5458}
5459
ff9d07a0
ZY		 5460static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5461
f5132b01 5462int kvm_is_in_guest(void)
ff9d07a0 5463{
086c9855 5464 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5465}
5466
5467static int kvm_is_user_mode(void)
5468{
5469 int user_mode = 3;
dcf46b94 5470
086c9855
AS		 5471 if (__this_cpu_read(current_vcpu))
5472 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5473
ff9d07a0
ZY		 5474 return user_mode != 0;
5475}
5476
5477static unsigned long kvm_get_guest_ip(void)
5478{
5479 unsigned long ip = 0;
dcf46b94 5480
086c9855
AS		 5481 if (__this_cpu_read(current_vcpu))
5482 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5483
ff9d07a0
ZY		 5484 return ip;
5485}
5486
5487static struct perf_guest_info_callbacks kvm_guest_cbs = {
5488 .is_in_guest = kvm_is_in_guest,
5489 .is_user_mode = kvm_is_user_mode,
5490 .get_guest_ip = kvm_get_guest_ip,
5491};
5492
5493void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5494{
086c9855 5495 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5496}
5497EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5498
5499void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5500{
086c9855 5501 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5502}
5503EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5504
ce88decf
XG		 5505static void kvm_set_mmio_spte_mask(void)
5506{
5507 u64 mask;
5508 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5509
5510 /*
5511 * Set the reserved bits and the present bit of an paging-structure
5512 * entry to generate page fault with PFER.RSV = 1.
5513 */
885032b9
XG		 5514 /* Mask the reserved physical address bits. */
5515 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5516
5517 /* Bit 62 is always reserved for 32bit host. */
5518 mask |= 0x3ull << 62;
5519
5520 /* Set the present bit. */
ce88decf
XG		 5521 mask |= 1ull;
5522
5523#ifdef CONFIG_X86_64
5524 /*
5525 * If reserved bit is not supported, clear the present bit to disable
5526 * mmio page fault.
5527 */
5528 if (maxphyaddr == 52)
5529 mask &= ~1ull;
5530#endif
5531
5532 kvm_mmu_set_mmio_spte_mask(mask);
5533}
5534
16e8d74d
MT		 5535#ifdef CONFIG_X86_64
5536static void pvclock_gtod_update_fn(struct work_struct *work)
5537{
d828199e
MT		 5538 struct kvm *kvm;
5539
5540 struct kvm_vcpu *vcpu;
5541 int i;
5542
2f303b74 5543 spin_lock(&kvm_lock);
d828199e
MT		 5544 list_for_each_entry(kvm, &vm_list, vm_list)
5545 kvm_for_each_vcpu(i, vcpu, kvm)
5546 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5547 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5548 spin_unlock(&kvm_lock);
16e8d74d
MT		 5549}
5550
5551static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5552
5553/*
5554 * Notification about pvclock gtod data update.
5555 */
5556static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5557 void *priv)
5558{
5559 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5560 struct timekeeper *tk = priv;
5561
5562 update_pvclock_gtod(tk);
5563
5564 /* disable master clock if host does not trust, or does not
5565 * use, TSC clocksource
5566 */
5567 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5568 atomic_read(&kvm_guest_has_master_clock) != 0)
5569 queue_work(system_long_wq, &pvclock_gtod_work);
5570
5571 return 0;
5572}
5573
5574static struct notifier_block pvclock_gtod_notifier = {
5575 .notifier_call = pvclock_gtod_notify,
5576};
5577#endif
5578
f8c16bba 5579int kvm_arch_init(void *opaque)
043405e1 5580{
b820cc0c 5581 int r;
6b61edf7 5582 struct kvm_x86_ops *ops = opaque;
f8c16bba 5583
f8c16bba
ZX		 5584 if (kvm_x86_ops) {
5585 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5586 r = -EEXIST;
5587 goto out;
f8c16bba
ZX		 5588 }
5589
5590 if (!ops->cpu_has_kvm_support()) {
5591 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5592 r = -EOPNOTSUPP;
5593 goto out;
f8c16bba
ZX		 5594 }
5595 if (ops->disabled_by_bios()) {
5596 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5597 r = -EOPNOTSUPP;
5598 goto out;
f8c16bba
ZX		 5599 }
5600
013f6a5d
MT		 5601 r = -ENOMEM;
5602 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5603 if (!shared_msrs) {
5604 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5605 goto out;
5606 }
5607
97db56ce
AK		 5608 r = kvm_mmu_module_init();
5609 if (r)
013f6a5d 5610 goto out_free_percpu;
97db56ce 5611
ce88decf 5612 kvm_set_mmio_spte_mask();
97db56ce 5613
f8c16bba 5614 kvm_x86_ops = ops;
920c8377
PB		 5615 kvm_init_msr_list();
5616
7b52345e 5617 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5618 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5619
b820cc0c 5620 kvm_timer_init();
c8076604 5621
ff9d07a0
ZY		 5622 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5623
2acf923e
DC		 5624 if (cpu_has_xsave)
5625 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5626
c5cc421b 5627 kvm_lapic_init();
16e8d74d
MT		 5628#ifdef CONFIG_X86_64
5629 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5630#endif
5631
f8c16bba 5632 return 0;
56c6d28a 5633
013f6a5d
MT		 5634out_free_percpu:
5635 free_percpu(shared_msrs);
56c6d28a 5636out:
56c6d28a 5637 return r;
043405e1 5638}
8776e519 5639
f8c16bba
ZX		 5640void kvm_arch_exit(void)
5641{
ff9d07a0
ZY		 5642 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5643
888d256e
JK		 5644 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5645 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5646 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5647 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5648#ifdef CONFIG_X86_64
5649 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5650#endif
f8c16bba 5651 kvm_x86_ops = NULL;
56c6d28a 5652 kvm_mmu_module_exit();
013f6a5d 5653 free_percpu(shared_msrs);
56c6d28a 5654}
f8c16bba 5655
8776e519
HB		 5656int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5657{
5658 ++vcpu->stat.halt_exits;
5659 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5660 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5661 return 1;
5662 } else {
5663 vcpu->run->exit_reason = KVM_EXIT_HLT;
5664 return 0;
5665 }
5666}
5667EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5668
55cd8e5a
GN		 5669int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5670{
5671 u64 param, ingpa, outgpa, ret;
5672 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5673 bool fast, longmode;
55cd8e5a
GN		 5674
5675 /*
5676 * hypercall generates UD from non zero cpl and real mode
5677 * per HYPER-V spec
5678 */
3eeb3288 5679 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5680 kvm_queue_exception(vcpu, UD_VECTOR);
5681 return 0;
5682 }
5683
a449c7aa 5684 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5685
5686 if (!longmode) {
ccd46936
GN		 5687 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5688 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5689 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5690 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5691 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5692 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5693 }
5694#ifdef CONFIG_X86_64
5695 else {
5696 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5697 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5698 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5699 }
5700#endif
5701
5702 code = param & 0xffff;
5703 fast = (param >> 16) & 0x1;
5704 rep_cnt = (param >> 32) & 0xfff;
5705 rep_idx = (param >> 48) & 0xfff;
5706
5707 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5708
c25bc163
GN		 5709 switch (code) {
5710 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5711 kvm_vcpu_on_spin(vcpu);
5712 break;
5713 default:
5714 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5715 break;
5716 }
55cd8e5a
GN		 5717
5718 ret = res | (((u64)rep_done & 0xfff) << 32);
5719 if (longmode) {
5720 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5721 } else {
5722 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5723 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5724 }
5725
5726 return 1;
5727}
5728
6aef266c
SV		 5729/*
5730 * kvm_pv_kick_cpu_op: Kick a vcpu.
5731 *
5732 * @apicid - apicid of vcpu to be kicked.
5733 */
5734static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5735{
24d2166b 5736 struct kvm_lapic_irq lapic_irq;
6aef266c 5737
24d2166b
R		 5738 lapic_irq.shorthand = 0;
5739 lapic_irq.dest_mode = 0;
5740 lapic_irq.dest_id = apicid;
6aef266c 5741
24d2166b
R		 5742 lapic_irq.delivery_mode = APIC_DM_REMRD;
5743 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5744}
5745
8776e519
HB		 5746int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5747{
5748 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5749 int op_64_bit, r = 1;
8776e519 5750
55cd8e5a
GN		 5751 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5752 return kvm_hv_hypercall(vcpu);
5753
5fdbf976
MT		 5754 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5755 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5756 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5757 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5758 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5759
229456fc 5760 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5761
a449c7aa
NA		 5762 op_64_bit = is_64_bit_mode(vcpu);
5763 if (!op_64_bit) {
8776e519
HB		 5764 nr &= 0xFFFFFFFF;
5765 a0 &= 0xFFFFFFFF;
5766 a1 &= 0xFFFFFFFF;
5767 a2 &= 0xFFFFFFFF;
5768 a3 &= 0xFFFFFFFF;
5769 }
5770
07708c4a
JK		 5771 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5772 ret = -KVM_EPERM;
5773 goto out;
5774 }
5775
8776e519 5776 switch (nr) {
b93463aa
AK		 5777 case KVM_HC_VAPIC_POLL_IRQ:
5778 ret = 0;
5779 break;
6aef266c
SV		 5780 case KVM_HC_KICK_CPU:
5781 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5782 ret = 0;
5783 break;
8776e519
HB		 5784 default:
5785 ret = -KVM_ENOSYS;
5786 break;
5787 }
07708c4a 5788out:
a449c7aa
NA		 5789 if (!op_64_bit)
5790 ret = (u32)ret;
5fdbf976 5791 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5792 ++vcpu->stat.hypercalls;
2f333bcb 5793 return r;
8776e519
HB		 5794}
5795EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5796
b6785def 5797static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5798{
d6aa1000 5799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5800 char instruction[3];
5fdbf976 5801 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5802
8776e519 5803 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5804
9d74191a 5805 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5806}
5807
b6c7a5dc
HB		 5808/*
5809 * Check if userspace requested an interrupt window, and that the
5810 * interrupt window is open.
5811 *
5812 * No need to exit to userspace if we already have an interrupt queued.
5813 */
851ba692 5814static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5815{
8061823a 5816 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5817 vcpu->run->request_interrupt_window &&
5df56646 5818 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5819}
5820
851ba692 5821static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5822{
851ba692
AK		 5823 struct kvm_run *kvm_run = vcpu->run;
5824
91586a3b 5825 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5826 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5827 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5828 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5829 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5830 else
b6c7a5dc 5831 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5832 kvm_arch_interrupt_allowed(vcpu) &&
5833 !kvm_cpu_has_interrupt(vcpu) &&
5834 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5835}
5836
95ba8273
GN		 5837static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5838{
5839 int max_irr, tpr;
5840
5841 if (!kvm_x86_ops->update_cr8_intercept)
5842 return;
5843
88c808fd
AK		 5844 if (!vcpu->arch.apic)
5845 return;
5846
8db3baa2
GN		 5847 if (!vcpu->arch.apic->vapic_addr)
5848 max_irr = kvm_lapic_find_highest_irr(vcpu);
5849 else
5850 max_irr = -1;
95ba8273
GN		 5851
5852 if (max_irr != -1)
5853 max_irr >>= 4;
5854
5855 tpr = kvm_lapic_get_cr8(vcpu);
5856
5857 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5858}
5859
b6b8a145 5860static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5861{
b6b8a145
JK		 5862 int r;
5863
95ba8273 5864 /* try to reinject previous events if any */
b59bb7bd 5865 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5866 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5867 vcpu->arch.exception.has_error_code,
5868 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5869 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5870 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5871 vcpu->arch.exception.error_code,
5872 vcpu->arch.exception.reinject);
b6b8a145 5873 return 0;
b59bb7bd
GN		 5874 }
5875
95ba8273
GN		 5876 if (vcpu->arch.nmi_injected) {
5877 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5878 return 0;
95ba8273
GN		 5879 }
5880
5881 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5882 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5883 return 0;
5884 }
5885
5886 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5887 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5888 if (r != 0)
5889 return r;
95ba8273
GN		 5890 }
5891
5892 /* try to inject new event if pending */
5893 if (vcpu->arch.nmi_pending) {
5894 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5895 --vcpu->arch.nmi_pending;
95ba8273
GN		 5896 vcpu->arch.nmi_injected = true;
5897 kvm_x86_ops->set_nmi(vcpu);
5898 }
c7c9c56c 5899 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5900 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5901 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5902 false);
5903 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5904 }
5905 }
b6b8a145 5906 return 0;
95ba8273
GN		 5907}
5908
7460fb4a
AK		 5909static void process_nmi(struct kvm_vcpu *vcpu)
5910{
5911 unsigned limit = 2;
5912
5913 /*
5914 * x86 is limited to one NMI running, and one NMI pending after it.
5915 * If an NMI is already in progress, limit further NMIs to just one.
5916 * Otherwise, allow two (and we'll inject the first one immediately).
5917 */
5918 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5919 limit = 1;
5920
5921 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5922 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5923 kvm_make_request(KVM_REQ_EVENT, vcpu);
5924}
5925
3d81bc7e 5926static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5927{
5928 u64 eoi_exit_bitmap[4];
cf9e65b7 5929 u32 tmr[8];
c7c9c56c 5930
3d81bc7e
YZ		 5931 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5932 return;
c7c9c56c
YZ		 5933
5934 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5935 memset(tmr, 0, 32);
c7c9c56c 5936
cf9e65b7 5937 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5938 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5939 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5940}
5941
9357d939
TY		 5942/*
5943 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5944 * exiting to the userspace. Otherwise, the value will be returned to the
5945 * userspace.
5946 */
851ba692 5947static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5948{
5949 int r;
6a8b1d13 5950 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5951 vcpu->run->request_interrupt_window;
730dca42 5952 bool req_immediate_exit = false;
b6c7a5dc 5953
3e007509 5954 if (vcpu->requests) {
a8eeb04a 5955 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5956 kvm_mmu_unload(vcpu);
a8eeb04a 5957 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5958 __kvm_migrate_timers(vcpu);
d828199e
MT		 5959 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5960 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5961 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5962 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5963 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5964 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5965 if (unlikely(r))
5966 goto out;
5967 }
a8eeb04a 5968 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5969 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5970 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5971 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5972 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5973 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5974 r = 0;
5975 goto out;
5976 }
a8eeb04a 5977 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5978 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5979 r = 0;
5980 goto out;
5981 }
a8eeb04a 5982 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5983 vcpu->fpu_active = 0;
5984 kvm_x86_ops->fpu_deactivate(vcpu);
5985 }
af585b92
GN		 5986 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5987 /* Page is swapped out. Do synthetic halt */
5988 vcpu->arch.apf.halted = true;
5989 r = 1;
5990 goto out;
5991 }
c9aaa895
GC		 5992 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5993 record_steal_time(vcpu);
7460fb4a
AK		 5994 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5995 process_nmi(vcpu);
f5132b01
GN		 5996 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5997 kvm_handle_pmu_event(vcpu);
5998 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5999 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6000 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6001 vcpu_scan_ioapic(vcpu);
2f52d58c 6002 }
b93463aa 6003
b463a6f7 6004 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6005 kvm_apic_accept_events(vcpu);
6006 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6007 r = 1;
6008 goto out;
6009 }
6010
b6b8a145
JK		 6011 if (inject_pending_event(vcpu, req_int_win) != 0)
6012 req_immediate_exit = true;
b463a6f7 6013 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6014 else if (vcpu->arch.nmi_pending)
c9a7953f 6015 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6016 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6017 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6018
6019 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6020 /*
6021 * Update architecture specific hints for APIC
6022 * virtual interrupt delivery.
6023 */
6024 if (kvm_x86_ops->hwapic_irr_update)
6025 kvm_x86_ops->hwapic_irr_update(vcpu,
6026 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6027 update_cr8_intercept(vcpu);
6028 kvm_lapic_sync_to_vapic(vcpu);
6029 }
6030 }
6031
d8368af8
AK		 6032 r = kvm_mmu_reload(vcpu);
6033 if (unlikely(r)) {
d905c069 6034 goto cancel_injection;
d8368af8
AK		 6035 }
6036
b6c7a5dc
HB		 6037 preempt_disable();
6038
6039 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6040 if (vcpu->fpu_active)
6041 kvm_load_guest_fpu(vcpu);
2acf923e 6042 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6043
6b7e2d09
XG		 6044 vcpu->mode = IN_GUEST_MODE;
6045
01b71917
MT		 6046 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6047
6b7e2d09
XG		 6048 /* We should set ->mode before check ->requests,
6049 * see the comment in make_all_cpus_request.
6050 */
01b71917 6051 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6052
d94e1dc9 6053 local_irq_disable();
32f88400 6054
6b7e2d09 6055 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6056 || need_resched() || signal_pending(current)) {
6b7e2d09 6057 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6058 smp_wmb();
6c142801
AK		 6059 local_irq_enable();
6060 preempt_enable();
01b71917 6061 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6062 r = 1;
d905c069 6063 goto cancel_injection;
6c142801
AK		 6064 }
6065
d6185f20
NHE		 6066 if (req_immediate_exit)
6067 smp_send_reschedule(vcpu->cpu);
6068
b6c7a5dc
HB		 6069 kvm_guest_enter();
6070
42dbaa5a 6071 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6072 set_debugreg(0, 7);
6073 set_debugreg(vcpu->arch.eff_db[0], 0);
6074 set_debugreg(vcpu->arch.eff_db[1], 1);
6075 set_debugreg(vcpu->arch.eff_db[2], 2);
6076 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6077 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6078 }
b6c7a5dc 6079
229456fc 6080 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6081 kvm_x86_ops->run(vcpu);
b6c7a5dc 6082
c77fb5fe
PB		 6083 /*
6084 * Do this here before restoring debug registers on the host. And
6085 * since we do this before handling the vmexit, a DR access vmexit
6086 * can (a) read the correct value of the debug registers, (b) set
6087 * KVM_DEBUGREG_WONT_EXIT again.
6088 */
6089 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6090 int i;
6091
6092 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6093 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6094 for (i = 0; i < KVM_NR_DB_REGS; i++)
6095 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6096 }
6097
24f1e32c
FW		 6098 /*
6099 * If the guest has used debug registers, at least dr7
6100 * will be disabled while returning to the host.
6101 * If we don't have active breakpoints in the host, we don't
6102 * care about the messed up debug address registers. But if
6103 * we have some of them active, restore the old state.
6104 */
59d8eb53 6105 if (hw_breakpoint_active())
24f1e32c 6106 hw_breakpoint_restore();
42dbaa5a 6107
886b470c
MT		 6108 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6109 native_read_tsc());
1d5f066e 6110
6b7e2d09 6111 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6112 smp_wmb();
a547c6db
YZ		 6113
6114 /* Interrupt is enabled by handle_external_intr() */
6115 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6116
6117 ++vcpu->stat.exits;
6118
6119 /*
6120 * We must have an instruction between local_irq_enable() and
6121 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6122 * the interrupt shadow. The stat.exits increment will do nicely.
6123 * But we need to prevent reordering, hence this barrier():
6124 */
6125 barrier();
6126
6127 kvm_guest_exit();
6128
6129 preempt_enable();
6130
f656ce01 6131 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6132
b6c7a5dc
HB		 6133 /*
6134 * Profile KVM exit RIPs:
6135 */
6136 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6137 unsigned long rip = kvm_rip_read(vcpu);
6138 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6139 }
6140
cc578287
ZA		 6141 if (unlikely(vcpu->arch.tsc_always_catchup))
6142 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6143
5cfb1d5a
MT		 6144 if (vcpu->arch.apic_attention)
6145 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6146
851ba692 6147 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6148 return r;
6149
6150cancel_injection:
6151 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6152 if (unlikely(vcpu->arch.apic_attention))
6153 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6154out:
6155 return r;
6156}
b6c7a5dc 6157
09cec754 6158
851ba692 6159static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6160{
6161 int r;
f656ce01 6162 struct kvm *kvm = vcpu->kvm;
d7690175 6163
f656ce01 6164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6165
6166 r = 1;
6167 while (r > 0) {
af585b92
GN		 6168 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6169 !vcpu->arch.apf.halted)
851ba692 6170 r = vcpu_enter_guest(vcpu);
d7690175 6171 else {
f656ce01 6172 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6173 kvm_vcpu_block(vcpu);
f656ce01 6174 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6175 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6176 kvm_apic_accept_events(vcpu);
09cec754
GN		 6177 switch(vcpu->arch.mp_state) {
6178 case KVM_MP_STATE_HALTED:
6aef266c 6179 vcpu->arch.pv.pv_unhalted = false;
d7690175 6180 vcpu->arch.mp_state =
09cec754
GN		 6181 KVM_MP_STATE_RUNNABLE;
6182 case KVM_MP_STATE_RUNNABLE:
af585b92 6183 vcpu->arch.apf.halted = false;
09cec754 6184 break;
66450a21
JK		 6185 case KVM_MP_STATE_INIT_RECEIVED:
6186 break;
09cec754
GN		 6187 default:
6188 r = -EINTR;
6189 break;
6190 }
6191 }
d7690175
MT		 6192 }
6193
09cec754
GN		 6194 if (r <= 0)
6195 break;
6196
6197 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6198 if (kvm_cpu_has_pending_timer(vcpu))
6199 kvm_inject_pending_timer_irqs(vcpu);
6200
851ba692 6201 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6202 r = -EINTR;
851ba692 6203 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6204 ++vcpu->stat.request_irq_exits;
6205 }
af585b92
GN		 6206
6207 kvm_check_async_pf_completion(vcpu);
6208
09cec754
GN		 6209 if (signal_pending(current)) {
6210 r = -EINTR;
851ba692 6211 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6212 ++vcpu->stat.signal_exits;
6213 }
6214 if (need_resched()) {
f656ce01 6215 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6216 cond_resched();
f656ce01 6217 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6218 }
b6c7a5dc
HB		 6219 }
6220
f656ce01 6221 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6222
6223 return r;
6224}
6225
716d51ab
GN		 6226static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6227{
6228 int r;
6229 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6230 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6231 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6232 if (r != EMULATE_DONE)
6233 return 0;
6234 return 1;
6235}
6236
6237static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6238{
6239 BUG_ON(!vcpu->arch.pio.count);
6240
6241 return complete_emulated_io(vcpu);
6242}
6243
f78146b0
AK		 6244/*
6245 * Implements the following, as a state machine:
6246 *
6247 * read:
6248 * for each fragment
87da7e66
XG		 6249 * for each mmio piece in the fragment
6250 * write gpa, len
6251 * exit
6252 * copy data
f78146b0
AK		 6253 * execute insn
6254 *
6255 * write:
6256 * for each fragment
87da7e66
XG		 6257 * for each mmio piece in the fragment
6258 * write gpa, len
6259 * copy data
6260 * exit
f78146b0 6261 */
716d51ab 6262static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6263{
6264 struct kvm_run *run = vcpu->run;
f78146b0 6265 struct kvm_mmio_fragment *frag;
87da7e66 6266 unsigned len;
5287f194 6267
716d51ab 6268 BUG_ON(!vcpu->mmio_needed);
5287f194 6269
716d51ab 6270 /* Complete previous fragment */
87da7e66
XG		 6271 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6272 len = min(8u, frag->len);
716d51ab 6273 if (!vcpu->mmio_is_write)
87da7e66
XG		 6274 memcpy(frag->data, run->mmio.data, len);
6275
6276 if (frag->len <= 8) {
6277 /* Switch to the next fragment. */
6278 frag++;
6279 vcpu->mmio_cur_fragment++;
6280 } else {
6281 /* Go forward to the next mmio piece. */
6282 frag->data += len;
6283 frag->gpa += len;
6284 frag->len -= len;
6285 }
6286
a08d3b3b 6287 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6288 vcpu->mmio_needed = 0;
0912c977
PB		 6289
6290 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6291 if (vcpu->mmio_is_write)
716d51ab
GN		 6292 return 1;
6293 vcpu->mmio_read_completed = 1;
6294 return complete_emulated_io(vcpu);
6295 }
87da7e66 6296
716d51ab
GN		 6297 run->exit_reason = KVM_EXIT_MMIO;
6298 run->mmio.phys_addr = frag->gpa;
6299 if (vcpu->mmio_is_write)
87da7e66
XG		 6300 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6301 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6302 run->mmio.is_write = vcpu->mmio_is_write;
6303 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6304 return 0;
5287f194
AK		 6305}
6306
716d51ab 6307
b6c7a5dc
HB		 6308int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6309{
6310 int r;
6311 sigset_t sigsaved;
6312
e5c30142
AK		 6313 if (!tsk_used_math(current) && init_fpu(current))
6314 return -ENOMEM;
6315
ac9f6dc0
AK		 6316 if (vcpu->sigset_active)
6317 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6318
a4535290 6319 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6320 kvm_vcpu_block(vcpu);
66450a21 6321 kvm_apic_accept_events(vcpu);
d7690175 6322 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6323 r = -EAGAIN;
6324 goto out;
b6c7a5dc
HB		 6325 }
6326
b6c7a5dc 6327 /* re-sync apic's tpr */
eea1cff9
AP		 6328 if (!irqchip_in_kernel(vcpu->kvm)) {
6329 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6330 r = -EINVAL;
6331 goto out;
6332 }
6333 }
b6c7a5dc 6334
716d51ab
GN		 6335 if (unlikely(vcpu->arch.complete_userspace_io)) {
6336 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6337 vcpu->arch.complete_userspace_io = NULL;
6338 r = cui(vcpu);
6339 if (r <= 0)
6340 goto out;
6341 } else
6342 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6343
851ba692 6344 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6345
6346out:
f1d86e46 6347 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6348 if (vcpu->sigset_active)
6349 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6350
b6c7a5dc
HB		 6351 return r;
6352}
6353
6354int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6355{
7ae441ea
GN		 6356 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6357 /*
6358 * We are here if userspace calls get_regs() in the middle of
6359 * instruction emulation. Registers state needs to be copied
4a969980 6360 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6361 * that usually, but some bad designed PV devices (vmware
6362 * backdoor interface) need this to work
6363 */
dd856efa 6364 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6365 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6366 }
5fdbf976
MT		 6367 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6368 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6369 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6370 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6371 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6372 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6373 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6374 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6375#ifdef CONFIG_X86_64
5fdbf976
MT		 6376 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6377 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6378 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6379 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6380 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6381 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6382 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6383 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6384#endif
6385
5fdbf976 6386 regs->rip = kvm_rip_read(vcpu);
91586a3b 6387 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6388
b6c7a5dc
HB		 6389 return 0;
6390}
6391
6392int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6393{
7ae441ea
GN		 6394 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6395 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6396
5fdbf976
MT		 6397 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6398 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6399 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6400 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6401 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6402 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6403 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6404 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6405#ifdef CONFIG_X86_64
5fdbf976
MT		 6406 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6407 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6408 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6409 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6410 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6411 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6412 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6413 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6414#endif
6415
5fdbf976 6416 kvm_rip_write(vcpu, regs->rip);
91586a3b 6417 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6418
b4f14abd
JK		 6419 vcpu->arch.exception.pending = false;
6420
3842d135
AK		 6421 kvm_make_request(KVM_REQ_EVENT, vcpu);
6422
b6c7a5dc
HB		 6423 return 0;
6424}
6425
b6c7a5dc
HB		 6426void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6427{
6428 struct kvm_segment cs;
6429
3e6e0aab 6430 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6431 *db = cs.db;
6432 *l = cs.l;
6433}
6434EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6435
6436int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6437 struct kvm_sregs *sregs)
6438{
89a27f4d 6439 struct desc_ptr dt;
b6c7a5dc 6440
3e6e0aab
GT		 6441 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6442 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6443 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6444 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6445 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6446 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6447
3e6e0aab
GT		 6448 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6449 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6450
6451 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6452 sregs->idt.limit = dt.size;
6453 sregs->idt.base = dt.address;
b6c7a5dc 6454 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6455 sregs->gdt.limit = dt.size;
6456 sregs->gdt.base = dt.address;
b6c7a5dc 6457
4d4ec087 6458 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6459 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6460 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6461 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6462 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6463 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6464 sregs->apic_base = kvm_get_apic_base(vcpu);
6465
923c61bb 6466 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6467
36752c9b 6468 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6469 set_bit(vcpu->arch.interrupt.nr,
6470 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6471
b6c7a5dc
HB		 6472 return 0;
6473}
6474
62d9f0db
MT		 6475int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6476 struct kvm_mp_state *mp_state)
6477{
66450a21 6478 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6479 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6480 vcpu->arch.pv.pv_unhalted)
6481 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6482 else
6483 mp_state->mp_state = vcpu->arch.mp_state;
6484
62d9f0db
MT		 6485 return 0;
6486}
6487
6488int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6489 struct kvm_mp_state *mp_state)
6490{
66450a21
JK		 6491 if (!kvm_vcpu_has_lapic(vcpu) &&
6492 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6493 return -EINVAL;
6494
6495 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6496 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6497 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6498 } else
6499 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6500 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6501 return 0;
6502}
6503
7f3d35fd
KW		 6504int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6505 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6506{
9d74191a 6507 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6508 int ret;
e01c2426 6509
8ec4722d 6510 init_emulate_ctxt(vcpu);
c697518a 6511
7f3d35fd 6512 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6513 has_error_code, error_code);
c697518a 6514
c697518a 6515 if (ret)
19d04437 6516 return EMULATE_FAIL;
37817f29 6517
9d74191a
TY		 6518 kvm_rip_write(vcpu, ctxt->eip);
6519 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6520 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6521 return EMULATE_DONE;
37817f29
IE		 6522}
6523EXPORT_SYMBOL_GPL(kvm_task_switch);
6524
b6c7a5dc
HB		 6525int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6526 struct kvm_sregs *sregs)
6527{
58cb628d 6528 struct msr_data apic_base_msr;
b6c7a5dc 6529 int mmu_reset_needed = 0;
63f42e02 6530 int pending_vec, max_bits, idx;
89a27f4d 6531 struct desc_ptr dt;
b6c7a5dc 6532
6d1068b3
PM		 6533 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6534 return -EINVAL;
6535
89a27f4d
GN		 6536 dt.size = sregs->idt.limit;
6537 dt.address = sregs->idt.base;
b6c7a5dc 6538 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6539 dt.size = sregs->gdt.limit;
6540 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6541 kvm_x86_ops->set_gdt(vcpu, &dt);
6542
ad312c7c 6543 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6544 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6545 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6546 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6547
2d3ad1f4 6548 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6549
f6801dff 6550 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6551 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6552 apic_base_msr.data = sregs->apic_base;
6553 apic_base_msr.host_initiated = true;
6554 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6555
4d4ec087 6556 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6557 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6558 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6559
fc78f519 6560 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6561 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6562 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6563 kvm_update_cpuid(vcpu);
63f42e02
XG		 6564
6565 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6566 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6567 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6568 mmu_reset_needed = 1;
6569 }
63f42e02 6570 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6571
6572 if (mmu_reset_needed)
6573 kvm_mmu_reset_context(vcpu);
6574
a50abc3b 6575 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6576 pending_vec = find_first_bit(
6577 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6578 if (pending_vec < max_bits) {
66fd3f7f 6579 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6580 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6581 }
6582
3e6e0aab
GT		 6583 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6584 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6585 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6586 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6587 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6588 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6589
3e6e0aab
GT		 6590 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6591 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6592
5f0269f5
ME		 6593 update_cr8_intercept(vcpu);
6594
9c3e4aab 6595 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6596 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6597 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6598 !is_protmode(vcpu))
9c3e4aab
MT		 6599 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6600
3842d135
AK		 6601 kvm_make_request(KVM_REQ_EVENT, vcpu);
6602
b6c7a5dc
HB		 6603 return 0;
6604}
6605
d0bfb940
JK		 6606int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6607 struct kvm_guest_debug *dbg)
b6c7a5dc 6608{
355be0b9 6609 unsigned long rflags;
ae675ef0 6610 int i, r;
b6c7a5dc 6611
4f926bf2
JK		 6612 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6613 r = -EBUSY;
6614 if (vcpu->arch.exception.pending)
2122ff5e 6615 goto out;
4f926bf2
JK		 6616 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6617 kvm_queue_exception(vcpu, DB_VECTOR);
6618 else
6619 kvm_queue_exception(vcpu, BP_VECTOR);
6620 }
6621
91586a3b
JK		 6622 /*
6623 * Read rflags as long as potentially injected trace flags are still
6624 * filtered out.
6625 */
6626 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6627
6628 vcpu->guest_debug = dbg->control;
6629 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6630 vcpu->guest_debug = 0;
6631
6632 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6633 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6634 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6635 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6636 } else {
6637 for (i = 0; i < KVM_NR_DB_REGS; i++)
6638 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6639 }
c8639010 6640 kvm_update_dr7(vcpu);
ae675ef0 6641
f92653ee
JK		 6642 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6643 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6644 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6645
91586a3b
JK		 6646 /*
6647 * Trigger an rflags update that will inject or remove the trace
6648 * flags.
6649 */
6650 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6651
c8639010 6652 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6653
4f926bf2 6654 r = 0;
d0bfb940 6655
2122ff5e 6656out:
b6c7a5dc
HB		 6657
6658 return r;
6659}
6660
8b006791
ZX		 6661/*
6662 * Translate a guest virtual address to a guest physical address.
6663 */
6664int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6665 struct kvm_translation *tr)
6666{
6667 unsigned long vaddr = tr->linear_address;
6668 gpa_t gpa;
f656ce01 6669 int idx;
8b006791 6670
f656ce01 6671 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6672 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6673 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6674 tr->physical_address = gpa;
6675 tr->valid = gpa != UNMAPPED_GVA;
6676 tr->writeable = 1;
6677 tr->usermode = 0;
8b006791
ZX		 6678
6679 return 0;
6680}
6681
d0752060
HB		 6682int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6683{
98918833
SY		 6684 struct i387_fxsave_struct *fxsave =
6685 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6686
d0752060
HB		 6687 memcpy(fpu->fpr, fxsave->st_space, 128);
6688 fpu->fcw = fxsave->cwd;
6689 fpu->fsw = fxsave->swd;
6690 fpu->ftwx = fxsave->twd;
6691 fpu->last_opcode = fxsave->fop;
6692 fpu->last_ip = fxsave->rip;
6693 fpu->last_dp = fxsave->rdp;
6694 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6695
d0752060
HB		 6696 return 0;
6697}
6698
6699int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6700{
98918833
SY		 6701 struct i387_fxsave_struct *fxsave =
6702 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6703
d0752060
HB		 6704 memcpy(fxsave->st_space, fpu->fpr, 128);
6705 fxsave->cwd = fpu->fcw;
6706 fxsave->swd = fpu->fsw;
6707 fxsave->twd = fpu->ftwx;
6708 fxsave->fop = fpu->last_opcode;
6709 fxsave->rip = fpu->last_ip;
6710 fxsave->rdp = fpu->last_dp;
6711 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6712
d0752060
HB		 6713 return 0;
6714}
6715
10ab25cd 6716int fx_init(struct kvm_vcpu *vcpu)
d0752060 6717{
10ab25cd
JK		 6718 int err;
6719
6720 err = fpu_alloc(&vcpu->arch.guest_fpu);
6721 if (err)
6722 return err;
6723
98918833 6724 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6725
2acf923e
DC		 6726 /*
6727 * Ensure guest xcr0 is valid for loading
6728 */
6729 vcpu->arch.xcr0 = XSTATE_FP;
6730
ad312c7c 6731 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6732
6733 return 0;
d0752060
HB		 6734}
6735EXPORT_SYMBOL_GPL(fx_init);
6736
98918833
SY		 6737static void fx_free(struct kvm_vcpu *vcpu)
6738{
6739 fpu_free(&vcpu->arch.guest_fpu);
6740}
6741
d0752060
HB		 6742void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6743{
2608d7a1 6744 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6745 return;
6746
2acf923e
DC		 6747 /*
6748 * Restore all possible states in the guest,
6749 * and assume host would use all available bits.
6750 * Guest xcr0 would be loaded later.
6751 */
6752 kvm_put_guest_xcr0(vcpu);
d0752060 6753 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6754 __kernel_fpu_begin();
98918833 6755 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6756 trace_kvm_fpu(1);
d0752060 6757}
d0752060
HB		 6758
6759void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6760{
2acf923e
DC		 6761 kvm_put_guest_xcr0(vcpu);
6762
d0752060
HB		 6763 if (!vcpu->guest_fpu_loaded)
6764 return;
6765
6766 vcpu->guest_fpu_loaded = 0;
98918833 6767 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6768 __kernel_fpu_end();
f096ed85 6769 ++vcpu->stat.fpu_reload;
a8eeb04a 6770 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6771 trace_kvm_fpu(0);
d0752060 6772}
e9b11c17
ZX		 6773
6774void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6775{
12f9a48f 6776 kvmclock_reset(vcpu);
7f1ea208 6777
f5f48ee1 6778 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6779 fx_free(vcpu);
e9b11c17
ZX		 6780 kvm_x86_ops->vcpu_free(vcpu);
6781}
6782
6783struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6784 unsigned int id)
6785{
6755bae8
ZA		 6786 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6787 printk_once(KERN_WARNING
6788 "kvm: SMP vm created on host with unstable TSC; "
6789 "guest TSC will not be reliable\n");
26e5215f
AK		 6790 return kvm_x86_ops->vcpu_create(kvm, id);
6791}
e9b11c17 6792
26e5215f
AK		 6793int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6794{
6795 int r;
e9b11c17 6796
0bed3b56 6797 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6798 r = vcpu_load(vcpu);
6799 if (r)
6800 return r;
57f252f2 6801 kvm_vcpu_reset(vcpu);
8a3c1a33 6802 kvm_mmu_setup(vcpu);
e9b11c17 6803 vcpu_put(vcpu);
e9b11c17 6804
26e5215f 6805 return r;
e9b11c17
ZX		 6806}
6807
42897d86
MT		 6808int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6809{
6810 int r;
8fe8ab46 6811 struct msr_data msr;
332967a3 6812 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6813
6814 r = vcpu_load(vcpu);
6815 if (r)
6816 return r;
8fe8ab46
WA		 6817 msr.data = 0x0;
6818 msr.index = MSR_IA32_TSC;
6819 msr.host_initiated = true;
6820 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6821 vcpu_put(vcpu);
6822
332967a3
AJ		 6823 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6824 KVMCLOCK_SYNC_PERIOD);
6825
42897d86
MT		 6826 return r;
6827}
6828
d40ccc62 6829void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6830{
9fc77441 6831 int r;
344d9588
GN		 6832 vcpu->arch.apf.msr_val = 0;
6833
9fc77441
MT		 6834 r = vcpu_load(vcpu);
6835 BUG_ON(r);
e9b11c17
ZX		 6836 kvm_mmu_unload(vcpu);
6837 vcpu_put(vcpu);
6838
98918833 6839 fx_free(vcpu);
e9b11c17
ZX		 6840 kvm_x86_ops->vcpu_free(vcpu);
6841}
6842
66450a21 6843void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6844{
7460fb4a
AK		 6845 atomic_set(&vcpu->arch.nmi_queued, 0);
6846 vcpu->arch.nmi_pending = 0;
448fa4a9 6847 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6848 kvm_clear_interrupt_queue(vcpu);
6849 kvm_clear_exception_queue(vcpu);
448fa4a9 6850
42dbaa5a
JK		 6851 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6852 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6853 kvm_update_dr6(vcpu);
42dbaa5a 6854 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6855 kvm_update_dr7(vcpu);
42dbaa5a 6856
3842d135 6857 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6858 vcpu->arch.apf.msr_val = 0;
c9aaa895 6859 vcpu->arch.st.msr_val = 0;
3842d135 6860
12f9a48f
GC		 6861 kvmclock_reset(vcpu);
6862
af585b92
GN		 6863 kvm_clear_async_pf_completion_queue(vcpu);
6864 kvm_async_pf_hash_reset(vcpu);
6865 vcpu->arch.apf.halted = false;
3842d135 6866
f5132b01
GN		 6867 kvm_pmu_reset(vcpu);
6868
66f7b72e
JS		 6869 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6870 vcpu->arch.regs_avail = ~0;
6871 vcpu->arch.regs_dirty = ~0;
6872
57f252f2 6873 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6874}
6875
66450a21
JK		 6876void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6877{
6878 struct kvm_segment cs;
6879
6880 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6881 cs.selector = vector << 8;
6882 cs.base = vector << 12;
6883 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6884 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6885}
6886
10474ae8 6887int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6888{
ca84d1a2
ZA		 6889 struct kvm *kvm;
6890 struct kvm_vcpu *vcpu;
6891 int i;
0dd6a6ed
ZA		 6892 int ret;
6893 u64 local_tsc;
6894 u64 max_tsc = 0;
6895 bool stable, backwards_tsc = false;
18863bdd
AK		 6896
6897 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6898 ret = kvm_x86_ops->hardware_enable(garbage);
6899 if (ret != 0)
6900 return ret;
6901
6902 local_tsc = native_read_tsc();
6903 stable = !check_tsc_unstable();
6904 list_for_each_entry(kvm, &vm_list, vm_list) {
6905 kvm_for_each_vcpu(i, vcpu, kvm) {
6906 if (!stable && vcpu->cpu == smp_processor_id())
6907 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6908 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6909 backwards_tsc = true;
6910 if (vcpu->arch.last_host_tsc > max_tsc)
6911 max_tsc = vcpu->arch.last_host_tsc;
6912 }
6913 }
6914 }
6915
6916 /*
6917 * Sometimes, even reliable TSCs go backwards. This happens on
6918 * platforms that reset TSC during suspend or hibernate actions, but
6919 * maintain synchronization. We must compensate. Fortunately, we can
6920 * detect that condition here, which happens early in CPU bringup,
6921 * before any KVM threads can be running. Unfortunately, we can't
6922 * bring the TSCs fully up to date with real time, as we aren't yet far
6923 * enough into CPU bringup that we know how much real time has actually
6924 * elapsed; our helper function, get_kernel_ns() will be using boot
6925 * variables that haven't been updated yet.
6926 *
6927 * So we simply find the maximum observed TSC above, then record the
6928 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6929 * the adjustment will be applied. Note that we accumulate
6930 * adjustments, in case multiple suspend cycles happen before some VCPU
6931 * gets a chance to run again. In the event that no KVM threads get a
6932 * chance to run, we will miss the entire elapsed period, as we'll have
6933 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6934 * loose cycle time. This isn't too big a deal, since the loss will be
6935 * uniform across all VCPUs (not to mention the scenario is extremely
6936 * unlikely). It is possible that a second hibernate recovery happens
6937 * much faster than a first, causing the observed TSC here to be
6938 * smaller; this would require additional padding adjustment, which is
6939 * why we set last_host_tsc to the local tsc observed here.
6940 *
6941 * N.B. - this code below runs only on platforms with reliable TSC,
6942 * as that is the only way backwards_tsc is set above. Also note
6943 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6944 * have the same delta_cyc adjustment applied if backwards_tsc
6945 * is detected. Note further, this adjustment is only done once,
6946 * as we reset last_host_tsc on all VCPUs to stop this from being
6947 * called multiple times (one for each physical CPU bringup).
6948 *
4a969980 6949 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6950 * will be compensated by the logic in vcpu_load, which sets the TSC to
6951 * catchup mode. This will catchup all VCPUs to real time, but cannot
6952 * guarantee that they stay in perfect synchronization.
6953 */
6954 if (backwards_tsc) {
6955 u64 delta_cyc = max_tsc - local_tsc;
16a96021 6956 backwards_tsc_observed = true;
0dd6a6ed
ZA		 6957 list_for_each_entry(kvm, &vm_list, vm_list) {
6958 kvm_for_each_vcpu(i, vcpu, kvm) {
6959 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6960 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6961 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6962 &vcpu->requests);
0dd6a6ed
ZA		 6963 }
6964
6965 /*
6966 * We have to disable TSC offset matching.. if you were
6967 * booting a VM while issuing an S4 host suspend....
6968 * you may have some problem. Solving this issue is
6969 * left as an exercise to the reader.
6970 */
6971 kvm->arch.last_tsc_nsec = 0;
6972 kvm->arch.last_tsc_write = 0;
6973 }
6974
6975 }
6976 return 0;
e9b11c17
ZX		 6977}
6978
6979void kvm_arch_hardware_disable(void *garbage)
6980{
6981 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6982 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6983}
6984
6985int kvm_arch_hardware_setup(void)
6986{
6987 return kvm_x86_ops->hardware_setup();
6988}
6989
6990void kvm_arch_hardware_unsetup(void)
6991{
6992 kvm_x86_ops->hardware_unsetup();
6993}
6994
6995void kvm_arch_check_processor_compat(void *rtn)
6996{
6997 kvm_x86_ops->check_processor_compatibility(rtn);
6998}
6999
3e515705
AK		 7000bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7001{
7002 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7003}
7004
54e9818f
GN		 7005struct static_key kvm_no_apic_vcpu __read_mostly;
7006
e9b11c17
ZX		 7007int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7008{
7009 struct page *page;
7010 struct kvm *kvm;
7011 int r;
7012
7013 BUG_ON(vcpu->kvm == NULL);
7014 kvm = vcpu->kvm;
7015
6aef266c 7016 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7017 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7018 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7019 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7020 else
a4535290 7021 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7022
7023 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7024 if (!page) {
7025 r = -ENOMEM;
7026 goto fail;
7027 }
ad312c7c 7028 vcpu->arch.pio_data = page_address(page);
e9b11c17 7029
cc578287 7030 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7031
e9b11c17
ZX		 7032 r = kvm_mmu_create(vcpu);
7033 if (r < 0)
7034 goto fail_free_pio_data;
7035
7036 if (irqchip_in_kernel(kvm)) {
7037 r = kvm_create_lapic(vcpu);
7038 if (r < 0)
7039 goto fail_mmu_destroy;
54e9818f
GN		 7040 } else
7041 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7042
890ca9ae
HY		 7043 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7044 GFP_KERNEL);
7045 if (!vcpu->arch.mce_banks) {
7046 r = -ENOMEM;
443c39bc 7047 goto fail_free_lapic;
890ca9ae
HY		 7048 }
7049 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7050
f1797359
WY		 7051 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7052 r = -ENOMEM;
f5f48ee1 7053 goto fail_free_mce_banks;
f1797359 7054 }
f5f48ee1 7055
66f7b72e
JS		 7056 r = fx_init(vcpu);
7057 if (r)
7058 goto fail_free_wbinvd_dirty_mask;
7059
ba904635 7060 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7061 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7062
7063 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7064 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7065
af585b92 7066 kvm_async_pf_hash_reset(vcpu);
f5132b01 7067 kvm_pmu_init(vcpu);
af585b92 7068
e9b11c17 7069 return 0;
66f7b72e
JS		 7070fail_free_wbinvd_dirty_mask:
7071 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7072fail_free_mce_banks:
7073 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7074fail_free_lapic:
7075 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7076fail_mmu_destroy:
7077 kvm_mmu_destroy(vcpu);
7078fail_free_pio_data:
ad312c7c 7079 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7080fail:
7081 return r;
7082}
7083
7084void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7085{
f656ce01
MT		 7086 int idx;
7087
f5132b01 7088 kvm_pmu_destroy(vcpu);
36cb93fd 7089 kfree(vcpu->arch.mce_banks);
e9b11c17 7090 kvm_free_lapic(vcpu);
f656ce01 7091 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7092 kvm_mmu_destroy(vcpu);
f656ce01 7093 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7094 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7095 if (!irqchip_in_kernel(vcpu->kvm))
7096 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7097}
d19a9cd2 7098
e08b9637 7099int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7100{
e08b9637
CO		 7101 if (type)
7102 return -EINVAL;
7103
f05e70ac 7104 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7105 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7106 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7107 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7108
5550af4d
SY		 7109 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7110 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7111 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7112 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7113 &kvm->arch.irq_sources_bitmap);
5550af4d 7114
038f8c11 7115 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7116 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7117 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7118
7119 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7120
7e44e449 7121 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7122 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7123
d89f5eff 7124 return 0;
d19a9cd2
ZX		 7125}
7126
7127static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7128{
9fc77441
MT		 7129 int r;
7130 r = vcpu_load(vcpu);
7131 BUG_ON(r);
d19a9cd2
ZX		 7132 kvm_mmu_unload(vcpu);
7133 vcpu_put(vcpu);
7134}
7135
7136static void kvm_free_vcpus(struct kvm *kvm)
7137{
7138 unsigned int i;
988a2cae 7139 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7140
7141 /*
7142 * Unpin any mmu pages first.
7143 */
af585b92
GN		 7144 kvm_for_each_vcpu(i, vcpu, kvm) {
7145 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7146 kvm_unload_vcpu_mmu(vcpu);
af585b92 7147 }
988a2cae
GN		 7148 kvm_for_each_vcpu(i, vcpu, kvm)
7149 kvm_arch_vcpu_free(vcpu);
7150
7151 mutex_lock(&kvm->lock);
7152 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7153 kvm->vcpus[i] = NULL;
d19a9cd2 7154
988a2cae
GN		 7155 atomic_set(&kvm->online_vcpus, 0);
7156 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7157}
7158
ad8ba2cd
SY		 7159void kvm_arch_sync_events(struct kvm *kvm)
7160{
332967a3 7161 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7162 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7163 kvm_free_all_assigned_devices(kvm);
aea924f6 7164 kvm_free_pit(kvm);
ad8ba2cd
SY		 7165}
7166
d19a9cd2
ZX		 7167void kvm_arch_destroy_vm(struct kvm *kvm)
7168{
27469d29
AH		 7169 if (current->mm == kvm->mm) {
7170 /*
7171 * Free memory regions allocated on behalf of userspace,
7172 * unless the the memory map has changed due to process exit
7173 * or fd copying.
7174 */
7175 struct kvm_userspace_memory_region mem;
7176 memset(&mem, 0, sizeof(mem));
7177 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7178 kvm_set_memory_region(kvm, &mem);
7179
7180 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7181 kvm_set_memory_region(kvm, &mem);
7182
7183 mem.slot = TSS_PRIVATE_MEMSLOT;
7184 kvm_set_memory_region(kvm, &mem);
7185 }
6eb55818 7186 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7187 kfree(kvm->arch.vpic);
7188 kfree(kvm->arch.vioapic);
d19a9cd2 7189 kvm_free_vcpus(kvm);
3d45830c
AK		 7190 if (kvm->arch.apic_access_page)
7191 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7192 if (kvm->arch.ept_identity_pagetable)
7193 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7194 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7195}
0de10343 7196
5587027c 7197void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7198 struct kvm_memory_slot *dont)
7199{
7200 int i;
7201
d89cc617
TY		 7202 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7203 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7204 kvm_kvfree(free->arch.rmap[i]);
7205 free->arch.rmap[i] = NULL;
77d11309 7206 }
d89cc617
TY		 7207 if (i == 0)
7208 continue;
7209
7210 if (!dont || free->arch.lpage_info[i - 1] !=
7211 dont->arch.lpage_info[i - 1]) {
7212 kvm_kvfree(free->arch.lpage_info[i - 1]);
7213 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7214 }
7215 }
7216}
7217
5587027c
AK		 7218int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7219 unsigned long npages)
db3fe4eb
TY		 7220{
7221 int i;
7222
d89cc617 7223 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7224 unsigned long ugfn;
7225 int lpages;
d89cc617 7226 int level = i + 1;
db3fe4eb
TY		 7227
7228 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7229 slot->base_gfn, level) + 1;
7230
d89cc617
TY		 7231 slot->arch.rmap[i] =
7232 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7233 if (!slot->arch.rmap[i])
77d11309 7234 goto out_free;
d89cc617
TY		 7235 if (i == 0)
7236 continue;
77d11309 7237
d89cc617
TY		 7238 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7239 sizeof(*slot->arch.lpage_info[i - 1]));
7240 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7241 goto out_free;
7242
7243 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7244 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7245 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7246 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7247 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7248 /*
7249 * If the gfn and userspace address are not aligned wrt each
7250 * other, or if explicitly asked to, disable large page
7251 * support for this slot
7252 */
7253 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7254 !kvm_largepages_enabled()) {
7255 unsigned long j;
7256
7257 for (j = 0; j < lpages; ++j)
d89cc617 7258 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7259 }
7260 }
7261
7262 return 0;
7263
7264out_free:
d89cc617
TY		 7265 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7266 kvm_kvfree(slot->arch.rmap[i]);
7267 slot->arch.rmap[i] = NULL;
7268 if (i == 0)
7269 continue;
7270
7271 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7272 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7273 }
7274 return -ENOMEM;
7275}
7276
e59dbe09
TY		 7277void kvm_arch_memslots_updated(struct kvm *kvm)
7278{
e6dff7d1
TY		 7279 /*
7280 * memslots->generation has been incremented.
7281 * mmio generation may have reached its maximum value.
7282 */
7283 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7284}
7285
f7784b8e
MT		 7286int kvm_arch_prepare_memory_region(struct kvm *kvm,
7287 struct kvm_memory_slot *memslot,
f7784b8e 7288 struct kvm_userspace_memory_region *mem,
7b6195a9 7289 enum kvm_mr_change change)
0de10343 7290{
7a905b14
TY		 7291 /*
7292 * Only private memory slots need to be mapped here since
7293 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7294 */
7b6195a9 7295 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7296 unsigned long userspace_addr;
604b38ac 7297
7a905b14
TY		 7298 /*
7299 * MAP_SHARED to prevent internal slot pages from being moved
7300 * by fork()/COW.
7301 */
7b6195a9 7302 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7303 PROT_READ | PROT_WRITE,
7304 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7305
7a905b14
TY		 7306 if (IS_ERR((void *)userspace_addr))
7307 return PTR_ERR((void *)userspace_addr);
604b38ac 7308
7a905b14 7309 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7310 }
7311
f7784b8e
MT		 7312 return 0;
7313}
7314
7315void kvm_arch_commit_memory_region(struct kvm *kvm,
7316 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7317 const struct kvm_memory_slot *old,
7318 enum kvm_mr_change change)
f7784b8e
MT		 7319{
7320
8482644a 7321 int nr_mmu_pages = 0;
f7784b8e 7322
8482644a 7323 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7324 int ret;
7325
8482644a
TY		 7326 ret = vm_munmap(old->userspace_addr,
7327 old->npages * PAGE_SIZE);
f7784b8e
MT		 7328 if (ret < 0)
7329 printk(KERN_WARNING
7330 "kvm_vm_ioctl_set_memory_region: "
7331 "failed to munmap memory\n");
7332 }
7333
48c0e4e9
XG		 7334 if (!kvm->arch.n_requested_mmu_pages)
7335 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7336
48c0e4e9 7337 if (nr_mmu_pages)
0de10343 7338 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7339 /*
7340 * Write protect all pages for dirty logging.
c126d94f
XG		 7341 *
7342 * All the sptes including the large sptes which point to this
7343 * slot are set to readonly. We can not create any new large
7344 * spte on this slot until the end of the logging.
7345 *
7346 * See the comments in fast_page_fault().
c972f3b1 7347 */
8482644a 7348 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7349 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7350}
1d737c8a 7351
2df72e9b 7352void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7353{
6ca18b69 7354 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7355}
7356
2df72e9b
MT		 7357void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7358 struct kvm_memory_slot *slot)
7359{
6ca18b69 7360 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7361}
7362
1d737c8a
ZX		 7363int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7364{
b6b8a145
JK		 7365 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7366 kvm_x86_ops->check_nested_events(vcpu, false);
7367
af585b92
GN		 7368 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7369 !vcpu->arch.apf.halted)
7370 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7371 || kvm_apic_has_events(vcpu)
6aef266c 7372 || vcpu->arch.pv.pv_unhalted
7460fb4a 7373 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7374 (kvm_arch_interrupt_allowed(vcpu) &&
7375 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7376}
5736199a 7377
b6d33834 7378int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7379{
b6d33834 7380 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7381}
78646121
GN		 7382
7383int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7384{
7385 return kvm_x86_ops->interrupt_allowed(vcpu);
7386}
229456fc 7387
f92653ee
JK		 7388bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7389{
7390 unsigned long current_rip = kvm_rip_read(vcpu) +
7391 get_segment_base(vcpu, VCPU_SREG_CS);
7392
7393 return current_rip == linear_rip;
7394}
7395EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7396
94fe45da
JK		 7397unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7398{
7399 unsigned long rflags;
7400
7401 rflags = kvm_x86_ops->get_rflags(vcpu);
7402 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7403 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7404 return rflags;
7405}
7406EXPORT_SYMBOL_GPL(kvm_get_rflags);
7407
7408void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7409{
7410 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7411 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7412 rflags |= X86_EFLAGS_TF;
94fe45da 7413 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7414 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7415}
7416EXPORT_SYMBOL_GPL(kvm_set_rflags);
7417
56028d08
GN		 7418void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7419{
7420 int r;
7421
fb67e14f 7422 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7423 work->wakeup_all)
56028d08
GN		 7424 return;
7425
7426 r = kvm_mmu_reload(vcpu);
7427 if (unlikely(r))
7428 return;
7429
fb67e14f
XG		 7430 if (!vcpu->arch.mmu.direct_map &&
7431 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7432 return;
7433
56028d08
GN		 7434 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7435}
7436
af585b92
GN		 7437static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7438{
7439 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7440}
7441
7442static inline u32 kvm_async_pf_next_probe(u32 key)
7443{
7444 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7445}
7446
7447static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7448{
7449 u32 key = kvm_async_pf_hash_fn(gfn);
7450
7451 while (vcpu->arch.apf.gfns[key] != ~0)
7452 key = kvm_async_pf_next_probe(key);
7453
7454 vcpu->arch.apf.gfns[key] = gfn;
7455}
7456
7457static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7458{
7459 int i;
7460 u32 key = kvm_async_pf_hash_fn(gfn);
7461
7462 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7463 (vcpu->arch.apf.gfns[key] != gfn &&
7464 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7465 key = kvm_async_pf_next_probe(key);
7466
7467 return key;
7468}
7469
7470bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7471{
7472 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7473}
7474
7475static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7476{
7477 u32 i, j, k;
7478
7479 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7480 while (true) {
7481 vcpu->arch.apf.gfns[i] = ~0;
7482 do {
7483 j = kvm_async_pf_next_probe(j);
7484 if (vcpu->arch.apf.gfns[j] == ~0)
7485 return;
7486 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7487 /*
7488 * k lies cyclically in ]i,j]
7489 * | i.k.j |
7490 * |....j i.k.| or |.k..j i...|
7491 */
7492 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7493 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7494 i = j;
7495 }
7496}
7497
7c90705b
GN		 7498static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7499{
7500
7501 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7502 sizeof(val));
7503}
7504
af585b92
GN		 7505void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7506 struct kvm_async_pf *work)
7507{
6389ee94
AK		 7508 struct x86_exception fault;
7509
7c90705b 7510 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7511 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7512
7513 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7514 (vcpu->arch.apf.send_user_only &&
7515 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7516 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7517 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7518 fault.vector = PF_VECTOR;
7519 fault.error_code_valid = true;
7520 fault.error_code = 0;
7521 fault.nested_page_fault = false;
7522 fault.address = work->arch.token;
7523 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7524 }
af585b92
GN		 7525}
7526
7527void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7528 struct kvm_async_pf *work)
7529{
6389ee94
AK		 7530 struct x86_exception fault;
7531
7c90705b 7532 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7533 if (work->wakeup_all)
7c90705b
GN		 7534 work->arch.token = ~0; /* broadcast wakeup */
7535 else
7536 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7537
7538 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7539 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7540 fault.vector = PF_VECTOR;
7541 fault.error_code_valid = true;
7542 fault.error_code = 0;
7543 fault.nested_page_fault = false;
7544 fault.address = work->arch.token;
7545 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7546 }
e6d53e3b 7547 vcpu->arch.apf.halted = false;
a4fa1635 7548 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7549}
7550
7551bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7552{
7553 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7554 return true;
7555 else
7556 return !kvm_event_needs_reinjection(vcpu) &&
7557 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7558}
7559
e0f0bbc5
AW		 7560void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7561{
7562 atomic_inc(&kvm->arch.noncoherent_dma_count);
7563}
7564EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7565
7566void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7567{
7568 atomic_dec(&kvm->arch.noncoherent_dma_count);
7569}
7570EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7571
7572bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7573{
7574 return atomic_read(&kvm->arch.noncoherent_dma_count);
7575}
7576EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7577
229456fc
MT		 7578EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7579EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7580EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7581EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7582EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7583EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7584EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7586EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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