]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/block/nvme-core.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: don't use PREPARE_DELAYED_WORK
[mirror_ubuntu-bionic-kernel.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
b60503ba
MW		 24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
b60503ba
MW		 33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
b60503ba
MW		 40#include <linux/sched.h>
41#include <linux/slab.h>
42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b60503ba
MW		 46#define NVME_Q_DEPTH 1024
47#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
48#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 49#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 50
51static int nvme_major;
52module_param(nvme_major, int, 0);
53
58ffacb5
MW		 54static int use_threaded_interrupts;
55module_param(use_threaded_interrupts, int, 0);
56
1fa6aead
MW		 57static DEFINE_SPINLOCK(dev_list_lock);
58static LIST_HEAD(dev_list);
59static struct task_struct *nvme_thread;
9a6b9458 60static struct workqueue_struct *nvme_workq;
1fa6aead 61
d4b4ff8e
KB		 62static void nvme_reset_failed_dev(struct work_struct *ws);
63
4d115420
KB		 64struct async_cmd_info {
65 struct kthread_work work;
66 struct kthread_worker *worker;
67 u32 result;
68 int status;
69 void *ctx;
70};
1fa6aead 71
b60503ba
MW		 72/*
73 * An NVM Express queue. Each device has at least two (one for admin
74 * commands and one for I/O commands).
75 */
76struct nvme_queue {
77 struct device *q_dmadev;
091b6092 78 struct nvme_dev *dev;
3193f07b 79 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 80 spinlock_t q_lock;
81 struct nvme_command *sq_cmds;
82 volatile struct nvme_completion *cqes;
83 dma_addr_t sq_dma_addr;
84 dma_addr_t cq_dma_addr;
85 wait_queue_head_t sq_full;
1fa6aead 86 wait_queue_t sq_cong_wait;
b60503ba
MW		 87 struct bio_list sq_cong;
88 u32 __iomem *q_db;
89 u16 q_depth;
90 u16 cq_vector;
91 u16 sq_head;
92 u16 sq_tail;
93 u16 cq_head;
c30341dc 94 u16 qid;
e9539f47
MW		 95 u8 cq_phase;
96 u8 cqe_seen;
22404274 97 u8 q_suspended;
4d115420 98 struct async_cmd_info cmdinfo;
b60503ba
MW		 99 unsigned long cmdid_data[];
100};
101
102/*
103 * Check we didin't inadvertently grow the command struct
104 */
105static inline void _nvme_check_size(void)
106{
107 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
108 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 112 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 113 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 114 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
115 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
116 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
117 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 118 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 119}
120
5c1281a3 121typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 122 struct nvme_completion *);
123
e85248e5 124struct nvme_cmd_info {
c2f5b650
MW		 125 nvme_completion_fn fn;
126 void *ctx;
e85248e5 127 unsigned long timeout;
c30341dc 128 int aborted;
e85248e5
MW		 129};
130
131static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
132{
133 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
134}
135
22404274
KB		 136static unsigned nvme_queue_extra(int depth)
137{
138 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
139}
140
b60503ba 141/**
714a7a22
MW		 142 * alloc_cmdid() - Allocate a Command ID
143 * @nvmeq: The queue that will be used for this command
144 * @ctx: A pointer that will be passed to the handler
c2f5b650 145 * @handler: The function to call on completion
b60503ba
MW		 146 *
147 * Allocate a Command ID for a queue. The data passed in will
148 * be passed to the completion handler. This is implemented by using
149 * the bottom two bits of the ctx pointer to store the handler ID.
150 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
151 * We can change this if it becomes a problem.
184d2944
MW		 152 *
153 * May be called with local interrupts disabled and the q_lock held,
154 * or with interrupts enabled and no locks held.
b60503ba 155 */
c2f5b650
MW		 156static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
157 nvme_completion_fn handler, unsigned timeout)
b60503ba 158{
e6d15f79 159 int depth = nvmeq->q_depth - 1;
e85248e5 160 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 161 int cmdid;
162
b60503ba
MW		 163 do {
164 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
165 if (cmdid >= depth)
166 return -EBUSY;
167 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
168
c2f5b650
MW		 169 info[cmdid].fn = handler;
170 info[cmdid].ctx = ctx;
e85248e5 171 info[cmdid].timeout = jiffies + timeout;
c30341dc 172 info[cmdid].aborted = 0;
b60503ba
MW		 173 return cmdid;
174}
175
176static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 177 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 178{
179 int cmdid;
180 wait_event_killable(nvmeq->sq_full,
e85248e5 181 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 182 return (cmdid < 0) ? -EINTR : cmdid;
183}
184
c2f5b650
MW		 185/* Special values must be less than 0x1000 */
186#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 187#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
188#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
189#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 190#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 191#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 192
5c1281a3 193static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 194 struct nvme_completion *cqe)
195{
196 if (ctx == CMD_CTX_CANCELLED)
197 return;
198 if (ctx == CMD_CTX_FLUSH)
199 return;
c30341dc
KB		 200 if (ctx == CMD_CTX_ABORT) {
201 ++dev->abort_limit;
202 return;
203 }
c2f5b650 204 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 205 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 206 "completed id %d twice on queue %d\n",
207 cqe->command_id, le16_to_cpup(&cqe->sq_id));
208 return;
209 }
210 if (ctx == CMD_CTX_INVALID) {
5c1281a3 211 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 212 "invalid id %d completed on queue %d\n",
213 cqe->command_id, le16_to_cpup(&cqe->sq_id));
214 return;
215 }
216
5c1281a3 217 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 218}
219
4d115420
KB		 220static void async_completion(struct nvme_dev *dev, void *ctx,
221 struct nvme_completion *cqe)
222{
223 struct async_cmd_info *cmdinfo = ctx;
224 cmdinfo->result = le32_to_cpup(&cqe->result);
225 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
226 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
227}
228
184d2944
MW		 229/*
230 * Called with local interrupts disabled and the q_lock held. May not sleep.
231 */
c2f5b650
MW		 232static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
233 nvme_completion_fn *fn)
b60503ba 234{
c2f5b650 235 void *ctx;
e85248e5 236 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 237
c2f5b650
MW		 238 if (cmdid >= nvmeq->q_depth) {
239 *fn = special_completion;
48e3d398 240 return CMD_CTX_INVALID;
c2f5b650 241 }
859361a2
KB		 242 if (fn)
243 *fn = info[cmdid].fn;
c2f5b650
MW		 244 ctx = info[cmdid].ctx;
245 info[cmdid].fn = special_completion;
e85248e5 246 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 247 clear_bit(cmdid, nvmeq->cmdid_data);
248 wake_up(&nvmeq->sq_full);
c2f5b650 249 return ctx;
b60503ba
MW		 250}
251
c2f5b650
MW		 252static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
253 nvme_completion_fn *fn)
3c0cf138 254{
c2f5b650 255 void *ctx;
e85248e5 256 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 257 if (fn)
258 *fn = info[cmdid].fn;
259 ctx = info[cmdid].ctx;
260 info[cmdid].fn = special_completion;
e85248e5 261 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 262 return ctx;
3c0cf138
MW		 263}
264
5d0f6131 265struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
b60503ba 266{
040a93b5 267 return dev->queues[get_cpu() + 1];
b60503ba
MW		 268}
269
5d0f6131 270void put_nvmeq(struct nvme_queue *nvmeq)
b60503ba 271{
1b23484b 272 put_cpu();
b60503ba
MW		 273}
274
275/**
714a7a22 276 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 277 * @nvmeq: The queue to use
278 * @cmd: The command to send
279 *
280 * Safe to use from interrupt context
281 */
282static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
283{
284 unsigned long flags;
285 u16 tail;
b60503ba
MW		 286 spin_lock_irqsave(&nvmeq->q_lock, flags);
287 tail = nvmeq->sq_tail;
288 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 289 if (++tail == nvmeq->q_depth)
290 tail = 0;
7547881d 291 writel(tail, nvmeq->q_db);
b60503ba
MW		 292 nvmeq->sq_tail = tail;
293 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
294
295 return 0;
296}
297
eca18b23 298static __le64 **iod_list(struct nvme_iod *iod)
e025344c 299{
eca18b23 300 return ((void *)iod) + iod->offset;
e025344c
SMM		 301}
302
eca18b23
MW		 303/*
304 * Will slightly overestimate the number of pages needed. This is OK
305 * as it only leads to a small amount of wasted memory for the lifetime of
306 * the I/O.
307 */
308static int nvme_npages(unsigned size)
309{
310 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
311 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
312}
b60503ba 313
eca18b23
MW		 314static struct nvme_iod *
315nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 316{
eca18b23
MW		 317 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
318 sizeof(__le64 *) * nvme_npages(nbytes) +
319 sizeof(struct scatterlist) * nseg, gfp);
320
321 if (iod) {
322 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
323 iod->npages = -1;
324 iod->length = nbytes;
2b196034 325 iod->nents = 0;
6198221f 326 iod->start_time = jiffies;
eca18b23
MW		 327 }
328
329 return iod;
b60503ba
MW		 330}
331
5d0f6131 332void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 333{
eca18b23
MW		 334 const int last_prp = PAGE_SIZE / 8 - 1;
335 int i;
336 __le64 **list = iod_list(iod);
337 dma_addr_t prp_dma = iod->first_dma;
338
339 if (iod->npages == 0)
340 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
341 for (i = 0; i < iod->npages; i++) {
342 __le64 *prp_list = list[i];
343 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
344 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
345 prp_dma = next_prp_dma;
346 }
347 kfree(iod);
b60503ba
MW		 348}
349
6198221f
KB		 350static void nvme_start_io_acct(struct bio *bio)
351{
352 struct gendisk *disk = bio->bi_bdev->bd_disk;
353 const int rw = bio_data_dir(bio);
354 int cpu = part_stat_lock();
355 part_round_stats(cpu, &disk->part0);
356 part_stat_inc(cpu, &disk->part0, ios[rw]);
357 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
358 part_inc_in_flight(&disk->part0, rw);
359 part_stat_unlock();
360}
361
362static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
363{
364 struct gendisk *disk = bio->bi_bdev->bd_disk;
365 const int rw = bio_data_dir(bio);
366 unsigned long duration = jiffies - start_time;
367 int cpu = part_stat_lock();
368 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
369 part_round_stats(cpu, &disk->part0);
370 part_dec_in_flight(&disk->part0, rw);
371 part_stat_unlock();
372}
373
5c1281a3 374static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 375 struct nvme_completion *cqe)
376{
eca18b23
MW		 377 struct nvme_iod *iod = ctx;
378 struct bio *bio = iod->private;
b60503ba
MW		 379 u16 status = le16_to_cpup(&cqe->status) >> 1;
380
9e59d091 381 if (iod->nents) {
2b196034 382 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 383 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 384 nvme_end_io_acct(bio, iod->start_time);
385 }
eca18b23 386 nvme_free_iod(dev, iod);
427e9708 387 if (status)
1ad2f893 388 bio_endio(bio, -EIO);
427e9708 389 else
1ad2f893 390 bio_endio(bio, 0);
b60503ba
MW		 391}
392
184d2944 393/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV		 394int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
395 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 396{
99802a7a 397 struct dma_pool *pool;
eca18b23
MW		 398 int length = total_len;
399 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 400 int dma_len = sg_dma_len(sg);
401 u64 dma_addr = sg_dma_address(sg);
402 int offset = offset_in_page(dma_addr);
e025344c 403 __le64 *prp_list;
eca18b23 404 __le64 **list = iod_list(iod);
e025344c 405 dma_addr_t prp_dma;
eca18b23 406 int nprps, i;
ff22b54f
MW		 407
408 cmd->prp1 = cpu_to_le64(dma_addr);
409 length -= (PAGE_SIZE - offset);
410 if (length <= 0)
eca18b23 411 return total_len;
ff22b54f
MW		 412
413 dma_len -= (PAGE_SIZE - offset);
414 if (dma_len) {
415 dma_addr += (PAGE_SIZE - offset);
416 } else {
417 sg = sg_next(sg);
418 dma_addr = sg_dma_address(sg);
419 dma_len = sg_dma_len(sg);
420 }
421
422 if (length <= PAGE_SIZE) {
423 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 424 return total_len;
e025344c
SMM		 425 }
426
427 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 428 if (nprps <= (256 / 8)) {
429 pool = dev->prp_small_pool;
eca18b23 430 iod->npages = 0;
99802a7a
MW		 431 } else {
432 pool = dev->prp_page_pool;
eca18b23 433 iod->npages = 1;
99802a7a
MW		 434 }
435
b77954cb
MW		 436 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
437 if (!prp_list) {
438 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 439 iod->npages = -1;
440 return (total_len - length) + PAGE_SIZE;
b77954cb 441 }
eca18b23
MW		 442 list[0] = prp_list;
443 iod->first_dma = prp_dma;
e025344c
SMM		 444 cmd->prp2 = cpu_to_le64(prp_dma);
445 i = 0;
446 for (;;) {
7523d834 447 if (i == PAGE_SIZE / 8) {
e025344c 448 __le64 *old_prp_list = prp_list;
b77954cb 449 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 450 if (!prp_list)
451 return total_len - length;
452 list[iod->npages++] = prp_list;
7523d834
MW		 453 prp_list[0] = old_prp_list[i - 1];
454 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
455 i = 1;
e025344c
SMM		 456 }
457 prp_list[i++] = cpu_to_le64(dma_addr);
458 dma_len -= PAGE_SIZE;
459 dma_addr += PAGE_SIZE;
460 length -= PAGE_SIZE;
461 if (length <= 0)
462 break;
463 if (dma_len > 0)
464 continue;
465 BUG_ON(dma_len < 0);
466 sg = sg_next(sg);
467 dma_addr = sg_dma_address(sg);
468 dma_len = sg_dma_len(sg);
ff22b54f
MW		 469 }
470
eca18b23 471 return total_len;
ff22b54f
MW		 472}
473
427e9708 474static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 475 int len)
427e9708 476{
20d0189b
KO		 477 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
478 if (!split)
427e9708
KB		 479 return -ENOMEM;
480
20d0189b
KO		 481 bio_chain(split, bio);
482
427e9708
KB		 483 if (bio_list_empty(&nvmeq->sq_cong))
484 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 485 bio_list_add(&nvmeq->sq_cong, split);
486 bio_list_add(&nvmeq->sq_cong, bio);
427e9708
KB		 487
488 return 0;
489}
490
1ad2f893
MW		 491/* NVMe scatterlists require no holes in the virtual address */
492#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
493 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
494
427e9708 495static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 496 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
497{
7988613b
KO		 498 struct bio_vec bvec, bvprv;
499 struct bvec_iter iter;
76830840 500 struct scatterlist *sg = NULL;
7988613b
KO		 501 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
502 int first = 1;
159b67d7
KB		 503
504 if (nvmeq->dev->stripe_size)
505 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 506 ((bio->bi_iter.bi_sector << 9) &
507 (nvmeq->dev->stripe_size - 1));
b60503ba 508
eca18b23 509 sg_init_table(iod->sg, psegs);
7988613b
KO		 510 bio_for_each_segment(bvec, bio, iter) {
511 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
512 sg->length += bvec.bv_len;
76830840 513 } else {
7988613b
KO		 514 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
515 return nvme_split_and_submit(bio, nvmeq,
20d0189b 516 length);
427e9708 517
eca18b23 518 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 519 sg_set_page(sg, bvec.bv_page,
520 bvec.bv_len, bvec.bv_offset);
76830840
MW		 521 nsegs++;
522 }
159b67d7 523
7988613b 524 if (split_len - length < bvec.bv_len)
20d0189b 525 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 526 length += bvec.bv_len;
76830840 527 bvprv = bvec;
7988613b 528 first = 0;
b60503ba 529 }
eca18b23 530 iod->nents = nsegs;
76830840 531 sg_mark_end(sg);
427e9708 532 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 533 return -ENOMEM;
427e9708 534
4f024f37 535 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 536 return length;
b60503ba
MW		 537}
538
0e5e4f0e
KB		 539/*
540 * We reuse the small pool to allocate the 16-byte range here as it is not
541 * worth having a special pool for these or additional cases to handle freeing
542 * the iod.
543 */
544static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
545 struct bio *bio, struct nvme_iod *iod, int cmdid)
546{
547 struct nvme_dsm_range *range;
548 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
549
550 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
551 &iod->first_dma);
552 if (!range)
553 return -ENOMEM;
554
555 iod_list(iod)[0] = (__le64 *)range;
556 iod->npages = 0;
557
558 range->cattr = cpu_to_le32(0);
4f024f37
KO		 559 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
560 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 561
562 memset(cmnd, 0, sizeof(*cmnd));
563 cmnd->dsm.opcode = nvme_cmd_dsm;
564 cmnd->dsm.command_id = cmdid;
565 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
566 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
567 cmnd->dsm.nr = 0;
568 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
569
570 if (++nvmeq->sq_tail == nvmeq->q_depth)
571 nvmeq->sq_tail = 0;
572 writel(nvmeq->sq_tail, nvmeq->q_db);
573
574 return 0;
575}
576
00df5cb4
MW		 577static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
578 int cmdid)
579{
580 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
581
582 memset(cmnd, 0, sizeof(*cmnd));
583 cmnd->common.opcode = nvme_cmd_flush;
584 cmnd->common.command_id = cmdid;
585 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
586
587 if (++nvmeq->sq_tail == nvmeq->q_depth)
588 nvmeq->sq_tail = 0;
589 writel(nvmeq->sq_tail, nvmeq->q_db);
590
591 return 0;
592}
593
5d0f6131 594int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 595{
596 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 597 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 598 if (unlikely(cmdid < 0))
599 return cmdid;
600
601 return nvme_submit_flush(nvmeq, ns, cmdid);
602}
603
184d2944
MW		 604/*
605 * Called with local interrupts disabled and the q_lock held. May not sleep.
606 */
b60503ba
MW		 607static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
608 struct bio *bio)
609{
ff22b54f 610 struct nvme_command *cmnd;
eca18b23 611 struct nvme_iod *iod;
b60503ba 612 enum dma_data_direction dma_dir;
1287dabd 613 int cmdid, length, result;
b60503ba
MW		 614 u16 control;
615 u32 dsmgmt;
b60503ba
MW		 616 int psegs = bio_phys_segments(ns->queue, bio);
617
00df5cb4
MW		 618 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
619 result = nvme_submit_flush_data(nvmeq, ns);
620 if (result)
621 return result;
622 }
623
1287dabd 624 result = -ENOMEM;
4f024f37 625 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
eca18b23 626 if (!iod)
eeee3226 627 goto nomem;
eca18b23 628 iod->private = bio;
b60503ba 629
eeee3226 630 result = -EBUSY;
ff976d72 631 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 632 if (unlikely(cmdid < 0))
eca18b23 633 goto free_iod;
b60503ba 634
0e5e4f0e
KB		 635 if (bio->bi_rw & REQ_DISCARD) {
636 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
637 if (result)
638 goto free_cmdid;
639 return result;
640 }
00df5cb4
MW		 641 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
642 return nvme_submit_flush(nvmeq, ns, cmdid);
643
b60503ba
MW		 644 control = 0;
645 if (bio->bi_rw & REQ_FUA)
646 control |= NVME_RW_FUA;
647 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
648 control |= NVME_RW_LR;
649
650 dsmgmt = 0;
651 if (bio->bi_rw & REQ_RAHEAD)
652 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
653
ff22b54f 654 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 655
b8deb62c 656 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 657 if (bio_data_dir(bio)) {
ff22b54f 658 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 659 dma_dir = DMA_TO_DEVICE;
660 } else {
ff22b54f 661 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 662 dma_dir = DMA_FROM_DEVICE;
663 }
664
427e9708
KB		 665 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
666 if (result <= 0)
859361a2 667 goto free_cmdid;
1ad2f893 668 length = result;
b60503ba 669
ff22b54f
MW		 670 cmnd->rw.command_id = cmdid;
671 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 672 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
673 GFP_ATOMIC);
4f024f37 674 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
1ad2f893 675 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 676 cmnd->rw.control = cpu_to_le16(control);
677 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 678
6198221f 679 nvme_start_io_acct(bio);
b60503ba
MW		 680 if (++nvmeq->sq_tail == nvmeq->q_depth)
681 nvmeq->sq_tail = 0;
7547881d 682 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 683
1974b1ae
MW		 684 return 0;
685
859361a2
KB		 686 free_cmdid:
687 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 688 free_iod:
689 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 690 nomem:
691 return result;
b60503ba
MW		 692}
693
e9539f47 694static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 695{
82123460 696 u16 head, phase;
b60503ba 697
b60503ba 698 head = nvmeq->cq_head;
82123460 699 phase = nvmeq->cq_phase;
b60503ba
MW		 700
701 for (;;) {
c2f5b650
MW		 702 void *ctx;
703 nvme_completion_fn fn;
b60503ba 704 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 705 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 706 break;
707 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
708 if (++head == nvmeq->q_depth) {
709 head = 0;
82123460 710 phase = !phase;
b60503ba
MW		 711 }
712
c2f5b650 713 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 714 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 715 }
716
717 /* If the controller ignores the cq head doorbell and continuously
718 * writes to the queue, it is theoretically possible to wrap around
719 * the queue twice and mistakenly return IRQ_NONE. Linux only
720 * requires that 0.1% of your interrupts are handled, so this isn't
721 * a big problem.
722 */
82123460 723 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 724 return 0;
b60503ba 725
b80d5ccc 726 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 727 nvmeq->cq_head = head;
82123460 728 nvmeq->cq_phase = phase;
b60503ba 729
e9539f47
MW		 730 nvmeq->cqe_seen = 1;
731 return 1;
b60503ba
MW		 732}
733
7d822457
MW		 734static void nvme_make_request(struct request_queue *q, struct bio *bio)
735{
736 struct nvme_ns *ns = q->queuedata;
737 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
738 int result = -EBUSY;
739
cd638946
KB		 740 if (!nvmeq) {
741 put_nvmeq(NULL);
742 bio_endio(bio, -EIO);
743 return;
744 }
745
7d822457 746 spin_lock_irq(&nvmeq->q_lock);
22404274 747 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 748 result = nvme_submit_bio_queue(nvmeq, ns, bio);
749 if (unlikely(result)) {
750 if (bio_list_empty(&nvmeq->sq_cong))
751 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
752 bio_list_add(&nvmeq->sq_cong, bio);
753 }
754
755 nvme_process_cq(nvmeq);
756 spin_unlock_irq(&nvmeq->q_lock);
757 put_nvmeq(nvmeq);
758}
759
b60503ba 760static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 761{
762 irqreturn_t result;
763 struct nvme_queue *nvmeq = data;
764 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 765 nvme_process_cq(nvmeq);
766 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
767 nvmeq->cqe_seen = 0;
58ffacb5
MW		 768 spin_unlock(&nvmeq->q_lock);
769 return result;
770}
771
772static irqreturn_t nvme_irq_check(int irq, void *data)
773{
774 struct nvme_queue *nvmeq = data;
775 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
776 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
777 return IRQ_NONE;
778 return IRQ_WAKE_THREAD;
779}
780
3c0cf138
MW		 781static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
782{
783 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 784 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 785 spin_unlock_irq(&nvmeq->q_lock);
786}
787
c2f5b650
MW		 788struct sync_cmd_info {
789 struct task_struct *task;
790 u32 result;
791 int status;
792};
793
5c1281a3 794static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 795 struct nvme_completion *cqe)
796{
797 struct sync_cmd_info *cmdinfo = ctx;
798 cmdinfo->result = le32_to_cpup(&cqe->result);
799 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
800 wake_up_process(cmdinfo->task);
801}
802
b60503ba
MW		 803/*
804 * Returns 0 on success. If the result is negative, it's a Linux error code;
805 * if the result is positive, it's an NVM Express status code
806 */
5d0f6131
VV		 807int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
808 u32 *result, unsigned timeout)
b60503ba
MW		 809{
810 int cmdid;
811 struct sync_cmd_info cmdinfo;
812
813 cmdinfo.task = current;
814 cmdinfo.status = -EINTR;
815
c2f5b650 816 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
e85248e5 817 timeout);
b60503ba
MW		 818 if (cmdid < 0)
819 return cmdid;
820 cmd->common.command_id = cmdid;
821
3c0cf138
MW		 822 set_current_state(TASK_KILLABLE);
823 nvme_submit_cmd(nvmeq, cmd);
78f8d257 824 schedule_timeout(timeout);
b60503ba 825
3c0cf138
MW		 826 if (cmdinfo.status == -EINTR) {
827 nvme_abort_command(nvmeq, cmdid);
828 return -EINTR;
829 }
830
b60503ba
MW		 831 if (result)
832 *result = cmdinfo.result;
833
834 return cmdinfo.status;
835}
836
4d115420
KB		 837static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
838 struct nvme_command *cmd,
839 struct async_cmd_info *cmdinfo, unsigned timeout)
840{
841 int cmdid;
842
843 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
844 if (cmdid < 0)
845 return cmdid;
846 cmdinfo->status = -EINTR;
847 cmd->common.command_id = cmdid;
848 nvme_submit_cmd(nvmeq, cmd);
849 return 0;
850}
851
5d0f6131 852int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 853 u32 *result)
854{
e85248e5 855 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 856}
857
4d115420
KB		 858static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
859 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
860{
861 return nvme_submit_async_cmd(dev->queues[0], cmd, cmdinfo,
862 ADMIN_TIMEOUT);
863}
864
b60503ba
MW		 865static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
866{
867 int status;
868 struct nvme_command c;
869
870 memset(&c, 0, sizeof(c));
871 c.delete_queue.opcode = opcode;
872 c.delete_queue.qid = cpu_to_le16(id);
873
874 status = nvme_submit_admin_cmd(dev, &c, NULL);
875 if (status)
876 return -EIO;
877 return 0;
878}
879
880static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
881 struct nvme_queue *nvmeq)
882{
883 int status;
884 struct nvme_command c;
885 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
886
887 memset(&c, 0, sizeof(c));
888 c.create_cq.opcode = nvme_admin_create_cq;
889 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
890 c.create_cq.cqid = cpu_to_le16(qid);
891 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
892 c.create_cq.cq_flags = cpu_to_le16(flags);
893 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
894
895 status = nvme_submit_admin_cmd(dev, &c, NULL);
896 if (status)
897 return -EIO;
898 return 0;
899}
900
901static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
902 struct nvme_queue *nvmeq)
903{
904 int status;
905 struct nvme_command c;
906 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
907
908 memset(&c, 0, sizeof(c));
909 c.create_sq.opcode = nvme_admin_create_sq;
910 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
911 c.create_sq.sqid = cpu_to_le16(qid);
912 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
913 c.create_sq.sq_flags = cpu_to_le16(flags);
914 c.create_sq.cqid = cpu_to_le16(qid);
915
916 status = nvme_submit_admin_cmd(dev, &c, NULL);
917 if (status)
918 return -EIO;
919 return 0;
920}
921
922static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
923{
924 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
925}
926
927static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
928{
929 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
930}
931
5d0f6131 932int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 933 dma_addr_t dma_addr)
934{
935 struct nvme_command c;
936
937 memset(&c, 0, sizeof(c));
938 c.identify.opcode = nvme_admin_identify;
939 c.identify.nsid = cpu_to_le32(nsid);
940 c.identify.prp1 = cpu_to_le64(dma_addr);
941 c.identify.cns = cpu_to_le32(cns);
942
943 return nvme_submit_admin_cmd(dev, &c, NULL);
944}
945
5d0f6131 946int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 947 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 948{
949 struct nvme_command c;
950
951 memset(&c, 0, sizeof(c));
952 c.features.opcode = nvme_admin_get_features;
a42cecce 953 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 954 c.features.prp1 = cpu_to_le64(dma_addr);
955 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 956
08df1e05 957 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 958}
959
5d0f6131
VV		 960int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
961 dma_addr_t dma_addr, u32 *result)
df348139
MW		 962{
963 struct nvme_command c;
964
965 memset(&c, 0, sizeof(c));
966 c.features.opcode = nvme_admin_set_features;
967 c.features.prp1 = cpu_to_le64(dma_addr);
968 c.features.fid = cpu_to_le32(fid);
969 c.features.dword11 = cpu_to_le32(dword11);
970
bc5fc7e4
MW		 971 return nvme_submit_admin_cmd(dev, &c, result);
972}
973
c30341dc
KB		 974/**
975 * nvme_abort_cmd - Attempt aborting a command
976 * @cmdid: Command id of a timed out IO
977 * @queue: The queue with timed out IO
978 *
979 * Schedule controller reset if the command was already aborted once before and
980 * still hasn't been returned to the driver, or if this is the admin queue.
981 */
982static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
983{
984 int a_cmdid;
985 struct nvme_command cmd;
986 struct nvme_dev *dev = nvmeq->dev;
987 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
988
989 if (!nvmeq->qid || info[cmdid].aborted) {
990 if (work_busy(&dev->reset_work))
991 return;
992 list_del_init(&dev->node);
993 dev_warn(&dev->pci_dev->dev,
994 "I/O %d QID %d timeout, reset controller\n", cmdid,
995 nvmeq->qid);
bdfd70fd 996 PREPARE_WORK(&dev->reset_work, nvme_reset_failed_dev);
c30341dc
KB		 997 queue_work(nvme_workq, &dev->reset_work);
998 return;
999 }
1000
1001 if (!dev->abort_limit)
1002 return;
1003
1004 a_cmdid = alloc_cmdid(dev->queues[0], CMD_CTX_ABORT, special_completion,
1005 ADMIN_TIMEOUT);
1006 if (a_cmdid < 0)
1007 return;
1008
1009 memset(&cmd, 0, sizeof(cmd));
1010 cmd.abort.opcode = nvme_admin_abort_cmd;
1011 cmd.abort.cid = cmdid;
1012 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1013 cmd.abort.command_id = a_cmdid;
1014
1015 --dev->abort_limit;
1016 info[cmdid].aborted = 1;
1017 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1018
1019 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1020 nvmeq->qid);
1021 nvme_submit_cmd(dev->queues[0], &cmd);
1022}
1023
a09115b2
MW		 1024/**
1025 * nvme_cancel_ios - Cancel outstanding I/Os
1026 * @queue: The queue to cancel I/Os on
1027 * @timeout: True to only cancel I/Os which have timed out
1028 */
1029static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1030{
1031 int depth = nvmeq->q_depth - 1;
1032 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1033 unsigned long now = jiffies;
1034 int cmdid;
1035
1036 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1037 void *ctx;
1038 nvme_completion_fn fn;
1039 static struct nvme_completion cqe = {
af2d9ca7 1040 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1041 };
1042
1043 if (timeout && !time_after(now, info[cmdid].timeout))
1044 continue;
053ab702
KB		 1045 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1046 continue;
c30341dc
KB		 1047 if (timeout && nvmeq->dev->initialized) {
1048 nvme_abort_cmd(cmdid, nvmeq);
1049 continue;
1050 }
1051 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1052 nvmeq->qid);
a09115b2
MW		 1053 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1054 fn(nvmeq->dev, ctx, &cqe);
1055 }
1056}
1057
22404274 1058static void nvme_free_queue(struct nvme_queue *nvmeq)
9e866774 1059{
22404274
KB		 1060 spin_lock_irq(&nvmeq->q_lock);
1061 while (bio_list_peek(&nvmeq->sq_cong)) {
1062 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1063 bio_endio(bio, -EIO);
1064 }
1065 spin_unlock_irq(&nvmeq->q_lock);
1066
9e866774
MW		 1067 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1068 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1069 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1070 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1071 kfree(nvmeq);
1072}
1073
a1a5ef99 1074static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1075{
1076 int i;
1077
a1a5ef99 1078 for (i = dev->queue_count - 1; i >= lowest; i--) {
22404274
KB		 1079 nvme_free_queue(dev->queues[i]);
1080 dev->queue_count--;
1081 dev->queues[i] = NULL;
1082 }
1083}
1084
4d115420
KB		 1085/**
1086 * nvme_suspend_queue - put queue into suspended state
1087 * @nvmeq - queue to suspend
1088 *
1089 * Returns 1 if already suspended, 0 otherwise.
1090 */
1091static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1092{
4d115420 1093 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1094
a09115b2 1095 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1096 if (nvmeq->q_suspended) {
1097 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1098 return 1;
3295874b 1099 }
22404274 1100 nvmeq->q_suspended = 1;
a09115b2
MW		 1101 spin_unlock_irq(&nvmeq->q_lock);
1102
aba2080f
MW		 1103 irq_set_affinity_hint(vector, NULL);
1104 free_irq(vector, nvmeq);
b60503ba 1105
4d115420
KB		 1106 return 0;
1107}
b60503ba 1108
4d115420
KB		 1109static void nvme_clear_queue(struct nvme_queue *nvmeq)
1110{
22404274
KB		 1111 spin_lock_irq(&nvmeq->q_lock);
1112 nvme_process_cq(nvmeq);
1113 nvme_cancel_ios(nvmeq, false);
1114 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1115}
1116
4d115420
KB		 1117static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1118{
1119 struct nvme_queue *nvmeq = dev->queues[qid];
1120
1121 if (!nvmeq)
1122 return;
1123 if (nvme_suspend_queue(nvmeq))
1124 return;
1125
0e53d180
KB		 1126 /* Don't tell the adapter to delete the admin queue.
1127 * Don't tell a removed adapter to delete IO queues. */
1128 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1129 adapter_delete_sq(dev, qid);
1130 adapter_delete_cq(dev, qid);
1131 }
4d115420 1132 nvme_clear_queue(nvmeq);
b60503ba
MW		 1133}
1134
1135static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1136 int depth, int vector)
1137{
1138 struct device *dmadev = &dev->pci_dev->dev;
22404274 1139 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1140 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1141 if (!nvmeq)
1142 return NULL;
1143
1144 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1145 &nvmeq->cq_dma_addr, GFP_KERNEL);
1146 if (!nvmeq->cqes)
1147 goto free_nvmeq;
1148 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1149
1150 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1151 &nvmeq->sq_dma_addr, GFP_KERNEL);
1152 if (!nvmeq->sq_cmds)
1153 goto free_cqdma;
1154
1155 nvmeq->q_dmadev = dmadev;
091b6092 1156 nvmeq->dev = dev;
3193f07b
MW		 1157 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1158 dev->instance, qid);
b60503ba
MW		 1159 spin_lock_init(&nvmeq->q_lock);
1160 nvmeq->cq_head = 0;
82123460 1161 nvmeq->cq_phase = 1;
b60503ba 1162 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1163 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1164 bio_list_init(&nvmeq->sq_cong);
b80d5ccc 1165 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1166 nvmeq->q_depth = depth;
1167 nvmeq->cq_vector = vector;
c30341dc 1168 nvmeq->qid = qid;
22404274
KB		 1169 nvmeq->q_suspended = 1;
1170 dev->queue_count++;
b60503ba
MW		 1171
1172 return nvmeq;
1173
1174 free_cqdma:
68b8eca5 1175 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1176 nvmeq->cq_dma_addr);
1177 free_nvmeq:
1178 kfree(nvmeq);
1179 return NULL;
1180}
1181
3001082c
MW		 1182static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1183 const char *name)
1184{
58ffacb5
MW		 1185 if (use_threaded_interrupts)
1186 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1187 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1188 name, nvmeq);
3001082c 1189 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1190 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1191}
1192
22404274 1193static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1194{
22404274
KB		 1195 struct nvme_dev *dev = nvmeq->dev;
1196 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1197
22404274
KB		 1198 nvmeq->sq_tail = 0;
1199 nvmeq->cq_head = 0;
1200 nvmeq->cq_phase = 1;
b80d5ccc 1201 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1202 memset(nvmeq->cmdid_data, 0, extra);
1203 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1204 nvme_cancel_ios(nvmeq, false);
1205 nvmeq->q_suspended = 0;
1206}
1207
1208static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1209{
1210 struct nvme_dev *dev = nvmeq->dev;
1211 int result;
3f85d50b 1212
b60503ba
MW		 1213 result = adapter_alloc_cq(dev, qid, nvmeq);
1214 if (result < 0)
22404274 1215 return result;
b60503ba
MW		 1216
1217 result = adapter_alloc_sq(dev, qid, nvmeq);
1218 if (result < 0)
1219 goto release_cq;
1220
3193f07b 1221 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1222 if (result < 0)
1223 goto release_sq;
1224
0a8d44cb 1225 spin_lock_irq(&nvmeq->q_lock);
22404274 1226 nvme_init_queue(nvmeq, qid);
0a8d44cb 1227 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1228
1229 return result;
b60503ba
MW		 1230
1231 release_sq:
1232 adapter_delete_sq(dev, qid);
1233 release_cq:
1234 adapter_delete_cq(dev, qid);
22404274 1235 return result;
b60503ba
MW		 1236}
1237
ba47e386
MW		 1238static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1239{
1240 unsigned long timeout;
1241 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1242
1243 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1244
1245 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1246 msleep(100);
1247 if (fatal_signal_pending(current))
1248 return -EINTR;
1249 if (time_after(jiffies, timeout)) {
1250 dev_err(&dev->pci_dev->dev,
1251 "Device not ready; aborting initialisation\n");
1252 return -ENODEV;
1253 }
1254 }
1255
1256 return 0;
1257}
1258
1259/*
1260 * If the device has been passed off to us in an enabled state, just clear
1261 * the enabled bit. The spec says we should set the 'shutdown notification
1262 * bits', but doing so may cause the device to complete commands to the
1263 * admin queue ... and we don't know what memory that might be pointing at!
1264 */
1265static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1266{
44af146a
MW		 1267 u32 cc = readl(&dev->bar->cc);
1268
1269 if (cc & NVME_CC_ENABLE)
1270 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1271 return nvme_wait_ready(dev, cap, false);
1272}
1273
1274static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1275{
1276 return nvme_wait_ready(dev, cap, true);
1277}
1278
1894d8f1
KB		 1279static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1280{
1281 unsigned long timeout;
1282 u32 cc;
1283
1284 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1285 writel(cc, &dev->bar->cc);
1286
1287 timeout = 2 * HZ + jiffies;
1288 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1289 NVME_CSTS_SHST_CMPLT) {
1290 msleep(100);
1291 if (fatal_signal_pending(current))
1292 return -EINTR;
1293 if (time_after(jiffies, timeout)) {
1294 dev_err(&dev->pci_dev->dev,
1295 "Device shutdown incomplete; abort shutdown\n");
1296 return -ENODEV;
1297 }
1298 }
1299
1300 return 0;
1301}
1302
8d85fce7 1303static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1304{
ba47e386 1305 int result;
b60503ba 1306 u32 aqa;
ba47e386 1307 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1308 struct nvme_queue *nvmeq;
1309
ba47e386
MW		 1310 result = nvme_disable_ctrl(dev, cap);
1311 if (result < 0)
1312 return result;
b60503ba 1313
cd638946
KB		 1314 nvmeq = dev->queues[0];
1315 if (!nvmeq) {
1316 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1317 if (!nvmeq)
1318 return -ENOMEM;
1319 dev->queues[0] = nvmeq;
1320 }
b60503ba
MW		 1321
1322 aqa = nvmeq->q_depth - 1;
1323 aqa |= aqa << 16;
1324
1325 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1326 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1327 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1328 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1329
1330 writel(aqa, &dev->bar->aqa);
1331 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1332 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1333 writel(dev->ctrl_config, &dev->bar->cc);
1334
ba47e386 1335 result = nvme_enable_ctrl(dev, cap);
025c557a 1336 if (result)
cd638946 1337 return result;
9e866774 1338
3193f07b 1339 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1340 if (result)
cd638946 1341 return result;
025c557a 1342
0a8d44cb 1343 spin_lock_irq(&nvmeq->q_lock);
22404274 1344 nvme_init_queue(nvmeq, 0);
0a8d44cb 1345 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1346 return result;
1347}
1348
5d0f6131 1349struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1350 unsigned long addr, unsigned length)
b60503ba 1351{
36c14ed9 1352 int i, err, count, nents, offset;
7fc3cdab
MW		 1353 struct scatterlist *sg;
1354 struct page **pages;
eca18b23 1355 struct nvme_iod *iod;
36c14ed9
MW		 1356
1357 if (addr & 3)
eca18b23 1358 return ERR_PTR(-EINVAL);
5460fc03 1359 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1360 return ERR_PTR(-EINVAL);
7fc3cdab 1361
36c14ed9 1362 offset = offset_in_page(addr);
7fc3cdab
MW		 1363 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1364 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1365 if (!pages)
1366 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1367
1368 err = get_user_pages_fast(addr, count, 1, pages);
1369 if (err < count) {
1370 count = err;
1371 err = -EFAULT;
1372 goto put_pages;
1373 }
7fc3cdab 1374
eca18b23
MW		 1375 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1376 sg = iod->sg;
36c14ed9 1377 sg_init_table(sg, count);
d0ba1e49
MW		 1378 for (i = 0; i < count; i++) {
1379 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1380 min_t(unsigned, length, PAGE_SIZE - offset),
1381 offset);
d0ba1e49
MW		 1382 length -= (PAGE_SIZE - offset);
1383 offset = 0;
7fc3cdab 1384 }
fe304c43 1385 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1386 iod->nents = count;
7fc3cdab
MW		 1387
1388 err = -ENOMEM;
1389 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1390 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1391 if (!nents)
eca18b23 1392 goto free_iod;
b60503ba 1393
7fc3cdab 1394 kfree(pages);
eca18b23 1395 return iod;
b60503ba 1396
eca18b23
MW		 1397 free_iod:
1398 kfree(iod);
7fc3cdab
MW		 1399 put_pages:
1400 for (i = 0; i < count; i++)
1401 put_page(pages[i]);
1402 kfree(pages);
eca18b23 1403 return ERR_PTR(err);
7fc3cdab 1404}
b60503ba 1405
5d0f6131 1406void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1407 struct nvme_iod *iod)
7fc3cdab 1408{
1c2ad9fa 1409 int i;
b60503ba 1410
1c2ad9fa
MW		 1411 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1412 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1413
1c2ad9fa
MW		 1414 for (i = 0; i < iod->nents; i++)
1415 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1416}
b60503ba 1417
a53295b6
MW		 1418static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1419{
1420 struct nvme_dev *dev = ns->dev;
1421 struct nvme_queue *nvmeq;
1422 struct nvme_user_io io;
1423 struct nvme_command c;
f410c680
KB		 1424 unsigned length, meta_len;
1425 int status, i;
1426 struct nvme_iod *iod, *meta_iod = NULL;
1427 dma_addr_t meta_dma_addr;
1428 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1429
1430 if (copy_from_user(&io, uio, sizeof(io)))
1431 return -EFAULT;
6c7d4945 1432 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1433 meta_len = (io.nblocks + 1) * ns->ms;
1434
1435 if (meta_len && ((io.metadata & 3) || !io.metadata))
1436 return -EINVAL;
6c7d4945
MW		 1437
1438 switch (io.opcode) {
1439 case nvme_cmd_write:
1440 case nvme_cmd_read:
6bbf1acd 1441 case nvme_cmd_compare:
eca18b23 1442 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1443 break;
6c7d4945 1444 default:
6bbf1acd 1445 return -EINVAL;
6c7d4945
MW		 1446 }
1447
eca18b23
MW		 1448 if (IS_ERR(iod))
1449 return PTR_ERR(iod);
a53295b6
MW		 1450
1451 memset(&c, 0, sizeof(c));
1452 c.rw.opcode = io.opcode;
1453 c.rw.flags = io.flags;
6c7d4945 1454 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1455 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1456 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1457 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1458 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1459 c.rw.reftag = cpu_to_le32(io.reftag);
1460 c.rw.apptag = cpu_to_le16(io.apptag);
1461 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1462
1463 if (meta_len) {
1b56749e
KB		 1464 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1465 meta_len);
f410c680
KB		 1466 if (IS_ERR(meta_iod)) {
1467 status = PTR_ERR(meta_iod);
1468 meta_iod = NULL;
1469 goto unmap;
1470 }
1471
1472 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1473 &meta_dma_addr, GFP_KERNEL);
1474 if (!meta_mem) {
1475 status = -ENOMEM;
1476 goto unmap;
1477 }
1478
1479 if (io.opcode & 1) {
1480 int meta_offset = 0;
1481
1482 for (i = 0; i < meta_iod->nents; i++) {
1483 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1484 meta_iod->sg[i].offset;
1485 memcpy(meta_mem + meta_offset, meta,
1486 meta_iod->sg[i].length);
1487 kunmap_atomic(meta);
1488 meta_offset += meta_iod->sg[i].length;
1489 }
1490 }
1491
1492 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1493 }
1494
eca18b23 1495 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1496
040a93b5 1497 nvmeq = get_nvmeq(dev);
fa922821
MW		 1498 /*
1499 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW		 1500 * disabled. We may be preempted at any point, and be rescheduled
1501 * to a different CPU. That will cause cacheline bouncing, but no
1502 * additional races since q_lock already protects against other CPUs.
1503 */
a53295b6 1504 put_nvmeq(nvmeq);
b77954cb
MW		 1505 if (length != (io.nblocks + 1) << ns->lba_shift)
1506 status = -ENOMEM;
22404274
KB		 1507 else if (!nvmeq || nvmeq->q_suspended)
1508 status = -EBUSY;
b77954cb 1509 else
ff976d72 1510 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
a53295b6 1511
f410c680
KB		 1512 if (meta_len) {
1513 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1514 int meta_offset = 0;
1515
1516 for (i = 0; i < meta_iod->nents; i++) {
1517 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1518 meta_iod->sg[i].offset;
1519 memcpy(meta, meta_mem + meta_offset,
1520 meta_iod->sg[i].length);
1521 kunmap_atomic(meta);
1522 meta_offset += meta_iod->sg[i].length;
1523 }
1524 }
1525
1526 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1527 meta_dma_addr);
1528 }
1529
1530 unmap:
1c2ad9fa 1531 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1532 nvme_free_iod(dev, iod);
f410c680
KB		 1533
1534 if (meta_iod) {
1535 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1536 nvme_free_iod(dev, meta_iod);
1537 }
1538
a53295b6
MW		 1539 return status;
1540}
1541
50af8bae 1542static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1543 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1544{
6bbf1acd 1545 struct nvme_admin_cmd cmd;
6ee44cdc 1546 struct nvme_command c;
eca18b23 1547 int status, length;
c7d36ab8 1548 struct nvme_iod *uninitialized_var(iod);
94f370ca 1549 unsigned timeout;
6ee44cdc 1550
6bbf1acd
MW		 1551 if (!capable(CAP_SYS_ADMIN))
1552 return -EACCES;
1553 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1554 return -EFAULT;
6ee44cdc
MW		 1555
1556 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1557 c.common.opcode = cmd.opcode;
1558 c.common.flags = cmd.flags;
1559 c.common.nsid = cpu_to_le32(cmd.nsid);
1560 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1561 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1562 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1563 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1564 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1565 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1566 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1567 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1568
1569 length = cmd.data_len;
1570 if (cmd.data_len) {
49742188
MW		 1571 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1572 length);
eca18b23
MW		 1573 if (IS_ERR(iod))
1574 return PTR_ERR(iod);
1575 length = nvme_setup_prps(dev, &c.common, iod, length,
1576 GFP_KERNEL);
6bbf1acd
MW		 1577 }
1578
94f370ca
KB		 1579 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1580 ADMIN_TIMEOUT;
6bbf1acd 1581 if (length != cmd.data_len)
b77954cb
MW		 1582 status = -ENOMEM;
1583 else
94f370ca
KB		 1584 status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result,
1585 timeout);
eca18b23 1586
6bbf1acd 1587 if (cmd.data_len) {
1c2ad9fa 1588 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1589 nvme_free_iod(dev, iod);
6bbf1acd 1590 }
f4f117f6 1591
cf90bc48 1592 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1593 sizeof(cmd.result)))
1594 status = -EFAULT;
1595
6ee44cdc
MW		 1596 return status;
1597}
1598
b60503ba
MW		 1599static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1600 unsigned long arg)
1601{
1602 struct nvme_ns *ns = bdev->bd_disk->private_data;
1603
1604 switch (cmd) {
6bbf1acd 1605 case NVME_IOCTL_ID:
c3bfe717 1606 force_successful_syscall_return();
6bbf1acd
MW		 1607 return ns->ns_id;
1608 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1609 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1610 case NVME_IOCTL_SUBMIT_IO:
1611 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1612 case SG_GET_VERSION_NUM:
1613 return nvme_sg_get_version_num((void __user *)arg);
1614 case SG_IO:
1615 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1616 default:
1617 return -ENOTTY;
1618 }
1619}
1620
320a3827
KB		 1621#ifdef CONFIG_COMPAT
1622static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1623 unsigned int cmd, unsigned long arg)
1624{
1625 struct nvme_ns *ns = bdev->bd_disk->private_data;
1626
1627 switch (cmd) {
1628 case SG_IO:
1629 return nvme_sg_io32(ns, arg);
1630 }
1631 return nvme_ioctl(bdev, mode, cmd, arg);
1632}
1633#else
1634#define nvme_compat_ioctl NULL
1635#endif
1636
9ac27090
KB		 1637static int nvme_open(struct block_device *bdev, fmode_t mode)
1638{
1639 struct nvme_ns *ns = bdev->bd_disk->private_data;
1640 struct nvme_dev *dev = ns->dev;
1641
1642 kref_get(&dev->kref);
1643 return 0;
1644}
1645
1646static void nvme_free_dev(struct kref *kref);
1647
1648static void nvme_release(struct gendisk *disk, fmode_t mode)
1649{
1650 struct nvme_ns *ns = disk->private_data;
1651 struct nvme_dev *dev = ns->dev;
1652
1653 kref_put(&dev->kref, nvme_free_dev);
1654}
1655
b60503ba
MW		 1656static const struct block_device_operations nvme_fops = {
1657 .owner = THIS_MODULE,
1658 .ioctl = nvme_ioctl,
320a3827 1659 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1660 .open = nvme_open,
1661 .release = nvme_release,
b60503ba
MW		 1662};
1663
1fa6aead
MW		 1664static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1665{
1666 while (bio_list_peek(&nvmeq->sq_cong)) {
1667 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1668 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB		 1669
1670 if (bio_list_empty(&nvmeq->sq_cong))
1671 remove_wait_queue(&nvmeq->sq_full,
1672 &nvmeq->sq_cong_wait);
1fa6aead 1673 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB		 1674 if (bio_list_empty(&nvmeq->sq_cong))
1675 add_wait_queue(&nvmeq->sq_full,
1676 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1677 bio_list_add_head(&nvmeq->sq_cong, bio);
1678 break;
1679 }
1680 }
1681}
1682
1683static int nvme_kthread(void *data)
1684{
d4b4ff8e 1685 struct nvme_dev *dev, *next;
1fa6aead
MW		 1686
1687 while (!kthread_should_stop()) {
564a232c 1688 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1689 spin_lock(&dev_list_lock);
d4b4ff8e 1690 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1691 int i;
d4b4ff8e
KB		 1692 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1693 dev->initialized) {
1694 if (work_busy(&dev->reset_work))
1695 continue;
1696 list_del_init(&dev->node);
1697 dev_warn(&dev->pci_dev->dev,
1698 "Failed status, reset controller\n");
bdfd70fd 1699 PREPARE_WORK(&dev->reset_work,
d4b4ff8e
KB		 1700 nvme_reset_failed_dev);
1701 queue_work(nvme_workq, &dev->reset_work);
1702 continue;
1703 }
1fa6aead
MW		 1704 for (i = 0; i < dev->queue_count; i++) {
1705 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1706 if (!nvmeq)
1707 continue;
1fa6aead 1708 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1709 if (nvmeq->q_suspended)
1710 goto unlock;
bc57a0f7 1711 nvme_process_cq(nvmeq);
a09115b2 1712 nvme_cancel_ios(nvmeq, true);
1fa6aead 1713 nvme_resubmit_bios(nvmeq);
22404274 1714 unlock:
1fa6aead
MW		 1715 spin_unlock_irq(&nvmeq->q_lock);
1716 }
1717 }
1718 spin_unlock(&dev_list_lock);
acb7aa0d 1719 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1720 }
1721 return 0;
1722}
1723
0e5e4f0e
KB		 1724static void nvme_config_discard(struct nvme_ns *ns)
1725{
1726 u32 logical_block_size = queue_logical_block_size(ns->queue);
1727 ns->queue->limits.discard_zeroes_data = 0;
1728 ns->queue->limits.discard_alignment = logical_block_size;
1729 ns->queue->limits.discard_granularity = logical_block_size;
1730 ns->queue->limits.max_discard_sectors = 0xffffffff;
1731 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1732}
1733
c3bfe717 1734static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1735 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1736{
1737 struct nvme_ns *ns;
1738 struct gendisk *disk;
1739 int lbaf;
1740
1741 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1742 return NULL;
1743
1744 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1745 if (!ns)
1746 return NULL;
1747 ns->queue = blk_alloc_queue(GFP_KERNEL);
1748 if (!ns->queue)
1749 goto out_free_ns;
4eeb9215
MW		 1750 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1751 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1752 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1753 blk_queue_make_request(ns->queue, nvme_make_request);
1754 ns->dev = dev;
1755 ns->queue->queuedata = ns;
1756
469071a3 1757 disk = alloc_disk(0);
b60503ba
MW		 1758 if (!disk)
1759 goto out_free_queue;
5aff9382 1760 ns->ns_id = nsid;
b60503ba
MW		 1761 ns->disk = disk;
1762 lbaf = id->flbas & 0xf;
1763 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1764 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1765 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1766 if (dev->max_hw_sectors)
1767 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1768
1769 disk->major = nvme_major;
469071a3 1770 disk->first_minor = 0;
b60503ba
MW		 1771 disk->fops = &nvme_fops;
1772 disk->private_data = ns;
1773 disk->queue = ns->queue;
388f037f 1774 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1775 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1776 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1777 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1778
0e5e4f0e
KB		 1779 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1780 nvme_config_discard(ns);
1781
b60503ba
MW		 1782 return ns;
1783
1784 out_free_queue:
1785 blk_cleanup_queue(ns->queue);
1786 out_free_ns:
1787 kfree(ns);
1788 return NULL;
1789}
1790
b3b06812 1791static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1792{
1793 int status;
1794 u32 result;
b3b06812 1795 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1796
df348139 1797 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1798 &result);
b60503ba 1799 if (status)
7e03b124 1800 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 1801 return min(result & 0xffff, result >> 16) + 1;
1802}
1803
9d713c2b
KB		 1804static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1805{
b80d5ccc 1806 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1807}
1808
8d85fce7 1809static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1810{
3193f07b 1811 struct nvme_queue *adminq = dev->queues[0];
fa08a396 1812 struct pci_dev *pdev = dev->pci_dev;
9d713c2b 1813 int result, cpu, i, vecs, nr_io_queues, size, q_depth;
b60503ba 1814
b348b7d5
MW		 1815 nr_io_queues = num_online_cpus();
1816 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 1817 if (result < 0)
1818 return result;
b348b7d5
MW		 1819 if (result < nr_io_queues)
1820 nr_io_queues = result;
b60503ba 1821
9d713c2b
KB		 1822 size = db_bar_size(dev, nr_io_queues);
1823 if (size > 8192) {
f1938f6e 1824 iounmap(dev->bar);
9d713c2b
KB		 1825 do {
1826 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1827 if (dev->bar)
1828 break;
1829 if (!--nr_io_queues)
1830 return -ENOMEM;
1831 size = db_bar_size(dev, nr_io_queues);
1832 } while (1);
f1938f6e
MW		 1833 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1834 dev->queues[0]->q_db = dev->dbs;
1835 }
1836
9d713c2b 1837 /* Deregister the admin queue's interrupt */
3193f07b 1838 free_irq(dev->entry[0].vector, adminq);
9d713c2b 1839
063a8096
MW		 1840 vecs = nr_io_queues;
1841 for (i = 0; i < vecs; i++)
1b23484b
MW		 1842 dev->entry[i].entry = i;
1843 for (;;) {
063a8096
MW		 1844 result = pci_enable_msix(pdev, dev->entry, vecs);
1845 if (result <= 0)
1b23484b 1846 break;
063a8096 1847 vecs = result;
1b23484b
MW		 1848 }
1849
063a8096
MW		 1850 if (result < 0) {
1851 vecs = nr_io_queues;
1852 if (vecs > 32)
1853 vecs = 32;
fa08a396 1854 for (;;) {
063a8096 1855 result = pci_enable_msi_block(pdev, vecs);
fa08a396 1856 if (result == 0) {
063a8096 1857 for (i = 0; i < vecs; i++)
fa08a396
RRG		 1858 dev->entry[i].vector = i + pdev->irq;
1859 break;
063a8096
MW		 1860 } else if (result < 0) {
1861 vecs = 1;
fa08a396
RRG		 1862 break;
1863 }
063a8096 1864 vecs = result;
fa08a396
RRG		 1865 }
1866 }
1867
063a8096
MW		 1868 /*
1869 * Should investigate if there's a performance win from allocating
1870 * more queues than interrupt vectors; it might allow the submission
1871 * path to scale better, even if the receive path is limited by the
1872 * number of interrupts.
1873 */
1874 nr_io_queues = vecs;
1875
3193f07b 1876 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 1877 if (result) {
3193f07b 1878 adminq->q_suspended = 1;
22404274 1879 goto free_queues;
9d713c2b 1880 }
1b23484b 1881
cd638946
KB		 1882 /* Free previously allocated queues that are no longer usable */
1883 spin_lock(&dev_list_lock);
1884 for (i = dev->queue_count - 1; i > nr_io_queues; i--) {
1885 struct nvme_queue *nvmeq = dev->queues[i];
1886
0a8d44cb 1887 spin_lock_irq(&nvmeq->q_lock);
cd638946 1888 nvme_cancel_ios(nvmeq, false);
0a8d44cb 1889 spin_unlock_irq(&nvmeq->q_lock);
cd638946
KB		 1890
1891 nvme_free_queue(nvmeq);
1892 dev->queue_count--;
1893 dev->queues[i] = NULL;
1894 }
1895 spin_unlock(&dev_list_lock);
1896
1b23484b 1897 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1898 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1899 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1900 cpu = cpumask_next(cpu, cpu_online_mask);
1901 }
1902
a0cadb85
KB		 1903 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1904 NVME_Q_DEPTH);
cd638946 1905 for (i = dev->queue_count - 1; i < nr_io_queues; i++) {
22404274
KB		 1906 dev->queues[i + 1] = nvme_alloc_queue(dev, i + 1, q_depth, i);
1907 if (!dev->queues[i + 1]) {
1908 result = -ENOMEM;
1909 goto free_queues;
1910 }
1b23484b 1911 }
b60503ba 1912
9ecdc946
MW		 1913 for (; i < num_possible_cpus(); i++) {
1914 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1915 dev->queues[i + 1] = dev->queues[target + 1];
1916 }
1917
22404274
KB		 1918 for (i = 1; i < dev->queue_count; i++) {
1919 result = nvme_create_queue(dev->queues[i], i);
1920 if (result) {
1921 for (--i; i > 0; i--)
1922 nvme_disable_queue(dev, i);
1923 goto free_queues;
1924 }
1925 }
b60503ba 1926
22404274 1927 return 0;
b60503ba 1928
22404274 1929 free_queues:
a1a5ef99 1930 nvme_free_queues(dev, 1);
22404274 1931 return result;
b60503ba
MW		 1932}
1933
422ef0c7
MW		 1934/*
1935 * Return: error value if an error occurred setting up the queues or calling
1936 * Identify Device. 0 if these succeeded, even if adding some of the
1937 * namespaces failed. At the moment, these failures are silent. TBD which
1938 * failures should be reported.
1939 */
8d85fce7 1940static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 1941{
68608c26 1942 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 1943 int res;
1944 unsigned nn, i;
cbb6218f 1945 struct nvme_ns *ns;
51814232 1946 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 1947 struct nvme_id_ns *id_ns;
1948 void *mem;
b60503ba 1949 dma_addr_t dma_addr;
159b67d7 1950 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 1951
68608c26 1952 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 1953 if (!mem)
1954 return -ENOMEM;
b60503ba 1955
bc5fc7e4 1956 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 1957 if (res) {
1958 res = -EIO;
cbb6218f 1959 goto out;
b60503ba
MW		 1960 }
1961
bc5fc7e4 1962 ctrl = mem;
51814232 1963 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 1964 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 1965 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 1966 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1967 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1968 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 1969 if (ctrl->mdts)
8fc23e03 1970 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 1971 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
1972 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 1973 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 1974
bc5fc7e4 1975 id_ns = mem;
2b2c1896 1976 for (i = 1; i <= nn; i++) {
bc5fc7e4 1977 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 1978 if (res)
1979 continue;
1980
bc5fc7e4 1981 if (id_ns->ncap == 0)
b60503ba
MW		 1982 continue;
1983
bc5fc7e4 1984 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 1985 dma_addr + 4096, NULL);
b60503ba 1986 if (res)
12209036 1987 memset(mem + 4096, 0, 4096);
b60503ba 1988
bc5fc7e4 1989 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 1990 if (ns)
1991 list_add_tail(&ns->list, &dev->namespaces);
1992 }
1993 list_for_each_entry(ns, &dev->namespaces, list)
1994 add_disk(ns->disk);
422ef0c7 1995 res = 0;
b60503ba 1996
bc5fc7e4 1997 out:
684f5c20 1998 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 1999 return res;
2000}
2001
0877cb0d
KB		 2002static int nvme_dev_map(struct nvme_dev *dev)
2003{
2004 int bars, result = -ENOMEM;
2005 struct pci_dev *pdev = dev->pci_dev;
2006
2007 if (pci_enable_device_mem(pdev))
2008 return result;
2009
2010 dev->entry[0].vector = pdev->irq;
2011 pci_set_master(pdev);
2012 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2013 if (pci_request_selected_regions(pdev, bars, "nvme"))
2014 goto disable_pci;
2015
052d0efa
RK		 2016 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2017 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2018 goto disable;
0877cb0d 2019
0877cb0d
KB		 2020 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2021 if (!dev->bar)
2022 goto disable;
0e53d180
KB		 2023 if (readl(&dev->bar->csts) == -1) {
2024 result = -ENODEV;
2025 goto unmap;
2026 }
b80d5ccc 2027 dev->db_stride = 1 << NVME_CAP_STRIDE(readq(&dev->bar->cap));
0877cb0d
KB		 2028 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2029
2030 return 0;
2031
0e53d180
KB		 2032 unmap:
2033 iounmap(dev->bar);
2034 dev->bar = NULL;
0877cb0d
KB		 2035 disable:
2036 pci_release_regions(pdev);
2037 disable_pci:
2038 pci_disable_device(pdev);
2039 return result;
2040}
2041
2042static void nvme_dev_unmap(struct nvme_dev *dev)
2043{
2044 if (dev->pci_dev->msi_enabled)
2045 pci_disable_msi(dev->pci_dev);
2046 else if (dev->pci_dev->msix_enabled)
2047 pci_disable_msix(dev->pci_dev);
2048
2049 if (dev->bar) {
2050 iounmap(dev->bar);
2051 dev->bar = NULL;
9a6b9458 2052 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2053 }
2054
0877cb0d
KB		 2055 if (pci_is_enabled(dev->pci_dev))
2056 pci_disable_device(dev->pci_dev);
2057}
2058
4d115420
KB		 2059struct nvme_delq_ctx {
2060 struct task_struct *waiter;
2061 struct kthread_worker *worker;
2062 atomic_t refcount;
2063};
2064
2065static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2066{
2067 dq->waiter = current;
2068 mb();
2069
2070 for (;;) {
2071 set_current_state(TASK_KILLABLE);
2072 if (!atomic_read(&dq->refcount))
2073 break;
2074 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2075 fatal_signal_pending(current)) {
2076 set_current_state(TASK_RUNNING);
2077
2078 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2079 nvme_disable_queue(dev, 0);
2080
2081 send_sig(SIGKILL, dq->worker->task, 1);
2082 flush_kthread_worker(dq->worker);
2083 return;
2084 }
2085 }
2086 set_current_state(TASK_RUNNING);
2087}
2088
2089static void nvme_put_dq(struct nvme_delq_ctx *dq)
2090{
2091 atomic_dec(&dq->refcount);
2092 if (dq->waiter)
2093 wake_up_process(dq->waiter);
2094}
2095
2096static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2097{
2098 atomic_inc(&dq->refcount);
2099 return dq;
2100}
2101
2102static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2103{
2104 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2105
2106 nvme_clear_queue(nvmeq);
2107 nvme_put_dq(dq);
2108}
2109
2110static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2111 kthread_work_func_t fn)
2112{
2113 struct nvme_command c;
2114
2115 memset(&c, 0, sizeof(c));
2116 c.delete_queue.opcode = opcode;
2117 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2118
2119 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2120 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2121}
2122
2123static void nvme_del_cq_work_handler(struct kthread_work *work)
2124{
2125 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2126 cmdinfo.work);
2127 nvme_del_queue_end(nvmeq);
2128}
2129
2130static int nvme_delete_cq(struct nvme_queue *nvmeq)
2131{
2132 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2133 nvme_del_cq_work_handler);
2134}
2135
2136static void nvme_del_sq_work_handler(struct kthread_work *work)
2137{
2138 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2139 cmdinfo.work);
2140 int status = nvmeq->cmdinfo.status;
2141
2142 if (!status)
2143 status = nvme_delete_cq(nvmeq);
2144 if (status)
2145 nvme_del_queue_end(nvmeq);
2146}
2147
2148static int nvme_delete_sq(struct nvme_queue *nvmeq)
2149{
2150 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2151 nvme_del_sq_work_handler);
2152}
2153
2154static void nvme_del_queue_start(struct kthread_work *work)
2155{
2156 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2157 cmdinfo.work);
2158 allow_signal(SIGKILL);
2159 if (nvme_delete_sq(nvmeq))
2160 nvme_del_queue_end(nvmeq);
2161}
2162
2163static void nvme_disable_io_queues(struct nvme_dev *dev)
2164{
2165 int i;
2166 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2167 struct nvme_delq_ctx dq;
2168 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2169 &worker, "nvme%d", dev->instance);
2170
2171 if (IS_ERR(kworker_task)) {
2172 dev_err(&dev->pci_dev->dev,
2173 "Failed to create queue del task\n");
2174 for (i = dev->queue_count - 1; i > 0; i--)
2175 nvme_disable_queue(dev, i);
2176 return;
2177 }
2178
2179 dq.waiter = NULL;
2180 atomic_set(&dq.refcount, 0);
2181 dq.worker = &worker;
2182 for (i = dev->queue_count - 1; i > 0; i--) {
2183 struct nvme_queue *nvmeq = dev->queues[i];
2184
2185 if (nvme_suspend_queue(nvmeq))
2186 continue;
2187 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2188 nvmeq->cmdinfo.worker = dq.worker;
2189 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2190 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2191 }
2192 nvme_wait_dq(&dq, dev);
2193 kthread_stop(kworker_task);
2194}
2195
f0b50732 2196static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2197{
22404274
KB		 2198 int i;
2199
d4b4ff8e 2200 dev->initialized = 0;
b60503ba 2201
1fa6aead 2202 spin_lock(&dev_list_lock);
f0b50732 2203 list_del_init(&dev->node);
1fa6aead
MW		 2204 spin_unlock(&dev_list_lock);
2205
4d115420
KB		 2206 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2207 for (i = dev->queue_count - 1; i >= 0; i--) {
2208 struct nvme_queue *nvmeq = dev->queues[i];
2209 nvme_suspend_queue(nvmeq);
2210 nvme_clear_queue(nvmeq);
2211 }
2212 } else {
2213 nvme_disable_io_queues(dev);
1894d8f1 2214 nvme_shutdown_ctrl(dev);
4d115420
KB		 2215 nvme_disable_queue(dev, 0);
2216 }
f0b50732
KB		 2217 nvme_dev_unmap(dev);
2218}
2219
2220static void nvme_dev_remove(struct nvme_dev *dev)
2221{
9ac27090 2222 struct nvme_ns *ns;
f0b50732 2223
9ac27090
KB		 2224 list_for_each_entry(ns, &dev->namespaces, list) {
2225 if (ns->disk->flags & GENHD_FL_UP)
2226 del_gendisk(ns->disk);
2227 if (!blk_queue_dying(ns->queue))
2228 blk_cleanup_queue(ns->queue);
b60503ba 2229 }
b60503ba
MW		 2230}
2231
091b6092
MW		 2232static int nvme_setup_prp_pools(struct nvme_dev *dev)
2233{
2234 struct device *dmadev = &dev->pci_dev->dev;
2235 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2236 PAGE_SIZE, PAGE_SIZE, 0);
2237 if (!dev->prp_page_pool)
2238 return -ENOMEM;
2239
99802a7a
MW		 2240 /* Optimisation for I/Os between 4k and 128k */
2241 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2242 256, 256, 0);
2243 if (!dev->prp_small_pool) {
2244 dma_pool_destroy(dev->prp_page_pool);
2245 return -ENOMEM;
2246 }
091b6092
MW		 2247 return 0;
2248}
2249
2250static void nvme_release_prp_pools(struct nvme_dev *dev)
2251{
2252 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2253 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2254}
2255
cd58ad7d
QSA		 2256static DEFINE_IDA(nvme_instance_ida);
2257
2258static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2259{
cd58ad7d
QSA		 2260 int instance, error;
2261
2262 do {
2263 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2264 return -ENODEV;
2265
2266 spin_lock(&dev_list_lock);
2267 error = ida_get_new(&nvme_instance_ida, &instance);
2268 spin_unlock(&dev_list_lock);
2269 } while (error == -EAGAIN);
2270
2271 if (error)
2272 return -ENODEV;
2273
2274 dev->instance = instance;
2275 return 0;
b60503ba
MW		 2276}
2277
2278static void nvme_release_instance(struct nvme_dev *dev)
2279{
cd58ad7d
QSA		 2280 spin_lock(&dev_list_lock);
2281 ida_remove(&nvme_instance_ida, dev->instance);
2282 spin_unlock(&dev_list_lock);
b60503ba
MW		 2283}
2284
9ac27090
KB		 2285static void nvme_free_namespaces(struct nvme_dev *dev)
2286{
2287 struct nvme_ns *ns, *next;
2288
2289 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2290 list_del(&ns->list);
2291 put_disk(ns->disk);
2292 kfree(ns);
2293 }
2294}
2295
5e82e952
KB		 2296static void nvme_free_dev(struct kref *kref)
2297{
2298 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2299
2300 nvme_free_namespaces(dev);
5e82e952
KB		 2301 kfree(dev->queues);
2302 kfree(dev->entry);
2303 kfree(dev);
2304}
2305
2306static int nvme_dev_open(struct inode *inode, struct file *f)
2307{
2308 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2309 miscdev);
2310 kref_get(&dev->kref);
2311 f->private_data = dev;
2312 return 0;
2313}
2314
2315static int nvme_dev_release(struct inode *inode, struct file *f)
2316{
2317 struct nvme_dev *dev = f->private_data;
2318 kref_put(&dev->kref, nvme_free_dev);
2319 return 0;
2320}
2321
2322static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2323{
2324 struct nvme_dev *dev = f->private_data;
2325 switch (cmd) {
2326 case NVME_IOCTL_ADMIN_CMD:
2327 return nvme_user_admin_cmd(dev, (void __user *)arg);
2328 default:
2329 return -ENOTTY;
2330 }
2331}
2332
2333static const struct file_operations nvme_dev_fops = {
2334 .owner = THIS_MODULE,
2335 .open = nvme_dev_open,
2336 .release = nvme_dev_release,
2337 .unlocked_ioctl = nvme_dev_ioctl,
2338 .compat_ioctl = nvme_dev_ioctl,
2339};
2340
f0b50732
KB		 2341static int nvme_dev_start(struct nvme_dev *dev)
2342{
2343 int result;
2344
2345 result = nvme_dev_map(dev);
2346 if (result)
2347 return result;
2348
2349 result = nvme_configure_admin_queue(dev);
2350 if (result)
2351 goto unmap;
2352
2353 spin_lock(&dev_list_lock);
2354 list_add(&dev->node, &dev_list);
2355 spin_unlock(&dev_list_lock);
2356
2357 result = nvme_setup_io_queues(dev);
d82e8bfd 2358 if (result && result != -EBUSY)
f0b50732
KB		 2359 goto disable;
2360
d82e8bfd 2361 return result;
f0b50732
KB		 2362
2363 disable:
a1a5ef99 2364 nvme_disable_queue(dev, 0);
f0b50732
KB		 2365 spin_lock(&dev_list_lock);
2366 list_del_init(&dev->node);
2367 spin_unlock(&dev_list_lock);
2368 unmap:
2369 nvme_dev_unmap(dev);
2370 return result;
2371}
2372
9a6b9458
KB		 2373static int nvme_remove_dead_ctrl(void *arg)
2374{
2375 struct nvme_dev *dev = (struct nvme_dev *)arg;
2376 struct pci_dev *pdev = dev->pci_dev;
2377
2378 if (pci_get_drvdata(pdev))
2379 pci_stop_and_remove_bus_device(pdev);
2380 kref_put(&dev->kref, nvme_free_dev);
2381 return 0;
2382}
2383
2384static void nvme_remove_disks(struct work_struct *ws)
2385{
2386 int i;
2387 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2388
2389 nvme_dev_remove(dev);
2390 spin_lock(&dev_list_lock);
2391 for (i = dev->queue_count - 1; i > 0; i--) {
2392 BUG_ON(!dev->queues[i] || !dev->queues[i]->q_suspended);
2393 nvme_free_queue(dev->queues[i]);
2394 dev->queue_count--;
2395 dev->queues[i] = NULL;
2396 }
2397 spin_unlock(&dev_list_lock);
2398}
2399
2400static int nvme_dev_resume(struct nvme_dev *dev)
2401{
2402 int ret;
2403
2404 ret = nvme_dev_start(dev);
2405 if (ret && ret != -EBUSY)
2406 return ret;
2407 if (ret == -EBUSY) {
2408 spin_lock(&dev_list_lock);
bdfd70fd 2409 PREPARE_WORK(&dev->reset_work, nvme_remove_disks);
9a6b9458
KB		 2410 queue_work(nvme_workq, &dev->reset_work);
2411 spin_unlock(&dev_list_lock);
2412 }
d4b4ff8e 2413 dev->initialized = 1;
9a6b9458
KB		 2414 return 0;
2415}
2416
2417static void nvme_dev_reset(struct nvme_dev *dev)
2418{
2419 nvme_dev_shutdown(dev);
2420 if (nvme_dev_resume(dev)) {
2421 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2422 kref_get(&dev->kref);
2423 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2424 dev->instance))) {
2425 dev_err(&dev->pci_dev->dev,
2426 "Failed to start controller remove task\n");
2427 kref_put(&dev->kref, nvme_free_dev);
2428 }
2429 }
2430}
2431
2432static void nvme_reset_failed_dev(struct work_struct *ws)
2433{
2434 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2435 nvme_dev_reset(dev);
2436}
2437
8d85fce7 2438static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2439{
0877cb0d 2440 int result = -ENOMEM;
b60503ba
MW		 2441 struct nvme_dev *dev;
2442
2443 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2444 if (!dev)
2445 return -ENOMEM;
2446 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2447 GFP_KERNEL);
2448 if (!dev->entry)
2449 goto free;
1b23484b
MW		 2450 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2451 GFP_KERNEL);
b60503ba
MW		 2452 if (!dev->queues)
2453 goto free;
2454
2455 INIT_LIST_HEAD(&dev->namespaces);
bdfd70fd 2456 INIT_WORK(&dev->reset_work, nvme_reset_failed_dev);
b60503ba 2457 dev->pci_dev = pdev;
9a6b9458 2458 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2459 result = nvme_set_instance(dev);
2460 if (result)
0877cb0d 2461 goto free;
b60503ba 2462
091b6092
MW		 2463 result = nvme_setup_prp_pools(dev);
2464 if (result)
0877cb0d 2465 goto release;
091b6092 2466
f0b50732 2467 result = nvme_dev_start(dev);
d82e8bfd
KB		 2468 if (result) {
2469 if (result == -EBUSY)
2470 goto create_cdev;
0877cb0d 2471 goto release_pools;
d82e8bfd 2472 }
b60503ba 2473
9ac27090 2474 kref_init(&dev->kref);
740216fc 2475 result = nvme_dev_add(dev);
d82e8bfd 2476 if (result)
f0b50732 2477 goto shutdown;
740216fc 2478
d82e8bfd 2479 create_cdev:
5e82e952
KB		 2480 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2481 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2482 dev->miscdev.parent = &pdev->dev;
2483 dev->miscdev.name = dev->name;
2484 dev->miscdev.fops = &nvme_dev_fops;
2485 result = misc_register(&dev->miscdev);
2486 if (result)
2487 goto remove;
2488
d4b4ff8e 2489 dev->initialized = 1;
b60503ba
MW		 2490 return 0;
2491
5e82e952
KB		 2492 remove:
2493 nvme_dev_remove(dev);
9ac27090 2494 nvme_free_namespaces(dev);
f0b50732
KB		 2495 shutdown:
2496 nvme_dev_shutdown(dev);
0877cb0d 2497 release_pools:
a1a5ef99 2498 nvme_free_queues(dev, 0);
091b6092 2499 nvme_release_prp_pools(dev);
0877cb0d
KB		 2500 release:
2501 nvme_release_instance(dev);
b60503ba
MW		 2502 free:
2503 kfree(dev->queues);
2504 kfree(dev->entry);
2505 kfree(dev);
2506 return result;
2507}
2508
09ece142
KB		 2509static void nvme_shutdown(struct pci_dev *pdev)
2510{
2511 struct nvme_dev *dev = pci_get_drvdata(pdev);
2512 nvme_dev_shutdown(dev);
2513}
2514
8d85fce7 2515static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2516{
2517 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2518
2519 spin_lock(&dev_list_lock);
2520 list_del_init(&dev->node);
2521 spin_unlock(&dev_list_lock);
2522
2523 pci_set_drvdata(pdev, NULL);
2524 flush_work(&dev->reset_work);
5e82e952 2525 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2526 nvme_dev_remove(dev);
2527 nvme_dev_shutdown(dev);
a1a5ef99 2528 nvme_free_queues(dev, 0);
9a6b9458
KB		 2529 nvme_release_instance(dev);
2530 nvme_release_prp_pools(dev);
5e82e952 2531 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2532}
2533
2534/* These functions are yet to be implemented */
2535#define nvme_error_detected NULL
2536#define nvme_dump_registers NULL
2537#define nvme_link_reset NULL
2538#define nvme_slot_reset NULL
2539#define nvme_error_resume NULL
cd638946
KB		 2540
2541static int nvme_suspend(struct device *dev)
2542{
2543 struct pci_dev *pdev = to_pci_dev(dev);
2544 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2545
2546 nvme_dev_shutdown(ndev);
2547 return 0;
2548}
2549
2550static int nvme_resume(struct device *dev)
2551{
2552 struct pci_dev *pdev = to_pci_dev(dev);
2553 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2554
9a6b9458 2555 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
bdfd70fd 2556 PREPARE_WORK(&ndev->reset_work, nvme_reset_failed_dev);
9a6b9458
KB		 2557 queue_work(nvme_workq, &ndev->reset_work);
2558 }
2559 return 0;
cd638946
KB		 2560}
2561
2562static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2563
1d352035 2564static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2565 .error_detected = nvme_error_detected,
2566 .mmio_enabled = nvme_dump_registers,
2567 .link_reset = nvme_link_reset,
2568 .slot_reset = nvme_slot_reset,
2569 .resume = nvme_error_resume,
2570};
2571
2572/* Move to pci_ids.h later */
2573#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2574
2575static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2576 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2577 { 0, }
2578};
2579MODULE_DEVICE_TABLE(pci, nvme_id_table);
2580
2581static struct pci_driver nvme_driver = {
2582 .name = "nvme",
2583 .id_table = nvme_id_table,
2584 .probe = nvme_probe,
8d85fce7 2585 .remove = nvme_remove,
09ece142 2586 .shutdown = nvme_shutdown,
cd638946
KB		 2587 .driver = {
2588 .pm = &nvme_dev_pm_ops,
2589 },
b60503ba
MW		 2590 .err_handler = &nvme_err_handler,
2591};
2592
2593static int __init nvme_init(void)
2594{
0ac13140 2595 int result;
1fa6aead
MW		 2596
2597 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2598 if (IS_ERR(nvme_thread))
2599 return PTR_ERR(nvme_thread);
b60503ba 2600
9a6b9458
KB		 2601 result = -ENOMEM;
2602 nvme_workq = create_singlethread_workqueue("nvme");
2603 if (!nvme_workq)
2604 goto kill_kthread;
2605
5c42ea16
KB		 2606 result = register_blkdev(nvme_major, "nvme");
2607 if (result < 0)
9a6b9458 2608 goto kill_workq;
5c42ea16 2609 else if (result > 0)
0ac13140 2610 nvme_major = result;
b60503ba
MW		 2611
2612 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2613 if (result)
2614 goto unregister_blkdev;
2615 return 0;
b60503ba 2616
1fa6aead 2617 unregister_blkdev:
b60503ba 2618 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2619 kill_workq:
2620 destroy_workqueue(nvme_workq);
1fa6aead
MW		 2621 kill_kthread:
2622 kthread_stop(nvme_thread);
b60503ba
MW		 2623 return result;
2624}
2625
2626static void __exit nvme_exit(void)
2627{
2628 pci_unregister_driver(&nvme_driver);
2629 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2630 destroy_workqueue(nvme_workq);
1fa6aead 2631 kthread_stop(nvme_thread);
b60503ba
MW		 2632}
2633
2634MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2635MODULE_LICENSE("GPL");
366e8217 2636MODULE_VERSION("0.8");
b60503ba
MW		 2637module_init(nvme_init);
2638module_exit(nvme_exit);
ubuntu-bionic-kernel mirror