1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
35 static void __init
spectre_v2_select_mitigation(void);
36 static void __init
ssb_select_mitigation(void);
37 static void __init
l1tf_select_mitigation(void);
38 static void __init
mds_select_mitigation(void);
40 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
41 u64 x86_spec_ctrl_base
;
42 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base
);
43 static DEFINE_MUTEX(spec_ctrl_mutex
);
46 * The vendor and possibly platform specific bits which can be modified in
49 static u64 __ro_after_init x86_spec_ctrl_mask
= SPEC_CTRL_IBRS
;
52 * AMD specific MSR info for Speculative Store Bypass control.
53 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
55 u64 __ro_after_init x86_amd_ls_cfg_base
;
56 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask
;
58 /* Control conditional STIBP in switch_to() */
59 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp
);
60 /* Control conditional IBPB in switch_mm() */
61 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb
);
62 /* Control unconditional IBPB in switch_mm() */
63 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb
);
65 /* Control MDS CPU buffer clear before returning to user space */
66 DEFINE_STATIC_KEY_FALSE(mds_user_clear
);
67 EXPORT_SYMBOL_GPL(mds_user_clear
);
68 /* Control MDS CPU buffer clear before idling (halt, mwait) */
69 DEFINE_STATIC_KEY_FALSE(mds_idle_clear
);
70 EXPORT_SYMBOL_GPL(mds_idle_clear
);
72 void __init
check_bugs(void)
77 * identify_boot_cpu() initialized SMT support information, let the
80 cpu_smt_check_topology_early();
82 if (!IS_ENABLED(CONFIG_SMP
)) {
84 print_cpu_info(&boot_cpu_data
);
88 * Read the SPEC_CTRL MSR to account for reserved bits which may
89 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
90 * init code as it is not enumerated and depends on the family.
92 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
93 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
95 /* Allow STIBP in MSR_SPEC_CTRL if supported */
96 if (boot_cpu_has(X86_FEATURE_STIBP
))
97 x86_spec_ctrl_mask
|= SPEC_CTRL_STIBP
;
99 /* Select the proper spectre mitigation before patching alternatives */
100 spectre_v2_select_mitigation();
103 * Select proper mitigation for any exposure to the Speculative Store
104 * Bypass vulnerability.
106 ssb_select_mitigation();
108 l1tf_select_mitigation();
110 mds_select_mitigation();
116 * Check whether we are able to run this kernel safely on SMP.
118 * - i386 is no longer supported.
119 * - In order to run on anything without a TSC, we need to be
120 * compiled for a i486.
122 if (boot_cpu_data
.x86
< 4)
123 panic("Kernel requires i486+ for 'invlpg' and other features");
125 init_utsname()->machine
[1] =
126 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
127 alternative_instructions();
129 fpu__init_check_bugs();
130 #else /* CONFIG_X86_64 */
131 alternative_instructions();
134 * Make sure the first 2MB area is not mapped by huge pages
135 * There are typically fixed size MTRRs in there and overlapping
136 * MTRRs into large pages causes slow downs.
138 * Right now we don't do that with gbpages because there seems
139 * very little benefit for that case.
142 set_memory_4k((unsigned long)__va(0), 1);
147 x86_virt_spec_ctrl(u64 guest_spec_ctrl
, u64 guest_virt_spec_ctrl
, bool setguest
)
149 u64 msrval
, guestval
, hostval
= x86_spec_ctrl_base
;
150 struct thread_info
*ti
= current_thread_info();
152 /* Is MSR_SPEC_CTRL implemented ? */
153 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
)) {
155 * Restrict guest_spec_ctrl to supported values. Clear the
156 * modifiable bits in the host base value and or the
157 * modifiable bits from the guest value.
159 guestval
= hostval
& ~x86_spec_ctrl_mask
;
160 guestval
|= guest_spec_ctrl
& x86_spec_ctrl_mask
;
162 /* SSBD controlled in MSR_SPEC_CTRL */
163 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
164 static_cpu_has(X86_FEATURE_AMD_SSBD
))
165 hostval
|= ssbd_tif_to_spec_ctrl(ti
->flags
);
167 /* Conditional STIBP enabled? */
168 if (static_branch_unlikely(&switch_to_cond_stibp
))
169 hostval
|= stibp_tif_to_spec_ctrl(ti
->flags
);
171 if (hostval
!= guestval
) {
172 msrval
= setguest
? guestval
: hostval
;
173 wrmsrl(MSR_IA32_SPEC_CTRL
, msrval
);
178 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
179 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
181 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD
) &&
182 !static_cpu_has(X86_FEATURE_VIRT_SSBD
))
186 * If the host has SSBD mitigation enabled, force it in the host's
187 * virtual MSR value. If its not permanently enabled, evaluate
188 * current's TIF_SSBD thread flag.
190 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
))
191 hostval
= SPEC_CTRL_SSBD
;
193 hostval
= ssbd_tif_to_spec_ctrl(ti
->flags
);
195 /* Sanitize the guest value */
196 guestval
= guest_virt_spec_ctrl
& SPEC_CTRL_SSBD
;
198 if (hostval
!= guestval
) {
201 tif
= setguest
? ssbd_spec_ctrl_to_tif(guestval
) :
202 ssbd_spec_ctrl_to_tif(hostval
);
204 speculation_ctrl_update(tif
);
207 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl
);
209 static void x86_amd_ssb_disable(void)
211 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_ssbd_mask
;
213 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD
))
214 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, SPEC_CTRL_SSBD
);
215 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
))
216 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
220 #define pr_fmt(fmt) "MDS: " fmt
222 /* Default mitigation for L1TF-affected CPUs */
223 static enum mds_mitigations mds_mitigation __ro_after_init
= MDS_MITIGATION_FULL
;
224 static bool mds_nosmt __ro_after_init
= false;
226 static const char * const mds_strings
[] = {
227 [MDS_MITIGATION_OFF
] = "Vulnerable",
228 [MDS_MITIGATION_FULL
] = "Mitigation: Clear CPU buffers",
229 [MDS_MITIGATION_VMWERV
] = "Vulnerable: Clear CPU buffers attempted, no microcode",
232 static void mds_select_mitigation(void)
234 if (!boot_cpu_has_bug(X86_BUG_MDS
)) {
235 mds_mitigation
= MDS_MITIGATION_OFF
;
239 if (mds_mitigation
== MDS_MITIGATION_FULL
) {
240 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR
))
241 mds_mitigation
= MDS_MITIGATION_VMWERV
;
243 static_branch_enable(&mds_user_clear
);
245 if (mds_nosmt
&& !boot_cpu_has(X86_BUG_MSBDS_ONLY
))
246 cpu_smt_disable(false);
249 pr_info("%s\n", mds_strings
[mds_mitigation
]);
252 static int __init
mds_cmdline(char *str
)
254 if (!boot_cpu_has_bug(X86_BUG_MDS
))
260 if (!strcmp(str
, "off"))
261 mds_mitigation
= MDS_MITIGATION_OFF
;
262 else if (!strcmp(str
, "full"))
263 mds_mitigation
= MDS_MITIGATION_FULL
;
264 else if (!strcmp(str
, "full,nosmt")) {
265 mds_mitigation
= MDS_MITIGATION_FULL
;
271 early_param("mds", mds_cmdline
);
274 #define pr_fmt(fmt) "Spectre V2 : " fmt
276 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
279 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init
=
280 SPECTRE_V2_USER_NONE
;
282 #ifdef CONFIG_RETPOLINE
283 static bool spectre_v2_bad_module
;
285 bool retpoline_module_ok(bool has_retpoline
)
287 if (spectre_v2_enabled
== SPECTRE_V2_NONE
|| has_retpoline
)
290 pr_err("System may be vulnerable to spectre v2\n");
291 spectre_v2_bad_module
= true;
295 static inline const char *spectre_v2_module_string(void)
297 return spectre_v2_bad_module
? " - vulnerable module loaded" : "";
300 static inline const char *spectre_v2_module_string(void) { return ""; }
303 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
305 int len
= strlen(opt
);
307 return len
== arglen
&& !strncmp(arg
, opt
, len
);
310 /* The kernel command line selection for spectre v2 */
311 enum spectre_v2_mitigation_cmd
{
314 SPECTRE_V2_CMD_FORCE
,
315 SPECTRE_V2_CMD_RETPOLINE
,
316 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
317 SPECTRE_V2_CMD_RETPOLINE_AMD
,
320 enum spectre_v2_user_cmd
{
321 SPECTRE_V2_USER_CMD_NONE
,
322 SPECTRE_V2_USER_CMD_AUTO
,
323 SPECTRE_V2_USER_CMD_FORCE
,
324 SPECTRE_V2_USER_CMD_PRCTL
,
325 SPECTRE_V2_USER_CMD_PRCTL_IBPB
,
326 SPECTRE_V2_USER_CMD_SECCOMP
,
327 SPECTRE_V2_USER_CMD_SECCOMP_IBPB
,
330 static const char * const spectre_v2_user_strings
[] = {
331 [SPECTRE_V2_USER_NONE
] = "User space: Vulnerable",
332 [SPECTRE_V2_USER_STRICT
] = "User space: Mitigation: STIBP protection",
333 [SPECTRE_V2_USER_STRICT_PREFERRED
] = "User space: Mitigation: STIBP always-on protection",
334 [SPECTRE_V2_USER_PRCTL
] = "User space: Mitigation: STIBP via prctl",
335 [SPECTRE_V2_USER_SECCOMP
] = "User space: Mitigation: STIBP via seccomp and prctl",
338 static const struct {
340 enum spectre_v2_user_cmd cmd
;
342 } v2_user_options
[] __initdata
= {
343 { "auto", SPECTRE_V2_USER_CMD_AUTO
, false },
344 { "off", SPECTRE_V2_USER_CMD_NONE
, false },
345 { "on", SPECTRE_V2_USER_CMD_FORCE
, true },
346 { "prctl", SPECTRE_V2_USER_CMD_PRCTL
, false },
347 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB
, false },
348 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP
, false },
349 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB
, false },
352 static void __init
spec_v2_user_print_cond(const char *reason
, bool secure
)
354 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
355 pr_info("spectre_v2_user=%s forced on command line.\n", reason
);
358 static enum spectre_v2_user_cmd __init
359 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd
)
365 case SPECTRE_V2_CMD_NONE
:
366 return SPECTRE_V2_USER_CMD_NONE
;
367 case SPECTRE_V2_CMD_FORCE
:
368 return SPECTRE_V2_USER_CMD_FORCE
;
373 ret
= cmdline_find_option(boot_command_line
, "spectre_v2_user",
376 return SPECTRE_V2_USER_CMD_AUTO
;
378 for (i
= 0; i
< ARRAY_SIZE(v2_user_options
); i
++) {
379 if (match_option(arg
, ret
, v2_user_options
[i
].option
)) {
380 spec_v2_user_print_cond(v2_user_options
[i
].option
,
381 v2_user_options
[i
].secure
);
382 return v2_user_options
[i
].cmd
;
386 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg
);
387 return SPECTRE_V2_USER_CMD_AUTO
;
391 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd
)
393 enum spectre_v2_user_mitigation mode
= SPECTRE_V2_USER_NONE
;
394 bool smt_possible
= IS_ENABLED(CONFIG_SMP
);
395 enum spectre_v2_user_cmd cmd
;
397 if (!boot_cpu_has(X86_FEATURE_IBPB
) && !boot_cpu_has(X86_FEATURE_STIBP
))
400 if (cpu_smt_control
== CPU_SMT_FORCE_DISABLED
||
401 cpu_smt_control
== CPU_SMT_NOT_SUPPORTED
)
402 smt_possible
= false;
404 cmd
= spectre_v2_parse_user_cmdline(v2_cmd
);
406 case SPECTRE_V2_USER_CMD_NONE
:
408 case SPECTRE_V2_USER_CMD_FORCE
:
409 mode
= SPECTRE_V2_USER_STRICT
;
411 case SPECTRE_V2_USER_CMD_PRCTL
:
412 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
413 mode
= SPECTRE_V2_USER_PRCTL
;
415 case SPECTRE_V2_USER_CMD_AUTO
:
416 case SPECTRE_V2_USER_CMD_SECCOMP
:
417 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
418 if (IS_ENABLED(CONFIG_SECCOMP
))
419 mode
= SPECTRE_V2_USER_SECCOMP
;
421 mode
= SPECTRE_V2_USER_PRCTL
;
426 * At this point, an STIBP mode other than "off" has been set.
427 * If STIBP support is not being forced, check if STIBP always-on
430 if (mode
!= SPECTRE_V2_USER_STRICT
&&
431 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON
))
432 mode
= SPECTRE_V2_USER_STRICT_PREFERRED
;
434 /* Initialize Indirect Branch Prediction Barrier */
435 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
436 setup_force_cpu_cap(X86_FEATURE_USE_IBPB
);
439 case SPECTRE_V2_USER_CMD_FORCE
:
440 case SPECTRE_V2_USER_CMD_PRCTL_IBPB
:
441 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB
:
442 static_branch_enable(&switch_mm_always_ibpb
);
444 case SPECTRE_V2_USER_CMD_PRCTL
:
445 case SPECTRE_V2_USER_CMD_AUTO
:
446 case SPECTRE_V2_USER_CMD_SECCOMP
:
447 static_branch_enable(&switch_mm_cond_ibpb
);
453 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
454 static_key_enabled(&switch_mm_always_ibpb
) ?
455 "always-on" : "conditional");
458 /* If enhanced IBRS is enabled no STIBP required */
459 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
463 * If SMT is not possible or STIBP is not available clear the STIBP
466 if (!smt_possible
|| !boot_cpu_has(X86_FEATURE_STIBP
))
467 mode
= SPECTRE_V2_USER_NONE
;
469 spectre_v2_user
= mode
;
470 /* Only print the STIBP mode when SMT possible */
472 pr_info("%s\n", spectre_v2_user_strings
[mode
]);
475 static const char * const spectre_v2_strings
[] = {
476 [SPECTRE_V2_NONE
] = "Vulnerable",
477 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
478 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
479 [SPECTRE_V2_IBRS_ENHANCED
] = "Mitigation: Enhanced IBRS",
482 static const struct {
484 enum spectre_v2_mitigation_cmd cmd
;
486 } mitigation_options
[] __initdata
= {
487 { "off", SPECTRE_V2_CMD_NONE
, false },
488 { "on", SPECTRE_V2_CMD_FORCE
, true },
489 { "retpoline", SPECTRE_V2_CMD_RETPOLINE
, false },
490 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD
, false },
491 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC
, false },
492 { "auto", SPECTRE_V2_CMD_AUTO
, false },
495 static void __init
spec_v2_print_cond(const char *reason
, bool secure
)
497 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) != secure
)
498 pr_info("%s selected on command line.\n", reason
);
501 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
503 enum spectre_v2_mitigation_cmd cmd
= SPECTRE_V2_CMD_AUTO
;
507 if (cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
508 return SPECTRE_V2_CMD_NONE
;
510 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
, sizeof(arg
));
512 return SPECTRE_V2_CMD_AUTO
;
514 for (i
= 0; i
< ARRAY_SIZE(mitigation_options
); i
++) {
515 if (!match_option(arg
, ret
, mitigation_options
[i
].option
))
517 cmd
= mitigation_options
[i
].cmd
;
521 if (i
>= ARRAY_SIZE(mitigation_options
)) {
522 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
523 return SPECTRE_V2_CMD_AUTO
;
526 if ((cmd
== SPECTRE_V2_CMD_RETPOLINE
||
527 cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
||
528 cmd
== SPECTRE_V2_CMD_RETPOLINE_GENERIC
) &&
529 !IS_ENABLED(CONFIG_RETPOLINE
)) {
530 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options
[i
].option
);
531 return SPECTRE_V2_CMD_AUTO
;
534 if (cmd
== SPECTRE_V2_CMD_RETPOLINE_AMD
&&
535 boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
536 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
537 return SPECTRE_V2_CMD_AUTO
;
540 spec_v2_print_cond(mitigation_options
[i
].option
,
541 mitigation_options
[i
].secure
);
545 static void __init
spectre_v2_select_mitigation(void)
547 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
548 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
551 * If the CPU is not affected and the command line mode is NONE or AUTO
552 * then nothing to do.
554 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
555 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
559 case SPECTRE_V2_CMD_NONE
:
562 case SPECTRE_V2_CMD_FORCE
:
563 case SPECTRE_V2_CMD_AUTO
:
564 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED
)) {
565 mode
= SPECTRE_V2_IBRS_ENHANCED
;
566 /* Force it so VMEXIT will restore correctly */
567 x86_spec_ctrl_base
|= SPEC_CTRL_IBRS
;
568 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
569 goto specv2_set_mode
;
571 if (IS_ENABLED(CONFIG_RETPOLINE
))
574 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
575 if (IS_ENABLED(CONFIG_RETPOLINE
))
578 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
579 if (IS_ENABLED(CONFIG_RETPOLINE
))
580 goto retpoline_generic
;
582 case SPECTRE_V2_CMD_RETPOLINE
:
583 if (IS_ENABLED(CONFIG_RETPOLINE
))
587 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
591 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
593 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
594 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
595 goto retpoline_generic
;
597 mode
= SPECTRE_V2_RETPOLINE_AMD
;
598 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
599 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
602 mode
= SPECTRE_V2_RETPOLINE_GENERIC
;
603 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
607 spectre_v2_enabled
= mode
;
608 pr_info("%s\n", spectre_v2_strings
[mode
]);
611 * If spectre v2 protection has been enabled, unconditionally fill
612 * RSB during a context switch; this protects against two independent
615 * - RSB underflow (and switch to BTB) on Skylake+
616 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
618 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
619 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
622 * Retpoline means the kernel is safe because it has no indirect
623 * branches. Enhanced IBRS protects firmware too, so, enable restricted
624 * speculation around firmware calls only when Enhanced IBRS isn't
627 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
628 * the user might select retpoline on the kernel command line and if
629 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
630 * enable IBRS around firmware calls.
632 if (boot_cpu_has(X86_FEATURE_IBRS
) && mode
!= SPECTRE_V2_IBRS_ENHANCED
) {
633 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW
);
634 pr_info("Enabling Restricted Speculation for firmware calls\n");
637 /* Set up IBPB and STIBP depending on the general spectre V2 command */
638 spectre_v2_user_select_mitigation(cmd
);
641 static void update_stibp_msr(void * __unused
)
643 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
646 /* Update x86_spec_ctrl_base in case SMT state changed. */
647 static void update_stibp_strict(void)
649 u64 mask
= x86_spec_ctrl_base
& ~SPEC_CTRL_STIBP
;
651 if (sched_smt_active())
652 mask
|= SPEC_CTRL_STIBP
;
654 if (mask
== x86_spec_ctrl_base
)
657 pr_info("Update user space SMT mitigation: STIBP %s\n",
658 mask
& SPEC_CTRL_STIBP
? "always-on" : "off");
659 x86_spec_ctrl_base
= mask
;
660 on_each_cpu(update_stibp_msr
, NULL
, 1);
663 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
664 static void update_indir_branch_cond(void)
666 if (sched_smt_active())
667 static_branch_enable(&switch_to_cond_stibp
);
669 static_branch_disable(&switch_to_cond_stibp
);
672 /* Update the static key controlling the MDS CPU buffer clear in idle */
673 static void update_mds_branch_idle(void)
676 * Enable the idle clearing on CPUs which are affected only by
677 * MDBDS and not any other MDS variant. The other variants cannot
678 * be mitigated when SMT is enabled, so clearing the buffers on
679 * idle would be a window dressing exercise.
681 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY
))
684 if (sched_smt_active())
685 static_branch_enable(&mds_idle_clear
);
687 static_branch_disable(&mds_idle_clear
);
690 void arch_smt_update(void)
692 /* Enhanced IBRS implies STIBP. No update required. */
693 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
696 mutex_lock(&spec_ctrl_mutex
);
698 switch (spectre_v2_user
) {
699 case SPECTRE_V2_USER_NONE
:
701 case SPECTRE_V2_USER_STRICT
:
702 case SPECTRE_V2_USER_STRICT_PREFERRED
:
703 update_stibp_strict();
705 case SPECTRE_V2_USER_PRCTL
:
706 case SPECTRE_V2_USER_SECCOMP
:
707 update_indir_branch_cond();
711 switch(mds_mitigation
) {
712 case MDS_MITIGATION_FULL
:
713 case MDS_MITIGATION_VMWERV
:
714 update_mds_branch_idle();
716 case MDS_MITIGATION_OFF
:
720 mutex_unlock(&spec_ctrl_mutex
);
724 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
726 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
728 /* The kernel command line selection */
729 enum ssb_mitigation_cmd
{
730 SPEC_STORE_BYPASS_CMD_NONE
,
731 SPEC_STORE_BYPASS_CMD_AUTO
,
732 SPEC_STORE_BYPASS_CMD_ON
,
733 SPEC_STORE_BYPASS_CMD_PRCTL
,
734 SPEC_STORE_BYPASS_CMD_SECCOMP
,
737 static const char * const ssb_strings
[] = {
738 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
739 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
740 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl",
741 [SPEC_STORE_BYPASS_SECCOMP
] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
744 static const struct {
746 enum ssb_mitigation_cmd cmd
;
747 } ssb_mitigation_options
[] __initdata
= {
748 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
749 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
750 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
751 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
752 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP
}, /* Disable Speculative Store Bypass via prctl and seccomp */
755 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
757 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
761 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
762 return SPEC_STORE_BYPASS_CMD_NONE
;
764 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
767 return SPEC_STORE_BYPASS_CMD_AUTO
;
769 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
770 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
773 cmd
= ssb_mitigation_options
[i
].cmd
;
777 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
778 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
779 return SPEC_STORE_BYPASS_CMD_AUTO
;
786 static enum ssb_mitigation __init
__ssb_select_mitigation(void)
788 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
789 enum ssb_mitigation_cmd cmd
;
791 if (!boot_cpu_has(X86_FEATURE_SSBD
))
794 cmd
= ssb_parse_cmdline();
795 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
796 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
797 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
801 case SPEC_STORE_BYPASS_CMD_AUTO
:
802 case SPEC_STORE_BYPASS_CMD_SECCOMP
:
804 * Choose prctl+seccomp as the default mode if seccomp is
807 if (IS_ENABLED(CONFIG_SECCOMP
))
808 mode
= SPEC_STORE_BYPASS_SECCOMP
;
810 mode
= SPEC_STORE_BYPASS_PRCTL
;
812 case SPEC_STORE_BYPASS_CMD_ON
:
813 mode
= SPEC_STORE_BYPASS_DISABLE
;
815 case SPEC_STORE_BYPASS_CMD_PRCTL
:
816 mode
= SPEC_STORE_BYPASS_PRCTL
;
818 case SPEC_STORE_BYPASS_CMD_NONE
:
823 * We have three CPU feature flags that are in play here:
824 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
825 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
826 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
828 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
829 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
831 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
832 * use a completely different MSR and bit dependent on family.
834 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) &&
835 !static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
836 x86_amd_ssb_disable();
838 x86_spec_ctrl_base
|= SPEC_CTRL_SSBD
;
839 x86_spec_ctrl_mask
|= SPEC_CTRL_SSBD
;
840 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
847 static void ssb_select_mitigation(void)
849 ssb_mode
= __ssb_select_mitigation();
851 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
852 pr_info("%s\n", ssb_strings
[ssb_mode
]);
856 #define pr_fmt(fmt) "Speculation prctl: " fmt
858 static void task_update_spec_tif(struct task_struct
*tsk
)
860 /* Force the update of the real TIF bits */
861 set_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
);
864 * Immediately update the speculation control MSRs for the current
865 * task, but for a non-current task delay setting the CPU
866 * mitigation until it is scheduled next.
868 * This can only happen for SECCOMP mitigation. For PRCTL it's
869 * always the current task.
872 speculation_ctrl_update_current();
875 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
877 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
&&
878 ssb_mode
!= SPEC_STORE_BYPASS_SECCOMP
)
883 /* If speculation is force disabled, enable is not allowed */
884 if (task_spec_ssb_force_disable(task
))
886 task_clear_spec_ssb_disable(task
);
887 task_update_spec_tif(task
);
889 case PR_SPEC_DISABLE
:
890 task_set_spec_ssb_disable(task
);
891 task_update_spec_tif(task
);
893 case PR_SPEC_FORCE_DISABLE
:
894 task_set_spec_ssb_disable(task
);
895 task_set_spec_ssb_force_disable(task
);
896 task_update_spec_tif(task
);
904 static int ib_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
908 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
911 * Indirect branch speculation is always disabled in strict
914 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
915 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
917 task_clear_spec_ib_disable(task
);
918 task_update_spec_tif(task
);
920 case PR_SPEC_DISABLE
:
921 case PR_SPEC_FORCE_DISABLE
:
923 * Indirect branch speculation is always allowed when
924 * mitigation is force disabled.
926 if (spectre_v2_user
== SPECTRE_V2_USER_NONE
)
928 if (spectre_v2_user
== SPECTRE_V2_USER_STRICT
||
929 spectre_v2_user
== SPECTRE_V2_USER_STRICT_PREFERRED
)
931 task_set_spec_ib_disable(task
);
932 if (ctrl
== PR_SPEC_FORCE_DISABLE
)
933 task_set_spec_ib_force_disable(task
);
934 task_update_spec_tif(task
);
942 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
946 case PR_SPEC_STORE_BYPASS
:
947 return ssb_prctl_set(task
, ctrl
);
948 case PR_SPEC_INDIRECT_BRANCH
:
949 return ib_prctl_set(task
, ctrl
);
955 #ifdef CONFIG_SECCOMP
956 void arch_seccomp_spec_mitigate(struct task_struct
*task
)
958 if (ssb_mode
== SPEC_STORE_BYPASS_SECCOMP
)
959 ssb_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
960 if (spectre_v2_user
== SPECTRE_V2_USER_SECCOMP
)
961 ib_prctl_set(task
, PR_SPEC_FORCE_DISABLE
);
965 static int ssb_prctl_get(struct task_struct
*task
)
968 case SPEC_STORE_BYPASS_DISABLE
:
969 return PR_SPEC_DISABLE
;
970 case SPEC_STORE_BYPASS_SECCOMP
:
971 case SPEC_STORE_BYPASS_PRCTL
:
972 if (task_spec_ssb_force_disable(task
))
973 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
974 if (task_spec_ssb_disable(task
))
975 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
976 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
978 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
979 return PR_SPEC_ENABLE
;
980 return PR_SPEC_NOT_AFFECTED
;
984 static int ib_prctl_get(struct task_struct
*task
)
986 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
987 return PR_SPEC_NOT_AFFECTED
;
989 switch (spectre_v2_user
) {
990 case SPECTRE_V2_USER_NONE
:
991 return PR_SPEC_ENABLE
;
992 case SPECTRE_V2_USER_PRCTL
:
993 case SPECTRE_V2_USER_SECCOMP
:
994 if (task_spec_ib_force_disable(task
))
995 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
996 if (task_spec_ib_disable(task
))
997 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
998 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
999 case SPECTRE_V2_USER_STRICT
:
1000 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1001 return PR_SPEC_DISABLE
;
1003 return PR_SPEC_NOT_AFFECTED
;
1007 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
1010 case PR_SPEC_STORE_BYPASS
:
1011 return ssb_prctl_get(task
);
1012 case PR_SPEC_INDIRECT_BRANCH
:
1013 return ib_prctl_get(task
);
1019 void x86_spec_ctrl_setup_ap(void)
1021 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL
))
1022 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1024 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
1025 x86_amd_ssb_disable();
1029 #define pr_fmt(fmt) "L1TF: " fmt
1031 /* Default mitigation for L1TF-affected CPUs */
1032 enum l1tf_mitigations l1tf_mitigation __ro_after_init
= L1TF_MITIGATION_FLUSH
;
1033 #if IS_ENABLED(CONFIG_KVM_INTEL)
1034 EXPORT_SYMBOL_GPL(l1tf_mitigation
);
1036 enum vmx_l1d_flush_state l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
1037 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation
);
1041 * These CPUs all support 44bits physical address space internally in the
1042 * cache but CPUID can report a smaller number of physical address bits.
1044 * The L1TF mitigation uses the top most address bit for the inversion of
1045 * non present PTEs. When the installed memory reaches into the top most
1046 * address bit due to memory holes, which has been observed on machines
1047 * which report 36bits physical address bits and have 32G RAM installed,
1048 * then the mitigation range check in l1tf_select_mitigation() triggers.
1049 * This is a false positive because the mitigation is still possible due to
1050 * the fact that the cache uses 44bit internally. Use the cache bits
1051 * instead of the reported physical bits and adjust them on the affected
1052 * machines to 44bit if the reported bits are less than 44.
1054 static void override_cache_bits(struct cpuinfo_x86
*c
)
1059 switch (c
->x86_model
) {
1060 case INTEL_FAM6_NEHALEM
:
1061 case INTEL_FAM6_WESTMERE
:
1062 case INTEL_FAM6_SANDYBRIDGE
:
1063 case INTEL_FAM6_IVYBRIDGE
:
1064 case INTEL_FAM6_HASWELL_CORE
:
1065 case INTEL_FAM6_HASWELL_ULT
:
1066 case INTEL_FAM6_HASWELL_GT3E
:
1067 case INTEL_FAM6_BROADWELL_CORE
:
1068 case INTEL_FAM6_BROADWELL_GT3E
:
1069 case INTEL_FAM6_SKYLAKE_MOBILE
:
1070 case INTEL_FAM6_SKYLAKE_DESKTOP
:
1071 case INTEL_FAM6_KABYLAKE_MOBILE
:
1072 case INTEL_FAM6_KABYLAKE_DESKTOP
:
1073 if (c
->x86_cache_bits
< 44)
1074 c
->x86_cache_bits
= 44;
1079 static void __init
l1tf_select_mitigation(void)
1083 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1086 override_cache_bits(&boot_cpu_data
);
1088 switch (l1tf_mitigation
) {
1089 case L1TF_MITIGATION_OFF
:
1090 case L1TF_MITIGATION_FLUSH_NOWARN
:
1091 case L1TF_MITIGATION_FLUSH
:
1093 case L1TF_MITIGATION_FLUSH_NOSMT
:
1094 case L1TF_MITIGATION_FULL
:
1095 cpu_smt_disable(false);
1097 case L1TF_MITIGATION_FULL_FORCE
:
1098 cpu_smt_disable(true);
1102 #if CONFIG_PGTABLE_LEVELS == 2
1103 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1107 half_pa
= (u64
)l1tf_pfn_limit() << PAGE_SHIFT
;
1108 if (e820__mapped_any(half_pa
, ULLONG_MAX
- half_pa
, E820_TYPE_RAM
)) {
1109 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1110 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1112 pr_info("However, doing so will make a part of your RAM unusable.\n");
1113 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
1117 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV
);
1120 static int __init
l1tf_cmdline(char *str
)
1122 if (!boot_cpu_has_bug(X86_BUG_L1TF
))
1128 if (!strcmp(str
, "off"))
1129 l1tf_mitigation
= L1TF_MITIGATION_OFF
;
1130 else if (!strcmp(str
, "flush,nowarn"))
1131 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOWARN
;
1132 else if (!strcmp(str
, "flush"))
1133 l1tf_mitigation
= L1TF_MITIGATION_FLUSH
;
1134 else if (!strcmp(str
, "flush,nosmt"))
1135 l1tf_mitigation
= L1TF_MITIGATION_FLUSH_NOSMT
;
1136 else if (!strcmp(str
, "full"))
1137 l1tf_mitigation
= L1TF_MITIGATION_FULL
;
1138 else if (!strcmp(str
, "full,force"))
1139 l1tf_mitigation
= L1TF_MITIGATION_FULL_FORCE
;
1143 early_param("l1tf", l1tf_cmdline
);
1149 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1151 #if IS_ENABLED(CONFIG_KVM_INTEL)
1152 static const char * const l1tf_vmx_states
[] = {
1153 [VMENTER_L1D_FLUSH_AUTO
] = "auto",
1154 [VMENTER_L1D_FLUSH_NEVER
] = "vulnerable",
1155 [VMENTER_L1D_FLUSH_COND
] = "conditional cache flushes",
1156 [VMENTER_L1D_FLUSH_ALWAYS
] = "cache flushes",
1157 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = "EPT disabled",
1158 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = "flush not necessary"
1161 static ssize_t
l1tf_show_state(char *buf
)
1163 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
)
1164 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1166 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_EPT_DISABLED
||
1167 (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
&&
1168 sched_smt_active())) {
1169 return sprintf(buf
, "%s; VMX: %s\n", L1TF_DEFAULT_MSG
,
1170 l1tf_vmx_states
[l1tf_vmx_mitigation
]);
1173 return sprintf(buf
, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG
,
1174 l1tf_vmx_states
[l1tf_vmx_mitigation
],
1175 sched_smt_active() ? "vulnerable" : "disabled");
1178 static ssize_t
l1tf_show_state(char *buf
)
1180 return sprintf(buf
, "%s\n", L1TF_DEFAULT_MSG
);
1184 static ssize_t
mds_show_state(char *buf
)
1186 if (!hypervisor_is_type(X86_HYPER_NATIVE
)) {
1187 return sprintf(buf
, "%s; SMT Host state unknown\n",
1188 mds_strings
[mds_mitigation
]);
1191 if (boot_cpu_has(X86_BUG_MSBDS_ONLY
)) {
1192 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1193 sched_smt_active() ? "mitigated" : "disabled");
1196 return sprintf(buf
, "%s; SMT %s\n", mds_strings
[mds_mitigation
],
1197 sched_smt_active() ? "vulnerable" : "disabled");
1200 static char *stibp_state(void)
1202 if (spectre_v2_enabled
== SPECTRE_V2_IBRS_ENHANCED
)
1205 switch (spectre_v2_user
) {
1206 case SPECTRE_V2_USER_NONE
:
1207 return ", STIBP: disabled";
1208 case SPECTRE_V2_USER_STRICT
:
1209 return ", STIBP: forced";
1210 case SPECTRE_V2_USER_STRICT_PREFERRED
:
1211 return ", STIBP: always-on";
1212 case SPECTRE_V2_USER_PRCTL
:
1213 case SPECTRE_V2_USER_SECCOMP
:
1214 if (static_key_enabled(&switch_to_cond_stibp
))
1215 return ", STIBP: conditional";
1220 static char *ibpb_state(void)
1222 if (boot_cpu_has(X86_FEATURE_IBPB
)) {
1223 if (static_key_enabled(&switch_mm_always_ibpb
))
1224 return ", IBPB: always-on";
1225 if (static_key_enabled(&switch_mm_cond_ibpb
))
1226 return ", IBPB: conditional";
1227 return ", IBPB: disabled";
1232 static ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
1233 char *buf
, unsigned int bug
)
1235 if (!boot_cpu_has_bug(bug
))
1236 return sprintf(buf
, "Not affected\n");
1239 case X86_BUG_CPU_MELTDOWN
:
1240 if (boot_cpu_has(X86_FEATURE_PTI
))
1241 return sprintf(buf
, "Mitigation: PTI\n");
1245 case X86_BUG_SPECTRE_V1
:
1246 return sprintf(buf
, "Mitigation: __user pointer sanitization\n");
1248 case X86_BUG_SPECTRE_V2
:
1249 return sprintf(buf
, "%s%s%s%s%s%s\n", spectre_v2_strings
[spectre_v2_enabled
],
1251 boot_cpu_has(X86_FEATURE_USE_IBRS_FW
) ? ", IBRS_FW" : "",
1253 boot_cpu_has(X86_FEATURE_RSB_CTXSW
) ? ", RSB filling" : "",
1254 spectre_v2_module_string());
1256 case X86_BUG_SPEC_STORE_BYPASS
:
1257 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
1260 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV
))
1261 return l1tf_show_state(buf
);
1265 return mds_show_state(buf
);
1271 return sprintf(buf
, "Vulnerable\n");
1274 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1276 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
1279 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1281 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
1284 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1286 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
1289 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1291 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);
1294 ssize_t
cpu_show_l1tf(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1296 return cpu_show_common(dev
, attr
, buf
, X86_BUG_L1TF
);
1299 ssize_t
cpu_show_mds(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1301 return cpu_show_common(dev
, attr
, buf
, X86_BUG_MDS
);