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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1122cc78 | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
da285121 | 35 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 36 | static void __init ssb_select_mitigation(void); |
05516ad8 | 37 | static void __init l1tf_select_mitigation(void); |
fc5ee888 | 38 | static void __init mds_select_mitigation(void); |
da285121 | 39 | |
7011f443 JK |
40 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
41 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 42 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 43 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 44 | |
d0c3bedd KRW |
45 | /* |
46 | * The vendor and possibly platform specific bits which can be modified in | |
47 | * x86_spec_ctrl_base. | |
48 | */ | |
e5f984ed | 49 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 50 | |
c37b94dd KRW |
51 | /* |
52 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 53 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
54 | */ |
55 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 56 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 57 | |
8edb388f | 58 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 59 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
60 | /* Control conditional IBPB in switch_mm() */ |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
62 | /* Control unconditional IBPB in switch_mm() */ | |
63 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 64 | |
5ab15133 TG |
65 | /* Control MDS CPU buffer clear before returning to user space */ |
66 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 67 | EXPORT_SYMBOL_GPL(mds_user_clear); |
f3eb8f09 TG |
68 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
69 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
70 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
5ab15133 | 71 | |
1353ebb4 JF |
72 | void __init check_bugs(void) |
73 | { | |
74 | identify_boot_cpu(); | |
55a36b65 | 75 | |
483ec3c6 TG |
76 | /* |
77 | * identify_boot_cpu() initialized SMT support information, let the | |
78 | * core code know. | |
79 | */ | |
ade31b9e | 80 | cpu_smt_check_topology_early(); |
483ec3c6 | 81 | |
62a67e12 BP |
82 | if (!IS_ENABLED(CONFIG_SMP)) { |
83 | pr_info("CPU: "); | |
84 | print_cpu_info(&boot_cpu_data); | |
85 | } | |
86 | ||
296b454a KRW |
87 | /* |
88 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
89 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
90 | * init code as it is not enumerated and depends on the family. | |
296b454a | 91 | */ |
50f9b919 | 92 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
93 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
94 | ||
e5f984ed TG |
95 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
96 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
97 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
98 | ||
da285121 DW |
99 | /* Select the proper spectre mitigation before patching alternatives */ |
100 | spectre_v2_select_mitigation(); | |
101 | ||
e63490c8 KRW |
102 | /* |
103 | * Select proper mitigation for any exposure to the Speculative Store | |
104 | * Bypass vulnerability. | |
105 | */ | |
106 | ssb_select_mitigation(); | |
107 | ||
05516ad8 AK |
108 | l1tf_select_mitigation(); |
109 | ||
fc5ee888 TG |
110 | mds_select_mitigation(); |
111 | ||
15ff73d9 JP |
112 | arch_smt_update(); |
113 | ||
62a67e12 | 114 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
115 | /* |
116 | * Check whether we are able to run this kernel safely on SMP. | |
117 | * | |
118 | * - i386 is no longer supported. | |
119 | * - In order to run on anything without a TSC, we need to be | |
120 | * compiled for a i486. | |
121 | */ | |
122 | if (boot_cpu_data.x86 < 4) | |
123 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
124 | ||
bfe4bb15 MV |
125 | init_utsname()->machine[1] = |
126 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 127 | alternative_instructions(); |
304bceda | 128 | |
4d164092 | 129 | fpu__init_check_bugs(); |
62a67e12 BP |
130 | #else /* CONFIG_X86_64 */ |
131 | alternative_instructions(); | |
132 | ||
133 | /* | |
134 | * Make sure the first 2MB area is not mapped by huge pages | |
135 | * There are typically fixed size MTRRs in there and overlapping | |
136 | * MTRRs into large pages causes slow downs. | |
137 | * | |
138 | * Right now we don't do that with gbpages because there seems | |
139 | * very little benefit for that case. | |
140 | */ | |
141 | if (!direct_gbpages) | |
142 | set_memory_4k((unsigned long)__va(0), 1); | |
143 | #endif | |
1353ebb4 | 144 | } |
61dc0f55 | 145 | |
12376b62 BP |
146 | void |
147 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 148 | { |
e5f984ed | 149 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 150 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 151 | |
50f9b919 | 152 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 153 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
154 | /* |
155 | * Restrict guest_spec_ctrl to supported values. Clear the | |
156 | * modifiable bits in the host base value and or the | |
157 | * modifiable bits from the guest value. | |
158 | */ | |
159 | guestval = hostval & ~x86_spec_ctrl_mask; | |
160 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
161 | ||
12376b62 | 162 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
163 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
164 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 165 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 166 | |
e0b04783 TC |
167 | /* Conditional STIBP enabled? */ |
168 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
169 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
170 | ||
e5f984ed TG |
171 | if (hostval != guestval) { |
172 | msrval = setguest ? guestval : hostval; | |
173 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
174 | } |
175 | } | |
1238ed31 TG |
176 | |
177 | /* | |
178 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
179 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
180 | */ | |
181 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
182 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
183 | return; | |
184 | ||
185 | /* | |
186 | * If the host has SSBD mitigation enabled, force it in the host's | |
187 | * virtual MSR value. If its not permanently enabled, evaluate | |
188 | * current's TIF_SSBD thread flag. | |
189 | */ | |
190 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
191 | hostval = SPEC_CTRL_SSBD; | |
192 | else | |
193 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
194 | ||
195 | /* Sanitize the guest value */ | |
196 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
197 | ||
198 | if (hostval != guestval) { | |
199 | unsigned long tif; | |
200 | ||
201 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
202 | ssbd_spec_ctrl_to_tif(hostval); | |
203 | ||
8fce7184 | 204 | speculation_ctrl_update(tif); |
1238ed31 | 205 | } |
19fff03f | 206 | } |
12376b62 | 207 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 208 | |
8fe36c9d | 209 | static void x86_amd_ssb_disable(void) |
c37b94dd | 210 | { |
8fe36c9d | 211 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 212 | |
65e02bbd TL |
213 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
214 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
215 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
216 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
217 | } | |
218 | ||
fc5ee888 TG |
219 | #undef pr_fmt |
220 | #define pr_fmt(fmt) "MDS: " fmt | |
221 | ||
222 | /* Default mitigation for L1TF-affected CPUs */ | |
223 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; | |
e2f3c337 | 224 | static bool mds_nosmt __ro_after_init = false; |
fc5ee888 TG |
225 | |
226 | static const char * const mds_strings[] = { | |
227 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
ebf1e8cb TG |
228 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
229 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
fc5ee888 TG |
230 | }; |
231 | ||
232 | static void mds_select_mitigation(void) | |
233 | { | |
234 | if (!boot_cpu_has_bug(X86_BUG_MDS)) { | |
235 | mds_mitigation = MDS_MITIGATION_OFF; | |
236 | return; | |
237 | } | |
238 | ||
239 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
ebf1e8cb TG |
240 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
241 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
e2f3c337 | 242 | |
ebf1e8cb | 243 | static_branch_enable(&mds_user_clear); |
e2f3c337 JP |
244 | |
245 | if (mds_nosmt && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) | |
246 | cpu_smt_disable(false); | |
fc5ee888 | 247 | } |
e2f3c337 | 248 | |
fc5ee888 TG |
249 | pr_info("%s\n", mds_strings[mds_mitigation]); |
250 | } | |
251 | ||
252 | static int __init mds_cmdline(char *str) | |
253 | { | |
254 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
255 | return 0; | |
256 | ||
257 | if (!str) | |
258 | return -EINVAL; | |
259 | ||
260 | if (!strcmp(str, "off")) | |
261 | mds_mitigation = MDS_MITIGATION_OFF; | |
262 | else if (!strcmp(str, "full")) | |
263 | mds_mitigation = MDS_MITIGATION_FULL; | |
e2f3c337 JP |
264 | else if (!strcmp(str, "full,nosmt")) { |
265 | mds_mitigation = MDS_MITIGATION_FULL; | |
266 | mds_nosmt = true; | |
267 | } | |
fc5ee888 TG |
268 | |
269 | return 0; | |
270 | } | |
271 | early_param("mds", mds_cmdline); | |
272 | ||
aef0bebc TG |
273 | #undef pr_fmt |
274 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
275 | ||
276 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
277 | SPECTRE_V2_NONE; | |
278 | ||
6cd930f0 TG |
279 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
280 | SPECTRE_V2_USER_NONE; | |
281 | ||
e9a556ad | 282 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
283 | static bool spectre_v2_bad_module; |
284 | ||
d280282b AK |
285 | bool retpoline_module_ok(bool has_retpoline) |
286 | { | |
287 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
288 | return true; | |
289 | ||
c8b8e109 | 290 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
291 | spectre_v2_bad_module = true; |
292 | return false; | |
293 | } | |
bb3c2578 TG |
294 | |
295 | static inline const char *spectre_v2_module_string(void) | |
296 | { | |
297 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
298 | } | |
299 | #else | |
300 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 301 | #endif |
da285121 | 302 | |
da285121 DW |
303 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
304 | { | |
305 | int len = strlen(opt); | |
306 | ||
307 | return len == arglen && !strncmp(arg, opt, len); | |
308 | } | |
309 | ||
aef0bebc TG |
310 | /* The kernel command line selection for spectre v2 */ |
311 | enum spectre_v2_mitigation_cmd { | |
312 | SPECTRE_V2_CMD_NONE, | |
313 | SPECTRE_V2_CMD_AUTO, | |
314 | SPECTRE_V2_CMD_FORCE, | |
315 | SPECTRE_V2_CMD_RETPOLINE, | |
316 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
317 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
318 | }; | |
319 | ||
6cd930f0 TG |
320 | enum spectre_v2_user_cmd { |
321 | SPECTRE_V2_USER_CMD_NONE, | |
322 | SPECTRE_V2_USER_CMD_AUTO, | |
323 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 324 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 325 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 326 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 327 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
328 | }; |
329 | ||
330 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
331 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
332 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
333 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
334 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
335 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
336 | }; |
337 | ||
338 | static const struct { | |
339 | const char *option; | |
340 | enum spectre_v2_user_cmd cmd; | |
341 | bool secure; | |
342 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
343 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
344 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
345 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
346 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
347 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
348 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
349 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
350 | }; |
351 | ||
352 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
353 | { | |
354 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
355 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
356 | } | |
357 | ||
358 | static enum spectre_v2_user_cmd __init | |
359 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
360 | { | |
361 | char arg[20]; | |
362 | int ret, i; | |
363 | ||
364 | switch (v2_cmd) { | |
365 | case SPECTRE_V2_CMD_NONE: | |
366 | return SPECTRE_V2_USER_CMD_NONE; | |
367 | case SPECTRE_V2_CMD_FORCE: | |
368 | return SPECTRE_V2_USER_CMD_FORCE; | |
369 | default: | |
370 | break; | |
371 | } | |
372 | ||
373 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
374 | arg, sizeof(arg)); | |
375 | if (ret < 0) | |
376 | return SPECTRE_V2_USER_CMD_AUTO; | |
377 | ||
378 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
379 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
380 | spec_v2_user_print_cond(v2_user_options[i].option, | |
381 | v2_user_options[i].secure); | |
382 | return v2_user_options[i].cmd; | |
383 | } | |
384 | } | |
385 | ||
386 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
387 | return SPECTRE_V2_USER_CMD_AUTO; | |
388 | } | |
389 | ||
390 | static void __init | |
391 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
392 | { | |
393 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
394 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 395 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
396 | |
397 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
398 | return; | |
399 | ||
400 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
401 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
402 | smt_possible = false; | |
403 | ||
fd1b7023 TG |
404 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
405 | switch (cmd) { | |
6cd930f0 TG |
406 | case SPECTRE_V2_USER_CMD_NONE: |
407 | goto set_mode; | |
408 | case SPECTRE_V2_USER_CMD_FORCE: | |
409 | mode = SPECTRE_V2_USER_STRICT; | |
410 | break; | |
2cdf6a58 | 411 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 412 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
413 | mode = SPECTRE_V2_USER_PRCTL; |
414 | break; | |
1c3cf627 TG |
415 | case SPECTRE_V2_USER_CMD_AUTO: |
416 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 417 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
418 | if (IS_ENABLED(CONFIG_SECCOMP)) |
419 | mode = SPECTRE_V2_USER_SECCOMP; | |
420 | else | |
421 | mode = SPECTRE_V2_USER_PRCTL; | |
422 | break; | |
6cd930f0 TG |
423 | } |
424 | ||
fbed8eca TL |
425 | /* |
426 | * At this point, an STIBP mode other than "off" has been set. | |
427 | * If STIBP support is not being forced, check if STIBP always-on | |
428 | * is preferred. | |
429 | */ | |
430 | if (mode != SPECTRE_V2_USER_STRICT && | |
431 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
432 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
433 | ||
6cd930f0 TG |
434 | /* Initialize Indirect Branch Prediction Barrier */ |
435 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
436 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 437 | |
fd1b7023 TG |
438 | switch (cmd) { |
439 | case SPECTRE_V2_USER_CMD_FORCE: | |
440 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
441 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
442 | static_branch_enable(&switch_mm_always_ibpb); |
443 | break; | |
fd1b7023 TG |
444 | case SPECTRE_V2_USER_CMD_PRCTL: |
445 | case SPECTRE_V2_USER_CMD_AUTO: | |
446 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
447 | static_branch_enable(&switch_mm_cond_ibpb); |
448 | break; | |
58b2d4c8 TG |
449 | default: |
450 | break; | |
451 | } | |
452 | ||
453 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
454 | static_key_enabled(&switch_mm_always_ibpb) ? |
455 | "always-on" : "conditional"); | |
6cd930f0 TG |
456 | } |
457 | ||
8edb388f | 458 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
459 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
460 | return; | |
461 | ||
2cdf6a58 | 462 | /* |
8edb388f | 463 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
464 | * mode. |
465 | */ | |
466 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
467 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
468 | set_mode: |
469 | spectre_v2_user = mode; | |
470 | /* Only print the STIBP mode when SMT possible */ | |
471 | if (smt_possible) | |
472 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
473 | } | |
474 | ||
0eb5928b | 475 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
476 | [SPECTRE_V2_NONE] = "Vulnerable", |
477 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
478 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
479 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
480 | }; | |
481 | ||
17c33e7c KA |
482 | static const struct { |
483 | const char *option; | |
484 | enum spectre_v2_mitigation_cmd cmd; | |
485 | bool secure; | |
5a76cb46 | 486 | } mitigation_options[] __initdata = { |
aef0bebc TG |
487 | { "off", SPECTRE_V2_CMD_NONE, false }, |
488 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
489 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
490 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
491 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
492 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
493 | }; |
494 | ||
10640103 | 495 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 496 | { |
10640103 | 497 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
498 | pr_info("%s selected on command line.\n", reason); |
499 | } | |
500 | ||
da285121 DW |
501 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
502 | { | |
aef0bebc | 503 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 504 | char arg[20]; |
17c33e7c | 505 | int ret, i; |
17c33e7c KA |
506 | |
507 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
508 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 509 | |
4e8e955a TC |
510 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
511 | if (ret < 0) | |
512 | return SPECTRE_V2_CMD_AUTO; | |
513 | ||
514 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
515 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
516 | continue; | |
517 | cmd = mitigation_options[i].cmd; | |
518 | break; | |
519 | } | |
520 | ||
521 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
522 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
523 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
524 | } |
525 | ||
17c33e7c KA |
526 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
527 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
528 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
529 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 530 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 531 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
532 | } |
533 | ||
534 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
535 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
536 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
537 | return SPECTRE_V2_CMD_AUTO; | |
538 | } | |
539 | ||
10640103 TG |
540 | spec_v2_print_cond(mitigation_options[i].option, |
541 | mitigation_options[i].secure); | |
17c33e7c | 542 | return cmd; |
da285121 DW |
543 | } |
544 | ||
545 | static void __init spectre_v2_select_mitigation(void) | |
546 | { | |
547 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
548 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
549 | ||
550 | /* | |
551 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
552 | * then nothing to do. | |
553 | */ | |
554 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
555 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
556 | return; | |
557 | ||
558 | switch (cmd) { | |
559 | case SPECTRE_V2_CMD_NONE: | |
560 | return; | |
561 | ||
562 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 563 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
564 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
565 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
566 | /* Force it so VMEXIT will restore correctly */ | |
567 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
568 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
569 | goto specv2_set_mode; | |
570 | } | |
d0f293e0 DL |
571 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
572 | goto retpoline_auto; | |
573 | break; | |
da285121 DW |
574 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
575 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
576 | goto retpoline_amd; | |
577 | break; | |
578 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
579 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
580 | goto retpoline_generic; | |
581 | break; | |
582 | case SPECTRE_V2_CMD_RETPOLINE: | |
583 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
584 | goto retpoline_auto; | |
585 | break; | |
586 | } | |
713f1b95 | 587 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
588 | return; |
589 | ||
590 | retpoline_auto: | |
591 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
592 | retpoline_amd: | |
593 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 594 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
595 | goto retpoline_generic; |
596 | } | |
51dd01b5 | 597 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
598 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
599 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
600 | } else { | |
601 | retpoline_generic: | |
51dd01b5 | 602 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
603 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
604 | } | |
605 | ||
1044fde9 | 606 | specv2_set_mode: |
da285121 DW |
607 | spectre_v2_enabled = mode; |
608 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
609 | |
610 | /* | |
14623a43 JK |
611 | * If spectre v2 protection has been enabled, unconditionally fill |
612 | * RSB during a context switch; this protects against two independent | |
613 | * issues: | |
c995efd5 | 614 | * |
14623a43 JK |
615 | * - RSB underflow (and switch to BTB) on Skylake+ |
616 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 617 | */ |
14623a43 JK |
618 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
619 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 620 | |
390b99c3 DW |
621 | /* |
622 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
623 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
624 | * speculation around firmware calls only when Enhanced IBRS isn't | |
625 | * supported. | |
626 | * | |
627 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
628 | * the user might select retpoline on the kernel command line and if | |
629 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
630 | * enable IBRS around firmware calls. | |
390b99c3 | 631 | */ |
1044fde9 | 632 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
633 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
634 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
635 | } | |
7011f443 | 636 | |
6cd930f0 TG |
637 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
638 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
639 | } |
640 | ||
984d266f | 641 | static void update_stibp_msr(void * __unused) |
aef0bebc | 642 | { |
984d266f | 643 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
644 | } |
645 | ||
984d266f TG |
646 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
647 | static void update_stibp_strict(void) | |
aef0bebc | 648 | { |
984d266f TG |
649 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
650 | ||
651 | if (sched_smt_active()) | |
652 | mask |= SPEC_CTRL_STIBP; | |
653 | ||
654 | if (mask == x86_spec_ctrl_base) | |
655 | return; | |
656 | ||
657 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
658 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
659 | x86_spec_ctrl_base = mask; | |
660 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
661 | } |
662 | ||
2cdf6a58 TG |
663 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
664 | static void update_indir_branch_cond(void) | |
665 | { | |
666 | if (sched_smt_active()) | |
667 | static_branch_enable(&switch_to_cond_stibp); | |
668 | else | |
669 | static_branch_disable(&switch_to_cond_stibp); | |
670 | } | |
671 | ||
fc5ee888 TG |
672 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
673 | static void update_mds_branch_idle(void) | |
674 | { | |
675 | /* | |
676 | * Enable the idle clearing on CPUs which are affected only by | |
677 | * MDBDS and not any other MDS variant. The other variants cannot | |
678 | * be mitigated when SMT is enabled, so clearing the buffers on | |
679 | * idle would be a window dressing exercise. | |
680 | */ | |
681 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY)) | |
682 | return; | |
683 | ||
684 | if (sched_smt_active()) | |
685 | static_branch_enable(&mds_idle_clear); | |
686 | else | |
687 | static_branch_disable(&mds_idle_clear); | |
688 | } | |
689 | ||
aef0bebc TG |
690 | void arch_smt_update(void) |
691 | { | |
984d266f TG |
692 | /* Enhanced IBRS implies STIBP. No update required. */ |
693 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
694 | return; |
695 | ||
696 | mutex_lock(&spec_ctrl_mutex); | |
697 | ||
984d266f TG |
698 | switch (spectre_v2_user) { |
699 | case SPECTRE_V2_USER_NONE: | |
700 | break; | |
701 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 702 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
703 | update_stibp_strict(); |
704 | break; | |
ac40ad3b | 705 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 706 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 707 | update_indir_branch_cond(); |
ac40ad3b | 708 | break; |
aef0bebc | 709 | } |
984d266f | 710 | |
ebf1e8cb TG |
711 | switch(mds_mitigation) { |
712 | case MDS_MITIGATION_FULL: | |
713 | case MDS_MITIGATION_VMWERV: | |
fc5ee888 | 714 | update_mds_branch_idle(); |
ebf1e8cb TG |
715 | break; |
716 | case MDS_MITIGATION_OFF: | |
717 | break; | |
718 | } | |
fc5ee888 | 719 | |
aef0bebc TG |
720 | mutex_unlock(&spec_ctrl_mutex); |
721 | } | |
722 | ||
e63490c8 KRW |
723 | #undef pr_fmt |
724 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
725 | ||
b5e6d77d | 726 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
727 | |
728 | /* The kernel command line selection */ | |
729 | enum ssb_mitigation_cmd { | |
730 | SPEC_STORE_BYPASS_CMD_NONE, | |
731 | SPEC_STORE_BYPASS_CMD_AUTO, | |
732 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 733 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 734 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
735 | }; |
736 | ||
0eb5928b | 737 | static const char * const ssb_strings[] = { |
e63490c8 | 738 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 739 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
740 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
741 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
742 | }; |
743 | ||
744 | static const struct { | |
745 | const char *option; | |
746 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 747 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
748 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
749 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
750 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
751 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
752 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
753 | }; |
754 | ||
755 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
756 | { | |
757 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
758 | char arg[20]; | |
759 | int ret, i; | |
760 | ||
761 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
762 | return SPEC_STORE_BYPASS_CMD_NONE; | |
763 | } else { | |
764 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
765 | arg, sizeof(arg)); | |
766 | if (ret < 0) | |
767 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
768 | ||
769 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
770 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
771 | continue; | |
772 | ||
773 | cmd = ssb_mitigation_options[i].cmd; | |
774 | break; | |
775 | } | |
776 | ||
777 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
778 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
779 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
780 | } | |
781 | } | |
782 | ||
783 | return cmd; | |
784 | } | |
785 | ||
dbe3009d | 786 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
787 | { |
788 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
789 | enum ssb_mitigation_cmd cmd; | |
790 | ||
8fe36c9d | 791 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
792 | return mode; |
793 | ||
794 | cmd = ssb_parse_cmdline(); | |
795 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
796 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
797 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
798 | return mode; | |
799 | ||
800 | switch (cmd) { | |
801 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
802 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
803 | /* | |
804 | * Choose prctl+seccomp as the default mode if seccomp is | |
805 | * enabled. | |
806 | */ | |
807 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
808 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
809 | else | |
810 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 811 | break; |
e63490c8 KRW |
812 | case SPEC_STORE_BYPASS_CMD_ON: |
813 | mode = SPEC_STORE_BYPASS_DISABLE; | |
814 | break; | |
574dcf89 TG |
815 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
816 | mode = SPEC_STORE_BYPASS_PRCTL; | |
817 | break; | |
e63490c8 KRW |
818 | case SPEC_STORE_BYPASS_CMD_NONE: |
819 | break; | |
820 | } | |
821 | ||
23b9eab9 KRW |
822 | /* |
823 | * We have three CPU feature flags that are in play here: | |
824 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 825 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
826 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
827 | */ | |
574dcf89 | 828 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 829 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 830 | /* |
3b881627 KRW |
831 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
832 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 833 | */ |
5005c716 TL |
834 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
835 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 836 | x86_amd_ssb_disable(); |
5005c716 | 837 | } else { |
8fe36c9d | 838 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 839 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 840 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
841 | } |
842 | } | |
843 | ||
e63490c8 KRW |
844 | return mode; |
845 | } | |
846 | ||
043d480e | 847 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
848 | { |
849 | ssb_mode = __ssb_select_mitigation(); | |
850 | ||
851 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
852 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
853 | } | |
854 | ||
da285121 | 855 | #undef pr_fmt |
c7416003 | 856 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 857 | |
801d6893 | 858 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 859 | { |
801d6893 TG |
860 | /* Force the update of the real TIF bits */ |
861 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
862 | |
863 | /* | |
864 | * Immediately update the speculation control MSRs for the current | |
865 | * task, but for a non-current task delay setting the CPU | |
866 | * mitigation until it is scheduled next. | |
867 | * | |
868 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
869 | * always the current task. | |
870 | */ | |
801d6893 | 871 | if (tsk == current) |
d4595948 TG |
872 | speculation_ctrl_update_current(); |
873 | } | |
874 | ||
875 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
876 | { | |
c7416003 KC |
877 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
878 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
879 | return -ENXIO; |
880 | ||
733f4234 TG |
881 | switch (ctrl) { |
882 | case PR_SPEC_ENABLE: | |
883 | /* If speculation is force disabled, enable is not allowed */ | |
884 | if (task_spec_ssb_force_disable(task)) | |
885 | return -EPERM; | |
886 | task_clear_spec_ssb_disable(task); | |
801d6893 | 887 | task_update_spec_tif(task); |
733f4234 TG |
888 | break; |
889 | case PR_SPEC_DISABLE: | |
890 | task_set_spec_ssb_disable(task); | |
801d6893 | 891 | task_update_spec_tif(task); |
733f4234 TG |
892 | break; |
893 | case PR_SPEC_FORCE_DISABLE: | |
894 | task_set_spec_ssb_disable(task); | |
895 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 896 | task_update_spec_tif(task); |
733f4234 TG |
897 | break; |
898 | default: | |
899 | return -ERANGE; | |
900 | } | |
574dcf89 TG |
901 | return 0; |
902 | } | |
903 | ||
ac40ad3b TG |
904 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
905 | { | |
906 | switch (ctrl) { | |
907 | case PR_SPEC_ENABLE: | |
908 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
909 | return 0; | |
910 | /* | |
911 | * Indirect branch speculation is always disabled in strict | |
912 | * mode. | |
913 | */ | |
fbed8eca TL |
914 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
915 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
916 | return -EPERM; |
917 | task_clear_spec_ib_disable(task); | |
918 | task_update_spec_tif(task); | |
919 | break; | |
920 | case PR_SPEC_DISABLE: | |
921 | case PR_SPEC_FORCE_DISABLE: | |
922 | /* | |
923 | * Indirect branch speculation is always allowed when | |
924 | * mitigation is force disabled. | |
925 | */ | |
926 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
927 | return -EPERM; | |
fbed8eca TL |
928 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
929 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
930 | return 0; |
931 | task_set_spec_ib_disable(task); | |
932 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
933 | task_set_spec_ib_force_disable(task); | |
934 | task_update_spec_tif(task); | |
935 | break; | |
936 | default: | |
937 | return -ERANGE; | |
938 | } | |
939 | return 0; | |
940 | } | |
941 | ||
5b38e244 TG |
942 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
943 | unsigned long ctrl) | |
944 | { | |
945 | switch (which) { | |
946 | case PR_SPEC_STORE_BYPASS: | |
947 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
948 | case PR_SPEC_INDIRECT_BRANCH: |
949 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
950 | default: |
951 | return -ENODEV; | |
952 | } | |
953 | } | |
954 | ||
955 | #ifdef CONFIG_SECCOMP | |
956 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
957 | { | |
c7416003 KC |
958 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
959 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
960 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
961 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
962 | } |
963 | #endif | |
964 | ||
199bfed2 | 965 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
966 | { |
967 | switch (ssb_mode) { | |
968 | case SPEC_STORE_BYPASS_DISABLE: | |
969 | return PR_SPEC_DISABLE; | |
c7416003 | 970 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 971 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
972 | if (task_spec_ssb_force_disable(task)) |
973 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
974 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
975 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
976 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
977 | default: | |
978 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
979 | return PR_SPEC_ENABLE; | |
980 | return PR_SPEC_NOT_AFFECTED; | |
981 | } | |
982 | } | |
983 | ||
ac40ad3b TG |
984 | static int ib_prctl_get(struct task_struct *task) |
985 | { | |
986 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
987 | return PR_SPEC_NOT_AFFECTED; | |
988 | ||
989 | switch (spectre_v2_user) { | |
990 | case SPECTRE_V2_USER_NONE: | |
991 | return PR_SPEC_ENABLE; | |
992 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 993 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
994 | if (task_spec_ib_force_disable(task)) |
995 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
996 | if (task_spec_ib_disable(task)) | |
997 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
998 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
999 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 1000 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
1001 | return PR_SPEC_DISABLE; |
1002 | default: | |
1003 | return PR_SPEC_NOT_AFFECTED; | |
1004 | } | |
1005 | } | |
1006 | ||
199bfed2 | 1007 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
1008 | { |
1009 | switch (which) { | |
1010 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 1011 | return ssb_prctl_get(task); |
ac40ad3b TG |
1012 | case PR_SPEC_INDIRECT_BRANCH: |
1013 | return ib_prctl_get(task); | |
574dcf89 TG |
1014 | default: |
1015 | return -ENODEV; | |
1016 | } | |
1017 | } | |
1018 | ||
23b9eab9 KRW |
1019 | void x86_spec_ctrl_setup_ap(void) |
1020 | { | |
50f9b919 | 1021 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 1022 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
1023 | |
1024 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 1025 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
1026 | } |
1027 | ||
73ca9f47 KRW |
1028 | #undef pr_fmt |
1029 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 1030 | |
24fcb53c JK |
1031 | /* Default mitigation for L1TF-affected CPUs */ |
1032 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 1033 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
1034 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1035 | ||
522c7bed | 1036 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
1037 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
1038 | #endif | |
1039 | ||
f1f016ed AK |
1040 | /* |
1041 | * These CPUs all support 44bits physical address space internally in the | |
1042 | * cache but CPUID can report a smaller number of physical address bits. | |
1043 | * | |
1044 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1045 | * non present PTEs. When the installed memory reaches into the top most | |
1046 | * address bit due to memory holes, which has been observed on machines | |
1047 | * which report 36bits physical address bits and have 32G RAM installed, | |
1048 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1049 | * This is a false positive because the mitigation is still possible due to | |
1050 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1051 | * instead of the reported physical bits and adjust them on the affected | |
1052 | * machines to 44bit if the reported bits are less than 44. | |
1053 | */ | |
1054 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1055 | { | |
1056 | if (c->x86 != 6) | |
1057 | return; | |
1058 | ||
1059 | switch (c->x86_model) { | |
1060 | case INTEL_FAM6_NEHALEM: | |
1061 | case INTEL_FAM6_WESTMERE: | |
1062 | case INTEL_FAM6_SANDYBRIDGE: | |
1063 | case INTEL_FAM6_IVYBRIDGE: | |
1064 | case INTEL_FAM6_HASWELL_CORE: | |
1065 | case INTEL_FAM6_HASWELL_ULT: | |
1066 | case INTEL_FAM6_HASWELL_GT3E: | |
1067 | case INTEL_FAM6_BROADWELL_CORE: | |
1068 | case INTEL_FAM6_BROADWELL_GT3E: | |
1069 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
1070 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
1071 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
1072 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
1073 | if (c->x86_cache_bits < 44) | |
1074 | c->x86_cache_bits = 44; | |
1075 | break; | |
1076 | } | |
1077 | } | |
1078 | ||
73ca9f47 KRW |
1079 | static void __init l1tf_select_mitigation(void) |
1080 | { | |
1081 | u64 half_pa; | |
1082 | ||
1083 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1084 | return; | |
1085 | ||
f1f016ed AK |
1086 | override_cache_bits(&boot_cpu_data); |
1087 | ||
24fcb53c JK |
1088 | switch (l1tf_mitigation) { |
1089 | case L1TF_MITIGATION_OFF: | |
1090 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1091 | case L1TF_MITIGATION_FLUSH: | |
1092 | break; | |
1093 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1094 | case L1TF_MITIGATION_FULL: | |
1095 | cpu_smt_disable(false); | |
1096 | break; | |
1097 | case L1TF_MITIGATION_FULL_FORCE: | |
1098 | cpu_smt_disable(true); | |
1099 | break; | |
1100 | } | |
1101 | ||
73ca9f47 KRW |
1102 | #if CONFIG_PGTABLE_LEVELS == 2 |
1103 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1104 | return; | |
1105 | #endif | |
1106 | ||
73ca9f47 KRW |
1107 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1108 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1109 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
f80e341a VB |
1110 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1111 | half_pa); | |
1112 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
1113 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
73ca9f47 KRW |
1114 | return; |
1115 | } | |
1116 | ||
1117 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1118 | } | |
24fcb53c JK |
1119 | |
1120 | static int __init l1tf_cmdline(char *str) | |
1121 | { | |
1122 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1123 | return 0; | |
1124 | ||
1125 | if (!str) | |
1126 | return -EINVAL; | |
1127 | ||
1128 | if (!strcmp(str, "off")) | |
1129 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1130 | else if (!strcmp(str, "flush,nowarn")) | |
1131 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1132 | else if (!strcmp(str, "flush")) | |
1133 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1134 | else if (!strcmp(str, "flush,nosmt")) | |
1135 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1136 | else if (!strcmp(str, "full")) | |
1137 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1138 | else if (!strcmp(str, "full,force")) | |
1139 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | early_param("l1tf", l1tf_cmdline); | |
1144 | ||
73ca9f47 KRW |
1145 | #undef pr_fmt |
1146 | ||
61dc0f55 | 1147 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1148 | |
b9cfedcd TG |
1149 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1150 | ||
1151 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1152 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1153 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1154 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1155 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1156 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1157 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1158 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1159 | }; |
1160 | ||
1161 | static ssize_t l1tf_show_state(char *buf) | |
1162 | { | |
1163 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1164 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1165 | ||
3899f7b1 PB |
1166 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1167 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1168 | sched_smt_active())) { |
3899f7b1 PB |
1169 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1170 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1171 | } |
3899f7b1 PB |
1172 | |
1173 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1174 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1175 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1176 | } |
1177 | #else | |
1178 | static ssize_t l1tf_show_state(char *buf) | |
1179 | { | |
1180 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1181 | } | |
1182 | #endif | |
1183 | ||
1122cc78 TG |
1184 | static ssize_t mds_show_state(char *buf) |
1185 | { | |
1186 | if (!hypervisor_is_type(X86_HYPER_NATIVE)) { | |
1187 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1188 | mds_strings[mds_mitigation]); | |
1189 | } | |
1190 | ||
1191 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1192 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1193 | sched_smt_active() ? "mitigated" : "disabled"); | |
1194 | } | |
1195 | ||
1196 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1197 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1198 | } | |
1199 | ||
2daa53e8 TC |
1200 | static char *stibp_state(void) |
1201 | { | |
4a8d91c8 TC |
1202 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1203 | return ""; | |
1204 | ||
6cd930f0 TG |
1205 | switch (spectre_v2_user) { |
1206 | case SPECTRE_V2_USER_NONE: | |
1207 | return ", STIBP: disabled"; | |
1208 | case SPECTRE_V2_USER_STRICT: | |
1209 | return ", STIBP: forced"; | |
fbed8eca TL |
1210 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1211 | return ", STIBP: always-on"; | |
ac40ad3b | 1212 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1213 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1214 | if (static_key_enabled(&switch_to_cond_stibp)) |
1215 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1216 | } |
1217 | return ""; | |
2daa53e8 TC |
1218 | } |
1219 | ||
1220 | static char *ibpb_state(void) | |
1221 | { | |
58b2d4c8 | 1222 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1223 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1224 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1225 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1226 | return ", IBPB: conditional"; | |
1227 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1228 | } |
1229 | return ""; | |
2daa53e8 TC |
1230 | } |
1231 | ||
ace051d5 | 1232 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1233 | char *buf, unsigned int bug) |
61dc0f55 | 1234 | { |
d2b8fc2d | 1235 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1236 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1237 | |
1238 | switch (bug) { | |
1239 | case X86_BUG_CPU_MELTDOWN: | |
1240 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1241 | return sprintf(buf, "Mitigation: PTI\n"); | |
1242 | ||
1243 | break; | |
1244 | ||
1245 | case X86_BUG_SPECTRE_V1: | |
1246 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1247 | ||
1248 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1249 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1250 | ibpb_state(), |
d2b8fc2d | 1251 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1252 | stibp_state(), |
5e2fafd5 | 1253 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1254 | spectre_v2_module_string()); |
1255 | ||
e63490c8 KRW |
1256 | case X86_BUG_SPEC_STORE_BYPASS: |
1257 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1258 | ||
05516ad8 AK |
1259 | case X86_BUG_L1TF: |
1260 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1261 | return l1tf_show_state(buf); |
05516ad8 | 1262 | break; |
1122cc78 TG |
1263 | |
1264 | case X86_BUG_MDS: | |
1265 | return mds_show_state(buf); | |
1266 | ||
d2b8fc2d KRW |
1267 | default: |
1268 | break; | |
1269 | } | |
1270 | ||
61dc0f55 TG |
1271 | return sprintf(buf, "Vulnerable\n"); |
1272 | } | |
1273 | ||
d2b8fc2d KRW |
1274 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1275 | { | |
1276 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1277 | } | |
1278 | ||
713f1b95 | 1279 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1280 | { |
d2b8fc2d | 1281 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1282 | } |
1283 | ||
713f1b95 | 1284 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1285 | { |
d2b8fc2d | 1286 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1287 | } |
d7de9182 KRW |
1288 | |
1289 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1290 | { | |
1291 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1292 | } | |
05516ad8 AK |
1293 | |
1294 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1295 | { | |
1296 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1297 | } | |
1122cc78 TG |
1298 | |
1299 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
1300 | { | |
1301 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
1302 | } | |
61dc0f55 | 1303 | #endif |