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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
6cd930f0 TG |
56 | /* Control conditional STIPB in switch_to() */ |
57 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); | |
58b2d4c8 TG |
58 | /* Control conditional IBPB in switch_mm() */ |
59 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
60 | /* Control unconditional IBPB in switch_mm() */ | |
61 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 62 | |
1353ebb4 JF |
63 | void __init check_bugs(void) |
64 | { | |
65 | identify_boot_cpu(); | |
55a36b65 | 66 | |
483ec3c6 TG |
67 | /* |
68 | * identify_boot_cpu() initialized SMT support information, let the | |
69 | * core code know. | |
70 | */ | |
ade31b9e | 71 | cpu_smt_check_topology_early(); |
483ec3c6 | 72 | |
62a67e12 BP |
73 | if (!IS_ENABLED(CONFIG_SMP)) { |
74 | pr_info("CPU: "); | |
75 | print_cpu_info(&boot_cpu_data); | |
76 | } | |
77 | ||
296b454a KRW |
78 | /* |
79 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
80 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
81 | * init code as it is not enumerated and depends on the family. | |
296b454a | 82 | */ |
50f9b919 | 83 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
84 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
85 | ||
e5f984ed TG |
86 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
87 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
88 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
89 | ||
da285121 DW |
90 | /* Select the proper spectre mitigation before patching alternatives */ |
91 | spectre_v2_select_mitigation(); | |
92 | ||
e63490c8 KRW |
93 | /* |
94 | * Select proper mitigation for any exposure to the Speculative Store | |
95 | * Bypass vulnerability. | |
96 | */ | |
97 | ssb_select_mitigation(); | |
98 | ||
05516ad8 AK |
99 | l1tf_select_mitigation(); |
100 | ||
62a67e12 | 101 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
102 | /* |
103 | * Check whether we are able to run this kernel safely on SMP. | |
104 | * | |
105 | * - i386 is no longer supported. | |
106 | * - In order to run on anything without a TSC, we need to be | |
107 | * compiled for a i486. | |
108 | */ | |
109 | if (boot_cpu_data.x86 < 4) | |
110 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
111 | ||
bfe4bb15 MV |
112 | init_utsname()->machine[1] = |
113 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 114 | alternative_instructions(); |
304bceda | 115 | |
4d164092 | 116 | fpu__init_check_bugs(); |
62a67e12 BP |
117 | #else /* CONFIG_X86_64 */ |
118 | alternative_instructions(); | |
119 | ||
120 | /* | |
121 | * Make sure the first 2MB area is not mapped by huge pages | |
122 | * There are typically fixed size MTRRs in there and overlapping | |
123 | * MTRRs into large pages causes slow downs. | |
124 | * | |
125 | * Right now we don't do that with gbpages because there seems | |
126 | * very little benefit for that case. | |
127 | */ | |
128 | if (!direct_gbpages) | |
129 | set_memory_4k((unsigned long)__va(0), 1); | |
130 | #endif | |
1353ebb4 | 131 | } |
61dc0f55 | 132 | |
12376b62 BP |
133 | void |
134 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 135 | { |
e5f984ed | 136 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 137 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 138 | |
50f9b919 | 139 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 140 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
141 | /* |
142 | * Restrict guest_spec_ctrl to supported values. Clear the | |
143 | * modifiable bits in the host base value and or the | |
144 | * modifiable bits from the guest value. | |
145 | */ | |
146 | guestval = hostval & ~x86_spec_ctrl_mask; | |
147 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
148 | ||
12376b62 | 149 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
150 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
151 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 152 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 153 | |
e0b04783 TC |
154 | /* Conditional STIBP enabled? */ |
155 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
156 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
157 | ||
e5f984ed TG |
158 | if (hostval != guestval) { |
159 | msrval = setguest ? guestval : hostval; | |
160 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
161 | } |
162 | } | |
1238ed31 TG |
163 | |
164 | /* | |
165 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
166 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
167 | */ | |
168 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
169 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
170 | return; | |
171 | ||
172 | /* | |
173 | * If the host has SSBD mitigation enabled, force it in the host's | |
174 | * virtual MSR value. If its not permanently enabled, evaluate | |
175 | * current's TIF_SSBD thread flag. | |
176 | */ | |
177 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
178 | hostval = SPEC_CTRL_SSBD; | |
179 | else | |
180 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
181 | ||
182 | /* Sanitize the guest value */ | |
183 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
184 | ||
185 | if (hostval != guestval) { | |
186 | unsigned long tif; | |
187 | ||
188 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
189 | ssbd_spec_ctrl_to_tif(hostval); | |
190 | ||
8fce7184 | 191 | speculation_ctrl_update(tif); |
1238ed31 | 192 | } |
19fff03f | 193 | } |
12376b62 | 194 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 195 | |
8fe36c9d | 196 | static void x86_amd_ssb_disable(void) |
c37b94dd | 197 | { |
8fe36c9d | 198 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 199 | |
65e02bbd TL |
200 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
201 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
202 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
203 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
204 | } | |
205 | ||
aef0bebc TG |
206 | #undef pr_fmt |
207 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
208 | ||
209 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
210 | SPECTRE_V2_NONE; | |
211 | ||
6cd930f0 TG |
212 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
213 | SPECTRE_V2_USER_NONE; | |
214 | ||
d280282b | 215 | #ifdef RETPOLINE |
bb3c2578 TG |
216 | static bool spectre_v2_bad_module; |
217 | ||
d280282b AK |
218 | bool retpoline_module_ok(bool has_retpoline) |
219 | { | |
220 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
221 | return true; | |
222 | ||
c8b8e109 | 223 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
224 | spectre_v2_bad_module = true; |
225 | return false; | |
226 | } | |
bb3c2578 TG |
227 | |
228 | static inline const char *spectre_v2_module_string(void) | |
229 | { | |
230 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
231 | } | |
232 | #else | |
233 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 234 | #endif |
da285121 | 235 | |
da285121 DW |
236 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
237 | { | |
238 | int len = strlen(opt); | |
239 | ||
240 | return len == arglen && !strncmp(arg, opt, len); | |
241 | } | |
242 | ||
aef0bebc TG |
243 | /* The kernel command line selection for spectre v2 */ |
244 | enum spectre_v2_mitigation_cmd { | |
245 | SPECTRE_V2_CMD_NONE, | |
246 | SPECTRE_V2_CMD_AUTO, | |
247 | SPECTRE_V2_CMD_FORCE, | |
248 | SPECTRE_V2_CMD_RETPOLINE, | |
249 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
250 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
251 | }; | |
252 | ||
6cd930f0 TG |
253 | enum spectre_v2_user_cmd { |
254 | SPECTRE_V2_USER_CMD_NONE, | |
255 | SPECTRE_V2_USER_CMD_AUTO, | |
256 | SPECTRE_V2_USER_CMD_FORCE, | |
257 | }; | |
258 | ||
259 | static const char * const spectre_v2_user_strings[] = { | |
260 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", | |
261 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
262 | }; | |
263 | ||
264 | static const struct { | |
265 | const char *option; | |
266 | enum spectre_v2_user_cmd cmd; | |
267 | bool secure; | |
268 | } v2_user_options[] __initdata = { | |
269 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, | |
270 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
271 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
272 | }; | |
273 | ||
274 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
275 | { | |
276 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
277 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
278 | } | |
279 | ||
280 | static enum spectre_v2_user_cmd __init | |
281 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
282 | { | |
283 | char arg[20]; | |
284 | int ret, i; | |
285 | ||
286 | switch (v2_cmd) { | |
287 | case SPECTRE_V2_CMD_NONE: | |
288 | return SPECTRE_V2_USER_CMD_NONE; | |
289 | case SPECTRE_V2_CMD_FORCE: | |
290 | return SPECTRE_V2_USER_CMD_FORCE; | |
291 | default: | |
292 | break; | |
293 | } | |
294 | ||
295 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
296 | arg, sizeof(arg)); | |
297 | if (ret < 0) | |
298 | return SPECTRE_V2_USER_CMD_AUTO; | |
299 | ||
300 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
301 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
302 | spec_v2_user_print_cond(v2_user_options[i].option, | |
303 | v2_user_options[i].secure); | |
304 | return v2_user_options[i].cmd; | |
305 | } | |
306 | } | |
307 | ||
308 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
309 | return SPECTRE_V2_USER_CMD_AUTO; | |
310 | } | |
311 | ||
312 | static void __init | |
313 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
314 | { | |
315 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
316 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
317 | ||
318 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
319 | return; | |
320 | ||
321 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
322 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
323 | smt_possible = false; | |
324 | ||
325 | switch (spectre_v2_parse_user_cmdline(v2_cmd)) { | |
326 | case SPECTRE_V2_USER_CMD_AUTO: | |
327 | case SPECTRE_V2_USER_CMD_NONE: | |
328 | goto set_mode; | |
329 | case SPECTRE_V2_USER_CMD_FORCE: | |
330 | mode = SPECTRE_V2_USER_STRICT; | |
331 | break; | |
332 | } | |
333 | ||
334 | /* Initialize Indirect Branch Prediction Barrier */ | |
335 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
336 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 TG |
337 | |
338 | switch (mode) { | |
339 | case SPECTRE_V2_USER_STRICT: | |
340 | static_branch_enable(&switch_mm_always_ibpb); | |
341 | break; | |
342 | default: | |
343 | break; | |
344 | } | |
345 | ||
346 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
347 | mode == SPECTRE_V2_USER_STRICT ? "always-on" : "conditional"); | |
6cd930f0 TG |
348 | } |
349 | ||
350 | /* If enhanced IBRS is enabled no STIPB required */ | |
351 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
352 | return; | |
353 | ||
354 | set_mode: | |
355 | spectre_v2_user = mode; | |
356 | /* Only print the STIBP mode when SMT possible */ | |
357 | if (smt_possible) | |
358 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
359 | } | |
360 | ||
0eb5928b | 361 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
362 | [SPECTRE_V2_NONE] = "Vulnerable", |
363 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
364 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
365 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
366 | }; | |
367 | ||
17c33e7c KA |
368 | static const struct { |
369 | const char *option; | |
370 | enum spectre_v2_mitigation_cmd cmd; | |
371 | bool secure; | |
5a76cb46 | 372 | } mitigation_options[] __initdata = { |
aef0bebc TG |
373 | { "off", SPECTRE_V2_CMD_NONE, false }, |
374 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
375 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
376 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
377 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
378 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
379 | }; |
380 | ||
10640103 | 381 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 382 | { |
10640103 | 383 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
384 | pr_info("%s selected on command line.\n", reason); |
385 | } | |
386 | ||
da285121 DW |
387 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
388 | { | |
aef0bebc | 389 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 390 | char arg[20]; |
17c33e7c | 391 | int ret, i; |
17c33e7c KA |
392 | |
393 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
394 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 395 | |
4e8e955a TC |
396 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
397 | if (ret < 0) | |
398 | return SPECTRE_V2_CMD_AUTO; | |
399 | ||
400 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
401 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
402 | continue; | |
403 | cmd = mitigation_options[i].cmd; | |
404 | break; | |
405 | } | |
406 | ||
407 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
408 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
409 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
410 | } |
411 | ||
17c33e7c KA |
412 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
413 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
414 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
415 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 416 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 417 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
418 | } |
419 | ||
420 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
421 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
422 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
423 | return SPECTRE_V2_CMD_AUTO; | |
424 | } | |
425 | ||
10640103 TG |
426 | spec_v2_print_cond(mitigation_options[i].option, |
427 | mitigation_options[i].secure); | |
17c33e7c | 428 | return cmd; |
da285121 DW |
429 | } |
430 | ||
431 | static void __init spectre_v2_select_mitigation(void) | |
432 | { | |
433 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
434 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
435 | ||
436 | /* | |
437 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
438 | * then nothing to do. | |
439 | */ | |
440 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
441 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
442 | return; | |
443 | ||
444 | switch (cmd) { | |
445 | case SPECTRE_V2_CMD_NONE: | |
446 | return; | |
447 | ||
448 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 449 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
450 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
451 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
452 | /* Force it so VMEXIT will restore correctly */ | |
453 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
454 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
455 | goto specv2_set_mode; | |
456 | } | |
d0f293e0 DL |
457 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
458 | goto retpoline_auto; | |
459 | break; | |
da285121 DW |
460 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
461 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
462 | goto retpoline_amd; | |
463 | break; | |
464 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
465 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
466 | goto retpoline_generic; | |
467 | break; | |
468 | case SPECTRE_V2_CMD_RETPOLINE: | |
469 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
470 | goto retpoline_auto; | |
471 | break; | |
472 | } | |
713f1b95 | 473 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
474 | return; |
475 | ||
476 | retpoline_auto: | |
477 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
478 | retpoline_amd: | |
479 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 480 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
481 | goto retpoline_generic; |
482 | } | |
51dd01b5 | 483 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
484 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
485 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
486 | } else { | |
487 | retpoline_generic: | |
51dd01b5 | 488 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
489 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
490 | } | |
491 | ||
1044fde9 | 492 | specv2_set_mode: |
da285121 DW |
493 | spectre_v2_enabled = mode; |
494 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
495 | |
496 | /* | |
14623a43 JK |
497 | * If spectre v2 protection has been enabled, unconditionally fill |
498 | * RSB during a context switch; this protects against two independent | |
499 | * issues: | |
c995efd5 | 500 | * |
14623a43 JK |
501 | * - RSB underflow (and switch to BTB) on Skylake+ |
502 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 503 | */ |
14623a43 JK |
504 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
505 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 506 | |
390b99c3 DW |
507 | /* |
508 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
509 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
510 | * speculation around firmware calls only when Enhanced IBRS isn't | |
511 | * supported. | |
512 | * | |
513 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
514 | * the user might select retpoline on the kernel command line and if | |
515 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
516 | * enable IBRS around firmware calls. | |
390b99c3 | 517 | */ |
1044fde9 | 518 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
519 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
520 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
521 | } | |
7011f443 | 522 | |
6cd930f0 TG |
523 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
524 | spectre_v2_user_select_mitigation(cmd); | |
525 | ||
7011f443 JK |
526 | /* Enable STIBP if appropriate */ |
527 | arch_smt_update(); | |
da285121 DW |
528 | } |
529 | ||
984d266f | 530 | static void update_stibp_msr(void * __unused) |
aef0bebc | 531 | { |
984d266f | 532 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
533 | } |
534 | ||
984d266f TG |
535 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
536 | static void update_stibp_strict(void) | |
aef0bebc | 537 | { |
984d266f TG |
538 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
539 | ||
540 | if (sched_smt_active()) | |
541 | mask |= SPEC_CTRL_STIBP; | |
542 | ||
543 | if (mask == x86_spec_ctrl_base) | |
544 | return; | |
545 | ||
546 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
547 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
548 | x86_spec_ctrl_base = mask; | |
549 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
550 | } |
551 | ||
552 | void arch_smt_update(void) | |
553 | { | |
984d266f TG |
554 | /* Enhanced IBRS implies STIBP. No update required. */ |
555 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
556 | return; |
557 | ||
558 | mutex_lock(&spec_ctrl_mutex); | |
559 | ||
984d266f TG |
560 | switch (spectre_v2_user) { |
561 | case SPECTRE_V2_USER_NONE: | |
562 | break; | |
563 | case SPECTRE_V2_USER_STRICT: | |
564 | update_stibp_strict(); | |
565 | break; | |
ac40ad3b TG |
566 | case SPECTRE_V2_USER_PRCTL: |
567 | break; | |
aef0bebc | 568 | } |
984d266f | 569 | |
aef0bebc TG |
570 | mutex_unlock(&spec_ctrl_mutex); |
571 | } | |
572 | ||
e63490c8 KRW |
573 | #undef pr_fmt |
574 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
575 | ||
b5e6d77d | 576 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
577 | |
578 | /* The kernel command line selection */ | |
579 | enum ssb_mitigation_cmd { | |
580 | SPEC_STORE_BYPASS_CMD_NONE, | |
581 | SPEC_STORE_BYPASS_CMD_AUTO, | |
582 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 583 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 584 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
585 | }; |
586 | ||
0eb5928b | 587 | static const char * const ssb_strings[] = { |
e63490c8 | 588 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 589 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
590 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
591 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
592 | }; |
593 | ||
594 | static const struct { | |
595 | const char *option; | |
596 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 597 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
598 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
599 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
600 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
601 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
602 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
603 | }; |
604 | ||
605 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
606 | { | |
607 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
608 | char arg[20]; | |
609 | int ret, i; | |
610 | ||
611 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
612 | return SPEC_STORE_BYPASS_CMD_NONE; | |
613 | } else { | |
614 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
615 | arg, sizeof(arg)); | |
616 | if (ret < 0) | |
617 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
618 | ||
619 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
620 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
621 | continue; | |
622 | ||
623 | cmd = ssb_mitigation_options[i].cmd; | |
624 | break; | |
625 | } | |
626 | ||
627 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
628 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
629 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
630 | } | |
631 | } | |
632 | ||
633 | return cmd; | |
634 | } | |
635 | ||
dbe3009d | 636 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
637 | { |
638 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
639 | enum ssb_mitigation_cmd cmd; | |
640 | ||
8fe36c9d | 641 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
642 | return mode; |
643 | ||
644 | cmd = ssb_parse_cmdline(); | |
645 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
646 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
647 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
648 | return mode; | |
649 | ||
650 | switch (cmd) { | |
651 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
652 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
653 | /* | |
654 | * Choose prctl+seccomp as the default mode if seccomp is | |
655 | * enabled. | |
656 | */ | |
657 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
658 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
659 | else | |
660 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 661 | break; |
e63490c8 KRW |
662 | case SPEC_STORE_BYPASS_CMD_ON: |
663 | mode = SPEC_STORE_BYPASS_DISABLE; | |
664 | break; | |
574dcf89 TG |
665 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
666 | mode = SPEC_STORE_BYPASS_PRCTL; | |
667 | break; | |
e63490c8 KRW |
668 | case SPEC_STORE_BYPASS_CMD_NONE: |
669 | break; | |
670 | } | |
671 | ||
23b9eab9 KRW |
672 | /* |
673 | * We have three CPU feature flags that are in play here: | |
674 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 675 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
676 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
677 | */ | |
574dcf89 | 678 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 679 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 680 | /* |
3b881627 KRW |
681 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
682 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 683 | */ |
5005c716 TL |
684 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
685 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 686 | x86_amd_ssb_disable(); |
5005c716 | 687 | } else { |
8fe36c9d | 688 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 689 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 690 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
691 | } |
692 | } | |
693 | ||
e63490c8 KRW |
694 | return mode; |
695 | } | |
696 | ||
043d480e | 697 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
698 | { |
699 | ssb_mode = __ssb_select_mitigation(); | |
700 | ||
701 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
702 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
703 | } | |
704 | ||
da285121 | 705 | #undef pr_fmt |
c7416003 | 706 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 707 | |
801d6893 | 708 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 709 | { |
801d6893 TG |
710 | /* Force the update of the real TIF bits */ |
711 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
712 | |
713 | /* | |
714 | * Immediately update the speculation control MSRs for the current | |
715 | * task, but for a non-current task delay setting the CPU | |
716 | * mitigation until it is scheduled next. | |
717 | * | |
718 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
719 | * always the current task. | |
720 | */ | |
801d6893 | 721 | if (tsk == current) |
d4595948 TG |
722 | speculation_ctrl_update_current(); |
723 | } | |
724 | ||
725 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
726 | { | |
c7416003 KC |
727 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
728 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
729 | return -ENXIO; |
730 | ||
733f4234 TG |
731 | switch (ctrl) { |
732 | case PR_SPEC_ENABLE: | |
733 | /* If speculation is force disabled, enable is not allowed */ | |
734 | if (task_spec_ssb_force_disable(task)) | |
735 | return -EPERM; | |
736 | task_clear_spec_ssb_disable(task); | |
801d6893 | 737 | task_update_spec_tif(task); |
733f4234 TG |
738 | break; |
739 | case PR_SPEC_DISABLE: | |
740 | task_set_spec_ssb_disable(task); | |
801d6893 | 741 | task_update_spec_tif(task); |
733f4234 TG |
742 | break; |
743 | case PR_SPEC_FORCE_DISABLE: | |
744 | task_set_spec_ssb_disable(task); | |
745 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 746 | task_update_spec_tif(task); |
733f4234 TG |
747 | break; |
748 | default: | |
749 | return -ERANGE; | |
750 | } | |
574dcf89 TG |
751 | return 0; |
752 | } | |
753 | ||
ac40ad3b TG |
754 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
755 | { | |
756 | switch (ctrl) { | |
757 | case PR_SPEC_ENABLE: | |
758 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
759 | return 0; | |
760 | /* | |
761 | * Indirect branch speculation is always disabled in strict | |
762 | * mode. | |
763 | */ | |
764 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
765 | return -EPERM; | |
766 | task_clear_spec_ib_disable(task); | |
767 | task_update_spec_tif(task); | |
768 | break; | |
769 | case PR_SPEC_DISABLE: | |
770 | case PR_SPEC_FORCE_DISABLE: | |
771 | /* | |
772 | * Indirect branch speculation is always allowed when | |
773 | * mitigation is force disabled. | |
774 | */ | |
775 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
776 | return -EPERM; | |
777 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
778 | return 0; | |
779 | task_set_spec_ib_disable(task); | |
780 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
781 | task_set_spec_ib_force_disable(task); | |
782 | task_update_spec_tif(task); | |
783 | break; | |
784 | default: | |
785 | return -ERANGE; | |
786 | } | |
787 | return 0; | |
788 | } | |
789 | ||
5b38e244 TG |
790 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
791 | unsigned long ctrl) | |
792 | { | |
793 | switch (which) { | |
794 | case PR_SPEC_STORE_BYPASS: | |
795 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
796 | case PR_SPEC_INDIRECT_BRANCH: |
797 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
798 | default: |
799 | return -ENODEV; | |
800 | } | |
801 | } | |
802 | ||
803 | #ifdef CONFIG_SECCOMP | |
804 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
805 | { | |
c7416003 KC |
806 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
807 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
808 | } |
809 | #endif | |
810 | ||
199bfed2 | 811 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
812 | { |
813 | switch (ssb_mode) { | |
814 | case SPEC_STORE_BYPASS_DISABLE: | |
815 | return PR_SPEC_DISABLE; | |
c7416003 | 816 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 817 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
818 | if (task_spec_ssb_force_disable(task)) |
819 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
820 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
821 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
822 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
823 | default: | |
824 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
825 | return PR_SPEC_ENABLE; | |
826 | return PR_SPEC_NOT_AFFECTED; | |
827 | } | |
828 | } | |
829 | ||
ac40ad3b TG |
830 | static int ib_prctl_get(struct task_struct *task) |
831 | { | |
832 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
833 | return PR_SPEC_NOT_AFFECTED; | |
834 | ||
835 | switch (spectre_v2_user) { | |
836 | case SPECTRE_V2_USER_NONE: | |
837 | return PR_SPEC_ENABLE; | |
838 | case SPECTRE_V2_USER_PRCTL: | |
839 | if (task_spec_ib_force_disable(task)) | |
840 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
841 | if (task_spec_ib_disable(task)) | |
842 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
843 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
844 | case SPECTRE_V2_USER_STRICT: | |
845 | return PR_SPEC_DISABLE; | |
846 | default: | |
847 | return PR_SPEC_NOT_AFFECTED; | |
848 | } | |
849 | } | |
850 | ||
199bfed2 | 851 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
852 | { |
853 | switch (which) { | |
854 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 855 | return ssb_prctl_get(task); |
ac40ad3b TG |
856 | case PR_SPEC_INDIRECT_BRANCH: |
857 | return ib_prctl_get(task); | |
574dcf89 TG |
858 | default: |
859 | return -ENODEV; | |
860 | } | |
861 | } | |
862 | ||
23b9eab9 KRW |
863 | void x86_spec_ctrl_setup_ap(void) |
864 | { | |
50f9b919 | 865 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 866 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
867 | |
868 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 869 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
870 | } |
871 | ||
73ca9f47 KRW |
872 | #undef pr_fmt |
873 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 874 | |
24fcb53c JK |
875 | /* Default mitigation for L1TF-affected CPUs */ |
876 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 877 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
878 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
879 | ||
522c7bed | 880 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
881 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
882 | #endif | |
883 | ||
f1f016ed AK |
884 | /* |
885 | * These CPUs all support 44bits physical address space internally in the | |
886 | * cache but CPUID can report a smaller number of physical address bits. | |
887 | * | |
888 | * The L1TF mitigation uses the top most address bit for the inversion of | |
889 | * non present PTEs. When the installed memory reaches into the top most | |
890 | * address bit due to memory holes, which has been observed on machines | |
891 | * which report 36bits physical address bits and have 32G RAM installed, | |
892 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
893 | * This is a false positive because the mitigation is still possible due to | |
894 | * the fact that the cache uses 44bit internally. Use the cache bits | |
895 | * instead of the reported physical bits and adjust them on the affected | |
896 | * machines to 44bit if the reported bits are less than 44. | |
897 | */ | |
898 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
899 | { | |
900 | if (c->x86 != 6) | |
901 | return; | |
902 | ||
903 | switch (c->x86_model) { | |
904 | case INTEL_FAM6_NEHALEM: | |
905 | case INTEL_FAM6_WESTMERE: | |
906 | case INTEL_FAM6_SANDYBRIDGE: | |
907 | case INTEL_FAM6_IVYBRIDGE: | |
908 | case INTEL_FAM6_HASWELL_CORE: | |
909 | case INTEL_FAM6_HASWELL_ULT: | |
910 | case INTEL_FAM6_HASWELL_GT3E: | |
911 | case INTEL_FAM6_BROADWELL_CORE: | |
912 | case INTEL_FAM6_BROADWELL_GT3E: | |
913 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
914 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
915 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
916 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
917 | if (c->x86_cache_bits < 44) | |
918 | c->x86_cache_bits = 44; | |
919 | break; | |
920 | } | |
921 | } | |
922 | ||
73ca9f47 KRW |
923 | static void __init l1tf_select_mitigation(void) |
924 | { | |
925 | u64 half_pa; | |
926 | ||
927 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
928 | return; | |
929 | ||
f1f016ed AK |
930 | override_cache_bits(&boot_cpu_data); |
931 | ||
24fcb53c JK |
932 | switch (l1tf_mitigation) { |
933 | case L1TF_MITIGATION_OFF: | |
934 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
935 | case L1TF_MITIGATION_FLUSH: | |
936 | break; | |
937 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
938 | case L1TF_MITIGATION_FULL: | |
939 | cpu_smt_disable(false); | |
940 | break; | |
941 | case L1TF_MITIGATION_FULL_FORCE: | |
942 | cpu_smt_disable(true); | |
943 | break; | |
944 | } | |
945 | ||
73ca9f47 KRW |
946 | #if CONFIG_PGTABLE_LEVELS == 2 |
947 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
948 | return; | |
949 | #endif | |
950 | ||
73ca9f47 KRW |
951 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
952 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
953 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
954 | return; | |
955 | } | |
956 | ||
957 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
958 | } | |
24fcb53c JK |
959 | |
960 | static int __init l1tf_cmdline(char *str) | |
961 | { | |
962 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
963 | return 0; | |
964 | ||
965 | if (!str) | |
966 | return -EINVAL; | |
967 | ||
968 | if (!strcmp(str, "off")) | |
969 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
970 | else if (!strcmp(str, "flush,nowarn")) | |
971 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
972 | else if (!strcmp(str, "flush")) | |
973 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
974 | else if (!strcmp(str, "flush,nosmt")) | |
975 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
976 | else if (!strcmp(str, "full")) | |
977 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
978 | else if (!strcmp(str, "full,force")) | |
979 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
980 | ||
981 | return 0; | |
982 | } | |
983 | early_param("l1tf", l1tf_cmdline); | |
984 | ||
73ca9f47 KRW |
985 | #undef pr_fmt |
986 | ||
61dc0f55 | 987 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 988 | |
b9cfedcd TG |
989 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
990 | ||
991 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 992 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
993 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
994 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
995 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
996 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
997 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 998 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
999 | }; |
1000 | ||
1001 | static ssize_t l1tf_show_state(char *buf) | |
1002 | { | |
1003 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1004 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1005 | ||
3899f7b1 PB |
1006 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1007 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1008 | sched_smt_active())) { |
3899f7b1 PB |
1009 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1010 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1011 | } |
3899f7b1 PB |
1012 | |
1013 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1014 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1015 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1016 | } |
1017 | #else | |
1018 | static ssize_t l1tf_show_state(char *buf) | |
1019 | { | |
1020 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1021 | } | |
1022 | #endif | |
1023 | ||
2daa53e8 TC |
1024 | static char *stibp_state(void) |
1025 | { | |
4a8d91c8 TC |
1026 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1027 | return ""; | |
1028 | ||
6cd930f0 TG |
1029 | switch (spectre_v2_user) { |
1030 | case SPECTRE_V2_USER_NONE: | |
1031 | return ", STIBP: disabled"; | |
1032 | case SPECTRE_V2_USER_STRICT: | |
1033 | return ", STIBP: forced"; | |
ac40ad3b TG |
1034 | case SPECTRE_V2_USER_PRCTL: |
1035 | return ""; | |
6cd930f0 TG |
1036 | } |
1037 | return ""; | |
2daa53e8 TC |
1038 | } |
1039 | ||
1040 | static char *ibpb_state(void) | |
1041 | { | |
58b2d4c8 TG |
1042 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
1043 | switch (spectre_v2_user) { | |
1044 | case SPECTRE_V2_USER_NONE: | |
1045 | return ", IBPB: disabled"; | |
1046 | case SPECTRE_V2_USER_STRICT: | |
1047 | return ", IBPB: always-on"; | |
ac40ad3b TG |
1048 | case SPECTRE_V2_USER_PRCTL: |
1049 | return ""; | |
58b2d4c8 TG |
1050 | } |
1051 | } | |
1052 | return ""; | |
2daa53e8 TC |
1053 | } |
1054 | ||
ace051d5 | 1055 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1056 | char *buf, unsigned int bug) |
61dc0f55 | 1057 | { |
d2b8fc2d | 1058 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1059 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1060 | |
1061 | switch (bug) { | |
1062 | case X86_BUG_CPU_MELTDOWN: | |
1063 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1064 | return sprintf(buf, "Mitigation: PTI\n"); | |
1065 | ||
1066 | break; | |
1067 | ||
1068 | case X86_BUG_SPECTRE_V1: | |
1069 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1070 | ||
1071 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1072 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1073 | ibpb_state(), |
d2b8fc2d | 1074 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1075 | stibp_state(), |
5e2fafd5 | 1076 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1077 | spectre_v2_module_string()); |
1078 | ||
e63490c8 KRW |
1079 | case X86_BUG_SPEC_STORE_BYPASS: |
1080 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1081 | ||
05516ad8 AK |
1082 | case X86_BUG_L1TF: |
1083 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1084 | return l1tf_show_state(buf); |
05516ad8 | 1085 | break; |
d2b8fc2d KRW |
1086 | default: |
1087 | break; | |
1088 | } | |
1089 | ||
61dc0f55 TG |
1090 | return sprintf(buf, "Vulnerable\n"); |
1091 | } | |
1092 | ||
d2b8fc2d KRW |
1093 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1094 | { | |
1095 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1096 | } | |
1097 | ||
713f1b95 | 1098 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1099 | { |
d2b8fc2d | 1100 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1101 | } |
1102 | ||
713f1b95 | 1103 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1104 | { |
d2b8fc2d | 1105 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1106 | } |
d7de9182 KRW |
1107 | |
1108 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1109 | { | |
1110 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1111 | } | |
05516ad8 AK |
1112 | |
1113 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1114 | { | |
1115 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1116 | } | |
61dc0f55 | 1117 | #endif |