]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/scsi/cxlflash/main.c
scsi: cxlflash: Remove zeroing of private command data
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / cxlflash / main.c
CommitLineData
c21e0bbf
MO
1/*
2 * CXL Flash Device Driver
3 *
4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 *
7 * Copyright (C) 2015 IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/delay.h>
16#include <linux/list.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19
20#include <asm/unaligned.h>
21
22#include <misc/cxl.h>
23
24#include <scsi/scsi_cmnd.h>
25#include <scsi/scsi_host.h>
65be2c79 26#include <uapi/scsi/cxlflash_ioctl.h>
c21e0bbf
MO
27
28#include "main.h"
29#include "sislite.h"
30#include "common.h"
31
32MODULE_DESCRIPTION(CXLFLASH_ADAPTER_NAME);
33MODULE_AUTHOR("Manoj N. Kumar <manoj@linux.vnet.ibm.com>");
34MODULE_AUTHOR("Matthew R. Ochs <mrochs@linux.vnet.ibm.com>");
35MODULE_LICENSE("GPL");
36
f3d79b3e
UK
37static struct class *cxlflash_class;
38static u32 cxlflash_major;
39static DECLARE_BITMAP(cxlflash_minor, CXLFLASH_MAX_ADAPTERS);
40
c21e0bbf
MO
41/**
42 * process_cmd_err() - command error handler
43 * @cmd: AFU command that experienced the error.
44 * @scp: SCSI command associated with the AFU command in error.
45 *
46 * Translates error bits from AFU command to SCSI command results.
47 */
48static void process_cmd_err(struct afu_cmd *cmd, struct scsi_cmnd *scp)
49{
88d33628
MO
50 struct afu *afu = cmd->parent;
51 struct cxlflash_cfg *cfg = afu->parent;
52 struct device *dev = &cfg->dev->dev;
c21e0bbf
MO
53 struct sisl_ioarcb *ioarcb;
54 struct sisl_ioasa *ioasa;
8396012f 55 u32 resid;
c21e0bbf
MO
56
57 if (unlikely(!cmd))
58 return;
59
60 ioarcb = &(cmd->rcb);
61 ioasa = &(cmd->sa);
62
63 if (ioasa->rc.flags & SISL_RC_FLAGS_UNDERRUN) {
8396012f
MO
64 resid = ioasa->resid;
65 scsi_set_resid(scp, resid);
88d33628
MO
66 dev_dbg(dev, "%s: cmd underrun cmd = %p scp = %p, resid = %d\n",
67 __func__, cmd, scp, resid);
c21e0bbf
MO
68 }
69
70 if (ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN) {
88d33628
MO
71 dev_dbg(dev, "%s: cmd underrun cmd = %p scp = %p\n",
72 __func__, cmd, scp);
c21e0bbf
MO
73 scp->result = (DID_ERROR << 16);
74 }
75
88d33628
MO
76 dev_dbg(dev, "%s: cmd failed afu_rc=%02x scsi_rc=%02x fc_rc=%02x "
77 "afu_extra=%02x scsi_extra=%02x fc_extra=%02x\n", __func__,
78 ioasa->rc.afu_rc, ioasa->rc.scsi_rc, ioasa->rc.fc_rc,
79 ioasa->afu_extra, ioasa->scsi_extra, ioasa->fc_extra);
c21e0bbf
MO
80
81 if (ioasa->rc.scsi_rc) {
82 /* We have a SCSI status */
83 if (ioasa->rc.flags & SISL_RC_FLAGS_SENSE_VALID) {
84 memcpy(scp->sense_buffer, ioasa->sense_data,
85 SISL_SENSE_DATA_LEN);
86 scp->result = ioasa->rc.scsi_rc;
87 } else
88 scp->result = ioasa->rc.scsi_rc | (DID_ERROR << 16);
89 }
90
91 /*
92 * We encountered an error. Set scp->result based on nature
93 * of error.
94 */
95 if (ioasa->rc.fc_rc) {
96 /* We have an FC status */
97 switch (ioasa->rc.fc_rc) {
98 case SISL_FC_RC_LINKDOWN:
99 scp->result = (DID_REQUEUE << 16);
100 break;
101 case SISL_FC_RC_RESID:
102 /* This indicates an FCP resid underrun */
103 if (!(ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN)) {
104 /* If the SISL_RC_FLAGS_OVERRUN flag was set,
105 * then we will handle this error else where.
106 * If not then we must handle it here.
8396012f 107 * This is probably an AFU bug.
c21e0bbf
MO
108 */
109 scp->result = (DID_ERROR << 16);
110 }
111 break;
112 case SISL_FC_RC_RESIDERR:
113 /* Resid mismatch between adapter and device */
114 case SISL_FC_RC_TGTABORT:
115 case SISL_FC_RC_ABORTOK:
116 case SISL_FC_RC_ABORTFAIL:
117 case SISL_FC_RC_NOLOGI:
118 case SISL_FC_RC_ABORTPEND:
119 case SISL_FC_RC_WRABORTPEND:
120 case SISL_FC_RC_NOEXP:
121 case SISL_FC_RC_INUSE:
122 scp->result = (DID_ERROR << 16);
123 break;
124 }
125 }
126
127 if (ioasa->rc.afu_rc) {
128 /* We have an AFU error */
129 switch (ioasa->rc.afu_rc) {
130 case SISL_AFU_RC_NO_CHANNELS:
8396012f 131 scp->result = (DID_NO_CONNECT << 16);
c21e0bbf
MO
132 break;
133 case SISL_AFU_RC_DATA_DMA_ERR:
134 switch (ioasa->afu_extra) {
135 case SISL_AFU_DMA_ERR_PAGE_IN:
136 /* Retry */
137 scp->result = (DID_IMM_RETRY << 16);
138 break;
139 case SISL_AFU_DMA_ERR_INVALID_EA:
140 default:
141 scp->result = (DID_ERROR << 16);
142 }
143 break;
144 case SISL_AFU_RC_OUT_OF_DATA_BUFS:
145 /* Retry */
146 scp->result = (DID_ALLOC_FAILURE << 16);
147 break;
148 default:
149 scp->result = (DID_ERROR << 16);
150 }
151 }
152}
153
154/**
155 * cmd_complete() - command completion handler
156 * @cmd: AFU command that has completed.
157 *
158 * Prepares and submits command that has either completed or timed out to
159 * the SCSI stack. Checks AFU command back into command pool for non-internal
fe7f9698 160 * (cmd->scp populated) commands.
c21e0bbf
MO
161 */
162static void cmd_complete(struct afu_cmd *cmd)
163{
164 struct scsi_cmnd *scp;
c21e0bbf
MO
165 ulong lock_flags;
166 struct afu *afu = cmd->parent;
167 struct cxlflash_cfg *cfg = afu->parent;
88d33628 168 struct device *dev = &cfg->dev->dev;
d732d14f 169 struct hwq *hwq = get_hwq(afu, cmd->hwq_index);
c21e0bbf
MO
170 bool cmd_is_tmf;
171
d732d14f
UK
172 spin_lock_irqsave(&hwq->hsq_slock, lock_flags);
173 list_del(&cmd->list);
174 spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags);
175
fe7f9698
MO
176 if (cmd->scp) {
177 scp = cmd->scp;
8396012f 178 if (unlikely(cmd->sa.ioasc))
c21e0bbf
MO
179 process_cmd_err(cmd, scp);
180 else
181 scp->result = (DID_OK << 16);
182
c21e0bbf 183 cmd_is_tmf = cmd->cmd_tmf;
c21e0bbf 184
88d33628
MO
185 dev_dbg_ratelimited(dev, "%s:scp=%p result=%08x ioasc=%08x\n",
186 __func__, scp, scp->result, cmd->sa.ioasc);
c21e0bbf 187
c21e0bbf
MO
188 scp->scsi_done(scp);
189
190 if (cmd_is_tmf) {
018d1dc9 191 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
c21e0bbf
MO
192 cfg->tmf_active = false;
193 wake_up_all_locked(&cfg->tmf_waitq);
018d1dc9 194 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf
MO
195 }
196 } else
197 complete(&cmd->cevent);
198}
199
2450a5e3
UK
200/**
201 * flush_pending_cmds() - flush all pending commands on this hardware queue
202 * @hwq: Hardware queue to flush.
203 *
204 * The hardware send queue lock associated with this hardware queue must be
205 * held when calling this routine.
206 */
207static void flush_pending_cmds(struct hwq *hwq)
208{
209 struct afu_cmd *cmd, *tmp;
210 struct scsi_cmnd *scp;
211
212 list_for_each_entry_safe(cmd, tmp, &hwq->pending_cmds, list) {
213 /* Bypass command when on a doneq, cmd_complete() will handle */
214 if (!list_empty(&cmd->queue))
215 continue;
216
217 list_del(&cmd->list);
218
219 if (cmd->scp) {
220 scp = cmd->scp;
221 scp->result = (DID_IMM_RETRY << 16);
222 scp->scsi_done(scp);
223 } else {
224 cmd->cmd_aborted = true;
225 complete(&cmd->cevent);
226 }
227 }
228}
229
15305514 230/**
ddc869e9
UK
231 * context_reset() - reset context via specified register
232 * @hwq: Hardware queue owning the context to be reset.
74579cfb 233 * @reset_reg: MMIO register to perform reset.
ddc869e9 234 *
4ab47257
UK
235 * When the reset is successful, the SISLite specification guarantees that
236 * the AFU has aborted all currently pending I/O. Accordingly, these commands
237 * must be flushed.
238 *
ddc869e9 239 * Return: 0 on success, -errno on failure
15305514 240 */
ddc869e9 241static int context_reset(struct hwq *hwq, __be64 __iomem *reset_reg)
15305514 242{
ddc869e9 243 struct cxlflash_cfg *cfg = hwq->afu->parent;
3d2f617d 244 struct device *dev = &cfg->dev->dev;
ddc869e9
UK
245 int rc = -ETIMEDOUT;
246 int nretry = 0;
247 u64 val = 0x1;
4ab47257 248 ulong lock_flags;
15305514 249
ddc869e9 250 dev_dbg(dev, "%s: hwq=%p\n", __func__, hwq);
15305514 251
4ab47257
UK
252 spin_lock_irqsave(&hwq->hsq_slock, lock_flags);
253
ddc869e9 254 writeq_be(val, reset_reg);
15305514 255 do {
ddc869e9
UK
256 val = readq_be(reset_reg);
257 if ((val & 0x1) == 0x0) {
258 rc = 0;
15305514 259 break;
ddc869e9
UK
260 }
261
15305514 262 /* Double delay each time */
ea765431 263 udelay(1 << nretry);
15305514 264 } while (nretry++ < MC_ROOM_RETRY_CNT);
3d2f617d 265
4ab47257
UK
266 if (!rc)
267 flush_pending_cmds(hwq);
268
269 spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags);
270
ddc869e9
UK
271 dev_dbg(dev, "%s: returning rc=%d, val=%016llx nretry=%d\n",
272 __func__, rc, val, nretry);
273 return rc;
15305514
MO
274}
275
74579cfb 276/**
ddc869e9
UK
277 * context_reset_ioarrin() - reset context via IOARRIN register
278 * @hwq: Hardware queue owning the context to be reset.
279 *
280 * Return: 0 on success, -errno on failure
74579cfb 281 */
ddc869e9 282static int context_reset_ioarrin(struct hwq *hwq)
74579cfb 283{
ddc869e9 284 return context_reset(hwq, &hwq->host_map->ioarrin);
74579cfb
MO
285}
286
bae0ac69 287/**
ddc869e9
UK
288 * context_reset_sq() - reset context via SQ_CONTEXT_RESET register
289 * @hwq: Hardware queue owning the context to be reset.
290 *
291 * Return: 0 on success, -errno on failure
bae0ac69 292 */
ddc869e9 293static int context_reset_sq(struct hwq *hwq)
bae0ac69 294{
ddc869e9 295 return context_reset(hwq, &hwq->host_map->sq_ctx_reset);
bae0ac69
MO
296}
297
15305514 298/**
48b4be36 299 * send_cmd_ioarrin() - sends an AFU command via IOARRIN register
15305514
MO
300 * @afu: AFU associated with the host.
301 * @cmd: AFU command to send.
302 *
303 * Return:
1284fb0c 304 * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure
15305514 305 */
48b4be36 306static int send_cmd_ioarrin(struct afu *afu, struct afu_cmd *cmd)
15305514
MO
307{
308 struct cxlflash_cfg *cfg = afu->parent;
309 struct device *dev = &cfg->dev->dev;
a583d00a 310 struct hwq *hwq = get_hwq(afu, cmd->hwq_index);
15305514 311 int rc = 0;
11f7b184
UK
312 s64 room;
313 ulong lock_flags;
15305514
MO
314
315 /*
11f7b184
UK
316 * To avoid the performance penalty of MMIO, spread the update of
317 * 'room' over multiple commands.
15305514 318 */
edc034e8 319 spin_lock_irqsave(&hwq->hsq_slock, lock_flags);
a583d00a
UK
320 if (--hwq->room < 0) {
321 room = readq_be(&hwq->host_map->cmd_room);
11f7b184
UK
322 if (room <= 0) {
323 dev_dbg_ratelimited(dev, "%s: no cmd_room to send "
324 "0x%02X, room=0x%016llX\n",
325 __func__, cmd->rcb.cdb[0], room);
a583d00a 326 hwq->room = 0;
11f7b184
UK
327 rc = SCSI_MLQUEUE_HOST_BUSY;
328 goto out;
15305514 329 }
a583d00a 330 hwq->room = room - 1;
15305514
MO
331 }
332
d732d14f 333 list_add(&cmd->list, &hwq->pending_cmds);
a583d00a 334 writeq_be((u64)&cmd->rcb, &hwq->host_map->ioarrin);
15305514 335out:
edc034e8 336 spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags);
88d33628
MO
337 dev_dbg(dev, "%s: cmd=%p len=%u ea=%016llx rc=%d\n", __func__,
338 cmd, cmd->rcb.data_len, cmd->rcb.data_ea, rc);
15305514 339 return rc;
15305514
MO
340}
341
bae0ac69
MO
342/**
343 * send_cmd_sq() - sends an AFU command via SQ ring
344 * @afu: AFU associated with the host.
345 * @cmd: AFU command to send.
346 *
347 * Return:
348 * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure
349 */
350static int send_cmd_sq(struct afu *afu, struct afu_cmd *cmd)
351{
352 struct cxlflash_cfg *cfg = afu->parent;
353 struct device *dev = &cfg->dev->dev;
a583d00a 354 struct hwq *hwq = get_hwq(afu, cmd->hwq_index);
bae0ac69
MO
355 int rc = 0;
356 int newval;
357 ulong lock_flags;
358
a583d00a 359 newval = atomic_dec_if_positive(&hwq->hsq_credits);
bae0ac69
MO
360 if (newval <= 0) {
361 rc = SCSI_MLQUEUE_HOST_BUSY;
362 goto out;
363 }
364
365 cmd->rcb.ioasa = &cmd->sa;
366
a583d00a 367 spin_lock_irqsave(&hwq->hsq_slock, lock_flags);
bae0ac69 368
a583d00a
UK
369 *hwq->hsq_curr = cmd->rcb;
370 if (hwq->hsq_curr < hwq->hsq_end)
371 hwq->hsq_curr++;
bae0ac69 372 else
a583d00a 373 hwq->hsq_curr = hwq->hsq_start;
d732d14f
UK
374
375 list_add(&cmd->list, &hwq->pending_cmds);
a583d00a 376 writeq_be((u64)hwq->hsq_curr, &hwq->host_map->sq_tail);
bae0ac69 377
a583d00a 378 spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags);
bae0ac69 379out:
88d33628
MO
380 dev_dbg(dev, "%s: cmd=%p len=%u ea=%016llx ioasa=%p rc=%d curr=%p "
381 "head=%016llx tail=%016llx\n", __func__, cmd, cmd->rcb.data_len,
a583d00a
UK
382 cmd->rcb.data_ea, cmd->rcb.ioasa, rc, hwq->hsq_curr,
383 readq_be(&hwq->host_map->sq_head),
384 readq_be(&hwq->host_map->sq_tail));
bae0ac69
MO
385 return rc;
386}
387
15305514
MO
388/**
389 * wait_resp() - polls for a response or timeout to a sent AFU command
390 * @afu: AFU associated with the host.
391 * @cmd: AFU command that was sent.
9ba848ac 392 *
ddc869e9 393 * Return: 0 on success, -errno on failure
15305514 394 */
9ba848ac 395static int wait_resp(struct afu *afu, struct afu_cmd *cmd)
15305514 396{
88d33628
MO
397 struct cxlflash_cfg *cfg = afu->parent;
398 struct device *dev = &cfg->dev->dev;
9ba848ac 399 int rc = 0;
15305514
MO
400 ulong timeout = msecs_to_jiffies(cmd->rcb.timeout * 2 * 1000);
401
402 timeout = wait_for_completion_timeout(&cmd->cevent, timeout);
ddc869e9
UK
403 if (!timeout)
404 rc = -ETIMEDOUT;
15305514 405
2450a5e3
UK
406 if (cmd->cmd_aborted)
407 rc = -EAGAIN;
408
9ba848ac 409 if (unlikely(cmd->sa.ioasc != 0)) {
88d33628
MO
410 dev_err(dev, "%s: cmd %02x failed, ioasc=%08x\n",
411 __func__, cmd->rcb.cdb[0], cmd->sa.ioasc);
ddc869e9 412 rc = -EIO;
9ba848ac
MO
413 }
414
415 return rc;
15305514
MO
416}
417
8c052e9e
MO
418/**
419 * cmd_to_target_hwq() - selects a target hardware queue for a SCSI command
420 * @host: SCSI host associated with device.
421 * @scp: SCSI command to send.
422 * @afu: SCSI command to send.
423 *
424 * Hashes a command based upon the hardware queue mode.
425 *
426 * Return: Trusted index of target hardware queue
427 */
428static u32 cmd_to_target_hwq(struct Scsi_Host *host, struct scsi_cmnd *scp,
429 struct afu *afu)
430{
431 u32 tag;
432 u32 hwq = 0;
433
434 if (afu->num_hwqs == 1)
435 return 0;
436
437 switch (afu->hwq_mode) {
438 case HWQ_MODE_RR:
439 hwq = afu->hwq_rr_count++ % afu->num_hwqs;
440 break;
441 case HWQ_MODE_TAG:
442 tag = blk_mq_unique_tag(scp->request);
443 hwq = blk_mq_unique_tag_to_hwq(tag);
444 break;
445 case HWQ_MODE_CPU:
446 hwq = smp_processor_id() % afu->num_hwqs;
447 break;
448 default:
449 WARN_ON_ONCE(1);
450 }
451
452 return hwq;
453}
454
c21e0bbf
MO
455/**
456 * send_tmf() - sends a Task Management Function (TMF)
457 * @afu: AFU to checkout from.
458 * @scp: SCSI command from stack.
459 * @tmfcmd: TMF command to send.
460 *
461 * Return:
1284fb0c 462 * 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure
c21e0bbf
MO
463 */
464static int send_tmf(struct afu *afu, struct scsi_cmnd *scp, u64 tmfcmd)
465{
8c052e9e
MO
466 struct Scsi_Host *host = scp->device->host;
467 struct cxlflash_cfg *cfg = shost_priv(host);
d4ace351 468 struct afu_cmd *cmd = sc_to_afucz(scp);
4392ba49 469 struct device *dev = &cfg->dev->dev;
8c052e9e
MO
470 int hwq_index = cmd_to_target_hwq(host, scp, afu);
471 struct hwq *hwq = get_hwq(afu, hwq_index);
c21e0bbf
MO
472 ulong lock_flags;
473 int rc = 0;
018d1dc9 474 ulong to;
c21e0bbf 475
018d1dc9
MO
476 /* When Task Management Function is active do not send another */
477 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
c21e0bbf 478 if (cfg->tmf_active)
018d1dc9
MO
479 wait_event_interruptible_lock_irq(cfg->tmf_waitq,
480 !cfg->tmf_active,
481 cfg->tmf_slock);
c21e0bbf 482 cfg->tmf_active = true;
018d1dc9 483 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf 484
fe7f9698 485 cmd->scp = scp;
d4ace351
MO
486 cmd->parent = afu;
487 cmd->cmd_tmf = true;
8c052e9e 488 cmd->hwq_index = hwq_index;
d4ace351 489
a583d00a 490 cmd->rcb.ctx_id = hwq->ctx_hndl;
5fbb96c8 491 cmd->rcb.msi = SISL_MSI_RRQ_UPDATED;
e8e17ea6 492 cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel);
c21e0bbf 493 cmd->rcb.lun_id = lun_to_lunid(scp->device->lun);
c21e0bbf 494 cmd->rcb.req_flags = (SISL_REQ_FLAGS_PORT_LUN_ID |
d4ace351
MO
495 SISL_REQ_FLAGS_SUP_UNDERRUN |
496 SISL_REQ_FLAGS_TMF_CMD);
c21e0bbf
MO
497 memcpy(cmd->rcb.cdb, &tmfcmd, sizeof(tmfcmd));
498
48b4be36 499 rc = afu->send_cmd(afu, cmd);
c21e0bbf 500 if (unlikely(rc)) {
018d1dc9 501 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
c21e0bbf 502 cfg->tmf_active = false;
018d1dc9 503 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf
MO
504 goto out;
505 }
506
018d1dc9
MO
507 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
508 to = msecs_to_jiffies(5000);
509 to = wait_event_interruptible_lock_irq_timeout(cfg->tmf_waitq,
510 !cfg->tmf_active,
511 cfg->tmf_slock,
512 to);
513 if (!to) {
514 cfg->tmf_active = false;
88d33628 515 dev_err(dev, "%s: TMF timed out\n", __func__);
018d1dc9
MO
516 rc = -1;
517 }
518 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf
MO
519out:
520 return rc;
521}
522
523/**
524 * cxlflash_driver_info() - information handler for this host driver
525 * @host: SCSI host associated with device.
526 *
527 * Return: A string describing the device.
528 */
529static const char *cxlflash_driver_info(struct Scsi_Host *host)
530{
531 return CXLFLASH_ADAPTER_NAME;
532}
533
534/**
535 * cxlflash_queuecommand() - sends a mid-layer request
536 * @host: SCSI host associated with device.
537 * @scp: SCSI command to send.
538 *
1284fb0c 539 * Return: 0 on success, SCSI_MLQUEUE_HOST_BUSY on failure
c21e0bbf
MO
540 */
541static int cxlflash_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scp)
542{
88d33628 543 struct cxlflash_cfg *cfg = shost_priv(host);
c21e0bbf 544 struct afu *afu = cfg->afu;
4392ba49 545 struct device *dev = &cfg->dev->dev;
0d8978f7 546 struct afu_cmd *cmd = sc_to_afuci(scp);
9d89326c 547 struct scatterlist *sg = scsi_sglist(scp);
8c052e9e
MO
548 int hwq_index = cmd_to_target_hwq(host, scp, afu);
549 struct hwq *hwq = get_hwq(afu, hwq_index);
9d89326c 550 u16 req_flags = SISL_REQ_FLAGS_SUP_UNDERRUN;
c21e0bbf 551 ulong lock_flags;
c21e0bbf
MO
552 int rc = 0;
553
4392ba49 554 dev_dbg_ratelimited(dev, "%s: (scp=%p) %d/%d/%d/%llu "
88d33628 555 "cdb=(%08x-%08x-%08x-%08x)\n",
4392ba49
MO
556 __func__, scp, host->host_no, scp->device->channel,
557 scp->device->id, scp->device->lun,
558 get_unaligned_be32(&((u32 *)scp->cmnd)[0]),
559 get_unaligned_be32(&((u32 *)scp->cmnd)[1]),
560 get_unaligned_be32(&((u32 *)scp->cmnd)[2]),
561 get_unaligned_be32(&((u32 *)scp->cmnd)[3]));
c21e0bbf 562
018d1dc9
MO
563 /*
564 * If a Task Management Function is active, wait for it to complete
c21e0bbf
MO
565 * before continuing with regular commands.
566 */
018d1dc9 567 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
c21e0bbf 568 if (cfg->tmf_active) {
018d1dc9 569 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf
MO
570 rc = SCSI_MLQUEUE_HOST_BUSY;
571 goto out;
572 }
018d1dc9 573 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf 574
5cdac81a 575 switch (cfg->state) {
f92ba507
MO
576 case STATE_PROBING:
577 case STATE_PROBED:
439e85c1 578 case STATE_RESET:
88d33628 579 dev_dbg_ratelimited(dev, "%s: device is in reset\n", __func__);
5cdac81a
MO
580 rc = SCSI_MLQUEUE_HOST_BUSY;
581 goto out;
582 case STATE_FAILTERM:
88d33628 583 dev_dbg_ratelimited(dev, "%s: device has failed\n", __func__);
5cdac81a
MO
584 scp->result = (DID_NO_CONNECT << 16);
585 scp->scsi_done(scp);
586 rc = 0;
587 goto out;
588 default:
589 break;
590 }
591
9d89326c 592 if (likely(sg)) {
fdc3f382
MO
593 cmd->rcb.data_len = sg->length;
594 cmd->rcb.data_ea = (uintptr_t)sg_virt(sg);
9d89326c 595 }
c21e0bbf 596
fe7f9698 597 cmd->scp = scp;
5fbb96c8 598 cmd->parent = afu;
8c052e9e 599 cmd->hwq_index = hwq_index;
c21e0bbf 600
a583d00a 601 cmd->rcb.ctx_id = hwq->ctx_hndl;
9d89326c 602 cmd->rcb.msi = SISL_MSI_RRQ_UPDATED;
e8e17ea6 603 cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel);
9d89326c 604 cmd->rcb.lun_id = lun_to_lunid(scp->device->lun);
c21e0bbf 605
9d89326c
MO
606 if (scp->sc_data_direction == DMA_TO_DEVICE)
607 req_flags |= SISL_REQ_FLAGS_HOST_WRITE;
c21e0bbf 608
9d89326c 609 cmd->rcb.req_flags = req_flags;
c21e0bbf
MO
610 memcpy(cmd->rcb.cdb, scp->cmnd, sizeof(cmd->rcb.cdb));
611
48b4be36 612 rc = afu->send_cmd(afu, cmd);
c21e0bbf
MO
613out:
614 return rc;
615}
616
617/**
15305514 618 * cxlflash_wait_for_pci_err_recovery() - wait for error recovery during probe
1284fb0c 619 * @cfg: Internal structure associated with the host.
c21e0bbf 620 */
15305514 621static void cxlflash_wait_for_pci_err_recovery(struct cxlflash_cfg *cfg)
c21e0bbf 622{
15305514 623 struct pci_dev *pdev = cfg->dev;
c21e0bbf 624
15305514
MO
625 if (pci_channel_offline(pdev))
626 wait_event_timeout(cfg->reset_waitq,
627 !pci_channel_offline(pdev),
628 CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT);
c21e0bbf
MO
629}
630
631/**
15305514 632 * free_mem() - free memory associated with the AFU
1284fb0c 633 * @cfg: Internal structure associated with the host.
c21e0bbf 634 */
15305514 635static void free_mem(struct cxlflash_cfg *cfg)
c21e0bbf 636{
15305514 637 struct afu *afu = cfg->afu;
c21e0bbf 638
15305514 639 if (cfg->afu) {
15305514
MO
640 free_pages((ulong)afu, get_order(sizeof(struct afu)));
641 cfg->afu = NULL;
5cdac81a 642 }
c21e0bbf
MO
643}
644
3b4f03cd
UK
645/**
646 * cxlflash_reset_sync() - synchronizing point for asynchronous resets
647 * @cfg: Internal structure associated with the host.
648 */
649static void cxlflash_reset_sync(struct cxlflash_cfg *cfg)
650{
651 if (cfg->async_reset_cookie == 0)
652 return;
653
654 /* Wait until all async calls prior to this cookie have completed */
655 async_synchronize_cookie(cfg->async_reset_cookie + 1);
656 cfg->async_reset_cookie = 0;
657}
658
c21e0bbf 659/**
15305514 660 * stop_afu() - stops the AFU command timers and unmaps the MMIO space
1284fb0c 661 * @cfg: Internal structure associated with the host.
c21e0bbf 662 *
15305514 663 * Safe to call with AFU in a partially allocated/initialized state.
ee91e332 664 *
d940f9ae 665 * Cancels scheduled worker threads, waits for any active internal AFU
2588f222 666 * commands to timeout, disables IRQ polling and then unmaps the MMIO space.
c21e0bbf 667 */
15305514 668static void stop_afu(struct cxlflash_cfg *cfg)
c21e0bbf 669{
15305514 670 struct afu *afu = cfg->afu;
a583d00a
UK
671 struct hwq *hwq;
672 int i;
c21e0bbf 673
d940f9ae 674 cancel_work_sync(&cfg->work_q);
3b4f03cd
UK
675 if (!current_is_async())
676 cxlflash_reset_sync(cfg);
d940f9ae 677
15305514 678 if (likely(afu)) {
de01283b
MO
679 while (atomic_read(&afu->cmds_active))
680 ssleep(1);
a583d00a
UK
681
682 if (afu_is_irqpoll_enabled(afu)) {
bb85ef68 683 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
684 hwq = get_hwq(afu, i);
685
686 irq_poll_disable(&hwq->irqpoll);
687 }
688 }
689
c21e0bbf 690 if (likely(afu->afu_map)) {
1786f4a0 691 cxl_psa_unmap((void __iomem *)afu->afu_map);
c21e0bbf
MO
692 afu->afu_map = NULL;
693 }
694 }
695}
696
697/**
9526f360 698 * term_intr() - disables all AFU interrupts
1284fb0c 699 * @cfg: Internal structure associated with the host.
c21e0bbf 700 * @level: Depth of allocation, where to begin waterfall tear down.
a583d00a 701 * @index: Index of the hardware queue.
c21e0bbf
MO
702 *
703 * Safe to call with AFU/MC in partially allocated/initialized state.
704 */
a583d00a
UK
705static void term_intr(struct cxlflash_cfg *cfg, enum undo_level level,
706 u32 index)
c21e0bbf 707{
c21e0bbf 708 struct afu *afu = cfg->afu;
4392ba49 709 struct device *dev = &cfg->dev->dev;
a583d00a 710 struct hwq *hwq;
c21e0bbf 711
a583d00a
UK
712 if (!afu) {
713 dev_err(dev, "%s: returning with NULL afu\n", __func__);
714 return;
715 }
716
717 hwq = get_hwq(afu, index);
718
719 if (!hwq->ctx) {
720 dev_err(dev, "%s: returning with NULL MC\n", __func__);
c21e0bbf
MO
721 return;
722 }
723
724 switch (level) {
c21e0bbf 725 case UNMAP_THREE:
a583d00a
UK
726 /* SISL_MSI_ASYNC_ERROR is setup only for the primary HWQ */
727 if (index == PRIMARY_HWQ)
728 cxl_unmap_afu_irq(hwq->ctx, 3, hwq);
c21e0bbf 729 case UNMAP_TWO:
a583d00a 730 cxl_unmap_afu_irq(hwq->ctx, 2, hwq);
c21e0bbf 731 case UNMAP_ONE:
a583d00a 732 cxl_unmap_afu_irq(hwq->ctx, 1, hwq);
c21e0bbf 733 case FREE_IRQ:
a583d00a 734 cxl_free_afu_irqs(hwq->ctx);
9526f360
MK
735 /* fall through */
736 case UNDO_NOOP:
737 /* No action required */
738 break;
739 }
740}
741
742/**
743 * term_mc() - terminates the master context
744 * @cfg: Internal structure associated with the host.
a583d00a 745 * @index: Index of the hardware queue.
9526f360
MK
746 *
747 * Safe to call with AFU/MC in partially allocated/initialized state.
748 */
a583d00a 749static void term_mc(struct cxlflash_cfg *cfg, u32 index)
9526f360 750{
9526f360
MK
751 struct afu *afu = cfg->afu;
752 struct device *dev = &cfg->dev->dev;
a583d00a 753 struct hwq *hwq;
2450a5e3 754 ulong lock_flags;
9526f360 755
a583d00a
UK
756 if (!afu) {
757 dev_err(dev, "%s: returning with NULL afu\n", __func__);
9526f360 758 return;
c21e0bbf 759 }
9526f360 760
a583d00a
UK
761 hwq = get_hwq(afu, index);
762
763 if (!hwq->ctx) {
764 dev_err(dev, "%s: returning with NULL MC\n", __func__);
765 return;
766 }
767
768 WARN_ON(cxl_stop_context(hwq->ctx));
769 if (index != PRIMARY_HWQ)
770 WARN_ON(cxl_release_context(hwq->ctx));
771 hwq->ctx = NULL;
2450a5e3
UK
772
773 spin_lock_irqsave(&hwq->hsq_slock, lock_flags);
774 flush_pending_cmds(hwq);
775 spin_unlock_irqrestore(&hwq->hsq_slock, lock_flags);
c21e0bbf
MO
776}
777
778/**
779 * term_afu() - terminates the AFU
1284fb0c 780 * @cfg: Internal structure associated with the host.
c21e0bbf
MO
781 *
782 * Safe to call with AFU/MC in partially allocated/initialized state.
783 */
784static void term_afu(struct cxlflash_cfg *cfg)
785{
88d33628 786 struct device *dev = &cfg->dev->dev;
a583d00a 787 int k;
88d33628 788
9526f360
MK
789 /*
790 * Tear down is carefully orchestrated to ensure
791 * no interrupts can come in when the problem state
792 * area is unmapped.
793 *
a583d00a 794 * 1) Disable all AFU interrupts for each master
9526f360 795 * 2) Unmap the problem state area
a583d00a 796 * 3) Stop each master context
9526f360 797 */
bb85ef68 798 for (k = cfg->afu->num_hwqs - 1; k >= 0; k--)
a583d00a
UK
799 term_intr(cfg, UNMAP_THREE, k);
800
c21e0bbf
MO
801 if (cfg->afu)
802 stop_afu(cfg);
803
bb85ef68 804 for (k = cfg->afu->num_hwqs - 1; k >= 0; k--)
a583d00a 805 term_mc(cfg, k);
6ded8b3c 806
88d33628 807 dev_dbg(dev, "%s: returning\n", __func__);
c21e0bbf
MO
808}
809
704c4b0d
UK
810/**
811 * notify_shutdown() - notifies device of pending shutdown
812 * @cfg: Internal structure associated with the host.
813 * @wait: Whether to wait for shutdown processing to complete.
814 *
815 * This function will notify the AFU that the adapter is being shutdown
816 * and will wait for shutdown processing to complete if wait is true.
817 * This notification should flush pending I/Os to the device and halt
818 * further I/Os until the next AFU reset is issued and device restarted.
819 */
820static void notify_shutdown(struct cxlflash_cfg *cfg, bool wait)
821{
822 struct afu *afu = cfg->afu;
823 struct device *dev = &cfg->dev->dev;
704c4b0d 824 struct dev_dependent_vals *ddv;
c885d3fe 825 __be64 __iomem *fc_port_regs;
704c4b0d
UK
826 u64 reg, status;
827 int i, retry_cnt = 0;
828
829 ddv = (struct dev_dependent_vals *)cfg->dev_id->driver_data;
830 if (!(ddv->flags & CXLFLASH_NOTIFY_SHUTDOWN))
831 return;
832
1bd2b282 833 if (!afu || !afu->afu_map) {
88d33628 834 dev_dbg(dev, "%s: Problem state area not mapped\n", __func__);
1bd2b282
UK
835 return;
836 }
837
704c4b0d 838 /* Notify AFU */
66d4bce4 839 for (i = 0; i < cfg->num_fc_ports; i++) {
c885d3fe
MO
840 fc_port_regs = get_fc_port_regs(cfg, i);
841
842 reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]);
704c4b0d 843 reg |= SISL_FC_SHUTDOWN_NORMAL;
c885d3fe 844 writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]);
704c4b0d
UK
845 }
846
847 if (!wait)
848 return;
849
850 /* Wait up to 1.5 seconds for shutdown processing to complete */
66d4bce4 851 for (i = 0; i < cfg->num_fc_ports; i++) {
c885d3fe 852 fc_port_regs = get_fc_port_regs(cfg, i);
704c4b0d 853 retry_cnt = 0;
c885d3fe 854
704c4b0d 855 while (true) {
c885d3fe 856 status = readq_be(&fc_port_regs[FC_STATUS / 8]);
704c4b0d
UK
857 if (status & SISL_STATUS_SHUTDOWN_COMPLETE)
858 break;
859 if (++retry_cnt >= MC_RETRY_CNT) {
860 dev_dbg(dev, "%s: port %d shutdown processing "
861 "not yet completed\n", __func__, i);
862 break;
863 }
864 msleep(100 * retry_cnt);
865 }
866 }
867}
868
f3d79b3e
UK
869/**
870 * cxlflash_get_minor() - gets the first available minor number
871 *
872 * Return: Unique minor number that can be used to create the character device.
873 */
874static int cxlflash_get_minor(void)
875{
876 int minor;
877 long bit;
878
879 bit = find_first_zero_bit(cxlflash_minor, CXLFLASH_MAX_ADAPTERS);
880 if (bit >= CXLFLASH_MAX_ADAPTERS)
881 return -1;
882
883 minor = bit & MINORMASK;
884 set_bit(minor, cxlflash_minor);
885 return minor;
886}
887
888/**
889 * cxlflash_put_minor() - releases the minor number
890 * @minor: Minor number that is no longer needed.
891 */
892static void cxlflash_put_minor(int minor)
893{
894 clear_bit(minor, cxlflash_minor);
895}
896
897/**
898 * cxlflash_release_chrdev() - release the character device for the host
899 * @cfg: Internal structure associated with the host.
900 */
901static void cxlflash_release_chrdev(struct cxlflash_cfg *cfg)
902{
903 put_device(cfg->chardev);
904 device_unregister(cfg->chardev);
905 cfg->chardev = NULL;
906 cdev_del(&cfg->cdev);
907 cxlflash_put_minor(MINOR(cfg->cdev.dev));
908}
909
c21e0bbf
MO
910/**
911 * cxlflash_remove() - PCI entry point to tear down host
912 * @pdev: PCI device associated with the host.
913 *
f92ba507
MO
914 * Safe to use as a cleanup in partially allocated/initialized state. Note that
915 * the reset_waitq is flushed as part of the stop/termination of user contexts.
c21e0bbf
MO
916 */
917static void cxlflash_remove(struct pci_dev *pdev)
918{
919 struct cxlflash_cfg *cfg = pci_get_drvdata(pdev);
88d33628 920 struct device *dev = &pdev->dev;
c21e0bbf
MO
921 ulong lock_flags;
922
babf985d 923 if (!pci_is_enabled(pdev)) {
88d33628 924 dev_dbg(dev, "%s: Device is disabled\n", __func__);
babf985d
UK
925 return;
926 }
927
c21e0bbf
MO
928 /* If a Task Management Function is active, wait for it to complete
929 * before continuing with remove.
930 */
018d1dc9 931 spin_lock_irqsave(&cfg->tmf_slock, lock_flags);
c21e0bbf 932 if (cfg->tmf_active)
018d1dc9
MO
933 wait_event_interruptible_lock_irq(cfg->tmf_waitq,
934 !cfg->tmf_active,
935 cfg->tmf_slock);
936 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags);
c21e0bbf 937
704c4b0d
UK
938 /* Notify AFU and wait for shutdown processing to complete */
939 notify_shutdown(cfg, true);
940
5cdac81a 941 cfg->state = STATE_FAILTERM;
65be2c79 942 cxlflash_stop_term_user_contexts(cfg);
5cdac81a 943
c21e0bbf 944 switch (cfg->init_state) {
f3d79b3e
UK
945 case INIT_STATE_CDEV:
946 cxlflash_release_chrdev(cfg);
c21e0bbf 947 case INIT_STATE_SCSI:
65be2c79 948 cxlflash_term_local_luns(cfg);
c21e0bbf 949 scsi_remove_host(cfg->host);
c21e0bbf 950 case INIT_STATE_AFU:
b45cdbaf 951 term_afu(cfg);
c21e0bbf 952 case INIT_STATE_PCI:
c21e0bbf
MO
953 pci_disable_device(pdev);
954 case INIT_STATE_NONE:
c21e0bbf 955 free_mem(cfg);
8b5b1e87 956 scsi_host_put(cfg->host);
c21e0bbf
MO
957 break;
958 }
959
88d33628 960 dev_dbg(dev, "%s: returning\n", __func__);
c21e0bbf
MO
961}
962
963/**
964 * alloc_mem() - allocates the AFU and its command pool
1284fb0c 965 * @cfg: Internal structure associated with the host.
c21e0bbf
MO
966 *
967 * A partially allocated state remains on failure.
968 *
969 * Return:
970 * 0 on success
971 * -ENOMEM on failure to allocate memory
972 */
973static int alloc_mem(struct cxlflash_cfg *cfg)
974{
975 int rc = 0;
4392ba49 976 struct device *dev = &cfg->dev->dev;
c21e0bbf 977
bae0ac69 978 /* AFU is ~28k, i.e. only one 64k page or up to seven 4k pages */
c21e0bbf
MO
979 cfg->afu = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
980 get_order(sizeof(struct afu)));
981 if (unlikely(!cfg->afu)) {
4392ba49
MO
982 dev_err(dev, "%s: cannot get %d free pages\n",
983 __func__, get_order(sizeof(struct afu)));
c21e0bbf
MO
984 rc = -ENOMEM;
985 goto out;
986 }
987 cfg->afu->parent = cfg;
bb85ef68 988 cfg->afu->desired_hwqs = CXLFLASH_DEF_HWQS;
c21e0bbf 989 cfg->afu->afu_map = NULL;
c21e0bbf
MO
990out:
991 return rc;
992}
993
994/**
995 * init_pci() - initializes the host as a PCI device
1284fb0c 996 * @cfg: Internal structure associated with the host.
c21e0bbf 997 *
1284fb0c 998 * Return: 0 on success, -errno on failure
c21e0bbf
MO
999 */
1000static int init_pci(struct cxlflash_cfg *cfg)
1001{
1002 struct pci_dev *pdev = cfg->dev;
88d33628 1003 struct device *dev = &cfg->dev->dev;
c21e0bbf
MO
1004 int rc = 0;
1005
c21e0bbf
MO
1006 rc = pci_enable_device(pdev);
1007 if (rc || pci_channel_offline(pdev)) {
1008 if (pci_channel_offline(pdev)) {
1009 cxlflash_wait_for_pci_err_recovery(cfg);
1010 rc = pci_enable_device(pdev);
1011 }
1012
1013 if (rc) {
88d33628 1014 dev_err(dev, "%s: Cannot enable adapter\n", __func__);
c21e0bbf 1015 cxlflash_wait_for_pci_err_recovery(cfg);
961487e4 1016 goto out;
c21e0bbf
MO
1017 }
1018 }
1019
c21e0bbf 1020out:
88d33628 1021 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf 1022 return rc;
c21e0bbf
MO
1023}
1024
1025/**
1026 * init_scsi() - adds the host to the SCSI stack and kicks off host scan
1284fb0c 1027 * @cfg: Internal structure associated with the host.
c21e0bbf 1028 *
1284fb0c 1029 * Return: 0 on success, -errno on failure
c21e0bbf
MO
1030 */
1031static int init_scsi(struct cxlflash_cfg *cfg)
1032{
1033 struct pci_dev *pdev = cfg->dev;
88d33628 1034 struct device *dev = &cfg->dev->dev;
c21e0bbf
MO
1035 int rc = 0;
1036
1037 rc = scsi_add_host(cfg->host, &pdev->dev);
1038 if (rc) {
88d33628 1039 dev_err(dev, "%s: scsi_add_host failed rc=%d\n", __func__, rc);
c21e0bbf
MO
1040 goto out;
1041 }
1042
1043 scsi_scan_host(cfg->host);
1044
1045out:
88d33628 1046 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
1047 return rc;
1048}
1049
1050/**
1051 * set_port_online() - transitions the specified host FC port to online state
1052 * @fc_regs: Top of MMIO region defined for specified port.
1053 *
1054 * The provided MMIO region must be mapped prior to call. Online state means
1055 * that the FC link layer has synced, completed the handshaking process, and
1056 * is ready for login to start.
1057 */
1786f4a0 1058static void set_port_online(__be64 __iomem *fc_regs)
c21e0bbf
MO
1059{
1060 u64 cmdcfg;
1061
1062 cmdcfg = readq_be(&fc_regs[FC_MTIP_CMDCONFIG / 8]);
1063 cmdcfg &= (~FC_MTIP_CMDCONFIG_OFFLINE); /* clear OFF_LINE */
1064 cmdcfg |= (FC_MTIP_CMDCONFIG_ONLINE); /* set ON_LINE */
1065 writeq_be(cmdcfg, &fc_regs[FC_MTIP_CMDCONFIG / 8]);
1066}
1067
1068/**
1069 * set_port_offline() - transitions the specified host FC port to offline state
1070 * @fc_regs: Top of MMIO region defined for specified port.
1071 *
1072 * The provided MMIO region must be mapped prior to call.
1073 */
1786f4a0 1074static void set_port_offline(__be64 __iomem *fc_regs)
c21e0bbf
MO
1075{
1076 u64 cmdcfg;
1077
1078 cmdcfg = readq_be(&fc_regs[FC_MTIP_CMDCONFIG / 8]);
1079 cmdcfg &= (~FC_MTIP_CMDCONFIG_ONLINE); /* clear ON_LINE */
1080 cmdcfg |= (FC_MTIP_CMDCONFIG_OFFLINE); /* set OFF_LINE */
1081 writeq_be(cmdcfg, &fc_regs[FC_MTIP_CMDCONFIG / 8]);
1082}
1083
1084/**
1085 * wait_port_online() - waits for the specified host FC port come online
1086 * @fc_regs: Top of MMIO region defined for specified port.
1087 * @delay_us: Number of microseconds to delay between reading port status.
1088 * @nretry: Number of cycles to retry reading port status.
1089 *
1090 * The provided MMIO region must be mapped prior to call. This will timeout
1091 * when the cable is not plugged in.
1092 *
1093 * Return:
1094 * TRUE (1) when the specified port is online
1095 * FALSE (0) when the specified port fails to come online after timeout
c21e0bbf 1096 */
88d33628 1097static bool wait_port_online(__be64 __iomem *fc_regs, u32 delay_us, u32 nretry)
c21e0bbf
MO
1098{
1099 u64 status;
1100
88d33628 1101 WARN_ON(delay_us < 1000);
c21e0bbf
MO
1102
1103 do {
1104 msleep(delay_us / 1000);
1105 status = readq_be(&fc_regs[FC_MTIP_STATUS / 8]);
05dab432
MO
1106 if (status == U64_MAX)
1107 nretry /= 2;
c21e0bbf
MO
1108 } while ((status & FC_MTIP_STATUS_MASK) != FC_MTIP_STATUS_ONLINE &&
1109 nretry--);
1110
1111 return ((status & FC_MTIP_STATUS_MASK) == FC_MTIP_STATUS_ONLINE);
1112}
1113
1114/**
1115 * wait_port_offline() - waits for the specified host FC port go offline
1116 * @fc_regs: Top of MMIO region defined for specified port.
1117 * @delay_us: Number of microseconds to delay between reading port status.
1118 * @nretry: Number of cycles to retry reading port status.
1119 *
1120 * The provided MMIO region must be mapped prior to call.
1121 *
1122 * Return:
1123 * TRUE (1) when the specified port is offline
1124 * FALSE (0) when the specified port fails to go offline after timeout
c21e0bbf 1125 */
88d33628 1126static bool wait_port_offline(__be64 __iomem *fc_regs, u32 delay_us, u32 nretry)
c21e0bbf
MO
1127{
1128 u64 status;
1129
88d33628 1130 WARN_ON(delay_us < 1000);
c21e0bbf
MO
1131
1132 do {
1133 msleep(delay_us / 1000);
1134 status = readq_be(&fc_regs[FC_MTIP_STATUS / 8]);
05dab432
MO
1135 if (status == U64_MAX)
1136 nretry /= 2;
c21e0bbf
MO
1137 } while ((status & FC_MTIP_STATUS_MASK) != FC_MTIP_STATUS_OFFLINE &&
1138 nretry--);
1139
1140 return ((status & FC_MTIP_STATUS_MASK) == FC_MTIP_STATUS_OFFLINE);
1141}
1142
1143/**
1144 * afu_set_wwpn() - configures the WWPN for the specified host FC port
1145 * @afu: AFU associated with the host that owns the specified FC port.
1146 * @port: Port number being configured.
1147 * @fc_regs: Top of MMIO region defined for specified port.
1148 * @wwpn: The world-wide-port-number previously discovered for port.
1149 *
1150 * The provided MMIO region must be mapped prior to call. As part of the
1151 * sequence to configure the WWPN, the port is toggled offline and then back
1152 * online. This toggling action can cause this routine to delay up to a few
1153 * seconds. When configured to use the internal LUN feature of the AFU, a
1154 * failure to come online is overridden.
c21e0bbf 1155 */
f8013261
MO
1156static void afu_set_wwpn(struct afu *afu, int port, __be64 __iomem *fc_regs,
1157 u64 wwpn)
c21e0bbf 1158{
88d33628
MO
1159 struct cxlflash_cfg *cfg = afu->parent;
1160 struct device *dev = &cfg->dev->dev;
1161
c21e0bbf 1162 set_port_offline(fc_regs);
c21e0bbf
MO
1163 if (!wait_port_offline(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US,
1164 FC_PORT_STATUS_RETRY_CNT)) {
88d33628
MO
1165 dev_dbg(dev, "%s: wait on port %d to go offline timed out\n",
1166 __func__, port);
c21e0bbf
MO
1167 }
1168
f8013261 1169 writeq_be(wwpn, &fc_regs[FC_PNAME / 8]);
964497b3 1170
c21e0bbf 1171 set_port_online(fc_regs);
c21e0bbf
MO
1172 if (!wait_port_online(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US,
1173 FC_PORT_STATUS_RETRY_CNT)) {
88d33628
MO
1174 dev_dbg(dev, "%s: wait on port %d to go online timed out\n",
1175 __func__, port);
c21e0bbf 1176 }
c21e0bbf
MO
1177}
1178
1179/**
1180 * afu_link_reset() - resets the specified host FC port
1181 * @afu: AFU associated with the host that owns the specified FC port.
1182 * @port: Port number being configured.
1183 * @fc_regs: Top of MMIO region defined for specified port.
1184 *
1185 * The provided MMIO region must be mapped prior to call. The sequence to
1186 * reset the port involves toggling it offline and then back online. This
1187 * action can cause this routine to delay up to a few seconds. An effort
1188 * is made to maintain link with the device by switching to host to use
1189 * the alternate port exclusively while the reset takes place.
1190 * failure to come online is overridden.
1191 */
1786f4a0 1192static void afu_link_reset(struct afu *afu, int port, __be64 __iomem *fc_regs)
c21e0bbf 1193{
88d33628
MO
1194 struct cxlflash_cfg *cfg = afu->parent;
1195 struct device *dev = &cfg->dev->dev;
c21e0bbf
MO
1196 u64 port_sel;
1197
1198 /* first switch the AFU to the other links, if any */
1199 port_sel = readq_be(&afu->afu_map->global.regs.afu_port_sel);
4da74db0 1200 port_sel &= ~(1ULL << port);
c21e0bbf
MO
1201 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel);
1202 cxlflash_afu_sync(afu, 0, 0, AFU_GSYNC);
1203
1204 set_port_offline(fc_regs);
1205 if (!wait_port_offline(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US,
1206 FC_PORT_STATUS_RETRY_CNT))
88d33628
MO
1207 dev_err(dev, "%s: wait on port %d to go offline timed out\n",
1208 __func__, port);
c21e0bbf
MO
1209
1210 set_port_online(fc_regs);
1211 if (!wait_port_online(fc_regs, FC_PORT_STATUS_RETRY_INTERVAL_US,
1212 FC_PORT_STATUS_RETRY_CNT))
88d33628
MO
1213 dev_err(dev, "%s: wait on port %d to go online timed out\n",
1214 __func__, port);
c21e0bbf
MO
1215
1216 /* switch back to include this port */
4da74db0 1217 port_sel |= (1ULL << port);
c21e0bbf
MO
1218 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel);
1219 cxlflash_afu_sync(afu, 0, 0, AFU_GSYNC);
1220
88d33628 1221 dev_dbg(dev, "%s: returning port_sel=%016llx\n", __func__, port_sel);
c21e0bbf
MO
1222}
1223
c21e0bbf
MO
1224/**
1225 * afu_err_intr_init() - clears and initializes the AFU for error interrupts
1226 * @afu: AFU associated with the host.
1227 */
1228static void afu_err_intr_init(struct afu *afu)
1229{
66d4bce4 1230 struct cxlflash_cfg *cfg = afu->parent;
c885d3fe 1231 __be64 __iomem *fc_port_regs;
c21e0bbf 1232 int i;
a583d00a 1233 struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ);
c21e0bbf
MO
1234 u64 reg;
1235
1236 /* global async interrupts: AFU clears afu_ctrl on context exit
1237 * if async interrupts were sent to that context. This prevents
1238 * the AFU form sending further async interrupts when
1239 * there is
1240 * nobody to receive them.
1241 */
1242
1243 /* mask all */
1244 writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_mask);
a583d00a
UK
1245 /* set LISN# to send and point to primary master context */
1246 reg = ((u64) (((hwq->ctx_hndl << 8) | SISL_MSI_ASYNC_ERROR)) << 40);
c21e0bbf
MO
1247
1248 if (afu->internal_lun)
1249 reg |= 1; /* Bit 63 indicates local lun */
1250 writeq_be(reg, &afu->afu_map->global.regs.afu_ctrl);
1251 /* clear all */
1252 writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_clear);
1253 /* unmask bits that are of interest */
1254 /* note: afu can send an interrupt after this step */
1255 writeq_be(SISL_ASTATUS_MASK, &afu->afu_map->global.regs.aintr_mask);
1256 /* clear again in case a bit came on after previous clear but before */
1257 /* unmask */
1258 writeq_be(-1ULL, &afu->afu_map->global.regs.aintr_clear);
1259
1260 /* Clear/Set internal lun bits */
c885d3fe
MO
1261 fc_port_regs = get_fc_port_regs(cfg, 0);
1262 reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]);
c21e0bbf
MO
1263 reg &= SISL_FC_INTERNAL_MASK;
1264 if (afu->internal_lun)
1265 reg |= ((u64)(afu->internal_lun - 1) << SISL_FC_INTERNAL_SHIFT);
c885d3fe 1266 writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]);
c21e0bbf
MO
1267
1268 /* now clear FC errors */
66d4bce4 1269 for (i = 0; i < cfg->num_fc_ports; i++) {
c885d3fe
MO
1270 fc_port_regs = get_fc_port_regs(cfg, i);
1271
1272 writeq_be(0xFFFFFFFFU, &fc_port_regs[FC_ERROR / 8]);
1273 writeq_be(0, &fc_port_regs[FC_ERRCAP / 8]);
c21e0bbf
MO
1274 }
1275
1276 /* sync interrupts for master's IOARRIN write */
1277 /* note that unlike asyncs, there can be no pending sync interrupts */
1278 /* at this time (this is a fresh context and master has not written */
1279 /* IOARRIN yet), so there is nothing to clear. */
1280
1281 /* set LISN#, it is always sent to the context that wrote IOARRIN */
bb85ef68 1282 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
1283 hwq = get_hwq(afu, i);
1284
1285 writeq_be(SISL_MSI_SYNC_ERROR, &hwq->host_map->ctx_ctrl);
1286 writeq_be(SISL_ISTATUS_MASK, &hwq->host_map->intr_mask);
1287 }
c21e0bbf
MO
1288}
1289
1290/**
1291 * cxlflash_sync_err_irq() - interrupt handler for synchronous errors
1292 * @irq: Interrupt number.
1293 * @data: Private data provided at interrupt registration, the AFU.
1294 *
1295 * Return: Always return IRQ_HANDLED.
1296 */
1297static irqreturn_t cxlflash_sync_err_irq(int irq, void *data)
1298{
a583d00a
UK
1299 struct hwq *hwq = (struct hwq *)data;
1300 struct cxlflash_cfg *cfg = hwq->afu->parent;
88d33628 1301 struct device *dev = &cfg->dev->dev;
c21e0bbf
MO
1302 u64 reg;
1303 u64 reg_unmasked;
1304
a583d00a 1305 reg = readq_be(&hwq->host_map->intr_status);
c21e0bbf
MO
1306 reg_unmasked = (reg & SISL_ISTATUS_UNMASK);
1307
1308 if (reg_unmasked == 0UL) {
88d33628
MO
1309 dev_err(dev, "%s: spurious interrupt, intr_status=%016llx\n",
1310 __func__, reg);
c21e0bbf
MO
1311 goto cxlflash_sync_err_irq_exit;
1312 }
1313
88d33628
MO
1314 dev_err(dev, "%s: unexpected interrupt, intr_status=%016llx\n",
1315 __func__, reg);
c21e0bbf 1316
a583d00a 1317 writeq_be(reg_unmasked, &hwq->host_map->intr_clear);
c21e0bbf
MO
1318
1319cxlflash_sync_err_irq_exit:
c21e0bbf
MO
1320 return IRQ_HANDLED;
1321}
1322
1323/**
9ba1a1fb
MO
1324 * process_hrrq() - process the read-response queue
1325 * @afu: AFU associated with the host.
7bb512aa 1326 * @doneq: Queue of commands harvested from the RRQ.
2588f222 1327 * @budget: Threshold of RRQ entries to process.
7bb512aa
MO
1328 *
1329 * This routine must be called holding the disabled RRQ spin lock.
c21e0bbf 1330 *
9ba1a1fb 1331 * Return: The number of entries processed.
c21e0bbf 1332 */
a583d00a 1333static int process_hrrq(struct hwq *hwq, struct list_head *doneq, int budget)
c21e0bbf 1334{
a583d00a 1335 struct afu *afu = hwq->afu;
c21e0bbf 1336 struct afu_cmd *cmd;
bae0ac69
MO
1337 struct sisl_ioasa *ioasa;
1338 struct sisl_ioarcb *ioarcb;
a583d00a 1339 bool toggle = hwq->toggle;
9ba1a1fb 1340 int num_hrrq = 0;
c21e0bbf 1341 u64 entry,
a583d00a
UK
1342 *hrrq_start = hwq->hrrq_start,
1343 *hrrq_end = hwq->hrrq_end,
1344 *hrrq_curr = hwq->hrrq_curr;
c21e0bbf 1345
2588f222 1346 /* Process ready RRQ entries up to the specified budget (if any) */
c21e0bbf
MO
1347 while (true) {
1348 entry = *hrrq_curr;
1349
1350 if ((entry & SISL_RESP_HANDLE_T_BIT) != toggle)
1351 break;
1352
bae0ac69
MO
1353 entry &= ~SISL_RESP_HANDLE_T_BIT;
1354
1355 if (afu_is_sq_cmd_mode(afu)) {
1356 ioasa = (struct sisl_ioasa *)entry;
1357 cmd = container_of(ioasa, struct afu_cmd, sa);
1358 } else {
1359 ioarcb = (struct sisl_ioarcb *)entry;
1360 cmd = container_of(ioarcb, struct afu_cmd, rcb);
1361 }
1362
7bb512aa 1363 list_add_tail(&cmd->queue, doneq);
c21e0bbf
MO
1364
1365 /* Advance to next entry or wrap and flip the toggle bit */
1366 if (hrrq_curr < hrrq_end)
1367 hrrq_curr++;
1368 else {
1369 hrrq_curr = hrrq_start;
1370 toggle ^= SISL_RESP_HANDLE_T_BIT;
1371 }
bae0ac69 1372
a583d00a 1373 atomic_inc(&hwq->hsq_credits);
9ba1a1fb 1374 num_hrrq++;
2588f222
MO
1375
1376 if (budget > 0 && num_hrrq >= budget)
1377 break;
c21e0bbf
MO
1378 }
1379
a583d00a
UK
1380 hwq->hrrq_curr = hrrq_curr;
1381 hwq->toggle = toggle;
c21e0bbf 1382
9ba1a1fb
MO
1383 return num_hrrq;
1384}
1385
7bb512aa
MO
1386/**
1387 * process_cmd_doneq() - process a queue of harvested RRQ commands
1388 * @doneq: Queue of completed commands.
1389 *
1390 * Note that upon return the queue can no longer be trusted.
1391 */
1392static void process_cmd_doneq(struct list_head *doneq)
1393{
1394 struct afu_cmd *cmd, *tmp;
1395
1396 WARN_ON(list_empty(doneq));
1397
1398 list_for_each_entry_safe(cmd, tmp, doneq, queue)
1399 cmd_complete(cmd);
1400}
1401
2588f222
MO
1402/**
1403 * cxlflash_irqpoll() - process a queue of harvested RRQ commands
1404 * @irqpoll: IRQ poll structure associated with queue to poll.
1405 * @budget: Threshold of RRQ entries to process per poll.
1406 *
1407 * Return: The number of entries processed.
1408 */
1409static int cxlflash_irqpoll(struct irq_poll *irqpoll, int budget)
1410{
a583d00a 1411 struct hwq *hwq = container_of(irqpoll, struct hwq, irqpoll);
2588f222
MO
1412 unsigned long hrrq_flags;
1413 LIST_HEAD(doneq);
1414 int num_entries = 0;
1415
a583d00a 1416 spin_lock_irqsave(&hwq->hrrq_slock, hrrq_flags);
2588f222 1417
a583d00a 1418 num_entries = process_hrrq(hwq, &doneq, budget);
2588f222
MO
1419 if (num_entries < budget)
1420 irq_poll_complete(irqpoll);
1421
a583d00a 1422 spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags);
2588f222
MO
1423
1424 process_cmd_doneq(&doneq);
1425 return num_entries;
1426}
1427
9ba1a1fb
MO
1428/**
1429 * cxlflash_rrq_irq() - interrupt handler for read-response queue (normal path)
1430 * @irq: Interrupt number.
1431 * @data: Private data provided at interrupt registration, the AFU.
1432 *
7bb512aa 1433 * Return: IRQ_HANDLED or IRQ_NONE when no ready entries found.
9ba1a1fb
MO
1434 */
1435static irqreturn_t cxlflash_rrq_irq(int irq, void *data)
1436{
a583d00a
UK
1437 struct hwq *hwq = (struct hwq *)data;
1438 struct afu *afu = hwq->afu;
7bb512aa
MO
1439 unsigned long hrrq_flags;
1440 LIST_HEAD(doneq);
1441 int num_entries = 0;
9ba1a1fb 1442
a583d00a 1443 spin_lock_irqsave(&hwq->hrrq_slock, hrrq_flags);
2588f222
MO
1444
1445 if (afu_is_irqpoll_enabled(afu)) {
a583d00a
UK
1446 irq_poll_sched(&hwq->irqpoll);
1447 spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags);
2588f222
MO
1448 return IRQ_HANDLED;
1449 }
1450
a583d00a
UK
1451 num_entries = process_hrrq(hwq, &doneq, -1);
1452 spin_unlock_irqrestore(&hwq->hrrq_slock, hrrq_flags);
7bb512aa
MO
1453
1454 if (num_entries == 0)
1455 return IRQ_NONE;
1456
1457 process_cmd_doneq(&doneq);
c21e0bbf
MO
1458 return IRQ_HANDLED;
1459}
1460
8056044c
MO
1461/*
1462 * Asynchronous interrupt information table
1463 *
1464 * NOTE:
1465 * - Order matters here as this array is indexed by bit position.
1466 *
1467 * - The checkpatch script considers the BUILD_SISL_ASTATUS_FC_PORT macro
1468 * as complex and complains due to a lack of parentheses/braces.
1469 */
1470#define ASTATUS_FC(_a, _b, _c, _d) \
1471 { SISL_ASTATUS_FC##_a##_##_b, _c, _a, (_d) }
1472
1473#define BUILD_SISL_ASTATUS_FC_PORT(_a) \
1474 ASTATUS_FC(_a, LINK_UP, "link up", 0), \
1475 ASTATUS_FC(_a, LINK_DN, "link down", 0), \
1476 ASTATUS_FC(_a, LOGI_S, "login succeeded", SCAN_HOST), \
1477 ASTATUS_FC(_a, LOGI_F, "login failed", CLR_FC_ERROR), \
1478 ASTATUS_FC(_a, LOGI_R, "login timed out, retrying", LINK_RESET), \
1479 ASTATUS_FC(_a, CRC_T, "CRC threshold exceeded", LINK_RESET), \
1480 ASTATUS_FC(_a, LOGO, "target initiated LOGO", 0), \
1481 ASTATUS_FC(_a, OTHER, "other error", CLR_FC_ERROR | LINK_RESET)
1482
1483static const struct asyc_intr_info ainfo[] = {
1484 BUILD_SISL_ASTATUS_FC_PORT(1),
1485 BUILD_SISL_ASTATUS_FC_PORT(0),
1486 BUILD_SISL_ASTATUS_FC_PORT(3),
1487 BUILD_SISL_ASTATUS_FC_PORT(2)
1488};
1489
c21e0bbf
MO
1490/**
1491 * cxlflash_async_err_irq() - interrupt handler for asynchronous errors
1492 * @irq: Interrupt number.
1493 * @data: Private data provided at interrupt registration, the AFU.
1494 *
1495 * Return: Always return IRQ_HANDLED.
1496 */
1497static irqreturn_t cxlflash_async_err_irq(int irq, void *data)
1498{
a583d00a
UK
1499 struct hwq *hwq = (struct hwq *)data;
1500 struct afu *afu = hwq->afu;
4392ba49
MO
1501 struct cxlflash_cfg *cfg = afu->parent;
1502 struct device *dev = &cfg->dev->dev;
c21e0bbf 1503 const struct asyc_intr_info *info;
1786f4a0 1504 struct sisl_global_map __iomem *global = &afu->afu_map->global;
c885d3fe 1505 __be64 __iomem *fc_port_regs;
8056044c 1506 u64 reg_unmasked;
c21e0bbf 1507 u64 reg;
8056044c 1508 u64 bit;
c21e0bbf 1509 u8 port;
c21e0bbf 1510
c21e0bbf
MO
1511 reg = readq_be(&global->regs.aintr_status);
1512 reg_unmasked = (reg & SISL_ASTATUS_UNMASK);
1513
8056044c 1514 if (unlikely(reg_unmasked == 0)) {
88d33628 1515 dev_err(dev, "%s: spurious interrupt, aintr_status=%016llx\n",
4392ba49 1516 __func__, reg);
c21e0bbf
MO
1517 goto out;
1518 }
1519
f15fbf8d 1520 /* FYI, it is 'okay' to clear AFU status before FC_ERROR */
c21e0bbf
MO
1521 writeq_be(reg_unmasked, &global->regs.aintr_clear);
1522
f15fbf8d 1523 /* Check each bit that is on */
8056044c
MO
1524 for_each_set_bit(bit, (ulong *)&reg_unmasked, BITS_PER_LONG) {
1525 if (unlikely(bit >= ARRAY_SIZE(ainfo))) {
1526 WARN_ON_ONCE(1);
c21e0bbf 1527 continue;
8056044c
MO
1528 }
1529
1530 info = &ainfo[bit];
1531 if (unlikely(info->status != 1ULL << bit)) {
1532 WARN_ON_ONCE(1);
1533 continue;
1534 }
c21e0bbf
MO
1535
1536 port = info->port;
c885d3fe 1537 fc_port_regs = get_fc_port_regs(cfg, port);
c21e0bbf 1538
88d33628 1539 dev_err(dev, "%s: FC Port %d -> %s, fc_status=%016llx\n",
4392ba49 1540 __func__, port, info->desc,
c885d3fe 1541 readq_be(&fc_port_regs[FC_STATUS / 8]));
c21e0bbf
MO
1542
1543 /*
f15fbf8d 1544 * Do link reset first, some OTHER errors will set FC_ERROR
c21e0bbf
MO
1545 * again if cleared before or w/o a reset
1546 */
1547 if (info->action & LINK_RESET) {
4392ba49
MO
1548 dev_err(dev, "%s: FC Port %d: resetting link\n",
1549 __func__, port);
c21e0bbf
MO
1550 cfg->lr_state = LINK_RESET_REQUIRED;
1551 cfg->lr_port = port;
1552 schedule_work(&cfg->work_q);
1553 }
1554
1555 if (info->action & CLR_FC_ERROR) {
c885d3fe 1556 reg = readq_be(&fc_port_regs[FC_ERROR / 8]);
c21e0bbf
MO
1557
1558 /*
f15fbf8d 1559 * Since all errors are unmasked, FC_ERROR and FC_ERRCAP
c21e0bbf
MO
1560 * should be the same and tracing one is sufficient.
1561 */
1562
88d33628 1563 dev_err(dev, "%s: fc %d: clearing fc_error=%016llx\n",
4392ba49 1564 __func__, port, reg);
c21e0bbf 1565
c885d3fe
MO
1566 writeq_be(reg, &fc_port_regs[FC_ERROR / 8]);
1567 writeq_be(0, &fc_port_regs[FC_ERRCAP / 8]);
c21e0bbf 1568 }
ef51074a
MO
1569
1570 if (info->action & SCAN_HOST) {
1571 atomic_inc(&cfg->scan_host_needed);
1572 schedule_work(&cfg->work_q);
1573 }
c21e0bbf
MO
1574 }
1575
1576out:
c21e0bbf
MO
1577 return IRQ_HANDLED;
1578}
1579
1580/**
1581 * start_context() - starts the master context
1284fb0c 1582 * @cfg: Internal structure associated with the host.
a583d00a 1583 * @index: Index of the hardware queue.
c21e0bbf
MO
1584 *
1585 * Return: A success or failure value from CXL services.
1586 */
a583d00a 1587static int start_context(struct cxlflash_cfg *cfg, u32 index)
c21e0bbf 1588{
88d33628 1589 struct device *dev = &cfg->dev->dev;
a583d00a 1590 struct hwq *hwq = get_hwq(cfg->afu, index);
c21e0bbf
MO
1591 int rc = 0;
1592
a583d00a
UK
1593 rc = cxl_start_context(hwq->ctx,
1594 hwq->work.work_element_descriptor,
c21e0bbf
MO
1595 NULL);
1596
88d33628 1597 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
1598 return rc;
1599}
1600
1601/**
1602 * read_vpd() - obtains the WWPNs from VPD
1284fb0c 1603 * @cfg: Internal structure associated with the host.
66d4bce4 1604 * @wwpn: Array of size MAX_FC_PORTS to pass back WWPNs
c21e0bbf 1605 *
1284fb0c 1606 * Return: 0 on success, -errno on failure
c21e0bbf
MO
1607 */
1608static int read_vpd(struct cxlflash_cfg *cfg, u64 wwpn[])
1609{
88d33628
MO
1610 struct device *dev = &cfg->dev->dev;
1611 struct pci_dev *pdev = cfg->dev;
c21e0bbf
MO
1612 int rc = 0;
1613 int ro_start, ro_size, i, j, k;
1614 ssize_t vpd_size;
1615 char vpd_data[CXLFLASH_VPD_LEN];
1616 char tmp_buf[WWPN_BUF_LEN] = { 0 };
bdcff1c5 1617 char *wwpn_vpd_tags[MAX_FC_PORTS] = { "V5", "V6", "V7", "V8" };
c21e0bbf
MO
1618
1619 /* Get the VPD data from the device */
88d33628 1620 vpd_size = cxl_read_adapter_vpd(pdev, vpd_data, sizeof(vpd_data));
c21e0bbf 1621 if (unlikely(vpd_size <= 0)) {
88d33628
MO
1622 dev_err(dev, "%s: Unable to read VPD (size = %ld)\n",
1623 __func__, vpd_size);
c21e0bbf
MO
1624 rc = -ENODEV;
1625 goto out;
1626 }
1627
1628 /* Get the read only section offset */
1629 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size,
1630 PCI_VPD_LRDT_RO_DATA);
1631 if (unlikely(ro_start < 0)) {
88d33628 1632 dev_err(dev, "%s: VPD Read-only data not found\n", __func__);
c21e0bbf
MO
1633 rc = -ENODEV;
1634 goto out;
1635 }
1636
1637 /* Get the read only section size, cap when extends beyond read VPD */
1638 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
1639 j = ro_size;
1640 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
1641 if (unlikely((i + j) > vpd_size)) {
88d33628
MO
1642 dev_dbg(dev, "%s: Might need to read more VPD (%d > %ld)\n",
1643 __func__, (i + j), vpd_size);
c21e0bbf
MO
1644 ro_size = vpd_size - i;
1645 }
1646
1647 /*
1648 * Find the offset of the WWPN tag within the read only
1649 * VPD data and validate the found field (partials are
1650 * no good to us). Convert the ASCII data to an integer
1651 * value. Note that we must copy to a temporary buffer
1652 * because the conversion service requires that the ASCII
1653 * string be terminated.
1654 */
66d4bce4 1655 for (k = 0; k < cfg->num_fc_ports; k++) {
c21e0bbf
MO
1656 j = ro_size;
1657 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
1658
1659 i = pci_vpd_find_info_keyword(vpd_data, i, j, wwpn_vpd_tags[k]);
1660 if (unlikely(i < 0)) {
88d33628
MO
1661 dev_err(dev, "%s: Port %d WWPN not found in VPD\n",
1662 __func__, k);
c21e0bbf
MO
1663 rc = -ENODEV;
1664 goto out;
1665 }
1666
1667 j = pci_vpd_info_field_size(&vpd_data[i]);
1668 i += PCI_VPD_INFO_FLD_HDR_SIZE;
1669 if (unlikely((i + j > vpd_size) || (j != WWPN_LEN))) {
88d33628
MO
1670 dev_err(dev, "%s: Port %d WWPN incomplete or bad VPD\n",
1671 __func__, k);
c21e0bbf
MO
1672 rc = -ENODEV;
1673 goto out;
1674 }
1675
1676 memcpy(tmp_buf, &vpd_data[i], WWPN_LEN);
1677 rc = kstrtoul(tmp_buf, WWPN_LEN, (ulong *)&wwpn[k]);
1678 if (unlikely(rc)) {
88d33628
MO
1679 dev_err(dev, "%s: WWPN conversion failed for port %d\n",
1680 __func__, k);
c21e0bbf
MO
1681 rc = -ENODEV;
1682 goto out;
1683 }
66d4bce4
MO
1684
1685 dev_dbg(dev, "%s: wwpn%d=%016llx\n", __func__, k, wwpn[k]);
c21e0bbf
MO
1686 }
1687
1688out:
88d33628 1689 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
1690 return rc;
1691}
1692
1693/**
15305514 1694 * init_pcr() - initialize the provisioning and control registers
1284fb0c 1695 * @cfg: Internal structure associated with the host.
c21e0bbf 1696 *
15305514
MO
1697 * Also sets up fast access to the mapped registers and initializes AFU
1698 * command fields that never change.
c21e0bbf 1699 */
15305514 1700static void init_pcr(struct cxlflash_cfg *cfg)
c21e0bbf
MO
1701{
1702 struct afu *afu = cfg->afu;
1786f4a0 1703 struct sisl_ctrl_map __iomem *ctrl_map;
a583d00a 1704 struct hwq *hwq;
c21e0bbf
MO
1705 int i;
1706
1707 for (i = 0; i < MAX_CONTEXT; i++) {
1708 ctrl_map = &afu->afu_map->ctrls[i].ctrl;
f15fbf8d
MO
1709 /* Disrupt any clients that could be running */
1710 /* e.g. clients that survived a master restart */
c21e0bbf
MO
1711 writeq_be(0, &ctrl_map->rht_start);
1712 writeq_be(0, &ctrl_map->rht_cnt_id);
1713 writeq_be(0, &ctrl_map->ctx_cap);
1714 }
1715
a583d00a 1716 /* Copy frequently used fields into hwq */
bb85ef68 1717 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
1718 hwq = get_hwq(afu, i);
1719
1720 hwq->ctx_hndl = (u16) cxl_process_element(hwq->ctx);
1721 hwq->host_map = &afu->afu_map->hosts[hwq->ctx_hndl].host;
1722 hwq->ctrl_map = &afu->afu_map->ctrls[hwq->ctx_hndl].ctrl;
c21e0bbf 1723
a583d00a
UK
1724 /* Program the Endian Control for the master context */
1725 writeq_be(SISL_ENDIAN_CTRL, &hwq->host_map->endian_ctrl);
1726 }
c21e0bbf
MO
1727}
1728
1729/**
1730 * init_global() - initialize AFU global registers
1284fb0c 1731 * @cfg: Internal structure associated with the host.
c21e0bbf 1732 */
15305514 1733static int init_global(struct cxlflash_cfg *cfg)
c21e0bbf
MO
1734{
1735 struct afu *afu = cfg->afu;
4392ba49 1736 struct device *dev = &cfg->dev->dev;
a583d00a
UK
1737 struct hwq *hwq;
1738 struct sisl_host_map __iomem *hmap;
c885d3fe 1739 __be64 __iomem *fc_port_regs;
66d4bce4 1740 u64 wwpn[MAX_FC_PORTS]; /* wwpn of AFU ports */
c21e0bbf
MO
1741 int i = 0, num_ports = 0;
1742 int rc = 0;
1743 u64 reg;
1744
1745 rc = read_vpd(cfg, &wwpn[0]);
1746 if (rc) {
4392ba49 1747 dev_err(dev, "%s: could not read vpd rc=%d\n", __func__, rc);
c21e0bbf
MO
1748 goto out;
1749 }
1750
a583d00a 1751 /* Set up RRQ and SQ in HWQ for master issued cmds */
bb85ef68 1752 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
1753 hwq = get_hwq(afu, i);
1754 hmap = hwq->host_map;
c21e0bbf 1755
a583d00a
UK
1756 writeq_be((u64) hwq->hrrq_start, &hmap->rrq_start);
1757 writeq_be((u64) hwq->hrrq_end, &hmap->rrq_end);
1758
1759 if (afu_is_sq_cmd_mode(afu)) {
1760 writeq_be((u64)hwq->hsq_start, &hmap->sq_start);
1761 writeq_be((u64)hwq->hsq_end, &hmap->sq_end);
1762 }
bae0ac69
MO
1763 }
1764
c21e0bbf
MO
1765 /* AFU configuration */
1766 reg = readq_be(&afu->afu_map->global.regs.afu_config);
1767 reg |= SISL_AFUCONF_AR_ALL|SISL_AFUCONF_ENDIAN;
1768 /* enable all auto retry options and control endianness */
1769 /* leave others at default: */
1770 /* CTX_CAP write protected, mbox_r does not clear on read and */
1771 /* checker on if dual afu */
1772 writeq_be(reg, &afu->afu_map->global.regs.afu_config);
1773
f15fbf8d 1774 /* Global port select: select either port */
c21e0bbf 1775 if (afu->internal_lun) {
f15fbf8d 1776 /* Only use port 0 */
c21e0bbf 1777 writeq_be(PORT0, &afu->afu_map->global.regs.afu_port_sel);
66d4bce4 1778 num_ports = 0;
c21e0bbf 1779 } else {
e8e17ea6
MO
1780 writeq_be(PORT_MASK(cfg->num_fc_ports),
1781 &afu->afu_map->global.regs.afu_port_sel);
66d4bce4 1782 num_ports = cfg->num_fc_ports;
c21e0bbf
MO
1783 }
1784
1785 for (i = 0; i < num_ports; i++) {
c885d3fe
MO
1786 fc_port_regs = get_fc_port_regs(cfg, i);
1787
f15fbf8d 1788 /* Unmask all errors (but they are still masked at AFU) */
c885d3fe 1789 writeq_be(0, &fc_port_regs[FC_ERRMSK / 8]);
f15fbf8d 1790 /* Clear CRC error cnt & set a threshold */
c885d3fe
MO
1791 (void)readq_be(&fc_port_regs[FC_CNT_CRCERR / 8]);
1792 writeq_be(MC_CRC_THRESH, &fc_port_regs[FC_CRC_THRESH / 8]);
c21e0bbf 1793
f15fbf8d 1794 /* Set WWPNs. If already programmed, wwpn[i] is 0 */
f8013261 1795 if (wwpn[i] != 0)
c885d3fe 1796 afu_set_wwpn(afu, i, &fc_port_regs[0], wwpn[i]);
c21e0bbf
MO
1797 /* Programming WWPN back to back causes additional
1798 * offline/online transitions and a PLOGI
1799 */
1800 msleep(100);
c21e0bbf
MO
1801 }
1802
f15fbf8d
MO
1803 /* Set up master's own CTX_CAP to allow real mode, host translation */
1804 /* tables, afu cmds and read/write GSCSI cmds. */
c21e0bbf 1805 /* First, unlock ctx_cap write by reading mbox */
bb85ef68 1806 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
1807 hwq = get_hwq(afu, i);
1808
1809 (void)readq_be(&hwq->ctrl_map->mbox_r); /* unlock ctx_cap */
1810 writeq_be((SISL_CTX_CAP_REAL_MODE | SISL_CTX_CAP_HOST_XLATE |
1811 SISL_CTX_CAP_READ_CMD | SISL_CTX_CAP_WRITE_CMD |
1812 SISL_CTX_CAP_AFU_CMD | SISL_CTX_CAP_GSCSI_CMD),
1813 &hwq->ctrl_map->ctx_cap);
1814 }
cb1e7bff
MO
1815
1816 /*
1817 * Determine write-same unmap support for host by evaluating the unmap
1818 * sector support bit of the context control register associated with
1819 * the primary hardware queue. Note that while this status is reflected
1820 * in a context register, the outcome can be assumed to be host-wide.
1821 */
1822 hwq = get_hwq(afu, PRIMARY_HWQ);
1823 reg = readq_be(&hwq->host_map->ctx_ctrl);
1824 if (reg & SISL_CTX_CTRL_UNMAP_SECTOR)
1825 cfg->ws_unmap = true;
1826
f15fbf8d 1827 /* Initialize heartbeat */
c21e0bbf 1828 afu->hb = readq_be(&afu->afu_map->global.regs.afu_hb);
c21e0bbf
MO
1829out:
1830 return rc;
1831}
1832
1833/**
1834 * start_afu() - initializes and starts the AFU
1284fb0c 1835 * @cfg: Internal structure associated with the host.
c21e0bbf
MO
1836 */
1837static int start_afu(struct cxlflash_cfg *cfg)
1838{
1839 struct afu *afu = cfg->afu;
88d33628 1840 struct device *dev = &cfg->dev->dev;
a583d00a 1841 struct hwq *hwq;
c21e0bbf 1842 int rc = 0;
a583d00a 1843 int i;
c21e0bbf 1844
c21e0bbf
MO
1845 init_pcr(cfg);
1846
a583d00a 1847 /* Initialize each HWQ */
bb85ef68 1848 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a 1849 hwq = get_hwq(afu, i);
c21e0bbf 1850
a583d00a
UK
1851 /* After an AFU reset, RRQ entries are stale, clear them */
1852 memset(&hwq->rrq_entry, 0, sizeof(hwq->rrq_entry));
bae0ac69 1853
a583d00a
UK
1854 /* Initialize RRQ pointers */
1855 hwq->hrrq_start = &hwq->rrq_entry[0];
1856 hwq->hrrq_end = &hwq->rrq_entry[NUM_RRQ_ENTRY - 1];
1857 hwq->hrrq_curr = hwq->hrrq_start;
1858 hwq->toggle = 1;
edc034e8
UK
1859
1860 /* Initialize spin locks */
a583d00a 1861 spin_lock_init(&hwq->hrrq_slock);
edc034e8 1862 spin_lock_init(&hwq->hsq_slock);
bae0ac69 1863
a583d00a
UK
1864 /* Initialize SQ */
1865 if (afu_is_sq_cmd_mode(afu)) {
1866 memset(&hwq->sq, 0, sizeof(hwq->sq));
1867 hwq->hsq_start = &hwq->sq[0];
1868 hwq->hsq_end = &hwq->sq[NUM_SQ_ENTRY - 1];
1869 hwq->hsq_curr = hwq->hsq_start;
1870
a583d00a
UK
1871 atomic_set(&hwq->hsq_credits, NUM_SQ_ENTRY - 1);
1872 }
1873
1874 /* Initialize IRQ poll */
1875 if (afu_is_irqpoll_enabled(afu))
1876 irq_poll_init(&hwq->irqpoll, afu->irqpoll_weight,
1877 cxlflash_irqpoll);
1878
1879 }
2588f222 1880
c21e0bbf
MO
1881 rc = init_global(cfg);
1882
88d33628 1883 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
1884 return rc;
1885}
1886
1887/**
9526f360 1888 * init_intr() - setup interrupt handlers for the master context
1284fb0c 1889 * @cfg: Internal structure associated with the host.
a583d00a 1890 * @hwq: Hardware queue to initialize.
c21e0bbf 1891 *
1284fb0c 1892 * Return: 0 on success, -errno on failure
c21e0bbf 1893 */
9526f360 1894static enum undo_level init_intr(struct cxlflash_cfg *cfg,
a583d00a 1895 struct hwq *hwq)
c21e0bbf 1896{
9526f360 1897 struct device *dev = &cfg->dev->dev;
a583d00a 1898 struct cxl_context *ctx = hwq->ctx;
c21e0bbf 1899 int rc = 0;
9526f360 1900 enum undo_level level = UNDO_NOOP;
a583d00a
UK
1901 bool is_primary_hwq = (hwq->index == PRIMARY_HWQ);
1902 int num_irqs = is_primary_hwq ? 3 : 2;
c21e0bbf 1903
a583d00a 1904 rc = cxl_allocate_afu_irqs(ctx, num_irqs);
c21e0bbf 1905 if (unlikely(rc)) {
88d33628 1906 dev_err(dev, "%s: allocate_afu_irqs failed rc=%d\n",
c21e0bbf 1907 __func__, rc);
9526f360 1908 level = UNDO_NOOP;
c21e0bbf
MO
1909 goto out;
1910 }
1911
a583d00a 1912 rc = cxl_map_afu_irq(ctx, 1, cxlflash_sync_err_irq, hwq,
c21e0bbf
MO
1913 "SISL_MSI_SYNC_ERROR");
1914 if (unlikely(rc <= 0)) {
88d33628 1915 dev_err(dev, "%s: SISL_MSI_SYNC_ERROR map failed\n", __func__);
c21e0bbf
MO
1916 level = FREE_IRQ;
1917 goto out;
1918 }
1919
a583d00a 1920 rc = cxl_map_afu_irq(ctx, 2, cxlflash_rrq_irq, hwq,
c21e0bbf
MO
1921 "SISL_MSI_RRQ_UPDATED");
1922 if (unlikely(rc <= 0)) {
88d33628 1923 dev_err(dev, "%s: SISL_MSI_RRQ_UPDATED map failed\n", __func__);
c21e0bbf
MO
1924 level = UNMAP_ONE;
1925 goto out;
1926 }
1927
a583d00a
UK
1928 /* SISL_MSI_ASYNC_ERROR is setup only for the primary HWQ */
1929 if (!is_primary_hwq)
1930 goto out;
1931
1932 rc = cxl_map_afu_irq(ctx, 3, cxlflash_async_err_irq, hwq,
c21e0bbf
MO
1933 "SISL_MSI_ASYNC_ERROR");
1934 if (unlikely(rc <= 0)) {
88d33628 1935 dev_err(dev, "%s: SISL_MSI_ASYNC_ERROR map failed\n", __func__);
c21e0bbf
MO
1936 level = UNMAP_TWO;
1937 goto out;
1938 }
9526f360
MK
1939out:
1940 return level;
1941}
c21e0bbf 1942
9526f360
MK
1943/**
1944 * init_mc() - create and register as the master context
1945 * @cfg: Internal structure associated with the host.
a583d00a 1946 * index: HWQ Index of the master context.
9526f360
MK
1947 *
1948 * Return: 0 on success, -errno on failure
1949 */
a583d00a 1950static int init_mc(struct cxlflash_cfg *cfg, u32 index)
9526f360
MK
1951{
1952 struct cxl_context *ctx;
1953 struct device *dev = &cfg->dev->dev;
a583d00a 1954 struct hwq *hwq = get_hwq(cfg->afu, index);
9526f360
MK
1955 int rc = 0;
1956 enum undo_level level;
1957
a583d00a
UK
1958 hwq->afu = cfg->afu;
1959 hwq->index = index;
d732d14f 1960 INIT_LIST_HEAD(&hwq->pending_cmds);
a583d00a
UK
1961
1962 if (index == PRIMARY_HWQ)
1963 ctx = cxl_get_context(cfg->dev);
1964 else
1965 ctx = cxl_dev_context_init(cfg->dev);
9526f360
MK
1966 if (unlikely(!ctx)) {
1967 rc = -ENOMEM;
a583d00a 1968 goto err1;
9526f360 1969 }
a583d00a
UK
1970
1971 WARN_ON(hwq->ctx);
1972 hwq->ctx = ctx;
9526f360
MK
1973
1974 /* Set it up as a master with the CXL */
1975 cxl_set_master(ctx);
1976
a583d00a
UK
1977 /* Reset AFU when initializing primary context */
1978 if (index == PRIMARY_HWQ) {
1979 rc = cxl_afu_reset(ctx);
1980 if (unlikely(rc)) {
1981 dev_err(dev, "%s: AFU reset failed rc=%d\n",
1982 __func__, rc);
1983 goto err1;
1984 }
9526f360
MK
1985 }
1986
a583d00a 1987 level = init_intr(cfg, hwq);
9526f360 1988 if (unlikely(level)) {
88d33628 1989 dev_err(dev, "%s: interrupt init failed rc=%d\n", __func__, rc);
a583d00a 1990 goto err2;
9526f360 1991 }
c21e0bbf
MO
1992
1993 /* This performs the equivalent of the CXL_IOCTL_START_WORK.
1994 * The CXL_IOCTL_GET_PROCESS_ELEMENT is implicit in the process
1995 * element (pe) that is embedded in the context (ctx)
1996 */
a583d00a 1997 rc = start_context(cfg, index);
c21e0bbf
MO
1998 if (unlikely(rc)) {
1999 dev_err(dev, "%s: start context failed rc=%d\n", __func__, rc);
2000 level = UNMAP_THREE;
a583d00a 2001 goto err2;
c21e0bbf 2002 }
a583d00a
UK
2003
2004out:
88d33628 2005 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf 2006 return rc;
a583d00a
UK
2007err2:
2008 term_intr(cfg, level, index);
2009 if (index != PRIMARY_HWQ)
2010 cxl_release_context(ctx);
2011err1:
2012 hwq->ctx = NULL;
2013 goto out;
c21e0bbf
MO
2014}
2015
a290b480
MO
2016/**
2017 * get_num_afu_ports() - determines and configures the number of AFU ports
2018 * @cfg: Internal structure associated with the host.
2019 *
2020 * This routine determines the number of AFU ports by converting the global
2021 * port selection mask. The converted value is only valid following an AFU
2022 * reset (explicit or power-on). This routine must be invoked shortly after
2023 * mapping as other routines are dependent on the number of ports during the
2024 * initialization sequence.
2025 *
2026 * To support legacy AFUs that might not have reflected an initial global
2027 * port mask (value read is 0), default to the number of ports originally
2028 * supported by the cxlflash driver (2) before hardware with other port
2029 * offerings was introduced.
2030 */
2031static void get_num_afu_ports(struct cxlflash_cfg *cfg)
2032{
2033 struct afu *afu = cfg->afu;
2034 struct device *dev = &cfg->dev->dev;
2035 u64 port_mask;
2036 int num_fc_ports = LEGACY_FC_PORTS;
2037
2038 port_mask = readq_be(&afu->afu_map->global.regs.afu_port_sel);
2039 if (port_mask != 0ULL)
2040 num_fc_ports = min(ilog2(port_mask) + 1, MAX_FC_PORTS);
2041
2042 dev_dbg(dev, "%s: port_mask=%016llx num_fc_ports=%d\n",
2043 __func__, port_mask, num_fc_ports);
2044
2045 cfg->num_fc_ports = num_fc_ports;
2046 cfg->host->max_channel = PORTNUM2CHAN(num_fc_ports);
2047}
2048
c21e0bbf
MO
2049/**
2050 * init_afu() - setup as master context and start AFU
1284fb0c 2051 * @cfg: Internal structure associated with the host.
c21e0bbf
MO
2052 *
2053 * This routine is a higher level of control for configuring the
2054 * AFU on probe and reset paths.
2055 *
1284fb0c 2056 * Return: 0 on success, -errno on failure
c21e0bbf
MO
2057 */
2058static int init_afu(struct cxlflash_cfg *cfg)
2059{
2060 u64 reg;
2061 int rc = 0;
2062 struct afu *afu = cfg->afu;
2063 struct device *dev = &cfg->dev->dev;
a583d00a
UK
2064 struct hwq *hwq;
2065 int i;
c21e0bbf 2066
5cdac81a
MO
2067 cxl_perst_reloads_same_image(cfg->cxl_afu, true);
2068
bb85ef68
MO
2069 afu->num_hwqs = afu->desired_hwqs;
2070 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
2071 rc = init_mc(cfg, i);
2072 if (rc) {
2073 dev_err(dev, "%s: init_mc failed rc=%d index=%d\n",
2074 __func__, rc, i);
2075 goto err1;
2076 }
c21e0bbf
MO
2077 }
2078
a583d00a
UK
2079 /* Map the entire MMIO space of the AFU using the first context */
2080 hwq = get_hwq(afu, PRIMARY_HWQ);
2081 afu->afu_map = cxl_psa_map(hwq->ctx);
c21e0bbf 2082 if (!afu->afu_map) {
88d33628 2083 dev_err(dev, "%s: cxl_psa_map failed\n", __func__);
ee3491ba 2084 rc = -ENOMEM;
c21e0bbf
MO
2085 goto err1;
2086 }
2087
e5ce067b
MO
2088 /* No byte reverse on reading afu_version or string will be backwards */
2089 reg = readq(&afu->afu_map->global.regs.afu_version);
2090 memcpy(afu->version, &reg, sizeof(reg));
c21e0bbf
MO
2091 afu->interface_version =
2092 readq_be(&afu->afu_map->global.regs.interface_version);
e5ce067b 2093 if ((afu->interface_version + 1) == 0) {
88d33628
MO
2094 dev_err(dev, "Back level AFU, please upgrade. AFU version %s "
2095 "interface version %016llx\n", afu->version,
e5ce067b
MO
2096 afu->interface_version);
2097 rc = -EINVAL;
d940f9ae 2098 goto err1;
ee3491ba
MO
2099 }
2100
bae0ac69
MO
2101 if (afu_is_sq_cmd_mode(afu)) {
2102 afu->send_cmd = send_cmd_sq;
2103 afu->context_reset = context_reset_sq;
2104 } else {
2105 afu->send_cmd = send_cmd_ioarrin;
2106 afu->context_reset = context_reset_ioarrin;
2107 }
48b4be36 2108
88d33628
MO
2109 dev_dbg(dev, "%s: afu_ver=%s interface_ver=%016llx\n", __func__,
2110 afu->version, afu->interface_version);
c21e0bbf 2111
a290b480
MO
2112 get_num_afu_ports(cfg);
2113
c21e0bbf
MO
2114 rc = start_afu(cfg);
2115 if (rc) {
88d33628 2116 dev_err(dev, "%s: start_afu failed, rc=%d\n", __func__, rc);
d940f9ae 2117 goto err1;
c21e0bbf
MO
2118 }
2119
2120 afu_err_intr_init(cfg->afu);
bb85ef68 2121 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
2122 hwq = get_hwq(afu, i);
2123
a583d00a
UK
2124 hwq->room = readq_be(&hwq->host_map->cmd_room);
2125 }
c21e0bbf 2126
2cb79266
MO
2127 /* Restore the LUN mappings */
2128 cxlflash_restore_luntable(cfg);
ee3491ba 2129out:
88d33628 2130 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf 2131 return rc;
ee3491ba 2132
ee3491ba 2133err1:
bb85ef68 2134 for (i = afu->num_hwqs - 1; i >= 0; i--) {
a583d00a
UK
2135 term_intr(cfg, UNMAP_THREE, i);
2136 term_mc(cfg, i);
2137 }
ee3491ba 2138 goto out;
c21e0bbf
MO
2139}
2140
3b4f03cd
UK
2141/**
2142 * afu_reset() - resets the AFU
2143 * @cfg: Internal structure associated with the host.
2144 *
2145 * Return: 0 on success, -errno on failure
2146 */
2147static int afu_reset(struct cxlflash_cfg *cfg)
2148{
2149 struct device *dev = &cfg->dev->dev;
2150 int rc = 0;
2151
2152 /* Stop the context before the reset. Since the context is
2153 * no longer available restart it after the reset is complete
2154 */
2155 term_afu(cfg);
2156
2157 rc = init_afu(cfg);
2158
2159 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
2160 return rc;
2161}
2162
2163/**
2164 * drain_ioctls() - wait until all currently executing ioctls have completed
2165 * @cfg: Internal structure associated with the host.
2166 *
2167 * Obtain write access to read/write semaphore that wraps ioctl
2168 * handling to 'drain' ioctls currently executing.
2169 */
2170static void drain_ioctls(struct cxlflash_cfg *cfg)
2171{
2172 down_write(&cfg->ioctl_rwsem);
2173 up_write(&cfg->ioctl_rwsem);
2174}
2175
2176/**
2177 * cxlflash_async_reset_host() - asynchronous host reset handler
2178 * @data: Private data provided while scheduling reset.
2179 * @cookie: Cookie that can be used for checkpointing.
2180 */
2181static void cxlflash_async_reset_host(void *data, async_cookie_t cookie)
2182{
2183 struct cxlflash_cfg *cfg = data;
2184 struct device *dev = &cfg->dev->dev;
2185 int rc = 0;
2186
2187 if (cfg->state != STATE_RESET) {
2188 dev_dbg(dev, "%s: Not performing a reset, state=%d\n",
2189 __func__, cfg->state);
2190 goto out;
2191 }
2192
2193 drain_ioctls(cfg);
2194 cxlflash_mark_contexts_error(cfg);
2195 rc = afu_reset(cfg);
2196 if (rc)
2197 cfg->state = STATE_FAILTERM;
2198 else
2199 cfg->state = STATE_NORMAL;
2200 wake_up_all(&cfg->reset_waitq);
2201
2202out:
2203 scsi_unblock_requests(cfg->host);
2204}
2205
2206/**
2207 * cxlflash_schedule_async_reset() - schedule an asynchronous host reset
2208 * @cfg: Internal structure associated with the host.
2209 */
2210static void cxlflash_schedule_async_reset(struct cxlflash_cfg *cfg)
2211{
2212 struct device *dev = &cfg->dev->dev;
2213
2214 if (cfg->state != STATE_NORMAL) {
2215 dev_dbg(dev, "%s: Not performing reset state=%d\n",
2216 __func__, cfg->state);
2217 return;
2218 }
2219
2220 cfg->state = STATE_RESET;
2221 scsi_block_requests(cfg->host);
2222 cfg->async_reset_cookie = async_schedule(cxlflash_async_reset_host,
2223 cfg);
2224}
2225
c21e0bbf 2226/**
b413ed3b 2227 * send_afu_cmd() - builds and sends an internal AFU command
c21e0bbf 2228 * @afu: AFU associated with the host.
b413ed3b 2229 * @rcb: Pre-populated IOARCB describing command to send.
c21e0bbf 2230 *
b413ed3b
MO
2231 * The AFU can only take one internal AFU command at a time. This limitation is
2232 * enforced by using a mutex to provide exclusive access to the AFU during the
2233 * operation. This design point requires calling threads to not be on interrupt
2234 * context due to the possibility of sleeping during concurrent AFU operations.
c21e0bbf 2235 *
b413ed3b
MO
2236 * The command status is optionally passed back to the caller when the caller
2237 * populates the IOASA field of the IOARCB with a pointer to an IOASA structure.
5cdac81a 2238 *
c21e0bbf 2239 * Return:
91995b34 2240 * 0 on success, -errno on failure
c21e0bbf 2241 */
b413ed3b 2242static int send_afu_cmd(struct afu *afu, struct sisl_ioarcb *rcb)
c21e0bbf 2243{
5cdac81a 2244 struct cxlflash_cfg *cfg = afu->parent;
4392ba49 2245 struct device *dev = &cfg->dev->dev;
c21e0bbf 2246 struct afu_cmd *cmd = NULL;
a583d00a 2247 struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ);
350bb478 2248 char *buf = NULL;
c21e0bbf 2249 int rc = 0;
ddc869e9 2250 int nretry = 0;
c21e0bbf
MO
2251 static DEFINE_MUTEX(sync_active);
2252
5cdac81a 2253 if (cfg->state != STATE_NORMAL) {
88d33628
MO
2254 dev_dbg(dev, "%s: Sync not required state=%u\n",
2255 __func__, cfg->state);
5cdac81a
MO
2256 return 0;
2257 }
2258
c21e0bbf 2259 mutex_lock(&sync_active);
de01283b 2260 atomic_inc(&afu->cmds_active);
2450a5e3 2261 buf = kmalloc(sizeof(*cmd) + __alignof__(*cmd) - 1, GFP_KERNEL);
350bb478
MO
2262 if (unlikely(!buf)) {
2263 dev_err(dev, "%s: no memory for command\n", __func__);
91995b34 2264 rc = -ENOMEM;
c21e0bbf
MO
2265 goto out;
2266 }
2267
350bb478 2268 cmd = (struct afu_cmd *)PTR_ALIGN(buf, __alignof__(*cmd));
ddc869e9
UK
2269
2270retry:
2450a5e3 2271 memset(cmd, 0, sizeof(*cmd));
b413ed3b 2272 memcpy(&cmd->rcb, rcb, sizeof(*rcb));
2450a5e3 2273 INIT_LIST_HEAD(&cmd->queue);
350bb478 2274 init_completion(&cmd->cevent);
350bb478 2275 cmd->parent = afu;
a583d00a 2276 cmd->hwq_index = hwq->index;
a583d00a 2277 cmd->rcb.ctx_id = hwq->ctx_hndl;
c21e0bbf 2278
b413ed3b
MO
2279 dev_dbg(dev, "%s: afu=%p cmd=%p type=%02x nretry=%d\n",
2280 __func__, afu, cmd, cmd->rcb.cdb[0], nretry);
c21e0bbf 2281
48b4be36 2282 rc = afu->send_cmd(afu, cmd);
91995b34
UK
2283 if (unlikely(rc)) {
2284 rc = -ENOBUFS;
c21e0bbf 2285 goto out;
91995b34 2286 }
c21e0bbf 2287
9ba848ac 2288 rc = wait_resp(afu, cmd);
2450a5e3
UK
2289 switch (rc) {
2290 case -ETIMEDOUT:
ddc869e9 2291 rc = afu->context_reset(hwq);
2450a5e3
UK
2292 if (rc) {
2293 cxlflash_schedule_async_reset(cfg);
2294 break;
2295 }
2296 /* fall through to retry */
2297 case -EAGAIN:
2298 if (++nretry < 2)
ddc869e9 2299 goto retry;
2450a5e3
UK
2300 /* fall through to exit */
2301 default:
2302 break;
ddc869e9
UK
2303 }
2304
b413ed3b
MO
2305 if (rcb->ioasa)
2306 *rcb->ioasa = cmd->sa;
c21e0bbf 2307out:
de01283b 2308 atomic_dec(&afu->cmds_active);
c21e0bbf 2309 mutex_unlock(&sync_active);
350bb478 2310 kfree(buf);
88d33628 2311 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
2312 return rc;
2313}
2314
b413ed3b
MO
2315/**
2316 * cxlflash_afu_sync() - builds and sends an AFU sync command
2317 * @afu: AFU associated with the host.
2318 * @ctx: Identifies context requesting sync.
2319 * @res: Identifies resource requesting sync.
2320 * @mode: Type of sync to issue (lightweight, heavyweight, global).
2321 *
2322 * AFU sync operations are only necessary and allowed when the device is
2323 * operating normally. When not operating normally, sync requests can occur as
2324 * part of cleaning up resources associated with an adapter prior to removal.
2325 * In this scenario, these requests are simply ignored (safe due to the AFU
2326 * going away).
2327 *
2328 * Return:
2329 * 0 on success, -errno on failure
2330 */
2331int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t ctx, res_hndl_t res, u8 mode)
2332{
2333 struct cxlflash_cfg *cfg = afu->parent;
2334 struct device *dev = &cfg->dev->dev;
2335 struct sisl_ioarcb rcb = { 0 };
2336
2337 dev_dbg(dev, "%s: afu=%p ctx=%u res=%u mode=%u\n",
2338 __func__, afu, ctx, res, mode);
2339
2340 rcb.req_flags = SISL_REQ_FLAGS_AFU_CMD;
2341 rcb.msi = SISL_MSI_RRQ_UPDATED;
2342 rcb.timeout = MC_AFU_SYNC_TIMEOUT;
2343
2344 rcb.cdb[0] = SISL_AFU_CMD_SYNC;
2345 rcb.cdb[1] = mode;
2346 put_unaligned_be16(ctx, &rcb.cdb[2]);
2347 put_unaligned_be32(res, &rcb.cdb[4]);
2348
2349 return send_afu_cmd(afu, &rcb);
2350}
2351
4ab47257
UK
2352/**
2353 * cxlflash_eh_abort_handler() - abort a SCSI command
2354 * @scp: SCSI command to abort.
2355 *
2356 * CXL Flash devices do not support a single command abort. Reset the context
2357 * as per SISLite specification. Flush any pending commands in the hardware
2358 * queue before the reset.
2359 *
2360 * Return: SUCCESS/FAILED as defined in scsi/scsi.h
2361 */
2362static int cxlflash_eh_abort_handler(struct scsi_cmnd *scp)
2363{
2364 int rc = FAILED;
2365 struct Scsi_Host *host = scp->device->host;
2366 struct cxlflash_cfg *cfg = shost_priv(host);
2367 struct afu_cmd *cmd = sc_to_afuc(scp);
2368 struct device *dev = &cfg->dev->dev;
2369 struct afu *afu = cfg->afu;
2370 struct hwq *hwq = get_hwq(afu, cmd->hwq_index);
2371
2372 dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu "
2373 "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no,
2374 scp->device->channel, scp->device->id, scp->device->lun,
2375 get_unaligned_be32(&((u32 *)scp->cmnd)[0]),
2376 get_unaligned_be32(&((u32 *)scp->cmnd)[1]),
2377 get_unaligned_be32(&((u32 *)scp->cmnd)[2]),
2378 get_unaligned_be32(&((u32 *)scp->cmnd)[3]));
2379
2380 /* When the state is not normal, another reset/reload is in progress.
2381 * Return failed and the mid-layer will invoke host reset handler.
2382 */
2383 if (cfg->state != STATE_NORMAL) {
2384 dev_dbg(dev, "%s: Invalid state for abort, state=%d\n",
2385 __func__, cfg->state);
2386 goto out;
2387 }
2388
2389 rc = afu->context_reset(hwq);
2390 if (unlikely(rc))
2391 goto out;
2392
2393 rc = SUCCESS;
2394
2395out:
2396 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
2397 return rc;
2398}
2399
15305514
MO
2400/**
2401 * cxlflash_eh_device_reset_handler() - reset a single LUN
2402 * @scp: SCSI command to send.
2403 *
2404 * Return:
2405 * SUCCESS as defined in scsi/scsi.h
2406 * FAILED as defined in scsi/scsi.h
2407 */
2408static int cxlflash_eh_device_reset_handler(struct scsi_cmnd *scp)
2409{
2410 int rc = SUCCESS;
2411 struct Scsi_Host *host = scp->device->host;
88d33628
MO
2412 struct cxlflash_cfg *cfg = shost_priv(host);
2413 struct device *dev = &cfg->dev->dev;
15305514
MO
2414 struct afu *afu = cfg->afu;
2415 int rcr = 0;
2416
88d33628
MO
2417 dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu "
2418 "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no,
2419 scp->device->channel, scp->device->id, scp->device->lun,
2420 get_unaligned_be32(&((u32 *)scp->cmnd)[0]),
2421 get_unaligned_be32(&((u32 *)scp->cmnd)[1]),
2422 get_unaligned_be32(&((u32 *)scp->cmnd)[2]),
2423 get_unaligned_be32(&((u32 *)scp->cmnd)[3]));
15305514 2424
ed486daa 2425retry:
15305514
MO
2426 switch (cfg->state) {
2427 case STATE_NORMAL:
2428 rcr = send_tmf(afu, scp, TMF_LUN_RESET);
2429 if (unlikely(rcr))
2430 rc = FAILED;
2431 break;
2432 case STATE_RESET:
2433 wait_event(cfg->reset_waitq, cfg->state != STATE_RESET);
ed486daa 2434 goto retry;
15305514
MO
2435 default:
2436 rc = FAILED;
2437 break;
2438 }
2439
88d33628 2440 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
15305514
MO
2441 return rc;
2442}
2443
2444/**
2445 * cxlflash_eh_host_reset_handler() - reset the host adapter
2446 * @scp: SCSI command from stack identifying host.
2447 *
1d3324c3
MO
2448 * Following a reset, the state is evaluated again in case an EEH occurred
2449 * during the reset. In such a scenario, the host reset will either yield
2450 * until the EEH recovery is complete or return success or failure based
2451 * upon the current device state.
2452 *
15305514
MO
2453 * Return:
2454 * SUCCESS as defined in scsi/scsi.h
2455 * FAILED as defined in scsi/scsi.h
2456 */
2457static int cxlflash_eh_host_reset_handler(struct scsi_cmnd *scp)
2458{
2459 int rc = SUCCESS;
2460 int rcr = 0;
2461 struct Scsi_Host *host = scp->device->host;
88d33628
MO
2462 struct cxlflash_cfg *cfg = shost_priv(host);
2463 struct device *dev = &cfg->dev->dev;
15305514 2464
88d33628
MO
2465 dev_dbg(dev, "%s: (scp=%p) %d/%d/%d/%llu "
2466 "cdb=(%08x-%08x-%08x-%08x)\n", __func__, scp, host->host_no,
2467 scp->device->channel, scp->device->id, scp->device->lun,
2468 get_unaligned_be32(&((u32 *)scp->cmnd)[0]),
2469 get_unaligned_be32(&((u32 *)scp->cmnd)[1]),
2470 get_unaligned_be32(&((u32 *)scp->cmnd)[2]),
2471 get_unaligned_be32(&((u32 *)scp->cmnd)[3]));
15305514
MO
2472
2473 switch (cfg->state) {
2474 case STATE_NORMAL:
2475 cfg->state = STATE_RESET;
f411396d 2476 drain_ioctls(cfg);
15305514
MO
2477 cxlflash_mark_contexts_error(cfg);
2478 rcr = afu_reset(cfg);
2479 if (rcr) {
2480 rc = FAILED;
2481 cfg->state = STATE_FAILTERM;
2482 } else
2483 cfg->state = STATE_NORMAL;
2484 wake_up_all(&cfg->reset_waitq);
1d3324c3
MO
2485 ssleep(1);
2486 /* fall through */
15305514
MO
2487 case STATE_RESET:
2488 wait_event(cfg->reset_waitq, cfg->state != STATE_RESET);
2489 if (cfg->state == STATE_NORMAL)
2490 break;
2491 /* fall through */
2492 default:
2493 rc = FAILED;
2494 break;
2495 }
2496
88d33628 2497 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
15305514
MO
2498 return rc;
2499}
2500
2501/**
2502 * cxlflash_change_queue_depth() - change the queue depth for the device
2503 * @sdev: SCSI device destined for queue depth change.
2504 * @qdepth: Requested queue depth value to set.
2505 *
2506 * The requested queue depth is capped to the maximum supported value.
2507 *
2508 * Return: The actual queue depth set.
2509 */
2510static int cxlflash_change_queue_depth(struct scsi_device *sdev, int qdepth)
2511{
2512
2513 if (qdepth > CXLFLASH_MAX_CMDS_PER_LUN)
2514 qdepth = CXLFLASH_MAX_CMDS_PER_LUN;
2515
2516 scsi_change_queue_depth(sdev, qdepth);
2517 return sdev->queue_depth;
2518}
2519
2520/**
2521 * cxlflash_show_port_status() - queries and presents the current port status
e0f01a21 2522 * @port: Desired port for status reporting.
90c9f8f4 2523 * @cfg: Internal structure associated with the host.
15305514
MO
2524 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2525 *
66d4bce4 2526 * Return: The size of the ASCII string returned in @buf or -EINVAL.
15305514 2527 */
90c9f8f4
MO
2528static ssize_t cxlflash_show_port_status(u32 port,
2529 struct cxlflash_cfg *cfg,
2530 char *buf)
15305514 2531{
66d4bce4 2532 struct device *dev = &cfg->dev->dev;
15305514 2533 char *disp_status;
15305514 2534 u64 status;
c885d3fe 2535 __be64 __iomem *fc_port_regs;
15305514 2536
66d4bce4
MO
2537 WARN_ON(port >= MAX_FC_PORTS);
2538
2539 if (port >= cfg->num_fc_ports) {
2540 dev_info(dev, "%s: Port %d not supported on this card.\n",
2541 __func__, port);
2542 return -EINVAL;
2543 }
15305514 2544
c885d3fe
MO
2545 fc_port_regs = get_fc_port_regs(cfg, port);
2546 status = readq_be(&fc_port_regs[FC_MTIP_STATUS / 8]);
e0f01a21 2547 status &= FC_MTIP_STATUS_MASK;
15305514
MO
2548
2549 if (status == FC_MTIP_STATUS_ONLINE)
2550 disp_status = "online";
2551 else if (status == FC_MTIP_STATUS_OFFLINE)
2552 disp_status = "offline";
2553 else
2554 disp_status = "unknown";
2555
e0f01a21
MO
2556 return scnprintf(buf, PAGE_SIZE, "%s\n", disp_status);
2557}
2558
2559/**
2560 * port0_show() - queries and presents the current status of port 0
2561 * @dev: Generic device associated with the host owning the port.
2562 * @attr: Device attribute representing the port.
2563 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2564 *
2565 * Return: The size of the ASCII string returned in @buf.
2566 */
2567static ssize_t port0_show(struct device *dev,
2568 struct device_attribute *attr,
2569 char *buf)
2570{
88d33628 2571 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
e0f01a21 2572
90c9f8f4 2573 return cxlflash_show_port_status(0, cfg, buf);
15305514
MO
2574}
2575
2576/**
e0f01a21
MO
2577 * port1_show() - queries and presents the current status of port 1
2578 * @dev: Generic device associated with the host owning the port.
2579 * @attr: Device attribute representing the port.
2580 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2581 *
2582 * Return: The size of the ASCII string returned in @buf.
2583 */
2584static ssize_t port1_show(struct device *dev,
2585 struct device_attribute *attr,
2586 char *buf)
2587{
88d33628 2588 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
e0f01a21 2589
90c9f8f4 2590 return cxlflash_show_port_status(1, cfg, buf);
e0f01a21
MO
2591}
2592
bdcff1c5
MO
2593/**
2594 * port2_show() - queries and presents the current status of port 2
2595 * @dev: Generic device associated with the host owning the port.
2596 * @attr: Device attribute representing the port.
2597 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2598 *
2599 * Return: The size of the ASCII string returned in @buf.
2600 */
2601static ssize_t port2_show(struct device *dev,
2602 struct device_attribute *attr,
2603 char *buf)
2604{
2605 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2606
2607 return cxlflash_show_port_status(2, cfg, buf);
2608}
2609
2610/**
2611 * port3_show() - queries and presents the current status of port 3
2612 * @dev: Generic device associated with the host owning the port.
2613 * @attr: Device attribute representing the port.
2614 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2615 *
2616 * Return: The size of the ASCII string returned in @buf.
2617 */
2618static ssize_t port3_show(struct device *dev,
2619 struct device_attribute *attr,
2620 char *buf)
2621{
2622 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2623
2624 return cxlflash_show_port_status(3, cfg, buf);
2625}
2626
e0f01a21
MO
2627/**
2628 * lun_mode_show() - presents the current LUN mode of the host
15305514 2629 * @dev: Generic device associated with the host.
e0f01a21 2630 * @attr: Device attribute representing the LUN mode.
15305514
MO
2631 * @buf: Buffer of length PAGE_SIZE to report back the LUN mode in ASCII.
2632 *
2633 * Return: The size of the ASCII string returned in @buf.
2634 */
e0f01a21
MO
2635static ssize_t lun_mode_show(struct device *dev,
2636 struct device_attribute *attr, char *buf)
15305514 2637{
88d33628 2638 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
15305514
MO
2639 struct afu *afu = cfg->afu;
2640
e0f01a21 2641 return scnprintf(buf, PAGE_SIZE, "%u\n", afu->internal_lun);
15305514
MO
2642}
2643
2644/**
e0f01a21 2645 * lun_mode_store() - sets the LUN mode of the host
15305514 2646 * @dev: Generic device associated with the host.
e0f01a21 2647 * @attr: Device attribute representing the LUN mode.
15305514
MO
2648 * @buf: Buffer of length PAGE_SIZE containing the LUN mode in ASCII.
2649 * @count: Length of data resizing in @buf.
2650 *
2651 * The CXL Flash AFU supports a dummy LUN mode where the external
2652 * links and storage are not required. Space on the FPGA is used
2653 * to create 1 or 2 small LUNs which are presented to the system
2654 * as if they were a normal storage device. This feature is useful
2655 * during development and also provides manufacturing with a way
2656 * to test the AFU without an actual device.
2657 *
2658 * 0 = external LUN[s] (default)
2659 * 1 = internal LUN (1 x 64K, 512B blocks, id 0)
2660 * 2 = internal LUN (1 x 64K, 4K blocks, id 0)
2661 * 3 = internal LUN (2 x 32K, 512B blocks, ids 0,1)
2662 * 4 = internal LUN (2 x 32K, 4K blocks, ids 0,1)
2663 *
2664 * Return: The size of the ASCII string returned in @buf.
2665 */
e0f01a21
MO
2666static ssize_t lun_mode_store(struct device *dev,
2667 struct device_attribute *attr,
2668 const char *buf, size_t count)
15305514
MO
2669{
2670 struct Scsi_Host *shost = class_to_shost(dev);
88d33628 2671 struct cxlflash_cfg *cfg = shost_priv(shost);
15305514
MO
2672 struct afu *afu = cfg->afu;
2673 int rc;
2674 u32 lun_mode;
2675
2676 rc = kstrtouint(buf, 10, &lun_mode);
2677 if (!rc && (lun_mode < 5) && (lun_mode != afu->internal_lun)) {
2678 afu->internal_lun = lun_mode;
603ecce9
MK
2679
2680 /*
2681 * When configured for internal LUN, there is only one channel,
66d4bce4
MO
2682 * channel number 0, else there will be one less than the number
2683 * of fc ports for this card.
603ecce9
MK
2684 */
2685 if (afu->internal_lun)
2686 shost->max_channel = 0;
2687 else
e8e17ea6 2688 shost->max_channel = PORTNUM2CHAN(cfg->num_fc_ports);
603ecce9 2689
15305514
MO
2690 afu_reset(cfg);
2691 scsi_scan_host(cfg->host);
2692 }
2693
2694 return count;
2695}
2696
2697/**
e0f01a21 2698 * ioctl_version_show() - presents the current ioctl version of the host
15305514
MO
2699 * @dev: Generic device associated with the host.
2700 * @attr: Device attribute representing the ioctl version.
2701 * @buf: Buffer of length PAGE_SIZE to report back the ioctl version.
2702 *
2703 * Return: The size of the ASCII string returned in @buf.
2704 */
e0f01a21
MO
2705static ssize_t ioctl_version_show(struct device *dev,
2706 struct device_attribute *attr, char *buf)
15305514 2707{
c6ed2d7e
MO
2708 ssize_t bytes = 0;
2709
2710 bytes = scnprintf(buf, PAGE_SIZE,
2711 "disk: %u\n", DK_CXLFLASH_VERSION_0);
2712 bytes += scnprintf(buf + bytes, PAGE_SIZE - bytes,
2713 "host: %u\n", HT_CXLFLASH_VERSION_0);
2714
2715 return bytes;
15305514
MO
2716}
2717
2718/**
e0f01a21
MO
2719 * cxlflash_show_port_lun_table() - queries and presents the port LUN table
2720 * @port: Desired port for status reporting.
90c9f8f4 2721 * @cfg: Internal structure associated with the host.
e0f01a21
MO
2722 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2723 *
66d4bce4 2724 * Return: The size of the ASCII string returned in @buf or -EINVAL.
e0f01a21
MO
2725 */
2726static ssize_t cxlflash_show_port_lun_table(u32 port,
90c9f8f4 2727 struct cxlflash_cfg *cfg,
e0f01a21
MO
2728 char *buf)
2729{
66d4bce4 2730 struct device *dev = &cfg->dev->dev;
c885d3fe 2731 __be64 __iomem *fc_port_luns;
e0f01a21
MO
2732 int i;
2733 ssize_t bytes = 0;
e0f01a21 2734
66d4bce4
MO
2735 WARN_ON(port >= MAX_FC_PORTS);
2736
2737 if (port >= cfg->num_fc_ports) {
2738 dev_info(dev, "%s: Port %d not supported on this card.\n",
2739 __func__, port);
2740 return -EINVAL;
2741 }
e0f01a21 2742
c885d3fe 2743 fc_port_luns = get_fc_port_luns(cfg, port);
e0f01a21
MO
2744
2745 for (i = 0; i < CXLFLASH_NUM_VLUNS; i++)
2746 bytes += scnprintf(buf + bytes, PAGE_SIZE - bytes,
c885d3fe
MO
2747 "%03d: %016llx\n",
2748 i, readq_be(&fc_port_luns[i]));
e0f01a21
MO
2749 return bytes;
2750}
2751
2752/**
2753 * port0_lun_table_show() - presents the current LUN table of port 0
2754 * @dev: Generic device associated with the host owning the port.
2755 * @attr: Device attribute representing the port.
2756 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2757 *
2758 * Return: The size of the ASCII string returned in @buf.
2759 */
2760static ssize_t port0_lun_table_show(struct device *dev,
2761 struct device_attribute *attr,
2762 char *buf)
2763{
88d33628 2764 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
e0f01a21 2765
90c9f8f4 2766 return cxlflash_show_port_lun_table(0, cfg, buf);
e0f01a21
MO
2767}
2768
2769/**
2770 * port1_lun_table_show() - presents the current LUN table of port 1
2771 * @dev: Generic device associated with the host owning the port.
2772 * @attr: Device attribute representing the port.
2773 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2774 *
2775 * Return: The size of the ASCII string returned in @buf.
2776 */
2777static ssize_t port1_lun_table_show(struct device *dev,
2778 struct device_attribute *attr,
2779 char *buf)
2780{
88d33628 2781 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
e0f01a21 2782
90c9f8f4 2783 return cxlflash_show_port_lun_table(1, cfg, buf);
e0f01a21
MO
2784}
2785
bdcff1c5
MO
2786/**
2787 * port2_lun_table_show() - presents the current LUN table of port 2
2788 * @dev: Generic device associated with the host owning the port.
2789 * @attr: Device attribute representing the port.
2790 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2791 *
2792 * Return: The size of the ASCII string returned in @buf.
2793 */
2794static ssize_t port2_lun_table_show(struct device *dev,
2795 struct device_attribute *attr,
2796 char *buf)
2797{
2798 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2799
2800 return cxlflash_show_port_lun_table(2, cfg, buf);
2801}
2802
2803/**
2804 * port3_lun_table_show() - presents the current LUN table of port 3
2805 * @dev: Generic device associated with the host owning the port.
2806 * @attr: Device attribute representing the port.
2807 * @buf: Buffer of length PAGE_SIZE to report back port status in ASCII.
2808 *
2809 * Return: The size of the ASCII string returned in @buf.
2810 */
2811static ssize_t port3_lun_table_show(struct device *dev,
2812 struct device_attribute *attr,
2813 char *buf)
2814{
2815 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2816
2817 return cxlflash_show_port_lun_table(3, cfg, buf);
2818}
2819
2588f222
MO
2820/**
2821 * irqpoll_weight_show() - presents the current IRQ poll weight for the host
2822 * @dev: Generic device associated with the host.
2823 * @attr: Device attribute representing the IRQ poll weight.
2824 * @buf: Buffer of length PAGE_SIZE to report back the current IRQ poll
2825 * weight in ASCII.
2826 *
2827 * An IRQ poll weight of 0 indicates polling is disabled.
2828 *
2829 * Return: The size of the ASCII string returned in @buf.
2830 */
2831static ssize_t irqpoll_weight_show(struct device *dev,
2832 struct device_attribute *attr, char *buf)
2833{
2834 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2835 struct afu *afu = cfg->afu;
2836
2837 return scnprintf(buf, PAGE_SIZE, "%u\n", afu->irqpoll_weight);
2838}
2839
2840/**
2841 * irqpoll_weight_store() - sets the current IRQ poll weight for the host
2842 * @dev: Generic device associated with the host.
2843 * @attr: Device attribute representing the IRQ poll weight.
2844 * @buf: Buffer of length PAGE_SIZE containing the desired IRQ poll
2845 * weight in ASCII.
2846 * @count: Length of data resizing in @buf.
2847 *
2848 * An IRQ poll weight of 0 indicates polling is disabled.
2849 *
2850 * Return: The size of the ASCII string returned in @buf.
2851 */
2852static ssize_t irqpoll_weight_store(struct device *dev,
2853 struct device_attribute *attr,
2854 const char *buf, size_t count)
2855{
2856 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2857 struct device *cfgdev = &cfg->dev->dev;
2858 struct afu *afu = cfg->afu;
a583d00a 2859 struct hwq *hwq;
2588f222 2860 u32 weight;
a583d00a 2861 int rc, i;
2588f222
MO
2862
2863 rc = kstrtouint(buf, 10, &weight);
2864 if (rc)
2865 return -EINVAL;
2866
2867 if (weight > 256) {
2868 dev_info(cfgdev,
2869 "Invalid IRQ poll weight. It must be 256 or less.\n");
2870 return -EINVAL;
2871 }
2872
2873 if (weight == afu->irqpoll_weight) {
2874 dev_info(cfgdev,
2875 "Current IRQ poll weight has the same weight.\n");
2876 return -EINVAL;
2877 }
2878
a583d00a 2879 if (afu_is_irqpoll_enabled(afu)) {
bb85ef68 2880 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
2881 hwq = get_hwq(afu, i);
2882
2883 irq_poll_disable(&hwq->irqpoll);
2884 }
2885 }
2588f222
MO
2886
2887 afu->irqpoll_weight = weight;
2888
a583d00a 2889 if (weight > 0) {
bb85ef68 2890 for (i = 0; i < afu->num_hwqs; i++) {
a583d00a
UK
2891 hwq = get_hwq(afu, i);
2892
2893 irq_poll_init(&hwq->irqpoll, weight, cxlflash_irqpoll);
2894 }
2895 }
2588f222
MO
2896
2897 return count;
2898}
2899
bb85ef68
MO
2900/**
2901 * num_hwqs_show() - presents the number of hardware queues for the host
2902 * @dev: Generic device associated with the host.
2903 * @attr: Device attribute representing the number of hardware queues.
2904 * @buf: Buffer of length PAGE_SIZE to report back the number of hardware
2905 * queues in ASCII.
2906 *
2907 * Return: The size of the ASCII string returned in @buf.
2908 */
2909static ssize_t num_hwqs_show(struct device *dev,
2910 struct device_attribute *attr, char *buf)
2911{
2912 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2913 struct afu *afu = cfg->afu;
2914
2915 return scnprintf(buf, PAGE_SIZE, "%u\n", afu->num_hwqs);
2916}
2917
2918/**
2919 * num_hwqs_store() - sets the number of hardware queues for the host
2920 * @dev: Generic device associated with the host.
2921 * @attr: Device attribute representing the number of hardware queues.
2922 * @buf: Buffer of length PAGE_SIZE containing the number of hardware
2923 * queues in ASCII.
2924 * @count: Length of data resizing in @buf.
2925 *
2926 * n > 0: num_hwqs = n
2927 * n = 0: num_hwqs = num_online_cpus()
2928 * n < 0: num_online_cpus() / abs(n)
2929 *
2930 * Return: The size of the ASCII string returned in @buf.
2931 */
2932static ssize_t num_hwqs_store(struct device *dev,
2933 struct device_attribute *attr,
2934 const char *buf, size_t count)
2935{
2936 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2937 struct afu *afu = cfg->afu;
2938 int rc;
2939 int nhwqs, num_hwqs;
2940
2941 rc = kstrtoint(buf, 10, &nhwqs);
2942 if (rc)
2943 return -EINVAL;
2944
2945 if (nhwqs >= 1)
2946 num_hwqs = nhwqs;
2947 else if (nhwqs == 0)
2948 num_hwqs = num_online_cpus();
2949 else
2950 num_hwqs = num_online_cpus() / abs(nhwqs);
2951
2952 afu->desired_hwqs = min(num_hwqs, CXLFLASH_MAX_HWQS);
2953 WARN_ON_ONCE(afu->desired_hwqs == 0);
2954
2955retry:
2956 switch (cfg->state) {
2957 case STATE_NORMAL:
2958 cfg->state = STATE_RESET;
2959 drain_ioctls(cfg);
2960 cxlflash_mark_contexts_error(cfg);
2961 rc = afu_reset(cfg);
2962 if (rc)
2963 cfg->state = STATE_FAILTERM;
2964 else
2965 cfg->state = STATE_NORMAL;
2966 wake_up_all(&cfg->reset_waitq);
2967 break;
2968 case STATE_RESET:
2969 wait_event(cfg->reset_waitq, cfg->state != STATE_RESET);
2970 if (cfg->state == STATE_NORMAL)
2971 goto retry;
2972 default:
2973 /* Ideally should not happen */
2974 dev_err(dev, "%s: Device is not ready, state=%d\n",
2975 __func__, cfg->state);
2976 break;
2977 }
2978
2979 return count;
2980}
2981
8c052e9e
MO
2982static const char *hwq_mode_name[MAX_HWQ_MODE] = { "rr", "tag", "cpu" };
2983
2984/**
2985 * hwq_mode_show() - presents the HWQ steering mode for the host
2986 * @dev: Generic device associated with the host.
2987 * @attr: Device attribute representing the HWQ steering mode.
2988 * @buf: Buffer of length PAGE_SIZE to report back the HWQ steering mode
2989 * as a character string.
2990 *
2991 * Return: The size of the ASCII string returned in @buf.
2992 */
2993static ssize_t hwq_mode_show(struct device *dev,
2994 struct device_attribute *attr, char *buf)
2995{
2996 struct cxlflash_cfg *cfg = shost_priv(class_to_shost(dev));
2997 struct afu *afu = cfg->afu;
2998
2999 return scnprintf(buf, PAGE_SIZE, "%s\n", hwq_mode_name[afu->hwq_mode]);
3000}
3001
3002/**
3003 * hwq_mode_store() - sets the HWQ steering mode for the host
3004 * @dev: Generic device associated with the host.
3005 * @attr: Device attribute representing the HWQ steering mode.
3006 * @buf: Buffer of length PAGE_SIZE containing the HWQ steering mode
3007 * as a character string.
3008 * @count: Length of data resizing in @buf.
3009 *
3010 * rr = Round-Robin
3011 * tag = Block MQ Tagging
3012 * cpu = CPU Affinity
3013 *
3014 * Return: The size of the ASCII string returned in @buf.
3015 */
3016static ssize_t hwq_mode_store(struct device *dev,
3017 struct device_attribute *attr,
3018 const char *buf, size_t count)
3019{
3020 struct Scsi_Host *shost = class_to_shost(dev);
3021 struct cxlflash_cfg *cfg = shost_priv(shost);
3022 struct device *cfgdev = &cfg->dev->dev;
3023 struct afu *afu = cfg->afu;
3024 int i;
3025 u32 mode = MAX_HWQ_MODE;
3026
3027 for (i = 0; i < MAX_HWQ_MODE; i++) {
3028 if (!strncmp(hwq_mode_name[i], buf, strlen(hwq_mode_name[i]))) {
3029 mode = i;
3030 break;
3031 }
3032 }
3033
3034 if (mode >= MAX_HWQ_MODE) {
3035 dev_info(cfgdev, "Invalid HWQ steering mode.\n");
3036 return -EINVAL;
3037 }
3038
3039 if ((mode == HWQ_MODE_TAG) && !shost_use_blk_mq(shost)) {
3040 dev_info(cfgdev, "SCSI-MQ is not enabled, use a different "
3041 "HWQ steering mode.\n");
3042 return -EINVAL;
3043 }
3044
3045 afu->hwq_mode = mode;
3046
3047 return count;
3048}
3049
e0f01a21
MO
3050/**
3051 * mode_show() - presents the current mode of the device
15305514
MO
3052 * @dev: Generic device associated with the device.
3053 * @attr: Device attribute representing the device mode.
3054 * @buf: Buffer of length PAGE_SIZE to report back the dev mode in ASCII.
3055 *
3056 * Return: The size of the ASCII string returned in @buf.
3057 */
e0f01a21
MO
3058static ssize_t mode_show(struct device *dev,
3059 struct device_attribute *attr, char *buf)
15305514
MO
3060{
3061 struct scsi_device *sdev = to_scsi_device(dev);
3062
e0f01a21
MO
3063 return scnprintf(buf, PAGE_SIZE, "%s\n",
3064 sdev->hostdata ? "superpipe" : "legacy");
15305514
MO
3065}
3066
3067/*
3068 * Host attributes
3069 */
e0f01a21
MO
3070static DEVICE_ATTR_RO(port0);
3071static DEVICE_ATTR_RO(port1);
bdcff1c5
MO
3072static DEVICE_ATTR_RO(port2);
3073static DEVICE_ATTR_RO(port3);
e0f01a21
MO
3074static DEVICE_ATTR_RW(lun_mode);
3075static DEVICE_ATTR_RO(ioctl_version);
3076static DEVICE_ATTR_RO(port0_lun_table);
3077static DEVICE_ATTR_RO(port1_lun_table);
bdcff1c5
MO
3078static DEVICE_ATTR_RO(port2_lun_table);
3079static DEVICE_ATTR_RO(port3_lun_table);
2588f222 3080static DEVICE_ATTR_RW(irqpoll_weight);
bb85ef68 3081static DEVICE_ATTR_RW(num_hwqs);
8c052e9e 3082static DEVICE_ATTR_RW(hwq_mode);
15305514
MO
3083
3084static struct device_attribute *cxlflash_host_attrs[] = {
3085 &dev_attr_port0,
3086 &dev_attr_port1,
bdcff1c5
MO
3087 &dev_attr_port2,
3088 &dev_attr_port3,
15305514
MO
3089 &dev_attr_lun_mode,
3090 &dev_attr_ioctl_version,
e0f01a21
MO
3091 &dev_attr_port0_lun_table,
3092 &dev_attr_port1_lun_table,
bdcff1c5
MO
3093 &dev_attr_port2_lun_table,
3094 &dev_attr_port3_lun_table,
2588f222 3095 &dev_attr_irqpoll_weight,
bb85ef68 3096 &dev_attr_num_hwqs,
8c052e9e 3097 &dev_attr_hwq_mode,
15305514
MO
3098 NULL
3099};
3100
3101/*
3102 * Device attributes
3103 */
e0f01a21 3104static DEVICE_ATTR_RO(mode);
15305514
MO
3105
3106static struct device_attribute *cxlflash_dev_attrs[] = {
3107 &dev_attr_mode,
3108 NULL
3109};
3110
3111/*
3112 * Host template
3113 */
3114static struct scsi_host_template driver_template = {
3115 .module = THIS_MODULE,
3116 .name = CXLFLASH_ADAPTER_NAME,
3117 .info = cxlflash_driver_info,
3118 .ioctl = cxlflash_ioctl,
3119 .proc_name = CXLFLASH_NAME,
3120 .queuecommand = cxlflash_queuecommand,
4ab47257 3121 .eh_abort_handler = cxlflash_eh_abort_handler,
15305514
MO
3122 .eh_device_reset_handler = cxlflash_eh_device_reset_handler,
3123 .eh_host_reset_handler = cxlflash_eh_host_reset_handler,
3124 .change_queue_depth = cxlflash_change_queue_depth,
83430833 3125 .cmd_per_lun = CXLFLASH_MAX_CMDS_PER_LUN,
15305514 3126 .can_queue = CXLFLASH_MAX_CMDS,
5fbb96c8 3127 .cmd_size = sizeof(struct afu_cmd) + __alignof__(struct afu_cmd) - 1,
15305514 3128 .this_id = -1,
68ab2d76 3129 .sg_tablesize = 1, /* No scatter gather support */
15305514
MO
3130 .max_sectors = CXLFLASH_MAX_SECTORS,
3131 .use_clustering = ENABLE_CLUSTERING,
3132 .shost_attrs = cxlflash_host_attrs,
3133 .sdev_attrs = cxlflash_dev_attrs,
3134};
3135
3136/*
3137 * Device dependent values
3138 */
96e1b660
UK
3139static struct dev_dependent_vals dev_corsa_vals = { CXLFLASH_MAX_SECTORS,
3140 0ULL };
3141static struct dev_dependent_vals dev_flash_gt_vals = { CXLFLASH_MAX_SECTORS,
704c4b0d 3142 CXLFLASH_NOTIFY_SHUTDOWN };
42f90a6b
MO
3143static struct dev_dependent_vals dev_briard_vals = { CXLFLASH_MAX_SECTORS,
3144 CXLFLASH_NOTIFY_SHUTDOWN };
15305514
MO
3145
3146/*
3147 * PCI device binding table
3148 */
3149static struct pci_device_id cxlflash_pci_table[] = {
3150 {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CORSA,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_corsa_vals},
a2746fb1
MK
3152 {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_FLASH_GT,
3153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_flash_gt_vals},
42f90a6b
MO
3154 {PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_BRIARD,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&dev_briard_vals},
15305514
MO
3156 {}
3157};
3158
3159MODULE_DEVICE_TABLE(pci, cxlflash_pci_table);
3160
c21e0bbf
MO
3161/**
3162 * cxlflash_worker_thread() - work thread handler for the AFU
3163 * @work: Work structure contained within cxlflash associated with host.
3164 *
3165 * Handles the following events:
3166 * - Link reset which cannot be performed on interrupt context due to
3167 * blocking up to a few seconds
ef51074a 3168 * - Rescan the host
c21e0bbf
MO
3169 */
3170static void cxlflash_worker_thread(struct work_struct *work)
3171{
5cdac81a
MO
3172 struct cxlflash_cfg *cfg = container_of(work, struct cxlflash_cfg,
3173 work_q);
c21e0bbf 3174 struct afu *afu = cfg->afu;
4392ba49 3175 struct device *dev = &cfg->dev->dev;
c885d3fe 3176 __be64 __iomem *fc_port_regs;
c21e0bbf
MO
3177 int port;
3178 ulong lock_flags;
3179
5cdac81a
MO
3180 /* Avoid MMIO if the device has failed */
3181
3182 if (cfg->state != STATE_NORMAL)
3183 return;
3184
c21e0bbf
MO
3185 spin_lock_irqsave(cfg->host->host_lock, lock_flags);
3186
3187 if (cfg->lr_state == LINK_RESET_REQUIRED) {
3188 port = cfg->lr_port;
3189 if (port < 0)
4392ba49
MO
3190 dev_err(dev, "%s: invalid port index %d\n",
3191 __func__, port);
c21e0bbf
MO
3192 else {
3193 spin_unlock_irqrestore(cfg->host->host_lock,
3194 lock_flags);
3195
3196 /* The reset can block... */
c885d3fe
MO
3197 fc_port_regs = get_fc_port_regs(cfg, port);
3198 afu_link_reset(afu, port, fc_port_regs);
c21e0bbf
MO
3199 spin_lock_irqsave(cfg->host->host_lock, lock_flags);
3200 }
3201
3202 cfg->lr_state = LINK_RESET_COMPLETE;
3203 }
3204
c21e0bbf 3205 spin_unlock_irqrestore(cfg->host->host_lock, lock_flags);
ef51074a
MO
3206
3207 if (atomic_dec_if_positive(&cfg->scan_host_needed) >= 0)
3208 scsi_scan_host(cfg->host);
c21e0bbf
MO
3209}
3210
f3d79b3e
UK
3211/**
3212 * cxlflash_chr_open() - character device open handler
3213 * @inode: Device inode associated with this character device.
3214 * @file: File pointer for this device.
3215 *
3216 * Only users with admin privileges are allowed to open the character device.
3217 *
3218 * Return: 0 on success, -errno on failure
3219 */
3220static int cxlflash_chr_open(struct inode *inode, struct file *file)
3221{
3222 struct cxlflash_cfg *cfg;
3223
3224 if (!capable(CAP_SYS_ADMIN))
3225 return -EACCES;
3226
3227 cfg = container_of(inode->i_cdev, struct cxlflash_cfg, cdev);
3228 file->private_data = cfg;
3229
3230 return 0;
3231}
3232
c6ed2d7e
MO
3233/**
3234 * decode_hioctl() - translates encoded host ioctl to easily identifiable string
3235 * @cmd: The host ioctl command to decode.
3236 *
3237 * Return: A string identifying the decoded host ioctl.
3238 */
3239static char *decode_hioctl(int cmd)
3240{
3241 switch (cmd) {
1f829583
MO
3242 case HT_CXLFLASH_LUN_PROVISION:
3243 return __stringify_1(HT_CXLFLASH_LUN_PROVISION);
c6ed2d7e
MO
3244 }
3245
3246 return "UNKNOWN";
3247}
3248
1f829583
MO
3249/**
3250 * cxlflash_lun_provision() - host LUN provisioning handler
3251 * @cfg: Internal structure associated with the host.
3252 * @arg: Kernel copy of userspace ioctl data structure.
3253 *
3254 * Return: 0 on success, -errno on failure
3255 */
3256static int cxlflash_lun_provision(struct cxlflash_cfg *cfg,
3257 struct ht_cxlflash_lun_provision *lunprov)
3258{
3259 struct afu *afu = cfg->afu;
3260 struct device *dev = &cfg->dev->dev;
3261 struct sisl_ioarcb rcb;
3262 struct sisl_ioasa asa;
3263 __be64 __iomem *fc_port_regs;
3264 u16 port = lunprov->port;
3265 u16 scmd = lunprov->hdr.subcmd;
3266 u16 type;
3267 u64 reg;
3268 u64 size;
3269 u64 lun_id;
3270 int rc = 0;
3271
3272 if (!afu_is_lun_provision(afu)) {
3273 rc = -ENOTSUPP;
3274 goto out;
3275 }
3276
3277 if (port >= cfg->num_fc_ports) {
3278 rc = -EINVAL;
3279 goto out;
3280 }
3281
3282 switch (scmd) {
3283 case HT_CXLFLASH_LUN_PROVISION_SUBCMD_CREATE_LUN:
3284 type = SISL_AFU_LUN_PROVISION_CREATE;
3285 size = lunprov->size;
3286 lun_id = 0;
3287 break;
3288 case HT_CXLFLASH_LUN_PROVISION_SUBCMD_DELETE_LUN:
3289 type = SISL_AFU_LUN_PROVISION_DELETE;
3290 size = 0;
3291 lun_id = lunprov->lun_id;
3292 break;
3293 case HT_CXLFLASH_LUN_PROVISION_SUBCMD_QUERY_PORT:
3294 fc_port_regs = get_fc_port_regs(cfg, port);
3295
3296 reg = readq_be(&fc_port_regs[FC_MAX_NUM_LUNS / 8]);
3297 lunprov->max_num_luns = reg;
3298 reg = readq_be(&fc_port_regs[FC_CUR_NUM_LUNS / 8]);
3299 lunprov->cur_num_luns = reg;
3300 reg = readq_be(&fc_port_regs[FC_MAX_CAP_PORT / 8]);
3301 lunprov->max_cap_port = reg;
3302 reg = readq_be(&fc_port_regs[FC_CUR_CAP_PORT / 8]);
3303 lunprov->cur_cap_port = reg;
3304
3305 goto out;
3306 default:
3307 rc = -EINVAL;
3308 goto out;
3309 }
3310
3311 memset(&rcb, 0, sizeof(rcb));
3312 memset(&asa, 0, sizeof(asa));
3313 rcb.req_flags = SISL_REQ_FLAGS_AFU_CMD;
3314 rcb.lun_id = lun_id;
3315 rcb.msi = SISL_MSI_RRQ_UPDATED;
3316 rcb.timeout = MC_LUN_PROV_TIMEOUT;
3317 rcb.ioasa = &asa;
3318
3319 rcb.cdb[0] = SISL_AFU_CMD_LUN_PROVISION;
3320 rcb.cdb[1] = type;
3321 rcb.cdb[2] = port;
3322 put_unaligned_be64(size, &rcb.cdb[8]);
3323
3324 rc = send_afu_cmd(afu, &rcb);
3325 if (rc) {
3326 dev_err(dev, "%s: send_afu_cmd failed rc=%d asc=%08x afux=%x\n",
3327 __func__, rc, asa.ioasc, asa.afu_extra);
3328 goto out;
3329 }
3330
3331 if (scmd == HT_CXLFLASH_LUN_PROVISION_SUBCMD_CREATE_LUN) {
3332 lunprov->lun_id = (u64)asa.lunid_hi << 32 | asa.lunid_lo;
3333 memcpy(lunprov->wwid, asa.wwid, sizeof(lunprov->wwid));
3334 }
3335out:
3336 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
3337 return rc;
3338}
3339
d3c606a7
MO
3340/**
3341 * cxlflash_afu_debug() - host AFU debug handler
3342 * @cfg: Internal structure associated with the host.
3343 * @arg: Kernel copy of userspace ioctl data structure.
3344 *
3345 * For debug requests requiring a data buffer, always provide an aligned
3346 * (cache line) buffer to the AFU to appease any alignment requirements.
3347 *
3348 * Return: 0 on success, -errno on failure
3349 */
3350static int cxlflash_afu_debug(struct cxlflash_cfg *cfg,
3351 struct ht_cxlflash_afu_debug *afu_dbg)
3352{
3353 struct afu *afu = cfg->afu;
3354 struct device *dev = &cfg->dev->dev;
3355 struct sisl_ioarcb rcb;
3356 struct sisl_ioasa asa;
3357 char *buf = NULL;
3358 char *kbuf = NULL;
3359 void __user *ubuf = (__force void __user *)afu_dbg->data_ea;
3360 u16 req_flags = SISL_REQ_FLAGS_AFU_CMD;
3361 u32 ulen = afu_dbg->data_len;
3362 bool is_write = afu_dbg->hdr.flags & HT_CXLFLASH_HOST_WRITE;
3363 int rc = 0;
3364
3365 if (!afu_is_afu_debug(afu)) {
3366 rc = -ENOTSUPP;
3367 goto out;
3368 }
3369
3370 if (ulen) {
3371 req_flags |= SISL_REQ_FLAGS_SUP_UNDERRUN;
3372
3373 if (ulen > HT_CXLFLASH_AFU_DEBUG_MAX_DATA_LEN) {
3374 rc = -EINVAL;
3375 goto out;
3376 }
3377
3378 if (unlikely(!access_ok(is_write ? VERIFY_READ : VERIFY_WRITE,
3379 ubuf, ulen))) {
3380 rc = -EFAULT;
3381 goto out;
3382 }
3383
3384 buf = kmalloc(ulen + cache_line_size() - 1, GFP_KERNEL);
3385 if (unlikely(!buf)) {
3386 rc = -ENOMEM;
3387 goto out;
3388 }
3389
3390 kbuf = PTR_ALIGN(buf, cache_line_size());
3391
3392 if (is_write) {
3393 req_flags |= SISL_REQ_FLAGS_HOST_WRITE;
3394
3395 rc = copy_from_user(kbuf, ubuf, ulen);
3396 if (unlikely(rc))
3397 goto out;
3398 }
3399 }
3400
3401 memset(&rcb, 0, sizeof(rcb));
3402 memset(&asa, 0, sizeof(asa));
3403
3404 rcb.req_flags = req_flags;
3405 rcb.msi = SISL_MSI_RRQ_UPDATED;
3406 rcb.timeout = MC_AFU_DEBUG_TIMEOUT;
3407 rcb.ioasa = &asa;
3408
3409 if (ulen) {
3410 rcb.data_len = ulen;
3411 rcb.data_ea = (uintptr_t)kbuf;
3412 }
3413
3414 rcb.cdb[0] = SISL_AFU_CMD_DEBUG;
3415 memcpy(&rcb.cdb[4], afu_dbg->afu_subcmd,
3416 HT_CXLFLASH_AFU_DEBUG_SUBCMD_LEN);
3417
3418 rc = send_afu_cmd(afu, &rcb);
3419 if (rc) {
3420 dev_err(dev, "%s: send_afu_cmd failed rc=%d asc=%08x afux=%x\n",
3421 __func__, rc, asa.ioasc, asa.afu_extra);
3422 goto out;
3423 }
3424
3425 if (ulen && !is_write)
3426 rc = copy_to_user(ubuf, kbuf, ulen);
3427out:
3428 kfree(buf);
3429 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
3430 return rc;
3431}
3432
c6ed2d7e
MO
3433/**
3434 * cxlflash_chr_ioctl() - character device IOCTL handler
3435 * @file: File pointer for this device.
3436 * @cmd: IOCTL command.
3437 * @arg: Userspace ioctl data structure.
3438 *
3439 * A read/write semaphore is used to implement a 'drain' of currently
3440 * running ioctls. The read semaphore is taken at the beginning of each
3441 * ioctl thread and released upon concluding execution. Additionally the
3442 * semaphore should be released and then reacquired in any ioctl execution
3443 * path which will wait for an event to occur that is outside the scope of
3444 * the ioctl (i.e. an adapter reset). To drain the ioctls currently running,
3445 * a thread simply needs to acquire the write semaphore.
3446 *
3447 * Return: 0 on success, -errno on failure
3448 */
3449static long cxlflash_chr_ioctl(struct file *file, unsigned int cmd,
3450 unsigned long arg)
3451{
3452 typedef int (*hioctl) (struct cxlflash_cfg *, void *);
3453
3454 struct cxlflash_cfg *cfg = file->private_data;
3455 struct device *dev = &cfg->dev->dev;
3456 char buf[sizeof(union cxlflash_ht_ioctls)];
3457 void __user *uarg = (void __user *)arg;
3458 struct ht_cxlflash_hdr *hdr;
3459 size_t size = 0;
3460 bool known_ioctl = false;
3461 int idx = 0;
3462 int rc = 0;
3463 hioctl do_ioctl = NULL;
3464
3465 static const struct {
3466 size_t size;
3467 hioctl ioctl;
3468 } ioctl_tbl[] = { /* NOTE: order matters here */
1f829583
MO
3469 { sizeof(struct ht_cxlflash_lun_provision),
3470 (hioctl)cxlflash_lun_provision },
d3c606a7
MO
3471 { sizeof(struct ht_cxlflash_afu_debug),
3472 (hioctl)cxlflash_afu_debug },
c6ed2d7e
MO
3473 };
3474
3475 /* Hold read semaphore so we can drain if needed */
3476 down_read(&cfg->ioctl_rwsem);
3477
3478 dev_dbg(dev, "%s: cmd=%u idx=%d tbl_size=%lu\n",
3479 __func__, cmd, idx, sizeof(ioctl_tbl));
3480
3481 switch (cmd) {
1f829583 3482 case HT_CXLFLASH_LUN_PROVISION:
d3c606a7 3483 case HT_CXLFLASH_AFU_DEBUG:
1f829583
MO
3484 known_ioctl = true;
3485 idx = _IOC_NR(HT_CXLFLASH_LUN_PROVISION) - _IOC_NR(cmd);
3486 size = ioctl_tbl[idx].size;
3487 do_ioctl = ioctl_tbl[idx].ioctl;
3488
3489 if (likely(do_ioctl))
3490 break;
3491
3492 /* fall through */
c6ed2d7e
MO
3493 default:
3494 rc = -EINVAL;
3495 goto out;
3496 }
3497
3498 if (unlikely(copy_from_user(&buf, uarg, size))) {
3499 dev_err(dev, "%s: copy_from_user() fail "
3500 "size=%lu cmd=%d (%s) uarg=%p\n",
3501 __func__, size, cmd, decode_hioctl(cmd), uarg);
3502 rc = -EFAULT;
3503 goto out;
3504 }
3505
3506 hdr = (struct ht_cxlflash_hdr *)&buf;
3507 if (hdr->version != HT_CXLFLASH_VERSION_0) {
3508 dev_dbg(dev, "%s: Version %u not supported for %s\n",
3509 __func__, hdr->version, decode_hioctl(cmd));
3510 rc = -EINVAL;
3511 goto out;
3512 }
3513
3514 if (hdr->rsvd[0] || hdr->rsvd[1] || hdr->return_flags) {
3515 dev_dbg(dev, "%s: Reserved/rflags populated\n", __func__);
3516 rc = -EINVAL;
3517 goto out;
3518 }
3519
3520 rc = do_ioctl(cfg, (void *)&buf);
3521 if (likely(!rc))
3522 if (unlikely(copy_to_user(uarg, &buf, size))) {
3523 dev_err(dev, "%s: copy_to_user() fail "
3524 "size=%lu cmd=%d (%s) uarg=%p\n",
3525 __func__, size, cmd, decode_hioctl(cmd), uarg);
3526 rc = -EFAULT;
3527 }
3528
3529 /* fall through to exit */
3530
3531out:
3532 up_read(&cfg->ioctl_rwsem);
3533 if (unlikely(rc && known_ioctl))
3534 dev_err(dev, "%s: ioctl %s (%08X) returned rc=%d\n",
3535 __func__, decode_hioctl(cmd), cmd, rc);
3536 else
3537 dev_dbg(dev, "%s: ioctl %s (%08X) returned rc=%d\n",
3538 __func__, decode_hioctl(cmd), cmd, rc);
3539 return rc;
3540}
3541
f3d79b3e
UK
3542/*
3543 * Character device file operations
3544 */
3545static const struct file_operations cxlflash_chr_fops = {
3546 .owner = THIS_MODULE,
3547 .open = cxlflash_chr_open,
c6ed2d7e
MO
3548 .unlocked_ioctl = cxlflash_chr_ioctl,
3549 .compat_ioctl = cxlflash_chr_ioctl,
f3d79b3e
UK
3550};
3551
3552/**
3553 * init_chrdev() - initialize the character device for the host
3554 * @cfg: Internal structure associated with the host.
3555 *
3556 * Return: 0 on success, -errno on failure
3557 */
3558static int init_chrdev(struct cxlflash_cfg *cfg)
3559{
3560 struct device *dev = &cfg->dev->dev;
3561 struct device *char_dev;
3562 dev_t devno;
3563 int minor;
3564 int rc = 0;
3565
3566 minor = cxlflash_get_minor();
3567 if (unlikely(minor < 0)) {
3568 dev_err(dev, "%s: Exhausted allowed adapters\n", __func__);
3569 rc = -ENOSPC;
3570 goto out;
3571 }
3572
3573 devno = MKDEV(cxlflash_major, minor);
3574 cdev_init(&cfg->cdev, &cxlflash_chr_fops);
3575
3576 rc = cdev_add(&cfg->cdev, devno, 1);
3577 if (rc) {
3578 dev_err(dev, "%s: cdev_add failed rc=%d\n", __func__, rc);
3579 goto err1;
3580 }
3581
3582 char_dev = device_create(cxlflash_class, NULL, devno,
3583 NULL, "cxlflash%d", minor);
3584 if (IS_ERR(char_dev)) {
3585 rc = PTR_ERR(char_dev);
3586 dev_err(dev, "%s: device_create failed rc=%d\n",
3587 __func__, rc);
3588 goto err2;
3589 }
3590
3591 cfg->chardev = char_dev;
3592out:
3593 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
3594 return rc;
3595err2:
3596 cdev_del(&cfg->cdev);
3597err1:
3598 cxlflash_put_minor(minor);
3599 goto out;
3600}
3601
c21e0bbf
MO
3602/**
3603 * cxlflash_probe() - PCI entry point to add host
3604 * @pdev: PCI device associated with the host.
3605 * @dev_id: PCI device id associated with device.
3606 *
f92ba507
MO
3607 * The device will initially start out in a 'probing' state and
3608 * transition to the 'normal' state at the end of a successful
3609 * probe. Should an EEH event occur during probe, the notification
3610 * thread (error_detected()) will wait until the probe handler
3611 * is nearly complete. At that time, the device will be moved to
3612 * a 'probed' state and the EEH thread woken up to drive the slot
3613 * reset and recovery (device moves to 'normal' state). Meanwhile,
3614 * the probe will be allowed to exit successfully.
3615 *
1284fb0c 3616 * Return: 0 on success, -errno on failure
c21e0bbf
MO
3617 */
3618static int cxlflash_probe(struct pci_dev *pdev,
3619 const struct pci_device_id *dev_id)
3620{
3621 struct Scsi_Host *host;
3622 struct cxlflash_cfg *cfg = NULL;
88d33628 3623 struct device *dev = &pdev->dev;
c21e0bbf
MO
3624 struct dev_dependent_vals *ddv;
3625 int rc = 0;
66d4bce4 3626 int k;
c21e0bbf
MO
3627
3628 dev_dbg(&pdev->dev, "%s: Found CXLFLASH with IRQ: %d\n",
3629 __func__, pdev->irq);
3630
3631 ddv = (struct dev_dependent_vals *)dev_id->driver_data;
3632 driver_template.max_sectors = ddv->max_sectors;
3633
3634 host = scsi_host_alloc(&driver_template, sizeof(struct cxlflash_cfg));
3635 if (!host) {
88d33628 3636 dev_err(dev, "%s: scsi_host_alloc failed\n", __func__);
c21e0bbf
MO
3637 rc = -ENOMEM;
3638 goto out;
3639 }
3640
3641 host->max_id = CXLFLASH_MAX_NUM_TARGETS_PER_BUS;
3642 host->max_lun = CXLFLASH_MAX_NUM_LUNS_PER_TARGET;
c21e0bbf
MO
3643 host->unique_id = host->host_no;
3644 host->max_cmd_len = CXLFLASH_MAX_CDB_LEN;
3645
88d33628 3646 cfg = shost_priv(host);
c21e0bbf
MO
3647 cfg->host = host;
3648 rc = alloc_mem(cfg);
3649 if (rc) {
88d33628 3650 dev_err(dev, "%s: alloc_mem failed\n", __func__);
c21e0bbf 3651 rc = -ENOMEM;
8b5b1e87 3652 scsi_host_put(cfg->host);
c21e0bbf
MO
3653 goto out;
3654 }
3655
3656 cfg->init_state = INIT_STATE_NONE;
3657 cfg->dev = pdev;
17ead26f 3658 cfg->cxl_fops = cxlflash_cxl_fops;
2cb79266
MO
3659
3660 /*
66d4bce4
MO
3661 * Promoted LUNs move to the top of the LUN table. The rest stay on
3662 * the bottom half. The bottom half grows from the end (index = 255),
3663 * whereas the top half grows from the beginning (index = 0).
3664 *
3665 * Initialize the last LUN index for all possible ports.
2cb79266 3666 */
66d4bce4
MO
3667 cfg->promote_lun_index = 0;
3668
3669 for (k = 0; k < MAX_FC_PORTS; k++)
3670 cfg->last_lun_index[k] = CXLFLASH_NUM_VLUNS/2 - 1;
2cb79266 3671
c21e0bbf 3672 cfg->dev_id = (struct pci_device_id *)dev_id;
c21e0bbf
MO
3673
3674 init_waitqueue_head(&cfg->tmf_waitq);
439e85c1 3675 init_waitqueue_head(&cfg->reset_waitq);
c21e0bbf
MO
3676
3677 INIT_WORK(&cfg->work_q, cxlflash_worker_thread);
3678 cfg->lr_state = LINK_RESET_INVALID;
3679 cfg->lr_port = -1;
0d73122c 3680 spin_lock_init(&cfg->tmf_slock);
65be2c79
MO
3681 mutex_init(&cfg->ctx_tbl_list_mutex);
3682 mutex_init(&cfg->ctx_recovery_mutex);
0a27ae51 3683 init_rwsem(&cfg->ioctl_rwsem);
65be2c79
MO
3684 INIT_LIST_HEAD(&cfg->ctx_err_recovery);
3685 INIT_LIST_HEAD(&cfg->lluns);
c21e0bbf
MO
3686
3687 pci_set_drvdata(pdev, cfg);
3688
c21e0bbf
MO
3689 cfg->cxl_afu = cxl_pci_to_afu(pdev);
3690
3691 rc = init_pci(cfg);
3692 if (rc) {
88d33628 3693 dev_err(dev, "%s: init_pci failed rc=%d\n", __func__, rc);
c21e0bbf
MO
3694 goto out_remove;
3695 }
3696 cfg->init_state = INIT_STATE_PCI;
3697
3698 rc = init_afu(cfg);
f92ba507 3699 if (rc && !wq_has_sleeper(&cfg->reset_waitq)) {
88d33628 3700 dev_err(dev, "%s: init_afu failed rc=%d\n", __func__, rc);
c21e0bbf
MO
3701 goto out_remove;
3702 }
3703 cfg->init_state = INIT_STATE_AFU;
3704
c21e0bbf
MO
3705 rc = init_scsi(cfg);
3706 if (rc) {
88d33628 3707 dev_err(dev, "%s: init_scsi failed rc=%d\n", __func__, rc);
c21e0bbf
MO
3708 goto out_remove;
3709 }
3710 cfg->init_state = INIT_STATE_SCSI;
3711
f3d79b3e
UK
3712 rc = init_chrdev(cfg);
3713 if (rc) {
3714 dev_err(dev, "%s: init_chrdev failed rc=%d\n", __func__, rc);
3715 goto out_remove;
3716 }
3717 cfg->init_state = INIT_STATE_CDEV;
3718
f92ba507
MO
3719 if (wq_has_sleeper(&cfg->reset_waitq)) {
3720 cfg->state = STATE_PROBED;
3721 wake_up_all(&cfg->reset_waitq);
3722 } else
3723 cfg->state = STATE_NORMAL;
c21e0bbf 3724out:
88d33628 3725 dev_dbg(dev, "%s: returning rc=%d\n", __func__, rc);
c21e0bbf
MO
3726 return rc;
3727
3728out_remove:
3729 cxlflash_remove(pdev);
3730 goto out;
3731}
3732
5cdac81a
MO
3733/**
3734 * cxlflash_pci_error_detected() - called when a PCI error is detected
3735 * @pdev: PCI device struct.
3736 * @state: PCI channel state.
3737 *
1d3324c3
MO
3738 * When an EEH occurs during an active reset, wait until the reset is
3739 * complete and then take action based upon the device state.
3740 *
5cdac81a
MO
3741 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT
3742 */
3743static pci_ers_result_t cxlflash_pci_error_detected(struct pci_dev *pdev,
3744 pci_channel_state_t state)
3745{
65be2c79 3746 int rc = 0;
5cdac81a
MO
3747 struct cxlflash_cfg *cfg = pci_get_drvdata(pdev);
3748 struct device *dev = &cfg->dev->dev;
3749
3750 dev_dbg(dev, "%s: pdev=%p state=%u\n", __func__, pdev, state);
3751
3752 switch (state) {
3753 case pci_channel_io_frozen:
f92ba507
MO
3754 wait_event(cfg->reset_waitq, cfg->state != STATE_RESET &&
3755 cfg->state != STATE_PROBING);
1d3324c3
MO
3756 if (cfg->state == STATE_FAILTERM)
3757 return PCI_ERS_RESULT_DISCONNECT;
3758
439e85c1 3759 cfg->state = STATE_RESET;
5cdac81a 3760 scsi_block_requests(cfg->host);
0a27ae51 3761 drain_ioctls(cfg);
65be2c79
MO
3762 rc = cxlflash_mark_contexts_error(cfg);
3763 if (unlikely(rc))
88d33628 3764 dev_err(dev, "%s: Failed to mark user contexts rc=%d\n",
65be2c79 3765 __func__, rc);
9526f360 3766 term_afu(cfg);
5cdac81a
MO
3767 return PCI_ERS_RESULT_NEED_RESET;
3768 case pci_channel_io_perm_failure:
3769 cfg->state = STATE_FAILTERM;
439e85c1 3770 wake_up_all(&cfg->reset_waitq);
5cdac81a
MO
3771 scsi_unblock_requests(cfg->host);
3772 return PCI_ERS_RESULT_DISCONNECT;
3773 default:
3774 break;
3775 }
3776 return PCI_ERS_RESULT_NEED_RESET;
3777}
3778
3779/**
3780 * cxlflash_pci_slot_reset() - called when PCI slot has been reset
3781 * @pdev: PCI device struct.
3782 *
3783 * This routine is called by the pci error recovery code after the PCI
3784 * slot has been reset, just before we should resume normal operations.
3785 *
3786 * Return: PCI_ERS_RESULT_RECOVERED or PCI_ERS_RESULT_DISCONNECT
3787 */
3788static pci_ers_result_t cxlflash_pci_slot_reset(struct pci_dev *pdev)
3789{
3790 int rc = 0;
3791 struct cxlflash_cfg *cfg = pci_get_drvdata(pdev);
3792 struct device *dev = &cfg->dev->dev;
3793
3794 dev_dbg(dev, "%s: pdev=%p\n", __func__, pdev);
3795
3796 rc = init_afu(cfg);
3797 if (unlikely(rc)) {
88d33628 3798 dev_err(dev, "%s: EEH recovery failed rc=%d\n", __func__, rc);
5cdac81a
MO
3799 return PCI_ERS_RESULT_DISCONNECT;
3800 }
3801
3802 return PCI_ERS_RESULT_RECOVERED;
3803}
3804
3805/**
3806 * cxlflash_pci_resume() - called when normal operation can resume
3807 * @pdev: PCI device struct
3808 */
3809static void cxlflash_pci_resume(struct pci_dev *pdev)
3810{
3811 struct cxlflash_cfg *cfg = pci_get_drvdata(pdev);
3812 struct device *dev = &cfg->dev->dev;
3813
3814 dev_dbg(dev, "%s: pdev=%p\n", __func__, pdev);
3815
3816 cfg->state = STATE_NORMAL;
439e85c1 3817 wake_up_all(&cfg->reset_waitq);
5cdac81a
MO
3818 scsi_unblock_requests(cfg->host);
3819}
3820
f3d79b3e
UK
3821/**
3822 * cxlflash_devnode() - provides devtmpfs for devices in the cxlflash class
3823 * @dev: Character device.
3824 * @mode: Mode that can be used to verify access.
3825 *
3826 * Return: Allocated string describing the devtmpfs structure.
3827 */
3828static char *cxlflash_devnode(struct device *dev, umode_t *mode)
3829{
3830 return kasprintf(GFP_KERNEL, "cxlflash/%s", dev_name(dev));
3831}
3832
3833/**
3834 * cxlflash_class_init() - create character device class
3835 *
3836 * Return: 0 on success, -errno on failure
3837 */
3838static int cxlflash_class_init(void)
3839{
3840 dev_t devno;
3841 int rc = 0;
3842
3843 rc = alloc_chrdev_region(&devno, 0, CXLFLASH_MAX_ADAPTERS, "cxlflash");
3844 if (unlikely(rc)) {
3845 pr_err("%s: alloc_chrdev_region failed rc=%d\n", __func__, rc);
3846 goto out;
3847 }
3848
3849 cxlflash_major = MAJOR(devno);
3850
3851 cxlflash_class = class_create(THIS_MODULE, "cxlflash");
3852 if (IS_ERR(cxlflash_class)) {
3853 rc = PTR_ERR(cxlflash_class);
3854 pr_err("%s: class_create failed rc=%d\n", __func__, rc);
3855 goto err;
3856 }
3857
3858 cxlflash_class->devnode = cxlflash_devnode;
3859out:
3860 pr_debug("%s: returning rc=%d\n", __func__, rc);
3861 return rc;
3862err:
3863 unregister_chrdev_region(devno, CXLFLASH_MAX_ADAPTERS);
3864 goto out;
3865}
3866
3867/**
3868 * cxlflash_class_exit() - destroy character device class
3869 */
3870static void cxlflash_class_exit(void)
3871{
3872 dev_t devno = MKDEV(cxlflash_major, 0);
3873
3874 class_destroy(cxlflash_class);
3875 unregister_chrdev_region(devno, CXLFLASH_MAX_ADAPTERS);
3876}
3877
5cdac81a
MO
3878static const struct pci_error_handlers cxlflash_err_handler = {
3879 .error_detected = cxlflash_pci_error_detected,
3880 .slot_reset = cxlflash_pci_slot_reset,
3881 .resume = cxlflash_pci_resume,
3882};
3883
c21e0bbf
MO
3884/*
3885 * PCI device structure
3886 */
3887static struct pci_driver cxlflash_driver = {
3888 .name = CXLFLASH_NAME,
3889 .id_table = cxlflash_pci_table,
3890 .probe = cxlflash_probe,
3891 .remove = cxlflash_remove,
babf985d 3892 .shutdown = cxlflash_remove,
5cdac81a 3893 .err_handler = &cxlflash_err_handler,
c21e0bbf
MO
3894};
3895
3896/**
3897 * init_cxlflash() - module entry point
3898 *
1284fb0c 3899 * Return: 0 on success, -errno on failure
c21e0bbf
MO
3900 */
3901static int __init init_cxlflash(void)
3902{
f3d79b3e
UK
3903 int rc;
3904
db853d50 3905 check_sizes();
65be2c79 3906 cxlflash_list_init();
f3d79b3e
UK
3907 rc = cxlflash_class_init();
3908 if (unlikely(rc))
3909 goto out;
65be2c79 3910
f3d79b3e
UK
3911 rc = pci_register_driver(&cxlflash_driver);
3912 if (unlikely(rc))
3913 goto err;
3914out:
3915 pr_debug("%s: returning rc=%d\n", __func__, rc);
3916 return rc;
3917err:
3918 cxlflash_class_exit();
3919 goto out;
c21e0bbf
MO
3920}
3921
3922/**
3923 * exit_cxlflash() - module exit point
3924 */
3925static void __exit exit_cxlflash(void)
3926{
65be2c79
MO
3927 cxlflash_term_global_luns();
3928 cxlflash_free_errpage();
3929
c21e0bbf 3930 pci_unregister_driver(&cxlflash_driver);
f3d79b3e 3931 cxlflash_class_exit();
c21e0bbf
MO
3932}
3933
3934module_init(init_cxlflash);
3935module_exit(exit_cxlflash);