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target-arm: Convert performance monitor registers
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
0ecb72a5 7static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 8{
9 int nregs;
10
11 /* VFP data registers are always little-endian. */
12 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
13 if (reg < nregs) {
14 stfq_le_p(buf, env->vfp.regs[reg]);
15 return 8;
16 }
17 if (arm_feature(env, ARM_FEATURE_NEON)) {
18 /* Aliases for Q regs. */
19 nregs += 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
22 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
23 return 16;
24 }
25 }
26 switch (reg - nregs) {
27 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
28 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
29 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
30 }
31 return 0;
32}
33
0ecb72a5 34static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 35{
36 int nregs;
37
38 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
39 if (reg < nregs) {
40 env->vfp.regs[reg] = ldfq_le_p(buf);
41 return 8;
42 }
43 if (arm_feature(env, ARM_FEATURE_NEON)) {
44 nregs += 16;
45 if (reg < nregs) {
46 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
47 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
48 return 16;
49 }
50 }
51 switch (reg - nregs) {
52 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
53 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 54 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 55 }
56 return 0;
57}
58
e9aa6c21
PM		 59static const ARMCPRegInfo cp_reginfo[] = {
60 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
61 * version" bits will read as a reserved value, which should cause
62 * Linux to not try to use the debug hardware.
63 */
64 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
65 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
66 REGINFO_SENTINEL
67};
68
7d57f408
PM		 69static const ARMCPRegInfo not_v6_cp_reginfo[] = {
70 /* Not all pre-v6 cores implemented this WFI, so this is slightly
71 * over-broad.
72 */
73 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
74 .access = PL1_W, .type = ARM_CP_WFI },
75 REGINFO_SENTINEL
76};
77
78static const ARMCPRegInfo not_v7_cp_reginfo[] = {
79 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
80 * is UNPREDICTABLE; we choose to NOP as most implementations do).
81 */
82 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
83 .access = PL1_W, .type = ARM_CP_WFI },
84 REGINFO_SENTINEL
85};
86
87static const ARMCPRegInfo v6_cp_reginfo[] = {
88 /* prefetch by MVA in v6, NOP in v7 */
89 { .name = "MVA_prefetch",
90 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
91 .access = PL1_W, .type = ARM_CP_NOP },
92 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
93 .access = PL0_W, .type = ARM_CP_NOP },
94 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
95 .access = PL0_W, .type = ARM_CP_NOP },
96 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
97 .access = PL0_W, .type = ARM_CP_NOP },
98 REGINFO_SENTINEL
99};
100
200ac0ef
PM		 101static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
102 uint64_t *value)
103{
104 /* Generic performance monitor register read function for where
105 * user access may be allowed by PMUSERENR.
106 */
107 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
108 return EXCP_UDEF;
109 }
110 *value = CPREG_FIELD32(env, ri);
111 return 0;
112}
113
114static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
115 uint64_t value)
116{
117 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
118 return EXCP_UDEF;
119 }
120 /* only the DP, X, D and E bits are writable */
121 env->cp15.c9_pmcr &= ~0x39;
122 env->cp15.c9_pmcr |= (value & 0x39);
123 return 0;
124}
125
126static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
127 uint64_t value)
128{
129 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
130 return EXCP_UDEF;
131 }
132 value &= (1 << 31);
133 env->cp15.c9_pmcnten |= value;
134 return 0;
135}
136
137static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
138 uint64_t value)
139{
140 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
141 return EXCP_UDEF;
142 }
143 value &= (1 << 31);
144 env->cp15.c9_pmcnten &= ~value;
145 return 0;
146}
147
148static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
149 uint64_t value)
150{
151 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
152 return EXCP_UDEF;
153 }
154 env->cp15.c9_pmovsr &= ~value;
155 return 0;
156}
157
158static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
159 uint64_t value)
160{
161 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
162 return EXCP_UDEF;
163 }
164 env->cp15.c9_pmxevtyper = value & 0xff;
165 return 0;
166}
167
168static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
169 uint64_t value)
170{
171 env->cp15.c9_pmuserenr = value & 1;
172 return 0;
173}
174
175static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
176 uint64_t value)
177{
178 /* We have no event counters so only the C bit can be changed */
179 value &= (1 << 31);
180 env->cp15.c9_pminten |= value;
181 return 0;
182}
183
184static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
185 uint64_t value)
186{
187 value &= (1 << 31);
188 env->cp15.c9_pminten &= ~value;
189 return 0;
190}
191
e9aa6c21
PM		 192static const ARMCPRegInfo v7_cp_reginfo[] = {
193 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
194 * debug components
195 */
196 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
197 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
198 { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
199 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 200 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
201 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
202 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 203 /* Performance monitors are implementation defined in v7,
204 * but with an ARM recommended set of registers, which we
205 * follow (although we don't actually implement any counters)
206 *
207 * Performance registers fall into three categories:
208 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
209 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
210 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
211 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
212 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
213 */
214 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
215 .access = PL0_RW, .resetvalue = 0,
216 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
217 .readfn = pmreg_read, .writefn = pmcntenset_write },
218 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
219 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
220 .readfn = pmreg_read, .writefn = pmcntenclr_write },
221 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
222 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
223 .readfn = pmreg_read, .writefn = pmovsr_write },
224 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
225 * respect PMUSERENR.
226 */
227 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
228 .access = PL0_W, .type = ARM_CP_NOP },
229 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
230 * We choose to RAZ/WI. XXX should respect PMUSERENR.
231 */
232 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
233 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
234 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
235 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
236 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
237 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
238 .access = PL0_RW,
239 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
240 .readfn = pmreg_read, .writefn = pmxevtyper_write },
241 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
242 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
243 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
244 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
245 .access = PL0_R | PL1_RW,
246 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
247 .resetvalue = 0,
248 .writefn = pmuserenr_write },
249 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
250 .access = PL1_RW,
251 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
252 .resetvalue = 0,
253 .writefn = pmintenset_write },
254 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
255 .access = PL1_RW,
256 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
257 .resetvalue = 0,
258 .writefn = pmintenclr_write },
e9aa6c21
PM		 259 REGINFO_SENTINEL
260};
261
c326b979
PM		 262static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
263{
264 value &= 1;
265 env->teecr = value;
266 return 0;
267}
268
269static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
270 uint64_t *value)
271{
272 /* This is a helper function because the user access rights
273 * depend on the value of the TEECR.
274 */
275 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
276 return EXCP_UDEF;
277 }
278 *value = env->teehbr;
279 return 0;
280}
281
282static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
283 uint64_t value)
284{
285 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
286 return EXCP_UDEF;
287 }
288 env->teehbr = value;
289 return 0;
290}
291
292static const ARMCPRegInfo t2ee_cp_reginfo[] = {
293 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
294 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
295 .resetvalue = 0,
296 .writefn = teecr_write },
297 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
298 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
299 .resetvalue = 0,
300 .readfn = teehbr_read, .writefn = teehbr_write },
301 REGINFO_SENTINEL
302};
303
4d31c596
PM		 304static const ARMCPRegInfo v6k_cp_reginfo[] = {
305 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
306 .access = PL0_RW,
307 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
308 .resetvalue = 0 },
309 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
310 .access = PL0_R|PL1_W,
311 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
312 .resetvalue = 0 },
313 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
314 .access = PL1_RW,
315 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
316 .resetvalue = 0 },
317 REGINFO_SENTINEL
318};
319
2ceb98c0
PM		 320void register_cp_regs_for_features(ARMCPU *cpu)
321{
322 /* Register all the coprocessor registers based on feature bits */
323 CPUARMState *env = &cpu->env;
324 if (arm_feature(env, ARM_FEATURE_M)) {
325 /* M profile has no coprocessor registers */
326 return;
327 }
328
e9aa6c21 329 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408
PM		 330 if (arm_feature(env, ARM_FEATURE_V6)) {
331 define_arm_cp_regs(cpu, v6_cp_reginfo);
332 } else {
333 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
334 }
4d31c596
PM		 335 if (arm_feature(env, ARM_FEATURE_V6K)) {
336 define_arm_cp_regs(cpu, v6k_cp_reginfo);
337 }
e9aa6c21 338 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 339 /* v7 performance monitor control register: same implementor
340 * field as main ID register, and we implement no event counters.
341 */
342 ARMCPRegInfo pmcr = {
343 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
344 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
345 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
346 .readfn = pmreg_read, .writefn = pmcr_write
347 };
348 define_one_arm_cp_reg(cpu, &pmcr);
e9aa6c21 349 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 350 } else {
351 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 352 }
c326b979
PM		 353 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
354 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
355 }
2ceb98c0
PM		 356}
357
778c3a06 358ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 359{
dec9c2d4 360 ARMCPU *cpu;
40f137e1 361 CPUARMState *env;
b26eefb6 362 static int inited = 0;
40f137e1 363
777dc784 364 if (!object_class_by_name(cpu_model)) {
aaed909a 365 return NULL;
777dc784
PM		 366 }
367 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 368 env = &cpu->env;
777dc784 369 env->cpu_model_str = cpu_model;
581be094 370 arm_cpu_realize(cpu);
777dc784 371
f4fc247b 372 if (tcg_enabled() && !inited) {
b26eefb6
PB		 373 inited = 1;
374 arm_translate_init();
375 }
376
df90dadb 377 cpu_reset(CPU(cpu));
56aebc89
PB		 378 if (arm_feature(env, ARM_FEATURE_NEON)) {
379 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
380 51, "arm-neon.xml", 0);
381 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
382 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
383 35, "arm-vfp3.xml", 0);
384 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
385 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
386 19, "arm-vfp.xml", 0);
387 }
0bf46a40 388 qemu_init_vcpu(env);
778c3a06 389 return cpu;
40f137e1
PB		 390}
391
777dc784
PM		 392typedef struct ARMCPUListState {
393 fprintf_function cpu_fprintf;
394 FILE *file;
395} ARMCPUListState;
3371d272 396
777dc784
PM		 397/* Sort alphabetically by type name, except for "any". */
398static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 399{
777dc784
PM		 400 ObjectClass *class_a = (ObjectClass *)a;
401 ObjectClass *class_b = (ObjectClass *)b;
402 const char *name_a, *name_b;
5adb4839 403
777dc784
PM		 404 name_a = object_class_get_name(class_a);
405 name_b = object_class_get_name(class_b);
406 if (strcmp(name_a, "any") == 0) {
407 return 1;
408 } else if (strcmp(name_b, "any") == 0) {
409 return -1;
410 } else {
411 return strcmp(name_a, name_b);
5adb4839
PB		 412 }
413}
414
777dc784 415static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 416{
777dc784
PM		 417 ObjectClass *oc = data;
418 ARMCPUListState *s = user_data;
3371d272 419
777dc784
PM		 420 (*s->cpu_fprintf)(s->file, " %s\n",
421 object_class_get_name(oc));
422}
423
424void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
425{
426 ARMCPUListState s = {
427 .file = f,
428 .cpu_fprintf = cpu_fprintf,
429 };
430 GSList *list;
431
432 list = object_class_get_list(TYPE_ARM_CPU, false);
433 list = g_slist_sort(list, arm_cpu_list_compare);
434 (*cpu_fprintf)(f, "Available CPUs:\n");
435 g_slist_foreach(list, arm_cpu_list_entry, &s);
436 g_slist_free(list);
40f137e1
PB		 437}
438
4b6a83fb
PM		 439void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
440 const ARMCPRegInfo *r, void *opaque)
441{
442 /* Define implementations of coprocessor registers.
443 * We store these in a hashtable because typically
444 * there are less than 150 registers in a space which
445 * is 16*16*16*8*8 = 262144 in size.
446 * Wildcarding is supported for the crm, opc1 and opc2 fields.
447 * If a register is defined twice then the second definition is
448 * used, so this can be used to define some generic registers and
449 * then override them with implementation specific variations.
450 * At least one of the original and the second definition should
451 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
452 * against accidental use.
453 */
454 int crm, opc1, opc2;
455 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
456 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
457 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
458 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
459 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
460 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
461 /* 64 bit registers have only CRm and Opc1 fields */
462 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
463 /* Check that the register definition has enough info to handle
464 * reads and writes if they are permitted.
465 */
466 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
467 if (r->access & PL3_R) {
468 assert(r->fieldoffset || r->readfn);
469 }
470 if (r->access & PL3_W) {
471 assert(r->fieldoffset || r->writefn);
472 }
473 }
474 /* Bad type field probably means missing sentinel at end of reg list */
475 assert(cptype_valid(r->type));
476 for (crm = crmmin; crm <= crmmax; crm++) {
477 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
478 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
479 uint32_t *key = g_new(uint32_t, 1);
480 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
481 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
482 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
483 r2->opaque = opaque;
484 /* Make sure reginfo passed to helpers for wildcarded regs
485 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
486 */
487 r2->crm = crm;
488 r2->opc1 = opc1;
489 r2->opc2 = opc2;
490 /* Overriding of an existing definition must be explicitly
491 * requested.
492 */
493 if (!(r->type & ARM_CP_OVERRIDE)) {
494 ARMCPRegInfo *oldreg;
495 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
496 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
497 fprintf(stderr, "Register redefined: cp=%d %d bit "
498 "crn=%d crm=%d opc1=%d opc2=%d, "
499 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
500 r2->crn, r2->crm, r2->opc1, r2->opc2,
501 oldreg->name, r2->name);
502 assert(0);
503 }
504 }
505 g_hash_table_insert(cpu->cp_regs, key, r2);
506 }
507 }
508 }
509}
510
511void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
512 const ARMCPRegInfo *regs, void *opaque)
513{
514 /* Define a whole list of registers */
515 const ARMCPRegInfo *r;
516 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
517 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
518 }
519}
520
521const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
522{
523 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
524}
525
526int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
527 uint64_t value)
528{
529 /* Helper coprocessor write function for write-ignore registers */
530 return 0;
531}
532
533int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
534{
535 /* Helper coprocessor write function for read-as-zero registers */
536 *value = 0;
537 return 0;
538}
539
0ecb72a5 540static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 541{
542 /* Return true if it is not valid for us to switch to
543 * this CPU mode (ie all the UNPREDICTABLE cases in
544 * the ARM ARM CPSRWriteByInstr pseudocode).
545 */
546 switch (mode) {
547 case ARM_CPU_MODE_USR:
548 case ARM_CPU_MODE_SYS:
549 case ARM_CPU_MODE_SVC:
550 case ARM_CPU_MODE_ABT:
551 case ARM_CPU_MODE_UND:
552 case ARM_CPU_MODE_IRQ:
553 case ARM_CPU_MODE_FIQ:
554 return 0;
555 default:
556 return 1;
557 }
558}
559
2f4a40e5
AZ		 560uint32_t cpsr_read(CPUARMState *env)
561{
562 int ZF;
6fbe23d5
PB		 563 ZF = (env->ZF == 0);
564 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 565 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
566 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
567 | ((env->condexec_bits & 0xfc) << 8)
568 | (env->GE << 16);
569}
570
571void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
572{
2f4a40e5 573 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 574 env->ZF = (~val) & CPSR_Z;
575 env->NF = val;
2f4a40e5
AZ		 576 env->CF = (val >> 29) & 1;
577 env->VF = (val << 3) & 0x80000000;
578 }
579 if (mask & CPSR_Q)
580 env->QF = ((val & CPSR_Q) != 0);
581 if (mask & CPSR_T)
582 env->thumb = ((val & CPSR_T) != 0);
583 if (mask & CPSR_IT_0_1) {
584 env->condexec_bits &= ~3;
585 env->condexec_bits |= (val >> 25) & 3;
586 }
587 if (mask & CPSR_IT_2_7) {
588 env->condexec_bits &= 3;
589 env->condexec_bits |= (val >> 8) & 0xfc;
590 }
591 if (mask & CPSR_GE) {
592 env->GE = (val >> 16) & 0xf;
593 }
594
595 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 596 if (bad_mode_switch(env, val & CPSR_M)) {
597 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
598 * We choose to ignore the attempt and leave the CPSR M field
599 * untouched.
600 */
601 mask &= ~CPSR_M;
602 } else {
603 switch_mode(env, val & CPSR_M);
604 }
2f4a40e5
AZ		 605 }
606 mask &= ~CACHED_CPSR_BITS;
607 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
608}
609
b26eefb6
PB		 610/* Sign/zero extend */
611uint32_t HELPER(sxtb16)(uint32_t x)
612{
613 uint32_t res;
614 res = (uint16_t)(int8_t)x;
615 res |= (uint32_t)(int8_t)(x >> 16) << 16;
616 return res;
617}
618
619uint32_t HELPER(uxtb16)(uint32_t x)
620{
621 uint32_t res;
622 res = (uint16_t)(uint8_t)x;
623 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
624 return res;
625}
626
f51bbbfe
PB		 627uint32_t HELPER(clz)(uint32_t x)
628{
7bbcb0af 629 return clz32(x);
f51bbbfe
PB		 630}
631
3670669c
PB		 632int32_t HELPER(sdiv)(int32_t num, int32_t den)
633{
634 if (den == 0)
635 return 0;
686eeb93
AJ		 636 if (num == INT_MIN && den == -1)
637 return INT_MIN;
3670669c
PB		 638 return num / den;
639}
640
641uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
642{
643 if (den == 0)
644 return 0;
645 return num / den;
646}
647
648uint32_t HELPER(rbit)(uint32_t x)
649{
650 x = ((x & 0xff000000) >> 24)
651 | ((x & 0x00ff0000) >> 8)
652 | ((x & 0x0000ff00) << 8)
653 | ((x & 0x000000ff) << 24);
654 x = ((x & 0xf0f0f0f0) >> 4)
655 | ((x & 0x0f0f0f0f) << 4);
656 x = ((x & 0x88888888) >> 3)
657 | ((x & 0x44444444) >> 1)
658 | ((x & 0x22222222) << 1)
659 | ((x & 0x11111111) << 3);
660 return x;
661}
662
ad69471c
PB		 663uint32_t HELPER(abs)(uint32_t x)
664{
665 return ((int32_t)x < 0) ? -x : x;
666}
667
5fafdf24 668#if defined(CONFIG_USER_ONLY)
b5ff1b31 669
0ecb72a5 670void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 671{
672 env->exception_index = -1;
673}
674
0ecb72a5 675int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 676 int mmu_idx)
b5ff1b31
FB		 677{
678 if (rw == 2) {
679 env->exception_index = EXCP_PREFETCH_ABORT;
680 env->cp15.c6_insn = address;
681 } else {
682 env->exception_index = EXCP_DATA_ABORT;
683 env->cp15.c6_data = address;
684 }
685 return 1;
686}
687
0ecb72a5 688void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 689{
690 cpu_abort(env, "cp15 insn %08x\n", insn);
691}
692
0ecb72a5 693uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31
FB		 694{
695 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 696}
697
9ee6e8bb 698/* These should probably raise undefined insn exceptions. */
0ecb72a5 699void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 700{
701 cpu_abort(env, "v7m_mrs %d\n", reg);
702}
703
0ecb72a5 704uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 705{
706 cpu_abort(env, "v7m_mrs %d\n", reg);
707 return 0;
708}
709
0ecb72a5 710void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 711{
712 if (mode != ARM_CPU_MODE_USR)
713 cpu_abort(env, "Tried to switch out of user mode\n");
714}
715
0ecb72a5 716void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 717{
718 cpu_abort(env, "banked r13 write\n");
719}
720
0ecb72a5 721uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 722{
723 cpu_abort(env, "banked r13 read\n");
724 return 0;
725}
726
b5ff1b31
FB		 727#else
728
729/* Map CPU modes onto saved register banks. */
0ecb72a5 730static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 731{
732 switch (mode) {
733 case ARM_CPU_MODE_USR:
734 case ARM_CPU_MODE_SYS:
735 return 0;
736 case ARM_CPU_MODE_SVC:
737 return 1;
738 case ARM_CPU_MODE_ABT:
739 return 2;
740 case ARM_CPU_MODE_UND:
741 return 3;
742 case ARM_CPU_MODE_IRQ:
743 return 4;
744 case ARM_CPU_MODE_FIQ:
745 return 5;
746 }
1b9e01c1 747 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 748 return -1;
749}
750
0ecb72a5 751void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 752{
753 int old_mode;
754 int i;
755
756 old_mode = env->uncached_cpsr & CPSR_M;
757 if (mode == old_mode)
758 return;
759
760 if (old_mode == ARM_CPU_MODE_FIQ) {
761 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 762 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 763 } else if (mode == ARM_CPU_MODE_FIQ) {
764 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 765 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 766 }
767
1b9e01c1 768 i = bank_number(env, old_mode);
b5ff1b31
FB		 769 env->banked_r13[i] = env->regs[13];
770 env->banked_r14[i] = env->regs[14];
771 env->banked_spsr[i] = env->spsr;
772
1b9e01c1 773 i = bank_number(env, mode);
b5ff1b31
FB		 774 env->regs[13] = env->banked_r13[i];
775 env->regs[14] = env->banked_r14[i];
776 env->spsr = env->banked_spsr[i];
777}
778
9ee6e8bb
PB		 779static void v7m_push(CPUARMState *env, uint32_t val)
780{
781 env->regs[13] -= 4;
782 stl_phys(env->regs[13], val);
783}
784
785static uint32_t v7m_pop(CPUARMState *env)
786{
787 uint32_t val;
788 val = ldl_phys(env->regs[13]);
789 env->regs[13] += 4;
790 return val;
791}
792
793/* Switch to V7M main or process stack pointer. */
794static void switch_v7m_sp(CPUARMState *env, int process)
795{
796 uint32_t tmp;
797 if (env->v7m.current_sp != process) {
798 tmp = env->v7m.other_sp;
799 env->v7m.other_sp = env->regs[13];
800 env->regs[13] = tmp;
801 env->v7m.current_sp = process;
802 }
803}
804
805static void do_v7m_exception_exit(CPUARMState *env)
806{
807 uint32_t type;
808 uint32_t xpsr;
809
810 type = env->regs[15];
811 if (env->v7m.exception != 0)
983fe826 812 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 813
814 /* Switch to the target stack. */
815 switch_v7m_sp(env, (type & 4) != 0);
816 /* Pop registers. */
817 env->regs[0] = v7m_pop(env);
818 env->regs[1] = v7m_pop(env);
819 env->regs[2] = v7m_pop(env);
820 env->regs[3] = v7m_pop(env);
821 env->regs[12] = v7m_pop(env);
822 env->regs[14] = v7m_pop(env);
823 env->regs[15] = v7m_pop(env);
824 xpsr = v7m_pop(env);
825 xpsr_write(env, xpsr, 0xfffffdff);
826 /* Undo stack alignment. */
827 if (xpsr & 0x200)
828 env->regs[13] |= 4;
829 /* ??? The exception return type specifies Thread/Handler mode. However
830 this is also implied by the xPSR value. Not sure what to do
831 if there is a mismatch. */
832 /* ??? Likewise for mismatches between the CONTROL register and the stack
833 pointer. */
834}
835
2b3ea315 836static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 837{
838 uint32_t xpsr = xpsr_read(env);
839 uint32_t lr;
840 uint32_t addr;
841
842 lr = 0xfffffff1;
843 if (env->v7m.current_sp)
844 lr |= 4;
845 if (env->v7m.exception == 0)
846 lr |= 8;
847
848 /* For exceptions we just mark as pending on the NVIC, and let that
849 handle it. */
850 /* TODO: Need to escalate if the current priority is higher than the
851 one we're raising. */
852 switch (env->exception_index) {
853 case EXCP_UDEF:
983fe826 854 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 855 return;
856 case EXCP_SWI:
857 env->regs[15] += 2;
983fe826 858 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 859 return;
860 case EXCP_PREFETCH_ABORT:
861 case EXCP_DATA_ABORT:
983fe826 862 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 863 return;
864 case EXCP_BKPT:
2ad207d4
PB		 865 if (semihosting_enabled) {
866 int nr;
d8fd2954 867 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 868 if (nr == 0xab) {
869 env->regs[15] += 2;
870 env->regs[0] = do_arm_semihosting(env);
871 return;
872 }
873 }
983fe826 874 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 875 return;
876 case EXCP_IRQ:
983fe826 877 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 878 break;
879 case EXCP_EXCEPTION_EXIT:
880 do_v7m_exception_exit(env);
881 return;
882 default:
883 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
884 return; /* Never happens. Keep compiler happy. */
885 }
886
887 /* Align stack pointer. */
888 /* ??? Should only do this if Configuration Control Register
889 STACKALIGN bit is set. */
890 if (env->regs[13] & 4) {
ab19b0ec 891 env->regs[13] -= 4;
9ee6e8bb
PB		 892 xpsr |= 0x200;
893 }
6c95676b 894 /* Switch to the handler mode. */
9ee6e8bb
PB		 895 v7m_push(env, xpsr);
896 v7m_push(env, env->regs[15]);
897 v7m_push(env, env->regs[14]);
898 v7m_push(env, env->regs[12]);
899 v7m_push(env, env->regs[3]);
900 v7m_push(env, env->regs[2]);
901 v7m_push(env, env->regs[1]);
902 v7m_push(env, env->regs[0]);
903 switch_v7m_sp(env, 0);
c98d174c
PM		 904 /* Clear IT bits */
905 env->condexec_bits = 0;
9ee6e8bb
PB		 906 env->regs[14] = lr;
907 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
908 env->regs[15] = addr & 0xfffffffe;
909 env->thumb = addr & 1;
910}
911
b5ff1b31
FB		 912/* Handle a CPU exception. */
913void do_interrupt(CPUARMState *env)
914{
915 uint32_t addr;
916 uint32_t mask;
917 int new_mode;
918 uint32_t offset;
919
9ee6e8bb
PB		 920 if (IS_M(env)) {
921 do_interrupt_v7m(env);
922 return;
923 }
b5ff1b31
FB		 924 /* TODO: Vectored interrupt controller. */
925 switch (env->exception_index) {
926 case EXCP_UDEF:
927 new_mode = ARM_CPU_MODE_UND;
928 addr = 0x04;
929 mask = CPSR_I;
930 if (env->thumb)
931 offset = 2;
932 else
933 offset = 4;
934 break;
935 case EXCP_SWI:
8e71621f
PB		 936 if (semihosting_enabled) {
937 /* Check for semihosting interrupt. */
938 if (env->thumb) {
d8fd2954 939 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 940 } else {
d8fd2954
PB		 941 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
942 & 0xffffff;
8e71621f
PB		 943 }
944 /* Only intercept calls from privileged modes, to provide some
945 semblance of security. */
946 if (((mask == 0x123456 && !env->thumb)
947 || (mask == 0xab && env->thumb))
948 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
949 env->regs[0] = do_arm_semihosting(env);
950 return;
951 }
952 }
b5ff1b31
FB		 953 new_mode = ARM_CPU_MODE_SVC;
954 addr = 0x08;
955 mask = CPSR_I;
601d70b9 956 /* The PC already points to the next instruction. */
b5ff1b31
FB		 957 offset = 0;
958 break;
06c949e6 959 case EXCP_BKPT:
9ee6e8bb 960 /* See if this is a semihosting syscall. */
2ad207d4 961 if (env->thumb && semihosting_enabled) {
d8fd2954 962 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 963 if (mask == 0xab
964 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
965 env->regs[15] += 2;
966 env->regs[0] = do_arm_semihosting(env);
967 return;
968 }
969 }
81c05daf 970 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 971 /* Fall through to prefetch abort. */
972 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 973 new_mode = ARM_CPU_MODE_ABT;
974 addr = 0x0c;
975 mask = CPSR_A | CPSR_I;
976 offset = 4;
977 break;
978 case EXCP_DATA_ABORT:
979 new_mode = ARM_CPU_MODE_ABT;
980 addr = 0x10;
981 mask = CPSR_A | CPSR_I;
982 offset = 8;
983 break;
984 case EXCP_IRQ:
985 new_mode = ARM_CPU_MODE_IRQ;
986 addr = 0x18;
987 /* Disable IRQ and imprecise data aborts. */
988 mask = CPSR_A | CPSR_I;
989 offset = 4;
990 break;
991 case EXCP_FIQ:
992 new_mode = ARM_CPU_MODE_FIQ;
993 addr = 0x1c;
994 /* Disable FIQ, IRQ and imprecise data aborts. */
995 mask = CPSR_A | CPSR_I | CPSR_F;
996 offset = 4;
997 break;
998 default:
999 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1000 return; /* Never happens. Keep compiler happy. */
1001 }
1002 /* High vectors. */
1003 if (env->cp15.c1_sys & (1 << 13)) {
1004 addr += 0xffff0000;
1005 }
1006 switch_mode (env, new_mode);
1007 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1008 /* Clear IT bits. */
1009 env->condexec_bits = 0;
30a8cac1 1010 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1011 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1012 env->uncached_cpsr |= mask;
be5e7a76
DES		 1013 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1014 * and we should just guard the thumb mode on V4 */
1015 if (arm_feature(env, ARM_FEATURE_V4T)) {
1016 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1017 }
b5ff1b31
FB		 1018 env->regs[14] = env->regs[15] + offset;
1019 env->regs[15] = addr;
1020 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1021}
1022
1023/* Check section/page access permissions.
1024 Returns the page protection flags, or zero if the access is not
1025 permitted. */
0ecb72a5 1026static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1027 int access_type, int is_user)
b5ff1b31 1028{
9ee6e8bb
PB		 1029 int prot_ro;
1030
dd4ebc2e 1031 if (domain_prot == 3) {
b5ff1b31 1032 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1033 }
b5ff1b31 1034
9ee6e8bb
PB		 1035 if (access_type == 1)
1036 prot_ro = 0;
1037 else
1038 prot_ro = PAGE_READ;
1039
b5ff1b31
FB		 1040 switch (ap) {
1041 case 0:
78600320 1042 if (access_type == 1)
b5ff1b31
FB		 1043 return 0;
1044 switch ((env->cp15.c1_sys >> 8) & 3) {
1045 case 1:
1046 return is_user ? 0 : PAGE_READ;
1047 case 2:
1048 return PAGE_READ;
1049 default:
1050 return 0;
1051 }
1052 case 1:
1053 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1054 case 2:
1055 if (is_user)
9ee6e8bb 1056 return prot_ro;
b5ff1b31
FB		 1057 else
1058 return PAGE_READ | PAGE_WRITE;
1059 case 3:
1060 return PAGE_READ | PAGE_WRITE;
d4934d18 1061 case 4: /* Reserved. */
9ee6e8bb
PB		 1062 return 0;
1063 case 5:
1064 return is_user ? 0 : prot_ro;
1065 case 6:
1066 return prot_ro;
d4934d18 1067 case 7:
0ab06d83 1068 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1069 return 0;
1070 return prot_ro;
b5ff1b31
FB		 1071 default:
1072 abort();
1073 }
1074}
1075
0ecb72a5 1076static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1077{
1078 uint32_t table;
1079
1080 if (address & env->cp15.c2_mask)
1081 table = env->cp15.c2_base1 & 0xffffc000;
1082 else
1083 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1084
1085 table |= (address >> 18) & 0x3ffc;
1086 return table;
1087}
1088
0ecb72a5 1089static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1090 int is_user, uint32_t *phys_ptr, int *prot,
1091 target_ulong *page_size)
b5ff1b31
FB		 1092{
1093 int code;
1094 uint32_t table;
1095 uint32_t desc;
1096 int type;
1097 int ap;
1098 int domain;
dd4ebc2e 1099 int domain_prot;
b5ff1b31
FB		 1100 uint32_t phys_addr;
1101
9ee6e8bb
PB		 1102 /* Pagetable walk. */
1103 /* Lookup l1 descriptor. */
b2fa1797 1104 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1105 desc = ldl_phys(table);
1106 type = (desc & 3);
dd4ebc2e
JCD		 1107 domain = (desc >> 5) & 0x0f;
1108 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1109 if (type == 0) {
601d70b9 1110 /* Section translation fault. */
9ee6e8bb
PB		 1111 code = 5;
1112 goto do_fault;
1113 }
dd4ebc2e 1114 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1115 if (type == 2)
1116 code = 9; /* Section domain fault. */
1117 else
1118 code = 11; /* Page domain fault. */
1119 goto do_fault;
1120 }
1121 if (type == 2) {
1122 /* 1Mb section. */
1123 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1124 ap = (desc >> 10) & 3;
1125 code = 13;
d4c430a8 1126 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1127 } else {
1128 /* Lookup l2 entry. */
1129 if (type == 1) {
1130 /* Coarse pagetable. */
1131 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1132 } else {
1133 /* Fine pagetable. */
1134 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1135 }
1136 desc = ldl_phys(table);
1137 switch (desc & 3) {
1138 case 0: /* Page translation fault. */
1139 code = 7;
1140 goto do_fault;
1141 case 1: /* 64k page. */
1142 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1143 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1144 *page_size = 0x10000;
ce819861 1145 break;
9ee6e8bb
PB		 1146 case 2: /* 4k page. */
1147 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1148 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1149 *page_size = 0x1000;
ce819861 1150 break;
9ee6e8bb
PB		 1151 case 3: /* 1k page. */
1152 if (type == 1) {
1153 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1154 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1155 } else {
1156 /* Page translation fault. */
1157 code = 7;
1158 goto do_fault;
1159 }
1160 } else {
1161 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1162 }
1163 ap = (desc >> 4) & 3;
d4c430a8 1164 *page_size = 0x400;
ce819861
PB		 1165 break;
1166 default:
9ee6e8bb
PB		 1167 /* Never happens, but compiler isn't smart enough to tell. */
1168 abort();
ce819861 1169 }
9ee6e8bb
PB		 1170 code = 15;
1171 }
dd4ebc2e 1172 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1173 if (!*prot) {
1174 /* Access permission fault. */
1175 goto do_fault;
1176 }
3ad493fc 1177 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1178 *phys_ptr = phys_addr;
1179 return 0;
1180do_fault:
1181 return code | (domain << 4);
1182}
1183
0ecb72a5 1184static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1185 int is_user, uint32_t *phys_ptr, int *prot,
1186 target_ulong *page_size)
9ee6e8bb
PB		 1187{
1188 int code;
1189 uint32_t table;
1190 uint32_t desc;
1191 uint32_t xn;
1192 int type;
1193 int ap;
1194 int domain;
dd4ebc2e 1195 int domain_prot;
9ee6e8bb
PB		 1196 uint32_t phys_addr;
1197
1198 /* Pagetable walk. */
1199 /* Lookup l1 descriptor. */
b2fa1797 1200 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1201 desc = ldl_phys(table);
1202 type = (desc & 3);
1203 if (type == 0) {
601d70b9 1204 /* Section translation fault. */
9ee6e8bb
PB		 1205 code = 5;
1206 domain = 0;
1207 goto do_fault;
1208 } else if (type == 2 && (desc & (1 << 18))) {
1209 /* Supersection. */
1210 domain = 0;
b5ff1b31 1211 } else {
9ee6e8bb 1212 /* Section or page. */
dd4ebc2e 1213 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1214 }
dd4ebc2e
JCD		 1215 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1216 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1217 if (type == 2)
1218 code = 9; /* Section domain fault. */
1219 else
1220 code = 11; /* Page domain fault. */
1221 goto do_fault;
1222 }
1223 if (type == 2) {
1224 if (desc & (1 << 18)) {
1225 /* Supersection. */
1226 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1227 *page_size = 0x1000000;
b5ff1b31 1228 } else {
9ee6e8bb
PB		 1229 /* Section. */
1230 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1231 *page_size = 0x100000;
b5ff1b31 1232 }
9ee6e8bb
PB		 1233 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1234 xn = desc & (1 << 4);
1235 code = 13;
1236 } else {
1237 /* Lookup l2 entry. */
1238 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1239 desc = ldl_phys(table);
1240 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1241 switch (desc & 3) {
1242 case 0: /* Page translation fault. */
1243 code = 7;
b5ff1b31 1244 goto do_fault;
9ee6e8bb
PB		 1245 case 1: /* 64k page. */
1246 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1247 xn = desc & (1 << 15);
d4c430a8 1248 *page_size = 0x10000;
9ee6e8bb
PB		 1249 break;
1250 case 2: case 3: /* 4k page. */
1251 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1252 xn = desc & 1;
d4c430a8 1253 *page_size = 0x1000;
9ee6e8bb
PB		 1254 break;
1255 default:
1256 /* Never happens, but compiler isn't smart enough to tell. */
1257 abort();
b5ff1b31 1258 }
9ee6e8bb
PB		 1259 code = 15;
1260 }
dd4ebc2e 1261 if (domain_prot == 3) {
c0034328
JR		 1262 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1263 } else {
1264 if (xn && access_type == 2)
1265 goto do_fault;
9ee6e8bb 1266
c0034328
JR		 1267 /* The simplified model uses AP[0] as an access control bit. */
1268 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1269 /* Access flag fault. */
1270 code = (code == 15) ? 6 : 3;
1271 goto do_fault;
1272 }
dd4ebc2e 1273 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1274 if (!*prot) {
1275 /* Access permission fault. */
1276 goto do_fault;
1277 }
1278 if (!xn) {
1279 *prot |= PAGE_EXEC;
1280 }
3ad493fc 1281 }
9ee6e8bb 1282 *phys_ptr = phys_addr;
b5ff1b31
FB		 1283 return 0;
1284do_fault:
1285 return code | (domain << 4);
1286}
1287
0ecb72a5 1288static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 1289 int is_user, uint32_t *phys_ptr, int *prot)
1290{
1291 int n;
1292 uint32_t mask;
1293 uint32_t base;
1294
1295 *phys_ptr = address;
1296 for (n = 7; n >= 0; n--) {
1297 base = env->cp15.c6_region[n];
1298 if ((base & 1) == 0)
1299 continue;
1300 mask = 1 << ((base >> 1) & 0x1f);
1301 /* Keep this shift separate from the above to avoid an
1302 (undefined) << 32. */
1303 mask = (mask << 1) - 1;
1304 if (((base ^ address) & ~mask) == 0)
1305 break;
1306 }
1307 if (n < 0)
1308 return 2;
1309
1310 if (access_type == 2) {
1311 mask = env->cp15.c5_insn;
1312 } else {
1313 mask = env->cp15.c5_data;
1314 }
1315 mask = (mask >> (n * 4)) & 0xf;
1316 switch (mask) {
1317 case 0:
1318 return 1;
1319 case 1:
1320 if (is_user)
1321 return 1;
1322 *prot = PAGE_READ | PAGE_WRITE;
1323 break;
1324 case 2:
1325 *prot = PAGE_READ;
1326 if (!is_user)
1327 *prot |= PAGE_WRITE;
1328 break;
1329 case 3:
1330 *prot = PAGE_READ | PAGE_WRITE;
1331 break;
1332 case 5:
1333 if (is_user)
1334 return 1;
1335 *prot = PAGE_READ;
1336 break;
1337 case 6:
1338 *prot = PAGE_READ;
1339 break;
1340 default:
1341 /* Bad permission. */
1342 return 1;
1343 }
3ad493fc 1344 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1345 return 0;
1346}
1347
0ecb72a5 1348static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 1349 int access_type, int is_user,
d4c430a8
PB		 1350 uint32_t *phys_ptr, int *prot,
1351 target_ulong *page_size)
9ee6e8bb
PB		 1352{
1353 /* Fast Context Switch Extension. */
1354 if (address < 0x02000000)
1355 address += env->cp15.c13_fcse;
1356
1357 if ((env->cp15.c1_sys & 1) == 0) {
1358 /* MMU/MPU disabled. */
1359 *phys_ptr = address;
3ad493fc 1360 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1361 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1362 return 0;
1363 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1364 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1365 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1366 prot);
1367 } else if (env->cp15.c1_sys & (1 << 23)) {
1368 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1369 prot, page_size);
9ee6e8bb
PB		 1370 } else {
1371 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1372 prot, page_size);
9ee6e8bb
PB		 1373 }
1374}
1375
0ecb72a5 1376int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 1377 int access_type, int mmu_idx)
b5ff1b31
FB		 1378{
1379 uint32_t phys_addr;
d4c430a8 1380 target_ulong page_size;
b5ff1b31 1381 int prot;
6ebbf390 1382 int ret, is_user;
b5ff1b31 1383
6ebbf390 1384 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1385 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1386 &page_size);
b5ff1b31
FB		 1387 if (ret == 0) {
1388 /* Map a single [sub]page. */
1389 phys_addr &= ~(uint32_t)0x3ff;
1390 address &= ~(uint32_t)0x3ff;
3ad493fc 1391 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1392 return 0;
b5ff1b31
FB		 1393 }
1394
1395 if (access_type == 2) {
1396 env->cp15.c5_insn = ret;
1397 env->cp15.c6_insn = address;
1398 env->exception_index = EXCP_PREFETCH_ABORT;
1399 } else {
1400 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1401 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1402 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1403 env->cp15.c6_data = address;
1404 env->exception_index = EXCP_DATA_ABORT;
1405 }
1406 return 1;
1407}
1408
0ecb72a5 1409target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 1410{
1411 uint32_t phys_addr;
d4c430a8 1412 target_ulong page_size;
b5ff1b31
FB		 1413 int prot;
1414 int ret;
1415
d4c430a8 1416 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1417
1418 if (ret != 0)
1419 return -1;
1420
1421 return phys_addr;
1422}
1423
ce819861
PB		 1424/* Return basic MPU access permission bits. */
1425static uint32_t simple_mpu_ap_bits(uint32_t val)
1426{
1427 uint32_t ret;
1428 uint32_t mask;
1429 int i;
1430 ret = 0;
1431 mask = 3;
1432 for (i = 0; i < 16; i += 2) {
1433 ret |= (val >> i) & mask;
1434 mask <<= 2;
1435 }
1436 return ret;
1437}
1438
1439/* Pad basic MPU access permission bits to extended format. */
1440static uint32_t extended_mpu_ap_bits(uint32_t val)
1441{
1442 uint32_t ret;
1443 uint32_t mask;
1444 int i;
1445 ret = 0;
1446 mask = 3;
1447 for (i = 0; i < 16; i += 2) {
1448 ret |= (val & mask) << i;
1449 mask <<= 2;
1450 }
1451 return ret;
1452}
1453
0ecb72a5 1454void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31 1455{
9ee6e8bb
PB		 1456 int op1;
1457 int op2;
1458 int crm;
b5ff1b31 1459
9ee6e8bb 1460 op1 = (insn >> 21) & 7;
b5ff1b31 1461 op2 = (insn >> 5) & 7;
ce819861 1462 crm = insn & 0xf;
b5ff1b31 1463 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1464 case 0:
9ee6e8bb 1465 /* ID codes. */
610c3c8a
AZ		 1466 if (arm_feature(env, ARM_FEATURE_XSCALE))
1467 break;
c3d2689d
AZ		 1468 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1469 break;
a49ea279
PB		 1470 if (arm_feature(env, ARM_FEATURE_V7)
1471 && op1 == 2 && crm == 0 && op2 == 0) {
1472 env->cp15.c0_cssel = val & 0xf;
1473 break;
1474 }
b5ff1b31
FB		 1475 goto bad_reg;
1476 case 1: /* System configuration. */
2be27624
RH		 1477 if (arm_feature(env, ARM_FEATURE_V7)
1478 && op1 == 0 && crm == 1 && op2 == 0) {
1479 env->cp15.c1_scr = val;
1480 break;
1481 }
c3d2689d
AZ		 1482 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1483 op2 = 0;
b5ff1b31
FB		 1484 switch (op2) {
1485 case 0:
ce819861 1486 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1487 env->cp15.c1_sys = val;
b5ff1b31
FB		 1488 /* ??? Lots of these bits are not implemented. */
1489 /* This may enable/disable the MMU, so do a TLB flush. */
1490 tlb_flush(env, 1);
1491 break;
61cc8701 1492 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1493 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1494 env->cp15.c1_xscaleauxcr = val;
c1713132 1495 break;
610c3c8a 1496 }
9ee6e8bb
PB		 1497 /* Not implemented. */
1498 break;
b5ff1b31 1499 case 2:
610c3c8a
AZ		 1500 if (arm_feature(env, ARM_FEATURE_XSCALE))
1501 goto bad_reg;
4be27dbb
PB		 1502 if (env->cp15.c1_coproc != val) {
1503 env->cp15.c1_coproc = val;
1504 /* ??? Is this safe when called from within a TB? */
1505 tb_flush(env);
1506 }
c1713132 1507 break;
b5ff1b31
FB		 1508 default:
1509 goto bad_reg;
1510 }
1511 break;
ce819861
PB		 1512 case 2: /* MMU Page table control / MPU cache control. */
1513 if (arm_feature(env, ARM_FEATURE_MPU)) {
1514 switch (op2) {
1515 case 0:
1516 env->cp15.c2_data = val;
1517 break;
1518 case 1:
1519 env->cp15.c2_insn = val;
1520 break;
1521 default:
1522 goto bad_reg;
1523 }
1524 } else {
9ee6e8bb
PB		 1525 switch (op2) {
1526 case 0:
1527 env->cp15.c2_base0 = val;
1528 break;
1529 case 1:
1530 env->cp15.c2_base1 = val;
1531 break;
1532 case 2:
b2fa1797
PB		 1533 val &= 7;
1534 env->cp15.c2_control = val;
9ee6e8bb 1535 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1536 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1537 break;
1538 default:
1539 goto bad_reg;
1540 }
ce819861 1541 }
b5ff1b31 1542 break;
ce819861 1543 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1544 env->cp15.c3 = val;
405ee3ad 1545 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1546 break;
1547 case 4: /* Reserved. */
1548 goto bad_reg;
ce819861 1549 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1550 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1551 op2 = 0;
b5ff1b31
FB		 1552 switch (op2) {
1553 case 0:
ce819861
PB		 1554 if (arm_feature(env, ARM_FEATURE_MPU))
1555 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1556 env->cp15.c5_data = val;
1557 break;
1558 case 1:
ce819861
PB		 1559 if (arm_feature(env, ARM_FEATURE_MPU))
1560 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1561 env->cp15.c5_insn = val;
1562 break;
ce819861
PB		 1563 case 2:
1564 if (!arm_feature(env, ARM_FEATURE_MPU))
1565 goto bad_reg;
1566 env->cp15.c5_data = val;
b5ff1b31 1567 break;
ce819861
PB		 1568 case 3:
1569 if (!arm_feature(env, ARM_FEATURE_MPU))
1570 goto bad_reg;
1571 env->cp15.c5_insn = val;
b5ff1b31
FB		 1572 break;
1573 default:
1574 goto bad_reg;
1575 }
1576 break;
ce819861
PB		 1577 case 6: /* MMU Fault address / MPU base/size. */
1578 if (arm_feature(env, ARM_FEATURE_MPU)) {
1579 if (crm >= 8)
1580 goto bad_reg;
1581 env->cp15.c6_region[crm] = val;
1582 } else {
c3d2689d
AZ		 1583 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1584 op2 = 0;
ce819861
PB		 1585 switch (op2) {
1586 case 0:
1587 env->cp15.c6_data = val;
1588 break;
9ee6e8bb
PB		 1589 case 1: /* ??? This is WFAR on armv6 */
1590 case 2:
ce819861
PB		 1591 env->cp15.c6_insn = val;
1592 break;
1593 default:
1594 goto bad_reg;
1595 }
1596 }
1597 break;
b5ff1b31 1598 case 7: /* Cache control. */
c3d2689d
AZ		 1599 env->cp15.c15_i_max = 0x000;
1600 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1601 if (op1 != 0) {
1602 goto bad_reg;
1603 }
1604 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1605 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1606 switch (crm) {
1607 case 4:
1608 if (arm_feature(env, ARM_FEATURE_V7)) {
1609 env->cp15.c7_par = val & 0xfffff6ff;
1610 } else {
1611 env->cp15.c7_par = val & 0xfffff1ff;
1612 }
1613 break;
1614 case 8: {
1615 uint32_t phys_addr;
1616 target_ulong page_size;
1617 int prot;
1618 int ret, is_user = op2 & 2;
1619 int access_type = op2 & 1;
1620
1621 if (op2 & 4) {
1622 /* Other states are only available with TrustZone */
1623 goto bad_reg;
1624 }
1625 ret = get_phys_addr(env, val, access_type, is_user,
1626 &phys_addr, &prot, &page_size);
1627 if (ret == 0) {
1628 /* We do not set any attribute bits in the PAR */
1629 if (page_size == (1 << 24)
1630 && arm_feature(env, ARM_FEATURE_V7)) {
1631 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1632 } else {
1633 env->cp15.c7_par = phys_addr & 0xfffff000;
1634 }
1635 } else {
1636 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1637 ((ret & (12 << 1)) >> 6) |
1638 ((ret & 0xf) << 1) | 1;
1639 }
1640 break;
1641 }
1642 }
1643 }
b5ff1b31
FB		 1644 break;
1645 case 8: /* MMU TLB control. */
1646 switch (op2) {
dc8714ca
PM		 1647 case 0: /* Invalidate all (TLBIALL) */
1648 tlb_flush(env, 1);
b5ff1b31 1649 break;
dc8714ca 1650 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
d4c430a8 1651 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1652 break;
dc8714ca 1653 case 2: /* Invalidate by ASID (TLBIASID) */
9ee6e8bb
PB		 1654 tlb_flush(env, val == 0);
1655 break;
dc8714ca
PM		 1656 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1657 tlb_flush_page(env, val & TARGET_PAGE_MASK);
9ee6e8bb 1658 break;
b5ff1b31
FB		 1659 default:
1660 goto bad_reg;
1661 }
1662 break;
ce819861 1663 case 9:
c3d2689d
AZ		 1664 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1665 break;
5bc95aa2
DES		 1666 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1667 break; /* Ignore ReadBuffer access */
ce819861
PB		 1668 switch (crm) {
1669 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1670 switch (op1) {
1671 case 0: /* L1 cache. */
1672 switch (op2) {
1673 case 0:
1674 env->cp15.c9_data = val;
1675 break;
1676 case 1:
1677 env->cp15.c9_insn = val;
1678 break;
1679 default:
1680 goto bad_reg;
1681 }
1682 break;
1683 case 1: /* L2 cache. */
1684 /* Ignore writes to L2 lockdown/auxiliary registers. */
1685 break;
1686 default:
1687 goto bad_reg;
1688 }
1689 break;
ce819861
PB		 1690 case 1: /* TCM memory region registers. */
1691 /* Not implemented. */
1692 goto bad_reg;
b5ff1b31
FB		 1693 default:
1694 goto bad_reg;
1695 }
1696 break;
1697 case 10: /* MMU TLB lockdown. */
1698 /* ??? TLB lockdown not implemented. */
1699 break;
b5ff1b31
FB		 1700 case 12: /* Reserved. */
1701 goto bad_reg;
1702 case 13: /* Process ID. */
1703 switch (op2) {
1704 case 0:
d07edbfa
PB		 1705 /* Unlike real hardware the qemu TLB uses virtual addresses,
1706 not modified virtual addresses, so this causes a TLB flush.
1707 */
1708 if (env->cp15.c13_fcse != val)
1709 tlb_flush(env, 1);
1710 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1711 break;
1712 case 1:
d07edbfa 1713 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1714 if (env->cp15.c13_context != val
1715 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1716 tlb_flush(env, 0);
1717 env->cp15.c13_context = val;
b5ff1b31
FB		 1718 break;
1719 default:
1720 goto bad_reg;
1721 }
1722 break;
0383ac00
PM		 1723 case 14: /* Generic timer */
1724 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1725 /* Dummy implementation: RAZ/WI for all */
1726 break;
1727 }
b5ff1b31
FB		 1728 goto bad_reg;
1729 case 15: /* Implementation specific. */
c1713132 1730 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1731 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1732 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1733 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1734 tb_flush(env);
1735 env->cp15.c15_cpar = val & 0x3fff;
1736 }
c1713132
AZ		 1737 break;
1738 }
1739 goto bad_reg;
1740 }
c3d2689d
AZ		 1741 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1742 switch (crm) {
1743 case 0:
1744 break;
1745 case 1: /* Set TI925T configuration. */
1746 env->cp15.c15_ticonfig = val & 0xe7;
1747 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1748 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1749 break;
1750 case 2: /* Set I_max. */
1751 env->cp15.c15_i_max = val;
1752 break;
1753 case 3: /* Set I_min. */
1754 env->cp15.c15_i_min = val;
1755 break;
1756 case 4: /* Set thread-ID. */
1757 env->cp15.c15_threadid = val & 0xffff;
1758 break;
1759 case 8: /* Wait-for-interrupt (deprecated). */
1760 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1761 break;
1762 default:
1763 goto bad_reg;
1764 }
1765 }
7da362d0
ML		 1766 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1767 switch (crm) {
1768 case 0:
1769 if ((op1 == 0) && (op2 == 0)) {
1770 env->cp15.c15_power_control = val;
1771 } else if ((op1 == 0) && (op2 == 1)) {
1772 env->cp15.c15_diagnostic = val;
1773 } else if ((op1 == 0) && (op2 == 2)) {
1774 env->cp15.c15_power_diagnostic = val;
1775 }
1776 default:
1777 break;
1778 }
1779 }
b5ff1b31
FB		 1780 break;
1781 }
1782 return;
1783bad_reg:
1784 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1785 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1786 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1787}
1788
0ecb72a5 1789uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31 1790{
9ee6e8bb
PB		 1791 int op1;
1792 int op2;
1793 int crm;
b5ff1b31 1794
9ee6e8bb 1795 op1 = (insn >> 21) & 7;
b5ff1b31 1796 op2 = (insn >> 5) & 7;
c3d2689d 1797 crm = insn & 0xf;
b5ff1b31
FB		 1798 switch ((insn >> 16) & 0xf) {
1799 case 0: /* ID codes. */
9ee6e8bb
PB		 1800 switch (op1) {
1801 case 0:
1802 switch (crm) {
1803 case 0:
1804 switch (op2) {
1805 case 0: /* Device ID. */
1806 return env->cp15.c0_cpuid;
1807 case 1: /* Cache Type. */
1808 return env->cp15.c0_cachetype;
1809 case 2: /* TCM status. */
1810 return 0;
1811 case 3: /* TLB type register. */
1812 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1813 case 5: /* MPIDR */
1814 /* The MPIDR was standardised in v7; prior to
1815 * this it was implemented only in the 11MPCore.
1816 * For all other pre-v7 cores it does not exist.
1817 */
1818 if (arm_feature(env, ARM_FEATURE_V7) ||
1819 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1820 int mpidr = env->cpu_index;
1821 /* We don't support setting cluster ID ([8..11])
1822 * so these bits always RAZ.
1823 */
1824 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1825 mpidr |= (1 << 31);
1826 /* Cores which are uniprocessor (non-coherent)
1827 * but still implement the MP extensions set
1828 * bit 30. (For instance, A9UP.) However we do
1829 * not currently model any of those cores.
1830 */
1831 }
1832 return mpidr;
10055562 1833 }
607b4b08 1834 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1835 default:
1836 goto bad_reg;
1837 }
1838 case 1:
1839 if (!arm_feature(env, ARM_FEATURE_V6))
1840 goto bad_reg;
1841 return env->cp15.c0_c1[op2];
1842 case 2:
1843 if (!arm_feature(env, ARM_FEATURE_V6))
1844 goto bad_reg;
1845 return env->cp15.c0_c2[op2];
1846 case 3: case 4: case 5: case 6: case 7:
1847 return 0;
1848 default:
1849 goto bad_reg;
1850 }
1851 case 1:
1852 /* These registers aren't documented on arm11 cores. However
1853 Linux looks at them anyway. */
1854 if (!arm_feature(env, ARM_FEATURE_V6))
1855 goto bad_reg;
1856 if (crm != 0)
1857 goto bad_reg;
a49ea279
PB		 1858 if (!arm_feature(env, ARM_FEATURE_V7))
1859 return 0;
1860
1861 switch (op2) {
1862 case 0:
1863 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1864 case 1:
1865 return env->cp15.c0_clid;
1866 case 7:
1867 return 0;
1868 }
1869 goto bad_reg;
1870 case 2:
1871 if (op2 != 0 || crm != 0)
610c3c8a 1872 goto bad_reg;
a49ea279 1873 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1874 default:
1875 goto bad_reg;
b5ff1b31
FB		 1876 }
1877 case 1: /* System configuration. */
2be27624
RH		 1878 if (arm_feature(env, ARM_FEATURE_V7)
1879 && op1 == 0 && crm == 1 && op2 == 0) {
1880 return env->cp15.c1_scr;
1881 }
c3d2689d
AZ		 1882 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1883 op2 = 0;
b5ff1b31
FB		 1884 switch (op2) {
1885 case 0: /* Control register. */
1886 return env->cp15.c1_sys;
1887 case 1: /* Auxiliary control register. */
c1713132 1888 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1889 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1890 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1891 goto bad_reg;
1892 switch (ARM_CPUID(env)) {
1893 case ARM_CPUID_ARM1026:
1894 return 1;
1895 case ARM_CPUID_ARM1136:
827df9f3 1896 case ARM_CPUID_ARM1136_R2:
7807eed9 1897 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1898 return 7;
1899 case ARM_CPUID_ARM11MPCORE:
1900 return 1;
1901 case ARM_CPUID_CORTEXA8:
533d177a 1902 return 2;
10055562 1903 case ARM_CPUID_CORTEXA9:
0b03bdfc 1904 case ARM_CPUID_CORTEXA15:
10055562 1905 return 0;
9ee6e8bb
PB		 1906 default:
1907 goto bad_reg;
1908 }
b5ff1b31 1909 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1910 if (arm_feature(env, ARM_FEATURE_XSCALE))
1911 goto bad_reg;
b5ff1b31
FB		 1912 return env->cp15.c1_coproc;
1913 default:
1914 goto bad_reg;
1915 }
ce819861
PB		 1916 case 2: /* MMU Page table control / MPU cache control. */
1917 if (arm_feature(env, ARM_FEATURE_MPU)) {
1918 switch (op2) {
1919 case 0:
1920 return env->cp15.c2_data;
1921 break;
1922 case 1:
1923 return env->cp15.c2_insn;
1924 break;
1925 default:
1926 goto bad_reg;
1927 }
1928 } else {
9ee6e8bb
PB		 1929 switch (op2) {
1930 case 0:
1931 return env->cp15.c2_base0;
1932 case 1:
1933 return env->cp15.c2_base1;
1934 case 2:
b2fa1797 1935 return env->cp15.c2_control;
9ee6e8bb
PB		 1936 default:
1937 goto bad_reg;
1938 }
1939 }
ce819861 1940 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1941 return env->cp15.c3;
1942 case 4: /* Reserved. */
1943 goto bad_reg;
ce819861 1944 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1945 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1946 op2 = 0;
b5ff1b31
FB		 1947 switch (op2) {
1948 case 0:
ce819861
PB		 1949 if (arm_feature(env, ARM_FEATURE_MPU))
1950 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1951 return env->cp15.c5_data;
1952 case 1:
ce819861 1953 if (arm_feature(env, ARM_FEATURE_MPU))
4de47793 1954 return simple_mpu_ap_bits(env->cp15.c5_insn);
ce819861
PB		 1955 return env->cp15.c5_insn;
1956 case 2:
1957 if (!arm_feature(env, ARM_FEATURE_MPU))
1958 goto bad_reg;
1959 return env->cp15.c5_data;
1960 case 3:
1961 if (!arm_feature(env, ARM_FEATURE_MPU))
1962 goto bad_reg;
b5ff1b31
FB		 1963 return env->cp15.c5_insn;
1964 default:
1965 goto bad_reg;
1966 }
9ee6e8bb 1967 case 6: /* MMU Fault address. */
ce819861 1968 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1969 if (crm >= 8)
ce819861 1970 goto bad_reg;
9ee6e8bb 1971 return env->cp15.c6_region[crm];
ce819861 1972 } else {
c3d2689d
AZ		 1973 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1974 op2 = 0;
9ee6e8bb
PB		 1975 switch (op2) {
1976 case 0:
1977 return env->cp15.c6_data;
1978 case 1:
1979 if (arm_feature(env, ARM_FEATURE_V6)) {
1980 /* Watchpoint Fault Adrress. */
1981 return 0; /* Not implemented. */
1982 } else {
1983 /* Instruction Fault Adrress. */
1984 /* Arm9 doesn't have an IFAR, but implementing it anyway
1985 shouldn't do any harm. */
1986 return env->cp15.c6_insn;
1987 }
1988 case 2:
1989 if (arm_feature(env, ARM_FEATURE_V6)) {
1990 /* Instruction Fault Adrress. */
1991 return env->cp15.c6_insn;
1992 } else {
1993 goto bad_reg;
1994 }
1995 default:
1996 goto bad_reg;
1997 }
b5ff1b31
FB		 1998 }
1999 case 7: /* Cache control. */
f8bf8606
AL		 2000 if (crm == 4 && op1 == 0 && op2 == 0) {
2001 return env->cp15.c7_par;
2002 }
6fbe23d5
PB		 2003 /* FIXME: Should only clear Z flag if destination is r15. */
2004 env->ZF = 0;
b5ff1b31
FB		 2005 return 0;
2006 case 8: /* MMU TLB control. */
2007 goto bad_reg;
74594c9d
PM		 2008 case 9:
2009 switch (crm) {
2010 case 0: /* Cache lockdown */
2011 switch (op1) {
2012 case 0: /* L1 cache. */
2013 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2014 return 0;
2015 }
2016 switch (op2) {
2017 case 0:
2018 return env->cp15.c9_data;
2019 case 1:
2020 return env->cp15.c9_insn;
2021 default:
2022 goto bad_reg;
2023 }
2024 case 1: /* L2 cache */
0b03bdfc
PM		 2025 /* L2 Lockdown and Auxiliary control. */
2026 switch (op2) {
2027 case 0:
2028 /* L2 cache lockdown (A8 only) */
2029 return 0;
2030 case 2:
2031 /* L2 cache auxiliary control (A8) or control (A15) */
2032 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
2033 /* Linux wants the number of processors from here.
2034 * Might as well set the interrupt-controller bit too.
2035 */
2036 return ((smp_cpus - 1) << 24) | (1 << 23);
2037 }
2038 return 0;
2039 case 3:
2040 /* L2 cache extended control (A15) */
2041 return 0;
2042 default:
74594c9d
PM		 2043 goto bad_reg;
2044 }
74594c9d
PM		 2045 default:
2046 goto bad_reg;
2047 }
2048 break;
b5ff1b31
FB		 2049 default:
2050 goto bad_reg;
2051 }
74594c9d 2052 break;
b5ff1b31
FB		 2053 case 10: /* MMU TLB lockdown. */
2054 /* ??? TLB lockdown not implemented. */
2055 return 0;
2056 case 11: /* TCM DMA control. */
2057 case 12: /* Reserved. */
2058 goto bad_reg;
2059 case 13: /* Process ID. */
2060 switch (op2) {
2061 case 0:
2062 return env->cp15.c13_fcse;
2063 case 1:
2064 return env->cp15.c13_context;
2065 default:
2066 goto bad_reg;
2067 }
0383ac00
PM		 2068 case 14: /* Generic timer */
2069 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2070 /* Dummy implementation: RAZ/WI for all */
2071 return 0;
2072 }
b5ff1b31
FB		 2073 goto bad_reg;
2074 case 15: /* Implementation specific. */
c1713132 2075 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2076 if (op2 == 0 && crm == 1)
c1713132
AZ		 2077 return env->cp15.c15_cpar;
2078
2079 goto bad_reg;
2080 }
c3d2689d
AZ		 2081 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2082 switch (crm) {
2083 case 0:
2084 return 0;
2085 case 1: /* Read TI925T configuration. */
2086 return env->cp15.c15_ticonfig;
2087 case 2: /* Read I_max. */
2088 return env->cp15.c15_i_max;
2089 case 3: /* Read I_min. */
2090 return env->cp15.c15_i_min;
2091 case 4: /* Read thread-ID. */
2092 return env->cp15.c15_threadid;
2093 case 8: /* TI925T_status */
2094 return 0;
2095 }
827df9f3
AZ		 2096 /* TODO: Peripheral port remap register:
2097 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2098 * controller base address at $rn & ~0xfff and map size of
2099 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2100 goto bad_reg;
2101 }
7da362d0
ML		 2102 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
2103 switch (crm) {
2104 case 0:
2105 if ((op1 == 4) && (op2 == 0)) {
2106 /* The config_base_address should hold the value of
2107 * the peripheral base. ARM should get this from a CPU
2108 * object property, but that support isn't available in
2109 * December 2011. Default to 0 for now and board models
2110 * that care can set it by a private hook */
2111 return env->cp15.c15_config_base_address;
2112 } else if ((op1 == 0) && (op2 == 0)) {
2113 /* power_control should be set to maximum latency. Again,
2114 default to 0 and set by private hook */
2115 return env->cp15.c15_power_control;
2116 } else if ((op1 == 0) && (op2 == 1)) {
2117 return env->cp15.c15_diagnostic;
2118 } else if ((op1 == 0) && (op2 == 2)) {
2119 return env->cp15.c15_power_diagnostic;
2120 }
2121 break;
2122 case 1: /* NEON Busy */
2123 return 0;
2124 case 5: /* tlb lockdown */
2125 case 6:
2126 case 7:
2127 if ((op1 == 5) && (op2 == 2)) {
2128 return 0;
2129 }
2130 break;
2131 default:
2132 break;
2133 }
2134 goto bad_reg;
2135 }
b5ff1b31
FB		 2136 return 0;
2137 }
2138bad_reg:
2139 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2140 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2141 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2142 return 0;
2143}
2144
0ecb72a5 2145void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2146{
39ea3d4e
PM		 2147 if ((env->uncached_cpsr & CPSR_M) == mode) {
2148 env->regs[13] = val;
2149 } else {
1b9e01c1 2150 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2151 }
9ee6e8bb
PB		 2152}
2153
0ecb72a5 2154uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2155{
39ea3d4e
PM		 2156 if ((env->uncached_cpsr & CPSR_M) == mode) {
2157 return env->regs[13];
2158 } else {
1b9e01c1 2159 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2160 }
9ee6e8bb
PB		 2161}
2162
0ecb72a5 2163uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2164{
2165 switch (reg) {
2166 case 0: /* APSR */
2167 return xpsr_read(env) & 0xf8000000;
2168 case 1: /* IAPSR */
2169 return xpsr_read(env) & 0xf80001ff;
2170 case 2: /* EAPSR */
2171 return xpsr_read(env) & 0xff00fc00;
2172 case 3: /* xPSR */
2173 return xpsr_read(env) & 0xff00fdff;
2174 case 5: /* IPSR */
2175 return xpsr_read(env) & 0x000001ff;
2176 case 6: /* EPSR */
2177 return xpsr_read(env) & 0x0700fc00;
2178 case 7: /* IEPSR */
2179 return xpsr_read(env) & 0x0700edff;
2180 case 8: /* MSP */
2181 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2182 case 9: /* PSP */
2183 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2184 case 16: /* PRIMASK */
2185 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2186 case 17: /* BASEPRI */
2187 case 18: /* BASEPRI_MAX */
9ee6e8bb 2188 return env->v7m.basepri;
82845826
SH		 2189 case 19: /* FAULTMASK */
2190 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2191 case 20: /* CONTROL */
2192 return env->v7m.control;
2193 default:
2194 /* ??? For debugging only. */
2195 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2196 return 0;
2197 }
2198}
2199
0ecb72a5 2200void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2201{
2202 switch (reg) {
2203 case 0: /* APSR */
2204 xpsr_write(env, val, 0xf8000000);
2205 break;
2206 case 1: /* IAPSR */
2207 xpsr_write(env, val, 0xf8000000);
2208 break;
2209 case 2: /* EAPSR */
2210 xpsr_write(env, val, 0xfe00fc00);
2211 break;
2212 case 3: /* xPSR */
2213 xpsr_write(env, val, 0xfe00fc00);
2214 break;
2215 case 5: /* IPSR */
2216 /* IPSR bits are readonly. */
2217 break;
2218 case 6: /* EPSR */
2219 xpsr_write(env, val, 0x0600fc00);
2220 break;
2221 case 7: /* IEPSR */
2222 xpsr_write(env, val, 0x0600fc00);
2223 break;
2224 case 8: /* MSP */
2225 if (env->v7m.current_sp)
2226 env->v7m.other_sp = val;
2227 else
2228 env->regs[13] = val;
2229 break;
2230 case 9: /* PSP */
2231 if (env->v7m.current_sp)
2232 env->regs[13] = val;
2233 else
2234 env->v7m.other_sp = val;
2235 break;
2236 case 16: /* PRIMASK */
2237 if (val & 1)
2238 env->uncached_cpsr |= CPSR_I;
2239 else
2240 env->uncached_cpsr &= ~CPSR_I;
2241 break;
82845826 2242 case 17: /* BASEPRI */
9ee6e8bb
PB		 2243 env->v7m.basepri = val & 0xff;
2244 break;
82845826 2245 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2246 val &= 0xff;
2247 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2248 env->v7m.basepri = val;
2249 break;
82845826
SH		 2250 case 19: /* FAULTMASK */
2251 if (val & 1)
2252 env->uncached_cpsr |= CPSR_F;
2253 else
2254 env->uncached_cpsr &= ~CPSR_F;
2255 break;
9ee6e8bb
PB		 2256 case 20: /* CONTROL */
2257 env->v7m.control = val & 3;
2258 switch_v7m_sp(env, (val & 2) != 0);
2259 break;
2260 default:
2261 /* ??? For debugging only. */
2262 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2263 return;
2264 }
2265}
2266
b5ff1b31 2267#endif
6ddbc6e4
PB		 2268
2269/* Note that signed overflow is undefined in C. The following routines are
2270 careful to use unsigned types where modulo arithmetic is required.
2271 Failure to do so _will_ break on newer gcc. */
2272
2273/* Signed saturating arithmetic. */
2274
1654b2d6 2275/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2276static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2277{
2278 uint16_t res;
2279
2280 res = a + b;
2281 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2282 if (a & 0x8000)
2283 res = 0x8000;
2284 else
2285 res = 0x7fff;
2286 }
2287 return res;
2288}
2289
1654b2d6 2290/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2291static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2292{
2293 uint8_t res;
2294
2295 res = a + b;
2296 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2297 if (a & 0x80)
2298 res = 0x80;
2299 else
2300 res = 0x7f;
2301 }
2302 return res;
2303}
2304
1654b2d6 2305/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2306static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2307{
2308 uint16_t res;
2309
2310 res = a - b;
2311 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2312 if (a & 0x8000)
2313 res = 0x8000;
2314 else
2315 res = 0x7fff;
2316 }
2317 return res;
2318}
2319
1654b2d6 2320/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2321static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2322{
2323 uint8_t res;
2324
2325 res = a - b;
2326 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2327 if (a & 0x80)
2328 res = 0x80;
2329 else
2330 res = 0x7f;
2331 }
2332 return res;
2333}
2334
2335#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2336#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2337#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2338#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2339#define PFX q
2340
2341#include "op_addsub.h"
2342
2343/* Unsigned saturating arithmetic. */
460a09c1 2344static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2345{
2346 uint16_t res;
2347 res = a + b;
2348 if (res < a)
2349 res = 0xffff;
2350 return res;
2351}
2352
460a09c1 2353static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2354{
4c4fd3f8 2355 if (a > b)
6ddbc6e4
PB		 2356 return a - b;
2357 else
2358 return 0;
2359}
2360
2361static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2362{
2363 uint8_t res;
2364 res = a + b;
2365 if (res < a)
2366 res = 0xff;
2367 return res;
2368}
2369
2370static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2371{
4c4fd3f8 2372 if (a > b)
6ddbc6e4
PB		 2373 return a - b;
2374 else
2375 return 0;
2376}
2377
2378#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2379#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2380#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2381#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2382#define PFX uq
2383
2384#include "op_addsub.h"
2385
2386/* Signed modulo arithmetic. */
2387#define SARITH16(a, b, n, op) do { \
2388 int32_t sum; \
db6e2e65 2389 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2390 RESULT(sum, n, 16); \
2391 if (sum >= 0) \
2392 ge |= 3 << (n * 2); \
2393 } while(0)
2394
2395#define SARITH8(a, b, n, op) do { \
2396 int32_t sum; \
db6e2e65 2397 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2398 RESULT(sum, n, 8); \
2399 if (sum >= 0) \
2400 ge |= 1 << n; \
2401 } while(0)
2402
2403
2404#define ADD16(a, b, n) SARITH16(a, b, n, +)
2405#define SUB16(a, b, n) SARITH16(a, b, n, -)
2406#define ADD8(a, b, n) SARITH8(a, b, n, +)
2407#define SUB8(a, b, n) SARITH8(a, b, n, -)
2408#define PFX s
2409#define ARITH_GE
2410
2411#include "op_addsub.h"
2412
2413/* Unsigned modulo arithmetic. */
2414#define ADD16(a, b, n) do { \
2415 uint32_t sum; \
2416 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2417 RESULT(sum, n, 16); \
a87aa10b 2418 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2419 ge |= 3 << (n * 2); \
2420 } while(0)
2421
2422#define ADD8(a, b, n) do { \
2423 uint32_t sum; \
2424 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2425 RESULT(sum, n, 8); \
a87aa10b
AZ		 2426 if ((sum >> 8) == 1) \
2427 ge |= 1 << n; \
6ddbc6e4
PB		 2428 } while(0)
2429
2430#define SUB16(a, b, n) do { \
2431 uint32_t sum; \
2432 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2433 RESULT(sum, n, 16); \
2434 if ((sum >> 16) == 0) \
2435 ge |= 3 << (n * 2); \
2436 } while(0)
2437
2438#define SUB8(a, b, n) do { \
2439 uint32_t sum; \
2440 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2441 RESULT(sum, n, 8); \
2442 if ((sum >> 8) == 0) \
a87aa10b 2443 ge |= 1 << n; \
6ddbc6e4
PB		 2444 } while(0)
2445
2446#define PFX u
2447#define ARITH_GE
2448
2449#include "op_addsub.h"
2450
2451/* Halved signed arithmetic. */
2452#define ADD16(a, b, n) \
2453 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2454#define SUB16(a, b, n) \
2455 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2456#define ADD8(a, b, n) \
2457 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2458#define SUB8(a, b, n) \
2459 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2460#define PFX sh
2461
2462#include "op_addsub.h"
2463
2464/* Halved unsigned arithmetic. */
2465#define ADD16(a, b, n) \
2466 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2467#define SUB16(a, b, n) \
2468 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2469#define ADD8(a, b, n) \
2470 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2471#define SUB8(a, b, n) \
2472 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2473#define PFX uh
2474
2475#include "op_addsub.h"
2476
2477static inline uint8_t do_usad(uint8_t a, uint8_t b)
2478{
2479 if (a > b)
2480 return a - b;
2481 else
2482 return b - a;
2483}
2484
2485/* Unsigned sum of absolute byte differences. */
2486uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2487{
2488 uint32_t sum;
2489 sum = do_usad(a, b);
2490 sum += do_usad(a >> 8, b >> 8);
2491 sum += do_usad(a >> 16, b >>16);
2492 sum += do_usad(a >> 24, b >> 24);
2493 return sum;
2494}
2495
2496/* For ARMv6 SEL instruction. */
2497uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2498{
2499 uint32_t mask;
2500
2501 mask = 0;
2502 if (flags & 1)
2503 mask |= 0xff;
2504 if (flags & 2)
2505 mask |= 0xff00;
2506 if (flags & 4)
2507 mask |= 0xff0000;
2508 if (flags & 8)
2509 mask |= 0xff000000;
2510 return (a & mask) | (b & ~mask);
2511}
2512
5e3f878a
PB		 2513uint32_t HELPER(logicq_cc)(uint64_t val)
2514{
2515 return (val >> 32) | (val != 0);
2516}
4373f3ce
PB		 2517
2518/* VFP support. We follow the convention used for VFP instrunctions:
2519 Single precition routines have a "s" suffix, double precision a
2520 "d" suffix. */
2521
2522/* Convert host exception flags to vfp form. */
2523static inline int vfp_exceptbits_from_host(int host_bits)
2524{
2525 int target_bits = 0;
2526
2527 if (host_bits & float_flag_invalid)
2528 target_bits |= 1;
2529 if (host_bits & float_flag_divbyzero)
2530 target_bits |= 2;
2531 if (host_bits & float_flag_overflow)
2532 target_bits |= 4;
36802b6b 2533 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2534 target_bits |= 8;
2535 if (host_bits & float_flag_inexact)
2536 target_bits |= 0x10;
cecd8504
PM		 2537 if (host_bits & float_flag_input_denormal)
2538 target_bits |= 0x80;
4373f3ce
PB		 2539 return target_bits;
2540}
2541
0ecb72a5 2542uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2543{
2544 int i;
2545 uint32_t fpscr;
2546
2547 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2548 | (env->vfp.vec_len << 16)
2549 | (env->vfp.vec_stride << 20);
2550 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2551 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2552 fpscr |= vfp_exceptbits_from_host(i);
2553 return fpscr;
2554}
2555
0ecb72a5 2556uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2557{
2558 return HELPER(vfp_get_fpscr)(env);
2559}
2560
4373f3ce
PB		 2561/* Convert vfp exception flags to target form. */
2562static inline int vfp_exceptbits_to_host(int target_bits)
2563{
2564 int host_bits = 0;
2565
2566 if (target_bits & 1)
2567 host_bits |= float_flag_invalid;
2568 if (target_bits & 2)
2569 host_bits |= float_flag_divbyzero;
2570 if (target_bits & 4)
2571 host_bits |= float_flag_overflow;
2572 if (target_bits & 8)
2573 host_bits |= float_flag_underflow;
2574 if (target_bits & 0x10)
2575 host_bits |= float_flag_inexact;
cecd8504
PM		 2576 if (target_bits & 0x80)
2577 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2578 return host_bits;
2579}
2580
0ecb72a5 2581void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2582{
2583 int i;
2584 uint32_t changed;
2585
2586 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2587 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2588 env->vfp.vec_len = (val >> 16) & 7;
2589 env->vfp.vec_stride = (val >> 20) & 3;
2590
2591 changed ^= val;
2592 if (changed & (3 << 22)) {
2593 i = (val >> 22) & 3;
2594 switch (i) {
2595 case 0:
2596 i = float_round_nearest_even;
2597 break;
2598 case 1:
2599 i = float_round_up;
2600 break;
2601 case 2:
2602 i = float_round_down;
2603 break;
2604 case 3:
2605 i = float_round_to_zero;
2606 break;
2607 }
2608 set_float_rounding_mode(i, &env->vfp.fp_status);
2609 }
cecd8504 2610 if (changed & (1 << 24)) {
fe76d976 2611 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2612 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2613 }
5c7908ed
PB		 2614 if (changed & (1 << 25))
2615 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2616
b12c390b 2617 i = vfp_exceptbits_to_host(val);
4373f3ce 2618 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2619 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2620}
2621
0ecb72a5 2622void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2623{
2624 HELPER(vfp_set_fpscr)(env, val);
2625}
2626
4373f3ce
PB		 2627#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2628
2629#define VFP_BINOP(name) \
ae1857ec 2630float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2631{ \
ae1857ec
PM		 2632 float_status *fpst = fpstp; \
2633 return float32_ ## name(a, b, fpst); \
4373f3ce 2634} \
ae1857ec 2635float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2636{ \
ae1857ec
PM		 2637 float_status *fpst = fpstp; \
2638 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2639}
2640VFP_BINOP(add)
2641VFP_BINOP(sub)
2642VFP_BINOP(mul)
2643VFP_BINOP(div)
2644#undef VFP_BINOP
2645
2646float32 VFP_HELPER(neg, s)(float32 a)
2647{
2648 return float32_chs(a);
2649}
2650
2651float64 VFP_HELPER(neg, d)(float64 a)
2652{
66230e0d 2653 return float64_chs(a);
4373f3ce
PB		 2654}
2655
2656float32 VFP_HELPER(abs, s)(float32 a)
2657{
2658 return float32_abs(a);
2659}
2660
2661float64 VFP_HELPER(abs, d)(float64 a)
2662{
66230e0d 2663 return float64_abs(a);
4373f3ce
PB		 2664}
2665
0ecb72a5 2666float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2667{
2668 return float32_sqrt(a, &env->vfp.fp_status);
2669}
2670
0ecb72a5 2671float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2672{
2673 return float64_sqrt(a, &env->vfp.fp_status);
2674}
2675
2676/* XXX: check quiet/signaling case */
2677#define DO_VFP_cmp(p, type) \
0ecb72a5 2678void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2679{ \
2680 uint32_t flags; \
2681 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2682 case 0: flags = 0x6; break; \
2683 case -1: flags = 0x8; break; \
2684 case 1: flags = 0x2; break; \
2685 default: case 2: flags = 0x3; break; \
2686 } \
2687 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2688 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2689} \
0ecb72a5 2690void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2691{ \
2692 uint32_t flags; \
2693 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2694 case 0: flags = 0x6; break; \
2695 case -1: flags = 0x8; break; \
2696 case 1: flags = 0x2; break; \
2697 default: case 2: flags = 0x3; break; \
2698 } \
2699 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2700 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2701}
2702DO_VFP_cmp(s, float32)
2703DO_VFP_cmp(d, float64)
2704#undef DO_VFP_cmp
2705
5500b06c 2706/* Integer to float and float to integer conversions */
4373f3ce 2707
5500b06c
PM		 2708#define CONV_ITOF(name, fsz, sign) \
2709 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2710{ \
2711 float_status *fpst = fpstp; \
85836979 2712 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2713}
2714
5500b06c
PM		 2715#define CONV_FTOI(name, fsz, sign, round) \
2716uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2717{ \
2718 float_status *fpst = fpstp; \
2719 if (float##fsz##_is_any_nan(x)) { \
2720 float_raise(float_flag_invalid, fpst); \
2721 return 0; \
2722 } \
2723 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2724}
2725
5500b06c
PM		 2726#define FLOAT_CONVS(name, p, fsz, sign) \
2727CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2728CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2729CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2730
5500b06c
PM		 2731FLOAT_CONVS(si, s, 32, )
2732FLOAT_CONVS(si, d, 64, )
2733FLOAT_CONVS(ui, s, 32, u)
2734FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2735
5500b06c
PM		 2736#undef CONV_ITOF
2737#undef CONV_FTOI
2738#undef FLOAT_CONVS
4373f3ce
PB		 2739
2740/* floating point conversion */
0ecb72a5 2741float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2742{
2d627737
PM		 2743 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2744 /* ARM requires that S<->D conversion of any kind of NaN generates
2745 * a quiet NaN by forcing the most significant frac bit to 1.
2746 */
2747 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2748}
2749
0ecb72a5 2750float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2751{
2d627737
PM		 2752 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2753 /* ARM requires that S<->D conversion of any kind of NaN generates
2754 * a quiet NaN by forcing the most significant frac bit to 1.
2755 */
2756 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2757}
2758
2759/* VFP3 fixed point conversion. */
622465e1 2760#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2761float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2762 void *fpstp) \
4373f3ce 2763{ \
5500b06c 2764 float_status *fpst = fpstp; \
622465e1 2765 float##fsz tmp; \
5500b06c
PM		 2766 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2767 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2768} \
5500b06c
PM		 2769uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2770 void *fpstp) \
4373f3ce 2771{ \
5500b06c 2772 float_status *fpst = fpstp; \
622465e1
PM		 2773 float##fsz tmp; \
2774 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2775 float_raise(float_flag_invalid, fpst); \
622465e1 2776 return 0; \
09d9487f 2777 } \
5500b06c
PM		 2778 tmp = float##fsz##_scalbn(x, shift, fpst); \
2779 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2780}
2781
2782VFP_CONV_FIX(sh, d, 64, int16, )
2783VFP_CONV_FIX(sl, d, 64, int32, )
2784VFP_CONV_FIX(uh, d, 64, uint16, u)
2785VFP_CONV_FIX(ul, d, 64, uint32, u)
2786VFP_CONV_FIX(sh, s, 32, int16, )
2787VFP_CONV_FIX(sl, s, 32, int32, )
2788VFP_CONV_FIX(uh, s, 32, uint16, u)
2789VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2790#undef VFP_CONV_FIX
2791
60011498 2792/* Half precision conversions. */
0ecb72a5 2793static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2794{
60011498 2795 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2796 float32 r = float16_to_float32(make_float16(a), ieee, s);
2797 if (ieee) {
2798 return float32_maybe_silence_nan(r);
2799 }
2800 return r;
60011498
PB		 2801}
2802
0ecb72a5 2803static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2804{
60011498 2805 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2806 float16 r = float32_to_float16(a, ieee, s);
2807 if (ieee) {
2808 r = float16_maybe_silence_nan(r);
2809 }
2810 return float16_val(r);
60011498
PB		 2811}
2812
0ecb72a5 2813float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2814{
2815 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2816}
2817
0ecb72a5 2818uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2819{
2820 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2821}
2822
0ecb72a5 2823float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2824{
2825 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2826}
2827
0ecb72a5 2828uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2829{
2830 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2831}
2832
dda3ec49 2833#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2834#define float32_three make_float32(0x40400000)
2835#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2836
0ecb72a5 2837float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2838{
dda3ec49
PM		 2839 float_status *s = &env->vfp.standard_fp_status;
2840 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2841 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2842 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2843 float_raise(float_flag_input_denormal, s);
2844 }
dda3ec49
PM		 2845 return float32_two;
2846 }
2847 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2848}
2849
0ecb72a5 2850float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2851{
71826966 2852 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2853 float32 product;
2854 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2855 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2856 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2857 float_raise(float_flag_input_denormal, s);
2858 }
6aae3df1 2859 return float32_one_point_five;
9ea62f57 2860 }
6aae3df1
PM		 2861 product = float32_mul(a, b, s);
2862 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2863}
2864
8f8e3aa4
PB		 2865/* NEON helpers. */
2866
56bf4fe2
CL		 2867/* Constants 256 and 512 are used in some helpers; we avoid relying on
2868 * int->float conversions at run-time. */
2869#define float64_256 make_float64(0x4070000000000000LL)
2870#define float64_512 make_float64(0x4080000000000000LL)
2871
fe0e4872
CL		 2872/* The algorithm that must be used to calculate the estimate
2873 * is specified by the ARM ARM.
2874 */
0ecb72a5 2875static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2876{
1146a817
PM		 2877 /* These calculations mustn't set any fp exception flags,
2878 * so we use a local copy of the fp_status.
2879 */
2880 float_status dummy_status = env->vfp.standard_fp_status;
2881 float_status *s = &dummy_status;
fe0e4872
CL		 2882 /* q = (int)(a * 512.0) */
2883 float64 q = float64_mul(float64_512, a, s);
2884 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2885
2886 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2887 q = int64_to_float64(q_int, s);
2888 q = float64_add(q, float64_half, s);
2889 q = float64_div(q, float64_512, s);
2890 q = float64_div(float64_one, q, s);
2891
2892 /* s = (int)(256.0 * r + 0.5) */
2893 q = float64_mul(q, float64_256, s);
2894 q = float64_add(q, float64_half, s);
2895 q_int = float64_to_int64_round_to_zero(q, s);
2896
2897 /* return (double)s / 256.0 */
2898 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2899}
2900
0ecb72a5 2901float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2902{
fe0e4872
CL		 2903 float_status *s = &env->vfp.standard_fp_status;
2904 float64 f64;
2905 uint32_t val32 = float32_val(a);
2906
2907 int result_exp;
2908 int a_exp = (val32 & 0x7f800000) >> 23;
2909 int sign = val32 & 0x80000000;
2910
2911 if (float32_is_any_nan(a)) {
2912 if (float32_is_signaling_nan(a)) {
2913 float_raise(float_flag_invalid, s);
2914 }
2915 return float32_default_nan;
2916 } else if (float32_is_infinity(a)) {
2917 return float32_set_sign(float32_zero, float32_is_neg(a));
2918 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2919 if (!float32_is_zero(a)) {
2920 float_raise(float_flag_input_denormal, s);
2921 }
fe0e4872
CL		 2922 float_raise(float_flag_divbyzero, s);
2923 return float32_set_sign(float32_infinity, float32_is_neg(a));
2924 } else if (a_exp >= 253) {
2925 float_raise(float_flag_underflow, s);
2926 return float32_set_sign(float32_zero, float32_is_neg(a));
2927 }
2928
2929 f64 = make_float64((0x3feULL << 52)
2930 | ((int64_t)(val32 & 0x7fffff) << 29));
2931
2932 result_exp = 253 - a_exp;
2933
2934 f64 = recip_estimate(f64, env);
2935
2936 val32 = sign
2937 | ((result_exp & 0xff) << 23)
2938 | ((float64_val(f64) >> 29) & 0x7fffff);
2939 return make_float32(val32);
4373f3ce
PB		 2940}
2941
e07be5d2
CL		 2942/* The algorithm that must be used to calculate the estimate
2943 * is specified by the ARM ARM.
2944 */
0ecb72a5 2945static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2946{
1146a817
PM		 2947 /* These calculations mustn't set any fp exception flags,
2948 * so we use a local copy of the fp_status.
2949 */
2950 float_status dummy_status = env->vfp.standard_fp_status;
2951 float_status *s = &dummy_status;
e07be5d2
CL		 2952 float64 q;
2953 int64_t q_int;
2954
2955 if (float64_lt(a, float64_half, s)) {
2956 /* range 0.25 <= a < 0.5 */
2957
2958 /* a in units of 1/512 rounded down */
2959 /* q0 = (int)(a * 512.0); */
2960 q = float64_mul(float64_512, a, s);
2961 q_int = float64_to_int64_round_to_zero(q, s);
2962
2963 /* reciprocal root r */
2964 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2965 q = int64_to_float64(q_int, s);
2966 q = float64_add(q, float64_half, s);
2967 q = float64_div(q, float64_512, s);
2968 q = float64_sqrt(q, s);
2969 q = float64_div(float64_one, q, s);
2970 } else {
2971 /* range 0.5 <= a < 1.0 */
2972
2973 /* a in units of 1/256 rounded down */
2974 /* q1 = (int)(a * 256.0); */
2975 q = float64_mul(float64_256, a, s);
2976 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2977
2978 /* reciprocal root r */
2979 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2980 q = int64_to_float64(q_int, s);
2981 q = float64_add(q, float64_half, s);
2982 q = float64_div(q, float64_256, s);
2983 q = float64_sqrt(q, s);
2984 q = float64_div(float64_one, q, s);
2985 }
2986 /* r in units of 1/256 rounded to nearest */
2987 /* s = (int)(256.0 * r + 0.5); */
2988
2989 q = float64_mul(q, float64_256,s );
2990 q = float64_add(q, float64_half, s);
2991 q_int = float64_to_int64_round_to_zero(q, s);
2992
2993 /* return (double)s / 256.0;*/
2994 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2995}
2996
0ecb72a5 2997float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 2998{
e07be5d2
CL		 2999 float_status *s = &env->vfp.standard_fp_status;
3000 int result_exp;
3001 float64 f64;
3002 uint32_t val;
3003 uint64_t val64;
3004
3005 val = float32_val(a);
3006
3007 if (float32_is_any_nan(a)) {
3008 if (float32_is_signaling_nan(a)) {
3009 float_raise(float_flag_invalid, s);
3010 }
3011 return float32_default_nan;
3012 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3013 if (!float32_is_zero(a)) {
3014 float_raise(float_flag_input_denormal, s);
3015 }
e07be5d2
CL		 3016 float_raise(float_flag_divbyzero, s);
3017 return float32_set_sign(float32_infinity, float32_is_neg(a));
3018 } else if (float32_is_neg(a)) {
3019 float_raise(float_flag_invalid, s);
3020 return float32_default_nan;
3021 } else if (float32_is_infinity(a)) {
3022 return float32_zero;
3023 }
3024
3025 /* Normalize to a double-precision value between 0.25 and 1.0,
3026 * preserving the parity of the exponent. */
3027 if ((val & 0x800000) == 0) {
3028 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3029 | (0x3feULL << 52)
3030 | ((uint64_t)(val & 0x7fffff) << 29));
3031 } else {
3032 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3033 | (0x3fdULL << 52)
3034 | ((uint64_t)(val & 0x7fffff) << 29));
3035 }
3036
3037 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3038
3039 f64 = recip_sqrt_estimate(f64, env);
3040
3041 val64 = float64_val(f64);
3042
26cc6abf 3043 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3044 | ((val64 >> 29) & 0x7fffff);
3045 return make_float32(val);
4373f3ce
PB		 3046}
3047
0ecb72a5 3048uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3049{
fe0e4872
CL		 3050 float64 f64;
3051
3052 if ((a & 0x80000000) == 0) {
3053 return 0xffffffff;
3054 }
3055
3056 f64 = make_float64((0x3feULL << 52)
3057 | ((int64_t)(a & 0x7fffffff) << 21));
3058
3059 f64 = recip_estimate (f64, env);
3060
3061 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3062}
3063
0ecb72a5 3064uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3065{
e07be5d2
CL		 3066 float64 f64;
3067
3068 if ((a & 0xc0000000) == 0) {
3069 return 0xffffffff;
3070 }
3071
3072 if (a & 0x80000000) {
3073 f64 = make_float64((0x3feULL << 52)
3074 | ((uint64_t)(a & 0x7fffffff) << 21));
3075 } else { /* bits 31-30 == '01' */
3076 f64 = make_float64((0x3fdULL << 52)
3077 | ((uint64_t)(a & 0x3fffffff) << 22));
3078 }
3079
3080 f64 = recip_sqrt_estimate(f64, env);
3081
3082 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3083}
fe1479c3 3084
da97f52c
PM		 3085/* VFPv4 fused multiply-accumulate */
3086float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3087{
3088 float_status *fpst = fpstp;
3089 return float32_muladd(a, b, c, 0, fpst);
3090}
3091
3092float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3093{
3094 float_status *fpst = fpstp;
3095 return float64_muladd(a, b, c, 0, fpst);
3096}
Qemu copy for testing