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target-i386: check/enforce: Check SVM flag support as well
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
98static const char *kvm_feature_name[] = {
c3d39807
DS		 99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 107};
108
296acb64
JR		 109static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118};
119
a9321a4d 120static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125};
126
8b4beddc
EH		 127const char *get_register_name_32(unsigned int reg)
128{
129 static const char *reg_names[CPU_NB_REGS32] = {
130 [R_EAX] = "EAX",
131 [R_ECX] = "ECX",
132 [R_EDX] = "EDX",
133 [R_EBX] = "EBX",
134 [R_ESP] = "ESP",
135 [R_EBP] = "EBP",
136 [R_ESI] = "ESI",
137 [R_EDI] = "EDI",
138 };
139
140 if (reg > CPU_NB_REGS32) {
141 return NULL;
142 }
143 return reg_names[reg];
144}
145
c6dc6f63
AP		 146/* collects per-function cpuid data
147 */
148typedef struct model_features_t {
149 uint32_t *guest_feat;
150 uint32_t *host_feat;
151 uint32_t check_feat;
152 const char **flag_names;
153 uint32_t cpuid;
8b4beddc
EH		 154 int reg;
155} model_features_t;
c6dc6f63
AP		 156
157int check_cpuid = 0;
158int enforce_cpuid = 0;
159
dc59944b
MT		 160#if defined(CONFIG_KVM)
161static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
162 (1 << KVM_FEATURE_NOP_IO_DELAY) |
163 (1 << KVM_FEATURE_MMU_OP) |
164 (1 << KVM_FEATURE_CLOCKSOURCE2) |
165 (1 << KVM_FEATURE_ASYNC_PF) |
166 (1 << KVM_FEATURE_STEAL_TIME) |
167 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
168static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
169#else
170static uint32_t kvm_default_features = 0;
171static const uint32_t kvm_pv_eoi_features = 0;
172#endif
173
174void enable_kvm_pv_eoi(void)
175{
176 kvm_default_features |= kvm_pv_eoi_features;
177}
178
bb44e0d1
JK		 179void host_cpuid(uint32_t function, uint32_t count,
180 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 181{
182#if defined(CONFIG_KVM)
a1fd24af
AL		 183 uint32_t vec[4];
184
185#ifdef __x86_64__
186 asm volatile("cpuid"
187 : "=a"(vec[0]), "=b"(vec[1]),
188 "=c"(vec[2]), "=d"(vec[3])
189 : "0"(function), "c"(count) : "cc");
190#else
191 asm volatile("pusha \n\t"
192 "cpuid \n\t"
193 "mov %%eax, 0(%2) \n\t"
194 "mov %%ebx, 4(%2) \n\t"
195 "mov %%ecx, 8(%2) \n\t"
196 "mov %%edx, 12(%2) \n\t"
197 "popa"
198 : : "a"(function), "c"(count), "S"(vec)
199 : "memory", "cc");
200#endif
201
bdde476a 202 if (eax)
a1fd24af 203 *eax = vec[0];
bdde476a 204 if (ebx)
a1fd24af 205 *ebx = vec[1];
bdde476a 206 if (ecx)
a1fd24af 207 *ecx = vec[2];
bdde476a 208 if (edx)
a1fd24af 209 *edx = vec[3];
bdde476a
AP		 210#endif
211}
c6dc6f63
AP		 212
213#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
214
215/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
216 * a substring. ex if !NULL points to the first char after a substring,
217 * otherwise the string is assumed to sized by a terminating nul.
218 * Return lexical ordering of *s1:*s2.
219 */
220static int sstrcmp(const char *s1, const char *e1, const char *s2,
221 const char *e2)
222{
223 for (;;) {
224 if (!*s1 || !*s2 || *s1 != *s2)
225 return (*s1 - *s2);
226 ++s1, ++s2;
227 if (s1 == e1 && s2 == e2)
228 return (0);
229 else if (s1 == e1)
230 return (*s2);
231 else if (s2 == e2)
232 return (*s1);
233 }
234}
235
236/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
237 * '|' delimited (possibly empty) strings in which case search for a match
238 * within the alternatives proceeds left to right. Return 0 for success,
239 * non-zero otherwise.
240 */
241static int altcmp(const char *s, const char *e, const char *altstr)
242{
243 const char *p, *q;
244
245 for (q = p = altstr; ; ) {
246 while (*p && *p != '|')
247 ++p;
248 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
249 return (0);
250 if (!*p)
251 return (1);
252 else
253 q = ++p;
254 }
255}
256
257/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 258 * *pval and return true, otherwise return false
c6dc6f63 259 */
e41e0fc6
JK		 260static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
261 const char **featureset)
c6dc6f63
AP		 262{
263 uint32_t mask;
264 const char **ppc;
e41e0fc6 265 bool found = false;
c6dc6f63 266
e41e0fc6 267 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 268 if (*ppc && !altcmp(s, e, *ppc)) {
269 *pval |= mask;
e41e0fc6 270 found = true;
c6dc6f63 271 }
e41e0fc6
JK		 272 }
273 return found;
c6dc6f63
AP		 274}
275
276static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
277 uint32_t *ext_features,
278 uint32_t *ext2_features,
279 uint32_t *ext3_features,
296acb64 280 uint32_t *kvm_features,
a9321a4d
PA		 281 uint32_t *svm_features,
282 uint32_t *cpuid_7_0_ebx_features)
c6dc6f63
AP		 283{
284 if (!lookup_feature(features, flagname, NULL, feature_name) &&
285 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
286 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
287 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64 288 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
a9321a4d
PA		 289 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
290 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
291 cpuid_7_0_ebx_feature_name))
c6dc6f63
AP		 292 fprintf(stderr, "CPU feature %s not found\n", flagname);
293}
294
295typedef struct x86_def_t {
296 struct x86_def_t *next;
297 const char *name;
298 uint32_t level;
299 uint32_t vendor1, vendor2, vendor3;
300 int family;
301 int model;
302 int stepping;
b862d1fe 303 int tsc_khz;
296acb64
JR		 304 uint32_t features, ext_features, ext2_features, ext3_features;
305 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 306 uint32_t xlevel;
307 char model_id[48];
308 int vendor_override;
b3baa152 309 /* Store the results of Centaur's CPUID instructions */
310 uint32_t ext4_features;
311 uint32_t xlevel2;
13526728
EH		 312 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
313 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 314} x86_def_t;
315
316#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
317#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
318 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
319#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
320 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
321 CPUID_PSE36 | CPUID_FXSR)
322#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
323#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
324 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
325 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
326 CPUID_PAE | CPUID_SEP | CPUID_APIC)
327
551a2dec
AP		 328#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
329 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
330 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
331 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
332 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 333 /* partly implemented:
334 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
335 CPUID_PSE36 (needed for Solaris) */
336 /* missing:
337 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 338#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 339 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 340 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 341 /* missing:
342 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 343 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 344#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 345 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
346 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 347 /* missing:
348 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 349#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
350 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 351#define TCG_SVM_FEATURES 0
a9321a4d 352#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 353
c6dc6f63
AP		 354/* maintains list of cpu model definitions
355 */
356static x86_def_t *x86_defs = {NULL};
357
358/* built-in cpu model definitions (deprecated)
359 */
360static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 361 {
362 .name = "qemu64",
363 .level = 4,
364 .vendor1 = CPUID_VENDOR_AMD_1,
365 .vendor2 = CPUID_VENDOR_AMD_2,
366 .vendor3 = CPUID_VENDOR_AMD_3,
367 .family = 6,
368 .model = 2,
369 .stepping = 3,
370 .features = PPRO_FEATURES |
c6dc6f63 371 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 372 CPUID_PSE36,
373 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 374 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 375 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
376 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
377 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
378 .xlevel = 0x8000000A,
c6dc6f63
AP		 379 },
380 {
381 .name = "phenom",
382 .level = 5,
383 .vendor1 = CPUID_VENDOR_AMD_1,
384 .vendor2 = CPUID_VENDOR_AMD_2,
385 .vendor3 = CPUID_VENDOR_AMD_3,
386 .family = 16,
387 .model = 2,
388 .stepping = 3,
c6dc6f63
AP		 389 .features = PPRO_FEATURES |
390 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 391 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 392 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
393 CPUID_EXT_POPCNT,
60032ac0 394 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 395 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
396 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 397 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 398 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
399 CPUID_EXT3_CR8LEG,
400 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
401 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
402 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
403 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 404 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 405 .xlevel = 0x8000001A,
406 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
407 },
408 {
409 .name = "core2duo",
410 .level = 10,
411 .family = 6,
412 .model = 15,
413 .stepping = 11,
c6dc6f63
AP		 414 .features = PPRO_FEATURES |
415 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 416 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
417 CPUID_HT | CPUID_TM | CPUID_PBE,
418 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
419 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
420 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 421 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
422 .ext3_features = CPUID_EXT3_LAHF_LM,
423 .xlevel = 0x80000008,
424 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
425 },
426 {
427 .name = "kvm64",
428 .level = 5,
429 .vendor1 = CPUID_VENDOR_INTEL_1,
430 .vendor2 = CPUID_VENDOR_INTEL_2,
431 .vendor3 = CPUID_VENDOR_INTEL_3,
432 .family = 15,
433 .model = 6,
434 .stepping = 1,
435 /* Missing: CPUID_VME, CPUID_HT */
436 .features = PPRO_FEATURES |
437 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
438 CPUID_PSE36,
439 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
440 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
441 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 442 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 443 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
444 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
445 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
446 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
447 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
448 .ext3_features = 0,
449 .xlevel = 0x80000008,
450 .model_id = "Common KVM processor"
451 },
c6dc6f63
AP		 452 {
453 .name = "qemu32",
454 .level = 4,
455 .family = 6,
456 .model = 3,
457 .stepping = 3,
458 .features = PPRO_FEATURES,
459 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 460 .xlevel = 0x80000004,
c6dc6f63 461 },
eafaf1e5
AP		 462 {
463 .name = "kvm32",
464 .level = 5,
465 .family = 15,
466 .model = 6,
467 .stepping = 1,
468 .features = PPRO_FEATURES |
469 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
470 .ext_features = CPUID_EXT_SSE3,
60032ac0 471 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 472 .ext3_features = 0,
473 .xlevel = 0x80000008,
474 .model_id = "Common 32-bit KVM processor"
475 },
c6dc6f63
AP		 476 {
477 .name = "coreduo",
478 .level = 10,
479 .family = 6,
480 .model = 14,
481 .stepping = 8,
c6dc6f63 482 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
484 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
485 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
486 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 487 .ext2_features = CPUID_EXT2_NX,
488 .xlevel = 0x80000008,
489 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
490 },
491 {
492 .name = "486",
58012d66 493 .level = 1,
c6dc6f63
AP		 494 .family = 4,
495 .model = 0,
496 .stepping = 0,
497 .features = I486_FEATURES,
498 .xlevel = 0,
499 },
500 {
501 .name = "pentium",
502 .level = 1,
503 .family = 5,
504 .model = 4,
505 .stepping = 3,
506 .features = PENTIUM_FEATURES,
507 .xlevel = 0,
508 },
509 {
510 .name = "pentium2",
511 .level = 2,
512 .family = 6,
513 .model = 5,
514 .stepping = 2,
515 .features = PENTIUM2_FEATURES,
516 .xlevel = 0,
517 },
518 {
519 .name = "pentium3",
520 .level = 2,
521 .family = 6,
522 .model = 7,
523 .stepping = 3,
524 .features = PENTIUM3_FEATURES,
525 .xlevel = 0,
526 },
527 {
528 .name = "athlon",
529 .level = 2,
530 .vendor1 = CPUID_VENDOR_AMD_1,
531 .vendor2 = CPUID_VENDOR_AMD_2,
532 .vendor3 = CPUID_VENDOR_AMD_3,
533 .family = 6,
534 .model = 2,
535 .stepping = 3,
60032ac0
EH		 536 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
537 CPUID_MCA,
538 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
539 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 540 .xlevel = 0x80000008,
c6dc6f63
AP		 541 },
542 {
543 .name = "n270",
544 /* original is on level 10 */
545 .level = 5,
546 .family = 6,
547 .model = 28,
548 .stepping = 2,
549 .features = PPRO_FEATURES |
8560efed
AJ		 550 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
551 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 552 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 553 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
554 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 555 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
556 CPUID_EXT2_NX,
8560efed 557 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 558 .xlevel = 0x8000000A,
559 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
560 },
3eca4642
EH		 561 {
562 .name = "Conroe",
563 .level = 2,
564 .vendor1 = CPUID_VENDOR_INTEL_1,
565 .vendor2 = CPUID_VENDOR_INTEL_2,
566 .vendor3 = CPUID_VENDOR_INTEL_3,
567 .family = 6,
568 .model = 2,
569 .stepping = 3,
570 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
571 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
572 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
573 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
574 CPUID_DE | CPUID_FP87,
575 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
580 },
581 {
582 .name = "Penryn",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
596 CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
601 },
602 {
603 .name = "Nehalem",
604 .level = 2,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 2,
610 .stepping = 3,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
617 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
618 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
619 .ext3_features = CPUID_EXT3_LAHF_LM,
620 .xlevel = 0x8000000A,
621 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
622 },
623 {
624 .name = "Westmere",
625 .level = 11,
626 .vendor1 = CPUID_VENDOR_INTEL_1,
627 .vendor2 = CPUID_VENDOR_INTEL_2,
628 .vendor3 = CPUID_VENDOR_INTEL_3,
629 .family = 6,
630 .model = 44,
631 .stepping = 1,
632 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
633 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
634 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
635 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
636 CPUID_DE | CPUID_FP87,
637 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
638 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
639 CPUID_EXT_SSE3,
640 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
641 .ext3_features = CPUID_EXT3_LAHF_LM,
642 .xlevel = 0x8000000A,
643 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
644 },
645 {
646 .name = "SandyBridge",
647 .level = 0xd,
648 .vendor1 = CPUID_VENDOR_INTEL_1,
649 .vendor2 = CPUID_VENDOR_INTEL_2,
650 .vendor3 = CPUID_VENDOR_INTEL_3,
651 .family = 6,
652 .model = 42,
653 .stepping = 1,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
660 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
661 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
662 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
663 CPUID_EXT_SSE3,
664 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
665 CPUID_EXT2_SYSCALL,
666 .ext3_features = CPUID_EXT3_LAHF_LM,
667 .xlevel = 0x8000000A,
668 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
669 },
37507094
EH		 670 {
671 .name = "Haswell",
672 .level = 0xd,
673 .vendor1 = CPUID_VENDOR_INTEL_1,
674 .vendor2 = CPUID_VENDOR_INTEL_2,
675 .vendor3 = CPUID_VENDOR_INTEL_3,
676 .family = 6,
677 .model = 60,
678 .stepping = 1,
679 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
683 CPUID_DE | CPUID_FP87,
684 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
685 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
686 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
687 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
688 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
689 CPUID_EXT_PCID,
80ae4160
EH		 690 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
691 CPUID_EXT2_SYSCALL,
37507094
EH		 692 .ext3_features = CPUID_EXT3_LAHF_LM,
693 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
694 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
695 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
696 CPUID_7_0_EBX_RTM,
697 .xlevel = 0x8000000A,
698 .model_id = "Intel Core Processor (Haswell)",
699 },
3eca4642
EH		 700 {
701 .name = "Opteron_G1",
702 .level = 5,
703 .vendor1 = CPUID_VENDOR_AMD_1,
704 .vendor2 = CPUID_VENDOR_AMD_2,
705 .vendor3 = CPUID_VENDOR_AMD_3,
706 .family = 15,
707 .model = 6,
708 .stepping = 1,
709 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
710 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
711 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
712 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
713 CPUID_DE | CPUID_FP87,
714 .ext_features = CPUID_EXT_SSE3,
715 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
716 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
717 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
718 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
719 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
720 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
721 .xlevel = 0x80000008,
722 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
723 },
724 {
725 .name = "Opteron_G2",
726 .level = 5,
727 .vendor1 = CPUID_VENDOR_AMD_1,
728 .vendor2 = CPUID_VENDOR_AMD_2,
729 .vendor3 = CPUID_VENDOR_AMD_3,
730 .family = 15,
731 .model = 6,
732 .stepping = 1,
733 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
734 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
735 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
736 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
737 CPUID_DE | CPUID_FP87,
738 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
739 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
740 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
741 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
742 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
743 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
744 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
745 CPUID_EXT2_DE | CPUID_EXT2_FPU,
746 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
747 .xlevel = 0x80000008,
748 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
749 },
750 {
751 .name = "Opteron_G3",
752 .level = 5,
753 .vendor1 = CPUID_VENDOR_AMD_1,
754 .vendor2 = CPUID_VENDOR_AMD_2,
755 .vendor3 = CPUID_VENDOR_AMD_3,
756 .family = 15,
757 .model = 6,
758 .stepping = 1,
759 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
763 CPUID_DE | CPUID_FP87,
764 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
765 CPUID_EXT_SSE3,
766 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
767 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
768 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
769 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
770 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
771 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
772 CPUID_EXT2_DE | CPUID_EXT2_FPU,
773 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
774 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
775 .xlevel = 0x80000008,
776 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
777 },
778 {
779 .name = "Opteron_G4",
780 .level = 0xd,
781 .vendor1 = CPUID_VENDOR_AMD_1,
782 .vendor2 = CPUID_VENDOR_AMD_2,
783 .vendor3 = CPUID_VENDOR_AMD_3,
784 .family = 21,
785 .model = 1,
786 .stepping = 2,
787 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
788 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
789 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
790 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
791 CPUID_DE | CPUID_FP87,
792 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
793 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
794 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
795 CPUID_EXT_SSE3,
796 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
797 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
798 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
799 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
800 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
801 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
802 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
803 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
804 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
805 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
806 CPUID_EXT3_LAHF_LM,
807 .xlevel = 0x8000001A,
808 .model_id = "AMD Opteron 62xx class CPU",
809 },
021941b9
AP		 810 {
811 .name = "Opteron_G5",
812 .level = 0xd,
813 .vendor1 = CPUID_VENDOR_AMD_1,
814 .vendor2 = CPUID_VENDOR_AMD_2,
815 .vendor3 = CPUID_VENDOR_AMD_3,
816 .family = 21,
817 .model = 2,
818 .stepping = 0,
819 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
823 CPUID_DE | CPUID_FP87,
824 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
825 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
826 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
827 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
828 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
829 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
830 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
831 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
832 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
833 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
834 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
835 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
836 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
837 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
838 CPUID_EXT3_LAHF_LM,
839 .xlevel = 0x8000001A,
840 .model_id = "AMD Opteron 63xx class CPU",
841 },
c6dc6f63
AP		 842};
843
e4ab0d6b 844#ifdef CONFIG_KVM
c6dc6f63
AP		 845static int cpu_x86_fill_model_id(char *str)
846{
847 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
848 int i;
849
850 for (i = 0; i < 3; i++) {
851 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
852 memcpy(str + i * 16 + 0, &eax, 4);
853 memcpy(str + i * 16 + 4, &ebx, 4);
854 memcpy(str + i * 16 + 8, &ecx, 4);
855 memcpy(str + i * 16 + 12, &edx, 4);
856 }
857 return 0;
858}
e4ab0d6b 859#endif
c6dc6f63 860
6e746f30
EH		 861/* Fill a x86_def_t struct with information about the host CPU, and
862 * the CPU features supported by the host hardware + host kernel
863 *
864 * This function may be called only if KVM is enabled.
865 */
866static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 867{
e4ab0d6b 868#ifdef CONFIG_KVM
12869995 869 KVMState *s = kvm_state;
c6dc6f63
AP		 870 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
871
6e746f30
EH		 872 assert(kvm_enabled());
873
c6dc6f63
AP		 874 x86_cpu_def->name = "host";
875 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 876 x86_cpu_def->vendor1 = ebx;
877 x86_cpu_def->vendor2 = edx;
878 x86_cpu_def->vendor3 = ecx;
879
880 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
881 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
882 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
883 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 884
12869995
EH		 885 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
886 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
887 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 888
6e746f30 889 if (x86_cpu_def->level >= 7) {
12869995
EH		 890 x86_cpu_def->cpuid_7_0_ebx_features =
891 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 892 } else {
893 x86_cpu_def->cpuid_7_0_ebx_features = 0;
894 }
895
12869995
EH		 896 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
897 x86_cpu_def->ext2_features =
898 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
899 x86_cpu_def->ext3_features =
900 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 901
c6dc6f63
AP		 902 cpu_x86_fill_model_id(x86_cpu_def->model_id);
903 x86_cpu_def->vendor_override = 0;
904
b3baa152 905 /* Call Centaur's CPUID instruction. */
906 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
907 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
908 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
909 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 910 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152 911 if (eax >= 0xC0000001) {
912 /* Support VIA max extended level */
913 x86_cpu_def->xlevel2 = eax;
914 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 915 x86_cpu_def->ext4_features =
916 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152 917 }
918 }
296acb64 919
fcb93c03
EH		 920 /* Other KVM-specific feature fields: */
921 x86_cpu_def->svm_features =
922 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 923 x86_cpu_def->kvm_features =
924 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 925
e4ab0d6b 926#endif /* CONFIG_KVM */
c6dc6f63
AP		 927}
928
929static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
930{
931 int i;
932
933 for (i = 0; i < 32; ++i)
934 if (1 << i & mask) {
8b4beddc
EH		 935 const char *reg = get_register_name_32(f->reg);
936 assert(reg);
937 fprintf(stderr, "warning: host doesn't support requested feature: "
938 "CPUID.%02XH:%s%s%s [bit %d]\n",
939 f->cpuid, reg,
940 f->flag_names[i] ? "." : "",
941 f->flag_names[i] ? f->flag_names[i] : "", i);
c6dc6f63
AP		 942 break;
943 }
944 return 0;
945}
946
947/* best effort attempt to inform user requested cpu flags aren't making
948 * their way to the guest. Note: ft[].check_feat ideally should be
949 * specified via a guest_def field to suppress report of extraneous flags.
6e746f30
EH		 950 *
951 * This function may be called only if KVM is enabled.
c6dc6f63 952 */
6e746f30 953static int kvm_check_features_against_host(x86_def_t *guest_def)
c6dc6f63
AP		 954{
955 x86_def_t host_def;
956 uint32_t mask;
957 int rv, i;
958 struct model_features_t ft[] = {
959 {&guest_def->features, &host_def.features,
8b4beddc 960 ~0, feature_name, 0x00000001, R_EDX},
c6dc6f63 961 {&guest_def->ext_features, &host_def.ext_features,
54830ff8 962 ~0, ext_feature_name, 0x00000001, R_ECX},
c6dc6f63 963 {&guest_def->ext2_features, &host_def.ext2_features,
22714625 964 ~0, ext2_feature_name, 0x80000001, R_EDX},
c6dc6f63 965 {&guest_def->ext3_features, &host_def.ext3_features,
396d2cfc 966 ~0, ext3_feature_name, 0x80000001, R_ECX}
8b4beddc 967 };
c6dc6f63 968
6e746f30
EH		 969 assert(kvm_enabled());
970
971 kvm_cpu_fill_host(&host_def);
66fe09ee 972 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 973 for (mask = 1; mask; mask <<= 1)
974 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
975 !(*ft[i].host_feat & mask)) {
976 unavailable_host_feature(&ft[i], mask);
977 rv = 1;
978 }
979 return rv;
980}
981
95b8519d
AF		 982static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
983 const char *name, Error **errp)
984{
985 X86CPU *cpu = X86_CPU(obj);
986 CPUX86State *env = &cpu->env;
987 int64_t value;
988
989 value = (env->cpuid_version >> 8) & 0xf;
990 if (value == 0xf) {
991 value += (env->cpuid_version >> 20) & 0xff;
992 }
993 visit_type_int(v, &value, name, errp);
994}
995
71ad61d3
AF		 996static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
997 const char *name, Error **errp)
ed5e1ec3 998{
71ad61d3
AF		 999 X86CPU *cpu = X86_CPU(obj);
1000 CPUX86State *env = &cpu->env;
1001 const int64_t min = 0;
1002 const int64_t max = 0xff + 0xf;
1003 int64_t value;
1004
1005 visit_type_int(v, &value, name, errp);
1006 if (error_is_set(errp)) {
1007 return;
1008 }
1009 if (value < min || value > max) {
1010 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1011 name ? name : "null", value, min, max);
1012 return;
1013 }
1014
ed5e1ec3 1015 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1016 if (value > 0x0f) {
1017 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1018 } else {
71ad61d3 1019 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1020 }
1021}
1022
67e30c83
AF		 1023static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1024 const char *name, Error **errp)
1025{
1026 X86CPU *cpu = X86_CPU(obj);
1027 CPUX86State *env = &cpu->env;
1028 int64_t value;
1029
1030 value = (env->cpuid_version >> 4) & 0xf;
1031 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1032 visit_type_int(v, &value, name, errp);
1033}
1034
c5291a4f
AF		 1035static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1036 const char *name, Error **errp)
b0704cbd 1037{
c5291a4f
AF		 1038 X86CPU *cpu = X86_CPU(obj);
1039 CPUX86State *env = &cpu->env;
1040 const int64_t min = 0;
1041 const int64_t max = 0xff;
1042 int64_t value;
1043
1044 visit_type_int(v, &value, name, errp);
1045 if (error_is_set(errp)) {
1046 return;
1047 }
1048 if (value < min || value > max) {
1049 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1050 name ? name : "null", value, min, max);
1051 return;
1052 }
1053
b0704cbd 1054 env->cpuid_version &= ~0xf00f0;
c5291a4f 1055 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1056}
1057
35112e41
AF		 1058static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1059 void *opaque, const char *name,
1060 Error **errp)
1061{
1062 X86CPU *cpu = X86_CPU(obj);
1063 CPUX86State *env = &cpu->env;
1064 int64_t value;
1065
1066 value = env->cpuid_version & 0xf;
1067 visit_type_int(v, &value, name, errp);
1068}
1069
036e2222
AF		 1070static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1071 void *opaque, const char *name,
1072 Error **errp)
38c3dc46 1073{
036e2222
AF		 1074 X86CPU *cpu = X86_CPU(obj);
1075 CPUX86State *env = &cpu->env;
1076 const int64_t min = 0;
1077 const int64_t max = 0xf;
1078 int64_t value;
1079
1080 visit_type_int(v, &value, name, errp);
1081 if (error_is_set(errp)) {
1082 return;
1083 }
1084 if (value < min || value > max) {
1085 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1086 name ? name : "null", value, min, max);
1087 return;
1088 }
1089
38c3dc46 1090 env->cpuid_version &= ~0xf;
036e2222 1091 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1092}
1093
8e1898bf
AF		 1094static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1095 const char *name, Error **errp)
1096{
1097 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1098
fa029887 1099 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1100}
1101
1102static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1103 const char *name, Error **errp)
1104{
1105 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1106
fa029887 1107 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1108}
1109
16b93aa8
AF		 1110static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1111 const char *name, Error **errp)
1112{
1113 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1114
fa029887 1115 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1116}
1117
1118static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1119 const char *name, Error **errp)
1120{
1121 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1122
fa029887 1123 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1124}
1125
d480e1af
AF		 1126static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1127{
1128 X86CPU *cpu = X86_CPU(obj);
1129 CPUX86State *env = &cpu->env;
1130 char *value;
1131 int i;
1132
9df694ee 1133 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1134 for (i = 0; i < 4; i++) {
1135 value[i ] = env->cpuid_vendor1 >> (8 * i);
1136 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1137 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1138 }
9df694ee 1139 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1140 return value;
1141}
1142
1143static void x86_cpuid_set_vendor(Object *obj, const char *value,
1144 Error **errp)
1145{
1146 X86CPU *cpu = X86_CPU(obj);
1147 CPUX86State *env = &cpu->env;
1148 int i;
1149
9df694ee 1150 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1151 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1152 "vendor", value);
1153 return;
1154 }
1155
1156 env->cpuid_vendor1 = 0;
1157 env->cpuid_vendor2 = 0;
1158 env->cpuid_vendor3 = 0;
1159 for (i = 0; i < 4; i++) {
1160 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1161 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1162 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1163 }
1164 env->cpuid_vendor_override = 1;
1165}
1166
63e886eb
AF		 1167static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1168{
1169 X86CPU *cpu = X86_CPU(obj);
1170 CPUX86State *env = &cpu->env;
1171 char *value;
1172 int i;
1173
1174 value = g_malloc(48 + 1);
1175 for (i = 0; i < 48; i++) {
1176 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1177 }
1178 value[48] = '\0';
1179 return value;
1180}
1181
938d4c25
AF		 1182static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1183 Error **errp)
dcce6675 1184{
938d4c25
AF		 1185 X86CPU *cpu = X86_CPU(obj);
1186 CPUX86State *env = &cpu->env;
dcce6675
AF		 1187 int c, len, i;
1188
1189 if (model_id == NULL) {
1190 model_id = "";
1191 }
1192 len = strlen(model_id);
d0a6acf4 1193 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1194 for (i = 0; i < 48; i++) {
1195 if (i >= len) {
1196 c = '\0';
1197 } else {
1198 c = (uint8_t)model_id[i];
1199 }
1200 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1201 }
1202}
1203
89e48965
AF		 1204static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1205 const char *name, Error **errp)
1206{
1207 X86CPU *cpu = X86_CPU(obj);
1208 int64_t value;
1209
1210 value = cpu->env.tsc_khz * 1000;
1211 visit_type_int(v, &value, name, errp);
1212}
1213
1214static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1215 const char *name, Error **errp)
1216{
1217 X86CPU *cpu = X86_CPU(obj);
1218 const int64_t min = 0;
2e84849a 1219 const int64_t max = INT64_MAX;
89e48965
AF		 1220 int64_t value;
1221
1222 visit_type_int(v, &value, name, errp);
1223 if (error_is_set(errp)) {
1224 return;
1225 }
1226 if (value < min || value > max) {
1227 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1228 name ? name : "null", value, min, max);
1229 return;
1230 }
1231
1232 cpu->env.tsc_khz = value / 1000;
1233}
1234
8f961357 1235static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1236{
c6dc6f63
AP		 1237 x86_def_t *def;
1238
9f3fb565
EH		 1239 for (def = x86_defs; def; def = def->next) {
1240 if (name && !strcmp(name, def->name)) {
c6dc6f63 1241 break;
9f3fb565
EH		 1242 }
1243 }
04c5b17a 1244 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1245 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1246 } else if (!def) {
8f961357 1247 return -1;
c6dc6f63
AP		 1248 } else {
1249 memcpy(x86_cpu_def, def, sizeof(*def));
1250 }
1251
8f961357
EH		 1252 return 0;
1253}
1254
1255/* Parse "+feature,-feature,feature=foo" CPU feature string
1256 */
1257static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1258{
1259 unsigned int i;
1260 char *featurestr; /* Single 'key=value" string being parsed */
1261 /* Features to be added */
1262 uint32_t plus_features = 0, plus_ext_features = 0;
1263 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1264 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1265 uint32_t plus_7_0_ebx_features = 0;
1266 /* Features to be removed */
1267 uint32_t minus_features = 0, minus_ext_features = 0;
1268 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1269 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1270 uint32_t minus_7_0_ebx_features = 0;
1271 uint32_t numvalue;
1272
c6dc6f63 1273 add_flagname_to_bitmaps("hypervisor", &plus_features,
a9321a4d
PA		 1274 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1275 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
c6dc6f63 1276
8f961357 1277 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1278
1279 while (featurestr) {
1280 char *val;
1281 if (featurestr[0] == '+') {
296acb64
JR		 1282 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1283 &plus_ext_features, &plus_ext2_features,
1284 &plus_ext3_features, &plus_kvm_features,
a9321a4d 1285 &plus_svm_features, &plus_7_0_ebx_features);
c6dc6f63 1286 } else if (featurestr[0] == '-') {
296acb64
JR		 1287 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1288 &minus_ext_features, &minus_ext2_features,
1289 &minus_ext3_features, &minus_kvm_features,
a9321a4d 1290 &minus_svm_features, &minus_7_0_ebx_features);
c6dc6f63
AP		 1291 } else if ((val = strchr(featurestr, '='))) {
1292 *val = 0; val++;
1293 if (!strcmp(featurestr, "family")) {
1294 char *err;
1295 numvalue = strtoul(val, &err, 0);
a88a677f 1296 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1297 fprintf(stderr, "bad numerical value %s\n", val);
1298 goto error;
1299 }
1300 x86_cpu_def->family = numvalue;
1301 } else if (!strcmp(featurestr, "model")) {
1302 char *err;
1303 numvalue = strtoul(val, &err, 0);
1304 if (!*val || *err || numvalue > 0xff) {
1305 fprintf(stderr, "bad numerical value %s\n", val);
1306 goto error;
1307 }
1308 x86_cpu_def->model = numvalue;
1309 } else if (!strcmp(featurestr, "stepping")) {
1310 char *err;
1311 numvalue = strtoul(val, &err, 0);
1312 if (!*val || *err || numvalue > 0xf) {
1313 fprintf(stderr, "bad numerical value %s\n", val);
1314 goto error;
1315 }
1316 x86_cpu_def->stepping = numvalue ;
1317 } else if (!strcmp(featurestr, "level")) {
1318 char *err;
1319 numvalue = strtoul(val, &err, 0);
1320 if (!*val || *err) {
1321 fprintf(stderr, "bad numerical value %s\n", val);
1322 goto error;
1323 }
1324 x86_cpu_def->level = numvalue;
1325 } else if (!strcmp(featurestr, "xlevel")) {
1326 char *err;
1327 numvalue = strtoul(val, &err, 0);
1328 if (!*val || *err) {
1329 fprintf(stderr, "bad numerical value %s\n", val);
1330 goto error;
1331 }
1332 if (numvalue < 0x80000000) {
2f7a21c4 1333 numvalue += 0x80000000;
c6dc6f63
AP		 1334 }
1335 x86_cpu_def->xlevel = numvalue;
1336 } else if (!strcmp(featurestr, "vendor")) {
1337 if (strlen(val) != 12) {
1338 fprintf(stderr, "vendor string must be 12 chars long\n");
1339 goto error;
1340 }
1341 x86_cpu_def->vendor1 = 0;
1342 x86_cpu_def->vendor2 = 0;
1343 x86_cpu_def->vendor3 = 0;
1344 for(i = 0; i < 4; i++) {
1345 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1346 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1347 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1348 }
1349 x86_cpu_def->vendor_override = 1;
1350 } else if (!strcmp(featurestr, "model_id")) {
1351 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1352 val);
b862d1fe
JR		 1353 } else if (!strcmp(featurestr, "tsc_freq")) {
1354 int64_t tsc_freq;
1355 char *err;
1356
1357 tsc_freq = strtosz_suffix_unit(val, &err,
1358 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1359 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1360 fprintf(stderr, "bad numerical value %s\n", val);
1361 goto error;
1362 }
1363 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1364 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1365 char *err;
1366 numvalue = strtoul(val, &err, 0);
1367 if (!*val || *err) {
1368 fprintf(stderr, "bad numerical value %s\n", val);
1369 goto error;
1370 }
1371 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1372 } else {
1373 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1374 goto error;
1375 }
1376 } else if (!strcmp(featurestr, "check")) {
1377 check_cpuid = 1;
1378 } else if (!strcmp(featurestr, "enforce")) {
1379 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1380 } else if (!strcmp(featurestr, "hv_relaxed")) {
1381 hyperv_enable_relaxed_timing(true);
1382 } else if (!strcmp(featurestr, "hv_vapic")) {
1383 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1384 } else {
1385 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1386 goto error;
1387 }
1388 featurestr = strtok(NULL, ",");
1389 }
1390 x86_cpu_def->features |= plus_features;
1391 x86_cpu_def->ext_features |= plus_ext_features;
1392 x86_cpu_def->ext2_features |= plus_ext2_features;
1393 x86_cpu_def->ext3_features |= plus_ext3_features;
1394 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1395 x86_cpu_def->svm_features |= plus_svm_features;
a9321a4d 1396 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
c6dc6f63
AP		 1397 x86_cpu_def->features &= ~minus_features;
1398 x86_cpu_def->ext_features &= ~minus_ext_features;
1399 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1400 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1401 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1402 x86_cpu_def->svm_features &= ~minus_svm_features;
a9321a4d 1403 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
6e746f30
EH		 1404 if (check_cpuid && kvm_enabled()) {
1405 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
c6dc6f63
AP		 1406 goto error;
1407 }
c6dc6f63
AP		 1408 return 0;
1409
1410error:
c6dc6f63
AP		 1411 return -1;
1412}
1413
1414/* generate a composite string into buf of all cpuid names in featureset
1415 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1416 * if flags, suppress names undefined in featureset.
1417 */
1418static void listflags(char *buf, int bufsize, uint32_t fbits,
1419 const char **featureset, uint32_t flags)
1420{
1421 const char **p = &featureset[31];
1422 char *q, *b, bit;
1423 int nc;
1424
1425 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1426 *buf = '\0';
1427 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1428 if (fbits & 1 << bit && (*p || !flags)) {
1429 if (*p)
1430 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1431 else
1432 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1433 if (bufsize <= nc) {
1434 if (b) {
1435 memcpy(b, "...", sizeof("..."));
1436 }
1437 return;
1438 }
1439 q += nc;
1440 bufsize -= nc;
1441 }
1442}
1443
e916cbf8
PM		 1444/* generate CPU information. */
1445void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1446{
c6dc6f63
AP		 1447 x86_def_t *def;
1448 char buf[256];
1449
c6dc6f63 1450 for (def = x86_defs; def; def = def->next) {
c04321b3 1451 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1452 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1453 }
ed2c54d4
AP		 1454 if (kvm_enabled()) {
1455 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1456 }
6cdf8854
PM		 1457 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1458 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1459 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1460 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1461 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1462 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1463 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1464 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1465 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1466}
1467
76b64a7a 1468CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1469{
1470 CpuDefinitionInfoList *cpu_list = NULL;
1471 x86_def_t *def;
1472
1473 for (def = x86_defs; def; def = def->next) {
1474 CpuDefinitionInfoList *entry;
1475 CpuDefinitionInfo *info;
1476
1477 info = g_malloc0(sizeof(*info));
1478 info->name = g_strdup(def->name);
1479
1480 entry = g_malloc0(sizeof(*entry));
1481 entry->value = info;
1482 entry->next = cpu_list;
1483 cpu_list = entry;
1484 }
1485
1486 return cpu_list;
1487}
1488
bc74b7db
EH		 1489#ifdef CONFIG_KVM
1490static void filter_features_for_kvm(X86CPU *cpu)
1491{
1492 CPUX86State *env = &cpu->env;
1493 KVMState *s = kvm_state;
1494
b8091f24
EH		 1495 env->cpuid_features &=
1496 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1497 env->cpuid_ext_features &=
1498 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1499 env->cpuid_ext2_features &=
1500 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1501 env->cpuid_ext3_features &=
1502 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1503 env->cpuid_svm_features &=
1504 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1505 env->cpuid_7_0_ebx_features &=
1506 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1507 env->cpuid_kvm_features &=
b8091f24
EH		 1508 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1509 env->cpuid_ext4_features &=
1510 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1511
1512}
1513#endif
1514
61dcd775 1515int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1516{
61dcd775 1517 CPUX86State *env = &cpu->env;
c6dc6f63 1518 x86_def_t def1, *def = &def1;
71ad61d3 1519 Error *error = NULL;
8f961357
EH		 1520 char *name, *features;
1521 gchar **model_pieces;
c6dc6f63 1522
db0ad1ba
JR		 1523 memset(def, 0, sizeof(*def));
1524
8f961357
EH		 1525 model_pieces = g_strsplit(cpu_model, ",", 2);
1526 if (!model_pieces[0]) {
1527 goto error;
1528 }
1529 name = model_pieces[0];
1530 features = model_pieces[1];
1531
1532 if (cpu_x86_find_by_name(def, name) < 0) {
1533 goto error;
1534 }
1535
1536 if (cpu_x86_parse_featurestr(def, features) < 0) {
1537 goto error;
1538 }
c6dc6f63
AP		 1539 if (def->vendor1) {
1540 env->cpuid_vendor1 = def->vendor1;
1541 env->cpuid_vendor2 = def->vendor2;
1542 env->cpuid_vendor3 = def->vendor3;
1543 } else {
1544 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1545 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1546 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1547 }
1548 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1549 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1550 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1551 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1552 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1553 env->cpuid_features = def->features;
c6dc6f63
AP		 1554 env->cpuid_ext_features = def->ext_features;
1555 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1556 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1557 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1558 env->cpuid_kvm_features = def->kvm_features;
296acb64 1559 env->cpuid_svm_features = def->svm_features;
b3baa152 1560 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1561 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1562 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1563 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1564 "tsc-frequency", &error);
3b671a40
EH		 1565
1566 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1567 * CPUID[1].EDX.
1568 */
1569 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1570 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1571 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1572 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1573 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1574 }
1575
551a2dec
AP		 1576 if (!kvm_enabled()) {
1577 env->cpuid_features &= TCG_FEATURES;
1578 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1579 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1580#ifdef TARGET_X86_64
1581 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1582#endif
1583 );
1584 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1585 env->cpuid_svm_features &= TCG_SVM_FEATURES;
bc74b7db
EH		 1586 } else {
1587#ifdef CONFIG_KVM
1588 filter_features_for_kvm(cpu);
1589#endif
551a2dec 1590 }
938d4c25 1591 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
18eb473f
IM		 1592 if (error) {
1593 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1594 error_free(error);
8f961357 1595 goto error;
71ad61d3 1596 }
8f961357
EH		 1597
1598 g_strfreev(model_pieces);
c6dc6f63 1599 return 0;
8f961357
EH		 1600error:
1601 g_strfreev(model_pieces);
1602 return -1;
c6dc6f63
AP		 1603}
1604
1605#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1606
0e26b7b8
BS		 1607void cpu_clear_apic_feature(CPUX86State *env)
1608{
1609 env->cpuid_features &= ~CPUID_APIC;
1610}
1611
c6dc6f63
AP		 1612#endif /* !CONFIG_USER_ONLY */
1613
c04321b3 1614/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1615 */
1616void x86_cpudef_setup(void)
1617{
93bfef4c
CV		 1618 int i, j;
1619 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1620
1621 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1622 x86_def_t *def = &builtin_x86_defs[i];
1623 def->next = x86_defs;
93bfef4c
CV		 1624
1625 /* Look for specific "cpudef" models that */
09faecf2 1626 /* have the QEMU version in .model_id */
93bfef4c 1627 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1628 if (strcmp(model_with_versions[j], def->name) == 0) {
1629 pstrcpy(def->model_id, sizeof(def->model_id),
1630 "QEMU Virtual CPU version ");
1631 pstrcat(def->model_id, sizeof(def->model_id),
1632 qemu_get_version());
93bfef4c
CV		 1633 break;
1634 }
1635 }
1636
bc3e1291 1637 x86_defs = def;
c6dc6f63 1638 }
c6dc6f63
AP		 1639}
1640
c6dc6f63
AP		 1641static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1642 uint32_t *ecx, uint32_t *edx)
1643{
1644 *ebx = env->cpuid_vendor1;
1645 *edx = env->cpuid_vendor2;
1646 *ecx = env->cpuid_vendor3;
1647
1648 /* sysenter isn't supported on compatibility mode on AMD, syscall
1649 * isn't supported in compatibility mode on Intel.
1650 * Normally we advertise the actual cpu vendor, but you can override
1651 * this if you want to use KVM's sysenter/syscall emulation
1652 * in compatibility mode and when doing cross vendor migration
1653 */
89354998 1654 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1655 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1656 }
1657}
1658
1659void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1660 uint32_t *eax, uint32_t *ebx,
1661 uint32_t *ecx, uint32_t *edx)
1662{
a60f24b5
AF		 1663 X86CPU *cpu = x86_env_get_cpu(env);
1664 CPUState *cs = CPU(cpu);
1665
c6dc6f63
AP		 1666 /* test if maximum index reached */
1667 if (index & 0x80000000) {
b3baa152 1668 if (index > env->cpuid_xlevel) {
1669 if (env->cpuid_xlevel2 > 0) {
1670 /* Handle the Centaur's CPUID instruction. */
1671 if (index > env->cpuid_xlevel2) {
1672 index = env->cpuid_xlevel2;
1673 } else if (index < 0xC0000000) {
1674 index = env->cpuid_xlevel;
1675 }
1676 } else {
57f26ae7
EH		 1677 /* Intel documentation states that invalid EAX input will
1678 * return the same information as EAX=cpuid_level
1679 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1680 */
1681 index = env->cpuid_level;
b3baa152 1682 }
1683 }
c6dc6f63
AP		 1684 } else {
1685 if (index > env->cpuid_level)
1686 index = env->cpuid_level;
1687 }
1688
1689 switch(index) {
1690 case 0:
1691 *eax = env->cpuid_level;
1692 get_cpuid_vendor(env, ebx, ecx, edx);
1693 break;
1694 case 1:
1695 *eax = env->cpuid_version;
1696 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1697 *ecx = env->cpuid_ext_features;
1698 *edx = env->cpuid_features;
1699 if (env->nr_cores * env->nr_threads > 1) {
1700 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1701 *edx |= 1 << 28; /* HTT bit */
1702 }
1703 break;
1704 case 2:
1705 /* cache info: needed for Pentium Pro compatibility */
1706 *eax = 1;
1707 *ebx = 0;
1708 *ecx = 0;
1709 *edx = 0x2c307d;
1710 break;
1711 case 4:
1712 /* cache info: needed for Core compatibility */
1713 if (env->nr_cores > 1) {
2f7a21c4 1714 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1715 } else {
2f7a21c4 1716 *eax = 0;
c6dc6f63
AP		 1717 }
1718 switch (count) {
1719 case 0: /* L1 dcache info */
1720 *eax |= 0x0000121;
1721 *ebx = 0x1c0003f;
1722 *ecx = 0x000003f;
1723 *edx = 0x0000001;
1724 break;
1725 case 1: /* L1 icache info */
1726 *eax |= 0x0000122;
1727 *ebx = 0x1c0003f;
1728 *ecx = 0x000003f;
1729 *edx = 0x0000001;
1730 break;
1731 case 2: /* L2 cache info */
1732 *eax |= 0x0000143;
1733 if (env->nr_threads > 1) {
1734 *eax |= (env->nr_threads - 1) << 14;
1735 }
1736 *ebx = 0x3c0003f;
1737 *ecx = 0x0000fff;
1738 *edx = 0x0000001;
1739 break;
1740 default: /* end of info */
1741 *eax = 0;
1742 *ebx = 0;
1743 *ecx = 0;
1744 *edx = 0;
1745 break;
1746 }
1747 break;
1748 case 5:
1749 /* mwait info: needed for Core compatibility */
1750 *eax = 0; /* Smallest monitor-line size in bytes */
1751 *ebx = 0; /* Largest monitor-line size in bytes */
1752 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1753 *edx = 0;
1754 break;
1755 case 6:
1756 /* Thermal and Power Leaf */
1757 *eax = 0;
1758 *ebx = 0;
1759 *ecx = 0;
1760 *edx = 0;
1761 break;
f7911686 1762 case 7:
13526728
EH		 1763 /* Structured Extended Feature Flags Enumeration Leaf */
1764 if (count == 0) {
1765 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1766 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1767 *ecx = 0; /* Reserved */
1768 *edx = 0; /* Reserved */
f7911686
YW		 1769 } else {
1770 *eax = 0;
1771 *ebx = 0;
1772 *ecx = 0;
1773 *edx = 0;
1774 }
1775 break;
c6dc6f63
AP		 1776 case 9:
1777 /* Direct Cache Access Information Leaf */
1778 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1779 *ebx = 0;
1780 *ecx = 0;
1781 *edx = 0;
1782 break;
1783 case 0xA:
1784 /* Architectural Performance Monitoring Leaf */
a0fa8208 1785 if (kvm_enabled()) {
a60f24b5 1786 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1787
1788 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1789 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1790 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1791 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1792 } else {
1793 *eax = 0;
1794 *ebx = 0;
1795 *ecx = 0;
1796 *edx = 0;
1797 }
c6dc6f63 1798 break;
51e49430
SY		 1799 case 0xD:
1800 /* Processor Extended State */
1801 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1802 *eax = 0;
1803 *ebx = 0;
1804 *ecx = 0;
1805 *edx = 0;
1806 break;
1807 }
1808 if (kvm_enabled()) {
a60f24b5 1809 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1810
1811 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1812 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1813 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1814 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1815 } else {
1816 *eax = 0;
1817 *ebx = 0;
1818 *ecx = 0;
1819 *edx = 0;
1820 }
1821 break;
c6dc6f63
AP		 1822 case 0x80000000:
1823 *eax = env->cpuid_xlevel;
1824 *ebx = env->cpuid_vendor1;
1825 *edx = env->cpuid_vendor2;
1826 *ecx = env->cpuid_vendor3;
1827 break;
1828 case 0x80000001:
1829 *eax = env->cpuid_version;
1830 *ebx = 0;
1831 *ecx = env->cpuid_ext3_features;
1832 *edx = env->cpuid_ext2_features;
1833
1834 /* The Linux kernel checks for the CMPLegacy bit and
1835 * discards multiple thread information if it is set.
1836 * So dont set it here for Intel to make Linux guests happy.
1837 */
1838 if (env->nr_cores * env->nr_threads > 1) {
1839 uint32_t tebx, tecx, tedx;
1840 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1841 if (tebx != CPUID_VENDOR_INTEL_1 ||
1842 tedx != CPUID_VENDOR_INTEL_2 ||
1843 tecx != CPUID_VENDOR_INTEL_3) {
1844 *ecx |= 1 << 1; /* CmpLegacy bit */
1845 }
1846 }
c6dc6f63
AP		 1847 break;
1848 case 0x80000002:
1849 case 0x80000003:
1850 case 0x80000004:
1851 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1852 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1853 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1854 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1855 break;
1856 case 0x80000005:
1857 /* cache info (L1 cache) */
1858 *eax = 0x01ff01ff;
1859 *ebx = 0x01ff01ff;
1860 *ecx = 0x40020140;
1861 *edx = 0x40020140;
1862 break;
1863 case 0x80000006:
1864 /* cache info (L2 cache) */
1865 *eax = 0;
1866 *ebx = 0x42004200;
1867 *ecx = 0x02008140;
1868 *edx = 0;
1869 break;
1870 case 0x80000008:
1871 /* virtual & phys address size in low 2 bytes. */
1872/* XXX: This value must match the one used in the MMU code. */
1873 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1874 /* 64 bit processor */
1875/* XXX: The physical address space is limited to 42 bits in exec.c. */
1876 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1877 } else {
1878 if (env->cpuid_features & CPUID_PSE36)
1879 *eax = 0x00000024; /* 36 bits physical */
1880 else
1881 *eax = 0x00000020; /* 32 bits physical */
1882 }
1883 *ebx = 0;
1884 *ecx = 0;
1885 *edx = 0;
1886 if (env->nr_cores * env->nr_threads > 1) {
1887 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1888 }
1889 break;
1890 case 0x8000000A:
9f3fb565
EH		 1891 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1892 *eax = 0x00000001; /* SVM Revision */
1893 *ebx = 0x00000010; /* nr of ASIDs */
1894 *ecx = 0;
1895 *edx = env->cpuid_svm_features; /* optional features */
1896 } else {
1897 *eax = 0;
1898 *ebx = 0;
1899 *ecx = 0;
1900 *edx = 0;
1901 }
c6dc6f63 1902 break;
b3baa152 1903 case 0xC0000000:
1904 *eax = env->cpuid_xlevel2;
1905 *ebx = 0;
1906 *ecx = 0;
1907 *edx = 0;
1908 break;
1909 case 0xC0000001:
1910 /* Support for VIA CPU's CPUID instruction */
1911 *eax = env->cpuid_version;
1912 *ebx = 0;
1913 *ecx = 0;
1914 *edx = env->cpuid_ext4_features;
1915 break;
1916 case 0xC0000002:
1917 case 0xC0000003:
1918 case 0xC0000004:
1919 /* Reserved for the future, and now filled with zero */
1920 *eax = 0;
1921 *ebx = 0;
1922 *ecx = 0;
1923 *edx = 0;
1924 break;
c6dc6f63
AP		 1925 default:
1926 /* reserved values: zero */
1927 *eax = 0;
1928 *ebx = 0;
1929 *ecx = 0;
1930 *edx = 0;
1931 break;
1932 }
1933}
5fd2087a
AF		 1934
1935/* CPUClass::reset() */
1936static void x86_cpu_reset(CPUState *s)
1937{
1938 X86CPU *cpu = X86_CPU(s);
1939 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1940 CPUX86State *env = &cpu->env;
c1958aea
AF		 1941 int i;
1942
1943 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1944 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
6fd2a026 1945 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1946 }
5fd2087a
AF		 1947
1948 xcc->parent_reset(s);
1949
c1958aea
AF		 1950
1951 memset(env, 0, offsetof(CPUX86State, breakpoints));
1952
1953 tlb_flush(env, 1);
1954
1955 env->old_exception = -1;
1956
1957 /* init to reset state */
1958
1959#ifdef CONFIG_SOFTMMU
1960 env->hflags |= HF_SOFTMMU_MASK;
1961#endif
1962 env->hflags2 |= HF2_GIF_MASK;
1963
1964 cpu_x86_update_cr0(env, 0x60000010);
1965 env->a20_mask = ~0x0;
1966 env->smbase = 0x30000;
1967
1968 env->idt.limit = 0xffff;
1969 env->gdt.limit = 0xffff;
1970 env->ldt.limit = 0xffff;
1971 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1972 env->tr.limit = 0xffff;
1973 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1974
1975 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1976 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1977 DESC_R_MASK | DESC_A_MASK);
1978 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1979 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1980 DESC_A_MASK);
1981 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1982 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1983 DESC_A_MASK);
1984 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1985 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1986 DESC_A_MASK);
1987 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1988 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1989 DESC_A_MASK);
1990 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1991 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1992 DESC_A_MASK);
1993
1994 env->eip = 0xfff0;
1995 env->regs[R_EDX] = env->cpuid_version;
1996
1997 env->eflags = 0x2;
1998
1999 /* FPU init */
2000 for (i = 0; i < 8; i++) {
2001 env->fptags[i] = 1;
2002 }
2003 env->fpuc = 0x37f;
2004
2005 env->mxcsr = 0x1f80;
2006
2007 env->pat = 0x0007040600070406ULL;
2008 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2009
2010 memset(env->dr, 0, sizeof(env->dr));
2011 env->dr[6] = DR6_FIXED_1;
2012 env->dr[7] = DR7_FIXED_1;
2013 cpu_breakpoint_remove_all(env, BP_CPU);
2014 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2015
2016#if !defined(CONFIG_USER_ONLY)
2017 /* We hard-wire the BSP to the first CPU. */
2018 if (env->cpu_index == 0) {
2019 apic_designate_bsp(env->apic_state);
2020 }
2021
2022 env->halted = !cpu_is_bsp(cpu);
2023#endif
5fd2087a
AF		 2024}
2025
dd673288
IM		 2026#ifndef CONFIG_USER_ONLY
2027bool cpu_is_bsp(X86CPU *cpu)
2028{
2029 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2030}
65dee380
IM		 2031
2032/* TODO: remove me, when reset over QOM tree is implemented */
2033static void x86_cpu_machine_reset_cb(void *opaque)
2034{
2035 X86CPU *cpu = opaque;
2036 cpu_reset(CPU(cpu));
2037}
dd673288
IM		 2038#endif
2039
de024815
AF		 2040static void mce_init(X86CPU *cpu)
2041{
2042 CPUX86State *cenv = &cpu->env;
2043 unsigned int bank;
2044
2045 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2046 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2047 (CPUID_MCE | CPUID_MCA)) {
2048 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2049 cenv->mcg_ctl = ~(uint64_t)0;
2050 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2051 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2052 }
2053 }
2054}
2055
bdeec802
IM		 2056#define MSI_ADDR_BASE 0xfee00000
2057
2058#ifndef CONFIG_USER_ONLY
2059static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2060{
2061 static int apic_mapped;
2062 CPUX86State *env = &cpu->env;
449994eb 2063 APICCommonState *apic;
bdeec802
IM		 2064 const char *apic_type = "apic";
2065
2066 if (kvm_irqchip_in_kernel()) {
2067 apic_type = "kvm-apic";
2068 } else if (xen_enabled()) {
2069 apic_type = "xen-apic";
2070 }
2071
2072 env->apic_state = qdev_try_create(NULL, apic_type);
2073 if (env->apic_state == NULL) {
2074 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2075 return;
2076 }
2077
2078 object_property_add_child(OBJECT(cpu), "apic",
2079 OBJECT(env->apic_state), NULL);
2080 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2081 /* TODO: convert to link<> */
449994eb 2082 apic = APIC_COMMON(env->apic_state);
60671e58 2083 apic->cpu = cpu;
bdeec802
IM		 2084
2085 if (qdev_init(env->apic_state)) {
2086 error_setg(errp, "APIC device '%s' could not be initialized",
2087 object_get_typename(OBJECT(env->apic_state)));
2088 return;
2089 }
2090
2091 /* XXX: mapping more APICs at the same memory location */
2092 if (apic_mapped == 0) {
2093 /* NOTE: the APIC is directly connected to the CPU - it is not
2094 on the global memory bus. */
2095 /* XXX: what if the base changes? */
2096 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2097 apic_mapped = 1;
2098 }
2099}
2100#endif
2101
7a059953
AF		 2102void x86_cpu_realize(Object *obj, Error **errp)
2103{
2104 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2105 CPUX86State *env = &cpu->env;
2106
2107 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2108 env->cpuid_level = 7;
2109 }
7a059953 2110
65dee380
IM		 2111#ifndef CONFIG_USER_ONLY
2112 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2113
2114 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2115 x86_cpu_apic_init(cpu, errp);
2116 if (error_is_set(errp)) {
2117 return;
2118 }
2119 }
65dee380
IM		 2120#endif
2121
7a059953
AF		 2122 mce_init(cpu);
2123 qemu_init_vcpu(&cpu->env);
65dee380 2124 cpu_reset(CPU(cpu));
7a059953
AF		 2125}
2126
de024815
AF		 2127static void x86_cpu_initfn(Object *obj)
2128{
2129 X86CPU *cpu = X86_CPU(obj);
2130 CPUX86State *env = &cpu->env;
d65e9815 2131 static int inited;
de024815
AF		 2132
2133 cpu_exec_init(env);
71ad61d3
AF		 2134
2135 object_property_add(obj, "family", "int",
95b8519d 2136 x86_cpuid_version_get_family,
71ad61d3 2137 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2138 object_property_add(obj, "model", "int",
67e30c83 2139 x86_cpuid_version_get_model,
c5291a4f 2140 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2141 object_property_add(obj, "stepping", "int",
35112e41 2142 x86_cpuid_version_get_stepping,
036e2222 2143 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2144 object_property_add(obj, "level", "int",
2145 x86_cpuid_get_level,
2146 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2147 object_property_add(obj, "xlevel", "int",
2148 x86_cpuid_get_xlevel,
2149 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2150 object_property_add_str(obj, "vendor",
2151 x86_cpuid_get_vendor,
2152 x86_cpuid_set_vendor, NULL);
938d4c25 2153 object_property_add_str(obj, "model-id",
63e886eb 2154 x86_cpuid_get_model_id,
938d4c25 2155 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2156 object_property_add(obj, "tsc-frequency", "int",
2157 x86_cpuid_get_tsc_freq,
2158 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2159
de024815 2160 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 2161
2162 /* init various static tables used in TCG mode */
2163 if (tcg_enabled() && !inited) {
2164 inited = 1;
2165 optimize_flags_init();
2166#ifndef CONFIG_USER_ONLY
2167 cpu_set_debug_excp_handler(breakpoint_handler);
2168#endif
2169 }
de024815
AF		 2170}
2171
5fd2087a
AF		 2172static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2173{
2174 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2175 CPUClass *cc = CPU_CLASS(oc);
2176
2177 xcc->parent_reset = cc->reset;
2178 cc->reset = x86_cpu_reset;
2179}
2180
2181static const TypeInfo x86_cpu_type_info = {
2182 .name = TYPE_X86_CPU,
2183 .parent = TYPE_CPU,
2184 .instance_size = sizeof(X86CPU),
de024815 2185 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2186 .abstract = false,
2187 .class_size = sizeof(X86CPUClass),
2188 .class_init = x86_cpu_common_class_init,
2189};
2190
2191static void x86_cpu_register_types(void)
2192{
2193 type_register_static(&x86_cpu_type_info);
2194}
2195
2196type_init(x86_cpu_register_types)
Qemu copy for testing