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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
a4d95d7c | 4 | Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r |
2ef2b01e | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
2ef2b01e A |
7 | \r |
8 | **/\r | |
9 | \r | |
cc15a619 PG |
10 | #ifndef ARM_V7_H_\r |
11 | #define ARM_V7_H_\r | |
2ef2b01e | 12 | \r |
11c20f4e | 13 | #include <Chipset/ArmV7Mmu.h>\r |
14 | \r | |
111339d2 | 15 | // ARM Interrupt ID in Exception Table\r |
16 | #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r | |
17 | \r | |
27331bff OM |
18 | // ID_PFR1 - ARM Processor Feature Register 1 definitions\r |
19 | #define ARM_PFR1_SEC (0xFUL << 4)\r | |
20 | #define ARM_PFR1_TIMER (0xFUL << 16)\r | |
21 | #define ARM_PFR1_GIC (0xFUL << 28)\r | |
22 | \r | |
2ef2b01e A |
23 | // Domain Access Control Register\r |
24 | #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r | |
25 | #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r | |
26 | #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r | |
27 | #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r | |
28 | #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r | |
29 | \r | |
063ad84e | 30 | // CPSR - Coprocessor Status Register definitions\r |
31 | #define CPSR_MODE_USER 0x10\r | |
32 | #define CPSR_MODE_FIQ 0x11\r | |
33 | #define CPSR_MODE_IRQ 0x12\r | |
34 | #define CPSR_MODE_SVC 0x13\r | |
35 | #define CPSR_MODE_ABORT 0x17\r | |
36 | #define CPSR_MODE_HYP 0x1A\r | |
37 | #define CPSR_MODE_UNDEFINED 0x1B\r | |
38 | #define CPSR_MODE_SYSTEM 0x1F\r | |
39 | #define CPSR_MODE_MASK 0x1F\r | |
40 | #define CPSR_ASYNC_ABORT (1 << 8)\r | |
41 | #define CPSR_IRQ (1 << 7)\r | |
42 | #define CPSR_FIQ (1 << 6)\r | |
43 | \r | |
44 | \r | |
11c20f4e | 45 | // CPACR - Coprocessor Access Control Register definitions\r |
1bfda055 | 46 | #define CPACR_CP_DENIED(cp) 0x00\r |
47 | #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
48 | #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
49 | #define CPACR_ASEDIS (1 << 31)\r | |
50 | #define CPACR_D32DIS (1 << 30)\r | |
51 | #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r | |
52 | \r | |
11c20f4e | 53 | // NSACR - Non-Secure Access Control Register definitions\r |
1bfda055 | 54 | #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r |
55 | #define NSACR_NSD32DIS (1 << 14)\r | |
56 | #define NSACR_NSASEDIS (1 << 15)\r | |
57 | #define NSACR_PLE (1 << 16)\r | |
58 | #define NSACR_TL (1 << 17)\r | |
59 | #define NSACR_NS_SMP (1 << 18)\r | |
60 | #define NSACR_RFR (1 << 19)\r | |
61 | \r | |
11c20f4e | 62 | // SCR - Secure Configuration Register definitions\r |
1bfda055 | 63 | #define SCR_NS (1 << 0)\r |
64 | #define SCR_IRQ (1 << 1)\r | |
65 | #define SCR_FIQ (1 << 2)\r | |
66 | #define SCR_EA (1 << 3)\r | |
67 | #define SCR_FW (1 << 4)\r | |
68 | #define SCR_AW (1 << 5)\r | |
69 | \r | |
bd6b9799 | 70 | // MIDR - Main ID Register definitions\r |
7aec2926 | 71 | #define ARM_CPU_TYPE_SHIFT 4\r |
bd6b9799 | 72 | #define ARM_CPU_TYPE_MASK 0xFFF\r |
a4d95d7c | 73 | #define ARM_CPU_TYPE_AEMV8 0xD0F\r |
b7dd4dbd OM |
74 | #define ARM_CPU_TYPE_A53 0xD03\r |
75 | #define ARM_CPU_TYPE_A57 0xD07\r | |
bd6b9799 | 76 | #define ARM_CPU_TYPE_A15 0xC0F\r |
7aec2926 | 77 | #define ARM_CPU_TYPE_A12 0xC0D\r |
bd6b9799 | 78 | #define ARM_CPU_TYPE_A9 0xC09\r |
7aec2926 | 79 | #define ARM_CPU_TYPE_A7 0xC07\r |
bd6b9799 | 80 | #define ARM_CPU_TYPE_A5 0xC05\r |
1bfda055 | 81 | \r |
b7dd4dbd OM |
82 | #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r |
83 | #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r | |
84 | \r | |
01bd6ea8 | 85 | #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r |
86 | \r | |
1bfda055 | 87 | VOID\r |
88 | EFIAPI\r | |
bd6b9799 | 89 | ArmEnableSWPInstruction (\r |
1bfda055 | 90 | VOID\r |
91 | );\r | |
92 | \r | |
3402aac7 | 93 | UINTN\r |
1bfda055 | 94 | EFIAPI\r |
9e2b420e | 95 | ArmReadCbar (\r |
96 | VOID\r | |
97 | );\r | |
1bfda055 | 98 | \r |
0530bfe3 | 99 | UINTN\r |
100 | EFIAPI\r | |
9e2b420e | 101 | ArmReadTpidrurw (\r |
102 | VOID\r | |
103 | );\r | |
0530bfe3 | 104 | \r |
0530bfe3 | 105 | VOID\r |
106 | EFIAPI\r | |
9e2b420e | 107 | ArmWriteTpidrurw (\r |
108 | UINTN Value\r | |
109 | );\r | |
0530bfe3 | 110 | \r |
d6dc67ba OM |
111 | UINT32\r |
112 | EFIAPI\r | |
113 | ArmReadNsacr (\r | |
114 | VOID\r | |
115 | );\r | |
116 | \r | |
117 | VOID\r | |
118 | EFIAPI\r | |
119 | ArmWriteNsacr (\r | |
120 | IN UINT32 Nsacr\r | |
121 | );\r | |
122 | \r | |
cc15a619 | 123 | #endif // ARM_V7_H_\r |