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1d5d0ae9 | 1 | //\r |
bebda7ce | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 3 | //\r |
3402aac7 RC |
4 | // This program and the accompanying materials\r |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1d5d0ae9 | 11 | //\r |
12 | //\r | |
13 | \r | |
1d5d0ae9 | 14 | #include <AutoGen.h>\r |
15 | \r | |
16 | INCLUDE AsmMacroIoLib.inc\r | |
3402aac7 | 17 | \r |
1d5d0ae9 | 18 | IMPORT CEntryPoint\r |
2d45f194 | 19 | IMPORT ArmPlatformGetCorePosition\r |
bebda7ce | 20 | IMPORT ArmPlatformIsPrimaryCore\r |
0787bc61 | 21 | IMPORT ArmReadMpidr\r |
b5a57223 | 22 | IMPORT ArmPlatformPeiBootAction\r |
1d5d0ae9 | 23 | EXPORT _ModuleEntryPoint\r |
3402aac7 | 24 | \r |
1d5d0ae9 | 25 | PRESERVE8\r |
26 | AREA PrePeiCoreEntryPoint, CODE, READONLY\r | |
3402aac7 | 27 | \r |
1d5d0ae9 | 28 | StartupAddr DCD CEntryPoint\r |
29 | \r | |
1d5d0ae9 | 30 | _ModuleEntryPoint\r |
b5a57223 | 31 | // Do early platform specific actions\r |
32 | bl ArmPlatformPeiBootAction\r | |
33 | \r | |
1d5d0ae9 | 34 | // Identify CPU ID\r |
0787bc61 | 35 | bl ArmReadMpidr\r |
bebda7ce | 36 | // Keep a copy of the MpId register value\r |
37 | mov r5, r0\r | |
3402aac7 | 38 | \r |
bebda7ce | 39 | // Is it the Primary Core ?\r |
91c38d4e | 40 | bl ArmPlatformIsPrimaryCore\r |
bebda7ce | 41 | \r |
1377db63 | 42 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
66edb631 | 43 | mov32 r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize)\r |
2dbcb8f0 | 44 | \r |
bebda7ce | 45 | // r0 is equal to 1 if I am the primary core\r |
46 | cmp r0, #1\r | |
2dbcb8f0 | 47 | beq _SetupPrimaryCoreStack\r |
48 | \r | |
49 | _SetupSecondaryCoreStack\r | |
1377db63 | 50 | // r1 contains the base of the secondary stacks\r |
2dbcb8f0 | 51 | \r |
2d45f194 | 52 | // Get the Core Position\r |
53 | mov r6, r1 // Save base of the secondary stacks\r | |
54 | mov r0, r5\r | |
55 | bl ArmPlatformGetCorePosition\r | |
2dbcb8f0 | 56 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
1377db63 | 57 | add r0, r0, #1\r |
1d5d0ae9 | 58 | \r |
2dbcb8f0 | 59 | // StackOffset = CorePos * StackSize\r |
66edb631 | 60 | mov32 r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)\r |
1377db63 | 61 | mul r0, r0, r2\r |
2dbcb8f0 | 62 | // SP = StackBase + StackOffset\r |
2d45f194 | 63 | add sp, r6, r0\r |
47a8e12f | 64 | \r |
65 | _PrepareArguments\r | |
1d5d0ae9 | 66 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r |
66edb631 AB |
67 | mov32 r2, FixedPcdGet32(PcdFvBaseAddress)\r |
68 | ldr r1, [r2, #4]\r | |
1d5d0ae9 | 69 | \r |
1377db63 | 70 | // Move sec startup address into a data register\r |
71 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
72 | ldr r3, StartupAddr\r | |
3402aac7 | 73 | \r |
1377db63 | 74 | // Jump to PrePeiCore C code\r |
0787bc61 | 75 | // r0 = mp_id\r |
1d5d0ae9 | 76 | // r1 = pei_core_address\r |
1377db63 | 77 | mov r0, r5\r |
78 | blx r3\r | |
79 | \r | |
80 | _SetupPrimaryCoreStack\r | |
3707dee3 | 81 | mov sp, r1\r |
7e2a8dfe AB |
82 | mov32 r8, FixedPcdGet64 (PcdCPUCoresStackBase)\r |
83 | mov32 r9, FixedPcdGet32 (PcdInitValueInTempStack)\r | |
84 | mov r10, r9\r | |
85 | mov r11, r9\r | |
86 | mov r12, r9\r | |
87 | 0:stm r8!, {r9-r12}\r | |
88 | cmp r8, r1\r | |
89 | blt 0b\r | |
1377db63 | 90 | b _PrepareArguments\r |
1d5d0ae9 | 91 | \r |
2dbcb8f0 | 92 | _NeverReturn\r |
93 | b _NeverReturn\r | |
94 | \r | |
1d5d0ae9 | 95 | END\r |