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2dbcb8f0 | 1 | //\r |
bebda7ce | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
2dbcb8f0 | 3 | // \r |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
11c20f4e | 13 | \r |
2dbcb8f0 | 14 | #include <AutoGen.h>\r |
11c20f4e | 15 | #include <AsmMacroIoLib.h>\r |
90d6a1bb | 16 | #include "SecInternal.h"\r |
11c20f4e | 17 | \r |
11c20f4e | 18 | .text\r |
19 | .align 3\r | |
20 | \r | |
11c20f4e | 21 | GCC_ASM_IMPORT(CEntryPoint)\r |
bebda7ce | 22 | GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r |
2d45f194 | 23 | GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r |
44e272fd | 24 | GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r |
e314d564 | 25 | GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r |
11c20f4e | 26 | GCC_ASM_IMPORT(ArmDisableInterrupts)\r |
27 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r | |
0787bc61 | 28 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
b1d41be7 | 29 | GCC_ASM_IMPORT(ArmCallWFE)\r |
90d6a1bb | 30 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r |
11c20f4e | 31 | \r |
2dbcb8f0 | 32 | StartupAddr: .word ASM_PFX(CEntryPoint)\r |
11c20f4e | 33 | \r |
34 | ASM_PFX(_ModuleEntryPoint):\r | |
2dbcb8f0 | 35 | // First ensure all interrupts are disabled\r |
36 | bl ASM_PFX(ArmDisableInterrupts)\r | |
11c20f4e | 37 | \r |
2dbcb8f0 | 38 | // Ensure that the MMU and caches are off\r |
39 | bl ASM_PFX(ArmDisableCachesAndMmu)\r | |
11c20f4e | 40 | \r |
a75568e9 | 41 | // By default, we are doing a cold boot\r |
42 | mov r10, #ARM_SEC_COLD_BOOT\r | |
43 | \r | |
2dbcb8f0 | 44 | // Jump to Platform Specific Boot Action function\r |
44e272fd | 45 | blx ASM_PFX(ArmPlatformSecBootAction)\r |
46 | \r | |
2dbcb8f0 | 47 | _IdentifyCpu:\r |
48 | // Identify CPU ID\r | |
11c20f4e | 49 | bl ASM_PFX(ArmReadMpidr)\r |
bebda7ce | 50 | // Keep a copy of the MpId register value\r |
51 | mov r9, r0\r | |
11c20f4e | 52 | \r |
2dbcb8f0 | 53 | // Is it the Primary Core ?\r |
bebda7ce | 54 | bl ASM_PFX(ArmPlatformIsPrimaryCore)\r |
55 | cmp r0, #1\r | |
2dbcb8f0 | 56 | // Only the primary core initialize the memory (SMC)\r |
11c20f4e | 57 | beq _InitMem\r |
58 | \r | |
90d6a1bb | 59 | _WaitInitMem:\r |
a75568e9 | 60 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
61 | // Otherwise we have to wait the Primary Core to finish the initialization\r | |
62 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
63 | bne _SetupSecondaryCoreStack\r | |
64 | \r | |
b1d41be7 | 65 | // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r |
66 | bl ASM_PFX(ArmCallWFE)\r | |
90d6a1bb | 67 | // Now the Init Mem is initialized, we setup the secondary core stacks\r |
2dbcb8f0 | 68 | b _SetupSecondaryCoreStack\r |
11c20f4e | 69 | \r |
70 | _InitMem:\r | |
8cfd2e24 | 71 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
72 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
73 | bne _SetupPrimaryCoreStack\r | |
74 | \r | |
f156d5b4 | 75 | // Initialize Init Boot Memory\r |
e314d564 | 76 | bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r |
2dbcb8f0 | 77 | \r |
2dbcb8f0 | 78 | _SetupPrimaryCoreStack:\r |
1377db63 | 79 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
80 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
81 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
82 | add r1, r1, r2\r | |
83 | \r | |
84 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r | |
2dbcb8f0 | 85 | \r |
86 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
87 | // 64-bit variable on the stack\r | |
1377db63 | 88 | SetPrimaryStack (r1, r2, r3)\r |
89 | b _PrepareArguments\r | |
2dbcb8f0 | 90 | \r |
91 | _SetupSecondaryCoreStack:\r | |
1377db63 | 92 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
93 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
94 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
2d45f194 | 95 | add r6, r1, r2\r |
1377db63 | 96 | \r |
2d45f194 | 97 | // Get the Core Position\r |
98 | mov r0, r9\r | |
99 | bl ASM_PFX(ArmPlatformGetCorePosition)\r | |
2dbcb8f0 | 100 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
101 | add r0, r0, #1\r | |
102 | \r | |
2dbcb8f0 | 103 | // StackOffset = CorePos * StackSize\r |
1377db63 | 104 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r |
2dbcb8f0 | 105 | mul r0, r0, r2\r |
106 | // SP = StackBase + StackOffset\r | |
2d45f194 | 107 | add sp, r6, r0\r |
11c20f4e | 108 | \r |
2dbcb8f0 | 109 | _PrepareArguments:\r |
110 | // Move sec startup address into a data register\r | |
111 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
11c20f4e | 112 | ldr r3, StartupAddr\r |
113 | \r | |
2dbcb8f0 | 114 | // Jump to SEC C code\r |
115 | // r0 = mp_id\r | |
a75568e9 | 116 | // r1 = Boot Mode\r |
bebda7ce | 117 | mov r0, r9\r |
a75568e9 | 118 | mov r1, r10\r |
2dbcb8f0 | 119 | blx r3\r |
120 | \r | |
121 | _NeverReturn:\r | |
122 | b _NeverReturn\r |