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4a50cf4e RN |
1 | /** @file\r |
2 | \r | |
3 | PCI Root Bridge Io Protocol code.\r | |
4 | \r | |
0edb7ec5 | 5 | Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>\r |
4a50cf4e RN |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "PciHostBridge.h"\r | |
17 | #include "PciRootBridge.h"\r | |
18 | #include "PciHostResource.h"\r | |
19 | \r | |
c15da8eb JY |
20 | extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;\r |
21 | \r | |
ccf66016 | 22 | #define NO_MAPPING (VOID *) (UINTN) -1\r |
4a50cf4e RN |
23 | \r |
24 | //\r | |
25 | // Lookup table for increment values based on transfer widths\r | |
26 | //\r | |
27 | UINT8 mInStride[] = {\r | |
28 | 1, // EfiPciWidthUint8\r | |
29 | 2, // EfiPciWidthUint16\r | |
30 | 4, // EfiPciWidthUint32\r | |
31 | 8, // EfiPciWidthUint64\r | |
32 | 0, // EfiPciWidthFifoUint8\r | |
33 | 0, // EfiPciWidthFifoUint16\r | |
34 | 0, // EfiPciWidthFifoUint32\r | |
35 | 0, // EfiPciWidthFifoUint64\r | |
36 | 1, // EfiPciWidthFillUint8\r | |
37 | 2, // EfiPciWidthFillUint16\r | |
38 | 4, // EfiPciWidthFillUint32\r | |
39 | 8 // EfiPciWidthFillUint64\r | |
40 | };\r | |
41 | \r | |
42 | //\r | |
43 | // Lookup table for increment values based on transfer widths\r | |
44 | //\r | |
45 | UINT8 mOutStride[] = {\r | |
46 | 1, // EfiPciWidthUint8\r | |
47 | 2, // EfiPciWidthUint16\r | |
48 | 4, // EfiPciWidthUint32\r | |
49 | 8, // EfiPciWidthUint64\r | |
50 | 1, // EfiPciWidthFifoUint8\r | |
51 | 2, // EfiPciWidthFifoUint16\r | |
52 | 4, // EfiPciWidthFifoUint32\r | |
53 | 8, // EfiPciWidthFifoUint64\r | |
54 | 0, // EfiPciWidthFillUint8\r | |
55 | 0, // EfiPciWidthFillUint16\r | |
56 | 0, // EfiPciWidthFillUint32\r | |
57 | 0 // EfiPciWidthFillUint64\r | |
58 | };\r | |
59 | \r | |
60 | /**\r | |
61 | Construct the Pci Root Bridge instance.\r | |
62 | \r | |
63 | @param Bridge The root bridge instance.\r | |
4a50cf4e RN |
64 | \r |
65 | @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r | |
66 | or NULL if creation fails.\r | |
67 | **/\r | |
68 | PCI_ROOT_BRIDGE_INSTANCE *\r | |
69 | CreateRootBridge (\r | |
401f8cd1 | 70 | IN PCI_ROOT_BRIDGE *Bridge\r |
4a50cf4e RN |
71 | )\r |
72 | {\r | |
73 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
74 | PCI_RESOURCE_TYPE Index;\r | |
75 | CHAR16 *DevicePathStr;\r | |
401f8cd1 | 76 | PCI_ROOT_BRIDGE_APERTURE *Aperture;\r |
4a50cf4e RN |
77 | \r |
78 | DevicePathStr = NULL;\r | |
79 | \r | |
80 | DEBUG ((EFI_D_INFO, "RootBridge: "));\r | |
81 | DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));\r | |
3da82965 LE |
82 | DEBUG ((EFI_D_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));\r |
83 | DEBUG ((EFI_D_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));\r | |
014b4720 | 84 | DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));\r |
3da82965 | 85 | DEBUG ((EFI_D_INFO, " AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,\r |
4a50cf4e RN |
86 | (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",\r |
87 | (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""\r | |
88 | ));\r | |
74d0a339 HG |
89 | DEBUG ((\r |
90 | EFI_D_INFO, " Bus: %lx - %lx Translation=%lx\n",\r | |
91 | Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation\r | |
92 | ));\r | |
93 | //\r | |
94 | // Translation for bus is not supported.\r | |
95 | //\r | |
96 | ASSERT (Bridge->Bus.Translation == 0);\r | |
97 | if (Bridge->Bus.Translation != 0) {\r | |
98 | return NULL;\r | |
99 | }\r | |
100 | \r | |
101 | DEBUG ((\r | |
102 | DEBUG_INFO, " Io: %lx - %lx Translation=%lx\n",\r | |
103 | Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation\r | |
104 | ));\r | |
105 | DEBUG ((\r | |
106 | DEBUG_INFO, " Mem: %lx - %lx Translation=%lx\n",\r | |
107 | Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation\r | |
108 | ));\r | |
109 | DEBUG ((\r | |
110 | DEBUG_INFO, " MemAbove4G: %lx - %lx Translation=%lx\n",\r | |
111 | Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation\r | |
112 | ));\r | |
113 | DEBUG ((\r | |
114 | DEBUG_INFO, " PMem: %lx - %lx Translation=%lx\n",\r | |
115 | Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation\r | |
116 | ));\r | |
117 | DEBUG ((\r | |
118 | DEBUG_INFO, " PMemAbove4G: %lx - %lx Translation=%lx\n",\r | |
119 | Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation\r | |
120 | ));\r | |
4a50cf4e RN |
121 | \r |
122 | //\r | |
123 | // Make sure Mem and MemAbove4G apertures are valid\r | |
124 | //\r | |
f9607bef | 125 | if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r |
4a50cf4e RN |
126 | ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r |
127 | if (Bridge->Mem.Limit >= SIZE_4GB) {\r | |
128 | return NULL;\r | |
129 | }\r | |
130 | }\r | |
f9607bef | 131 | if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r |
4a50cf4e RN |
132 | ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r |
133 | if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r | |
134 | return NULL;\r | |
135 | }\r | |
136 | }\r | |
f9607bef | 137 | if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r |
4a50cf4e RN |
138 | ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r |
139 | if (Bridge->PMem.Limit >= SIZE_4GB) {\r | |
140 | return NULL;\r | |
141 | }\r | |
142 | }\r | |
f9607bef | 143 | if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r |
4a50cf4e RN |
144 | ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r |
145 | if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r | |
146 | return NULL;\r | |
147 | }\r | |
148 | }\r | |
149 | \r | |
401f8cd1 RN |
150 | //\r |
151 | // Ignore AllocationAttributes when resources were already assigned.\r | |
152 | //\r | |
153 | if (!Bridge->ResourceAssigned) {\r | |
154 | if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r | |
155 | //\r | |
156 | // If this bit is set, then the PCI Root Bridge does not\r | |
157 | // support separate windows for Non-prefetchable and Prefetchable\r | |
158 | // memory.\r | |
159 | //\r | |
160 | ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r | |
161 | ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r | |
162 | if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r | |
163 | (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r | |
164 | ) {\r | |
165 | return NULL;\r | |
166 | }\r | |
4a50cf4e | 167 | }\r |
4a50cf4e | 168 | \r |
401f8cd1 RN |
169 | if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r |
170 | //\r | |
171 | // If this bit is not set, then the PCI Root Bridge does not support\r | |
172 | // 64 bit memory windows.\r | |
173 | //\r | |
174 | ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r | |
175 | ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r | |
176 | if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r | |
177 | (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r | |
178 | ) {\r | |
179 | return NULL;\r | |
180 | }\r | |
4a50cf4e RN |
181 | }\r |
182 | }\r | |
183 | \r | |
184 | RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));\r | |
185 | ASSERT (RootBridge != NULL);\r | |
186 | \r | |
187 | RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r | |
188 | RootBridge->Supports = Bridge->Supports;\r | |
189 | RootBridge->Attributes = Bridge->Attributes;\r | |
190 | RootBridge->DmaAbove4G = Bridge->DmaAbove4G;\r | |
014b4720 | 191 | RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;\r |
4a50cf4e RN |
192 | RootBridge->AllocationAttributes = Bridge->AllocationAttributes;\r |
193 | RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);\r | |
194 | RootBridge->DevicePathStr = DevicePathStr;\r | |
195 | RootBridge->ConfigBuffer = AllocatePool (\r | |
196 | TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r | |
197 | );\r | |
198 | ASSERT (RootBridge->ConfigBuffer != NULL);\r | |
199 | InitializeListHead (&RootBridge->Maps);\r | |
200 | \r | |
201 | CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
202 | CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
203 | CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
204 | CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
814f4306 RN |
205 | CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r |
206 | CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r | |
4a50cf4e RN |
207 | \r |
208 | for (Index = TypeIo; Index < TypeMax; Index++) {\r | |
401f8cd1 RN |
209 | switch (Index) {\r |
210 | case TypeBus:\r | |
211 | Aperture = &RootBridge->Bus;\r | |
212 | break;\r | |
213 | case TypeIo:\r | |
214 | Aperture = &RootBridge->Io;\r | |
215 | break;\r | |
216 | case TypeMem32:\r | |
217 | Aperture = &RootBridge->Mem;\r | |
218 | break;\r | |
219 | case TypeMem64:\r | |
220 | Aperture = &RootBridge->MemAbove4G;\r | |
221 | break;\r | |
222 | case TypePMem32:\r | |
223 | Aperture = &RootBridge->PMem;\r | |
224 | break;\r | |
225 | case TypePMem64:\r | |
226 | Aperture = &RootBridge->PMemAbove4G;\r | |
227 | break;\r | |
228 | default:\r | |
229 | ASSERT (FALSE);\r | |
26bd6437 | 230 | Aperture = NULL;\r |
401f8cd1 RN |
231 | break;\r |
232 | }\r | |
233 | RootBridge->ResAllocNode[Index].Type = Index;\r | |
234 | if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {\r | |
74d0a339 HG |
235 | //\r |
236 | // Base in ResAllocNode is a host address, while Base in Aperture is a\r | |
237 | // device address.\r | |
238 | //\r | |
239 | RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (Aperture->Base,\r | |
240 | Aperture->Translation);\r | |
401f8cd1 RN |
241 | RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;\r |
242 | RootBridge->ResAllocNode[Index].Status = ResAllocated;\r | |
243 | } else {\r | |
244 | RootBridge->ResAllocNode[Index].Base = 0;\r | |
245 | RootBridge->ResAllocNode[Index].Length = 0;\r | |
246 | RootBridge->ResAllocNode[Index].Status = ResNone;\r | |
247 | }\r | |
4a50cf4e RN |
248 | }\r |
249 | \r | |
250 | RootBridge->RootBridgeIo.SegmentNumber = Bridge->Segment;\r | |
4a50cf4e RN |
251 | RootBridge->RootBridgeIo.PollMem = RootBridgeIoPollMem;\r |
252 | RootBridge->RootBridgeIo.PollIo = RootBridgeIoPollIo;\r | |
253 | RootBridge->RootBridgeIo.Mem.Read = RootBridgeIoMemRead;\r | |
254 | RootBridge->RootBridgeIo.Mem.Write = RootBridgeIoMemWrite;\r | |
255 | RootBridge->RootBridgeIo.Io.Read = RootBridgeIoIoRead;\r | |
256 | RootBridge->RootBridgeIo.Io.Write = RootBridgeIoIoWrite;\r | |
257 | RootBridge->RootBridgeIo.CopyMem = RootBridgeIoCopyMem;\r | |
258 | RootBridge->RootBridgeIo.Pci.Read = RootBridgeIoPciRead;\r | |
259 | RootBridge->RootBridgeIo.Pci.Write = RootBridgeIoPciWrite;\r | |
260 | RootBridge->RootBridgeIo.Map = RootBridgeIoMap;\r | |
261 | RootBridge->RootBridgeIo.Unmap = RootBridgeIoUnmap;\r | |
262 | RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;\r | |
263 | RootBridge->RootBridgeIo.FreeBuffer = RootBridgeIoFreeBuffer;\r | |
264 | RootBridge->RootBridgeIo.Flush = RootBridgeIoFlush;\r | |
265 | RootBridge->RootBridgeIo.GetAttributes = RootBridgeIoGetAttributes;\r | |
266 | RootBridge->RootBridgeIo.SetAttributes = RootBridgeIoSetAttributes;\r | |
267 | RootBridge->RootBridgeIo.Configuration = RootBridgeIoConfiguration;\r | |
268 | \r | |
269 | return RootBridge;\r | |
270 | }\r | |
271 | \r | |
272 | /**\r | |
273 | Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r | |
274 | \r | |
275 | The I/O operations are carried out exactly as requested. The caller is\r | |
276 | responsible for satisfying any alignment and I/O width restrictions that a PI\r | |
277 | System on a platform might require. For example on some platforms, width\r | |
278 | requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other\r | |
279 | hand, will be handled by the driver.\r | |
280 | \r | |
281 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
282 | \r | |
283 | @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r | |
284 | \r | |
285 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
286 | \r | |
287 | @param[in] Address The base address of the I/O operation.\r | |
288 | \r | |
289 | @param[in] Count The number of I/O operations to perform. The number\r | |
290 | of bytes moved is Width size * Count, starting at\r | |
291 | Address.\r | |
292 | \r | |
293 | @param[in] Buffer For read operations, the destination buffer to\r | |
294 | store the results. For write operations, the source\r | |
295 | buffer from which to write data.\r | |
296 | \r | |
297 | @retval EFI_SUCCESS The parameters for this request pass the\r | |
298 | checks.\r | |
299 | \r | |
300 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
301 | \r | |
302 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
303 | \r | |
304 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
305 | \r | |
306 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r | |
307 | and Count is not valid for this PI system.\r | |
308 | **/\r | |
309 | EFI_STATUS\r | |
310 | RootBridgeIoCheckParameter (\r | |
311 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
312 | IN OPERATION_TYPE OperationType,\r | |
313 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
314 | IN UINT64 Address,\r | |
315 | IN UINTN Count,\r | |
316 | IN VOID *Buffer\r | |
317 | )\r | |
318 | {\r | |
319 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
320 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r | |
321 | UINT64 Base;\r | |
322 | UINT64 Limit;\r | |
323 | UINT32 Size;\r | |
324 | \r | |
325 | //\r | |
326 | // Check to see if Buffer is NULL\r | |
327 | //\r | |
328 | if (Buffer == NULL) {\r | |
329 | return EFI_INVALID_PARAMETER;\r | |
330 | }\r | |
331 | \r | |
332 | //\r | |
333 | // Check to see if Width is in the valid range\r | |
334 | //\r | |
335 | if ((UINT32) Width >= EfiPciWidthMaximum) {\r | |
336 | return EFI_INVALID_PARAMETER;\r | |
337 | }\r | |
338 | \r | |
339 | //\r | |
340 | // For FIFO type, the target address won't increase during the access,\r | |
341 | // so treat Count as 1\r | |
342 | //\r | |
343 | if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r | |
344 | Count = 1;\r | |
345 | }\r | |
346 | \r | |
347 | Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r | |
348 | Size = 1 << Width;\r | |
349 | \r | |
350 | //\r | |
351 | // Check to see if Address is aligned\r | |
352 | //\r | |
353 | if ((Address & (Size - 1)) != 0) {\r | |
354 | return EFI_UNSUPPORTED;\r | |
355 | }\r | |
356 | \r | |
357 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
358 | \r | |
359 | //\r | |
360 | // Check to see if any address associated with this transfer exceeds the\r | |
361 | // maximum allowed address. The maximum address implied by the parameters\r | |
362 | // passed in is Address + Size * Count. If the following condition is met,\r | |
363 | // then the transfer is not supported.\r | |
364 | //\r | |
365 | // Address + Size * Count > Limit + 1\r | |
366 | //\r | |
367 | // Since Limit can be the maximum integer value supported by the CPU and\r | |
368 | // Count can also be the maximum integer value supported by the CPU, this\r | |
369 | // range check must be adjusted to avoid all oveflow conditions.\r | |
370 | //\r | |
371 | if (OperationType == IoOperation) {\r | |
372 | //\r | |
373 | // Allow Legacy IO access\r | |
374 | //\r | |
375 | if (Address + MultU64x32 (Count, Size) <= 0x1000) {\r | |
376 | if ((RootBridge->Attributes & (\r | |
377 | EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |\r | |
378 | EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r | |
379 | EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {\r | |
380 | return EFI_SUCCESS;\r | |
381 | }\r | |
382 | }\r | |
383 | Base = RootBridge->Io.Base;\r | |
384 | Limit = RootBridge->Io.Limit;\r | |
385 | } else if (OperationType == MemOperation) {\r | |
386 | //\r | |
387 | // Allow Legacy MMIO access\r | |
388 | //\r | |
389 | if ((Address >= 0xA0000) && (Address + MultU64x32 (Count, Size)) <= 0xC0000) {\r | |
390 | if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {\r | |
391 | return EFI_SUCCESS;\r | |
392 | }\r | |
393 | }\r | |
394 | //\r | |
395 | // By comparing the Address against Limit we know which range to be used\r | |
396 | // for checking\r | |
397 | //\r | |
398 | if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {\r | |
399 | Base = RootBridge->Mem.Base;\r | |
400 | Limit = RootBridge->Mem.Limit;\r | |
401 | } else {\r | |
402 | Base = RootBridge->MemAbove4G.Base;\r | |
403 | Limit = RootBridge->MemAbove4G.Limit;\r | |
404 | }\r | |
405 | } else {\r | |
406 | PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r | |
407 | if (PciRbAddr->Bus < RootBridge->Bus.Base ||\r | |
408 | PciRbAddr->Bus > RootBridge->Bus.Limit) {\r | |
409 | return EFI_INVALID_PARAMETER;\r | |
410 | }\r | |
411 | \r | |
412 | if (PciRbAddr->Device > PCI_MAX_DEVICE ||\r | |
413 | PciRbAddr->Function > PCI_MAX_FUNC) {\r | |
414 | return EFI_INVALID_PARAMETER;\r | |
415 | }\r | |
416 | \r | |
417 | if (PciRbAddr->ExtendedRegister != 0) {\r | |
418 | Address = PciRbAddr->ExtendedRegister;\r | |
419 | } else {\r | |
420 | Address = PciRbAddr->Register;\r | |
421 | }\r | |
422 | Base = 0;\r | |
014b4720 | 423 | Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;\r |
4a50cf4e RN |
424 | }\r |
425 | \r | |
426 | if (Address < Base) {\r | |
427 | return EFI_INVALID_PARAMETER;\r | |
428 | }\r | |
429 | \r | |
430 | if (Address + MultU64x32 (Count, Size) > Limit + 1) {\r | |
431 | return EFI_INVALID_PARAMETER;\r | |
432 | }\r | |
433 | \r | |
434 | return EFI_SUCCESS;\r | |
435 | }\r | |
436 | \r | |
74d0a339 HG |
437 | /**\r |
438 | Use address to match apertures of memory type and then get the corresponding\r | |
439 | translation.\r | |
440 | \r | |
441 | @param RootBridge The root bridge instance.\r | |
442 | @param Address The address used to match aperture.\r | |
443 | @param Translation Pointer containing the output translation.\r | |
444 | \r | |
445 | @return EFI_SUCCESS Get translation successfully.\r | |
446 | @return EFI_INVALID_PARAMETER No matched memory aperture; the input Address\r | |
447 | must be invalid.\r | |
448 | **/\r | |
449 | EFI_STATUS\r | |
450 | RootBridgeIoGetMemTranslationByAddress (\r | |
451 | IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r | |
452 | IN UINT64 Address,\r | |
453 | IN OUT UINT64 *Translation\r | |
454 | )\r | |
455 | {\r | |
456 | if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {\r | |
457 | *Translation = RootBridge->Mem.Translation;\r | |
458 | } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {\r | |
459 | *Translation = RootBridge->PMem.Translation;\r | |
460 | } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {\r | |
461 | *Translation = RootBridge->MemAbove4G.Translation;\r | |
462 | } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {\r | |
463 | *Translation = RootBridge->PMemAbove4G.Translation;\r | |
464 | } else {\r | |
465 | return EFI_INVALID_PARAMETER;\r | |
466 | }\r | |
467 | \r | |
468 | return EFI_SUCCESS;\r | |
469 | }\r | |
470 | \r | |
0edb7ec5 RN |
471 | /**\r |
472 | Return the result of (Multiplicand * Multiplier / Divisor).\r | |
473 | \r | |
474 | @param Multiplicand A 64-bit unsigned value.\r | |
475 | @param Multiplier A 64-bit unsigned value.\r | |
476 | @param Divisor A 32-bit unsigned value.\r | |
477 | @param Remainder A pointer to a 32-bit unsigned value. This parameter is\r | |
478 | optional and may be NULL.\r | |
479 | \r | |
480 | @return Multiplicand * Multiplier / Divisor.\r | |
481 | **/\r | |
482 | UINT64\r | |
483 | MultThenDivU64x64x32 (\r | |
484 | IN UINT64 Multiplicand,\r | |
485 | IN UINT64 Multiplier,\r | |
486 | IN UINT32 Divisor,\r | |
487 | OUT UINT32 *Remainder OPTIONAL\r | |
488 | )\r | |
489 | {\r | |
490 | UINT64 Uint64;\r | |
491 | UINT32 LocalRemainder;\r | |
492 | UINT32 Uint32;\r | |
493 | if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {\r | |
494 | //\r | |
495 | // Make sure Multiplicand is the bigger one.\r | |
496 | //\r | |
497 | if (Multiplicand < Multiplier) {\r | |
498 | Uint64 = Multiplicand;\r | |
499 | Multiplicand = Multiplier;\r | |
500 | Multiplier = Uint64;\r | |
501 | }\r | |
502 | //\r | |
503 | // Because Multiplicand * Multiplier overflows,\r | |
504 | // Multiplicand * Multiplier / Divisor\r | |
505 | // = (2 * Multiplicand' + 1) * Multiplier / Divisor\r | |
506 | // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor\r | |
507 | //\r | |
508 | Uint64 = MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multiplier, Divisor, &LocalRemainder);\r | |
509 | Uint64 = LShiftU64 (Uint64, 1);\r | |
510 | Uint32 = 0;\r | |
511 | if ((Multiplicand & 0x1) == 1) {\r | |
512 | Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);\r | |
513 | }\r | |
514 | return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);\r | |
515 | } else {\r | |
516 | return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);\r | |
517 | }\r | |
518 | }\r | |
519 | \r | |
520 | /**\r | |
521 | Return the elapsed tick count from CurrentTick.\r | |
522 | \r | |
523 | @param CurrentTick On input, the previous tick count.\r | |
524 | On output, the current tick count.\r | |
525 | @param StartTick The value the performance counter starts with when it\r | |
526 | rolls over.\r | |
527 | @param EndTick The value that the performance counter ends with before\r | |
528 | it rolls over.\r | |
529 | \r | |
530 | @return The elapsed tick count from CurrentTick.\r | |
531 | **/\r | |
532 | UINT64\r | |
533 | GetElapsedTick (\r | |
534 | UINT64 *CurrentTick,\r | |
535 | UINT64 StartTick,\r | |
536 | UINT64 EndTick\r | |
537 | )\r | |
538 | {\r | |
539 | UINT64 PreviousTick;\r | |
d1102dba | 540 | \r |
0edb7ec5 RN |
541 | PreviousTick = *CurrentTick;\r |
542 | *CurrentTick = GetPerformanceCounter();\r | |
543 | if (StartTick < EndTick) {\r | |
544 | return *CurrentTick - PreviousTick;\r | |
545 | } else {\r | |
546 | return PreviousTick - *CurrentTick;\r | |
547 | }\r | |
548 | }\r | |
549 | \r | |
4a50cf4e RN |
550 | /**\r |
551 | Polls an address in memory mapped I/O space until an exit condition is met,\r | |
552 | or a timeout occurs.\r | |
553 | \r | |
554 | This function provides a standard way to poll a PCI memory location. A PCI\r | |
555 | memory read operation is performed at the PCI memory address specified by\r | |
556 | Address for the width specified by Width. The result of this PCI memory read\r | |
557 | operation is stored in Result. This PCI memory read operation is repeated\r | |
558 | until either a timeout of Delay 100 ns units has expired, or (Result & Mask)\r | |
559 | is equal to Value.\r | |
560 | \r | |
561 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
562 | @param[in] Width Signifies the width of the memory operations.\r | |
563 | @param[in] Address The base address of the memory operations. The caller\r | |
564 | is responsible for aligning Address if required.\r | |
565 | @param[in] Mask Mask used for the polling criteria. Bytes above Width\r | |
566 | in Mask are ignored. The bits in the bytes below Width\r | |
567 | which are zero in Mask are ignored when polling the\r | |
568 | memory address.\r | |
569 | @param[in] Value The comparison value used for the polling exit\r | |
570 | criteria.\r | |
571 | @param[in] Delay The number of 100 ns units to poll. Note that timer\r | |
572 | available may be of poorer granularity.\r | |
573 | @param[out] Result Pointer to the last value read from the memory\r | |
574 | location.\r | |
575 | \r | |
576 | @retval EFI_SUCCESS The last data returned from the access matched\r | |
577 | the poll exit criteria.\r | |
578 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
579 | @retval EFI_INVALID_PARAMETER Result is NULL.\r | |
580 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
581 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
582 | lack of resources.\r | |
583 | **/\r | |
4a50cf4e RN |
584 | EFI_STATUS\r |
585 | EFIAPI\r | |
586 | RootBridgeIoPollMem (\r | |
587 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
588 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
589 | IN UINT64 Address,\r | |
590 | IN UINT64 Mask,\r | |
591 | IN UINT64 Value,\r | |
592 | IN UINT64 Delay,\r | |
593 | OUT UINT64 *Result\r | |
594 | )\r | |
595 | {\r | |
596 | EFI_STATUS Status;\r | |
597 | UINT64 NumberOfTicks;\r | |
598 | UINT32 Remainder;\r | |
0edb7ec5 RN |
599 | UINT64 StartTick;\r |
600 | UINT64 EndTick;\r | |
601 | UINT64 CurrentTick;\r | |
602 | UINT64 ElapsedTick;\r | |
603 | UINT64 Frequency;\r | |
4a50cf4e RN |
604 | \r |
605 | if (Result == NULL) {\r | |
606 | return EFI_INVALID_PARAMETER;\r | |
607 | }\r | |
608 | \r | |
609 | if ((UINT32)Width > EfiPciWidthUint64) {\r | |
610 | return EFI_INVALID_PARAMETER;\r | |
611 | }\r | |
612 | \r | |
613 | //\r | |
614 | // No matter what, always do a single poll.\r | |
615 | //\r | |
616 | Status = This->Mem.Read (This, Width, Address, 1, Result);\r | |
617 | if (EFI_ERROR (Status)) {\r | |
618 | return Status;\r | |
619 | }\r | |
620 | \r | |
621 | if ((*Result & Mask) == Value) {\r | |
622 | return EFI_SUCCESS;\r | |
623 | }\r | |
624 | \r | |
625 | if (Delay == 0) {\r | |
626 | return EFI_SUCCESS;\r | |
627 | \r | |
628 | } else {\r | |
4a50cf4e | 629 | //\r |
0edb7ec5 | 630 | // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)\r |
4a50cf4e | 631 | //\r |
0edb7ec5 RN |
632 | Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);\r |
633 | NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);\r | |
634 | if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {\r | |
635 | NumberOfTicks++;\r | |
4a50cf4e | 636 | }\r |
0edb7ec5 RN |
637 | for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()\r |
638 | ; ElapsedTick <= NumberOfTicks\r | |
639 | ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)\r | |
640 | ) {\r | |
4a50cf4e RN |
641 | Status = This->Mem.Read (This, Width, Address, 1, Result);\r |
642 | if (EFI_ERROR (Status)) {\r | |
643 | return Status;\r | |
644 | }\r | |
645 | \r | |
646 | if ((*Result & Mask) == Value) {\r | |
647 | return EFI_SUCCESS;\r | |
648 | }\r | |
4a50cf4e RN |
649 | }\r |
650 | }\r | |
651 | return EFI_TIMEOUT;\r | |
652 | }\r | |
653 | \r | |
654 | /**\r | |
655 | Reads from the I/O space of a PCI Root Bridge. Returns when either the\r | |
656 | polling exit criteria is satisfied or after a defined duration.\r | |
657 | \r | |
658 | This function provides a standard way to poll a PCI I/O location. A PCI I/O\r | |
659 | read operation is performed at the PCI I/O address specified by Address for\r | |
660 | the width specified by Width.\r | |
661 | The result of this PCI I/O read operation is stored in Result. This PCI I/O\r | |
662 | read operation is repeated until either a timeout of Delay 100 ns units has\r | |
663 | expired, or (Result & Mask) is equal to Value.\r | |
664 | \r | |
665 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
666 | @param[in] Width Signifies the width of the I/O operations.\r | |
667 | @param[in] Address The base address of the I/O operations. The caller is\r | |
668 | responsible for aligning Address if required.\r | |
669 | @param[in] Mask Mask used for the polling criteria. Bytes above Width in\r | |
670 | Mask are ignored. The bits in the bytes below Width\r | |
671 | which are zero in Mask are ignored when polling the I/O\r | |
672 | address.\r | |
673 | @param[in] Value The comparison value used for the polling exit criteria.\r | |
674 | @param[in] Delay The number of 100 ns units to poll. Note that timer\r | |
675 | available may be of poorer granularity.\r | |
676 | @param[out] Result Pointer to the last value read from the memory location.\r | |
677 | \r | |
678 | @retval EFI_SUCCESS The last data returned from the access matched\r | |
679 | the poll exit criteria.\r | |
680 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
681 | @retval EFI_INVALID_PARAMETER Result is NULL.\r | |
682 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
683 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
684 | lack of resources.\r | |
685 | **/\r | |
686 | EFI_STATUS\r | |
687 | EFIAPI\r | |
688 | RootBridgeIoPollIo (\r | |
689 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
690 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
691 | IN UINT64 Address,\r | |
692 | IN UINT64 Mask,\r | |
693 | IN UINT64 Value,\r | |
694 | IN UINT64 Delay,\r | |
695 | OUT UINT64 *Result\r | |
696 | )\r | |
697 | {\r | |
698 | EFI_STATUS Status;\r | |
699 | UINT64 NumberOfTicks;\r | |
700 | UINT32 Remainder;\r | |
0edb7ec5 RN |
701 | UINT64 StartTick;\r |
702 | UINT64 EndTick;\r | |
703 | UINT64 CurrentTick;\r | |
704 | UINT64 ElapsedTick;\r | |
705 | UINT64 Frequency;\r | |
4a50cf4e RN |
706 | \r |
707 | //\r | |
708 | // No matter what, always do a single poll.\r | |
709 | //\r | |
710 | \r | |
711 | if (Result == NULL) {\r | |
712 | return EFI_INVALID_PARAMETER;\r | |
713 | }\r | |
714 | \r | |
715 | if ((UINT32)Width > EfiPciWidthUint64) {\r | |
716 | return EFI_INVALID_PARAMETER;\r | |
717 | }\r | |
718 | \r | |
719 | Status = This->Io.Read (This, Width, Address, 1, Result);\r | |
720 | if (EFI_ERROR (Status)) {\r | |
721 | return Status;\r | |
722 | }\r | |
723 | if ((*Result & Mask) == Value) {\r | |
724 | return EFI_SUCCESS;\r | |
725 | }\r | |
726 | \r | |
727 | if (Delay == 0) {\r | |
728 | return EFI_SUCCESS;\r | |
729 | \r | |
730 | } else {\r | |
4a50cf4e | 731 | //\r |
0edb7ec5 | 732 | // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)\r |
4a50cf4e | 733 | //\r |
0edb7ec5 RN |
734 | Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);\r |
735 | NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);\r | |
736 | if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {\r | |
737 | NumberOfTicks++;\r | |
4a50cf4e | 738 | }\r |
0edb7ec5 RN |
739 | for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()\r |
740 | ; ElapsedTick <= NumberOfTicks\r | |
741 | ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)\r | |
742 | ) {\r | |
4a50cf4e RN |
743 | Status = This->Io.Read (This, Width, Address, 1, Result);\r |
744 | if (EFI_ERROR (Status)) {\r | |
745 | return Status;\r | |
746 | }\r | |
747 | \r | |
748 | if ((*Result & Mask) == Value) {\r | |
749 | return EFI_SUCCESS;\r | |
750 | }\r | |
4a50cf4e RN |
751 | }\r |
752 | }\r | |
753 | return EFI_TIMEOUT;\r | |
754 | }\r | |
755 | \r | |
756 | /**\r | |
757 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
758 | bridge memory space.\r | |
759 | \r | |
760 | The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r | |
761 | controller registers in the PCI root bridge memory space.\r | |
762 | The memory operations are carried out exactly as requested. The caller is\r | |
763 | responsible for satisfying any alignment and memory width restrictions that a\r | |
764 | PCI Root Bridge on a platform might require.\r | |
765 | \r | |
766 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
767 | @param[in] Width Signifies the width of the memory operation.\r | |
768 | @param[in] Address The base address of the memory operation. The caller\r | |
769 | is responsible for aligning the Address if required.\r | |
770 | @param[in] Count The number of memory operations to perform. Bytes\r | |
771 | moved is Width size * Count, starting at Address.\r | |
772 | @param[out] Buffer For read operations, the destination buffer to store\r | |
773 | the results. For write operations, the source buffer\r | |
774 | to write data from.\r | |
775 | \r | |
776 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
777 | root bridge.\r | |
778 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
779 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
780 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
781 | lack of resources.\r | |
782 | **/\r | |
783 | EFI_STATUS\r | |
784 | EFIAPI\r | |
785 | RootBridgeIoMemRead (\r | |
786 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
787 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
788 | IN UINT64 Address,\r | |
789 | IN UINTN Count,\r | |
790 | OUT VOID *Buffer\r | |
791 | )\r | |
792 | {\r | |
793 | EFI_STATUS Status;\r | |
74d0a339 HG |
794 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
795 | UINT64 Translation;\r | |
4a50cf4e RN |
796 | \r |
797 | Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r | |
798 | Count, Buffer);\r | |
799 | if (EFI_ERROR (Status)) {\r | |
800 | return Status;\r | |
801 | }\r | |
74d0a339 HG |
802 | \r |
803 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
804 | Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r | |
805 | if (EFI_ERROR (Status)) {\r | |
806 | return Status;\r | |
807 | }\r | |
808 | \r | |
809 | // Address passed to CpuIo->Mem.Read needs to be a host address instead of\r | |
810 | // device address.\r | |
811 | return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r | |
812 | TO_HOST_ADDRESS (Address, Translation), Count, Buffer);\r | |
4a50cf4e RN |
813 | }\r |
814 | \r | |
815 | /**\r | |
816 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
817 | bridge memory space.\r | |
818 | \r | |
819 | The Mem.Read(), and Mem.Write() functions enable a driver to access PCI\r | |
820 | controller registers in the PCI root bridge memory space.\r | |
821 | The memory operations are carried out exactly as requested. The caller is\r | |
822 | responsible for satisfying any alignment and memory width restrictions that a\r | |
823 | PCI Root Bridge on a platform might require.\r | |
824 | \r | |
825 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
826 | @param[in] Width Signifies the width of the memory operation.\r | |
827 | @param[in] Address The base address of the memory operation. The caller\r | |
828 | is responsible for aligning the Address if required.\r | |
829 | @param[in] Count The number of memory operations to perform. Bytes\r | |
830 | moved is Width size * Count, starting at Address.\r | |
831 | @param[in] Buffer For read operations, the destination buffer to store\r | |
832 | the results. For write operations, the source buffer\r | |
833 | to write data from.\r | |
834 | \r | |
835 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
836 | root bridge.\r | |
837 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
838 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
839 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
840 | lack of resources.\r | |
841 | **/\r | |
842 | EFI_STATUS\r | |
843 | EFIAPI\r | |
844 | RootBridgeIoMemWrite (\r | |
845 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
846 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
847 | IN UINT64 Address,\r | |
848 | IN UINTN Count,\r | |
849 | IN VOID *Buffer\r | |
850 | )\r | |
851 | {\r | |
852 | EFI_STATUS Status;\r | |
74d0a339 HG |
853 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
854 | UINT64 Translation;\r | |
4a50cf4e RN |
855 | \r |
856 | Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,\r | |
857 | Count, Buffer);\r | |
858 | if (EFI_ERROR (Status)) {\r | |
859 | return Status;\r | |
860 | }\r | |
74d0a339 HG |
861 | \r |
862 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
863 | Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);\r | |
864 | if (EFI_ERROR (Status)) {\r | |
865 | return Status;\r | |
866 | }\r | |
867 | \r | |
868 | // Address passed to CpuIo->Mem.Write needs to be a host address instead of\r | |
869 | // device address.\r | |
870 | return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r | |
871 | TO_HOST_ADDRESS (Address, Translation), Count, Buffer);\r | |
4a50cf4e RN |
872 | }\r |
873 | \r | |
874 | /**\r | |
875 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
876 | bridge I/O space.\r | |
877 | \r | |
878 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
879 | @param[in] Width Signifies the width of the memory operations.\r | |
880 | @param[in] Address The base address of the I/O operation. The caller is\r | |
881 | responsible for aligning the Address if required.\r | |
882 | @param[in] Count The number of I/O operations to perform. Bytes moved\r | |
883 | is Width size * Count, starting at Address.\r | |
884 | @param[out] Buffer For read operations, the destination buffer to store\r | |
885 | the results. For write operations, the source buffer\r | |
886 | to write data from.\r | |
887 | \r | |
888 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
889 | root bridge.\r | |
890 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
891 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
892 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
893 | lack of resources.\r | |
894 | **/\r | |
895 | EFI_STATUS\r | |
896 | EFIAPI\r | |
897 | RootBridgeIoIoRead (\r | |
898 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
899 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
900 | IN UINT64 Address,\r | |
901 | IN UINTN Count,\r | |
902 | OUT VOID *Buffer\r | |
903 | )\r | |
904 | {\r | |
905 | EFI_STATUS Status;\r | |
74d0a339 HG |
906 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
907 | \r | |
4a50cf4e RN |
908 | Status = RootBridgeIoCheckParameter (\r |
909 | This, IoOperation, Width,\r | |
910 | Address, Count, Buffer\r | |
911 | );\r | |
912 | if (EFI_ERROR (Status)) {\r | |
913 | return Status;\r | |
914 | }\r | |
74d0a339 HG |
915 | \r |
916 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
917 | \r | |
918 | // Address passed to CpuIo->Io.Read needs to be a host address instead of\r | |
919 | // device address.\r | |
920 | return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r | |
921 | TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);\r | |
4a50cf4e RN |
922 | }\r |
923 | \r | |
924 | /**\r | |
925 | Enables a PCI driver to access PCI controller registers in the PCI root\r | |
926 | bridge I/O space.\r | |
927 | \r | |
928 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
929 | @param[in] Width Signifies the width of the memory operations.\r | |
930 | @param[in] Address The base address of the I/O operation. The caller is\r | |
931 | responsible for aligning the Address if required.\r | |
932 | @param[in] Count The number of I/O operations to perform. Bytes moved\r | |
933 | is Width size * Count, starting at Address.\r | |
934 | @param[in] Buffer For read operations, the destination buffer to store\r | |
935 | the results. For write operations, the source buffer\r | |
936 | to write data from.\r | |
937 | \r | |
938 | @retval EFI_SUCCESS The data was read from or written to the PCI\r | |
939 | root bridge.\r | |
940 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
941 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
942 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
943 | lack of resources.\r | |
944 | **/\r | |
945 | EFI_STATUS\r | |
946 | EFIAPI\r | |
947 | RootBridgeIoIoWrite (\r | |
948 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
949 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
950 | IN UINT64 Address,\r | |
951 | IN UINTN Count,\r | |
952 | IN VOID *Buffer\r | |
953 | )\r | |
954 | {\r | |
955 | EFI_STATUS Status;\r | |
74d0a339 HG |
956 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r |
957 | \r | |
4a50cf4e RN |
958 | Status = RootBridgeIoCheckParameter (\r |
959 | This, IoOperation, Width,\r | |
960 | Address, Count, Buffer\r | |
961 | );\r | |
962 | if (EFI_ERROR (Status)) {\r | |
963 | return Status;\r | |
964 | }\r | |
74d0a339 HG |
965 | \r |
966 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
967 | \r | |
968 | // Address passed to CpuIo->Io.Write needs to be a host address instead of\r | |
969 | // device address.\r | |
970 | return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r | |
971 | TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);\r | |
4a50cf4e RN |
972 | }\r |
973 | \r | |
974 | /**\r | |
975 | Enables a PCI driver to copy one region of PCI root bridge memory space to\r | |
976 | another region of PCI root bridge memory space.\r | |
977 | \r | |
978 | The CopyMem() function enables a PCI driver to copy one region of PCI root\r | |
979 | bridge memory space to another region of PCI root bridge memory space. This\r | |
980 | is especially useful for video scroll operation on a memory mapped video\r | |
981 | buffer.\r | |
982 | The memory operations are carried out exactly as requested. The caller is\r | |
983 | responsible for satisfying any alignment and memory width restrictions that a\r | |
984 | PCI root bridge on a platform might require.\r | |
985 | \r | |
986 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
987 | instance.\r | |
988 | @param[in] Width Signifies the width of the memory operations.\r | |
989 | @param[in] DestAddress The destination address of the memory operation. The\r | |
990 | caller is responsible for aligning the DestAddress if\r | |
991 | required.\r | |
992 | @param[in] SrcAddress The source address of the memory operation. The caller\r | |
993 | is responsible for aligning the SrcAddress if\r | |
994 | required.\r | |
995 | @param[in] Count The number of memory operations to perform. Bytes\r | |
996 | moved is Width size * Count, starting at DestAddress\r | |
997 | and SrcAddress.\r | |
998 | \r | |
999 | @retval EFI_SUCCESS The data was copied from one memory region\r | |
1000 | to another memory region.\r | |
1001 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r | |
1002 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r | |
1003 | lack of resources.\r | |
1004 | **/\r | |
1005 | EFI_STATUS\r | |
1006 | EFIAPI\r | |
1007 | RootBridgeIoCopyMem (\r | |
1008 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1009 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1010 | IN UINT64 DestAddress,\r | |
1011 | IN UINT64 SrcAddress,\r | |
1012 | IN UINTN Count\r | |
1013 | )\r | |
1014 | {\r | |
1015 | EFI_STATUS Status;\r | |
1016 | BOOLEAN Forward;\r | |
1017 | UINTN Stride;\r | |
1018 | UINTN Index;\r | |
1019 | UINT64 Result;\r | |
1020 | \r | |
1021 | if ((UINT32) Width > EfiPciWidthUint64) {\r | |
1022 | return EFI_INVALID_PARAMETER;\r | |
1023 | }\r | |
1024 | \r | |
1025 | if (DestAddress == SrcAddress) {\r | |
1026 | return EFI_SUCCESS;\r | |
1027 | }\r | |
1028 | \r | |
1029 | Stride = (UINTN) (1 << Width);\r | |
1030 | \r | |
1031 | Forward = TRUE;\r | |
1032 | if ((DestAddress > SrcAddress) &&\r | |
1033 | (DestAddress < (SrcAddress + Count * Stride))) {\r | |
1034 | Forward = FALSE;\r | |
1035 | SrcAddress = SrcAddress + (Count - 1) * Stride;\r | |
1036 | DestAddress = DestAddress + (Count - 1) * Stride;\r | |
1037 | }\r | |
1038 | \r | |
1039 | for (Index = 0; Index < Count; Index++) {\r | |
1040 | Status = RootBridgeIoMemRead (\r | |
1041 | This,\r | |
1042 | Width,\r | |
1043 | SrcAddress,\r | |
1044 | 1,\r | |
1045 | &Result\r | |
1046 | );\r | |
1047 | if (EFI_ERROR (Status)) {\r | |
1048 | return Status;\r | |
1049 | }\r | |
1050 | Status = RootBridgeIoMemWrite (\r | |
1051 | This,\r | |
1052 | Width,\r | |
1053 | DestAddress,\r | |
1054 | 1,\r | |
1055 | &Result\r | |
1056 | );\r | |
1057 | if (EFI_ERROR (Status)) {\r | |
1058 | return Status;\r | |
1059 | }\r | |
1060 | if (Forward) {\r | |
1061 | SrcAddress += Stride;\r | |
1062 | DestAddress += Stride;\r | |
1063 | } else {\r | |
1064 | SrcAddress -= Stride;\r | |
1065 | DestAddress -= Stride;\r | |
1066 | }\r | |
1067 | }\r | |
1068 | return EFI_SUCCESS;\r | |
1069 | }\r | |
1070 | \r | |
1071 | \r | |
1072 | /**\r | |
1073 | PCI configuration space access.\r | |
1074 | \r | |
1075 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1076 | @param Read TRUE indicating it's a read operation.\r | |
1077 | @param Width Signifies the width of the memory operation.\r | |
1078 | @param Address The address within the PCI configuration space\r | |
1079 | for the PCI controller.\r | |
1080 | @param Count The number of PCI configuration operations\r | |
1081 | to perform.\r | |
1082 | @param Buffer The destination buffer to store the results.\r | |
1083 | \r | |
1084 | @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.\r | |
1085 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1086 | **/\r | |
1087 | EFI_STATUS\r | |
1088 | EFIAPI\r | |
1089 | RootBridgeIoPciAccess (\r | |
1090 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1091 | IN BOOLEAN Read,\r | |
1092 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1093 | IN UINT64 Address,\r | |
1094 | IN UINTN Count,\r | |
1095 | IN OUT VOID *Buffer\r | |
1096 | )\r | |
1097 | {\r | |
1098 | EFI_STATUS Status;\r | |
1099 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1100 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;\r | |
1101 | UINT8 *Uint8Buffer;\r | |
1102 | UINT8 InStride;\r | |
1103 | UINT8 OutStride;\r | |
1104 | UINTN Size;\r | |
1105 | \r | |
1106 | Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r | |
1107 | if (EFI_ERROR (Status)) {\r | |
1108 | return Status;\r | |
1109 | }\r | |
1110 | \r | |
1111 | //\r | |
1112 | // Read Pci configuration space\r | |
1113 | //\r | |
1114 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1115 | CopyMem (&PciAddress, &Address, sizeof (PciAddress));\r | |
1116 | \r | |
1117 | if (PciAddress.ExtendedRegister == 0) {\r | |
1118 | PciAddress.ExtendedRegister = PciAddress.Register;\r | |
1119 | }\r | |
1120 | \r | |
1121 | Address = PCI_SEGMENT_LIB_ADDRESS (\r | |
1122 | RootBridge->RootBridgeIo.SegmentNumber,\r | |
1123 | PciAddress.Bus,\r | |
1124 | PciAddress.Device,\r | |
1125 | PciAddress.Function,\r | |
1126 | PciAddress.ExtendedRegister\r | |
1127 | );\r | |
1128 | \r | |
1129 | //\r | |
1130 | // Select loop based on the width of the transfer\r | |
1131 | //\r | |
1132 | InStride = mInStride[Width];\r | |
1133 | OutStride = mOutStride[Width];\r | |
1134 | Size = (UINTN) (1 << (Width & 0x03));\r | |
1135 | for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r | |
1136 | if (Read) {\r | |
1137 | PciSegmentReadBuffer (Address, Size, Uint8Buffer);\r | |
1138 | } else {\r | |
1139 | PciSegmentWriteBuffer (Address, Size, Uint8Buffer);\r | |
1140 | }\r | |
1141 | }\r | |
1142 | return EFI_SUCCESS;\r | |
1143 | }\r | |
1144 | \r | |
1145 | /**\r | |
1146 | Allows read from PCI configuration space.\r | |
1147 | \r | |
1148 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1149 | @param Width Signifies the width of the memory operation.\r | |
1150 | @param Address The address within the PCI configuration space\r | |
1151 | for the PCI controller.\r | |
1152 | @param Count The number of PCI configuration operations\r | |
1153 | to perform.\r | |
1154 | @param Buffer The destination buffer to store the results.\r | |
1155 | \r | |
1156 | @retval EFI_SUCCESS The data was read from the PCI root bridge.\r | |
1157 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1158 | **/\r | |
1159 | EFI_STATUS\r | |
1160 | EFIAPI\r | |
1161 | RootBridgeIoPciRead (\r | |
1162 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1163 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1164 | IN UINT64 Address,\r | |
1165 | IN UINTN Count,\r | |
1166 | IN OUT VOID *Buffer\r | |
1167 | )\r | |
1168 | {\r | |
1169 | return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);\r | |
1170 | }\r | |
1171 | \r | |
1172 | /**\r | |
1173 | Allows write to PCI configuration space.\r | |
1174 | \r | |
1175 | @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
1176 | @param Width Signifies the width of the memory operation.\r | |
1177 | @param Address The address within the PCI configuration space\r | |
1178 | for the PCI controller.\r | |
1179 | @param Count The number of PCI configuration operations\r | |
1180 | to perform.\r | |
1181 | @param Buffer The source buffer to get the results.\r | |
1182 | \r | |
1183 | @retval EFI_SUCCESS The data was written to the PCI root bridge.\r | |
1184 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1185 | **/\r | |
1186 | EFI_STATUS\r | |
1187 | EFIAPI\r | |
1188 | RootBridgeIoPciWrite (\r | |
1189 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1190 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
1191 | IN UINT64 Address,\r | |
1192 | IN UINTN Count,\r | |
1193 | IN OUT VOID *Buffer\r | |
1194 | )\r | |
1195 | {\r | |
1196 | return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);\r | |
1197 | }\r | |
1198 | \r | |
1199 | /**\r | |
4a50cf4e RN |
1200 | Provides the PCI controller-specific address needed to access\r |
1201 | system memory for DMA.\r | |
1202 | \r | |
1203 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1204 | @param Operation Indicate if the bus master is going to read or write\r | |
1205 | to system memory.\r | |
1206 | @param HostAddress The system memory address to map on the PCI controller.\r | |
1207 | @param NumberOfBytes On input the number of bytes to map.\r | |
1208 | On output the number of bytes that were mapped.\r | |
1209 | @param DeviceAddress The resulting map address for the bus master PCI\r | |
1210 | controller to use to access the system memory's HostAddress.\r | |
1211 | @param Mapping The value to pass to Unmap() when the bus master DMA\r | |
1212 | operation is complete.\r | |
1213 | \r | |
1214 | @retval EFI_SUCCESS Success.\r | |
1215 | @retval EFI_INVALID_PARAMETER Invalid parameters found.\r | |
1216 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r | |
1217 | @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.\r | |
1218 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.\r | |
4a50cf4e RN |
1219 | **/\r |
1220 | EFI_STATUS\r | |
1221 | EFIAPI\r | |
1222 | RootBridgeIoMap (\r | |
1223 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1224 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r | |
1225 | IN VOID *HostAddress,\r | |
1226 | IN OUT UINTN *NumberOfBytes,\r | |
1227 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
1228 | OUT VOID **Mapping\r | |
1229 | )\r | |
1230 | {\r | |
1231 | EFI_STATUS Status;\r | |
1232 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1233 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
1234 | MAP_INFO *MapInfo;\r | |
1235 | \r | |
1236 | if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||\r | |
1237 | Mapping == NULL) {\r | |
1238 | return EFI_INVALID_PARAMETER;\r | |
1239 | }\r | |
1240 | \r | |
1241 | //\r | |
1242 | // Make sure that Operation is valid\r | |
1243 | //\r | |
1244 | if ((UINT32) Operation >= EfiPciOperationMaximum) {\r | |
1245 | return EFI_INVALID_PARAMETER;\r | |
1246 | }\r | |
1247 | \r | |
1248 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1249 | \r | |
c15da8eb JY |
1250 | if (mIoMmuProtocol != NULL) {\r |
1251 | if (!RootBridge->DmaAbove4G) {\r | |
1252 | //\r | |
1253 | // Clear 64bit support\r | |
1254 | //\r | |
1255 | if (Operation > EfiPciOperationBusMasterCommonBuffer) {\r | |
1256 | Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);\r | |
1257 | }\r | |
1258 | }\r | |
1259 | Status = mIoMmuProtocol->Map (\r | |
1260 | mIoMmuProtocol,\r | |
7a85e847 | 1261 | (EDKII_IOMMU_OPERATION) Operation,\r |
c15da8eb JY |
1262 | HostAddress,\r |
1263 | NumberOfBytes,\r | |
1264 | DeviceAddress,\r | |
1265 | Mapping\r | |
1266 | );\r | |
1267 | return Status;\r | |
1268 | }\r | |
1269 | \r | |
4a50cf4e | 1270 | PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r |
e58a71d9 AB |
1271 | if ((!RootBridge->DmaAbove4G ||\r |
1272 | (Operation != EfiPciOperationBusMasterRead64 &&\r | |
1273 | Operation != EfiPciOperationBusMasterWrite64 &&\r | |
1274 | Operation != EfiPciOperationBusMasterCommonBuffer64)) &&\r | |
1275 | ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {\r | |
1276 | \r | |
4a50cf4e | 1277 | //\r |
e58a71d9 AB |
1278 | // If the root bridge or the device cannot handle performing DMA above\r |
1279 | // 4GB but any part of the DMA transfer being mapped is above 4GB, then\r | |
4a50cf4e RN |
1280 | // map the DMA transfer to a buffer below 4GB.\r |
1281 | //\r | |
1282 | \r | |
1283 | if (Operation == EfiPciOperationBusMasterCommonBuffer ||\r | |
1284 | Operation == EfiPciOperationBusMasterCommonBuffer64) {\r | |
1285 | //\r | |
1286 | // Common Buffer operations can not be remapped. If the common buffer\r | |
1287 | // if above 4GB, then it is not possible to generate a mapping, so return\r | |
1288 | // an error.\r | |
1289 | //\r | |
1290 | return EFI_UNSUPPORTED;\r | |
1291 | }\r | |
1292 | \r | |
1293 | //\r | |
1294 | // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r | |
1295 | // called later.\r | |
1296 | //\r | |
1297 | MapInfo = AllocatePool (sizeof (MAP_INFO));\r | |
1298 | if (MapInfo == NULL) {\r | |
1299 | *NumberOfBytes = 0;\r | |
1300 | return EFI_OUT_OF_RESOURCES;\r | |
1301 | }\r | |
1302 | \r | |
1303 | //\r | |
1304 | // Initialize the MAP_INFO structure\r | |
1305 | //\r | |
1306 | MapInfo->Signature = MAP_INFO_SIGNATURE;\r | |
1307 | MapInfo->Operation = Operation;\r | |
1308 | MapInfo->NumberOfBytes = *NumberOfBytes;\r | |
1309 | MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);\r | |
1310 | MapInfo->HostAddress = PhysicalAddress;\r | |
1311 | MapInfo->MappedHostAddress = SIZE_4GB - 1;\r | |
1312 | \r | |
1313 | //\r | |
1314 | // Allocate a buffer below 4GB to map the transfer to.\r | |
1315 | //\r | |
1316 | Status = gBS->AllocatePages (\r | |
1317 | AllocateMaxAddress,\r | |
1318 | EfiBootServicesData,\r | |
1319 | MapInfo->NumberOfPages,\r | |
1320 | &MapInfo->MappedHostAddress\r | |
1321 | );\r | |
1322 | if (EFI_ERROR (Status)) {\r | |
1323 | FreePool (MapInfo);\r | |
1324 | *NumberOfBytes = 0;\r | |
1325 | return Status;\r | |
1326 | }\r | |
1327 | \r | |
1328 | //\r | |
1329 | // If this is a read operation from the Bus Master's point of view,\r | |
1330 | // then copy the contents of the real buffer into the mapped buffer\r | |
1331 | // so the Bus Master can read the contents of the real buffer.\r | |
1332 | //\r | |
1333 | if (Operation == EfiPciOperationBusMasterRead ||\r | |
1334 | Operation == EfiPciOperationBusMasterRead64) {\r | |
1335 | CopyMem (\r | |
1336 | (VOID *) (UINTN) MapInfo->MappedHostAddress,\r | |
1337 | (VOID *) (UINTN) MapInfo->HostAddress,\r | |
1338 | MapInfo->NumberOfBytes\r | |
1339 | );\r | |
1340 | }\r | |
1341 | \r | |
1342 | InsertTailList (&RootBridge->Maps, &MapInfo->Link);\r | |
1343 | \r | |
1344 | //\r | |
1345 | // The DeviceAddress is the address of the maped buffer below 4GB\r | |
1346 | //\r | |
1347 | *DeviceAddress = MapInfo->MappedHostAddress;\r | |
1348 | //\r | |
1349 | // Return a pointer to the MAP_INFO structure in Mapping\r | |
1350 | //\r | |
1351 | *Mapping = MapInfo;\r | |
1352 | } else {\r | |
1353 | //\r | |
1354 | // If the root bridge CAN handle performing DMA above 4GB or\r | |
1355 | // the transfer is below 4GB, so the DeviceAddress is simply the\r | |
1356 | // HostAddress\r | |
1357 | //\r | |
1358 | *DeviceAddress = PhysicalAddress;\r | |
1359 | *Mapping = NO_MAPPING;\r | |
1360 | }\r | |
1361 | \r | |
1362 | return EFI_SUCCESS;\r | |
1363 | }\r | |
1364 | \r | |
1365 | /**\r | |
1366 | Completes the Map() operation and releases any corresponding resources.\r | |
1367 | \r | |
1368 | The Unmap() function completes the Map() operation and releases any\r | |
1369 | corresponding resources.\r | |
1370 | If the operation was an EfiPciOperationBusMasterWrite or\r | |
1371 | EfiPciOperationBusMasterWrite64, the data is committed to the target system\r | |
1372 | memory.\r | |
1373 | Any resources used for the mapping are freed.\r | |
1374 | \r | |
1375 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1376 | @param[in] Mapping The mapping value returned from Map().\r | |
1377 | \r | |
1378 | @retval EFI_SUCCESS The range was unmapped.\r | |
1379 | @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r | |
1380 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
1381 | **/\r | |
1382 | EFI_STATUS\r | |
1383 | EFIAPI\r | |
1384 | RootBridgeIoUnmap (\r | |
1385 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1386 | IN VOID *Mapping\r | |
1387 | )\r | |
1388 | {\r | |
1389 | MAP_INFO *MapInfo;\r | |
1390 | LIST_ENTRY *Link;\r | |
1391 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
c15da8eb JY |
1392 | EFI_STATUS Status;\r |
1393 | \r | |
1394 | if (mIoMmuProtocol != NULL) {\r | |
1395 | Status = mIoMmuProtocol->Unmap (\r | |
1396 | mIoMmuProtocol,\r | |
1397 | Mapping\r | |
1398 | );\r | |
1399 | return Status;\r | |
1400 | }\r | |
4a50cf4e RN |
1401 | \r |
1402 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
c15da8eb | 1403 | \r |
4a50cf4e RN |
1404 | //\r |
1405 | // See if the Map() operation associated with this Unmap() required a mapping\r | |
1406 | // buffer. If a mapping buffer was not required, then this function simply\r | |
1407 | // returns EFI_SUCCESS.\r | |
1408 | //\r | |
1409 | if (Mapping == NO_MAPPING) {\r | |
1410 | return EFI_SUCCESS;\r | |
1411 | }\r | |
1412 | \r | |
1413 | MapInfo = NO_MAPPING;\r | |
1414 | for (Link = GetFirstNode (&RootBridge->Maps)\r | |
1415 | ; !IsNull (&RootBridge->Maps, Link)\r | |
1416 | ; Link = GetNextNode (&RootBridge->Maps, Link)\r | |
1417 | ) {\r | |
1418 | MapInfo = MAP_INFO_FROM_LINK (Link);\r | |
1419 | if (MapInfo == Mapping) {\r | |
1420 | break;\r | |
1421 | }\r | |
1422 | }\r | |
1423 | //\r | |
1424 | // Mapping is not a valid value returned by Map()\r | |
1425 | //\r | |
1426 | if (MapInfo != Mapping) {\r | |
1427 | return EFI_INVALID_PARAMETER;\r | |
1428 | }\r | |
1429 | RemoveEntryList (&MapInfo->Link);\r | |
1430 | \r | |
1431 | //\r | |
1432 | // If this is a write operation from the Bus Master's point of view,\r | |
1433 | // then copy the contents of the mapped buffer into the real buffer\r | |
1434 | // so the processor can read the contents of the real buffer.\r | |
1435 | //\r | |
1436 | if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||\r | |
1437 | MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r | |
1438 | CopyMem (\r | |
1439 | (VOID *) (UINTN) MapInfo->HostAddress,\r | |
1440 | (VOID *) (UINTN) MapInfo->MappedHostAddress,\r | |
1441 | MapInfo->NumberOfBytes\r | |
1442 | );\r | |
1443 | }\r | |
1444 | \r | |
1445 | //\r | |
1446 | // Free the mapped buffer and the MAP_INFO structure.\r | |
1447 | //\r | |
1448 | gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r | |
1449 | FreePool (Mapping);\r | |
1450 | return EFI_SUCCESS;\r | |
1451 | }\r | |
1452 | \r | |
1453 | /**\r | |
1454 | Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer\r | |
1455 | or EfiPciOperationBusMasterCommonBuffer64 mapping.\r | |
1456 | \r | |
1457 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1458 | @param Type This parameter is not used and must be ignored.\r | |
1459 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
1460 | EfiRuntimeServicesData.\r | |
1461 | @param Pages The number of pages to allocate.\r | |
1462 | @param HostAddress A pointer to store the base system memory address of the\r | |
1463 | allocated range.\r | |
1464 | @param Attributes The requested bit mask of attributes for the allocated\r | |
1465 | range. Only the attributes\r | |
1466 | EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,\r | |
1467 | EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and\r | |
1468 | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this\r | |
1469 | function.\r | |
1470 | \r | |
1471 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
1472 | @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r | |
1473 | @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r | |
1474 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal\r | |
1475 | attribute bits are MEMORY_WRITE_COMBINE,\r | |
1476 | MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r | |
1477 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r | |
1478 | **/\r | |
1479 | EFI_STATUS\r | |
1480 | EFIAPI\r | |
1481 | RootBridgeIoAllocateBuffer (\r | |
1482 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1483 | IN EFI_ALLOCATE_TYPE Type,\r | |
1484 | IN EFI_MEMORY_TYPE MemoryType,\r | |
1485 | IN UINTN Pages,\r | |
1486 | OUT VOID **HostAddress,\r | |
1487 | IN UINT64 Attributes\r | |
1488 | )\r | |
1489 | {\r | |
1490 | EFI_STATUS Status;\r | |
1491 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
1492 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1493 | EFI_ALLOCATE_TYPE AllocateType;\r | |
1494 | \r | |
1495 | //\r | |
1496 | // Validate Attributes\r | |
1497 | //\r | |
1498 | if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r | |
1499 | return EFI_UNSUPPORTED;\r | |
1500 | }\r | |
1501 | \r | |
1502 | //\r | |
1503 | // Check for invalid inputs\r | |
1504 | //\r | |
1505 | if (HostAddress == NULL) {\r | |
1506 | return EFI_INVALID_PARAMETER;\r | |
1507 | }\r | |
1508 | \r | |
1509 | //\r | |
1510 | // The only valid memory types are EfiBootServicesData and\r | |
1511 | // EfiRuntimeServicesData\r | |
1512 | //\r | |
1513 | if (MemoryType != EfiBootServicesData &&\r | |
1514 | MemoryType != EfiRuntimeServicesData) {\r | |
1515 | return EFI_INVALID_PARAMETER;\r | |
1516 | }\r | |
1517 | \r | |
1518 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1519 | \r | |
c15da8eb JY |
1520 | if (mIoMmuProtocol != NULL) {\r |
1521 | if (!RootBridge->DmaAbove4G) {\r | |
1522 | //\r | |
1523 | // Clear DUAL_ADDRESS_CYCLE\r | |
1524 | //\r | |
8df95dd0 | 1525 | Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r |
c15da8eb JY |
1526 | }\r |
1527 | Status = mIoMmuProtocol->AllocateBuffer (\r | |
1528 | mIoMmuProtocol,\r | |
1529 | Type,\r | |
1530 | MemoryType,\r | |
1531 | Pages,\r | |
1532 | HostAddress,\r | |
1533 | Attributes\r | |
1534 | );\r | |
1535 | return Status;\r | |
1536 | }\r | |
1537 | \r | |
4a50cf4e | 1538 | AllocateType = AllocateAnyPages;\r |
e58a71d9 AB |
1539 | if (!RootBridge->DmaAbove4G ||\r |
1540 | (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {\r | |
4a50cf4e RN |
1541 | //\r |
1542 | // Limit allocations to memory below 4GB\r | |
1543 | //\r | |
1544 | AllocateType = AllocateMaxAddress;\r | |
1545 | PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);\r | |
1546 | }\r | |
1547 | Status = gBS->AllocatePages (\r | |
1548 | AllocateType,\r | |
1549 | MemoryType,\r | |
1550 | Pages,\r | |
1551 | &PhysicalAddress\r | |
1552 | );\r | |
1553 | if (!EFI_ERROR (Status)) {\r | |
1554 | *HostAddress = (VOID *) (UINTN) PhysicalAddress;\r | |
1555 | }\r | |
1556 | \r | |
1557 | return Status;\r | |
1558 | }\r | |
1559 | \r | |
1560 | /**\r | |
1561 | Frees memory that was allocated with AllocateBuffer().\r | |
1562 | \r | |
1563 | The FreeBuffer() function frees memory that was allocated with\r | |
1564 | AllocateBuffer().\r | |
1565 | \r | |
1566 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1567 | @param Pages The number of pages to free.\r | |
1568 | @param HostAddress The base system memory address of the allocated range.\r | |
1569 | \r | |
1570 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
1571 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and\r | |
1572 | Pages was not allocated with AllocateBuffer().\r | |
1573 | **/\r | |
1574 | EFI_STATUS\r | |
1575 | EFIAPI\r | |
1576 | RootBridgeIoFreeBuffer (\r | |
1577 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1578 | IN UINTN Pages,\r | |
1579 | OUT VOID *HostAddress\r | |
1580 | )\r | |
1581 | {\r | |
c15da8eb JY |
1582 | EFI_STATUS Status;\r |
1583 | \r | |
1584 | if (mIoMmuProtocol != NULL) {\r | |
1585 | Status = mIoMmuProtocol->FreeBuffer (\r | |
1586 | mIoMmuProtocol,\r | |
1587 | Pages,\r | |
1588 | HostAddress\r | |
1589 | );\r | |
1590 | return Status;\r | |
1591 | }\r | |
1592 | \r | |
4a50cf4e RN |
1593 | return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r |
1594 | }\r | |
1595 | \r | |
1596 | /**\r | |
1597 | Flushes all PCI posted write transactions from a PCI host bridge to system\r | |
1598 | memory.\r | |
1599 | \r | |
1600 | The Flush() function flushes any PCI posted write transactions from a PCI\r | |
1601 | host bridge to system memory. Posted write transactions are generated by PCI\r | |
1602 | bus masters when they perform write transactions to target addresses in\r | |
1603 | system memory.\r | |
1604 | This function does not flush posted write transactions from any PCI bridges.\r | |
1605 | A PCI controller specific action must be taken to guarantee that the posted\r | |
1606 | write transactions have been flushed from the PCI controller and from all the\r | |
1607 | PCI bridges into the PCI host bridge. This is typically done with a PCI read\r | |
1608 | transaction from the PCI controller prior to calling Flush().\r | |
1609 | \r | |
1610 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1611 | \r | |
1612 | @retval EFI_SUCCESS The PCI posted write transactions were flushed\r | |
1613 | from the PCI host bridge to system memory.\r | |
1614 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed\r | |
1615 | from the PCI host bridge due to a hardware error.\r | |
1616 | **/\r | |
1617 | EFI_STATUS\r | |
1618 | EFIAPI\r | |
1619 | RootBridgeIoFlush (\r | |
1620 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r | |
1621 | )\r | |
1622 | {\r | |
1623 | return EFI_SUCCESS;\r | |
1624 | }\r | |
1625 | \r | |
1626 | /**\r | |
1627 | Gets the attributes that a PCI root bridge supports setting with\r | |
1628 | SetAttributes(), and the attributes that a PCI root bridge is currently\r | |
1629 | using.\r | |
1630 | \r | |
1631 | The GetAttributes() function returns the mask of attributes that this PCI\r | |
1632 | root bridge supports and the mask of attributes that the PCI root bridge is\r | |
1633 | currently using.\r | |
1634 | \r | |
1635 | @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1636 | @param Supported A pointer to the mask of attributes that this PCI root\r | |
1637 | bridge supports setting with SetAttributes().\r | |
1638 | @param Attributes A pointer to the mask of attributes that this PCI root\r | |
1639 | bridge is currently using.\r | |
1640 | \r | |
1641 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes\r | |
1642 | that the PCI root bridge supports is returned\r | |
1643 | in Supports. If Attributes is not NULL, then\r | |
1644 | the attributes that the PCI root bridge is\r | |
1645 | currently using is returned in Attributes.\r | |
1646 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r | |
1647 | **/\r | |
1648 | EFI_STATUS\r | |
1649 | EFIAPI\r | |
1650 | RootBridgeIoGetAttributes (\r | |
1651 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1652 | OUT UINT64 *Supported,\r | |
1653 | OUT UINT64 *Attributes\r | |
1654 | )\r | |
1655 | {\r | |
1656 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1657 | \r | |
1658 | if (Attributes == NULL && Supported == NULL) {\r | |
1659 | return EFI_INVALID_PARAMETER;\r | |
1660 | }\r | |
1661 | \r | |
1662 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1663 | //\r | |
1664 | // Set the return value for Supported and Attributes\r | |
1665 | //\r | |
1666 | if (Supported != NULL) {\r | |
1667 | *Supported = RootBridge->Supports;\r | |
1668 | }\r | |
1669 | \r | |
1670 | if (Attributes != NULL) {\r | |
1671 | *Attributes = RootBridge->Attributes;\r | |
1672 | }\r | |
1673 | \r | |
1674 | return EFI_SUCCESS;\r | |
1675 | }\r | |
1676 | \r | |
1677 | /**\r | |
1678 | Sets attributes for a resource range on a PCI root bridge.\r | |
1679 | \r | |
1680 | The SetAttributes() function sets the attributes specified in Attributes for\r | |
1681 | the PCI root bridge on the resource range specified by ResourceBase and\r | |
1682 | ResourceLength. Since the granularity of setting these attributes may vary\r | |
1683 | from resource type to resource type, and from platform to platform, the\r | |
1684 | actual resource range and the one passed in by the caller may differ. As a\r | |
1685 | result, this function may set the attributes specified by Attributes on a\r | |
1686 | larger resource range than the caller requested. The actual range is returned\r | |
1687 | in ResourceBase and ResourceLength. The caller is responsible for verifying\r | |
1688 | that the actual range for which the attributes were set is acceptable.\r | |
1689 | \r | |
1690 | @param This A pointer to the\r | |
1691 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
1692 | @param Attributes The mask of attributes to set. If the\r | |
1693 | attribute bit MEMORY_WRITE_COMBINE,\r | |
1694 | MEMORY_CACHED, or MEMORY_DISABLE is set,\r | |
1695 | then the resource range is specified by\r | |
1696 | ResourceBase and ResourceLength. If\r | |
1697 | MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r | |
1698 | MEMORY_DISABLE are not set, then\r | |
1699 | ResourceBase and ResourceLength are ignored,\r | |
1700 | and may be NULL.\r | |
1701 | @param ResourceBase A pointer to the base address of the\r | |
1702 | resource range to be modified by the\r | |
1703 | attributes specified by Attributes.\r | |
1704 | @param ResourceLength A pointer to the length of the resource\r | |
1705 | range to be modified by the attributes\r | |
1706 | specified by Attributes.\r | |
1707 | \r | |
1708 | @retval EFI_SUCCESS The current configuration of this PCI root bridge\r | |
1709 | was returned in Resources.\r | |
1710 | @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r | |
1711 | could not be retrieved.\r | |
1712 | **/\r | |
1713 | EFI_STATUS\r | |
1714 | EFIAPI\r | |
1715 | RootBridgeIoSetAttributes (\r | |
1716 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1717 | IN UINT64 Attributes,\r | |
1718 | IN OUT UINT64 *ResourceBase,\r | |
1719 | IN OUT UINT64 *ResourceLength\r | |
1720 | )\r | |
1721 | {\r | |
1722 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1723 | \r | |
1724 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1725 | \r | |
1726 | if ((Attributes & (~RootBridge->Supports)) != 0) {\r | |
1727 | return EFI_UNSUPPORTED;\r | |
1728 | }\r | |
1729 | \r | |
1730 | RootBridge->Attributes = Attributes;\r | |
1731 | return EFI_SUCCESS;\r | |
1732 | }\r | |
1733 | \r | |
1734 | /**\r | |
1735 | Retrieves the current resource settings of this PCI root bridge in the form\r | |
6fbaed1f | 1736 | of a set of ACPI resource descriptors.\r |
4a50cf4e RN |
1737 | \r |
1738 | There are only two resource descriptor types from the ACPI Specification that\r | |
1739 | may be used to describe the current resources allocated to a PCI root bridge.\r | |
6fbaed1f DB |
1740 | These are the QWORD Address Space Descriptor, and the End Tag. The QWORD\r |
1741 | Address Space Descriptor can describe memory, I/O, and bus number ranges for\r | |
1742 | dynamic or fixed resources. The configuration of a PCI root bridge is described\r | |
1743 | with one or more QWORD Address Space Descriptors followed by an End Tag.\r | |
4a50cf4e RN |
1744 | \r |
1745 | @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
6fbaed1f | 1746 | @param[out] Resources A pointer to the resource descriptors that\r |
4a50cf4e | 1747 | describe the current configuration of this PCI root\r |
6fbaed1f | 1748 | bridge. The storage for the resource\r |
4a50cf4e RN |
1749 | descriptors is allocated by this function. The\r |
1750 | caller must treat the return buffer as read-only\r | |
1751 | data, and the buffer must not be freed by the\r | |
1752 | caller.\r | |
1753 | \r | |
1754 | @retval EFI_SUCCESS The current configuration of this PCI root bridge\r | |
1755 | was returned in Resources.\r | |
1756 | @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge\r | |
1757 | could not be retrieved.\r | |
1758 | **/\r | |
1759 | EFI_STATUS\r | |
1760 | EFIAPI\r | |
1761 | RootBridgeIoConfiguration (\r | |
1762 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r | |
1763 | OUT VOID **Resources\r | |
1764 | )\r | |
1765 | {\r | |
1766 | PCI_RESOURCE_TYPE Index;\r | |
1767 | PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r | |
1768 | PCI_RES_NODE *ResAllocNode;\r | |
1769 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r | |
1770 | EFI_ACPI_END_TAG_DESCRIPTOR *End;\r | |
1771 | \r | |
1772 | //\r | |
1773 | // Get this instance of the Root Bridge.\r | |
1774 | //\r | |
1775 | RootBridge = ROOT_BRIDGE_FROM_THIS (This);\r | |
1776 | ZeroMem (\r | |
1777 | RootBridge->ConfigBuffer,\r | |
1778 | TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r | |
1779 | );\r | |
1780 | Descriptor = RootBridge->ConfigBuffer;\r | |
1781 | for (Index = TypeIo; Index < TypeMax; Index++) {\r | |
1782 | \r | |
1783 | ResAllocNode = &RootBridge->ResAllocNode[Index];\r | |
1784 | \r | |
1785 | if (ResAllocNode->Status != ResAllocated) {\r | |
1786 | continue;\r | |
1787 | }\r | |
1788 | \r | |
1789 | Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r | |
1790 | Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r | |
74d0a339 HG |
1791 | // According to UEFI 2.7, RootBridgeIo->Configuration should return address\r |
1792 | // range in CPU view (host address), and ResAllocNode->Base is already a CPU\r | |
1793 | // view address (host address).\r | |
4a50cf4e RN |
1794 | Descriptor->AddrRangeMin = ResAllocNode->Base;\r |
1795 | Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r | |
1796 | Descriptor->AddrLen = ResAllocNode->Length;\r | |
74d0a339 HG |
1797 | Descriptor->AddrTranslationOffset = GetTranslationByResourceType (\r |
1798 | RootBridge,\r | |
1799 | ResAllocNode->Type\r | |
1800 | );\r | |
1801 | \r | |
4a50cf4e RN |
1802 | switch (ResAllocNode->Type) {\r |
1803 | \r | |
1804 | case TypeIo:\r | |
1805 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r | |
1806 | break;\r | |
1807 | \r | |
1808 | case TypePMem32:\r | |
1809 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r | |
1810 | case TypeMem32:\r | |
1811 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1812 | Descriptor->AddrSpaceGranularity = 32;\r | |
1813 | break;\r | |
1814 | \r | |
1815 | case TypePMem64:\r | |
1816 | Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r | |
1817 | case TypeMem64:\r | |
1818 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
1819 | Descriptor->AddrSpaceGranularity = 64;\r | |
1820 | break;\r | |
1821 | \r | |
1822 | case TypeBus:\r | |
1823 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r | |
1824 | break;\r | |
1825 | \r | |
1826 | default:\r | |
1827 | break;\r | |
1828 | }\r | |
1829 | \r | |
1830 | Descriptor++;\r | |
1831 | }\r | |
1832 | //\r | |
1833 | // Terminate the entries.\r | |
1834 | //\r | |
1835 | End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;\r | |
1836 | End->Desc = ACPI_END_TAG_DESCRIPTOR;\r | |
1837 | End->Checksum = 0x0;\r | |
1838 | \r | |
1839 | *Resources = RootBridge->ConfigBuffer;\r | |
1840 | return EFI_SUCCESS;\r | |
1841 | }\r |