MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

   1 /** @file
   2
   3   PCI Root Bridge Io Protocol code.
   4
   5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "PciHostBridge.h"
  17 #include "PciRootBridge.h"
  18 #include "PciHostResource.h"
  19
  20 extern EDKII_IOMMU_PROTOCOL        *mIoMmuProtocol;
  21
  22 #define NO_MAPPING  (VOID *) (UINTN) -1
  23
  24 //
  25 // Lookup table for increment values based on transfer widths
  26 //
  27 UINT8 mInStride[] = {
  28   1, // EfiPciWidthUint8
  29   2, // EfiPciWidthUint16
  30   4, // EfiPciWidthUint32
  31   8, // EfiPciWidthUint64
  32   0, // EfiPciWidthFifoUint8
  33   0, // EfiPciWidthFifoUint16
  34   0, // EfiPciWidthFifoUint32
  35   0, // EfiPciWidthFifoUint64
  36   1, // EfiPciWidthFillUint8
  37   2, // EfiPciWidthFillUint16
  38   4, // EfiPciWidthFillUint32
  39   8  // EfiPciWidthFillUint64
  40 };
  41
  42 //
  43 // Lookup table for increment values based on transfer widths
  44 //
  45 UINT8 mOutStride[] = {
  46   1, // EfiPciWidthUint8
  47   2, // EfiPciWidthUint16
  48   4, // EfiPciWidthUint32
  49   8, // EfiPciWidthUint64
  50   1, // EfiPciWidthFifoUint8
  51   2, // EfiPciWidthFifoUint16
  52   4, // EfiPciWidthFifoUint32
  53   8, // EfiPciWidthFifoUint64
  54   0, // EfiPciWidthFillUint8
  55   0, // EfiPciWidthFillUint16
  56   0, // EfiPciWidthFillUint32
  57   0  // EfiPciWidthFillUint64
  58 };
  59
  60 /**
  61   Construct the Pci Root Bridge instance.
  62
  63   @param Bridge            The root bridge instance.
  64
  65   @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
  66           or NULL if creation fails.
  67 **/
  68 PCI_ROOT_BRIDGE_INSTANCE *
  69 CreateRootBridge (
  70   IN PCI_ROOT_BRIDGE       *Bridge
  71   )
  72 {
  73   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
  74   PCI_RESOURCE_TYPE        Index;
  75   CHAR16                   *DevicePathStr;
  76   PCI_ROOT_BRIDGE_APERTURE *Aperture;
  77
  78   DevicePathStr = NULL;
  79
  80   DEBUG ((EFI_D_INFO, "RootBridge: "));
  81   DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
  82   DEBUG ((EFI_D_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
  83   DEBUG ((EFI_D_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
  84   DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
  85   DEBUG ((EFI_D_INFO, "     AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
  86           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
  87           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
  88           ));
  89   DEBUG ((
  90     EFI_D_INFO, "           Bus: %lx - %lx Translation=%lx\n",
  91     Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
  92     ));
  93   //
  94   // Translation for bus is not supported.
  95   //
  96   ASSERT (Bridge->Bus.Translation == 0);
  97   if (Bridge->Bus.Translation != 0) {
  98     return NULL;
  99   }
 100
 101   DEBUG ((
 102     DEBUG_INFO, "            Io: %lx - %lx Translation=%lx\n",
 103     Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
 104     ));
 105   DEBUG ((
 106     DEBUG_INFO, "           Mem: %lx - %lx Translation=%lx\n",
 107     Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
 108     ));
 109   DEBUG ((
 110     DEBUG_INFO, "    MemAbove4G: %lx - %lx Translation=%lx\n",
 111     Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation
 112     ));
 113   DEBUG ((
 114     DEBUG_INFO, "          PMem: %lx - %lx Translation=%lx\n",
 115     Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
 116     ));
 117   DEBUG ((
 118     DEBUG_INFO, "   PMemAbove4G: %lx - %lx Translation=%lx\n",
 119     Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation
 120     ));
 121
 122   //
 123   // Make sure Mem and MemAbove4G apertures are valid
 124   //
 125   if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
 126     ASSERT (Bridge->Mem.Limit < SIZE_4GB);
 127     if (Bridge->Mem.Limit >= SIZE_4GB) {
 128       return NULL;
 129     }
 130   }
 131   if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
 132     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
 133     if (Bridge->MemAbove4G.Base < SIZE_4GB) {
 134       return NULL;
 135     }
 136   }
 137   if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
 138     ASSERT (Bridge->PMem.Limit < SIZE_4GB);
 139     if (Bridge->PMem.Limit >= SIZE_4GB) {
 140       return NULL;
 141     }
 142   }
 143   if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
 144     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
 145     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
 146       return NULL;
 147     }
 148   }
 149
 150   //
 151   // Ignore AllocationAttributes when resources were already assigned.
 152   //
 153   if (!Bridge->ResourceAssigned) {
 154     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
 155       //
 156       // If this bit is set, then the PCI Root Bridge does not
 157       // support separate windows for Non-prefetchable and Prefetchable
 158       // memory.
 159       //
 160       ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
 161       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 162       if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
 163           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 164           ) {
 165         return NULL;
 166       }
 167     }
 168
 169     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {
 170       //
 171       // If this bit is not set, then the PCI Root Bridge does not support
 172       // 64 bit memory windows.
 173       //
 174       ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
 175       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 176       if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
 177           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 178           ) {
 179         return NULL;
 180       }
 181     }
 182   }
 183
 184   RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
 185   ASSERT (RootBridge != NULL);
 186
 187   RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
 188   RootBridge->Supports = Bridge->Supports;
 189   RootBridge->Attributes = Bridge->Attributes;
 190   RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
 191   RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
 192   RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
 193   RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
 194   RootBridge->DevicePathStr = DevicePathStr;
 195   RootBridge->ConfigBuffer = AllocatePool (
 196     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
 197     );
 198   ASSERT (RootBridge->ConfigBuffer != NULL);
 199   InitializeListHead (&RootBridge->Maps);
 200
 201   CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 202   CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 203   CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 204   CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 205   CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 206   CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 207
 208   for (Index = TypeIo; Index < TypeMax; Index++) {
 209     switch (Index) {
 210     case TypeBus:
 211       Aperture = &RootBridge->Bus;
 212       break;
 213     case TypeIo:
 214       Aperture = &RootBridge->Io;
 215       break;
 216     case TypeMem32:
 217       Aperture = &RootBridge->Mem;
 218       break;
 219     case TypeMem64:
 220       Aperture = &RootBridge->MemAbove4G;
 221       break;
 222     case TypePMem32:
 223       Aperture = &RootBridge->PMem;
 224       break;
 225     case TypePMem64:
 226       Aperture = &RootBridge->PMemAbove4G;
 227       break;
 228     default:
 229       ASSERT (FALSE);
 230       Aperture = NULL;
 231       break;
 232     }
 233     RootBridge->ResAllocNode[Index].Type     = Index;
 234     if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
 235       //
 236       // Base in ResAllocNode is a host address, while Base in Aperture is a
 237       // device address.
 238       //
 239       RootBridge->ResAllocNode[Index].Base   = TO_HOST_ADDRESS (Aperture->Base,
 240         Aperture->Translation);
 241       RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
 242       RootBridge->ResAllocNode[Index].Status = ResAllocated;
 243     } else {
 244       RootBridge->ResAllocNode[Index].Base   = 0;
 245       RootBridge->ResAllocNode[Index].Length = 0;
 246       RootBridge->ResAllocNode[Index].Status = ResNone;
 247     }
 248   }
 249
 250   RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;
 251   RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;
 252   RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;
 253   RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;
 254   RootBridge->RootBridgeIo.Mem.Write      = RootBridgeIoMemWrite;
 255   RootBridge->RootBridgeIo.Io.Read        = RootBridgeIoIoRead;
 256   RootBridge->RootBridgeIo.Io.Write       = RootBridgeIoIoWrite;
 257   RootBridge->RootBridgeIo.CopyMem        = RootBridgeIoCopyMem;
 258   RootBridge->RootBridgeIo.Pci.Read       = RootBridgeIoPciRead;
 259   RootBridge->RootBridgeIo.Pci.Write      = RootBridgeIoPciWrite;
 260   RootBridge->RootBridgeIo.Map            = RootBridgeIoMap;
 261   RootBridge->RootBridgeIo.Unmap          = RootBridgeIoUnmap;
 262   RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;
 263   RootBridge->RootBridgeIo.FreeBuffer     = RootBridgeIoFreeBuffer;
 264   RootBridge->RootBridgeIo.Flush          = RootBridgeIoFlush;
 265   RootBridge->RootBridgeIo.GetAttributes  = RootBridgeIoGetAttributes;
 266   RootBridge->RootBridgeIo.SetAttributes  = RootBridgeIoSetAttributes;
 267   RootBridge->RootBridgeIo.Configuration  = RootBridgeIoConfiguration;
 268
 269   return RootBridge;
 270 }
 271
 272 /**
 273   Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
 274
 275   The I/O operations are carried out exactly as requested. The caller is
 276   responsible for satisfying any alignment and I/O width restrictions that a PI
 277   System on a platform might require. For example on some platforms, width
 278   requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
 279   hand, will be handled by the driver.
 280
 281   @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 282
 283   @param[in] OperationType  I/O operation type: IO/MMIO/PCI.
 284
 285   @param[in] Width          Signifies the width of the I/O or Memory operation.
 286
 287   @param[in] Address        The base address of the I/O operation.
 288
 289   @param[in] Count          The number of I/O operations to perform. The number
 290                             of bytes moved is Width size * Count, starting at
 291                             Address.
 292
 293   @param[in] Buffer         For read operations, the destination buffer to
 294                             store the results. For write operations, the source
 295                             buffer from which to write data.
 296
 297   @retval EFI_SUCCESS            The parameters for this request pass the
 298                                  checks.
 299
 300   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
 301
 302   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 303
 304   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
 305
 306   @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
 307                                  and Count is not valid for this PI system.
 308 **/
 309 EFI_STATUS
 310 RootBridgeIoCheckParameter (
 311   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 312   IN OPERATION_TYPE                         OperationType,
 313   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 314   IN UINT64                                 Address,
 315   IN UINTN                                  Count,
 316   IN VOID                                   *Buffer
 317   )
 318 {
 319   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
 320   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;
 321   UINT64                                       Base;
 322   UINT64                                       Limit;
 323   UINT32                                       Size;
 324
 325   //
 326   // Check to see if Buffer is NULL
 327   //
 328   if (Buffer == NULL) {
 329     return EFI_INVALID_PARAMETER;
 330   }
 331
 332   //
 333   // Check to see if Width is in the valid range
 334   //
 335   if ((UINT32) Width >= EfiPciWidthMaximum) {
 336     return EFI_INVALID_PARAMETER;
 337   }
 338
 339   //
 340   // For FIFO type, the target address won't increase during the access,
 341   // so treat Count as 1
 342   //
 343   if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
 344     Count = 1;
 345   }
 346
 347   Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
 348   Size  = 1 << Width;
 349
 350   //
 351   // Check to see if Address is aligned
 352   //
 353   if ((Address & (Size - 1)) != 0) {
 354     return EFI_UNSUPPORTED;
 355   }
 356
 357   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 358
 359   //
 360   // Check to see if any address associated with this transfer exceeds the
 361   // maximum allowed address.  The maximum address implied by the parameters
 362   // passed in is Address + Size * Count.  If the following condition is met,
 363   // then the transfer is not supported.
 364   //
 365   //    Address + Size * Count > Limit + 1
 366   //
 367   // Since Limit can be the maximum integer value supported by the CPU and
 368   // Count can also be the maximum integer value supported by the CPU, this
 369   // range check must be adjusted to avoid all oveflow conditions.
 370   //
 371   if (OperationType == IoOperation) {
 372     //
 373     // Allow Legacy IO access
 374     //
 375     if (Address + MultU64x32 (Count, Size) <= 0x1000) {
 376       if ((RootBridge->Attributes & (
 377            EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 378            EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
 379            EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {
 380         return EFI_SUCCESS;
 381       }
 382     }
 383     Base = RootBridge->Io.Base;
 384     Limit = RootBridge->Io.Limit;
 385   } else if (OperationType == MemOperation) {
 386     //
 387     // Allow Legacy MMIO access
 388     //
 389     if ((Address >= 0xA0000) && (Address + MultU64x32 (Count, Size)) <= 0xC0000) {
 390       if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
 391         return EFI_SUCCESS;
 392       }
 393     }
 394     //
 395     // By comparing the Address against Limit we know which range to be used
 396     // for checking
 397     //
 398     if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {
 399       Base = RootBridge->Mem.Base;
 400       Limit = RootBridge->Mem.Limit;
 401     } else {
 402       Base = RootBridge->MemAbove4G.Base;
 403       Limit = RootBridge->MemAbove4G.Limit;
 404     }
 405   } else {
 406     PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
 407     if (PciRbAddr->Bus < RootBridge->Bus.Base ||
 408         PciRbAddr->Bus > RootBridge->Bus.Limit) {
 409       return EFI_INVALID_PARAMETER;
 410     }
 411
 412     if (PciRbAddr->Device > PCI_MAX_DEVICE ||
 413         PciRbAddr->Function > PCI_MAX_FUNC) {
 414       return EFI_INVALID_PARAMETER;
 415     }
 416
 417     if (PciRbAddr->ExtendedRegister != 0) {
 418       Address = PciRbAddr->ExtendedRegister;
 419     } else {
 420       Address = PciRbAddr->Register;
 421     }
 422     Base = 0;
 423     Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
 424   }
 425
 426   if (Address < Base) {
 427       return EFI_INVALID_PARAMETER;
 428   }
 429
 430   if (Address + MultU64x32 (Count, Size) > Limit + 1) {
 431     return EFI_INVALID_PARAMETER;
 432   }
 433
 434   return EFI_SUCCESS;
 435 }
 436
 437 /**
 438   Use address to match apertures of memory type and then get the corresponding
 439   translation.
 440
 441   @param RootBridge              The root bridge instance.
 442   @param Address                 The address used to match aperture.
 443   @param Translation             Pointer containing the output translation.
 444
 445   @return EFI_SUCCESS            Get translation successfully.
 446   @return EFI_INVALID_PARAMETER  No matched memory aperture; the input Address
 447                                  must be invalid.
 448 **/
 449 EFI_STATUS
 450 RootBridgeIoGetMemTranslationByAddress (
 451   IN PCI_ROOT_BRIDGE_INSTANCE               *RootBridge,
 452   IN UINT64                                 Address,
 453   IN OUT UINT64                             *Translation
 454   )
 455 {
 456   if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {
 457     *Translation = RootBridge->Mem.Translation;
 458   } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {
 459     *Translation = RootBridge->PMem.Translation;
 460   } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {
 461     *Translation = RootBridge->MemAbove4G.Translation;
 462   } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {
 463     *Translation = RootBridge->PMemAbove4G.Translation;
 464   } else {
 465     return EFI_INVALID_PARAMETER;
 466   }
 467
 468   return EFI_SUCCESS;
 469 }
 470
 471 /**
 472   Return the result of (Multiplicand * Multiplier / Divisor).
 473
 474   @param Multiplicand A 64-bit unsigned value.
 475   @param Multiplier   A 64-bit unsigned value.
 476   @param Divisor      A 32-bit unsigned value.
 477   @param Remainder    A pointer to a 32-bit unsigned value. This parameter is
 478                       optional and may be NULL.
 479
 480   @return Multiplicand * Multiplier / Divisor.
 481 **/
 482 UINT64
 483 MultThenDivU64x64x32 (
 484   IN      UINT64                    Multiplicand,
 485   IN      UINT64                    Multiplier,
 486   IN      UINT32                    Divisor,
 487   OUT     UINT32                    *Remainder  OPTIONAL
 488   )
 489 {
 490   UINT64                            Uint64;
 491   UINT32                            LocalRemainder;
 492   UINT32                            Uint32;
 493   if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {
 494     //
 495     // Make sure Multiplicand is the bigger one.
 496     //
 497     if (Multiplicand < Multiplier) {
 498       Uint64       = Multiplicand;
 499       Multiplicand = Multiplier;
 500       Multiplier   = Uint64;
 501     }
 502     //
 503     // Because Multiplicand * Multiplier overflows,
 504     //   Multiplicand * Multiplier / Divisor
 505     // = (2 * Multiplicand' + 1) * Multiplier / Divisor
 506     // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
 507     //
 508     Uint64 = MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multiplier, Divisor, &LocalRemainder);
 509     Uint64 = LShiftU64 (Uint64, 1);
 510     Uint32 = 0;
 511     if ((Multiplicand & 0x1) == 1) {
 512       Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);
 513     }
 514     return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);
 515   } else {
 516     return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);
 517   }
 518 }
 519
 520 /**
 521   Return the elapsed tick count from CurrentTick.
 522
 523   @param  CurrentTick  On input, the previous tick count.
 524                        On output, the current tick count.
 525   @param  StartTick    The value the performance counter starts with when it
 526                        rolls over.
 527   @param  EndTick      The value that the performance counter ends with before
 528                        it rolls over.
 529
 530   @return  The elapsed tick count from CurrentTick.
 531 **/
 532 UINT64
 533 GetElapsedTick (
 534   UINT64  *CurrentTick,
 535   UINT64  StartTick,
 536   UINT64  EndTick
 537   )
 538 {
 539   UINT64  PreviousTick;
 540
 541   PreviousTick = *CurrentTick;
 542   *CurrentTick = GetPerformanceCounter();
 543   if (StartTick < EndTick) {
 544     return *CurrentTick - PreviousTick;
 545   } else {
 546     return PreviousTick - *CurrentTick;
 547   }
 548 }
 549
 550 /**
 551   Polls an address in memory mapped I/O space until an exit condition is met,
 552   or a timeout occurs.
 553
 554   This function provides a standard way to poll a PCI memory location. A PCI
 555   memory read operation is performed at the PCI memory address specified by
 556   Address for the width specified by Width. The result of this PCI memory read
 557   operation is stored in Result. This PCI memory read operation is repeated
 558   until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
 559   is equal to Value.
 560
 561   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 562   @param[in]   Width     Signifies the width of the memory operations.
 563   @param[in]   Address   The base address of the memory operations. The caller
 564                          is responsible for aligning Address if required.
 565   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width
 566                          in Mask are ignored. The bits in the bytes below Width
 567                          which are zero in Mask are ignored when polling the
 568                          memory address.
 569   @param[in]   Value     The comparison value used for the polling exit
 570                          criteria.
 571   @param[in]   Delay     The number of 100 ns units to poll. Note that timer
 572                          available may be of poorer granularity.
 573   @param[out]  Result    Pointer to the last value read from the memory
 574                          location.
 575
 576   @retval EFI_SUCCESS            The last data returned from the access matched
 577                                  the poll exit criteria.
 578   @retval EFI_INVALID_PARAMETER  Width is invalid.
 579   @retval EFI_INVALID_PARAMETER  Result is NULL.
 580   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 581   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 582                                  lack of resources.
 583 **/
 584 EFI_STATUS
 585 EFIAPI
 586 RootBridgeIoPollMem (
 587   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 588   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 589   IN  UINT64                                 Address,
 590   IN  UINT64                                 Mask,
 591   IN  UINT64                                 Value,
 592   IN  UINT64                                 Delay,
 593   OUT UINT64                                 *Result
 594   )
 595 {
 596   EFI_STATUS  Status;
 597   UINT64      NumberOfTicks;
 598   UINT32      Remainder;
 599   UINT64      StartTick;
 600   UINT64      EndTick;
 601   UINT64      CurrentTick;
 602   UINT64      ElapsedTick;
 603   UINT64      Frequency;
 604
 605   if (Result == NULL) {
 606     return EFI_INVALID_PARAMETER;
 607   }
 608
 609   if ((UINT32)Width > EfiPciWidthUint64) {
 610     return EFI_INVALID_PARAMETER;
 611   }
 612
 613   //
 614   // No matter what, always do a single poll.
 615   //
 616   Status = This->Mem.Read (This, Width, Address, 1, Result);
 617   if (EFI_ERROR (Status)) {
 618     return Status;
 619   }
 620
 621   if ((*Result & Mask) == Value) {
 622     return EFI_SUCCESS;
 623   }
 624
 625   if (Delay == 0) {
 626     return EFI_SUCCESS;
 627
 628   } else {
 629     //
 630     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 631     //
 632     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 633     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
 634     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
 635       NumberOfTicks++;
 636     }
 637     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
 638         ; ElapsedTick <= NumberOfTicks
 639         ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 640         ) {
 641       Status = This->Mem.Read (This, Width, Address, 1, Result);
 642       if (EFI_ERROR (Status)) {
 643         return Status;
 644       }
 645
 646       if ((*Result & Mask) == Value) {
 647         return EFI_SUCCESS;
 648       }
 649     }
 650   }
 651   return EFI_TIMEOUT;
 652 }
 653
 654 /**
 655   Reads from the I/O space of a PCI Root Bridge. Returns when either the
 656   polling exit criteria is satisfied or after a defined duration.
 657
 658   This function provides a standard way to poll a PCI I/O location. A PCI I/O
 659   read operation is performed at the PCI I/O address specified by Address for
 660   the width specified by Width.
 661   The result of this PCI I/O read operation is stored in Result. This PCI I/O
 662   read operation is repeated until either a timeout of Delay 100 ns units has
 663   expired, or (Result & Mask) is equal to Value.
 664
 665   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 666   @param[in] Width     Signifies the width of the I/O operations.
 667   @param[in] Address   The base address of the I/O operations. The caller is
 668                        responsible for aligning Address if required.
 669   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in
 670                        Mask are ignored. The bits in the bytes below Width
 671                        which are zero in Mask are ignored when polling the I/O
 672                        address.
 673   @param[in] Value     The comparison value used for the polling exit criteria.
 674   @param[in] Delay     The number of 100 ns units to poll. Note that timer
 675                        available may be of poorer granularity.
 676   @param[out] Result   Pointer to the last value read from the memory location.
 677
 678   @retval EFI_SUCCESS            The last data returned from the access matched
 679                                  the poll exit criteria.
 680   @retval EFI_INVALID_PARAMETER  Width is invalid.
 681   @retval EFI_INVALID_PARAMETER  Result is NULL.
 682   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 683   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 684                                  lack of resources.
 685 **/
 686 EFI_STATUS
 687 EFIAPI
 688 RootBridgeIoPollIo (
 689   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 690   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 691   IN  UINT64                                 Address,
 692   IN  UINT64                                 Mask,
 693   IN  UINT64                                 Value,
 694   IN  UINT64                                 Delay,
 695   OUT UINT64                                 *Result
 696   )
 697 {
 698   EFI_STATUS  Status;
 699   UINT64      NumberOfTicks;
 700   UINT32      Remainder;
 701   UINT64      StartTick;
 702   UINT64      EndTick;
 703   UINT64      CurrentTick;
 704   UINT64      ElapsedTick;
 705   UINT64      Frequency;
 706
 707   //
 708   // No matter what, always do a single poll.
 709   //
 710
 711   if (Result == NULL) {
 712     return EFI_INVALID_PARAMETER;
 713   }
 714
 715   if ((UINT32)Width > EfiPciWidthUint64) {
 716     return EFI_INVALID_PARAMETER;
 717   }
 718
 719   Status = This->Io.Read (This, Width, Address, 1, Result);
 720   if (EFI_ERROR (Status)) {
 721     return Status;
 722   }
 723   if ((*Result & Mask) == Value) {
 724     return EFI_SUCCESS;
 725   }
 726
 727   if (Delay == 0) {
 728     return EFI_SUCCESS;
 729
 730   } else {
 731     //
 732     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 733     //
 734     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 735     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
 736     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
 737       NumberOfTicks++;
 738     }
 739     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
 740         ; ElapsedTick <= NumberOfTicks
 741         ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 742         ) {
 743       Status = This->Io.Read (This, Width, Address, 1, Result);
 744       if (EFI_ERROR (Status)) {
 745         return Status;
 746       }
 747
 748       if ((*Result & Mask) == Value) {
 749         return EFI_SUCCESS;
 750       }
 751     }
 752   }
 753   return EFI_TIMEOUT;
 754 }
 755
 756 /**
 757   Enables a PCI driver to access PCI controller registers in the PCI root
 758   bridge memory space.
 759
 760   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 761   controller registers in the PCI root bridge memory space.
 762   The memory operations are carried out exactly as requested. The caller is
 763   responsible for satisfying any alignment and memory width restrictions that a
 764   PCI Root Bridge on a platform might require.
 765
 766   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 767   @param[in]   Width     Signifies the width of the memory operation.
 768   @param[in]   Address   The base address of the memory operation. The caller
 769                          is responsible for aligning the Address if required.
 770   @param[in]   Count     The number of memory operations to perform. Bytes
 771                          moved is Width size * Count, starting at Address.
 772   @param[out]  Buffer    For read operations, the destination buffer to store
 773                          the results. For write operations, the source buffer
 774                          to write data from.
 775
 776   @retval EFI_SUCCESS            The data was read from or written to the PCI
 777                                  root bridge.
 778   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 779   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 780   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 781                                  lack of resources.
 782 **/
 783 EFI_STATUS
 784 EFIAPI
 785 RootBridgeIoMemRead (
 786   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 787   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 788   IN     UINT64                                 Address,
 789   IN     UINTN                                  Count,
 790   OUT    VOID                                   *Buffer
 791   )
 792 {
 793   EFI_STATUS                             Status;
 794   PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
 795   UINT64                                 Translation;
 796
 797   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 798                                        Count, Buffer);
 799   if (EFI_ERROR (Status)) {
 800     return Status;
 801   }
 802
 803   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 804   Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 805   if (EFI_ERROR (Status)) {
 806     return Status;
 807   }
 808
 809   // Address passed to CpuIo->Mem.Read needs to be a host address instead of
 810   // device address.
 811   return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 812       TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 813 }
 814
 815 /**
 816   Enables a PCI driver to access PCI controller registers in the PCI root
 817   bridge memory space.
 818
 819   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 820   controller registers in the PCI root bridge memory space.
 821   The memory operations are carried out exactly as requested. The caller is
 822   responsible for satisfying any alignment and memory width restrictions that a
 823   PCI Root Bridge on a platform might require.
 824
 825   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 826   @param[in]   Width     Signifies the width of the memory operation.
 827   @param[in]   Address   The base address of the memory operation. The caller
 828                          is responsible for aligning the Address if required.
 829   @param[in]   Count     The number of memory operations to perform. Bytes
 830                          moved is Width size * Count, starting at Address.
 831   @param[in]   Buffer    For read operations, the destination buffer to store
 832                          the results. For write operations, the source buffer
 833                          to write data from.
 834
 835   @retval EFI_SUCCESS            The data was read from or written to the PCI
 836                                  root bridge.
 837   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 838   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 839   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 840                                  lack of resources.
 841 **/
 842 EFI_STATUS
 843 EFIAPI
 844 RootBridgeIoMemWrite (
 845   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 846   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 847   IN     UINT64                                 Address,
 848   IN     UINTN                                  Count,
 849   IN     VOID                                   *Buffer
 850   )
 851 {
 852   EFI_STATUS                             Status;
 853   PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
 854   UINT64                                 Translation;
 855
 856   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 857                                        Count, Buffer);
 858   if (EFI_ERROR (Status)) {
 859     return Status;
 860   }
 861
 862   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 863   Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 864   if (EFI_ERROR (Status)) {
 865     return Status;
 866   }
 867
 868   // Address passed to CpuIo->Mem.Write needs to be a host address instead of
 869   // device address.
 870   return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 871       TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 872 }
 873
 874 /**
 875   Enables a PCI driver to access PCI controller registers in the PCI root
 876   bridge I/O space.
 877
 878   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 879   @param[in]   Width       Signifies the width of the memory operations.
 880   @param[in]   Address     The base address of the I/O operation. The caller is
 881                            responsible for aligning the Address if required.
 882   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 883                            is Width size * Count, starting at Address.
 884   @param[out]  Buffer      For read operations, the destination buffer to store
 885                            the results. For write operations, the source buffer
 886                            to write data from.
 887
 888   @retval EFI_SUCCESS              The data was read from or written to the PCI
 889                                    root bridge.
 890   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 891   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 892   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 893                                    lack of resources.
 894 **/
 895 EFI_STATUS
 896 EFIAPI
 897 RootBridgeIoIoRead (
 898   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 899   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 900   IN     UINT64                                 Address,
 901   IN     UINTN                                  Count,
 902   OUT    VOID                                   *Buffer
 903   )
 904 {
 905   EFI_STATUS                                    Status;
 906   PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
 907
 908   Status = RootBridgeIoCheckParameter (
 909              This, IoOperation, Width,
 910              Address, Count, Buffer
 911              );
 912   if (EFI_ERROR (Status)) {
 913     return Status;
 914   }
 915
 916   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 917
 918   // Address passed to CpuIo->Io.Read needs to be a host address instead of
 919   // device address.
 920   return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 921       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 922 }
 923
 924 /**
 925   Enables a PCI driver to access PCI controller registers in the PCI root
 926   bridge I/O space.
 927
 928   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 929   @param[in]   Width       Signifies the width of the memory operations.
 930   @param[in]   Address     The base address of the I/O operation. The caller is
 931                            responsible for aligning the Address if required.
 932   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 933                            is Width size * Count, starting at Address.
 934   @param[in]   Buffer      For read operations, the destination buffer to store
 935                            the results. For write operations, the source buffer
 936                            to write data from.
 937
 938   @retval EFI_SUCCESS              The data was read from or written to the PCI
 939                                    root bridge.
 940   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 941   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 942   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 943                                    lack of resources.
 944 **/
 945 EFI_STATUS
 946 EFIAPI
 947 RootBridgeIoIoWrite (
 948   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,
 949   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,
 950   IN       UINT64                                  Address,
 951   IN       UINTN                                   Count,
 952   IN       VOID                                    *Buffer
 953   )
 954 {
 955   EFI_STATUS                                    Status;
 956   PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
 957
 958   Status = RootBridgeIoCheckParameter (
 959              This, IoOperation, Width,
 960              Address, Count, Buffer
 961              );
 962   if (EFI_ERROR (Status)) {
 963     return Status;
 964   }
 965
 966   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 967
 968   // Address passed to CpuIo->Io.Write needs to be a host address instead of
 969   // device address.
 970   return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 971       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 972 }
 973
 974 /**
 975   Enables a PCI driver to copy one region of PCI root bridge memory space to
 976   another region of PCI root bridge memory space.
 977
 978   The CopyMem() function enables a PCI driver to copy one region of PCI root
 979   bridge memory space to another region of PCI root bridge memory space. This
 980   is especially useful for video scroll operation on a memory mapped video
 981   buffer.
 982   The memory operations are carried out exactly as requested. The caller is
 983   responsible for satisfying any alignment and memory width restrictions that a
 984   PCI root bridge on a platform might require.
 985
 986   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
 987                          instance.
 988   @param[in] Width       Signifies the width of the memory operations.
 989   @param[in] DestAddress The destination address of the memory operation. The
 990                          caller is responsible for aligning the DestAddress if
 991                          required.
 992   @param[in] SrcAddress  The source address of the memory operation. The caller
 993                          is responsible for aligning the SrcAddress if
 994                          required.
 995   @param[in] Count       The number of memory operations to perform. Bytes
 996                          moved is Width size * Count, starting at DestAddress
 997                          and SrcAddress.
 998
 999   @retval  EFI_SUCCESS             The data was copied from one memory region
1000                                    to another memory region.
1001   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
1002   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a
1003                                    lack of resources.
1004 **/
1005 EFI_STATUS
1006 EFIAPI
1007 RootBridgeIoCopyMem (
1008   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,
1009   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,
1010   IN UINT64                                       DestAddress,
1011   IN UINT64                                       SrcAddress,
1012   IN UINTN                                        Count
1013   )
1014 {
1015   EFI_STATUS  Status;
1016   BOOLEAN     Forward;
1017   UINTN       Stride;
1018   UINTN       Index;
1019   UINT64      Result;
1020
1021   if ((UINT32) Width > EfiPciWidthUint64) {
1022     return EFI_INVALID_PARAMETER;
1023   }
1024
1025   if (DestAddress == SrcAddress) {
1026     return EFI_SUCCESS;
1027   }
1028
1029   Stride = (UINTN) (1 << Width);
1030
1031   Forward = TRUE;
1032   if ((DestAddress > SrcAddress) &&
1033       (DestAddress < (SrcAddress + Count * Stride))) {
1034     Forward = FALSE;
1035     SrcAddress = SrcAddress + (Count - 1) * Stride;
1036     DestAddress = DestAddress + (Count - 1) * Stride;
1037   }
1038
1039   for (Index = 0; Index < Count; Index++) {
1040     Status = RootBridgeIoMemRead (
1041                This,
1042                Width,
1043                SrcAddress,
1044                1,
1045                &Result
1046                );
1047     if (EFI_ERROR (Status)) {
1048       return Status;
1049     }
1050     Status = RootBridgeIoMemWrite (
1051                This,
1052                Width,
1053                DestAddress,
1054                1,
1055                &Result
1056                );
1057     if (EFI_ERROR (Status)) {
1058       return Status;
1059     }
1060     if (Forward) {
1061       SrcAddress += Stride;
1062       DestAddress += Stride;
1063     } else {
1064       SrcAddress -= Stride;
1065       DestAddress -= Stride;
1066     }
1067   }
1068   return EFI_SUCCESS;
1069 }
1070
1071
1072 /**
1073   PCI configuration space access.
1074
1075   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1076   @param Read     TRUE indicating it's a read operation.
1077   @param Width    Signifies the width of the memory operation.
1078   @param Address  The address within the PCI configuration space
1079                   for the PCI controller.
1080   @param Count    The number of PCI configuration operations
1081                   to perform.
1082   @param Buffer   The destination buffer to store the results.
1083
1084   @retval EFI_SUCCESS            The data was read/written from/to the PCI root bridge.
1085   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1086 **/
1087 EFI_STATUS
1088 EFIAPI
1089 RootBridgeIoPciAccess (
1090   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1091   IN     BOOLEAN                               Read,
1092   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1093   IN     UINT64                                Address,
1094   IN     UINTN                                 Count,
1095   IN OUT VOID                                  *Buffer
1096   )
1097 {
1098   EFI_STATUS                                   Status;
1099   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
1100   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;
1101   UINT8                                        *Uint8Buffer;
1102   UINT8                                        InStride;
1103   UINT8                                        OutStride;
1104   UINTN                                        Size;
1105
1106   Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
1107   if (EFI_ERROR (Status)) {
1108     return Status;
1109   }
1110
1111   //
1112   // Read Pci configuration space
1113   //
1114   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1115   CopyMem (&PciAddress, &Address, sizeof (PciAddress));
1116
1117   if (PciAddress.ExtendedRegister == 0) {
1118     PciAddress.ExtendedRegister = PciAddress.Register;
1119   }
1120
1121   Address = PCI_SEGMENT_LIB_ADDRESS (
1122               RootBridge->RootBridgeIo.SegmentNumber,
1123               PciAddress.Bus,
1124               PciAddress.Device,
1125               PciAddress.Function,
1126               PciAddress.ExtendedRegister
1127               );
1128
1129   //
1130   // Select loop based on the width of the transfer
1131   //
1132   InStride  = mInStride[Width];
1133   OutStride = mOutStride[Width];
1134   Size      = (UINTN) (1 << (Width & 0x03));
1135   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
1136     if (Read) {
1137       PciSegmentReadBuffer (Address, Size, Uint8Buffer);
1138     } else {
1139       PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
1140     }
1141   }
1142   return EFI_SUCCESS;
1143 }
1144
1145 /**
1146   Allows read from PCI configuration space.
1147
1148   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1149   @param Width    Signifies the width of the memory operation.
1150   @param Address  The address within the PCI configuration space
1151                   for the PCI controller.
1152   @param Count    The number of PCI configuration operations
1153                   to perform.
1154   @param Buffer   The destination buffer to store the results.
1155
1156   @retval EFI_SUCCESS           The data was read from the PCI root bridge.
1157   @retval EFI_INVALID_PARAMETER Invalid parameters found.
1158 **/
1159 EFI_STATUS
1160 EFIAPI
1161 RootBridgeIoPciRead (
1162   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1163   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1164   IN     UINT64                                Address,
1165   IN     UINTN                                 Count,
1166   IN OUT VOID                                  *Buffer
1167   )
1168 {
1169   return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
1170 }
1171
1172 /**
1173   Allows write to PCI configuration space.
1174
1175   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1176   @param Width    Signifies the width of the memory operation.
1177   @param Address  The address within the PCI configuration space
1178                   for the PCI controller.
1179   @param Count    The number of PCI configuration operations
1180                   to perform.
1181   @param Buffer   The source buffer to get the results.
1182
1183   @retval EFI_SUCCESS            The data was written to the PCI root bridge.
1184   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1185 **/
1186 EFI_STATUS
1187 EFIAPI
1188 RootBridgeIoPciWrite (
1189   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1190   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1191   IN     UINT64                                Address,
1192   IN     UINTN                                 Count,
1193   IN OUT VOID                                  *Buffer
1194   )
1195 {
1196   return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
1197 }
1198
1199 /**
1200   Provides the PCI controller-specific address needed to access
1201   system memory for DMA.
1202
1203   @param This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1204   @param Operation      Indicate if the bus master is going to read or write
1205                         to system memory.
1206   @param HostAddress    The system memory address to map on the PCI controller.
1207   @param NumberOfBytes  On input the number of bytes to map.
1208                         On output the number of bytes that were mapped.
1209   @param DeviceAddress  The resulting map address for the bus master PCI
1210                         controller to use to access the system memory's HostAddress.
1211   @param Mapping        The value to pass to Unmap() when the bus master DMA
1212                         operation is complete.
1213
1214   @retval EFI_SUCCESS            Success.
1215   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1216   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
1217   @retval EFI_DEVICE_ERROR       The System hardware could not map the requested address.
1218   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to lack of resources.
1219 **/
1220 EFI_STATUS
1221 EFIAPI
1222 RootBridgeIoMap (
1223   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
1224   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
1225   IN     VOID                                       *HostAddress,
1226   IN OUT UINTN                                      *NumberOfBytes,
1227   OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
1228   OUT    VOID                                       **Mapping
1229   )
1230 {
1231   EFI_STATUS                                        Status;
1232   PCI_ROOT_BRIDGE_INSTANCE                          *RootBridge;
1233   EFI_PHYSICAL_ADDRESS                              PhysicalAddress;
1234   MAP_INFO                                          *MapInfo;
1235
1236   if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
1237       Mapping == NULL) {
1238     return EFI_INVALID_PARAMETER;
1239   }
1240
1241   //
1242   // Make sure that Operation is valid
1243   //
1244   if ((UINT32) Operation >= EfiPciOperationMaximum) {
1245     return EFI_INVALID_PARAMETER;
1246   }
1247
1248   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1249
1250   if (mIoMmuProtocol != NULL) {
1251     if (!RootBridge->DmaAbove4G) {
1252       //
1253       // Clear 64bit support
1254       //
1255       if (Operation > EfiPciOperationBusMasterCommonBuffer) {
1256         Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);
1257       }
1258     }
1259     Status = mIoMmuProtocol->Map (
1260                                mIoMmuProtocol,
1261                                (EDKII_IOMMU_OPERATION) Operation,
1262                                HostAddress,
1263                                NumberOfBytes,
1264                                DeviceAddress,
1265                                Mapping
1266                                );
1267     return Status;
1268   }
1269
1270   PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
1271   if ((!RootBridge->DmaAbove4G ||
1272        (Operation != EfiPciOperationBusMasterRead64 &&
1273         Operation != EfiPciOperationBusMasterWrite64 &&
1274         Operation != EfiPciOperationBusMasterCommonBuffer64)) &&
1275       ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {
1276
1277     //
1278     // If the root bridge or the device cannot handle performing DMA above
1279     // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1280     // map the DMA transfer to a buffer below 4GB.
1281     //
1282
1283     if (Operation == EfiPciOperationBusMasterCommonBuffer ||
1284         Operation == EfiPciOperationBusMasterCommonBuffer64) {
1285       //
1286       // Common Buffer operations can not be remapped.  If the common buffer
1287       // if above 4GB, then it is not possible to generate a mapping, so return
1288       // an error.
1289       //
1290       return EFI_UNSUPPORTED;
1291     }
1292
1293     //
1294     // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1295     // called later.
1296     //
1297     MapInfo = AllocatePool (sizeof (MAP_INFO));
1298     if (MapInfo == NULL) {
1299       *NumberOfBytes = 0;
1300       return EFI_OUT_OF_RESOURCES;
1301     }
1302
1303     //
1304     // Initialize the MAP_INFO structure
1305     //
1306     MapInfo->Signature         = MAP_INFO_SIGNATURE;
1307     MapInfo->Operation         = Operation;
1308     MapInfo->NumberOfBytes     = *NumberOfBytes;
1309     MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);
1310     MapInfo->HostAddress       = PhysicalAddress;
1311     MapInfo->MappedHostAddress = SIZE_4GB - 1;
1312
1313     //
1314     // Allocate a buffer below 4GB to map the transfer to.
1315     //
1316     Status = gBS->AllocatePages (
1317                     AllocateMaxAddress,
1318                     EfiBootServicesData,
1319                     MapInfo->NumberOfPages,
1320                     &MapInfo->MappedHostAddress
1321                     );
1322     if (EFI_ERROR (Status)) {
1323       FreePool (MapInfo);
1324       *NumberOfBytes = 0;
1325       return Status;
1326     }
1327
1328     //
1329     // If this is a read operation from the Bus Master's point of view,
1330     // then copy the contents of the real buffer into the mapped buffer
1331     // so the Bus Master can read the contents of the real buffer.
1332     //
1333     if (Operation == EfiPciOperationBusMasterRead ||
1334         Operation == EfiPciOperationBusMasterRead64) {
1335       CopyMem (
1336         (VOID *) (UINTN) MapInfo->MappedHostAddress,
1337         (VOID *) (UINTN) MapInfo->HostAddress,
1338         MapInfo->NumberOfBytes
1339         );
1340     }
1341
1342     InsertTailList (&RootBridge->Maps, &MapInfo->Link);
1343
1344     //
1345     // The DeviceAddress is the address of the maped buffer below 4GB
1346     //
1347     *DeviceAddress = MapInfo->MappedHostAddress;
1348     //
1349     // Return a pointer to the MAP_INFO structure in Mapping
1350     //
1351     *Mapping       = MapInfo;
1352   } else {
1353     //
1354     // If the root bridge CAN handle performing DMA above 4GB or
1355     // the transfer is below 4GB, so the DeviceAddress is simply the
1356     // HostAddress
1357     //
1358     *DeviceAddress = PhysicalAddress;
1359     *Mapping       = NO_MAPPING;
1360   }
1361
1362   return EFI_SUCCESS;
1363 }
1364
1365 /**
1366   Completes the Map() operation and releases any corresponding resources.
1367
1368   The Unmap() function completes the Map() operation and releases any
1369   corresponding resources.
1370   If the operation was an EfiPciOperationBusMasterWrite or
1371   EfiPciOperationBusMasterWrite64, the data is committed to the target system
1372   memory.
1373   Any resources used for the mapping are freed.
1374
1375   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1376   @param[in] Mapping   The mapping value returned from Map().
1377
1378   @retval EFI_SUCCESS            The range was unmapped.
1379   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
1380   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
1381 **/
1382 EFI_STATUS
1383 EFIAPI
1384 RootBridgeIoUnmap (
1385   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1386   IN VOID                             *Mapping
1387   )
1388 {
1389   MAP_INFO                 *MapInfo;
1390   LIST_ENTRY               *Link;
1391   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1392   EFI_STATUS                Status;
1393
1394   if (mIoMmuProtocol != NULL) {
1395     Status = mIoMmuProtocol->Unmap (
1396                                mIoMmuProtocol,
1397                                Mapping
1398                                );
1399     return Status;
1400   }
1401
1402   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1403
1404   //
1405   // See if the Map() operation associated with this Unmap() required a mapping
1406   // buffer. If a mapping buffer was not required, then this function simply
1407   // returns EFI_SUCCESS.
1408   //
1409   if (Mapping == NO_MAPPING) {
1410     return EFI_SUCCESS;
1411   }
1412
1413   MapInfo = NO_MAPPING;
1414   for (Link = GetFirstNode (&RootBridge->Maps)
1415        ; !IsNull (&RootBridge->Maps, Link)
1416        ; Link = GetNextNode (&RootBridge->Maps, Link)
1417        ) {
1418     MapInfo = MAP_INFO_FROM_LINK (Link);
1419     if (MapInfo == Mapping) {
1420       break;
1421     }
1422   }
1423   //
1424   // Mapping is not a valid value returned by Map()
1425   //
1426   if (MapInfo != Mapping) {
1427     return EFI_INVALID_PARAMETER;
1428   }
1429   RemoveEntryList (&MapInfo->Link);
1430
1431   //
1432   // If this is a write operation from the Bus Master's point of view,
1433   // then copy the contents of the mapped buffer into the real buffer
1434   // so the processor can read the contents of the real buffer.
1435   //
1436   if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
1437       MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
1438     CopyMem (
1439       (VOID *) (UINTN) MapInfo->HostAddress,
1440       (VOID *) (UINTN) MapInfo->MappedHostAddress,
1441       MapInfo->NumberOfBytes
1442       );
1443   }
1444
1445   //
1446   // Free the mapped buffer and the MAP_INFO structure.
1447   //
1448   gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
1449   FreePool (Mapping);
1450   return EFI_SUCCESS;
1451 }
1452
1453 /**
1454   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1455   or EfiPciOperationBusMasterCommonBuffer64 mapping.
1456
1457   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1458   @param Type        This parameter is not used and must be ignored.
1459   @param MemoryType  The type of memory to allocate, EfiBootServicesData or
1460                      EfiRuntimeServicesData.
1461   @param Pages       The number of pages to allocate.
1462   @param HostAddress A pointer to store the base system memory address of the
1463                      allocated range.
1464   @param Attributes  The requested bit mask of attributes for the allocated
1465                      range. Only the attributes
1466                      EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1467                      EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1468                      EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1469                      function.
1470
1471   @retval EFI_SUCCESS            The requested memory pages were allocated.
1472   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
1473   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
1474   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal
1475                                  attribute bits are MEMORY_WRITE_COMBINE,
1476                                  MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1477   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
1478 **/
1479 EFI_STATUS
1480 EFIAPI
1481 RootBridgeIoAllocateBuffer (
1482   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1483   IN  EFI_ALLOCATE_TYPE                Type,
1484   IN  EFI_MEMORY_TYPE                  MemoryType,
1485   IN  UINTN                            Pages,
1486   OUT VOID                             **HostAddress,
1487   IN  UINT64                           Attributes
1488   )
1489 {
1490   EFI_STATUS                Status;
1491   EFI_PHYSICAL_ADDRESS      PhysicalAddress;
1492   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1493   EFI_ALLOCATE_TYPE         AllocateType;
1494
1495   //
1496   // Validate Attributes
1497   //
1498   if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
1499     return EFI_UNSUPPORTED;
1500   }
1501
1502   //
1503   // Check for invalid inputs
1504   //
1505   if (HostAddress == NULL) {
1506     return EFI_INVALID_PARAMETER;
1507   }
1508
1509   //
1510   // The only valid memory types are EfiBootServicesData and
1511   // EfiRuntimeServicesData
1512   //
1513   if (MemoryType != EfiBootServicesData &&
1514       MemoryType != EfiRuntimeServicesData) {
1515     return EFI_INVALID_PARAMETER;
1516   }
1517
1518   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1519
1520   if (mIoMmuProtocol != NULL) {
1521     if (!RootBridge->DmaAbove4G) {
1522       //
1523       // Clear DUAL_ADDRESS_CYCLE
1524       //
1525       Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
1526     }
1527     Status = mIoMmuProtocol->AllocateBuffer (
1528                                mIoMmuProtocol,
1529                                Type,
1530                                MemoryType,
1531                                Pages,
1532                                HostAddress,
1533                                Attributes
1534                                );
1535     return Status;
1536   }
1537
1538   AllocateType = AllocateAnyPages;
1539   if (!RootBridge->DmaAbove4G ||
1540       (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
1541     //
1542     // Limit allocations to memory below 4GB
1543     //
1544     AllocateType    = AllocateMaxAddress;
1545     PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);
1546   }
1547   Status = gBS->AllocatePages (
1548                   AllocateType,
1549                   MemoryType,
1550                   Pages,
1551                   &PhysicalAddress
1552                   );
1553   if (!EFI_ERROR (Status)) {
1554     *HostAddress = (VOID *) (UINTN) PhysicalAddress;
1555   }
1556
1557   return Status;
1558 }
1559
1560 /**
1561   Frees memory that was allocated with AllocateBuffer().
1562
1563   The FreeBuffer() function frees memory that was allocated with
1564   AllocateBuffer().
1565
1566   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1567   @param Pages       The number of pages to free.
1568   @param HostAddress The base system memory address of the allocated range.
1569
1570   @retval EFI_SUCCESS            The requested memory pages were freed.
1571   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and
1572                                  Pages was not allocated with AllocateBuffer().
1573 **/
1574 EFI_STATUS
1575 EFIAPI
1576 RootBridgeIoFreeBuffer (
1577   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1578   IN  UINTN                            Pages,
1579   OUT VOID                             *HostAddress
1580   )
1581 {
1582   EFI_STATUS                Status;
1583
1584   if (mIoMmuProtocol != NULL) {
1585     Status = mIoMmuProtocol->FreeBuffer (
1586                                mIoMmuProtocol,
1587                                Pages,
1588                                HostAddress
1589                                );
1590     return Status;
1591   }
1592
1593   return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
1594 }
1595
1596 /**
1597   Flushes all PCI posted write transactions from a PCI host bridge to system
1598   memory.
1599
1600   The Flush() function flushes any PCI posted write transactions from a PCI
1601   host bridge to system memory. Posted write transactions are generated by PCI
1602   bus masters when they perform write transactions to target addresses in
1603   system memory.
1604   This function does not flush posted write transactions from any PCI bridges.
1605   A PCI controller specific action must be taken to guarantee that the posted
1606   write transactions have been flushed from the PCI controller and from all the
1607   PCI bridges into the PCI host bridge. This is typically done with a PCI read
1608   transaction from the PCI controller prior to calling Flush().
1609
1610   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1611
1612   @retval EFI_SUCCESS        The PCI posted write transactions were flushed
1613                              from the PCI host bridge to system memory.
1614   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed
1615                              from the PCI host bridge due to a hardware error.
1616 **/
1617 EFI_STATUS
1618 EFIAPI
1619 RootBridgeIoFlush (
1620   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This
1621   )
1622 {
1623   return EFI_SUCCESS;
1624 }
1625
1626 /**
1627   Gets the attributes that a PCI root bridge supports setting with
1628   SetAttributes(), and the attributes that a PCI root bridge is currently
1629   using.
1630
1631   The GetAttributes() function returns the mask of attributes that this PCI
1632   root bridge supports and the mask of attributes that the PCI root bridge is
1633   currently using.
1634
1635   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1636   @param Supported   A pointer to the mask of attributes that this PCI root
1637                      bridge supports setting with SetAttributes().
1638   @param Attributes  A pointer to the mask of attributes that this PCI root
1639                      bridge is currently using.
1640
1641   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes
1642                                  that the PCI root bridge supports is returned
1643                                  in Supports. If Attributes is not NULL, then
1644                                  the attributes that the PCI root bridge is
1645                                  currently using is returned in Attributes.
1646   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1647 **/
1648 EFI_STATUS
1649 EFIAPI
1650 RootBridgeIoGetAttributes (
1651   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1652   OUT UINT64                           *Supported,
1653   OUT UINT64                           *Attributes
1654   )
1655 {
1656   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1657
1658   if (Attributes == NULL && Supported == NULL) {
1659     return EFI_INVALID_PARAMETER;
1660   }
1661
1662   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1663   //
1664   // Set the return value for Supported and Attributes
1665   //
1666   if (Supported != NULL) {
1667     *Supported  = RootBridge->Supports;
1668   }
1669
1670   if (Attributes != NULL) {
1671     *Attributes = RootBridge->Attributes;
1672   }
1673
1674   return EFI_SUCCESS;
1675 }
1676
1677 /**
1678   Sets attributes for a resource range on a PCI root bridge.
1679
1680   The SetAttributes() function sets the attributes specified in Attributes for
1681   the PCI root bridge on the resource range specified by ResourceBase and
1682   ResourceLength. Since the granularity of setting these attributes may vary
1683   from resource type to resource type, and from platform to platform, the
1684   actual resource range and the one passed in by the caller may differ. As a
1685   result, this function may set the attributes specified by Attributes on a
1686   larger resource range than the caller requested. The actual range is returned
1687   in ResourceBase and ResourceLength. The caller is responsible for verifying
1688   that the actual range for which the attributes were set is acceptable.
1689
1690   @param This            A pointer to the
1691                          EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1692   @param Attributes      The mask of attributes to set. If the
1693                          attribute bit MEMORY_WRITE_COMBINE,
1694                          MEMORY_CACHED, or MEMORY_DISABLE is set,
1695                          then the resource range is specified by
1696                          ResourceBase and ResourceLength. If
1697                          MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1698                          MEMORY_DISABLE are not set, then
1699                          ResourceBase and ResourceLength are ignored,
1700                          and may be NULL.
1701   @param ResourceBase    A pointer to the base address of the
1702                          resource range to be modified by the
1703                          attributes specified by Attributes.
1704   @param ResourceLength  A pointer to the length of the resource
1705                                    range to be modified by the attributes
1706                                    specified by Attributes.
1707
1708   @retval  EFI_SUCCESS           The current configuration of this PCI root bridge
1709                                  was returned in Resources.
1710   @retval  EFI_UNSUPPORTED       The current configuration of this PCI root bridge
1711                                  could not be retrieved.
1712 **/
1713 EFI_STATUS
1714 EFIAPI
1715 RootBridgeIoSetAttributes (
1716   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1717   IN     UINT64                           Attributes,
1718   IN OUT UINT64                           *ResourceBase,
1719   IN OUT UINT64                           *ResourceLength
1720   )
1721 {
1722   PCI_ROOT_BRIDGE_INSTANCE            *RootBridge;
1723
1724   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1725
1726   if ((Attributes & (~RootBridge->Supports)) != 0) {
1727     return EFI_UNSUPPORTED;
1728   }
1729
1730   RootBridge->Attributes = Attributes;
1731   return EFI_SUCCESS;
1732 }
1733
1734 /**
1735   Retrieves the current resource settings of this PCI root bridge in the form
1736   of a set of ACPI resource descriptors.
1737
1738   There are only two resource descriptor types from the ACPI Specification that
1739   may be used to describe the current resources allocated to a PCI root bridge.
1740   These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1741   Address Space Descriptor can describe memory, I/O, and bus number ranges for
1742   dynamic or fixed resources. The configuration of a PCI root bridge is described
1743   with one or more QWORD Address Space Descriptors followed by an End Tag.
1744
1745   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1746   @param[out]  Resources   A pointer to the resource descriptors that
1747                            describe the current configuration of this PCI root
1748                            bridge. The storage for the resource
1749                            descriptors is allocated by this function. The
1750                            caller must treat the return buffer as read-only
1751                            data, and the buffer must not be freed by the
1752                            caller.
1753
1754   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge
1755                            was returned in Resources.
1756   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge
1757                            could not be retrieved.
1758 **/
1759 EFI_STATUS
1760 EFIAPI
1761 RootBridgeIoConfiguration (
1762   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,
1763   OUT VOID                                **Resources
1764   )
1765 {
1766   PCI_RESOURCE_TYPE                 Index;
1767   PCI_ROOT_BRIDGE_INSTANCE          *RootBridge;
1768   PCI_RES_NODE                      *ResAllocNode;
1769   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
1770   EFI_ACPI_END_TAG_DESCRIPTOR       *End;
1771
1772   //
1773   // Get this instance of the Root Bridge.
1774   //
1775   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1776   ZeroMem (
1777     RootBridge->ConfigBuffer,
1778     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1779     );
1780   Descriptor = RootBridge->ConfigBuffer;
1781   for (Index = TypeIo; Index < TypeMax; Index++) {
1782
1783     ResAllocNode = &RootBridge->ResAllocNode[Index];
1784
1785     if (ResAllocNode->Status != ResAllocated) {
1786       continue;
1787     }
1788
1789     Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1790     Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1791     // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1792     // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1793     // view address (host address).
1794     Descriptor->AddrRangeMin  = ResAllocNode->Base;
1795     Descriptor->AddrRangeMax  = ResAllocNode->Base + ResAllocNode->Length - 1;
1796     Descriptor->AddrLen       = ResAllocNode->Length;
1797     Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
1798       RootBridge,
1799       ResAllocNode->Type
1800       );
1801
1802     switch (ResAllocNode->Type) {
1803
1804     case TypeIo:
1805       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_IO;
1806       break;
1807
1808     case TypePMem32:
1809       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1810     case TypeMem32:
1811       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1812       Descriptor->AddrSpaceGranularity  = 32;
1813       break;
1814
1815     case TypePMem64:
1816       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1817     case TypeMem64:
1818       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1819       Descriptor->AddrSpaceGranularity  = 64;
1820       break;
1821
1822     case TypeBus:
1823       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_BUS;
1824       break;
1825
1826     default:
1827       break;
1828     }
1829
1830     Descriptor++;
1831   }
1832   //
1833   // Terminate the entries.
1834   //
1835   End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
1836   End->Desc     = ACPI_END_TAG_DESCRIPTOR;
1837   End->Checksum = 0x0;
1838
1839   *Resources = RootBridge->ConfigBuffer;
1840   return EFI_SUCCESS;
1841 }