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92870c98 | 1 | /** @file\r |
2 | \r | |
3 | This file contains the definition for XHCI host controller schedule routines.\r | |
4 | \r | |
d1102dba | 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
92870c98 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _EFI_XHCI_SCHED_H_\r | |
11 | #define _EFI_XHCI_SCHED_H_\r | |
12 | \r | |
13 | #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r | |
2363c692 | 14 | #define XHC_INIT_DEVICE_SLOT_RETRIES 1\r |
92870c98 | 15 | \r |
16 | //\r | |
17 | // Transfer types, used in URB to identify the transfer type\r | |
18 | //\r | |
19 | #define XHC_CTRL_TRANSFER 0x01\r | |
20 | #define XHC_BULK_TRANSFER 0x02\r | |
21 | #define XHC_INT_TRANSFER_SYNC 0x04\r | |
22 | #define XHC_INT_TRANSFER_ASYNC 0x08\r | |
23 | #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r | |
24 | \r | |
25 | //\r | |
26 | // 6.4.6 TRB Types\r | |
27 | //\r | |
28 | #define TRB_TYPE_NORMAL 1\r | |
29 | #define TRB_TYPE_SETUP_STAGE 2\r | |
30 | #define TRB_TYPE_DATA_STAGE 3\r | |
31 | #define TRB_TYPE_STATUS_STAGE 4\r | |
32 | #define TRB_TYPE_ISOCH 5\r | |
33 | #define TRB_TYPE_LINK 6\r | |
34 | #define TRB_TYPE_EVENT_DATA 7\r | |
35 | #define TRB_TYPE_NO_OP 8\r | |
36 | #define TRB_TYPE_EN_SLOT 9\r | |
37 | #define TRB_TYPE_DIS_SLOT 10\r | |
38 | #define TRB_TYPE_ADDRESS_DEV 11\r | |
39 | #define TRB_TYPE_CON_ENDPOINT 12\r | |
40 | #define TRB_TYPE_EVALU_CONTXT 13\r | |
41 | #define TRB_TYPE_RESET_ENDPOINT 14\r | |
42 | #define TRB_TYPE_STOP_ENDPOINT 15\r | |
43 | #define TRB_TYPE_SET_TR_DEQUE 16\r | |
44 | #define TRB_TYPE_RESET_DEV 17\r | |
45 | #define TRB_TYPE_GET_PORT_BANW 21\r | |
46 | #define TRB_TYPE_FORCE_HEADER 22\r | |
47 | #define TRB_TYPE_NO_OP_COMMAND 23\r | |
48 | #define TRB_TYPE_TRANS_EVENT 32\r | |
49 | #define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r | |
50 | #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r | |
51 | #define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r | |
52 | #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r | |
53 | #define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r | |
54 | \r | |
55 | //\r | |
56 | // Endpoint Type (EP Type).\r | |
57 | //\r | |
58 | #define ED_NOT_VALID 0\r | |
59 | #define ED_ISOCH_OUT 1\r | |
60 | #define ED_BULK_OUT 2\r | |
61 | #define ED_INTERRUPT_OUT 3\r | |
62 | #define ED_CONTROL_BIDIR 4\r | |
63 | #define ED_ISOCH_IN 5\r | |
64 | #define ED_BULK_IN 6\r | |
65 | #define ED_INTERRUPT_IN 7\r | |
66 | \r | |
67 | //\r | |
68 | // 6.4.5 TRB Completion Codes\r | |
69 | //\r | |
70 | #define TRB_COMPLETION_INVALID 0\r | |
71 | #define TRB_COMPLETION_SUCCESS 1\r | |
72 | #define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r | |
73 | #define TRB_COMPLETION_BABBLE_ERROR 3\r | |
74 | #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r | |
75 | #define TRB_COMPLETION_TRB_ERROR 5\r | |
76 | #define TRB_COMPLETION_STALL_ERROR 6\r | |
77 | #define TRB_COMPLETION_SHORT_PACKET 13\r | |
49be9c3c RN |
78 | #define TRB_COMPLETION_STOPPED 26\r |
79 | #define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r | |
92870c98 | 80 | \r |
81 | //\r | |
a9292c13 | 82 | // The topology string used to present usb device location\r |
92870c98 | 83 | //\r |
a9292c13 | 84 | typedef struct _USB_DEV_TOPOLOGY {\r |
85 | //\r | |
86 | // The tier concatenation of down stream port.\r | |
87 | //\r | |
88 | UINT32 RouteString:20;\r | |
89 | //\r | |
90 | // The root port number of the chain.\r | |
91 | //\r | |
92 | UINT32 RootPortNum:8;\r | |
93 | //\r | |
94 | // The Tier the device reside.\r | |
95 | //\r | |
96 | UINT32 TierNum:4;\r | |
97 | } USB_DEV_TOPOLOGY;\r | |
98 | \r | |
99 | //\r | |
100 | // USB Device's RouteChart\r | |
101 | //\r | |
102 | typedef union _USB_DEV_ROUTE {\r | |
103 | UINT32 Dword;\r | |
104 | USB_DEV_TOPOLOGY Route;\r | |
92870c98 | 105 | } USB_DEV_ROUTE;\r |
106 | \r | |
107 | //\r | |
108 | // Endpoint address and its capabilities\r | |
109 | //\r | |
110 | typedef struct _USB_ENDPOINT {\r | |
6b4483cd | 111 | //\r |
112 | // Store logical device address assigned by UsbBus\r | |
113 | // It's because some XHCI host controllers may assign the same physcial device\r | |
114 | // address for those devices inserted at different root port.\r | |
115 | //\r | |
116 | UINT8 BusAddr;\r | |
92870c98 | 117 | UINT8 DevAddr;\r |
118 | UINT8 EpAddr;\r | |
119 | EFI_USB_DATA_DIRECTION Direction;\r | |
120 | UINT8 DevSpeed;\r | |
121 | UINTN MaxPacket;\r | |
122 | UINTN Type;\r | |
123 | } USB_ENDPOINT;\r | |
124 | \r | |
125 | //\r | |
a9292c13 | 126 | // TRB Template\r |
92870c98 | 127 | //\r |
a9292c13 | 128 | typedef struct _TRB_TEMPLATE {\r |
129 | UINT32 Parameter1;\r | |
130 | \r | |
131 | UINT32 Parameter2;\r | |
132 | \r | |
133 | UINT32 Status;\r | |
134 | \r | |
92870c98 | 135 | UINT32 CycleBit:1;\r |
136 | UINT32 RsvdZ1:9;\r | |
137 | UINT32 Type:6;\r | |
a9292c13 | 138 | UINT32 Control:16;\r |
139 | } TRB_TEMPLATE;\r | |
92870c98 | 140 | \r |
141 | typedef struct _TRANSFER_RING {\r | |
142 | VOID *RingSeg0;\r | |
143 | UINTN TrbNumber;\r | |
a9292c13 | 144 | TRB_TEMPLATE *RingEnqueue;\r |
145 | TRB_TEMPLATE *RingDequeue;\r | |
92870c98 | 146 | UINT32 RingPCS;\r |
147 | } TRANSFER_RING;\r | |
148 | \r | |
149 | typedef struct _EVENT_RING {\r | |
92870c98 | 150 | VOID *ERSTBase;\r |
151 | VOID *EventRingSeg0;\r | |
152 | UINTN TrbNumber;\r | |
a9292c13 | 153 | TRB_TEMPLATE *EventRingEnqueue;\r |
154 | TRB_TEMPLATE *EventRingDequeue;\r | |
92870c98 | 155 | UINT32 EventRingCCS;\r |
156 | } EVENT_RING;\r | |
157 | \r | |
158 | //\r | |
159 | // URB (Usb Request Block) contains information for all kinds of\r | |
160 | // usb requests.\r | |
161 | //\r | |
162 | typedef struct _URB {\r | |
163 | UINT32 Signature;\r | |
164 | LIST_ENTRY UrbList;\r | |
165 | //\r | |
166 | // Usb Device URB related information\r | |
167 | //\r | |
168 | USB_ENDPOINT Ep;\r | |
169 | EFI_USB_DEVICE_REQUEST *Request;\r | |
170 | VOID *Data;\r | |
171 | UINTN DataLen;\r | |
1847ed0b EL |
172 | VOID *DataPhy;\r |
173 | VOID *DataMap;\r | |
92870c98 | 174 | EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r |
175 | VOID *Context;\r | |
176 | //\r | |
177 | // Execute result\r | |
178 | //\r | |
179 | UINT32 Result;\r | |
180 | //\r | |
181 | // completed data length\r | |
182 | //\r | |
183 | UINTN Completed;\r | |
184 | //\r | |
185 | // Command/Tranfer Ring info\r | |
186 | //\r | |
187 | TRANSFER_RING *Ring;\r | |
a9292c13 | 188 | TRB_TEMPLATE *TrbStart;\r |
189 | TRB_TEMPLATE *TrbEnd;\r | |
92870c98 | 190 | UINTN TrbNum;\r |
a50f7c4c | 191 | BOOLEAN StartDone;\r |
192 | BOOLEAN EndDone;\r | |
193 | BOOLEAN Finished;\r | |
194 | \r | |
195 | TRB_TEMPLATE *EvtTrb;\r | |
92870c98 | 196 | } URB;\r |
197 | \r | |
92870c98 | 198 | //\r |
199 | // 6.5 Event Ring Segment Table\r | |
200 | // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r | |
201 | // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r | |
202 | // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r | |
203 | // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r | |
204 | //\r | |
205 | typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r | |
206 | UINT32 PtrLo;\r | |
207 | UINT32 PtrHi;\r | |
208 | UINT32 RingTrbSize:16;\r | |
209 | UINT32 RsvdZ1:16;\r | |
210 | UINT32 RsvdZ2;\r | |
211 | } EVENT_RING_SEG_TABLE_ENTRY;\r | |
212 | \r | |
213 | //\r | |
214 | // 6.4.1.1 Normal TRB\r | |
215 | // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r | |
216 | // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r | |
217 | // Rings, and to define the Data stage information for Control Transfer Rings.\r | |
218 | //\r | |
219 | typedef struct _TRANSFER_TRB_NORMAL {\r | |
220 | UINT32 TRBPtrLo;\r | |
a9292c13 | 221 | \r |
92870c98 | 222 | UINT32 TRBPtrHi;\r |
a9292c13 | 223 | \r |
39e97c39 | 224 | UINT32 Length:17;\r |
92870c98 | 225 | UINT32 TDSize:5;\r |
226 | UINT32 IntTarget:10;\r | |
a9292c13 | 227 | \r |
92870c98 | 228 | UINT32 CycleBit:1;\r |
229 | UINT32 ENT:1;\r | |
230 | UINT32 ISP:1;\r | |
231 | UINT32 NS:1;\r | |
232 | UINT32 CH:1;\r | |
233 | UINT32 IOC:1;\r | |
234 | UINT32 IDT:1;\r | |
235 | UINT32 RsvdZ1:2;\r | |
236 | UINT32 BEI:1;\r | |
237 | UINT32 Type:6;\r | |
238 | UINT32 RsvdZ2:16;\r | |
239 | } TRANSFER_TRB_NORMAL;\r | |
240 | \r | |
241 | //\r | |
242 | // 6.4.1.2.1 Setup Stage TRB\r | |
243 | // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r | |
244 | //\r | |
a9292c13 | 245 | typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r |
92870c98 | 246 | UINT32 bmRequestType:8;\r |
247 | UINT32 bRequest:8;\r | |
248 | UINT32 wValue:16;\r | |
249 | \r | |
250 | UINT32 wIndex:16;\r | |
251 | UINT32 wLength:16;\r | |
252 | \r | |
39e97c39 | 253 | UINT32 Length:17;\r |
92870c98 | 254 | UINT32 RsvdZ1:5;\r |
255 | UINT32 IntTarget:10;\r | |
256 | \r | |
257 | UINT32 CycleBit:1;\r | |
258 | UINT32 RsvdZ2:4;\r | |
259 | UINT32 IOC:1;\r | |
260 | UINT32 IDT:1;\r | |
261 | UINT32 RsvdZ3:3;\r | |
262 | UINT32 Type:6;\r | |
263 | UINT32 TRT:2;\r | |
264 | UINT32 RsvdZ4:14;\r | |
265 | } TRANSFER_TRB_CONTROL_SETUP;\r | |
266 | \r | |
267 | //\r | |
268 | // 6.4.1.2.2 Data Stage TRB\r | |
269 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
270 | //\r | |
271 | typedef struct _TRANSFER_TRB_CONTROL_DATA {\r | |
272 | UINT32 TRBPtrLo;\r | |
a9292c13 | 273 | \r |
92870c98 | 274 | UINT32 TRBPtrHi;\r |
a9292c13 | 275 | \r |
39e97c39 | 276 | UINT32 Length:17;\r |
92870c98 | 277 | UINT32 TDSize:5;\r |
278 | UINT32 IntTarget:10;\r | |
a9292c13 | 279 | \r |
92870c98 | 280 | UINT32 CycleBit:1;\r |
281 | UINT32 ENT:1;\r | |
282 | UINT32 ISP:1;\r | |
283 | UINT32 NS:1;\r | |
284 | UINT32 CH:1;\r | |
285 | UINT32 IOC:1;\r | |
286 | UINT32 IDT:1;\r | |
287 | UINT32 RsvdZ1:3;\r | |
288 | UINT32 Type:6;\r | |
289 | UINT32 DIR:1;\r | |
290 | UINT32 RsvdZ2:15;\r | |
291 | } TRANSFER_TRB_CONTROL_DATA;\r | |
292 | \r | |
293 | //\r | |
294 | // 6.4.1.2.2 Data Stage TRB\r | |
295 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
296 | //\r | |
297 | typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r | |
298 | UINT32 RsvdZ1;\r | |
299 | UINT32 RsvdZ2;\r | |
a9292c13 | 300 | \r |
92870c98 | 301 | UINT32 RsvdZ3:22;\r |
302 | UINT32 IntTarget:10;\r | |
a9292c13 | 303 | \r |
92870c98 | 304 | UINT32 CycleBit:1;\r |
305 | UINT32 ENT:1;\r | |
306 | UINT32 RsvdZ4:2;\r | |
307 | UINT32 CH:1;\r | |
308 | UINT32 IOC:1;\r | |
309 | UINT32 RsvdZ5:4;\r | |
310 | UINT32 Type:6;\r | |
311 | UINT32 DIR:1;\r | |
312 | UINT32 RsvdZ6:15;\r | |
313 | } TRANSFER_TRB_CONTROL_STATUS;\r | |
314 | \r | |
315 | //\r | |
316 | // 6.4.2.1 Transfer Event TRB\r | |
317 | // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r | |
318 | // for more information on the use and operation of Transfer Events.\r | |
319 | //\r | |
320 | typedef struct _EVT_TRB_TRANSFER {\r | |
321 | UINT32 TRBPtrLo;\r | |
a9292c13 | 322 | \r |
92870c98 | 323 | UINT32 TRBPtrHi;\r |
a9292c13 | 324 | \r |
39e97c39 | 325 | UINT32 Length:24;\r |
a9292c13 | 326 | UINT32 Completecode:8;\r |
327 | \r | |
92870c98 | 328 | UINT32 CycleBit:1;\r |
329 | UINT32 RsvdZ1:1;\r | |
330 | UINT32 ED:1;\r | |
331 | UINT32 RsvdZ2:7;\r | |
332 | UINT32 Type:6;\r | |
a9292c13 | 333 | UINT32 EndpointId:5;\r |
92870c98 | 334 | UINT32 RsvdZ3:3;\r |
335 | UINT32 SlotId:8;\r | |
336 | } EVT_TRB_TRANSFER;\r | |
337 | \r | |
338 | //\r | |
339 | // 6.4.2.2 Command Completion Event TRB\r | |
340 | // A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r | |
341 | // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r | |
342 | //\r | |
a9292c13 | 343 | typedef struct _EVT_TRB_COMMAND_COMPLETION {\r |
92870c98 | 344 | UINT32 TRBPtrLo;\r |
a9292c13 | 345 | \r |
92870c98 | 346 | UINT32 TRBPtrHi;\r |
a9292c13 | 347 | \r |
92870c98 | 348 | UINT32 RsvdZ2:24;\r |
a9292c13 | 349 | UINT32 Completecode:8;\r |
350 | \r | |
92870c98 | 351 | UINT32 CycleBit:1;\r |
352 | UINT32 RsvdZ3:9;\r | |
353 | UINT32 Type:6;\r | |
354 | UINT32 VFID:8;\r | |
355 | UINT32 SlotId:8;\r | |
a9292c13 | 356 | } EVT_TRB_COMMAND_COMPLETION;\r |
357 | \r | |
358 | typedef union _TRB {\r | |
359 | TRB_TEMPLATE TrbTemplate;\r | |
360 | TRANSFER_TRB_NORMAL TrbNormal;\r | |
361 | TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r | |
362 | TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r | |
363 | TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r | |
364 | } TRB;\r | |
92870c98 | 365 | \r |
366 | //\r | |
367 | // 6.4.3.1 No Op Command TRB\r | |
368 | // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r | |
a9292c13 | 369 | // mechanisms offered by the xHCI.\r |
92870c98 | 370 | //\r |
371 | typedef struct _CMD_TRB_NO_OP {\r | |
372 | UINT32 RsvdZ0;\r | |
373 | UINT32 RsvdZ1;\r | |
374 | UINT32 RsvdZ2;\r | |
a9292c13 | 375 | \r |
92870c98 | 376 | UINT32 CycleBit:1;\r |
377 | UINT32 RsvdZ3:9;\r | |
378 | UINT32 Type:6;\r | |
379 | UINT32 RsvdZ4:16;\r | |
380 | } CMD_TRB_NO_OP;\r | |
381 | \r | |
382 | //\r | |
383 | // 6.4.3.2 Enable Slot Command TRB\r | |
384 | // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r | |
385 | // selected slot to the host in a Command Completion Event.\r | |
386 | //\r | |
a9292c13 | 387 | typedef struct _CMD_TRB_ENABLE_SLOT {\r |
92870c98 | 388 | UINT32 RsvdZ0;\r |
389 | UINT32 RsvdZ1;\r | |
390 | UINT32 RsvdZ2;\r | |
a9292c13 | 391 | \r |
92870c98 | 392 | UINT32 CycleBit:1;\r |
393 | UINT32 RsvdZ3:9;\r | |
394 | UINT32 Type:6;\r | |
395 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 396 | } CMD_TRB_ENABLE_SLOT;\r |
92870c98 | 397 | \r |
398 | //\r | |
399 | // 6.4.3.3 Disable Slot Command TRB\r | |
400 | // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r | |
401 | // internal xHC resources assigned to the slot.\r | |
402 | //\r | |
a9292c13 | 403 | typedef struct _CMD_TRB_DISABLE_SLOT {\r |
92870c98 | 404 | UINT32 RsvdZ0;\r |
405 | UINT32 RsvdZ1;\r | |
406 | UINT32 RsvdZ2;\r | |
a9292c13 | 407 | \r |
92870c98 | 408 | UINT32 CycleBit:1;\r |
409 | UINT32 RsvdZ3:9;\r | |
410 | UINT32 Type:6;\r | |
411 | UINT32 RsvdZ4:8;\r | |
412 | UINT32 SlotId:8;\r | |
a9292c13 | 413 | } CMD_TRB_DISABLE_SLOT;\r |
92870c98 | 414 | \r |
415 | //\r | |
416 | // 6.4.3.4 Address Device Command TRB\r | |
417 | // The Address Device Command TRB transitions the selected Device Context from the Default to the\r | |
418 | // Addressed state and causes the xHC to select an address for the USB device in the Default State and\r | |
419 | // issue a SET_ADDRESS request to the USB device.\r | |
420 | //\r | |
a9292c13 | 421 | typedef struct _CMD_TRB_ADDRESS_DEVICE {\r |
92870c98 | 422 | UINT32 PtrLo;\r |
a9292c13 | 423 | \r |
92870c98 | 424 | UINT32 PtrHi;\r |
a9292c13 | 425 | \r |
92870c98 | 426 | UINT32 RsvdZ1;\r |
a9292c13 | 427 | \r |
92870c98 | 428 | UINT32 CycleBit:1;\r |
429 | UINT32 RsvdZ2:8;\r | |
430 | UINT32 BSR:1;\r | |
431 | UINT32 Type:6;\r | |
432 | UINT32 RsvdZ3:8;\r | |
433 | UINT32 SlotId:8;\r | |
a9292c13 | 434 | } CMD_TRB_ADDRESS_DEVICE;\r |
92870c98 | 435 | \r |
436 | //\r | |
437 | // 6.4.3.5 Configure Endpoint Command TRB\r | |
438 | // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r | |
439 | // endpoints selected by the command.\r | |
440 | //\r | |
a9292c13 | 441 | typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r |
92870c98 | 442 | UINT32 PtrLo;\r |
a9292c13 | 443 | \r |
92870c98 | 444 | UINT32 PtrHi;\r |
a9292c13 | 445 | \r |
92870c98 | 446 | UINT32 RsvdZ1;\r |
a9292c13 | 447 | \r |
92870c98 | 448 | UINT32 CycleBit:1;\r |
449 | UINT32 RsvdZ2:8;\r | |
450 | UINT32 DC:1;\r | |
451 | UINT32 Type:6;\r | |
452 | UINT32 RsvdZ3:8;\r | |
453 | UINT32 SlotId:8;\r | |
a9292c13 | 454 | } CMD_TRB_CONFIG_ENDPOINT;\r |
92870c98 | 455 | \r |
456 | //\r | |
457 | // 6.4.3.6 Evaluate Context Command TRB\r | |
458 | // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r | |
459 | // Context data structures in the Device Context have been modified by system software and that the xHC\r | |
460 | // shall evaluate any changes\r | |
461 | //\r | |
a9292c13 | 462 | typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r |
92870c98 | 463 | UINT32 PtrLo;\r |
a9292c13 | 464 | \r |
92870c98 | 465 | UINT32 PtrHi;\r |
a9292c13 | 466 | \r |
92870c98 | 467 | UINT32 RsvdZ1;\r |
a9292c13 | 468 | \r |
92870c98 | 469 | UINT32 CycleBit:1;\r |
470 | UINT32 RsvdZ2:9;\r | |
471 | UINT32 Type:6;\r | |
472 | UINT32 RsvdZ3:8;\r | |
473 | UINT32 SlotId:8;\r | |
a9292c13 | 474 | } CMD_TRB_EVALUATE_CONTEXT;\r |
92870c98 | 475 | \r |
476 | //\r | |
477 | // 6.4.3.7 Reset Endpoint Command TRB\r | |
478 | // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r | |
479 | //\r | |
a9292c13 | 480 | typedef struct _CMD_TRB_RESET_ENDPOINT {\r |
92870c98 | 481 | UINT32 RsvdZ0;\r |
482 | UINT32 RsvdZ1;\r | |
483 | UINT32 RsvdZ2;\r | |
a9292c13 | 484 | \r |
92870c98 | 485 | UINT32 CycleBit:1;\r |
486 | UINT32 RsvdZ3:8;\r | |
487 | UINT32 TSP:1;\r | |
488 | UINT32 Type:6;\r | |
489 | UINT32 EDID:5;\r | |
490 | UINT32 RsvdZ4:3;\r | |
491 | UINT32 SlotId:8;\r | |
a9292c13 | 492 | } CMD_TRB_RESET_ENDPOINT;\r |
92870c98 | 493 | \r |
494 | //\r | |
495 | // 6.4.3.8 Stop Endpoint Command TRB\r | |
496 | // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r | |
497 | // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r | |
498 | //\r | |
a9292c13 | 499 | typedef struct _CMD_TRB_STOP_ENDPOINT {\r |
92870c98 | 500 | UINT32 RsvdZ0;\r |
501 | UINT32 RsvdZ1;\r | |
502 | UINT32 RsvdZ2;\r | |
a9292c13 | 503 | \r |
92870c98 | 504 | UINT32 CycleBit:1;\r |
505 | UINT32 RsvdZ3:9;\r | |
506 | UINT32 Type:6;\r | |
507 | UINT32 EDID:5;\r | |
508 | UINT32 RsvdZ4:2;\r | |
509 | UINT32 SP:1;\r | |
510 | UINT32 SlotId:8;\r | |
a9292c13 | 511 | } CMD_TRB_STOP_ENDPOINT;\r |
92870c98 | 512 | \r |
513 | //\r | |
514 | // 6.4.3.9 Set TR Dequeue Pointer Command TRB\r | |
515 | // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r | |
516 | // Pointer and DCS fields of an Endpoint or Stream Context.\r | |
517 | //\r | |
a9292c13 | 518 | typedef struct _CMD_SET_TR_DEQ_POINTER {\r |
92870c98 | 519 | UINT32 PtrLo;\r |
a9292c13 | 520 | \r |
92870c98 | 521 | UINT32 PtrHi;\r |
a9292c13 | 522 | \r |
92870c98 | 523 | UINT32 RsvdZ1:16;\r |
524 | UINT32 StreamID:16;\r | |
a9292c13 | 525 | \r |
92870c98 | 526 | UINT32 CycleBit:1;\r |
527 | UINT32 RsvdZ2:9;\r | |
528 | UINT32 Type:6;\r | |
529 | UINT32 Endpoint:5;\r | |
530 | UINT32 RsvdZ3:3;\r | |
531 | UINT32 SlotId:8;\r | |
a9292c13 | 532 | } CMD_SET_TR_DEQ_POINTER;\r |
92870c98 | 533 | \r |
534 | //\r | |
a9292c13 | 535 | // 6.4.4.1 Link TRB\r |
92870c98 | 536 | // A Link TRB provides support for non-contiguous TRB Rings.\r |
537 | //\r | |
a9292c13 | 538 | typedef struct _LINK_TRB {\r |
92870c98 | 539 | UINT32 PtrLo;\r |
a9292c13 | 540 | \r |
92870c98 | 541 | UINT32 PtrHi;\r |
a9292c13 | 542 | \r |
92870c98 | 543 | UINT32 RsvdZ1:22;\r |
544 | UINT32 InterTarget:10;\r | |
a9292c13 | 545 | \r |
92870c98 | 546 | UINT32 CycleBit:1;\r |
547 | UINT32 TC:1;\r | |
548 | UINT32 RsvdZ2:2;\r | |
549 | UINT32 CH:1;\r | |
550 | UINT32 IOC:1;\r | |
551 | UINT32 RsvdZ3:4;\r | |
552 | UINT32 Type:6;\r | |
553 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 554 | } LINK_TRB;\r |
92870c98 | 555 | \r |
556 | //\r | |
557 | // 6.2.2 Slot Context\r | |
558 | //\r | |
559 | typedef struct _SLOT_CONTEXT {\r | |
a9292c13 | 560 | UINT32 RouteString:20;\r |
92870c98 | 561 | UINT32 Speed:4;\r |
562 | UINT32 RsvdZ1:1;\r | |
563 | UINT32 MTT:1;\r | |
564 | UINT32 Hub:1;\r | |
565 | UINT32 ContextEntries:5;\r | |
566 | \r | |
567 | UINT32 MaxExitLatency:16;\r | |
568 | UINT32 RootHubPortNum:8;\r | |
569 | UINT32 PortNum:8;\r | |
570 | \r | |
571 | UINT32 TTHubSlotId:8;\r | |
572 | UINT32 TTPortNum:8;\r | |
573 | UINT32 TTT:2;\r | |
574 | UINT32 RsvdZ2:4;\r | |
575 | UINT32 InterTarget:10;\r | |
576 | \r | |
577 | UINT32 DeviceAddress:8;\r | |
578 | UINT32 RsvdZ3:19;\r | |
579 | UINT32 SlotState:5;\r | |
580 | \r | |
581 | UINT32 RsvdZ4;\r | |
582 | UINT32 RsvdZ5;\r | |
583 | UINT32 RsvdZ6;\r | |
584 | UINT32 RsvdZ7;\r | |
585 | } SLOT_CONTEXT;\r | |
586 | \r | |
6b4483cd | 587 | typedef struct _SLOT_CONTEXT_64 {\r |
588 | UINT32 RouteString:20;\r | |
589 | UINT32 Speed:4;\r | |
590 | UINT32 RsvdZ1:1;\r | |
591 | UINT32 MTT:1;\r | |
592 | UINT32 Hub:1;\r | |
593 | UINT32 ContextEntries:5;\r | |
594 | \r | |
595 | UINT32 MaxExitLatency:16;\r | |
596 | UINT32 RootHubPortNum:8;\r | |
597 | UINT32 PortNum:8;\r | |
598 | \r | |
599 | UINT32 TTHubSlotId:8;\r | |
600 | UINT32 TTPortNum:8;\r | |
601 | UINT32 TTT:2;\r | |
602 | UINT32 RsvdZ2:4;\r | |
603 | UINT32 InterTarget:10;\r | |
604 | \r | |
605 | UINT32 DeviceAddress:8;\r | |
606 | UINT32 RsvdZ3:19;\r | |
607 | UINT32 SlotState:5;\r | |
608 | \r | |
609 | UINT32 RsvdZ4;\r | |
610 | UINT32 RsvdZ5;\r | |
611 | UINT32 RsvdZ6;\r | |
612 | UINT32 RsvdZ7;\r | |
613 | \r | |
614 | UINT32 RsvdZ8;\r | |
615 | UINT32 RsvdZ9;\r | |
616 | UINT32 RsvdZ10;\r | |
617 | UINT32 RsvdZ11;\r | |
d1102dba | 618 | \r |
6b4483cd | 619 | UINT32 RsvdZ12;\r |
620 | UINT32 RsvdZ13;\r | |
621 | UINT32 RsvdZ14;\r | |
622 | UINT32 RsvdZ15;\r | |
623 | \r | |
624 | } SLOT_CONTEXT_64;\r | |
625 | \r | |
626 | \r | |
92870c98 | 627 | //\r |
628 | // 6.2.3 Endpoint Context\r | |
629 | //\r | |
630 | typedef struct _ENDPOINT_CONTEXT {\r | |
631 | UINT32 EPState:3;\r | |
632 | UINT32 RsvdZ1:5;\r | |
633 | UINT32 Mult:2;\r | |
634 | UINT32 MaxPStreams:5;\r | |
635 | UINT32 LSA:1;\r | |
636 | UINT32 Interval:8;\r | |
637 | UINT32 RsvdZ2:8;\r | |
638 | \r | |
639 | UINT32 RsvdZ3:1;\r | |
640 | UINT32 CErr:2;\r | |
641 | UINT32 EPType:3;\r | |
642 | UINT32 RsvdZ4:1;\r | |
643 | UINT32 HID:1;\r | |
644 | UINT32 MaxBurstSize:8;\r | |
645 | UINT32 MaxPacketSize:16;\r | |
646 | \r | |
647 | UINT32 PtrLo;\r | |
648 | \r | |
649 | UINT32 PtrHi;\r | |
650 | \r | |
651 | UINT32 AverageTRBLength:16;\r | |
652 | UINT32 MaxESITPayload:16;\r | |
653 | \r | |
654 | UINT32 RsvdZ5;\r | |
655 | UINT32 RsvdZ6;\r | |
656 | UINT32 RsvdZ7;\r | |
657 | } ENDPOINT_CONTEXT;\r | |
658 | \r | |
6b4483cd | 659 | typedef struct _ENDPOINT_CONTEXT_64 {\r |
660 | UINT32 EPState:3;\r | |
661 | UINT32 RsvdZ1:5;\r | |
662 | UINT32 Mult:2;\r | |
663 | UINT32 MaxPStreams:5;\r | |
664 | UINT32 LSA:1;\r | |
665 | UINT32 Interval:8;\r | |
666 | UINT32 RsvdZ2:8;\r | |
667 | \r | |
668 | UINT32 RsvdZ3:1;\r | |
669 | UINT32 CErr:2;\r | |
670 | UINT32 EPType:3;\r | |
671 | UINT32 RsvdZ4:1;\r | |
672 | UINT32 HID:1;\r | |
673 | UINT32 MaxBurstSize:8;\r | |
674 | UINT32 MaxPacketSize:16;\r | |
675 | \r | |
676 | UINT32 PtrLo;\r | |
677 | \r | |
678 | UINT32 PtrHi;\r | |
679 | \r | |
680 | UINT32 AverageTRBLength:16;\r | |
681 | UINT32 MaxESITPayload:16;\r | |
682 | \r | |
683 | UINT32 RsvdZ5;\r | |
684 | UINT32 RsvdZ6;\r | |
685 | UINT32 RsvdZ7;\r | |
d1102dba | 686 | \r |
6b4483cd | 687 | UINT32 RsvdZ8;\r |
688 | UINT32 RsvdZ9;\r | |
689 | UINT32 RsvdZ10;\r | |
690 | UINT32 RsvdZ11;\r | |
d1102dba | 691 | \r |
6b4483cd | 692 | UINT32 RsvdZ12;\r |
693 | UINT32 RsvdZ13;\r | |
694 | UINT32 RsvdZ14;\r | |
695 | UINT32 RsvdZ15;\r | |
696 | \r | |
697 | } ENDPOINT_CONTEXT_64;\r | |
698 | \r | |
699 | \r | |
92870c98 | 700 | //\r |
701 | // 6.2.5.1 Input Control Context\r | |
702 | //\r | |
703 | typedef struct _INPUT_CONTRL_CONTEXT {\r | |
704 | UINT32 Dword1;\r | |
705 | UINT32 Dword2;\r | |
706 | UINT32 RsvdZ1;\r | |
707 | UINT32 RsvdZ2;\r | |
708 | UINT32 RsvdZ3;\r | |
709 | UINT32 RsvdZ4;\r | |
710 | UINT32 RsvdZ5;\r | |
711 | UINT32 RsvdZ6;\r | |
712 | } INPUT_CONTRL_CONTEXT;\r | |
713 | \r | |
6b4483cd | 714 | typedef struct _INPUT_CONTRL_CONTEXT_64 {\r |
715 | UINT32 Dword1;\r | |
716 | UINT32 Dword2;\r | |
717 | UINT32 RsvdZ1;\r | |
718 | UINT32 RsvdZ2;\r | |
719 | UINT32 RsvdZ3;\r | |
720 | UINT32 RsvdZ4;\r | |
721 | UINT32 RsvdZ5;\r | |
722 | UINT32 RsvdZ6;\r | |
723 | UINT32 RsvdZ7;\r | |
724 | UINT32 RsvdZ8;\r | |
725 | UINT32 RsvdZ9;\r | |
726 | UINT32 RsvdZ10;\r | |
727 | UINT32 RsvdZ11;\r | |
728 | UINT32 RsvdZ12;\r | |
729 | UINT32 RsvdZ13;\r | |
730 | UINT32 RsvdZ14;\r | |
731 | } INPUT_CONTRL_CONTEXT_64;\r | |
732 | \r | |
92870c98 | 733 | //\r |
734 | // 6.2.1 Device Context\r | |
735 | //\r | |
736 | typedef struct _DEVICE_CONTEXT {\r | |
737 | SLOT_CONTEXT Slot;\r | |
738 | ENDPOINT_CONTEXT EP[31];\r | |
739 | } DEVICE_CONTEXT;\r | |
740 | \r | |
6b4483cd | 741 | typedef struct _DEVICE_CONTEXT_64 {\r |
742 | SLOT_CONTEXT_64 Slot;\r | |
743 | ENDPOINT_CONTEXT_64 EP[31];\r | |
744 | } DEVICE_CONTEXT_64;\r | |
745 | \r | |
92870c98 | 746 | //\r |
747 | // 6.2.5 Input Context\r | |
748 | //\r | |
749 | typedef struct _INPUT_CONTEXT {\r | |
750 | INPUT_CONTRL_CONTEXT InputControlContext;\r | |
751 | SLOT_CONTEXT Slot;\r | |
752 | ENDPOINT_CONTEXT EP[31];\r | |
753 | } INPUT_CONTEXT;\r | |
754 | \r | |
6b4483cd | 755 | typedef struct _INPUT_CONTEXT_64 {\r |
756 | INPUT_CONTRL_CONTEXT_64 InputControlContext;\r | |
757 | SLOT_CONTEXT_64 Slot;\r | |
758 | ENDPOINT_CONTEXT_64 EP[31];\r | |
759 | } INPUT_CONTEXT_64;\r | |
760 | \r | |
761 | \r | |
92870c98 | 762 | /**\r |
763 | Initialize the XHCI host controller for schedule.\r | |
764 | \r | |
a9292c13 | 765 | @param Xhc The XHCI Instance to be initialized.\r |
92870c98 | 766 | \r |
767 | **/\r | |
768 | VOID\r | |
769 | XhcInitSched (\r | |
a9292c13 | 770 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 771 | );\r |
772 | \r | |
773 | /**\r | |
774 | Free the resouce allocated at initializing schedule.\r | |
775 | \r | |
a9292c13 | 776 | @param Xhc The XHCI Instance.\r |
92870c98 | 777 | \r |
778 | **/\r | |
779 | VOID\r | |
780 | XhcFreeSched (\r | |
a9292c13 | 781 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 782 | );\r |
783 | \r | |
784 | /**\r | |
785 | Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r | |
786 | \r | |
a9292c13 | 787 | @param Xhc The XHCI Instance.\r |
92870c98 | 788 | @param Urb The URB to be rung.\r |
789 | \r | |
790 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
791 | \r | |
792 | **/\r | |
793 | EFI_STATUS\r | |
794 | RingIntTransferDoorBell (\r | |
a9292c13 | 795 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 796 | IN URB *Urb\r |
797 | );\r | |
798 | \r | |
799 | /**\r | |
800 | Execute the transfer by polling the URB. This is a synchronous operation.\r | |
801 | \r | |
a9292c13 | 802 | @param Xhc The XHCI Instance.\r |
92870c98 | 803 | @param CmdTransfer The executed URB is for cmd transfer or not.\r |
804 | @param Urb The URB to execute.\r | |
a9292c13 | 805 | @param Timeout The time to wait before abort, in millisecond.\r |
92870c98 | 806 | \r |
807 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
808 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
809 | @return EFI_SUCCESS The transfer finished OK.\r | |
810 | \r | |
811 | **/\r | |
812 | EFI_STATUS\r | |
813 | XhcExecTransfer (\r | |
a9292c13 | 814 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 815 | IN BOOLEAN CmdTransfer,\r |
816 | IN URB *Urb,\r | |
a9292c13 | 817 | IN UINTN Timeout\r |
92870c98 | 818 | );\r |
819 | \r | |
820 | /**\r | |
821 | Delete a single asynchronous interrupt transfer for\r | |
822 | the device and endpoint.\r | |
823 | \r | |
a9292c13 | 824 | @param Xhc The XHCI Instance.\r |
6b4483cd | 825 | @param BusAddr The logical device address assigned by UsbBus driver.\r |
92870c98 | 826 | @param EpNum The endpoint of the target.\r |
827 | \r | |
828 | @retval EFI_SUCCESS An asynchronous transfer is removed.\r | |
829 | @retval EFI_NOT_FOUND No transfer for the device is found.\r | |
830 | \r | |
831 | **/\r | |
832 | EFI_STATUS\r | |
833 | XhciDelAsyncIntTransfer (\r | |
a9292c13 | 834 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 835 | IN UINT8 BusAddr,\r |
92870c98 | 836 | IN UINT8 EpNum\r |
837 | );\r | |
838 | \r | |
839 | /**\r | |
840 | Remove all the asynchronous interrupt transfers.\r | |
841 | \r | |
a9292c13 | 842 | @param Xhc The XHCI Instance.\r |
92870c98 | 843 | \r |
844 | **/\r | |
845 | VOID\r | |
846 | XhciDelAllAsyncIntTransfers (\r | |
a9292c13 | 847 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 848 | );\r |
849 | \r | |
6681582d SZ |
850 | /**\r |
851 | Insert a single asynchronous interrupt transfer for\r | |
852 | the device and endpoint.\r | |
853 | \r | |
854 | @param Xhc The XHCI Instance\r | |
855 | @param BusAddr The logical device address assigned by UsbBus driver\r | |
856 | @param EpAddr Endpoint addrress\r | |
857 | @param DevSpeed The device speed\r | |
858 | @param MaxPacket The max packet length of the endpoint\r | |
859 | @param DataLen The length of data buffer\r | |
860 | @param Callback The function to call when data is transferred\r | |
861 | @param Context The context to the callback\r | |
862 | \r | |
863 | @return Created URB or NULL\r | |
864 | \r | |
865 | **/\r | |
866 | URB *\r | |
867 | XhciInsertAsyncIntTransfer (\r | |
868 | IN USB_XHCI_INSTANCE *Xhc,\r | |
869 | IN UINT8 BusAddr,\r | |
870 | IN UINT8 EpAddr,\r | |
871 | IN UINT8 DevSpeed,\r | |
872 | IN UINTN MaxPacket,\r | |
873 | IN UINTN DataLen,\r | |
874 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
875 | IN VOID *Context\r | |
876 | );\r | |
877 | \r | |
92870c98 | 878 | /**\r |
879 | Set Bios Ownership\r | |
880 | \r | |
a9292c13 | 881 | @param Xhc The XHCI Instance.\r |
92870c98 | 882 | \r |
883 | **/\r | |
884 | VOID\r | |
885 | XhcSetBiosOwnership (\r | |
a9292c13 | 886 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 887 | );\r |
888 | \r | |
889 | /**\r | |
890 | Clear Bios Ownership\r | |
891 | \r | |
a9292c13 | 892 | @param Xhc The XHCI Instance.\r |
92870c98 | 893 | \r |
894 | **/\r | |
895 | VOID\r | |
896 | XhcClearBiosOwnership (\r | |
a9292c13 | 897 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 898 | );\r |
899 | \r | |
92870c98 | 900 | /**\r |
901 | Find out the slot id according to the device's route string.\r | |
902 | \r | |
a9292c13 | 903 | @param Xhc The XHCI Instance.\r |
904 | @param RouteString The route string described the device location.\r | |
92870c98 | 905 | \r |
906 | @return The slot id used by the device.\r | |
907 | \r | |
908 | **/\r | |
909 | UINT8\r | |
910 | EFIAPI\r | |
911 | XhcRouteStringToSlotId (\r | |
a9292c13 | 912 | IN USB_XHCI_INSTANCE *Xhc,\r |
913 | IN USB_DEV_ROUTE RouteString\r | |
92870c98 | 914 | );\r |
915 | \r | |
916 | /**\r | |
917 | Calculate the device context index by endpoint address and direction.\r | |
918 | \r | |
919 | @param EpAddr The target endpoint number.\r | |
920 | @param Direction The direction of the target endpoint.\r | |
921 | \r | |
922 | @return The device context index of endpoint.\r | |
923 | \r | |
924 | **/\r | |
925 | UINT8\r | |
926 | XhcEndpointToDci (\r | |
927 | IN UINT8 EpAddr,\r | |
928 | IN UINT8 Direction\r | |
929 | );\r | |
930 | \r | |
931 | /**\r | |
932 | Ring the door bell to notify XHCI there is a transaction to be executed.\r | |
933 | \r | |
a9292c13 | 934 | @param Xhc The XHCI Instance.\r |
92870c98 | 935 | @param SlotId The slot id of the target device.\r |
936 | @param Dci The device context index of the target slot or endpoint.\r | |
937 | \r | |
938 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
939 | \r | |
940 | **/\r | |
941 | EFI_STATUS\r | |
942 | EFIAPI\r | |
943 | XhcRingDoorBell (\r | |
a9292c13 | 944 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 945 | IN UINT8 SlotId,\r |
946 | IN UINT8 Dci\r | |
947 | );\r | |
948 | \r | |
949 | /**\r | |
950 | Interrupt transfer periodic check handler.\r | |
951 | \r | |
952 | @param Event Interrupt event.\r | |
a9292c13 | 953 | @param Context Pointer to USB_XHCI_INSTANCE.\r |
92870c98 | 954 | \r |
955 | **/\r | |
956 | VOID\r | |
957 | EFIAPI\r | |
958 | XhcMonitorAsyncRequests (\r | |
959 | IN EFI_EVENT Event,\r | |
960 | IN VOID *Context\r | |
961 | );\r | |
962 | \r | |
963 | /**\r | |
964 | Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r | |
965 | \r | |
a9292c13 | 966 | @param Xhc The XHCI Instance.\r |
92870c98 | 967 | @param ParentRouteChart The route string pointed to the parent device if it exists.\r |
968 | @param Port The port to be polled.\r | |
969 | @param PortState The port state.\r | |
970 | \r | |
971 | @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r | |
972 | @retval Others Should not appear.\r | |
973 | \r | |
974 | **/\r | |
975 | EFI_STATUS\r | |
976 | EFIAPI\r | |
977 | XhcPollPortStatusChange (\r | |
a9292c13 | 978 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 979 | IN USB_DEV_ROUTE ParentRouteChart,\r |
980 | IN UINT8 Port,\r | |
981 | IN EFI_USB_PORT_STATUS *PortState\r | |
982 | );\r | |
983 | \r | |
984 | /**\r | |
985 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
986 | \r | |
a9292c13 | 987 | @param Xhc The XHCI Instance.\r |
92870c98 | 988 | @param SlotId The slot id to be configured.\r |
989 | @param PortNum The total number of downstream port supported by the hub.\r | |
990 | @param TTT The TT think time of the hub device.\r | |
991 | @param MTT The multi-TT of the hub device.\r | |
992 | \r | |
993 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
994 | \r | |
995 | **/\r | |
996 | EFI_STATUS\r | |
997 | XhcConfigHubContext (\r | |
a9292c13 | 998 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 999 | IN UINT8 SlotId,\r |
1000 | IN UINT8 PortNum,\r | |
1001 | IN UINT8 TTT,\r | |
1002 | IN UINT8 MTT\r | |
1003 | );\r | |
1004 | \r | |
6b4483cd | 1005 | \r |
1006 | /**\r | |
1007 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
1008 | \r | |
1009 | @param Xhc The XHCI Instance.\r | |
1010 | @param SlotId The slot id to be configured.\r | |
1011 | @param PortNum The total number of downstream port supported by the hub.\r | |
1012 | @param TTT The TT think time of the hub device.\r | |
1013 | @param MTT The multi-TT of the hub device.\r | |
1014 | \r | |
1015 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
1016 | \r | |
1017 | **/\r | |
1018 | EFI_STATUS\r | |
1019 | XhcConfigHubContext64 (\r | |
1020 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1021 | IN UINT8 SlotId,\r | |
1022 | IN UINT8 PortNum,\r | |
1023 | IN UINT8 TTT,\r | |
1024 | IN UINT8 MTT\r | |
1025 | );\r | |
1026 | \r | |
1027 | \r | |
92870c98 | 1028 | /**\r |
1029 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1030 | \r | |
a9292c13 | 1031 | @param Xhc The XHCI Instance.\r |
92870c98 | 1032 | @param SlotId The slot id to be configured.\r |
1033 | @param DeviceSpeed The device's speed.\r | |
1034 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1035 | \r | |
1036 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1037 | \r | |
1038 | **/\r | |
1039 | EFI_STATUS\r | |
1040 | EFIAPI\r | |
1041 | XhcSetConfigCmd (\r | |
a9292c13 | 1042 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1043 | IN UINT8 SlotId,\r |
1044 | IN UINT8 DeviceSpeed,\r | |
1045 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1046 | );\r | |
1047 | \r | |
6b4483cd | 1048 | \r |
1049 | /**\r | |
1050 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1051 | \r | |
1052 | @param Xhc The XHCI Instance.\r | |
1053 | @param SlotId The slot id to be configured.\r | |
1054 | @param DeviceSpeed The device's speed.\r | |
1055 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1056 | \r | |
1057 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1058 | \r | |
1059 | **/\r | |
1060 | EFI_STATUS\r | |
1061 | EFIAPI\r | |
1062 | XhcSetConfigCmd64 (\r | |
1063 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1064 | IN UINT8 SlotId,\r | |
1065 | IN UINT8 DeviceSpeed,\r | |
1066 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1067 | );\r | |
1068 | \r | |
e1f2dfec SZ |
1069 | /**\r |
1070 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1071 | \r | |
1072 | @param Xhc The XHCI Instance.\r | |
1073 | @param SlotId The slot id to be configured.\r | |
1074 | @param DeviceSpeed The device's speed.\r | |
1075 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1076 | @param Request USB device request to send.\r | |
1077 | \r | |
1078 | @retval EFI_SUCCESS Successfully set interface.\r | |
1079 | \r | |
1080 | **/\r | |
1081 | EFI_STATUS\r | |
1082 | EFIAPI\r | |
1083 | XhcSetInterface (\r | |
1084 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1085 | IN UINT8 SlotId,\r | |
1086 | IN UINT8 DeviceSpeed,\r | |
1087 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1088 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1089 | );\r | |
1090 | \r | |
1091 | /**\r | |
1092 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1093 | \r | |
1094 | @param Xhc The XHCI Instance.\r | |
1095 | @param SlotId The slot id to be configured.\r | |
1096 | @param DeviceSpeed The device's speed.\r | |
1097 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1098 | @param Request USB device request to send.\r | |
1099 | \r | |
1100 | @retval EFI_SUCCESS Successfully set interface.\r | |
1101 | \r | |
1102 | **/\r | |
1103 | EFI_STATUS\r | |
1104 | EFIAPI\r | |
1105 | XhcSetInterface64 (\r | |
1106 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1107 | IN UINT8 SlotId,\r | |
1108 | IN UINT8 DeviceSpeed,\r | |
1109 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1110 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1111 | );\r | |
6b4483cd | 1112 | \r |
92870c98 | 1113 | /**\r |
1114 | Find out the actual device address according to the requested device address from UsbBus.\r | |
1115 | \r | |
a9292c13 | 1116 | @param Xhc The XHCI Instance.\r |
1117 | @param BusDevAddr The requested device address by UsbBus upper driver.\r | |
92870c98 | 1118 | \r |
1119 | @return The actual device address assigned to the device.\r | |
1120 | \r | |
1121 | **/\r | |
1122 | UINT8\r | |
1123 | EFIAPI\r | |
1124 | XhcBusDevAddrToSlotId (\r | |
a9292c13 | 1125 | IN USB_XHCI_INSTANCE *Xhc,\r |
1126 | IN UINT8 BusDevAddr\r | |
92870c98 | 1127 | );\r |
1128 | \r | |
1129 | /**\r | |
1130 | Assign and initialize the device slot for a new device.\r | |
1131 | \r | |
a9292c13 | 1132 | @param Xhc The XHCI Instance.\r |
92870c98 | 1133 | @param ParentRouteChart The route string pointed to the parent device.\r |
1134 | @param ParentPort The port at which the device is located.\r | |
1135 | @param RouteChart The route string pointed to the device.\r | |
1136 | @param DeviceSpeed The device speed.\r | |
1137 | \r | |
1138 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1139 | \r | |
1140 | **/\r | |
1141 | EFI_STATUS\r | |
1142 | EFIAPI\r | |
1143 | XhcInitializeDeviceSlot (\r | |
a9292c13 | 1144 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1145 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1146 | IN UINT16 ParentPort,\r | |
1147 | IN USB_DEV_ROUTE RouteChart,\r | |
1148 | IN UINT8 DeviceSpeed\r | |
1149 | );\r | |
1150 | \r | |
6b4483cd | 1151 | /**\r |
1152 | Assign and initialize the device slot for a new device.\r | |
1153 | \r | |
1154 | @param Xhc The XHCI Instance.\r | |
1155 | @param ParentRouteChart The route string pointed to the parent device.\r | |
1156 | @param ParentPort The port at which the device is located.\r | |
1157 | @param RouteChart The route string pointed to the device.\r | |
1158 | @param DeviceSpeed The device speed.\r | |
1159 | \r | |
1160 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1161 | \r | |
1162 | **/\r | |
1163 | EFI_STATUS\r | |
1164 | EFIAPI\r | |
1165 | XhcInitializeDeviceSlot64 (\r | |
1166 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1167 | IN USB_DEV_ROUTE ParentRouteChart,\r | |
1168 | IN UINT16 ParentPort,\r | |
1169 | IN USB_DEV_ROUTE RouteChart,\r | |
1170 | IN UINT8 DeviceSpeed\r | |
1171 | );\r | |
1172 | \r | |
92870c98 | 1173 | /**\r |
1174 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1175 | \r | |
a9292c13 | 1176 | @param Xhc The XHCI Instance.\r |
92870c98 | 1177 | @param SlotId The slot id to be evaluated.\r |
1178 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1179 | \r | |
1180 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1181 | \r | |
1182 | **/\r | |
1183 | EFI_STATUS\r | |
1184 | EFIAPI\r | |
1185 | XhcEvaluateContext (\r | |
a9292c13 | 1186 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1187 | IN UINT8 SlotId,\r |
1188 | IN UINT32 MaxPacketSize\r | |
1189 | );\r | |
1190 | \r | |
6b4483cd | 1191 | \r |
1192 | /**\r | |
1193 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1194 | \r | |
1195 | @param Xhc The XHCI Instance.\r | |
1196 | @param SlotId The slot id to be evaluated.\r | |
1197 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1198 | \r | |
1199 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1200 | \r | |
1201 | **/\r | |
1202 | EFI_STATUS\r | |
1203 | EFIAPI\r | |
1204 | XhcEvaluateContext64 (\r | |
1205 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1206 | IN UINT8 SlotId,\r | |
1207 | IN UINT32 MaxPacketSize\r | |
1208 | );\r | |
1209 | \r | |
1210 | \r | |
92870c98 | 1211 | /**\r |
1212 | Disable the specified device slot.\r | |
1213 | \r | |
a9292c13 | 1214 | @param Xhc The XHCI Instance.\r |
92870c98 | 1215 | @param SlotId The slot id to be disabled.\r |
1216 | \r | |
1217 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1218 | \r | |
1219 | **/\r | |
1220 | EFI_STATUS\r | |
1221 | EFIAPI\r | |
1222 | XhcDisableSlotCmd (\r | |
a9292c13 | 1223 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1224 | IN UINT8 SlotId\r |
1225 | );\r | |
1226 | \r | |
6b4483cd | 1227 | \r |
1228 | /**\r | |
1229 | Disable the specified device slot.\r | |
1230 | \r | |
1231 | @param Xhc The XHCI Instance.\r | |
1232 | @param SlotId The slot id to be disabled.\r | |
1233 | \r | |
1234 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1235 | \r | |
1236 | **/\r | |
1237 | EFI_STATUS\r | |
1238 | EFIAPI\r | |
1239 | XhcDisableSlotCmd64 (\r | |
1240 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1241 | IN UINT8 SlotId\r | |
1242 | );\r | |
1243 | \r | |
1244 | \r | |
92870c98 | 1245 | /**\r |
1246 | Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r | |
1247 | \r | |
a9292c13 | 1248 | @param Xhc The XHCI Instance.\r |
92870c98 | 1249 | @param TrsRing The transfer ring to sync.\r |
1250 | \r | |
1251 | @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r | |
1252 | \r | |
1253 | **/\r | |
1254 | EFI_STATUS\r | |
1255 | EFIAPI\r | |
1256 | XhcSyncTrsRing (\r | |
a9292c13 | 1257 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1258 | TRANSFER_RING *TrsRing\r |
1259 | );\r | |
1260 | \r | |
1261 | /**\r | |
1262 | Synchronize the specified event ring to update the enqueue and dequeue pointer.\r | |
1263 | \r | |
a9292c13 | 1264 | @param Xhc The XHCI Instance.\r |
92870c98 | 1265 | @param EvtRing The event ring to sync.\r |
1266 | \r | |
1267 | @retval EFI_SUCCESS The event ring is synchronized successfully.\r | |
1268 | \r | |
1269 | **/\r | |
1270 | EFI_STATUS\r | |
1271 | EFIAPI\r | |
1272 | XhcSyncEventRing (\r | |
a9292c13 | 1273 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1274 | EVENT_RING *EvtRing\r |
1275 | );\r | |
1276 | \r | |
1277 | /**\r | |
1278 | Check if there is a new generated event.\r | |
1279 | \r | |
a9292c13 | 1280 | @param Xhc The XHCI Instance.\r |
92870c98 | 1281 | @param EvtRing The event ring to check.\r |
1282 | @param NewEvtTrb The new event TRB found.\r | |
1283 | \r | |
1284 | @retval EFI_SUCCESS Found a new event TRB at the event ring.\r | |
1285 | @retval EFI_NOT_READY The event ring has no new event.\r | |
1286 | \r | |
1287 | **/\r | |
1288 | EFI_STATUS\r | |
1289 | EFIAPI\r | |
1290 | XhcCheckNewEvent (\r | |
a9292c13 | 1291 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1292 | IN EVENT_RING *EvtRing,\r |
a9292c13 | 1293 | OUT TRB_TEMPLATE **NewEvtTrb\r |
92870c98 | 1294 | );\r |
1295 | \r | |
1296 | /**\r | |
1297 | Create XHCI transfer ring.\r | |
1298 | \r | |
a9292c13 | 1299 | @param Xhc The XHCI Instance.\r |
92870c98 | 1300 | @param TrbNum The number of TRB in the ring.\r |
1301 | @param TransferRing The created transfer ring.\r | |
1302 | \r | |
1303 | **/\r | |
1304 | VOID\r | |
1305 | CreateTransferRing (\r | |
a9292c13 | 1306 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1307 | IN UINTN TrbNum,\r |
1308 | OUT TRANSFER_RING *TransferRing\r | |
1309 | );\r | |
1310 | \r | |
1311 | /**\r | |
1312 | Create XHCI event ring.\r | |
1313 | \r | |
a9292c13 | 1314 | @param Xhc The XHCI Instance.\r |
92870c98 | 1315 | @param EventRing The created event ring.\r |
1316 | \r | |
1317 | **/\r | |
1318 | VOID\r | |
1319 | CreateEventRing (\r | |
a9292c13 | 1320 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1321 | OUT EVENT_RING *EventRing\r |
1322 | );\r | |
1323 | \r | |
1324 | /**\r | |
1325 | System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r | |
1326 | condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r | |
1327 | Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r | |
1328 | reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r | |
1329 | Stopped to the Running state.\r | |
1330 | \r | |
a9292c13 | 1331 | @param Xhc The XHCI Instance.\r |
92870c98 | 1332 | @param Urb The urb which makes the endpoint halted.\r |
1333 | \r | |
1334 | @retval EFI_SUCCESS The recovery is successful.\r | |
1335 | @retval Others Failed to recovery halted endpoint.\r | |
1336 | \r | |
1337 | **/\r | |
1338 | EFI_STATUS\r | |
1339 | EFIAPI\r | |
1340 | XhcRecoverHaltedEndpoint (\r | |
a9292c13 | 1341 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1342 | IN URB *Urb\r |
1343 | );\r | |
1344 | \r | |
12e6c738 FT |
1345 | /**\r |
1346 | System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r | |
1347 | Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r | |
1348 | the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r | |
1349 | state.\r | |
1350 | \r | |
1351 | @param Xhc The XHCI Instance.\r | |
1352 | @param Urb The urb which doesn't get completed in a specified timeout range.\r | |
1353 | \r | |
1354 | @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r | |
1355 | @retval Others Failed to stop the endpoint and dequeue the TDs.\r | |
1356 | \r | |
1357 | **/\r | |
1358 | EFI_STATUS\r | |
1359 | EFIAPI\r | |
1360 | XhcDequeueTrbFromEndpoint (\r | |
1361 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1362 | IN URB *Urb\r | |
1363 | );\r | |
1364 | \r | |
1365 | /**\r | |
1366 | Stop endpoint through XHCI's Stop_Endpoint cmd.\r | |
1367 | \r | |
1368 | @param Xhc The XHCI Instance.\r | |
1369 | @param SlotId The slot id to be configured.\r | |
1370 | @param Dci The device context index of endpoint.\r | |
49be9c3c | 1371 | @param PendingUrb The pending URB to check completion status when stopping the end point.\r |
12e6c738 FT |
1372 | \r |
1373 | @retval EFI_SUCCESS Stop endpoint successfully.\r | |
1374 | @retval Others Failed to stop endpoint.\r | |
1375 | \r | |
1376 | **/\r | |
1377 | EFI_STATUS\r | |
1378 | EFIAPI\r | |
1379 | XhcStopEndpoint (\r | |
1380 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1381 | IN UINT8 SlotId,\r | |
49be9c3c RN |
1382 | IN UINT8 Dci,\r |
1383 | IN URB *PendingUrb OPTIONAL\r | |
12e6c738 FT |
1384 | );\r |
1385 | \r | |
1386 | /**\r | |
1387 | Reset endpoint through XHCI's Reset_Endpoint cmd.\r | |
1388 | \r | |
1389 | @param Xhc The XHCI Instance.\r | |
1390 | @param SlotId The slot id to be configured.\r | |
1391 | @param Dci The device context index of endpoint.\r | |
1392 | \r | |
1393 | @retval EFI_SUCCESS Reset endpoint successfully.\r | |
1394 | @retval Others Failed to reset endpoint.\r | |
1395 | \r | |
1396 | **/\r | |
1397 | EFI_STATUS\r | |
1398 | EFIAPI\r | |
1399 | XhcResetEndpoint (\r | |
1400 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1401 | IN UINT8 SlotId,\r | |
1402 | IN UINT8 Dci\r | |
1403 | );\r | |
1404 | \r | |
1405 | /**\r | |
1406 | Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r | |
1407 | \r | |
1408 | @param Xhc The XHCI Instance.\r | |
1409 | @param SlotId The slot id to be configured.\r | |
1410 | @param Dci The device context index of endpoint.\r | |
1411 | @param Urb The dequeue pointer of the transfer ring specified\r | |
1412 | by the urb to be updated.\r | |
1413 | \r | |
1414 | @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r | |
1415 | @retval Others Failed to set transfer ring dequeue pointer.\r | |
1416 | \r | |
1417 | **/\r | |
1418 | EFI_STATUS\r | |
1419 | EFIAPI\r | |
1420 | XhcSetTrDequeuePointer (\r | |
1421 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1422 | IN UINT8 SlotId,\r | |
1423 | IN UINT8 Dci,\r | |
1424 | IN URB *Urb\r | |
1425 | );\r | |
1426 | \r | |
92870c98 | 1427 | /**\r |
1428 | Create a new URB for a new transaction.\r | |
1429 | \r | |
d98fc9ad SZ |
1430 | @param Xhc The XHCI Instance\r |
1431 | @param DevAddr The device address\r | |
1432 | @param EpAddr Endpoint addrress\r | |
1433 | @param DevSpeed The device speed\r | |
1434 | @param MaxPacket The max packet length of the endpoint\r | |
1435 | @param Type The transaction type\r | |
1436 | @param Request The standard USB request for control transfer\r | |
1437 | @param Data The user data to transfer\r | |
1438 | @param DataLen The length of data buffer\r | |
1439 | @param Callback The function to call when data is transferred\r | |
1440 | @param Context The context to the callback\r | |
92870c98 | 1441 | \r |
1442 | @return Created URB or NULL\r | |
1443 | \r | |
1444 | **/\r | |
1445 | URB*\r | |
1446 | XhcCreateUrb (\r | |
a9292c13 | 1447 | IN USB_XHCI_INSTANCE *Xhc,\r |
d98fc9ad | 1448 | IN UINT8 DevAddr,\r |
92870c98 | 1449 | IN UINT8 EpAddr,\r |
1450 | IN UINT8 DevSpeed,\r | |
1451 | IN UINTN MaxPacket,\r | |
1452 | IN UINTN Type,\r | |
1453 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
1454 | IN VOID *Data,\r | |
1455 | IN UINTN DataLen,\r | |
1456 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
1457 | IN VOID *Context\r | |
1458 | );\r | |
1459 | \r | |
1847ed0b EL |
1460 | /**\r |
1461 | Free an allocated URB.\r | |
1462 | \r | |
1463 | @param Xhc The XHCI device.\r | |
1464 | @param Urb The URB to free.\r | |
1465 | \r | |
1466 | **/\r | |
1467 | VOID\r | |
1468 | XhcFreeUrb (\r | |
1469 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1470 | IN URB *Urb\r | |
1471 | );\r | |
1472 | \r | |
92870c98 | 1473 | /**\r |
1474 | Create a transfer TRB.\r | |
1475 | \r | |
a9292c13 | 1476 | @param Xhc The XHCI Instance\r |
92870c98 | 1477 | @param Urb The urb used to construct the transfer TRB.\r |
1478 | \r | |
1479 | @return Created TRB or NULL\r | |
1480 | \r | |
1481 | **/\r | |
1482 | EFI_STATUS\r | |
1483 | XhcCreateTransferTrb (\r | |
a9292c13 | 1484 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1485 | IN URB *Urb\r |
1486 | );\r | |
1487 | \r | |
1488 | #endif\r |