]>
Commit | Line | Data |
---|---|---|
a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.2 standard.\r | |
3 | \r | |
bc14bdb3 | 4 | This file includes the definitions in the following specifications,\r |
427987f5 | 5 | PCI Local Bus Specification, 2.2\r |
6 | PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r | |
bc14bdb3 | 7 | PC Card Standard, 8.0\r |
3362c5f1 | 8 | PCI Power Management Interface Specifiction, Revision 1.2\r |
bc14bdb3 | 9 | \r |
35a461cb | 10 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r |
3362c5f1 | 11 | Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r |
9df063a0 | 12 | This program and the accompanying materials \r |
a7ed1e2e | 13 | are licensed and made available under the terms and conditions of the BSD License \r |
14 | which accompanies this distribution. The full text of the license may be found at \r | |
15 | http://opensource.org/licenses/bsd-license.php \r | |
16 | \r | |
17 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
18 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
19 | \r | |
a7ed1e2e | 20 | **/\r |
21 | \r | |
42eedea9 | 22 | #ifndef _PCI22_H_\r |
23 | #define _PCI22_H_\r | |
a7ed1e2e | 24 | \r |
a7ed1e2e | 25 | #define PCI_MAX_BUS 255\r |
a7ed1e2e | 26 | #define PCI_MAX_DEVICE 31\r |
27 | #define PCI_MAX_FUNC 7\r | |
28 | \r | |
766f4bc1 | 29 | #pragma pack(1)\r |
427987f5 | 30 | \r |
31 | ///\r | |
32 | /// Common header region in PCI Configuration Space\r | |
33 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
34 | ///\r | |
a7ed1e2e | 35 | typedef struct {\r |
36 | UINT16 VendorId;\r | |
37 | UINT16 DeviceId;\r | |
38 | UINT16 Command;\r | |
39 | UINT16 Status;\r | |
40 | UINT8 RevisionID;\r | |
41 | UINT8 ClassCode[3];\r | |
42 | UINT8 CacheLineSize;\r | |
43 | UINT8 LatencyTimer;\r | |
44 | UINT8 HeaderType;\r | |
45 | UINT8 BIST;\r | |
46 | } PCI_DEVICE_INDEPENDENT_REGION;\r | |
47 | \r | |
427987f5 | 48 | ///\r |
49 | /// PCI Device header region in PCI Configuration Space\r | |
50 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
51 | ///\r | |
a7ed1e2e | 52 | typedef struct {\r |
53 | UINT32 Bar[6];\r | |
54 | UINT32 CISPtr;\r | |
55 | UINT16 SubsystemVendorID;\r | |
56 | UINT16 SubsystemID;\r | |
57 | UINT32 ExpansionRomBar;\r | |
58 | UINT8 CapabilityPtr;\r | |
59 | UINT8 Reserved1[3];\r | |
60 | UINT32 Reserved2;\r | |
61 | UINT8 InterruptLine;\r | |
62 | UINT8 InterruptPin;\r | |
63 | UINT8 MinGnt;\r | |
64 | UINT8 MaxLat;\r | |
65 | } PCI_DEVICE_HEADER_TYPE_REGION;\r | |
66 | \r | |
427987f5 | 67 | ///\r |
68 | /// PCI Device Configuration Space\r | |
69 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
70 | ///\r | |
a7ed1e2e | 71 | typedef struct {\r |
72 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
73 | PCI_DEVICE_HEADER_TYPE_REGION Device;\r | |
74 | } PCI_TYPE00;\r | |
75 | \r | |
bc14bdb3 | 76 | ///\r |
427987f5 | 77 | /// PCI-PCI Bridge header region in PCI Configuration Space\r |
78 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
bc14bdb3 | 79 | ///\r |
a7ed1e2e | 80 | typedef struct {\r |
81 | UINT32 Bar[2];\r | |
82 | UINT8 PrimaryBus;\r | |
83 | UINT8 SecondaryBus;\r | |
84 | UINT8 SubordinateBus;\r | |
85 | UINT8 SecondaryLatencyTimer;\r | |
86 | UINT8 IoBase;\r | |
87 | UINT8 IoLimit;\r | |
88 | UINT16 SecondaryStatus;\r | |
89 | UINT16 MemoryBase;\r | |
90 | UINT16 MemoryLimit;\r | |
91 | UINT16 PrefetchableMemoryBase;\r | |
92 | UINT16 PrefetchableMemoryLimit;\r | |
93 | UINT32 PrefetchableBaseUpper32;\r | |
94 | UINT32 PrefetchableLimitUpper32;\r | |
95 | UINT16 IoBaseUpper16;\r | |
96 | UINT16 IoLimitUpper16;\r | |
97 | UINT8 CapabilityPtr;\r | |
98 | UINT8 Reserved[3];\r | |
99 | UINT32 ExpansionRomBAR;\r | |
100 | UINT8 InterruptLine;\r | |
101 | UINT8 InterruptPin;\r | |
102 | UINT16 BridgeControl;\r | |
103 | } PCI_BRIDGE_CONTROL_REGISTER;\r | |
104 | \r | |
427987f5 | 105 | ///\r |
106 | /// PCI-to-PCI Bridge Configuration Space\r | |
107 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
108 | ///\r | |
a7ed1e2e | 109 | typedef struct {\r |
110 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
111 | PCI_BRIDGE_CONTROL_REGISTER Bridge;\r | |
112 | } PCI_TYPE01;\r | |
113 | \r | |
114 | typedef union {\r | |
115 | PCI_TYPE00 Device;\r | |
116 | PCI_TYPE01 Bridge;\r | |
117 | } PCI_TYPE_GENERIC;\r | |
118 | \r | |
bc14bdb3 | 119 | /// \r |
427987f5 | 120 | /// CardBus Conroller Configuration Space, \r |
121 | /// Section 4.5.1, PC Card Standard. 8.0\r | |
bc14bdb3 | 122 | ///\r |
a7ed1e2e | 123 | typedef struct {\r |
bc14bdb3 | 124 | UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r |
125 | UINT8 Cap_Ptr;\r | |
126 | UINT8 Reserved;\r | |
127 | UINT16 SecondaryStatus; ///< Secondary Status\r | |
128 | UINT8 PciBusNumber; ///< PCI Bus Number\r | |
129 | UINT8 CardBusBusNumber; ///< CardBus Bus Number\r | |
130 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r | |
131 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r | |
132 | UINT32 MemoryBase0; ///< Memory Base Register 0\r | |
133 | UINT32 MemoryLimit0; ///< Memory Limit Register 0\r | |
a7ed1e2e | 134 | UINT32 MemoryBase1;\r |
135 | UINT32 MemoryLimit1;\r | |
136 | UINT32 IoBase0;\r | |
bc14bdb3 | 137 | UINT32 IoLimit0; ///< I/O Base Register 0\r |
138 | UINT32 IoBase1; ///< I/O Limit Register 0\r | |
a7ed1e2e | 139 | UINT32 IoLimit1;\r |
bc14bdb3 | 140 | UINT8 InterruptLine; ///< Interrupt Line\r |
141 | UINT8 InterruptPin; ///< Interrupt Pin\r | |
142 | UINT16 BridgeControl; ///< Bridge Control\r | |
a7ed1e2e | 143 | } PCI_CARDBUS_CONTROL_REGISTER;\r |
144 | \r | |
a2461f6b | 145 | //\r |
146 | // Definitions of PCI class bytes and manipulation macros.\r | |
147 | //\r | |
a7ed1e2e | 148 | #define PCI_CLASS_OLD 0x00\r |
bc14bdb3 | 149 | #define PCI_CLASS_OLD_OTHER 0x00\r |
150 | #define PCI_CLASS_OLD_VGA 0x01\r | |
a7ed1e2e | 151 | \r |
152 | #define PCI_CLASS_MASS_STORAGE 0x01\r | |
bc14bdb3 | 153 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r |
154 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01\r | |
155 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r | |
156 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03\r | |
157 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04\r | |
158 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r | |
a7ed1e2e | 159 | \r |
160 | #define PCI_CLASS_NETWORK 0x02\r | |
bc14bdb3 | 161 | #define PCI_CLASS_NETWORK_ETHERNET 0x00 \r |
162 | #define PCI_CLASS_NETWORK_TOKENRING 0x01\r | |
163 | #define PCI_CLASS_NETWORK_FDDI 0x02\r | |
164 | #define PCI_CLASS_NETWORK_ATM 0x03\r | |
165 | #define PCI_CLASS_NETWORK_ISDN 0x04\r | |
166 | #define PCI_CLASS_NETWORK_OTHER 0x80\r | |
a7ed1e2e | 167 | \r |
168 | #define PCI_CLASS_DISPLAY 0x03\r | |
bc14bdb3 | 169 | #define PCI_CLASS_DISPLAY_VGA 0x00\r |
170 | #define PCI_IF_VGA_VGA 0x00\r | |
171 | #define PCI_IF_VGA_8514 0x01\r | |
172 | #define PCI_CLASS_DISPLAY_XGA 0x01\r | |
173 | #define PCI_CLASS_DISPLAY_3D 0x02\r | |
174 | #define PCI_CLASS_DISPLAY_OTHER 0x80 \r | |
bc14bdb3 | 175 | \r |
176 | #define PCI_CLASS_MEDIA 0x04\r | |
177 | #define PCI_CLASS_MEDIA_VIDEO 0x00\r | |
178 | #define PCI_CLASS_MEDIA_AUDIO 0x01\r | |
179 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02\r | |
180 | #define PCI_CLASS_MEDIA_OTHER 0x80\r | |
181 | \r | |
182 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05\r | |
183 | #define PCI_CLASS_MEMORY_RAM 0x00\r | |
184 | #define PCI_CLASS_MEMORY_FLASH 0x01\r | |
185 | #define PCI_CLASS_MEMORY_OTHER 0x80\r | |
186 | \r | |
a7ed1e2e | 187 | #define PCI_CLASS_BRIDGE 0x06\r |
bc14bdb3 | 188 | #define PCI_CLASS_BRIDGE_HOST 0x00\r |
189 | #define PCI_CLASS_BRIDGE_ISA 0x01\r | |
190 | #define PCI_CLASS_BRIDGE_EISA 0x02\r | |
191 | #define PCI_CLASS_BRIDGE_MCA 0x03\r | |
192 | #define PCI_CLASS_BRIDGE_P2P 0x04\r | |
193 | #define PCI_IF_BRIDGE_P2P 0x00\r | |
194 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r | |
195 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05\r | |
196 | #define PCI_CLASS_BRIDGE_NUBUS 0x06\r | |
197 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07\r | |
198 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08\r | |
199 | #define PCI_CLASS_BRIDGE_OTHER 0x80\r | |
200 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r | |
201 | \r | |
202 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r | |
203 | #define PCI_SUBCLASS_SERIAL 0x00\r | |
204 | #define PCI_IF_GENERIC_XT 0x00\r | |
205 | #define PCI_IF_16450 0x01\r | |
206 | #define PCI_IF_16550 0x02\r | |
207 | #define PCI_IF_16650 0x03\r | |
208 | #define PCI_IF_16750 0x04\r | |
209 | #define PCI_IF_16850 0x05\r | |
210 | #define PCI_IF_16950 0x06\r | |
211 | #define PCI_SUBCLASS_PARALLEL 0x01\r | |
212 | #define PCI_IF_PARALLEL_PORT 0x00\r | |
213 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r | |
214 | #define PCI_IF_ECP_PARALLEL_PORT 0x02\r | |
215 | #define PCI_IF_1284_CONTROLLER 0x03\r | |
216 | #define PCI_IF_1284_DEVICE 0xFE\r | |
217 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r | |
218 | #define PCI_SUBCLASS_MODEM 0x03\r | |
219 | #define PCI_IF_GENERIC_MODEM 0x00\r | |
220 | #define PCI_IF_16450_MODEM 0x01\r | |
221 | #define PCI_IF_16550_MODEM 0x02\r | |
222 | #define PCI_IF_16650_MODEM 0x03\r | |
223 | #define PCI_IF_16750_MODEM 0x04\r | |
826a66d4 | 224 | #define PCI_SUBCLASS_SCC_OTHER 0x80\r |
a7ed1e2e | 225 | \r |
226 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r | |
bc14bdb3 | 227 | #define PCI_SUBCLASS_PIC 0x00\r |
228 | #define PCI_IF_8259_PIC 0x00\r | |
229 | #define PCI_IF_ISA_PIC 0x01\r | |
230 | #define PCI_IF_EISA_PIC 0x02\r | |
231 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r | |
232 | #define PCI_IF_APIC_CONTROLLER2 0x20 \r | |
233 | #define PCI_SUBCLASS_DMA 0x01\r | |
234 | #define PCI_IF_8237_DMA 0x00\r | |
235 | #define PCI_IF_ISA_DMA 0x01\r | |
236 | #define PCI_IF_EISA_DMA 0x02\r | |
237 | #define PCI_SUBCLASS_TIMER 0x02\r | |
238 | #define PCI_IF_8254_TIMER 0x00\r | |
239 | #define PCI_IF_ISA_TIMER 0x01\r | |
240 | #define PCI_IF_EISA_TIMER 0x02\r | |
241 | #define PCI_SUBCLASS_RTC 0x03\r | |
242 | #define PCI_IF_GENERIC_RTC 0x00\r | |
826a66d4 | 243 | #define PCI_IF_ISA_RTC 0x01\r |
bc14bdb3 | 244 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r |
245 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r | |
a7ed1e2e | 246 | \r |
247 | #define PCI_CLASS_INPUT_DEVICE 0x09\r | |
bc14bdb3 | 248 | #define PCI_SUBCLASS_KEYBOARD 0x00\r |
249 | #define PCI_SUBCLASS_PEN 0x01\r | |
250 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r | |
251 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r | |
252 | #define PCI_SUBCLASS_GAMEPORT 0x04\r | |
253 | #define PCI_IF_GAMEPORT 0x00\r | |
826a66d4 | 254 | #define PCI_IF_GAMEPORT1 0x10\r |
bc14bdb3 | 255 | #define PCI_SUBCLASS_INPUT_OTHER 0x80\r |
a7ed1e2e | 256 | \r |
257 | #define PCI_CLASS_DOCKING_STATION 0x0A\r | |
826a66d4 RN |
258 | #define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r |
259 | #define PCI_SUBCLASS_DOCKING_OTHER 0x80\r | |
a7ed1e2e | 260 | \r |
261 | #define PCI_CLASS_PROCESSOR 0x0B\r | |
bc14bdb3 | 262 | #define PCI_SUBCLASS_PROC_386 0x00\r |
263 | #define PCI_SUBCLASS_PROC_486 0x01\r | |
264 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02\r | |
265 | #define PCI_SUBCLASS_PROC_ALPHA 0x10\r | |
266 | #define PCI_SUBCLASS_PROC_POWERPC 0x20\r | |
267 | #define PCI_SUBCLASS_PROC_MIPS 0x30\r | |
268 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r | |
a7ed1e2e | 269 | \r |
270 | #define PCI_CLASS_SERIAL 0x0C\r | |
bc14bdb3 | 271 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00\r |
272 | #define PCI_IF_1394 0x00\r | |
273 | #define PCI_IF_1394_OPEN_HCI 0x10\r | |
274 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r | |
275 | #define PCI_CLASS_SERIAL_SSA 0x02\r | |
276 | #define PCI_CLASS_SERIAL_USB 0x03\r | |
277 | #define PCI_IF_UHCI 0x00\r | |
278 | #define PCI_IF_OHCI 0x10\r | |
279 | #define PCI_IF_USB_OTHER 0x80\r | |
280 | #define PCI_IF_USB_DEVICE 0xFE\r | |
281 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r | |
282 | #define PCI_CLASS_SERIAL_SMB 0x05\r | |
a7ed1e2e | 283 | \r |
284 | #define PCI_CLASS_WIRELESS 0x0D\r | |
bc14bdb3 | 285 | #define PCI_SUBCLASS_IRDA 0x00\r |
286 | #define PCI_SUBCLASS_IR 0x01\r | |
826a66d4 | 287 | #define PCI_SUBCLASS_RF 0x10\r |
bc14bdb3 | 288 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r |
a7ed1e2e | 289 | \r |
290 | #define PCI_CLASS_INTELLIGENT_IO 0x0E\r | |
291 | \r | |
292 | #define PCI_CLASS_SATELLITE 0x0F\r | |
bc14bdb3 | 293 | #define PCI_SUBCLASS_TV 0x01\r |
294 | #define PCI_SUBCLASS_AUDIO 0x02\r | |
295 | #define PCI_SUBCLASS_VOICE 0x03\r | |
296 | #define PCI_SUBCLASS_DATA 0x04\r | |
a7ed1e2e | 297 | \r |
bc14bdb3 | 298 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r |
299 | #define PCI_SUBCLASS_NET_COMPUT 0x00\r | |
300 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r | |
301 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80\r | |
a7ed1e2e | 302 | \r |
303 | #define PCI_CLASS_DPIO 0x11\r | |
bc14bdb3 | 304 | #define PCI_SUBCLASS_DPIO 0x00\r |
305 | #define PCI_SUBCLASS_DPIO_OTHER 0x80\r | |
a7ed1e2e | 306 | \r |
1833218d | 307 | /** \r |
308 | Macro that checks whether the Base Class code of device matched.\r | |
309 | \r | |
310 | @param _p Specified device.\r | |
311 | @param c Base Class code needs matching.\r | |
312 | \r | |
313 | @retval TRUE Base Class code matches the specified device.\r | |
314 | @retval FALSE Base Class code doesn't match the specified device. \r | |
315 | \r | |
316 | **/\r | |
a7ed1e2e | 317 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r |
1833218d | 318 | /** \r |
319 | Macro that checks whether the Base Class code and Sub-Class code of device matched.\r | |
320 | \r | |
321 | @param _p Specified device.\r | |
322 | @param c Base Class code needs matching.\r | |
323 | @param s Sub-Class code needs matching.\r | |
324 | \r | |
325 | @retval TRUE Base Class code and Sub-Class code match the specified device.\r | |
326 | @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r | |
327 | \r | |
328 | **/\r | |
a7ed1e2e | 329 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r |
1833218d | 330 | /** \r |
331 | Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r | |
332 | \r | |
333 | @param _p Specified device.\r | |
334 | @param c Base Class code needs matching.\r | |
335 | @param s Sub-Class code needs matching.\r | |
336 | @param p Interface code needs matching.\r | |
337 | \r | |
338 | @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r | |
339 | @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r | |
340 | \r | |
341 | **/\r | |
a7ed1e2e | 342 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r |
343 | \r | |
1833218d | 344 | /** \r |
345 | Macro that checks whether device is a display controller.\r | |
346 | \r | |
347 | @param _p Specified device.\r | |
348 | \r | |
349 | @retval TRUE Device is a display controller.\r | |
350 | @retval FALSE Device is not a display controller.\r | |
351 | \r | |
352 | **/\r | |
a7ed1e2e | 353 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r |
1833218d | 354 | /** \r |
355 | Macro that checks whether device is a VGA-compatible controller.\r | |
356 | \r | |
357 | @param _p Specified device.\r | |
358 | \r | |
359 | @retval TRUE Device is a VGA-compatible controller.\r | |
360 | @retval FALSE Device is not a VGA-compatible controller.\r | |
361 | \r | |
362 | **/\r | |
363 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r | |
364 | /** \r | |
365 | Macro that checks whether device is an 8514-compatible controller.\r | |
366 | \r | |
367 | @param _p Specified device.\r | |
368 | \r | |
369 | @retval TRUE Device is an 8514-compatible controller.\r | |
370 | @retval FALSE Device is not an 8514-compatible controller.\r | |
371 | \r | |
372 | **/\r | |
373 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r | |
374 | /** \r | |
375 | Macro that checks whether device is built before the Class Code field was defined.\r | |
376 | \r | |
377 | @param _p Specified device.\r | |
378 | \r | |
379 | @retval TRUE Device is an old device.\r | |
380 | @retval FALSE Device is not an old device.\r | |
381 | \r | |
382 | **/\r | |
a7ed1e2e | 383 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r |
1833218d | 384 | /** \r |
385 | Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r | |
386 | \r | |
387 | @param _p Specified device.\r | |
388 | \r | |
389 | @retval TRUE Device is an old VGA-compatible device.\r | |
390 | @retval FALSE Device is not an old VGA-compatible device.\r | |
391 | \r | |
392 | **/\r | |
a7ed1e2e | 393 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r |
1833218d | 394 | /** \r |
395 | Macro that checks whether device is an IDE controller.\r | |
396 | \r | |
397 | @param _p Specified device.\r | |
398 | \r | |
399 | @retval TRUE Device is an IDE controller.\r | |
400 | @retval FALSE Device is not an IDE controller.\r | |
401 | \r | |
402 | **/\r | |
a7ed1e2e | 403 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r |
1833218d | 404 | /** \r |
405 | Macro that checks whether device is a SCSI bus controller.\r | |
406 | \r | |
407 | @param _p Specified device.\r | |
408 | \r | |
409 | @retval TRUE Device is a SCSI bus controller.\r | |
410 | @retval FALSE Device is not a SCSI bus controller.\r | |
411 | \r | |
412 | **/\r | |
413 | #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r | |
414 | /** \r | |
415 | Macro that checks whether device is a RAID controller.\r | |
416 | \r | |
417 | @param _p Specified device.\r | |
418 | \r | |
419 | @retval TRUE Device is a RAID controller.\r | |
420 | @retval FALSE Device is not a RAID controller.\r | |
421 | \r | |
422 | **/\r | |
423 | #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r | |
424 | /** \r | |
425 | Macro that checks whether device is an ISA bridge.\r | |
426 | \r | |
427 | @param _p Specified device.\r | |
428 | \r | |
429 | @retval TRUE Device is an ISA bridge.\r | |
430 | @retval FALSE Device is not an ISA bridge.\r | |
431 | \r | |
432 | **/\r | |
433 | #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r | |
434 | /** \r | |
435 | Macro that checks whether device is a PCI-to-PCI bridge.\r | |
436 | \r | |
437 | @param _p Specified device.\r | |
438 | \r | |
439 | @retval TRUE Device is a PCI-to-PCI bridge.\r | |
440 | @retval FALSE Device is not a PCI-to-PCI bridge.\r | |
441 | \r | |
442 | **/\r | |
443 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r | |
444 | /** \r | |
445 | Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r | |
446 | \r | |
447 | @param _p Specified device.\r | |
448 | \r | |
449 | @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r | |
450 | @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r | |
451 | \r | |
452 | **/\r | |
453 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r | |
454 | /** \r | |
455 | Macro that checks whether device is a 16550-compatible serial controller.\r | |
456 | \r | |
457 | @param _p Specified device.\r | |
458 | \r | |
459 | @retval TRUE Device is a 16550-compatible serial controller.\r | |
460 | @retval FALSE Device is not a 16550-compatible serial controller.\r | |
461 | \r | |
462 | **/\r | |
a7ed1e2e | 463 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r |
1833218d | 464 | /** \r |
465 | Macro that checks whether device is a Universal Serial Bus controller.\r | |
466 | \r | |
467 | @param _p Specified device.\r | |
468 | \r | |
469 | @retval TRUE Device is a Universal Serial Bus controller.\r | |
470 | @retval FALSE Device is not a Universal Serial Bus controller.\r | |
471 | \r | |
472 | **/\r | |
a7ed1e2e | 473 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r |
474 | \r | |
bc14bdb3 | 475 | //\r |
476 | // the definition of Header Type \r | |
477 | //\r | |
a7ed1e2e | 478 | #define HEADER_TYPE_DEVICE 0x00\r |
479 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r | |
480 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r | |
a7ed1e2e | 481 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r |
bc14bdb3 | 482 | //\r |
483 | // Mask of Header type\r | |
484 | //\r | |
a7ed1e2e | 485 | #define HEADER_LAYOUT_CODE 0x7f\r |
1833218d | 486 | /** \r |
487 | Macro that checks whether device is a PCI-PCI bridge.\r | |
488 | \r | |
489 | @param _p Specified device.\r | |
490 | \r | |
491 | @retval TRUE Device is a PCI-PCI bridge.\r | |
492 | @retval FALSE Device is not a PCI-PCI bridge.\r | |
a7ed1e2e | 493 | \r |
1833218d | 494 | **/\r |
a7ed1e2e | 495 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r |
1833218d | 496 | /** \r |
497 | Macro that checks whether device is a CardBus bridge.\r | |
498 | \r | |
499 | @param _p Specified device.\r | |
500 | \r | |
501 | @retval TRUE Device is a CardBus bridge.\r | |
502 | @retval FALSE Device is not a CardBus bridge.\r | |
503 | \r | |
504 | **/\r | |
a7ed1e2e | 505 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r |
1833218d | 506 | /** \r |
507 | Macro that checks whether device is a multiple functions device.\r | |
508 | \r | |
509 | @param _p Specified device.\r | |
510 | \r | |
511 | @retval TRUE Device is a multiple functions device.\r | |
512 | @retval FALSE Device is not a multiple functions device.\r | |
513 | \r | |
514 | **/\r | |
a7ed1e2e | 515 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r |
516 | \r | |
bc14bdb3 | 517 | ///\r |
518 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r | |
519 | ///\r | |
a7ed1e2e | 520 | #define PCI_BRIDGE_ROMBAR 0x38\r |
521 | \r | |
522 | #define PCI_MAX_BAR 0x0006\r | |
523 | #define PCI_MAX_CONFIG_OFFSET 0x0100\r | |
524 | \r | |
525 | #define PCI_VENDOR_ID_OFFSET 0x00\r | |
526 | #define PCI_DEVICE_ID_OFFSET 0x02\r | |
527 | #define PCI_COMMAND_OFFSET 0x04\r | |
528 | #define PCI_PRIMARY_STATUS_OFFSET 0x06\r | |
529 | #define PCI_REVISION_ID_OFFSET 0x08\r | |
530 | #define PCI_CLASSCODE_OFFSET 0x09\r | |
531 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C\r | |
532 | #define PCI_LATENCY_TIMER_OFFSET 0x0D\r | |
533 | #define PCI_HEADER_TYPE_OFFSET 0x0E\r | |
534 | #define PCI_BIST_OFFSET 0x0F\r | |
535 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10\r | |
536 | #define PCI_CARDBUS_CIS_OFFSET 0x28\r | |
bc14bdb3 | 537 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r |
a7ed1e2e | 538 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r |
bc14bdb3 | 539 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r |
a7ed1e2e | 540 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r |
541 | #define PCI_EXPANSION_ROM_BASE 0x30\r | |
542 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34\r | |
bc14bdb3 | 543 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r |
544 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r | |
545 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r | |
546 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r | |
a7ed1e2e | 547 | \r |
a2461f6b | 548 | //\r |
549 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
550 | //\r | |
bc14bdb3 | 551 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r |
552 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r | |
553 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r | |
0e8768b6 | 554 | #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r |
bc14bdb3 | 555 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r |
556 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r | |
a7ed1e2e | 557 | \r |
bc14bdb3 | 558 | ///\r |
559 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r | |
560 | ///\r | |
a7ed1e2e | 561 | #define PCI_INT_LINE_UNKNOWN 0xFF \r |
562 | \r | |
1833218d | 563 | ///\r |
564 | /// PCI Access Data Format\r | |
565 | ///\r | |
a7ed1e2e | 566 | typedef union {\r |
567 | struct {\r | |
568 | UINT32 Reg : 8;\r | |
569 | UINT32 Func : 3;\r | |
570 | UINT32 Dev : 5;\r | |
571 | UINT32 Bus : 8;\r | |
572 | UINT32 Reserved : 7;\r | |
573 | UINT32 Enable : 1;\r | |
574 | } Bits;\r | |
575 | UINT32 Uint32;\r | |
576 | } PCI_CONFIG_ACCESS_CF8;\r | |
577 | \r | |
766f4bc1 | 578 | #pragma pack()\r |
579 | \r | |
bc14bdb3 | 580 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r |
581 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r | |
582 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r | |
583 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r | |
584 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r | |
585 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r | |
586 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r | |
587 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r | |
588 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r | |
589 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r | |
a7ed1e2e | 590 | \r |
a2461f6b | 591 | //\r |
592 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
593 | //\r | |
bc14bdb3 | 594 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r |
595 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r | |
596 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r | |
597 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r | |
598 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r | |
599 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r | |
600 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r | |
601 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r | |
602 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r | |
603 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r | |
604 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r | |
605 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r | |
606 | \r | |
a2461f6b | 607 | //\r |
608 | // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r | |
609 | //\r | |
bc14bdb3 | 610 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r |
611 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r | |
612 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r | |
613 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r | |
a7ed1e2e | 614 | \r |
615 | //\r | |
616 | // Following are the PCI status control bit\r | |
617 | //\r | |
bc14bdb3 | 618 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r |
619 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r | |
620 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r | |
621 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r | |
a7ed1e2e | 622 | \r |
bc14bdb3 | 623 | ///\r |
624 | /// defined in PC Card Standard\r | |
625 | ///\r | |
a7ed1e2e | 626 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r |
627 | \r | |
766f4bc1 | 628 | #pragma pack(1)\r |
a7ed1e2e | 629 | //\r |
630 | // PCI Capability List IDs and records\r | |
631 | //\r | |
632 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01\r | |
633 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02\r | |
634 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03\r | |
635 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r | |
636 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05\r | |
637 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r | |
12e6f4f1 | 638 | #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r |
a2461f6b | 639 | \r |
427987f5 | 640 | ///\r |
641 | /// Capabilities List Header\r | |
642 | /// Section 6.7, PCI Local Bus Specification, 2.2\r | |
643 | ///\r | |
a7ed1e2e | 644 | typedef struct {\r |
645 | UINT8 CapabilityID;\r | |
646 | UINT8 NextItemPtr;\r | |
647 | } EFI_PCI_CAPABILITY_HDR;\r | |
648 | \r | |
f0aa06e3 SEHM |
649 | ///\r |
650 | /// PMC - Power Management Capabilities\r | |
651 | /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r | |
652 | ///\r | |
653 | typedef union {\r | |
654 | struct {\r | |
655 | UINT16 Version : 3;\r | |
656 | UINT16 PmeClock : 1;\r | |
3362c5f1 | 657 | UINT16 Reserved : 1;\r |
f0aa06e3 SEHM |
658 | UINT16 DeviceSpecificInitialization : 1;\r |
659 | UINT16 AuxCurrent : 3;\r | |
660 | UINT16 D1Support : 1;\r | |
661 | UINT16 D2Support : 1;\r | |
662 | UINT16 PmeSupport : 5;\r | |
663 | } Bits;\r | |
664 | UINT16 Data;\r | |
665 | } EFI_PCI_PMC;\r | |
666 | \r | |
667 | #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r | |
668 | \r | |
669 | ///\r | |
670 | /// PMCSR - Power Management Control/Status\r | |
671 | /// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r | |
672 | ///\r | |
673 | typedef union {\r | |
674 | struct {\r | |
675 | UINT16 PowerState : 2;\r | |
cbedba86 RN |
676 | UINT16 ReservedForPciExpress : 1;\r |
677 | UINT16 NoSoftReset : 1;\r | |
678 | UINT16 Reserved : 4;\r | |
f0aa06e3 SEHM |
679 | UINT16 PmeEnable : 1;\r |
680 | UINT16 DataSelect : 4;\r | |
681 | UINT16 DataScale : 2;\r | |
682 | UINT16 PmeStatus : 1;\r | |
683 | } Bits;\r | |
684 | UINT16 Data;\r | |
685 | } EFI_PCI_PMCSR;\r | |
686 | \r | |
cbedba86 RN |
687 | #define PCI_POWER_STATE_D0 0\r |
688 | #define PCI_POWER_STATE_D1 1\r | |
689 | #define PCI_POWER_STATE_D2 2\r | |
690 | #define PCI_POWER_STATE_D3_HOT 3\r | |
691 | \r | |
692 | ///\r | |
693 | /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r | |
694 | /// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r | |
695 | ///\r | |
696 | typedef union {\r | |
697 | struct {\r | |
698 | UINT8 Reserved : 6;\r | |
699 | UINT8 B2B3 : 1;\r | |
700 | UINT8 BusPowerClockControl : 1;\r | |
701 | } Bits;\r | |
702 | UINT8 Uint8;\r | |
703 | } EFI_PCI_PMCSR_BSE;\r | |
704 | \r | |
705 | ///\r | |
706 | /// Power Management Register Block Definition\r | |
707 | /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r | |
708 | ///\r | |
709 | typedef struct {\r | |
710 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
711 | EFI_PCI_PMC PMC;\r | |
712 | EFI_PCI_PMCSR PMCSR;\r | |
713 | EFI_PCI_PMCSR_BSE BridgeExtention;\r | |
714 | UINT8 Data;\r | |
715 | } EFI_PCI_CAPABILITY_PMI;\r | |
716 | \r | |
1bc5d021 | 717 | ///\r |
427987f5 | 718 | /// A.G.P Capability\r |
719 | /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r | |
1bc5d021 | 720 | ///\r |
a7ed1e2e | 721 | typedef struct {\r |
722 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
723 | UINT8 Rev;\r | |
724 | UINT8 Reserved;\r | |
725 | UINT32 Status;\r | |
726 | UINT32 Command;\r | |
727 | } EFI_PCI_CAPABILITY_AGP;\r | |
728 | \r | |
1bc5d021 | 729 | ///\r |
427987f5 | 730 | /// VPD Capability Structure\r |
731 | /// Appendix I, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 732 | ///\r |
a7ed1e2e | 733 | typedef struct {\r |
734 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
735 | UINT16 AddrReg;\r | |
736 | UINT32 DataReg;\r | |
737 | } EFI_PCI_CAPABILITY_VPD;\r | |
738 | \r | |
1bc5d021 | 739 | ///\r |
427987f5 | 740 | /// Slot Numbering Capabilities Register\r |
741 | /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r | |
1bc5d021 | 742 | ///\r |
a7ed1e2e | 743 | typedef struct {\r |
744 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
745 | UINT8 ExpnsSlotReg;\r | |
746 | UINT8 ChassisNo;\r | |
747 | } EFI_PCI_CAPABILITY_SLOTID;\r | |
748 | \r | |
1bc5d021 | 749 | ///\r |
427987f5 | 750 | /// Message Capability Structure for 32-bit Message Address\r |
751 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 752 | ///\r |
a7ed1e2e | 753 | typedef struct {\r |
754 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
755 | UINT16 MsgCtrlReg;\r | |
756 | UINT32 MsgAddrReg;\r | |
757 | UINT16 MsgDataReg;\r | |
758 | } EFI_PCI_CAPABILITY_MSI32;\r | |
759 | \r | |
427987f5 | 760 | ///\r |
761 | /// Message Capability Structure for 64-bit Message Address\r | |
762 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
763 | ///\r | |
a7ed1e2e | 764 | typedef struct {\r |
765 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
766 | UINT16 MsgCtrlReg;\r | |
767 | UINT32 MsgAddrRegLsdw;\r | |
768 | UINT32 MsgAddrRegMsdw;\r | |
769 | UINT16 MsgDataReg;\r | |
770 | } EFI_PCI_CAPABILITY_MSI64;\r | |
771 | \r | |
1bc5d021 | 772 | ///\r |
427987f5 | 773 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r |
774 | /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r | |
1bc5d021 | 775 | ///\r |
a7ed1e2e | 776 | typedef struct {\r |
777 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
1bc5d021 | 778 | ///\r |
779 | /// not finished - fields need to go here\r | |
780 | ///\r | |
a7ed1e2e | 781 | } EFI_PCI_CAPABILITY_HOTPLUG;\r |
782 | \r | |
a7ed1e2e | 783 | #define PCI_BAR_IDX0 0x00\r |
784 | #define PCI_BAR_IDX1 0x01\r | |
785 | #define PCI_BAR_IDX2 0x02\r | |
786 | #define PCI_BAR_IDX3 0x03\r | |
787 | #define PCI_BAR_IDX4 0x04\r | |
788 | #define PCI_BAR_IDX5 0x05\r | |
a7ed1e2e | 789 | \r |
bc14bdb3 | 790 | ///\r |
791 | /// EFI PCI Option ROM definitions\r | |
792 | /// \r | |
793 | #define EFI_ROOT_BRIDGE_LIST 'eprb' \r | |
794 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r | |
afcf4907 | 795 | \r |
bc14bdb3 | 796 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r |
13c31065 | 797 | #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r |
bc14bdb3 | 798 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r |
a2461f6b | 799 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r |
bc14bdb3 | 800 | \r |
427987f5 | 801 | ///\r |
802 | /// Standard PCI Expansion ROM Header\r | |
803 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
804 | ///\r | |
bc14bdb3 | 805 | typedef struct {\r |
806 | UINT16 Signature; ///< 0xaa55\r | |
807 | UINT8 Reserved[0x16];\r | |
808 | UINT16 PcirOffset;\r | |
809 | } PCI_EXPANSION_ROM_HEADER;\r | |
810 | \r | |
427987f5 | 811 | ///\r |
812 | /// Legacy ROM Header Extensions\r | |
813 | /// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r | |
814 | ///\r | |
bc14bdb3 | 815 | typedef struct {\r |
816 | UINT16 Signature; ///< 0xaa55\r | |
817 | UINT8 Size512;\r | |
818 | UINT8 InitEntryPoint[3];\r | |
819 | UINT8 Reserved[0x12];\r | |
820 | UINT16 PcirOffset;\r | |
821 | } EFI_LEGACY_EXPANSION_ROM_HEADER;\r | |
822 | \r | |
427987f5 | 823 | ///\r |
824 | /// PCI Data Structure Format\r | |
825 | /// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r | |
826 | ///\r | |
bc14bdb3 | 827 | typedef struct {\r |
828 | UINT32 Signature; ///< "PCIR"\r | |
829 | UINT16 VendorId;\r | |
830 | UINT16 DeviceId;\r | |
831 | UINT16 Reserved0;\r | |
832 | UINT16 Length;\r | |
833 | UINT8 Revision;\r | |
834 | UINT8 ClassCode[3];\r | |
835 | UINT16 ImageLength;\r | |
836 | UINT16 CodeRevision;\r | |
837 | UINT8 CodeType;\r | |
838 | UINT8 Indicator;\r | |
839 | UINT16 Reserved1;\r | |
840 | } PCI_DATA_STRUCTURE;\r | |
841 | \r | |
842 | ///\r | |
427987f5 | 843 | /// EFI PCI Expansion ROM Header\r |
844 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
bc14bdb3 | 845 | ///\r |
afcf4907 | 846 | typedef struct {\r |
bc14bdb3 | 847 | UINT16 Signature; ///< 0xaa55\r |
afcf4907 | 848 | UINT16 InitializationSize;\r |
bc14bdb3 | 849 | UINT32 EfiSignature; ///< 0x0EF1\r |
afcf4907 | 850 | UINT16 EfiSubsystem;\r |
851 | UINT16 EfiMachineType;\r | |
852 | UINT16 CompressionType;\r | |
853 | UINT8 Reserved[8];\r | |
854 | UINT16 EfiImageHeaderOffset;\r | |
855 | UINT16 PcirOffset;\r | |
856 | } EFI_PCI_EXPANSION_ROM_HEADER;\r | |
857 | \r | |
858 | typedef union {\r | |
859 | UINT8 *Raw;\r | |
860 | PCI_EXPANSION_ROM_HEADER *Generic;\r | |
861 | EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r | |
862 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r | |
863 | } EFI_PCI_ROM_HEADER;\r | |
864 | \r | |
766f4bc1 | 865 | #pragma pack()\r |
866 | \r | |
a7ed1e2e | 867 | #endif\r |