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7f814ffd | 1 | /** @file\r |
81bc205d | 2 | Abstractions for simple OMAP DMA channel.\r |
3402aac7 | 3 | \r |
7f814ffd | 4 | \r |
5 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
3402aac7 | 6 | \r |
7f814ffd | 7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include <Base.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/OmapDmaLib.h>\r | |
7f814ffd | 20 | #include <Library/IoLib.h>\r |
8e7c9e03 | 21 | #include <Library/BaseMemoryLib.h>\r |
7f814ffd | 22 | #include <Omap3530/Omap3530.h>\r |
23 | \r | |
7f814ffd | 24 | \r |
3402aac7 | 25 | /**\r |
7f814ffd | 26 | Configure OMAP DMA Channel\r |
3402aac7 | 27 | \r |
7f814ffd | 28 | @param Channel DMA Channel to configure\r |
3402aac7 RC |
29 | @param Dma4 Pointer to structure used to initialize DMA registers for the Channel\r |
30 | \r | |
7f814ffd | 31 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r |
32 | @retval EFI_INVALID_PARAMETER Channel is not valid\r | |
33 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r | |
3402aac7 | 34 | \r |
8e7c9e03 | 35 | **/\r |
36 | EFI_STATUS\r | |
37 | EFIAPI\r | |
38 | EnableDmaChannel (\r | |
39 | IN UINTN Channel,\r | |
40 | IN OMAP_DMA4 *DMA4\r | |
41 | )\r | |
42 | {\r | |
43 | UINT32 RegVal;\r | |
44 | \r | |
45 | \r | |
46 | if (Channel > DMA4_MAX_CHANNEL) {\r | |
47 | return EFI_INVALID_PARAMETER;\r | |
48 | }\r | |
49 | \r | |
7f814ffd | 50 | /* 1) Configure the transfer parameters in the logical DMA registers */\r |
51 | /*-------------------------------------------------------------------*/\r | |
52 | \r | |
3402aac7 RC |
53 | /* a) Set the data type CSDP[1:0], the Read/Write Port access type\r |
54 | CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],\r | |
7f814ffd | 55 | write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */\r |
3402aac7 | 56 | \r |
7f814ffd | 57 | // Read CSDP\r |
58 | RegVal = MmioRead32 (DMA4_CSDP (Channel));\r | |
3402aac7 | 59 | \r |
7f814ffd | 60 | // Build reg\r |
61 | RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );\r | |
62 | RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));\r | |
63 | RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));\r | |
64 | RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));\r | |
65 | RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));\r | |
66 | RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));\r | |
67 | RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));\r | |
68 | RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));\r | |
69 | // Write CSDP\r | |
70 | MmioWrite32 (DMA4_CSDP (Channel), RegVal);\r | |
3402aac7 | 71 | \r |
7f814ffd | 72 | /* b) Set the number of element per frame CEN[23:0]*/\r |
73 | MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);\r | |
3402aac7 | 74 | \r |
7f814ffd | 75 | /* c) Set the number of frame per block CFN[15:0]*/\r |
76 | MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);\r | |
3402aac7 | 77 | \r |
7f814ffd | 78 | /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/\r |
79 | MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);\r | |
80 | MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);\r | |
3402aac7 | 81 | \r |
7f814ffd | 82 | /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],\r |
83 | read/write priority CCR[6]/CCR[26]\r | |
3402aac7 | 84 | I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to\r |
7f814ffd | 85 | LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber\r |
86 | */\r | |
3402aac7 | 87 | \r |
7f814ffd | 88 | // Read CCR\r |
89 | RegVal = MmioRead32 (DMA4_CCR (Channel));\r | |
90 | \r | |
91 | // Build reg\r | |
92 | RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber);\r | |
93 | RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);\r | |
94 | RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));\r | |
95 | RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));\r | |
96 | RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6));\r | |
97 | RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));\r | |
3402aac7 | 98 | \r |
7f814ffd | 99 | // Write CCR\r |
100 | MmioWrite32 (DMA4_CCR (Channel), RegVal);\r | |
3402aac7 | 101 | \r |
7f814ffd | 102 | /* f)- Set the source element index CSEI[15:0]*/\r |
103 | MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);\r | |
3402aac7 | 104 | \r |
7f814ffd | 105 | /* - Set the source frame index CSFI[15:0]*/\r |
106 | MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);\r | |
107 | \r | |
108 | \r | |
109 | /* - Set the destination element index CDEI[15:0]*/\r | |
110 | MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);\r | |
111 | \r | |
112 | /* - Set the destination frame index CDFI[31:0]*/\r | |
113 | MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r | |
3402aac7 | 114 | \r |
9f6b977f | 115 | MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r |
116 | \r | |
117 | // Enable all the status bits since we are polling\r | |
118 | MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r | |
119 | MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);\r | |
120 | \r | |
7f814ffd | 121 | /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r |
122 | /*--------------------------------------------------------------*/\r | |
123 | //write enable bit\r | |
8e7c9e03 | 124 | MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer\r |
125 | \r | |
126 | return EFI_SUCCESS;\r | |
127 | }\r | |
128 | \r | |
3402aac7 | 129 | /**\r |
7f814ffd | 130 | Turn of DMA channel configured by EnableDma().\r |
3402aac7 | 131 | \r |
7f814ffd | 132 | @param Channel DMA Channel to configure\r |
9f6b977f | 133 | @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS\r |
134 | @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r | |
3402aac7 | 135 | \r |
7f814ffd | 136 | @retval EFI_SUCCESS DMA hardware disabled\r |
137 | @retval EFI_INVALID_PARAMETER Channel is not valid\r | |
138 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r | |
3402aac7 | 139 | \r |
8e7c9e03 | 140 | **/\r |
141 | EFI_STATUS\r | |
142 | EFIAPI\r | |
143 | DisableDmaChannel (\r | |
144 | IN UINTN Channel,\r | |
145 | IN UINT32 SuccessMask,\r | |
146 | IN UINT32 ErrorMask\r | |
147 | )\r | |
148 | {\r | |
149 | EFI_STATUS Status = EFI_SUCCESS;\r | |
150 | UINT32 Reg;\r | |
151 | \r | |
152 | \r | |
153 | if (Channel > DMA4_MAX_CHANNEL) {\r | |
154 | return EFI_INVALID_PARAMETER;\r | |
155 | }\r | |
156 | \r | |
157 | do {\r | |
158 | Reg = MmioRead32 (DMA4_CSR(Channel));\r | |
159 | if ((Reg & ErrorMask) != 0) {\r | |
160 | Status = EFI_DEVICE_ERROR;\r | |
161 | DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));\r | |
162 | break;\r | |
163 | }\r | |
164 | } while ((Reg & SuccessMask) != SuccessMask);\r | |
165 | \r | |
166 | \r | |
167 | // Disable all status bits and clear them\r | |
9f6b977f | 168 | MmioWrite32 (DMA4_CICR (Channel), 0);\r |
8e7c9e03 | 169 | MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);\r |
170 | \r | |
3402aac7 | 171 | MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));\r |
8e7c9e03 | 172 | return Status;\r |
173 | }\r | |
174 | \r | |
175 | \r | |
176 | \r |