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a47463f2 | 1 | /** @file\r |
7fadaacd | 2 | CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.\r |
a47463f2 | 3 | \r |
7537f8c0 | 4 | Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r |
01a1c0fc | 5 | This program and the accompanying materials\r |
a47463f2 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
430fbbe0 | 15 | #ifndef _CPU_DXE_H_\r |
16 | #define _CPU_DXE_H_\r | |
a47463f2 | 17 | \r |
18 | #include <PiDxe.h>\r | |
19 | \r | |
20 | #include <Protocol/Cpu.h>\r | |
7fadaacd JF |
21 | #include <Protocol/MpService.h>\r |
22 | \r | |
23 | #include <Ppi/SecPlatformInformation.h>\r | |
24 | #include <Ppi/SecPlatformInformation2.h>\r | |
a47463f2 | 25 | \r |
26 | #include <Library/UefiDriverEntryPoint.h>\r | |
27 | #include <Library/UefiBootServicesTableLib.h>\r | |
28 | #include <Library/DxeServicesTableLib.h>\r | |
29 | #include <Library/BaseLib.h>\r | |
30 | #include <Library/CpuLib.h>\r | |
31 | #include <Library/BaseMemoryLib.h>\r | |
32 | #include <Library/MemoryAllocationLib.h>\r | |
33 | #include <Library/DebugLib.h>\r | |
34 | #include <Library/MtrrLib.h>\r | |
d4605c23 | 35 | #include <Library/LocalApicLib.h>\r |
661cab5d | 36 | #include <Library/UefiCpuLib.h>\r |
e41aad15 JF |
37 | #include <Library/UefiLib.h>\r |
38 | #include <Library/CpuExceptionHandlerLib.h>\r | |
7fadaacd JF |
39 | #include <Library/HobLib.h>\r |
40 | #include <Library/ReportStatusCodeLib.h>\r | |
41 | #include <Library/MpInitLib.h>\r | |
7537f8c0 | 42 | #include <Library/TimerLib.h>\r |
7fadaacd | 43 | \r |
32394027 | 44 | #include <Guid/IdleLoopEvent.h>\r |
e41aad15 | 45 | #include <Guid/VectorHandoffTable.h>\r |
a47463f2 | 46 | \r |
47 | #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \\r | |
48 | EFI_MEMORY_WC | \\r | |
49 | EFI_MEMORY_WT | \\r | |
50 | EFI_MEMORY_WB | \\r | |
51 | EFI_MEMORY_UCE \\r | |
52 | )\r | |
53 | \r | |
54 | \r | |
430fbbe0 | 55 | /**\r |
56 | Flush CPU data cache. If the instruction cache is fully coherent\r | |
57 | with all DMA operations then function can just return EFI_SUCCESS.\r | |
58 | \r | |
59 | @param This Protocol instance structure\r | |
60 | @param Start Physical address to start flushing from.\r | |
61 | @param Length Number of bytes to flush. Round up to chipset\r | |
62 | granularity.\r | |
63 | @param FlushType Specifies the type of flush operation to perform.\r | |
64 | \r | |
65 | @retval EFI_SUCCESS If cache was flushed\r | |
66 | @retval EFI_UNSUPPORTED If flush type is not supported.\r | |
67 | @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r | |
68 | \r | |
69 | **/\r | |
a47463f2 | 70 | EFI_STATUS\r |
71 | EFIAPI\r | |
72 | CpuFlushCpuDataCache (\r | |
73 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
74 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
75 | IN UINT64 Length,\r | |
76 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
77 | );\r | |
78 | \r | |
430fbbe0 | 79 | /**\r |
80 | Enables CPU interrupts.\r | |
81 | \r | |
82 | @param This Protocol instance structure\r | |
83 | \r | |
84 | @retval EFI_SUCCESS If interrupts were enabled in the CPU\r | |
85 | @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r | |
86 | \r | |
87 | **/\r | |
a47463f2 | 88 | EFI_STATUS\r |
89 | EFIAPI\r | |
90 | CpuEnableInterrupt (\r | |
91 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
92 | );\r | |
93 | \r | |
430fbbe0 | 94 | /**\r |
95 | Disables CPU interrupts.\r | |
96 | \r | |
97 | @param This Protocol instance structure\r | |
98 | \r | |
99 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
100 | @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r | |
101 | \r | |
102 | **/\r | |
a47463f2 | 103 | EFI_STATUS\r |
104 | EFIAPI\r | |
105 | CpuDisableInterrupt (\r | |
106 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
107 | );\r | |
108 | \r | |
430fbbe0 | 109 | /**\r |
110 | Return the state of interrupts.\r | |
111 | \r | |
112 | @param This Protocol instance structure\r | |
113 | @param State Pointer to the CPU's current interrupt state\r | |
114 | \r | |
115 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
116 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
117 | \r | |
118 | **/\r | |
a47463f2 | 119 | EFI_STATUS\r |
120 | EFIAPI\r | |
121 | CpuGetInterruptState (\r | |
122 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
123 | OUT BOOLEAN *State\r | |
124 | );\r | |
125 | \r | |
430fbbe0 | 126 | /**\r |
127 | Generates an INIT to the CPU.\r | |
128 | \r | |
129 | @param This Protocol instance structure\r | |
130 | @param InitType Type of CPU INIT to perform\r | |
131 | \r | |
132 | @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r | |
133 | seen.\r | |
134 | @retval EFI_DEVICE_ERROR If CPU INIT failed.\r | |
135 | @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r | |
136 | \r | |
137 | **/\r | |
a47463f2 | 138 | EFI_STATUS\r |
139 | EFIAPI\r | |
140 | CpuInit (\r | |
141 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
142 | IN EFI_CPU_INIT_TYPE InitType\r | |
143 | );\r | |
144 | \r | |
430fbbe0 | 145 | /**\r |
146 | Registers a function to be called from the CPU interrupt handler.\r | |
147 | \r | |
148 | @param This Protocol instance structure\r | |
149 | @param InterruptType Defines which interrupt to hook. IA-32\r | |
150 | valid range is 0x00 through 0xFF\r | |
151 | @param InterruptHandler A pointer to a function of type\r | |
152 | EFI_CPU_INTERRUPT_HANDLER that is called\r | |
153 | when a processor interrupt occurs. A null\r | |
154 | pointer is an error condition.\r | |
155 | \r | |
156 | @retval EFI_SUCCESS If handler installed or uninstalled.\r | |
157 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r | |
158 | for InterruptType was previously installed.\r | |
159 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r | |
160 | InterruptType was not previously installed.\r | |
161 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r | |
162 | is not supported.\r | |
163 | \r | |
164 | **/\r | |
a47463f2 | 165 | EFI_STATUS\r |
166 | EFIAPI\r | |
167 | CpuRegisterInterruptHandler (\r | |
168 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
169 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
170 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
171 | );\r | |
172 | \r | |
430fbbe0 | 173 | /**\r |
174 | Returns a timer value from one of the CPU's internal timers. There is no\r | |
175 | inherent time interval between ticks but is a function of the CPU frequency.\r | |
176 | \r | |
177 | @param This - Protocol instance structure.\r | |
178 | @param TimerIndex - Specifies which CPU timer is requested.\r | |
179 | @param TimerValue - Pointer to the returned timer value.\r | |
180 | @param TimerPeriod - A pointer to the amount of time that passes\r | |
181 | in femtoseconds (10-15) for each increment\r | |
182 | of TimerValue. If TimerValue does not\r | |
183 | increment at a predictable rate, then 0 is\r | |
184 | returned. The amount of time that has\r | |
185 | passed between two calls to GetTimerValue()\r | |
186 | can be calculated with the formula\r | |
187 | (TimerValue2 - TimerValue1) * TimerPeriod.\r | |
188 | This parameter is optional and may be NULL.\r | |
189 | \r | |
190 | @retval EFI_SUCCESS - If the CPU timer count was returned.\r | |
191 | @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r | |
192 | @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r | |
193 | @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r | |
194 | \r | |
195 | **/\r | |
a47463f2 | 196 | EFI_STATUS\r |
197 | EFIAPI\r | |
198 | CpuGetTimerValue (\r | |
199 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
200 | IN UINT32 TimerIndex,\r | |
201 | OUT UINT64 *TimerValue,\r | |
202 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
203 | );\r | |
204 | \r | |
430fbbe0 | 205 | /**\r |
206 | Set memory cacheability attributes for given range of memeory.\r | |
207 | \r | |
208 | @param This Protocol instance structure\r | |
209 | @param BaseAddress Specifies the start address of the\r | |
210 | memory range\r | |
211 | @param Length Specifies the length of the memory range\r | |
212 | @param Attributes The memory cacheability for the memory range\r | |
213 | \r | |
214 | @retval EFI_SUCCESS If the cacheability of that memory range is\r | |
215 | set successfully\r | |
216 | @retval EFI_UNSUPPORTED If the desired operation cannot be done\r | |
217 | @retval EFI_INVALID_PARAMETER The input parameter is not correct,\r | |
218 | such as Length = 0\r | |
219 | \r | |
220 | **/\r | |
a47463f2 | 221 | EFI_STATUS\r |
222 | EFIAPI\r | |
223 | CpuSetMemoryAttributes (\r | |
224 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
225 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
226 | IN UINT64 Length,\r | |
227 | IN UINT64 Attributes\r | |
228 | );\r | |
229 | \r | |
430fbbe0 | 230 | /**\r |
231 | Initialize Global Descriptor Table.\r | |
232 | \r | |
233 | **/\r | |
a47463f2 | 234 | VOID\r |
235 | InitGlobalDescriptorTable (\r | |
236 | VOID\r | |
237 | );\r | |
238 | \r | |
430fbbe0 | 239 | /**\r |
240 | Sets the code selector (CS).\r | |
241 | \r | |
242 | @param Selector Value of code selector.\r | |
243 | \r | |
244 | **/\r | |
a47463f2 | 245 | VOID\r |
246 | EFIAPI\r | |
247 | SetCodeSelector (\r | |
248 | UINT16 Selector\r | |
249 | );\r | |
250 | \r | |
430fbbe0 | 251 | /**\r |
252 | Sets the data selector (DS).\r | |
253 | \r | |
254 | @param Selector Value of data selector.\r | |
255 | \r | |
256 | **/\r | |
a47463f2 | 257 | VOID\r |
258 | EFIAPI\r | |
259 | SetDataSelectors (\r | |
260 | UINT16 Selector\r | |
261 | );\r | |
262 | \r | |
a47463f2 | 263 | #endif\r |
264 | \r |