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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 35 | static void __init ssb_select_mitigation(void); |
05516ad8 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
7011f443 JK |
38 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
39 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 40 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 41 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 42 | |
d0c3bedd KRW |
43 | /* |
44 | * The vendor and possibly platform specific bits which can be modified in | |
45 | * x86_spec_ctrl_base. | |
46 | */ | |
e5f984ed | 47 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 48 | |
c37b94dd KRW |
49 | /* |
50 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 51 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
52 | */ |
53 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 54 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 55 | |
6cd930f0 TG |
56 | /* Control conditional STIPB in switch_to() */ |
57 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); | |
58 | ||
1353ebb4 JF |
59 | void __init check_bugs(void) |
60 | { | |
61 | identify_boot_cpu(); | |
55a36b65 | 62 | |
483ec3c6 TG |
63 | /* |
64 | * identify_boot_cpu() initialized SMT support information, let the | |
65 | * core code know. | |
66 | */ | |
ade31b9e | 67 | cpu_smt_check_topology_early(); |
483ec3c6 | 68 | |
62a67e12 BP |
69 | if (!IS_ENABLED(CONFIG_SMP)) { |
70 | pr_info("CPU: "); | |
71 | print_cpu_info(&boot_cpu_data); | |
72 | } | |
73 | ||
296b454a KRW |
74 | /* |
75 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
76 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
77 | * init code as it is not enumerated and depends on the family. | |
296b454a | 78 | */ |
50f9b919 | 79 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
80 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
81 | ||
e5f984ed TG |
82 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
83 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
84 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
85 | ||
da285121 DW |
86 | /* Select the proper spectre mitigation before patching alternatives */ |
87 | spectre_v2_select_mitigation(); | |
88 | ||
e63490c8 KRW |
89 | /* |
90 | * Select proper mitigation for any exposure to the Speculative Store | |
91 | * Bypass vulnerability. | |
92 | */ | |
93 | ssb_select_mitigation(); | |
94 | ||
05516ad8 AK |
95 | l1tf_select_mitigation(); |
96 | ||
62a67e12 | 97 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
98 | /* |
99 | * Check whether we are able to run this kernel safely on SMP. | |
100 | * | |
101 | * - i386 is no longer supported. | |
102 | * - In order to run on anything without a TSC, we need to be | |
103 | * compiled for a i486. | |
104 | */ | |
105 | if (boot_cpu_data.x86 < 4) | |
106 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
107 | ||
bfe4bb15 MV |
108 | init_utsname()->machine[1] = |
109 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 110 | alternative_instructions(); |
304bceda | 111 | |
4d164092 | 112 | fpu__init_check_bugs(); |
62a67e12 BP |
113 | #else /* CONFIG_X86_64 */ |
114 | alternative_instructions(); | |
115 | ||
116 | /* | |
117 | * Make sure the first 2MB area is not mapped by huge pages | |
118 | * There are typically fixed size MTRRs in there and overlapping | |
119 | * MTRRs into large pages causes slow downs. | |
120 | * | |
121 | * Right now we don't do that with gbpages because there seems | |
122 | * very little benefit for that case. | |
123 | */ | |
124 | if (!direct_gbpages) | |
125 | set_memory_4k((unsigned long)__va(0), 1); | |
126 | #endif | |
1353ebb4 | 127 | } |
61dc0f55 | 128 | |
12376b62 BP |
129 | void |
130 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 131 | { |
e5f984ed | 132 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 133 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 134 | |
50f9b919 | 135 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 136 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
137 | /* |
138 | * Restrict guest_spec_ctrl to supported values. Clear the | |
139 | * modifiable bits in the host base value and or the | |
140 | * modifiable bits from the guest value. | |
141 | */ | |
142 | guestval = hostval & ~x86_spec_ctrl_mask; | |
143 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
144 | ||
12376b62 | 145 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
146 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
147 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 148 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 149 | |
e5f984ed TG |
150 | if (hostval != guestval) { |
151 | msrval = setguest ? guestval : hostval; | |
152 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
153 | } |
154 | } | |
1238ed31 TG |
155 | |
156 | /* | |
157 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
158 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
159 | */ | |
160 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
161 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
162 | return; | |
163 | ||
164 | /* | |
165 | * If the host has SSBD mitigation enabled, force it in the host's | |
166 | * virtual MSR value. If its not permanently enabled, evaluate | |
167 | * current's TIF_SSBD thread flag. | |
168 | */ | |
169 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
170 | hostval = SPEC_CTRL_SSBD; | |
171 | else | |
172 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
173 | ||
174 | /* Sanitize the guest value */ | |
175 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
176 | ||
177 | if (hostval != guestval) { | |
178 | unsigned long tif; | |
179 | ||
180 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
181 | ssbd_spec_ctrl_to_tif(hostval); | |
182 | ||
8fce7184 | 183 | speculation_ctrl_update(tif); |
1238ed31 | 184 | } |
19fff03f | 185 | } |
12376b62 | 186 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 187 | |
8fe36c9d | 188 | static void x86_amd_ssb_disable(void) |
c37b94dd | 189 | { |
8fe36c9d | 190 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 191 | |
65e02bbd TL |
192 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
193 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
194 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
195 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
196 | } | |
197 | ||
aef0bebc TG |
198 | #undef pr_fmt |
199 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
200 | ||
201 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
202 | SPECTRE_V2_NONE; | |
203 | ||
6cd930f0 TG |
204 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
205 | SPECTRE_V2_USER_NONE; | |
206 | ||
d280282b | 207 | #ifdef RETPOLINE |
bb3c2578 TG |
208 | static bool spectre_v2_bad_module; |
209 | ||
d280282b AK |
210 | bool retpoline_module_ok(bool has_retpoline) |
211 | { | |
212 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
213 | return true; | |
214 | ||
c8b8e109 | 215 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
216 | spectre_v2_bad_module = true; |
217 | return false; | |
218 | } | |
bb3c2578 TG |
219 | |
220 | static inline const char *spectre_v2_module_string(void) | |
221 | { | |
222 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
223 | } | |
224 | #else | |
225 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 226 | #endif |
da285121 | 227 | |
da285121 DW |
228 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
229 | { | |
230 | int len = strlen(opt); | |
231 | ||
232 | return len == arglen && !strncmp(arg, opt, len); | |
233 | } | |
234 | ||
aef0bebc TG |
235 | /* The kernel command line selection for spectre v2 */ |
236 | enum spectre_v2_mitigation_cmd { | |
237 | SPECTRE_V2_CMD_NONE, | |
238 | SPECTRE_V2_CMD_AUTO, | |
239 | SPECTRE_V2_CMD_FORCE, | |
240 | SPECTRE_V2_CMD_RETPOLINE, | |
241 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
242 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
243 | }; | |
244 | ||
6cd930f0 TG |
245 | enum spectre_v2_user_cmd { |
246 | SPECTRE_V2_USER_CMD_NONE, | |
247 | SPECTRE_V2_USER_CMD_AUTO, | |
248 | SPECTRE_V2_USER_CMD_FORCE, | |
249 | }; | |
250 | ||
251 | static const char * const spectre_v2_user_strings[] = { | |
252 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", | |
253 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
254 | }; | |
255 | ||
256 | static const struct { | |
257 | const char *option; | |
258 | enum spectre_v2_user_cmd cmd; | |
259 | bool secure; | |
260 | } v2_user_options[] __initdata = { | |
261 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, | |
262 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
263 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
264 | }; | |
265 | ||
266 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
267 | { | |
268 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
269 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
270 | } | |
271 | ||
272 | static enum spectre_v2_user_cmd __init | |
273 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
274 | { | |
275 | char arg[20]; | |
276 | int ret, i; | |
277 | ||
278 | switch (v2_cmd) { | |
279 | case SPECTRE_V2_CMD_NONE: | |
280 | return SPECTRE_V2_USER_CMD_NONE; | |
281 | case SPECTRE_V2_CMD_FORCE: | |
282 | return SPECTRE_V2_USER_CMD_FORCE; | |
283 | default: | |
284 | break; | |
285 | } | |
286 | ||
287 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
288 | arg, sizeof(arg)); | |
289 | if (ret < 0) | |
290 | return SPECTRE_V2_USER_CMD_AUTO; | |
291 | ||
292 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
293 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
294 | spec_v2_user_print_cond(v2_user_options[i].option, | |
295 | v2_user_options[i].secure); | |
296 | return v2_user_options[i].cmd; | |
297 | } | |
298 | } | |
299 | ||
300 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
301 | return SPECTRE_V2_USER_CMD_AUTO; | |
302 | } | |
303 | ||
304 | static void __init | |
305 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
306 | { | |
307 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
308 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
309 | ||
310 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
311 | return; | |
312 | ||
313 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
314 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
315 | smt_possible = false; | |
316 | ||
317 | switch (spectre_v2_parse_user_cmdline(v2_cmd)) { | |
318 | case SPECTRE_V2_USER_CMD_AUTO: | |
319 | case SPECTRE_V2_USER_CMD_NONE: | |
320 | goto set_mode; | |
321 | case SPECTRE_V2_USER_CMD_FORCE: | |
322 | mode = SPECTRE_V2_USER_STRICT; | |
323 | break; | |
324 | } | |
325 | ||
326 | /* Initialize Indirect Branch Prediction Barrier */ | |
327 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
328 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
329 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); | |
330 | } | |
331 | ||
332 | /* If enhanced IBRS is enabled no STIPB required */ | |
333 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
334 | return; | |
335 | ||
336 | set_mode: | |
337 | spectre_v2_user = mode; | |
338 | /* Only print the STIBP mode when SMT possible */ | |
339 | if (smt_possible) | |
340 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
341 | } | |
342 | ||
0eb5928b | 343 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
344 | [SPECTRE_V2_NONE] = "Vulnerable", |
345 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
346 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
347 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
348 | }; | |
349 | ||
17c33e7c KA |
350 | static const struct { |
351 | const char *option; | |
352 | enum spectre_v2_mitigation_cmd cmd; | |
353 | bool secure; | |
5a76cb46 | 354 | } mitigation_options[] __initdata = { |
aef0bebc TG |
355 | { "off", SPECTRE_V2_CMD_NONE, false }, |
356 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
357 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
358 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
359 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
360 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
361 | }; |
362 | ||
10640103 | 363 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 364 | { |
10640103 | 365 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
366 | pr_info("%s selected on command line.\n", reason); |
367 | } | |
368 | ||
da285121 DW |
369 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
370 | { | |
aef0bebc | 371 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 372 | char arg[20]; |
17c33e7c | 373 | int ret, i; |
17c33e7c KA |
374 | |
375 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
376 | return SPECTRE_V2_CMD_NONE; | |
17c33e7c | 377 | |
4e8e955a TC |
378 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
379 | if (ret < 0) | |
380 | return SPECTRE_V2_CMD_AUTO; | |
381 | ||
382 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
383 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
384 | continue; | |
385 | cmd = mitigation_options[i].cmd; | |
386 | break; | |
387 | } | |
388 | ||
389 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
390 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
391 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
392 | } |
393 | ||
17c33e7c KA |
394 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
395 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
396 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
397 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 398 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 399 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
400 | } |
401 | ||
402 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
403 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
404 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
405 | return SPECTRE_V2_CMD_AUTO; | |
406 | } | |
407 | ||
10640103 TG |
408 | spec_v2_print_cond(mitigation_options[i].option, |
409 | mitigation_options[i].secure); | |
17c33e7c | 410 | return cmd; |
da285121 DW |
411 | } |
412 | ||
413 | static void __init spectre_v2_select_mitigation(void) | |
414 | { | |
415 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
416 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
417 | ||
418 | /* | |
419 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
420 | * then nothing to do. | |
421 | */ | |
422 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
423 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
424 | return; | |
425 | ||
426 | switch (cmd) { | |
427 | case SPECTRE_V2_CMD_NONE: | |
428 | return; | |
429 | ||
430 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 431 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
432 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
433 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
434 | /* Force it so VMEXIT will restore correctly */ | |
435 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
436 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
437 | goto specv2_set_mode; | |
438 | } | |
d0f293e0 DL |
439 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
440 | goto retpoline_auto; | |
441 | break; | |
da285121 DW |
442 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
443 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
444 | goto retpoline_amd; | |
445 | break; | |
446 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
447 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
448 | goto retpoline_generic; | |
449 | break; | |
450 | case SPECTRE_V2_CMD_RETPOLINE: | |
451 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
452 | goto retpoline_auto; | |
453 | break; | |
454 | } | |
713f1b95 | 455 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
456 | return; |
457 | ||
458 | retpoline_auto: | |
459 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
460 | retpoline_amd: | |
461 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 462 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
463 | goto retpoline_generic; |
464 | } | |
51dd01b5 | 465 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
466 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
467 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
468 | } else { | |
469 | retpoline_generic: | |
51dd01b5 | 470 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
471 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
472 | } | |
473 | ||
1044fde9 | 474 | specv2_set_mode: |
da285121 DW |
475 | spectre_v2_enabled = mode; |
476 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
477 | |
478 | /* | |
14623a43 JK |
479 | * If spectre v2 protection has been enabled, unconditionally fill |
480 | * RSB during a context switch; this protects against two independent | |
481 | * issues: | |
c995efd5 | 482 | * |
14623a43 JK |
483 | * - RSB underflow (and switch to BTB) on Skylake+ |
484 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 485 | */ |
14623a43 JK |
486 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
487 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 488 | |
390b99c3 DW |
489 | /* |
490 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
491 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
492 | * speculation around firmware calls only when Enhanced IBRS isn't | |
493 | * supported. | |
494 | * | |
495 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
496 | * the user might select retpoline on the kernel command line and if | |
497 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
498 | * enable IBRS around firmware calls. | |
390b99c3 | 499 | */ |
1044fde9 | 500 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
501 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
502 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
503 | } | |
7011f443 | 504 | |
6cd930f0 TG |
505 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
506 | spectre_v2_user_select_mitigation(cmd); | |
507 | ||
7011f443 JK |
508 | /* Enable STIBP if appropriate */ |
509 | arch_smt_update(); | |
da285121 DW |
510 | } |
511 | ||
aef0bebc TG |
512 | static bool stibp_needed(void) |
513 | { | |
aef0bebc TG |
514 | /* Enhanced IBRS makes using STIBP unnecessary. */ |
515 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
516 | return false; | |
517 | ||
6cd930f0 TG |
518 | /* Check for strict user mitigation mode */ |
519 | return spectre_v2_user == SPECTRE_V2_USER_STRICT; | |
aef0bebc TG |
520 | } |
521 | ||
522 | static void update_stibp_msr(void *info) | |
523 | { | |
524 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
525 | } | |
526 | ||
527 | void arch_smt_update(void) | |
528 | { | |
529 | u64 mask; | |
530 | ||
531 | if (!stibp_needed()) | |
532 | return; | |
533 | ||
534 | mutex_lock(&spec_ctrl_mutex); | |
535 | ||
536 | mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; | |
537 | if (sched_smt_active()) | |
538 | mask |= SPEC_CTRL_STIBP; | |
539 | ||
540 | if (mask != x86_spec_ctrl_base) { | |
541 | pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", | |
542 | mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); | |
543 | x86_spec_ctrl_base = mask; | |
544 | on_each_cpu(update_stibp_msr, NULL, 1); | |
545 | } | |
546 | mutex_unlock(&spec_ctrl_mutex); | |
547 | } | |
548 | ||
e63490c8 KRW |
549 | #undef pr_fmt |
550 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
551 | ||
b5e6d77d | 552 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
553 | |
554 | /* The kernel command line selection */ | |
555 | enum ssb_mitigation_cmd { | |
556 | SPEC_STORE_BYPASS_CMD_NONE, | |
557 | SPEC_STORE_BYPASS_CMD_AUTO, | |
558 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 559 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 560 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
561 | }; |
562 | ||
0eb5928b | 563 | static const char * const ssb_strings[] = { |
e63490c8 | 564 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 565 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
566 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
567 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
568 | }; |
569 | ||
570 | static const struct { | |
571 | const char *option; | |
572 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 573 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
574 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
575 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
576 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
577 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
578 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
579 | }; |
580 | ||
581 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
582 | { | |
583 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
584 | char arg[20]; | |
585 | int ret, i; | |
586 | ||
587 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
588 | return SPEC_STORE_BYPASS_CMD_NONE; | |
589 | } else { | |
590 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
591 | arg, sizeof(arg)); | |
592 | if (ret < 0) | |
593 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
594 | ||
595 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
596 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
597 | continue; | |
598 | ||
599 | cmd = ssb_mitigation_options[i].cmd; | |
600 | break; | |
601 | } | |
602 | ||
603 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
604 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
605 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
606 | } | |
607 | } | |
608 | ||
609 | return cmd; | |
610 | } | |
611 | ||
dbe3009d | 612 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
613 | { |
614 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
615 | enum ssb_mitigation_cmd cmd; | |
616 | ||
8fe36c9d | 617 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
618 | return mode; |
619 | ||
620 | cmd = ssb_parse_cmdline(); | |
621 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
622 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
623 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
624 | return mode; | |
625 | ||
626 | switch (cmd) { | |
627 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
628 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
629 | /* | |
630 | * Choose prctl+seccomp as the default mode if seccomp is | |
631 | * enabled. | |
632 | */ | |
633 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
634 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
635 | else | |
636 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 637 | break; |
e63490c8 KRW |
638 | case SPEC_STORE_BYPASS_CMD_ON: |
639 | mode = SPEC_STORE_BYPASS_DISABLE; | |
640 | break; | |
574dcf89 TG |
641 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
642 | mode = SPEC_STORE_BYPASS_PRCTL; | |
643 | break; | |
e63490c8 KRW |
644 | case SPEC_STORE_BYPASS_CMD_NONE: |
645 | break; | |
646 | } | |
647 | ||
23b9eab9 KRW |
648 | /* |
649 | * We have three CPU feature flags that are in play here: | |
650 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 651 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
652 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
653 | */ | |
574dcf89 | 654 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 655 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 656 | /* |
3b881627 KRW |
657 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
658 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 659 | */ |
5005c716 TL |
660 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
661 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 662 | x86_amd_ssb_disable(); |
5005c716 | 663 | } else { |
8fe36c9d | 664 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 665 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 666 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
667 | } |
668 | } | |
669 | ||
e63490c8 KRW |
670 | return mode; |
671 | } | |
672 | ||
043d480e | 673 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
674 | { |
675 | ssb_mode = __ssb_select_mitigation(); | |
676 | ||
677 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
678 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
679 | } | |
680 | ||
da285121 | 681 | #undef pr_fmt |
c7416003 | 682 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 683 | |
199bfed2 | 684 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
574dcf89 | 685 | { |
733f4234 | 686 | bool update; |
574dcf89 | 687 | |
c7416003 KC |
688 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
689 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
690 | return -ENXIO; |
691 | ||
733f4234 TG |
692 | switch (ctrl) { |
693 | case PR_SPEC_ENABLE: | |
694 | /* If speculation is force disabled, enable is not allowed */ | |
695 | if (task_spec_ssb_force_disable(task)) | |
696 | return -EPERM; | |
697 | task_clear_spec_ssb_disable(task); | |
8fe36c9d | 698 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
699 | break; |
700 | case PR_SPEC_DISABLE: | |
701 | task_set_spec_ssb_disable(task); | |
8fe36c9d | 702 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
703 | break; |
704 | case PR_SPEC_FORCE_DISABLE: | |
705 | task_set_spec_ssb_disable(task); | |
706 | task_set_spec_ssb_force_disable(task); | |
8fe36c9d | 707 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
708 | break; |
709 | default: | |
710 | return -ERANGE; | |
711 | } | |
574dcf89 | 712 | |
199bfed2 KC |
713 | /* |
714 | * If being set on non-current task, delay setting the CPU | |
715 | * mitigation until it is next scheduled. | |
716 | */ | |
733f4234 | 717 | if (task == current && update) |
8fce7184 | 718 | speculation_ctrl_update_current(); |
574dcf89 TG |
719 | |
720 | return 0; | |
721 | } | |
722 | ||
5b38e244 TG |
723 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
724 | unsigned long ctrl) | |
725 | { | |
726 | switch (which) { | |
727 | case PR_SPEC_STORE_BYPASS: | |
728 | return ssb_prctl_set(task, ctrl); | |
729 | default: | |
730 | return -ENODEV; | |
731 | } | |
732 | } | |
733 | ||
734 | #ifdef CONFIG_SECCOMP | |
735 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
736 | { | |
c7416003 KC |
737 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
738 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
739 | } |
740 | #endif | |
741 | ||
199bfed2 | 742 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
743 | { |
744 | switch (ssb_mode) { | |
745 | case SPEC_STORE_BYPASS_DISABLE: | |
746 | return PR_SPEC_DISABLE; | |
c7416003 | 747 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 748 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
749 | if (task_spec_ssb_force_disable(task)) |
750 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
751 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
752 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
753 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
754 | default: | |
755 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
756 | return PR_SPEC_ENABLE; | |
757 | return PR_SPEC_NOT_AFFECTED; | |
758 | } | |
759 | } | |
760 | ||
199bfed2 | 761 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
762 | { |
763 | switch (which) { | |
764 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 765 | return ssb_prctl_get(task); |
574dcf89 TG |
766 | default: |
767 | return -ENODEV; | |
768 | } | |
769 | } | |
770 | ||
23b9eab9 KRW |
771 | void x86_spec_ctrl_setup_ap(void) |
772 | { | |
50f9b919 | 773 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 774 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
775 | |
776 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 777 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
778 | } |
779 | ||
73ca9f47 KRW |
780 | #undef pr_fmt |
781 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 782 | |
24fcb53c JK |
783 | /* Default mitigation for L1TF-affected CPUs */ |
784 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 785 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
786 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
787 | ||
522c7bed | 788 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
789 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
790 | #endif | |
791 | ||
f1f016ed AK |
792 | /* |
793 | * These CPUs all support 44bits physical address space internally in the | |
794 | * cache but CPUID can report a smaller number of physical address bits. | |
795 | * | |
796 | * The L1TF mitigation uses the top most address bit for the inversion of | |
797 | * non present PTEs. When the installed memory reaches into the top most | |
798 | * address bit due to memory holes, which has been observed on machines | |
799 | * which report 36bits physical address bits and have 32G RAM installed, | |
800 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
801 | * This is a false positive because the mitigation is still possible due to | |
802 | * the fact that the cache uses 44bit internally. Use the cache bits | |
803 | * instead of the reported physical bits and adjust them on the affected | |
804 | * machines to 44bit if the reported bits are less than 44. | |
805 | */ | |
806 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
807 | { | |
808 | if (c->x86 != 6) | |
809 | return; | |
810 | ||
811 | switch (c->x86_model) { | |
812 | case INTEL_FAM6_NEHALEM: | |
813 | case INTEL_FAM6_WESTMERE: | |
814 | case INTEL_FAM6_SANDYBRIDGE: | |
815 | case INTEL_FAM6_IVYBRIDGE: | |
816 | case INTEL_FAM6_HASWELL_CORE: | |
817 | case INTEL_FAM6_HASWELL_ULT: | |
818 | case INTEL_FAM6_HASWELL_GT3E: | |
819 | case INTEL_FAM6_BROADWELL_CORE: | |
820 | case INTEL_FAM6_BROADWELL_GT3E: | |
821 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
822 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
823 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
824 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
825 | if (c->x86_cache_bits < 44) | |
826 | c->x86_cache_bits = 44; | |
827 | break; | |
828 | } | |
829 | } | |
830 | ||
73ca9f47 KRW |
831 | static void __init l1tf_select_mitigation(void) |
832 | { | |
833 | u64 half_pa; | |
834 | ||
835 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
836 | return; | |
837 | ||
f1f016ed AK |
838 | override_cache_bits(&boot_cpu_data); |
839 | ||
24fcb53c JK |
840 | switch (l1tf_mitigation) { |
841 | case L1TF_MITIGATION_OFF: | |
842 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
843 | case L1TF_MITIGATION_FLUSH: | |
844 | break; | |
845 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
846 | case L1TF_MITIGATION_FULL: | |
847 | cpu_smt_disable(false); | |
848 | break; | |
849 | case L1TF_MITIGATION_FULL_FORCE: | |
850 | cpu_smt_disable(true); | |
851 | break; | |
852 | } | |
853 | ||
73ca9f47 KRW |
854 | #if CONFIG_PGTABLE_LEVELS == 2 |
855 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
856 | return; | |
857 | #endif | |
858 | ||
73ca9f47 KRW |
859 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
860 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
861 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
862 | return; | |
863 | } | |
864 | ||
865 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
866 | } | |
24fcb53c JK |
867 | |
868 | static int __init l1tf_cmdline(char *str) | |
869 | { | |
870 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
871 | return 0; | |
872 | ||
873 | if (!str) | |
874 | return -EINVAL; | |
875 | ||
876 | if (!strcmp(str, "off")) | |
877 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
878 | else if (!strcmp(str, "flush,nowarn")) | |
879 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
880 | else if (!strcmp(str, "flush")) | |
881 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
882 | else if (!strcmp(str, "flush,nosmt")) | |
883 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
884 | else if (!strcmp(str, "full")) | |
885 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
886 | else if (!strcmp(str, "full,force")) | |
887 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
888 | ||
889 | return 0; | |
890 | } | |
891 | early_param("l1tf", l1tf_cmdline); | |
892 | ||
73ca9f47 KRW |
893 | #undef pr_fmt |
894 | ||
61dc0f55 | 895 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 896 | |
b9cfedcd TG |
897 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
898 | ||
899 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 900 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
901 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
902 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
903 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
904 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
905 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 906 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
907 | }; |
908 | ||
909 | static ssize_t l1tf_show_state(char *buf) | |
910 | { | |
911 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
912 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
913 | ||
3899f7b1 PB |
914 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
915 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 916 | sched_smt_active())) { |
3899f7b1 PB |
917 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
918 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 919 | } |
3899f7b1 PB |
920 | |
921 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
922 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 923 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
924 | } |
925 | #else | |
926 | static ssize_t l1tf_show_state(char *buf) | |
927 | { | |
928 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
929 | } | |
930 | #endif | |
931 | ||
2daa53e8 TC |
932 | static char *stibp_state(void) |
933 | { | |
4a8d91c8 TC |
934 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
935 | return ""; | |
936 | ||
6cd930f0 TG |
937 | switch (spectre_v2_user) { |
938 | case SPECTRE_V2_USER_NONE: | |
939 | return ", STIBP: disabled"; | |
940 | case SPECTRE_V2_USER_STRICT: | |
941 | return ", STIBP: forced"; | |
942 | } | |
943 | return ""; | |
2daa53e8 TC |
944 | } |
945 | ||
946 | static char *ibpb_state(void) | |
947 | { | |
948 | if (boot_cpu_has(X86_FEATURE_USE_IBPB)) | |
949 | return ", IBPB"; | |
950 | else | |
951 | return ""; | |
952 | } | |
953 | ||
ace051d5 | 954 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 955 | char *buf, unsigned int bug) |
61dc0f55 | 956 | { |
d2b8fc2d | 957 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 958 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
959 | |
960 | switch (bug) { | |
961 | case X86_BUG_CPU_MELTDOWN: | |
962 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
963 | return sprintf(buf, "Mitigation: PTI\n"); | |
964 | ||
965 | break; | |
966 | ||
967 | case X86_BUG_SPECTRE_V1: | |
968 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
969 | ||
970 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 971 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 972 | ibpb_state(), |
d2b8fc2d | 973 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 974 | stibp_state(), |
5e2fafd5 | 975 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
976 | spectre_v2_module_string()); |
977 | ||
e63490c8 KRW |
978 | case X86_BUG_SPEC_STORE_BYPASS: |
979 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
980 | ||
05516ad8 AK |
981 | case X86_BUG_L1TF: |
982 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 983 | return l1tf_show_state(buf); |
05516ad8 | 984 | break; |
d2b8fc2d KRW |
985 | default: |
986 | break; | |
987 | } | |
988 | ||
61dc0f55 TG |
989 | return sprintf(buf, "Vulnerable\n"); |
990 | } | |
991 | ||
d2b8fc2d KRW |
992 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
993 | { | |
994 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
995 | } | |
996 | ||
713f1b95 | 997 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 998 | { |
d2b8fc2d | 999 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1000 | } |
1001 | ||
713f1b95 | 1002 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1003 | { |
d2b8fc2d | 1004 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1005 | } |
d7de9182 KRW |
1006 | |
1007 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1008 | { | |
1009 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1010 | } | |
05516ad8 AK |
1011 | |
1012 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1013 | { | |
1014 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1015 | } | |
61dc0f55 | 1016 | #endif |