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KVM: VMX: clean-up vmx_set_segment()
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CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
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26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC
42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT
47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK
50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
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53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT
56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK
72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH
75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX
82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT
85module_param(fasteoi, bool, S_IRUGO);
86
801d3424
NHE
87/*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
476bc001 92static bool __read_mostly nested = 0;
801d3424
NHE
93module_param(nested, bool, S_IRUGO);
94
cdc0e244
AK
95#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97#define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 100 (X86_CR0_WP | X86_CR0_NE)
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101#define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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103#define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
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107#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
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110#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
4b8d54f9
ZE
112/*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 116 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE
117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
00c25bce 123#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE
124#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126module_param(ple_gap, int, S_IRUGO);
127
128static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129module_param(ple_window, int, S_IRUGO);
130
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131extern const ulong vmx_return;
132
8bf00a52 133#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 134#define VMCS02_POOL_SIZE 1
61d2ef2c 135
a2fa3e9f
GH
136struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140};
141
d462b819
NHE
142/*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152};
153
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154struct shared_msr_entry {
155 unsigned index;
156 u64 data;
d5696725 157 u64 mask;
26bb0981
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158};
159
a9d30f33
NHE
160/*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
22bd0358 173typedef u64 natural_width;
a9d30f33
NHE
174struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
22bd0358 180
27d6c865
NHE
181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
22bd0358
NHE
184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE
320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE
336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE
343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE
350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE
356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE
361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE
363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE
368};
369
a2fa3e9f 370struct vcpu_vmx {
fb3f0f51 371 struct kvm_vcpu vcpu;
313dbd49 372 unsigned long host_rsp;
29bd8a78 373 u8 fail;
69c73028 374 u8 cpl;
9d58b931 375 bool nmi_known_unmasked;
51aa01d1 376 u32 exit_intr_info;
1155f76a 377 u32 idt_vectoring_info;
6de12732 378 ulong rflags;
26bb0981 379 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH
380 int nmsrs;
381 int save_nmsrs;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK
383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE
386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK
394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH
399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK
402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV
405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK
411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK
415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK
424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY
430
431 bool rdtscp_enabled;
ec378aee
NHE
432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH
435};
436
2fb92db1
AK
437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH
446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH
449}
450
22bd0358
NHE
451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE
457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584};
585static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587static inline short vmcs_field_to_offset(unsigned long field)
588{
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592}
593
a9d30f33
NHE
594static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595{
596 return to_vmx(vcpu)->nested.current_vmcs12;
597}
598
599static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600{
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 602 if (is_error_page(page))
a9d30f33 603 return NULL;
32cad84f 604
a9d30f33
NHE
605 return page;
606}
607
608static void nested_release_page(struct page *page)
609{
610 kvm_release_page_dirty(page);
611}
612
613static void nested_release_page_clean(struct page *page)
614{
615 kvm_release_page_clean(page);
616}
617
4e1096d2 618static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX
619static void kvm_cpu_vmxon(u64 addr);
620static void kvm_cpu_vmxoff(void);
aff48baa 621static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 622static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW
623static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
75880a01 627
6aa8b732
AK
628static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE
630/*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 635static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 636
3e7c73e9
AK
637static unsigned long *vmx_io_bitmap_a;
638static unsigned long *vmx_io_bitmap_b;
5897297b
AK
639static unsigned long *vmx_msr_bitmap_legacy;
640static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 641
110312c8 642static bool cpu_has_load_ia32_efer;
8bf00a52 643static bool cpu_has_load_perf_global_ctrl;
110312c8 644
2384d2b3
SY
645static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
646static DEFINE_SPINLOCK(vmx_vpid_lock);
647
1c3d14fe 648static struct vmcs_config {
6aa8b732
AK
649 int size;
650 int order;
651 u32 revision_id;
1c3d14fe
YS
652 u32 pin_based_exec_ctrl;
653 u32 cpu_based_exec_ctrl;
f78e0e2e 654 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS
655 u32 vmexit_ctrl;
656 u32 vmentry_ctrl;
657} vmcs_config;
6aa8b732 658
efff9e53 659static struct vmx_capability {
d56f546d
SY
660 u32 ept;
661 u32 vpid;
662} vmx_capability;
663
6aa8b732
AK
664#define VMX_SEGMENT_FIELD(seg) \
665 [VCPU_SREG_##seg] = { \
666 .selector = GUEST_##seg##_SELECTOR, \
667 .base = GUEST_##seg##_BASE, \
668 .limit = GUEST_##seg##_LIMIT, \
669 .ar_bytes = GUEST_##seg##_AR_BYTES, \
670 }
671
772e0318 672static const struct kvm_vmx_segment_field {
6aa8b732
AK
673 unsigned selector;
674 unsigned base;
675 unsigned limit;
676 unsigned ar_bytes;
677} kvm_vmx_segment_fields[] = {
678 VMX_SEGMENT_FIELD(CS),
679 VMX_SEGMENT_FIELD(DS),
680 VMX_SEGMENT_FIELD(ES),
681 VMX_SEGMENT_FIELD(FS),
682 VMX_SEGMENT_FIELD(GS),
683 VMX_SEGMENT_FIELD(SS),
684 VMX_SEGMENT_FIELD(TR),
685 VMX_SEGMENT_FIELD(LDTR),
686};
687
26bb0981
AK
688static u64 host_efer;
689
6de4f3ad
AK
690static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
691
4d56c8a7 692/*
8c06585d 693 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK
694 * away by decrementing the array size.
695 */
6aa8b732 696static const u32 vmx_msr_index[] = {
05b3e0c2 697#ifdef CONFIG_X86_64
44ea2b17 698 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 699#endif
8c06585d 700 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 701};
9d8f549d 702#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 703
31299944 704static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK
705{
706 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
707 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 708 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK
709}
710
31299944 711static inline bool is_no_device(u32 intr_info)
2ab455cc
AL
712{
713 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
714 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 715 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL
716}
717
31299944 718static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL
719{
720 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
721 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 722 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL
723}
724
31299944 725static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK
726{
727 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
728 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
729}
730
31299944 731static inline bool is_machine_check(u32 intr_info)
a0861c02
AK
732{
733 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
734 INTR_INFO_VALID_MASK)) ==
735 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
736}
737
31299944 738static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 739{
04547156 740 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY
741}
742
31299944 743static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 744{
04547156 745 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS
746}
747
31299944 748static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 749{
04547156 750 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS
751}
752
31299944 753static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 754{
04547156
SY
755 return vmcs_config.cpu_based_exec_ctrl &
756 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY
757}
758
774ead3a 759static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 760{
04547156
SY
761 return vmcs_config.cpu_based_2nd_exec_ctrl &
762 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
763}
764
765static inline bool cpu_has_vmx_flexpriority(void)
766{
767 return cpu_has_vmx_tpr_shadow() &&
768 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY
769}
770
e799794e
MT
771static inline bool cpu_has_vmx_ept_execute_only(void)
772{
31299944 773 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT
774}
775
776static inline bool cpu_has_vmx_eptp_uncacheable(void)
777{
31299944 778 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT
779}
780
781static inline bool cpu_has_vmx_eptp_writeback(void)
782{
31299944 783 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT
784}
785
786static inline bool cpu_has_vmx_ept_2m_page(void)
787{
31299944 788 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT
789}
790
878403b7
SY
791static inline bool cpu_has_vmx_ept_1g_page(void)
792{
31299944 793 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY
794}
795
4bc9b982
SY
796static inline bool cpu_has_vmx_ept_4levels(void)
797{
798 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
799}
800
83c3a331
XH
801static inline bool cpu_has_vmx_ept_ad_bits(void)
802{
803 return vmx_capability.ept & VMX_EPT_AD_BIT;
804}
805
31299944 806static inline bool cpu_has_vmx_invept_context(void)
d56f546d 807{
31299944 808 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY
809}
810
31299944 811static inline bool cpu_has_vmx_invept_global(void)
d56f546d 812{
31299944 813 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY
814}
815
518c8aee
GJ
816static inline bool cpu_has_vmx_invvpid_single(void)
817{
818 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
819}
820
b9d762fa
GJ
821static inline bool cpu_has_vmx_invvpid_global(void)
822{
823 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
824}
825
31299944 826static inline bool cpu_has_vmx_ept(void)
d56f546d 827{
04547156
SY
828 return vmcs_config.cpu_based_2nd_exec_ctrl &
829 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY
830}
831
31299944 832static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK
833{
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_UNRESTRICTED_GUEST;
836}
837
31299944 838static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE
839{
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
842}
843
31299944 844static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 845{
6d3e435e 846 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY
847}
848
31299944 849static inline bool cpu_has_vmx_vpid(void)
2384d2b3 850{
04547156
SY
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY
853}
854
31299944 855static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY
856{
857 return vmcs_config.cpu_based_2nd_exec_ctrl &
858 SECONDARY_EXEC_RDTSCP;
859}
860
ad756a16
MJ
861static inline bool cpu_has_vmx_invpcid(void)
862{
863 return vmcs_config.cpu_based_2nd_exec_ctrl &
864 SECONDARY_EXEC_ENABLE_INVPCID;
865}
866
31299944 867static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY
868{
869 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
870}
871
f5f48ee1
SY
872static inline bool cpu_has_vmx_wbinvd_exit(void)
873{
874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_WBINVD_EXITING;
876}
877
04547156
SY
878static inline bool report_flexpriority(void)
879{
880 return flexpriority_enabled;
881}
882
fe3ef05c
NHE
883static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
884{
885 return vmcs12->cpu_based_vm_exec_control & bit;
886}
887
888static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
889{
890 return (vmcs12->cpu_based_vm_exec_control &
891 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
892 (vmcs12->secondary_vm_exec_control & bit);
893}
894
644d711a
NHE
895static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
896 struct kvm_vcpu *vcpu)
897{
898 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
899}
900
901static inline bool is_exception(u32 intr_info)
902{
903 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
904 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
905}
906
907static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE
908static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
909 struct vmcs12 *vmcs12,
910 u32 reason, unsigned long qualification);
911
8b9cf98c 912static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK
913{
914 int i;
915
a2fa3e9f 916 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 917 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED
918 return i;
919 return -1;
920}
921
2384d2b3
SY
922static inline void __invvpid(int ext, u16 vpid, gva_t gva)
923{
924 struct {
925 u64 vpid : 16;
926 u64 rsvd : 48;
927 u64 gva;
928 } operand = { vpid, 0, gva };
929
4ecac3fd 930 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY
931 /* CF==1 or ZF==1 --> rc = -1 */
932 "; ja 1f ; ud2 ; 1:"
933 : : "a"(&operand), "c"(ext) : "cc", "memory");
934}
935
1439442c
SY
936static inline void __invept(int ext, u64 eptp, gpa_t gpa)
937{
938 struct {
939 u64 eptp, gpa;
940 } operand = {eptp, gpa};
941
4ecac3fd 942 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY
943 /* CF==1 or ZF==1 --> rc = -1 */
944 "; ja 1f ; ud2 ; 1:\n"
945 : : "a" (&operand), "c" (ext) : "cc", "memory");
946}
947
26bb0981 948static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED
949{
950 int i;
951
8b9cf98c 952 i = __find_msr_index(vmx, msr);
a75beee6 953 if (i >= 0)
a2fa3e9f 954 return &vmx->guest_msrs[i];
8b6d44c7 955 return NULL;
7725f0ba
AK
956}
957
6aa8b732
AK
958static void vmcs_clear(struct vmcs *vmcs)
959{
960 u64 phys_addr = __pa(vmcs);
961 u8 error;
962
4ecac3fd 963 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 964 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK
965 : "cc", "memory");
966 if (error)
967 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
968 vmcs, phys_addr);
969}
970
d462b819
NHE
971static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
972{
973 vmcs_clear(loaded_vmcs->vmcs);
974 loaded_vmcs->cpu = -1;
975 loaded_vmcs->launched = 0;
976}
977
7725b894
DX
978static void vmcs_load(struct vmcs *vmcs)
979{
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
983 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX
985 : "cc", "memory");
986 if (error)
2844d849 987 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX
988 vmcs, phys_addr);
989}
990
8f536b76
ZY
991#ifdef CONFIG_KEXEC
992/*
993 * This bitmap is used to indicate whether the vmclear
994 * operation is enabled on all cpus. All disabled by
995 * default.
996 */
997static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
998
999static inline void crash_enable_local_vmclear(int cpu)
1000{
1001 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1002}
1003
1004static inline void crash_disable_local_vmclear(int cpu)
1005{
1006 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1007}
1008
1009static inline int crash_local_vmclear_enabled(int cpu)
1010{
1011 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1012}
1013
1014static void crash_vmclear_local_loaded_vmcss(void)
1015{
1016 int cpu = raw_smp_processor_id();
1017 struct loaded_vmcs *v;
1018
1019 if (!crash_local_vmclear_enabled(cpu))
1020 return;
1021
1022 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1023 loaded_vmcss_on_cpu_link)
1024 vmcs_clear(v->vmcs);
1025}
1026#else
1027static inline void crash_enable_local_vmclear(int cpu) { }
1028static inline void crash_disable_local_vmclear(int cpu) { }
1029#endif /* CONFIG_KEXEC */
1030
d462b819 1031static void __loaded_vmcs_clear(void *arg)
6aa8b732 1032{
d462b819 1033 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1034 int cpu = raw_smp_processor_id();
6aa8b732 1035
d462b819
NHE
1036 if (loaded_vmcs->cpu != cpu)
1037 return; /* vcpu migration can race with cpu offline */
1038 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1039 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1040 crash_disable_local_vmclear(cpu);
d462b819 1041 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG
1042
1043 /*
1044 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1045 * is before setting loaded_vmcs->vcpu to -1 which is done in
1046 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1047 * then adds the vmcs into percpu list before it is deleted.
1048 */
1049 smp_wmb();
1050
d462b819 1051 loaded_vmcs_init(loaded_vmcs);
8f536b76 1052 crash_enable_local_vmclear(cpu);
6aa8b732
AK
1053}
1054
d462b819 1055static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1056{
e6c7d321
XG
1057 int cpu = loaded_vmcs->cpu;
1058
1059 if (cpu != -1)
1060 smp_call_function_single(cpu,
1061 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK
1062}
1063
1760dd49 1064static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY
1065{
1066 if (vmx->vpid == 0)
1067 return;
1068
518c8aee
GJ
1069 if (cpu_has_vmx_invvpid_single())
1070 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY
1071}
1072
b9d762fa
GJ
1073static inline void vpid_sync_vcpu_global(void)
1074{
1075 if (cpu_has_vmx_invvpid_global())
1076 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1077}
1078
1079static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1080{
1081 if (cpu_has_vmx_invvpid_single())
1760dd49 1082 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ
1083 else
1084 vpid_sync_vcpu_global();
1085}
1086
1439442c
SY
1087static inline void ept_sync_global(void)
1088{
1089 if (cpu_has_vmx_invept_global())
1090 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1091}
1092
1093static inline void ept_sync_context(u64 eptp)
1094{
089d034e 1095 if (enable_ept) {
1439442c
SY
1096 if (cpu_has_vmx_invept_context())
1097 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1098 else
1099 ept_sync_global();
1100 }
1101}
1102
96304217 1103static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1104{
5e520e62 1105 unsigned long value;
6aa8b732 1106
5e520e62
AK
1107 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1108 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK
1109 return value;
1110}
1111
96304217 1112static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK
1113{
1114 return vmcs_readl(field);
1115}
1116
96304217 1117static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK
1118{
1119 return vmcs_readl(field);
1120}
1121
96304217 1122static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1123{
05b3e0c2 1124#ifdef CONFIG_X86_64
6aa8b732
AK
1125 return vmcs_readl(field);
1126#else
1127 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1128#endif
1129}
1130
e52de1b8
AK
1131static noinline void vmwrite_error(unsigned long field, unsigned long value)
1132{
1133 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1134 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1135 dump_stack();
1136}
1137
6aa8b732
AK
1138static void vmcs_writel(unsigned long field, unsigned long value)
1139{
1140 u8 error;
1141
4ecac3fd 1142 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1143 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK
1144 if (unlikely(error))
1145 vmwrite_error(field, value);
6aa8b732
AK
1146}
1147
1148static void vmcs_write16(unsigned long field, u16 value)
1149{
1150 vmcs_writel(field, value);
1151}
1152
1153static void vmcs_write32(unsigned long field, u32 value)
1154{
1155 vmcs_writel(field, value);
1156}
1157
1158static void vmcs_write64(unsigned long field, u64 value)
1159{
6aa8b732 1160 vmcs_writel(field, value);
7682f2d0 1161#ifndef CONFIG_X86_64
6aa8b732
AK
1162 asm volatile ("");
1163 vmcs_writel(field+1, value >> 32);
1164#endif
1165}
1166
2ab455cc
AL
1167static void vmcs_clear_bits(unsigned long field, u32 mask)
1168{
1169 vmcs_writel(field, vmcs_readl(field) & ~mask);
1170}
1171
1172static void vmcs_set_bits(unsigned long field, u32 mask)
1173{
1174 vmcs_writel(field, vmcs_readl(field) | mask);
1175}
1176
2fb92db1
AK
1177static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1178{
1179 vmx->segment_cache.bitmask = 0;
1180}
1181
1182static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1183 unsigned field)
1184{
1185 bool ret;
1186 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1187
1188 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1189 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1190 vmx->segment_cache.bitmask = 0;
1191 }
1192 ret = vmx->segment_cache.bitmask & mask;
1193 vmx->segment_cache.bitmask |= mask;
1194 return ret;
1195}
1196
1197static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1198{
1199 u16 *p = &vmx->segment_cache.seg[seg].selector;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1202 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1203 return *p;
1204}
1205
1206static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1207{
1208 ulong *p = &vmx->segment_cache.seg[seg].base;
1209
1210 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1211 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1212 return *p;
1213}
1214
1215static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1216{
1217 u32 *p = &vmx->segment_cache.seg[seg].limit;
1218
1219 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1220 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1221 return *p;
1222}
1223
1224static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1225{
1226 u32 *p = &vmx->segment_cache.seg[seg].ar;
1227
1228 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1229 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1230 return *p;
1231}
1232
abd3f2d6
AK
1233static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1234{
1235 u32 eb;
1236
fd7373cc
JK
1237 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1238 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1239 if ((vcpu->guest_debug &
1240 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1241 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1242 eb |= 1u << BP_VECTOR;
7ffd92c5 1243 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1244 eb = ~0;
089d034e 1245 if (enable_ept)
1439442c 1246 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK
1247 if (vcpu->fpu_active)
1248 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE
1249
1250 /* When we are running a nested L2 guest and L1 specified for it a
1251 * certain exception bitmap, we must trap the same exceptions and pass
1252 * them to L1. When running L2, we will only handle the exceptions
1253 * specified above if L1 did not want them.
1254 */
1255 if (is_guest_mode(vcpu))
1256 eb |= get_vmcs12(vcpu)->exception_bitmap;
1257
abd3f2d6
AK
1258 vmcs_write32(EXCEPTION_BITMAP, eb);
1259}
1260
8bf00a52
GN
1261static void clear_atomic_switch_msr_special(unsigned long entry,
1262 unsigned long exit)
1263{
1264 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1265 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1266}
1267
61d2ef2c
AK
1268static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1269{
1270 unsigned i;
1271 struct msr_autoload *m = &vmx->msr_autoload;
1272
8bf00a52
GN
1273 switch (msr) {
1274 case MSR_EFER:
1275 if (cpu_has_load_ia32_efer) {
1276 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1277 VM_EXIT_LOAD_IA32_EFER);
1278 return;
1279 }
1280 break;
1281 case MSR_CORE_PERF_GLOBAL_CTRL:
1282 if (cpu_has_load_perf_global_ctrl) {
1283 clear_atomic_switch_msr_special(
1284 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1285 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1286 return;
1287 }
1288 break;
110312c8
AK
1289 }
1290
61d2ef2c
AK
1291 for (i = 0; i < m->nr; ++i)
1292 if (m->guest[i].index == msr)
1293 break;
1294
1295 if (i == m->nr)
1296 return;
1297 --m->nr;
1298 m->guest[i] = m->guest[m->nr];
1299 m->host[i] = m->host[m->nr];
1300 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1301 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1302}
1303
8bf00a52
GN
1304static void add_atomic_switch_msr_special(unsigned long entry,
1305 unsigned long exit, unsigned long guest_val_vmcs,
1306 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1307{
1308 vmcs_write64(guest_val_vmcs, guest_val);
1309 vmcs_write64(host_val_vmcs, host_val);
1310 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1311 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1312}
1313
61d2ef2c
AK
1314static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1315 u64 guest_val, u64 host_val)
1316{
1317 unsigned i;
1318 struct msr_autoload *m = &vmx->msr_autoload;
1319
8bf00a52
GN
1320 switch (msr) {
1321 case MSR_EFER:
1322 if (cpu_has_load_ia32_efer) {
1323 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1324 VM_EXIT_LOAD_IA32_EFER,
1325 GUEST_IA32_EFER,
1326 HOST_IA32_EFER,
1327 guest_val, host_val);
1328 return;
1329 }
1330 break;
1331 case MSR_CORE_PERF_GLOBAL_CTRL:
1332 if (cpu_has_load_perf_global_ctrl) {
1333 add_atomic_switch_msr_special(
1334 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1335 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1336 GUEST_IA32_PERF_GLOBAL_CTRL,
1337 HOST_IA32_PERF_GLOBAL_CTRL,
1338 guest_val, host_val);
1339 return;
1340 }
1341 break;
110312c8
AK
1342 }
1343
61d2ef2c
AK
1344 for (i = 0; i < m->nr; ++i)
1345 if (m->guest[i].index == msr)
1346 break;
1347
e7fc6f93
GN
1348 if (i == NR_AUTOLOAD_MSRS) {
1349 printk_once(KERN_WARNING"Not enough mst switch entries. "
1350 "Can't add msr %x\n", msr);
1351 return;
1352 } else if (i == m->nr) {
61d2ef2c
AK
1353 ++m->nr;
1354 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1355 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1356 }
1357
1358 m->guest[i].index = msr;
1359 m->guest[i].value = guest_val;
1360 m->host[i].index = msr;
1361 m->host[i].value = host_val;
1362}
1363
33ed6329
AK
1364static void reload_tss(void)
1365{
33ed6329
AK
1366 /*
1367 * VT restores TR but not its size. Useless.
1368 */
d359192f 1369 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1370 struct desc_struct *descs;
33ed6329 1371
d359192f 1372 descs = (void *)gdt->address;
33ed6329
AK
1373 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1374 load_TR_desc();
33ed6329
AK
1375}
1376
92c0d900 1377static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1378{
3a34a881 1379 u64 guest_efer;
51c6cf66
AK
1380 u64 ignore_bits;
1381
f6801dff 1382 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1383
51c6cf66 1384 /*
0fa06071 1385 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK
1386 * outside long mode
1387 */
1388 ignore_bits = EFER_NX | EFER_SCE;
1389#ifdef CONFIG_X86_64
1390 ignore_bits |= EFER_LMA | EFER_LME;
1391 /* SCE is meaningful only in long mode on Intel */
1392 if (guest_efer & EFER_LMA)
1393 ignore_bits &= ~(u64)EFER_SCE;
1394#endif
51c6cf66
AK
1395 guest_efer &= ~ignore_bits;
1396 guest_efer |= host_efer & ignore_bits;
26bb0981 1397 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1398 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK
1399
1400 clear_atomic_switch_msr(vmx, MSR_EFER);
1401 /* On ept, can't emulate nx, and must switch nx atomically */
1402 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1403 guest_efer = vmx->vcpu.arch.efer;
1404 if (!(guest_efer & EFER_LMA))
1405 guest_efer &= ~EFER_LME;
1406 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1407 return false;
1408 }
1409
26bb0981 1410 return true;
51c6cf66
AK
1411}
1412
2d49ec72
GN
1413static unsigned long segment_base(u16 selector)
1414{
d359192f 1415 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN
1416 struct desc_struct *d;
1417 unsigned long table_base;
1418 unsigned long v;
1419
1420 if (!(selector & ~3))
1421 return 0;
1422
d359192f 1423 table_base = gdt->address;
2d49ec72
GN
1424
1425 if (selector & 4) { /* from ldt */
1426 u16 ldt_selector = kvm_read_ldt();
1427
1428 if (!(ldt_selector & ~3))
1429 return 0;
1430
1431 table_base = segment_base(ldt_selector);
1432 }
1433 d = (struct desc_struct *)(table_base + (selector & ~7));
1434 v = get_desc_base(d);
1435#ifdef CONFIG_X86_64
1436 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1437 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1438#endif
1439 return v;
1440}
1441
1442static inline unsigned long kvm_read_tr_base(void)
1443{
1444 u16 tr;
1445 asm("str %0" : "=g"(tr));
1446 return segment_base(tr);
1447}
1448
04d2cc77 1449static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1450{
04d2cc77 1451 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1452 int i;
04d2cc77 1453
a2fa3e9f 1454 if (vmx->host_state.loaded)
33ed6329
AK
1455 return;
1456
a2fa3e9f 1457 vmx->host_state.loaded = 1;
33ed6329
AK
1458 /*
1459 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1460 * allow segment selectors with cpl > 0 or ti == 1.
1461 */
d6e88aec 1462 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1463 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1464 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1465 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1466 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV
1467 vmx->host_state.fs_reload_needed = 0;
1468 } else {
33ed6329 1469 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1470 vmx->host_state.fs_reload_needed = 1;
33ed6329 1471 }
9581d442 1472 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH
1473 if (!(vmx->host_state.gs_sel & 7))
1474 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK
1475 else {
1476 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1477 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK
1478 }
1479
b2da15ac
AK
1480#ifdef CONFIG_X86_64
1481 savesegment(ds, vmx->host_state.ds_sel);
1482 savesegment(es, vmx->host_state.es_sel);
1483#endif
1484
33ed6329
AK
1485#ifdef CONFIG_X86_64
1486 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1487 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1488#else
a2fa3e9f
GH
1489 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1490 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1491#endif
707c0874
AK
1492
1493#ifdef CONFIG_X86_64
c8770e7b
AK
1494 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1495 if (is_long_mode(&vmx->vcpu))
44ea2b17 1496 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1497#endif
26bb0981
AK
1498 for (i = 0; i < vmx->save_nmsrs; ++i)
1499 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK
1500 vmx->guest_msrs[i].data,
1501 vmx->guest_msrs[i].mask);
33ed6329
AK
1502}
1503
a9b21b62 1504static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1505{
a2fa3e9f 1506 if (!vmx->host_state.loaded)
33ed6329
AK
1507 return;
1508
e1beb1d3 1509 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1510 vmx->host_state.loaded = 0;
c8770e7b
AK
1511#ifdef CONFIG_X86_64
1512 if (is_long_mode(&vmx->vcpu))
1513 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1514#endif
152d3f2f 1515 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1516 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1517#ifdef CONFIG_X86_64
9581d442 1518 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK
1519#else
1520 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1521#endif
33ed6329 1522 }
0a77fe4c
AK
1523 if (vmx->host_state.fs_reload_needed)
1524 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK
1525#ifdef CONFIG_X86_64
1526 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1527 loadsegment(ds, vmx->host_state.ds_sel);
1528 loadsegment(es, vmx->host_state.es_sel);
1529 }
b2da15ac 1530#endif
152d3f2f 1531 reload_tss();
44ea2b17 1532#ifdef CONFIG_X86_64
c8770e7b 1533 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1534#endif
b1a74bf8
SS
1535 /*
1536 * If the FPU is not active (through the host task or
1537 * the guest vcpu), then restore the cr0.TS bit.
1538 */
1539 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1540 stts();
3444d7da 1541 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK
1542}
1543
a9b21b62
AK
1544static void vmx_load_host_state(struct vcpu_vmx *vmx)
1545{
1546 preempt_disable();
1547 __vmx_load_host_state(vmx);
1548 preempt_enable();
1549}
1550
6aa8b732
AK
1551/*
1552 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1553 * vcpu mutex is already taken.
1554 */
15ad7146 1555static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1556{
a2fa3e9f 1557 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1558 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1559
4610c9cc
DX
1560 if (!vmm_exclusive)
1561 kvm_cpu_vmxon(phys_addr);
d462b819
NHE
1562 else if (vmx->loaded_vmcs->cpu != cpu)
1563 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1564
d462b819
NHE
1565 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1566 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1567 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK
1568 }
1569
d462b819 1570 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1571 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK
1572 unsigned long sysenter_esp;
1573
a8eeb04a 1574 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1575 local_irq_disable();
8f536b76 1576 crash_disable_local_vmclear(cpu);
5a560f8b
XG
1577
1578 /*
1579 * Read loaded_vmcs->cpu should be before fetching
1580 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1581 * See the comments in __loaded_vmcs_clear().
1582 */
1583 smp_rmb();
1584
d462b819
NHE
1585 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1586 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1587 crash_enable_local_vmclear(cpu);
92fe13be
DX
1588 local_irq_enable();
1589
6aa8b732
AK
1590 /*
1591 * Linux uses per-cpu TSS and GDT, so set these when switching
1592 * processors.
1593 */
d6e88aec 1594 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1595 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK
1596
1597 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1598 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1599 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1600 }
6aa8b732
AK
1601}
1602
1603static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1604{
a9b21b62 1605 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1606 if (!vmm_exclusive) {
d462b819
NHE
1607 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1608 vcpu->cpu = -1;
4610c9cc
DX
1609 kvm_cpu_vmxoff();
1610 }
6aa8b732
AK
1611}
1612
5fd86fcf
AK
1613static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1614{
81231c69
AK
1615 ulong cr0;
1616
5fd86fcf
AK
1617 if (vcpu->fpu_active)
1618 return;
1619 vcpu->fpu_active = 1;
81231c69
AK
1620 cr0 = vmcs_readl(GUEST_CR0);
1621 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1622 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1623 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1624 update_exception_bitmap(vcpu);
edcafe3c 1625 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE
1626 if (is_guest_mode(vcpu))
1627 vcpu->arch.cr0_guest_owned_bits &=
1628 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1629 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK
1630}
1631
edcafe3c
AK
1632static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1633
fe3ef05c
NHE
1634/*
1635 * Return the cr0 value that a nested guest would read. This is a combination
1636 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1637 * its hypervisor (cr0_read_shadow).
1638 */
1639static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1640{
1641 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1642 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1643}
1644static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1645{
1646 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1647 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1648}
1649
5fd86fcf
AK
1650static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1651{
36cf24e0
NHE
1652 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1653 * set this *before* calling this function.
1654 */
edcafe3c 1655 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1656 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1657 update_exception_bitmap(vcpu);
edcafe3c
AK
1658 vcpu->arch.cr0_guest_owned_bits = 0;
1659 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE
1660 if (is_guest_mode(vcpu)) {
1661 /*
1662 * L1's specified read shadow might not contain the TS bit,
1663 * so now that we turned on shadowing of this bit, we need to
1664 * set this bit of the shadow. Like in nested_vmx_run we need
1665 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1666 * up-to-date here because we just decached cr0.TS (and we'll
1667 * only update vmcs12->guest_cr0 on nested exit).
1668 */
1669 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1670 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1671 (vcpu->arch.cr0 & X86_CR0_TS);
1672 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1673 } else
1674 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK
1675}
1676
6aa8b732
AK
1677static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1678{
78ac8b47 1679 unsigned long rflags, save_rflags;
345dcaa8 1680
6de12732
AK
1681 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1682 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1683 rflags = vmcs_readl(GUEST_RFLAGS);
1684 if (to_vmx(vcpu)->rmode.vm86_active) {
1685 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1686 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1687 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 }
1689 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1690 }
6de12732 1691 return to_vmx(vcpu)->rflags;
6aa8b732
AK
1692}
1693
1694static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1695{
6de12732 1696 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1697 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1698 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK
1699 if (to_vmx(vcpu)->rmode.vm86_active) {
1700 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1701 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1702 }
6aa8b732
AK
1703 vmcs_writel(GUEST_RFLAGS, rflags);
1704}
1705
2809f5d2
GC
1706static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1707{
1708 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1709 int ret = 0;
1710
1711 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1712 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1713 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1714 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC
1715
1716 return ret & mask;
1717}
1718
1719static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1720{
1721 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1722 u32 interruptibility = interruptibility_old;
1723
1724 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1725
48005f64 1726 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1727 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1728 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC
1729 interruptibility |= GUEST_INTR_STATE_STI;
1730
1731 if ((interruptibility != interruptibility_old))
1732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1733}
1734
6aa8b732
AK
1735static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1736{
1737 unsigned long rip;
6aa8b732 1738
5fdbf976 1739 rip = kvm_rip_read(vcpu);
6aa8b732 1740 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1741 kvm_rip_write(vcpu, rip);
6aa8b732 1742
2809f5d2
GC
1743 /* skipping an emulated instruction also counts */
1744 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK
1745}
1746
0b6ac343
NHE
1747/*
1748 * KVM wants to inject page-faults which it got to the guest. This function
1749 * checks whether in a nested guest, we need to inject them to L1 or L2.
1750 * This function assumes it is called with the exit reason in vmcs02 being
1751 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1752 * is running).
1753 */
1754static int nested_pf_handled(struct kvm_vcpu *vcpu)
1755{
1756 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1757
1758 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1759 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE
1760 return 0;
1761
1762 nested_vmx_vmexit(vcpu);
1763 return 1;
1764}
1765
298101da 1766static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
1767 bool has_error_code, u32 error_code,
1768 bool reinject)
298101da 1769{
77ab6db0 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1771 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1772
0b6ac343
NHE
1773 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1774 nested_pf_handled(vcpu))
1775 return;
1776
8ab2d2e2 1777 if (has_error_code) {
77ab6db0 1778 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK
1779 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1780 }
77ab6db0 1781
7ffd92c5 1782 if (vmx->rmode.vm86_active) {
71f9833b
SH
1783 int inc_eip = 0;
1784 if (kvm_exception_is_soft(nr))
1785 inc_eip = vcpu->arch.event_exit_inst_len;
1786 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1787 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK
1788 return;
1789 }
1790
66fd3f7f
GN
1791 if (kvm_exception_is_soft(nr)) {
1792 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1793 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK
1794 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1795 } else
1796 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1797
1798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK
1799}
1800
4e47c7a6
SY
1801static bool vmx_rdtscp_supported(void)
1802{
1803 return cpu_has_vmx_rdtscp();
1804}
1805
ad756a16
MJ
1806static bool vmx_invpcid_supported(void)
1807{
1808 return cpu_has_vmx_invpcid() && enable_ept;
1809}
1810
a75beee6
ED
1811/*
1812 * Swap MSR entry in host/guest MSR entry array.
1813 */
8b9cf98c 1814static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1815{
26bb0981 1816 struct shared_msr_entry tmp;
a2fa3e9f
GH
1817
1818 tmp = vmx->guest_msrs[to];
1819 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1820 vmx->guest_msrs[from] = tmp;
a75beee6
ED
1821}
1822
e38aea3e
AK
1823/*
1824 * Set up the vmcs to automatically save and restore system
1825 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1826 * mode, as fiddling with msrs is very expensive.
1827 */
8b9cf98c 1828static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1829{
26bb0981 1830 int save_nmsrs, index;
5897297b 1831 unsigned long *msr_bitmap;
e38aea3e 1832
a75beee6
ED
1833 save_nmsrs = 0;
1834#ifdef CONFIG_X86_64
8b9cf98c 1835 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1836 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1837 if (index >= 0)
8b9cf98c
RR
1838 move_msr_up(vmx, index, save_nmsrs++);
1839 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1840 if (index >= 0)
8b9cf98c
RR
1841 move_msr_up(vmx, index, save_nmsrs++);
1842 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1843 if (index >= 0)
8b9cf98c 1844 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY
1845 index = __find_msr_index(vmx, MSR_TSC_AUX);
1846 if (index >= 0 && vmx->rdtscp_enabled)
1847 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1848 /*
8c06585d 1849 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED
1850 * if efer.sce is enabled.
1851 */
8c06585d 1852 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1853 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1854 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED
1855 }
1856#endif
92c0d900
AK
1857 index = __find_msr_index(vmx, MSR_EFER);
1858 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1859 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1860
26bb0981 1861 vmx->save_nmsrs = save_nmsrs;
5897297b
AK
1862
1863 if (cpu_has_vmx_msr_bitmap()) {
1864 if (is_long_mode(&vmx->vcpu))
1865 msr_bitmap = vmx_msr_bitmap_longmode;
1866 else
1867 msr_bitmap = vmx_msr_bitmap_legacy;
1868
1869 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1870 }
e38aea3e
AK
1871}
1872
6aa8b732
AK
1873/*
1874 * reads and returns guest's timestamp counter "register"
1875 * guest_tsc = host_tsc + tsc_offset -- 21.3
1876 */
1877static u64 guest_read_tsc(void)
1878{
1879 u64 host_tsc, tsc_offset;
1880
1881 rdtscll(host_tsc);
1882 tsc_offset = vmcs_read64(TSC_OFFSET);
1883 return host_tsc + tsc_offset;
1884}
1885
d5c1785d
NHE
1886/*
1887 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1888 * counter, even if a nested guest (L2) is currently running.
1889 */
886b470c 1890u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1891{
886b470c 1892 u64 tsc_offset;
d5c1785d 1893
d5c1785d
NHE
1894 tsc_offset = is_guest_mode(vcpu) ?
1895 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1896 vmcs_read64(TSC_OFFSET);
1897 return host_tsc + tsc_offset;
1898}
1899
4051b188 1900/*
cc578287
ZA
1901 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1902 * software catchup for faster rates on slower CPUs.
4051b188 1903 */
cc578287 1904static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1905{
cc578287
ZA
1906 if (!scale)
1907 return;
1908
1909 if (user_tsc_khz > tsc_khz) {
1910 vcpu->arch.tsc_catchup = 1;
1911 vcpu->arch.tsc_always_catchup = 1;
1912 } else
1913 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR
1914}
1915
ba904635
WA
1916static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1917{
1918 return vmcs_read64(TSC_OFFSET);
1919}
1920
6aa8b732 1921/*
99e3e30a 1922 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1923 */
99e3e30a 1924static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1925{
27fc51b2 1926 if (is_guest_mode(vcpu)) {
7991825b 1927 /*
27fc51b2
NHE
1928 * We're here if L1 chose not to trap WRMSR to TSC. According
1929 * to the spec, this should set L1's TSC; The offset that L1
1930 * set for L2 remains unchanged, and still needs to be added
1931 * to the newly set TSC to get L2's TSC.
7991825b 1932 */
27fc51b2
NHE
1933 struct vmcs12 *vmcs12;
1934 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1935 /* recalculate vmcs02.TSC_OFFSET: */
1936 vmcs12 = get_vmcs12(vcpu);
1937 vmcs_write64(TSC_OFFSET, offset +
1938 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1939 vmcs12->tsc_offset : 0));
1940 } else {
1941 vmcs_write64(TSC_OFFSET, offset);
1942 }
6aa8b732
AK
1943}
1944
f1e2b260 1945static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA
1946{
1947 u64 offset = vmcs_read64(TSC_OFFSET);
1948 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE
1949 if (is_guest_mode(vcpu)) {
1950 /* Even when running L2, the adjustment needs to apply to L1 */
1951 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1952 }
e48672fa
ZA
1953}
1954
857e4099
JR
1955static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1956{
1957 return target_tsc - native_read_tsc();
1958}
1959
801d3424
NHE
1960static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1961{
1962 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1963 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1964}
1965
1966/*
1967 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1968 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1969 * all guests if the "nested" module option is off, and can also be disabled
1970 * for a single guest by disabling its VMX cpuid bit.
1971 */
1972static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1973{
1974 return nested && guest_cpuid_has_vmx(vcpu);
1975}
1976
b87a51ae
NHE
1977/*
1978 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1979 * returned for the various VMX controls MSRs when nested VMX is enabled.
1980 * The same values should also be used to verify that vmcs12 control fields are
1981 * valid during nested entry from L1 to L2.
1982 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1983 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1984 * bit in the high half is on if the corresponding bit in the control field
1985 * may be on. See also vmx_control_verify().
1986 * TODO: allow these variables to be modified (downgraded) by module options
1987 * or other means.
1988 */
1989static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1990static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1991static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1992static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1993static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1994static __init void nested_vmx_setup_ctls_msrs(void)
1995{
1996 /*
1997 * Note that as a general rule, the high half of the MSRs (bits in
1998 * the control fields which may be 1) should be initialized by the
1999 * intersection of the underlying hardware's MSR (i.e., features which
2000 * can be supported) and the list of features we want to expose -
2001 * because they are known to be properly supported in our code.
2002 * Also, usually, the low half of the MSRs (bits which must be 1) can
2003 * be set to 0, meaning that L1 may turn off any of these bits. The
2004 * reason is that if one of these bits is necessary, it will appear
2005 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2006 * fields of vmcs01 and vmcs02, will turn these bits off - and
2007 * nested_vmx_exit_handled() will not pass related exits to L1.
2008 * These rules have exceptions below.
2009 */
2010
2011 /* pin-based controls */
2012 /*
2013 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2014 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2015 */
2016 nested_vmx_pinbased_ctls_low = 0x16 ;
2017 nested_vmx_pinbased_ctls_high = 0x16 |
2018 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2019 PIN_BASED_VIRTUAL_NMIS;
2020
2021 /* exit controls */
2022 nested_vmx_exit_ctls_low = 0;
b6f1250e 2023 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE
2024#ifdef CONFIG_X86_64
2025 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2026#else
2027 nested_vmx_exit_ctls_high = 0;
2028#endif
2029
2030 /* entry controls */
2031 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2032 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2033 nested_vmx_entry_ctls_low = 0;
2034 nested_vmx_entry_ctls_high &=
2035 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2036
2037 /* cpu-based controls */
2038 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2039 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2040 nested_vmx_procbased_ctls_low = 0;
2041 nested_vmx_procbased_ctls_high &=
2042 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2043 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2044 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2045 CPU_BASED_CR3_STORE_EXITING |
2046#ifdef CONFIG_X86_64
2047 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2048#endif
2049 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2050 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2051 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE
2052 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2053 /*
2054 * We can allow some features even when not supported by the
2055 * hardware. For example, L1 can specify an MSR bitmap - and we
2056 * can use it to avoid exits to L1 - even when L0 runs L2
2057 * without MSR bitmaps.
2058 */
2059 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2060
2061 /* secondary cpu-based controls */
2062 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2063 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2064 nested_vmx_secondary_ctls_low = 0;
2065 nested_vmx_secondary_ctls_high &=
2066 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2067}
2068
2069static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2070{
2071 /*
2072 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2073 */
2074 return ((control & high) | low) == control;
2075}
2076
2077static inline u64 vmx_control_msr(u32 low, u32 high)
2078{
2079 return low | ((u64)high << 32);
2080}
2081
2082/*
2083 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2084 * also let it use VMX-specific MSRs.
2085 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2086 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2087 * like all other MSRs).
2088 */
2089static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2090{
2091 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2092 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2093 /*
2094 * According to the spec, processors which do not support VMX
2095 * should throw a #GP(0) when VMX capability MSRs are read.
2096 */
2097 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2098 return 1;
2099 }
2100
2101 switch (msr_index) {
2102 case MSR_IA32_FEATURE_CONTROL:
2103 *pdata = 0;
2104 break;
2105 case MSR_IA32_VMX_BASIC:
2106 /*
2107 * This MSR reports some information about VMX support. We
2108 * should return information about the VMX we emulate for the
2109 * guest, and the VMCS structure we give it - not about the
2110 * VMX support of the underlying hardware.
2111 */
2112 *pdata = VMCS12_REVISION |
2113 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2114 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2115 break;
2116 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2117 case MSR_IA32_VMX_PINBASED_CTLS:
2118 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2119 nested_vmx_pinbased_ctls_high);
2120 break;
2121 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2122 case MSR_IA32_VMX_PROCBASED_CTLS:
2123 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2124 nested_vmx_procbased_ctls_high);
2125 break;
2126 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2127 case MSR_IA32_VMX_EXIT_CTLS:
2128 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2129 nested_vmx_exit_ctls_high);
2130 break;
2131 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2132 case MSR_IA32_VMX_ENTRY_CTLS:
2133 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2134 nested_vmx_entry_ctls_high);
2135 break;
2136 case MSR_IA32_VMX_MISC:
2137 *pdata = 0;
2138 break;
2139 /*
2140 * These MSRs specify bits which the guest must keep fixed (on or off)
2141 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2142 * We picked the standard core2 setting.
2143 */
2144#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2145#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2146 case MSR_IA32_VMX_CR0_FIXED0:
2147 *pdata = VMXON_CR0_ALWAYSON;
2148 break;
2149 case MSR_IA32_VMX_CR0_FIXED1:
2150 *pdata = -1ULL;
2151 break;
2152 case MSR_IA32_VMX_CR4_FIXED0:
2153 *pdata = VMXON_CR4_ALWAYSON;
2154 break;
2155 case MSR_IA32_VMX_CR4_FIXED1:
2156 *pdata = -1ULL;
2157 break;
2158 case MSR_IA32_VMX_VMCS_ENUM:
2159 *pdata = 0x1f;
2160 break;
2161 case MSR_IA32_VMX_PROCBASED_CTLS2:
2162 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2163 nested_vmx_secondary_ctls_high);
2164 break;
2165 case MSR_IA32_VMX_EPT_VPID_CAP:
2166 /* Currently, no nested ept or nested vpid */
2167 *pdata = 0;
2168 break;
2169 default:
2170 return 0;
2171 }
2172
2173 return 1;
2174}
2175
2176static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2177{
2178 if (!nested_vmx_allowed(vcpu))
2179 return 0;
2180
2181 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2182 /* TODO: the right thing. */
2183 return 1;
2184 /*
2185 * No need to treat VMX capability MSRs specially: If we don't handle
2186 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2187 */
2188 return 0;
2189}
2190
6aa8b732
AK
2191/*
2192 * Reads an msr value (of 'msr_index') into 'pdata'.
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2195 */
2196static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2197{
2198 u64 data;
26bb0981 2199 struct shared_msr_entry *msr;
6aa8b732
AK
2200
2201 if (!pdata) {
2202 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2203 return -EINVAL;
2204 }
2205
2206 switch (msr_index) {
05b3e0c2 2207#ifdef CONFIG_X86_64
6aa8b732
AK
2208 case MSR_FS_BASE:
2209 data = vmcs_readl(GUEST_FS_BASE);
2210 break;
2211 case MSR_GS_BASE:
2212 data = vmcs_readl(GUEST_GS_BASE);
2213 break;
44ea2b17
AK
2214 case MSR_KERNEL_GS_BASE:
2215 vmx_load_host_state(to_vmx(vcpu));
2216 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2217 break;
26bb0981 2218#endif
6aa8b732 2219 case MSR_EFER:
3bab1f5d 2220 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2221 case MSR_IA32_TSC:
6aa8b732
AK
2222 data = guest_read_tsc();
2223 break;
2224 case MSR_IA32_SYSENTER_CS:
2225 data = vmcs_read32(GUEST_SYSENTER_CS);
2226 break;
2227 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2228 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK
2229 break;
2230 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2231 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2232 break;
4e47c7a6
SY
2233 case MSR_TSC_AUX:
2234 if (!to_vmx(vcpu)->rdtscp_enabled)
2235 return 1;
2236 /* Otherwise falls through */
6aa8b732 2237 default:
b87a51ae
NHE
2238 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2239 return 0;
8b9cf98c 2240 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK
2241 if (msr) {
2242 data = msr->data;
2243 break;
6aa8b732 2244 }
3bab1f5d 2245 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK
2246 }
2247
2248 *pdata = data;
2249 return 0;
2250}
2251
2252/*
2253 * Writes msr value into into the appropriate "register".
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
8fe8ab46 2257static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2258{
a2fa3e9f 2259 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2260 struct shared_msr_entry *msr;
2cc51560 2261 int ret = 0;
8fe8ab46
WA
2262 u32 msr_index = msr_info->index;
2263 u64 data = msr_info->data;
2cc51560 2264
6aa8b732 2265 switch (msr_index) {
3bab1f5d 2266 case MSR_EFER:
8fe8ab46 2267 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2268 break;
16175a79 2269#ifdef CONFIG_X86_64
6aa8b732 2270 case MSR_FS_BASE:
2fb92db1 2271 vmx_segment_cache_clear(vmx);
6aa8b732
AK
2272 vmcs_writel(GUEST_FS_BASE, data);
2273 break;
2274 case MSR_GS_BASE:
2fb92db1 2275 vmx_segment_cache_clear(vmx);
6aa8b732
AK
2276 vmcs_writel(GUEST_GS_BASE, data);
2277 break;
44ea2b17
AK
2278 case MSR_KERNEL_GS_BASE:
2279 vmx_load_host_state(vmx);
2280 vmx->msr_guest_kernel_gs_base = data;
2281 break;
6aa8b732
AK
2282#endif
2283 case MSR_IA32_SYSENTER_CS:
2284 vmcs_write32(GUEST_SYSENTER_CS, data);
2285 break;
2286 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2287 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK
2288 break;
2289 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2290 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2291 break;
af24a4e4 2292 case MSR_IA32_TSC:
8fe8ab46 2293 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2294 break;
468d472f
SY
2295 case MSR_IA32_CR_PAT:
2296 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2297 vmcs_write64(GUEST_IA32_PAT, data);
2298 vcpu->arch.pat = data;
2299 break;
2300 }
8fe8ab46 2301 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2302 break;
ba904635
WA
2303 case MSR_IA32_TSC_ADJUST:
2304 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY
2305 break;
2306 case MSR_TSC_AUX:
2307 if (!vmx->rdtscp_enabled)
2308 return 1;
2309 /* Check reserved bit, higher 32 bits should be zero */
2310 if ((data >> 32) != 0)
2311 return 1;
2312 /* Otherwise falls through */
6aa8b732 2313 default:
b87a51ae
NHE
2314 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2315 break;
8b9cf98c 2316 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK
2317 if (msr) {
2318 msr->data = data;
2225fd56
AK
2319 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2320 preempt_disable();
9ee73970
AK
2321 kvm_set_shared_msr(msr->index, msr->data,
2322 msr->mask);
2225fd56
AK
2323 preempt_enable();
2324 }
3bab1f5d 2325 break;
6aa8b732 2326 }
8fe8ab46 2327 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK
2328 }
2329
2cc51560 2330 return ret;
6aa8b732
AK
2331}
2332
5fdbf976 2333static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2334{
5fdbf976
MT
2335 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2336 switch (reg) {
2337 case VCPU_REGS_RSP:
2338 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2339 break;
2340 case VCPU_REGS_RIP:
2341 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2342 break;
6de4f3ad
AK
2343 case VCPU_EXREG_PDPTR:
2344 if (enable_ept)
2345 ept_save_pdptrs(vcpu);
2346 break;
5fdbf976
MT
2347 default:
2348 break;
2349 }
6aa8b732
AK
2350}
2351
6aa8b732
AK
2352static __init int cpu_has_kvm_support(void)
2353{
6210e37b 2354 return cpu_has_vmx();
6aa8b732
AK
2355}
2356
2357static __init int vmx_disabled_by_bios(void)
2358{
2359 u64 msr;
2360
2361 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2362 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2363 /* launched w/ TXT and VMX disabled */
cafd6659
SW
2364 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2365 && tboot_enabled())
2366 return 1;
23f3e991 2367 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2368 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2369 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW
2370 && !tboot_enabled()) {
2371 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2372 "activate TXT before enabling KVM\n");
cafd6659 2373 return 1;
f9335afe 2374 }
23f3e991
JC
2375 /* launched w/o TXT and VMX disabled */
2376 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2377 && !tboot_enabled())
2378 return 1;
cafd6659
SW
2379 }
2380
2381 return 0;
6aa8b732
AK
2382}
2383
7725b894
DX
2384static void kvm_cpu_vmxon(u64 addr)
2385{
2386 asm volatile (ASM_VMX_VMXON_RAX
2387 : : "a"(&addr), "m"(addr)
2388 : "memory", "cc");
2389}
2390
10474ae8 2391static int hardware_enable(void *garbage)
6aa8b732
AK
2392{
2393 int cpu = raw_smp_processor_id();
2394 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2395 u64 old, test_bits;
6aa8b732 2396
10474ae8
AG
2397 if (read_cr4() & X86_CR4_VMXE)
2398 return -EBUSY;
2399
d462b819 2400 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY
2401
2402 /*
2403 * Now we can enable the vmclear operation in kdump
2404 * since the loaded_vmcss_on_cpu list on this cpu
2405 * has been initialized.
2406 *
2407 * Though the cpu is not in VMX operation now, there
2408 * is no problem to enable the vmclear operation
2409 * for the loaded_vmcss_on_cpu list is empty!
2410 */
2411 crash_enable_local_vmclear(cpu);
2412
6aa8b732 2413 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW
2414
2415 test_bits = FEATURE_CONTROL_LOCKED;
2416 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2417 if (tboot_enabled())
2418 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2419
2420 if ((old & test_bits) != test_bits) {
6aa8b732 2421 /* enable and lock */
cafd6659
SW
2422 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2423 }
66aee91a 2424 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2425
4610c9cc
DX
2426 if (vmm_exclusive) {
2427 kvm_cpu_vmxon(phys_addr);
2428 ept_sync_global();
2429 }
10474ae8 2430
3444d7da
AK
2431 store_gdt(&__get_cpu_var(host_gdt));
2432
10474ae8 2433 return 0;
6aa8b732
AK
2434}
2435
d462b819 2436static void vmclear_local_loaded_vmcss(void)
543e4243
AK
2437{
2438 int cpu = raw_smp_processor_id();
d462b819 2439 struct loaded_vmcs *v, *n;
543e4243 2440
d462b819
NHE
2441 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2442 loaded_vmcss_on_cpu_link)
2443 __loaded_vmcs_clear(v);
543e4243
AK
2444}
2445
710ff4a8
EH
2446
2447/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2448 * tricks.
2449 */
2450static void kvm_cpu_vmxoff(void)
6aa8b732 2451{
4ecac3fd 2452 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK
2453}
2454
710ff4a8
EH
2455static void hardware_disable(void *garbage)
2456{
4610c9cc 2457 if (vmm_exclusive) {
d462b819 2458 vmclear_local_loaded_vmcss();
4610c9cc
DX
2459 kvm_cpu_vmxoff();
2460 }
7725b894 2461 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH
2462}
2463
1c3d14fe 2464static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2465 u32 msr, u32 *result)
1c3d14fe
YS
2466{
2467 u32 vmx_msr_low, vmx_msr_high;
2468 u32 ctl = ctl_min | ctl_opt;
2469
2470 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2471
2472 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2473 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2474
2475 /* Ensure minimum (required) set of control bits are supported. */
2476 if (ctl_min & ~ctl)
002c7f7c 2477 return -EIO;
1c3d14fe
YS
2478
2479 *result = ctl;
2480 return 0;
2481}
2482
110312c8
AK
2483static __init bool allow_1_setting(u32 msr, u32 ctl)
2484{
2485 u32 vmx_msr_low, vmx_msr_high;
2486
2487 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2488 return vmx_msr_high & ctl;
2489}
2490
002c7f7c 2491static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK
2492{
2493 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2494 u32 min, opt, min2, opt2;
1c3d14fe
YS
2495 u32 _pin_based_exec_control = 0;
2496 u32 _cpu_based_exec_control = 0;
f78e0e2e 2497 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS
2498 u32 _vmexit_control = 0;
2499 u32 _vmentry_control = 0;
2500
2501 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2502 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS
2503 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2504 &_pin_based_exec_control) < 0)
002c7f7c 2505 return -EIO;
1c3d14fe 2506
10166744 2507 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS
2508#ifdef CONFIG_X86_64
2509 CPU_BASED_CR8_LOAD_EXITING |
2510 CPU_BASED_CR8_STORE_EXITING |
2511#endif
d56f546d
SY
2512 CPU_BASED_CR3_LOAD_EXITING |
2513 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS
2514 CPU_BASED_USE_IO_BITMAPS |
2515 CPU_BASED_MOV_DR_EXITING |
a7052897 2516 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY
2517 CPU_BASED_MWAIT_EXITING |
2518 CPU_BASED_MONITOR_EXITING |
fee84b07
AK
2519 CPU_BASED_INVLPG_EXITING |
2520 CPU_BASED_RDPMC_EXITING;
443381a8 2521
f78e0e2e 2522 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2523 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2524 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS
2525 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2526 &_cpu_based_exec_control) < 0)
002c7f7c 2527 return -EIO;
6e5d865c
YS
2528#ifdef CONFIG_X86_64
2529 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2530 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2531 ~CPU_BASED_CR8_STORE_EXITING;
2532#endif
f78e0e2e 2533 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY
2534 min2 = 0;
2535 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2536 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2537 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2538 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2539 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2540 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ
2541 SECONDARY_EXEC_RDTSCP |
2542 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY
2543 if (adjust_vmx_controls(min2, opt2,
2544 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY
2545 &_cpu_based_2nd_exec_control) < 0)
2546 return -EIO;
2547 }
2548#ifndef CONFIG_X86_64
2549 if (!(_cpu_based_2nd_exec_control &
2550 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2551 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2552#endif
d56f546d 2553 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT
2554 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2555 enabled */
5fff7d27
GN
2556 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2557 CPU_BASED_CR3_STORE_EXITING |
2558 CPU_BASED_INVLPG_EXITING);
d56f546d
SY
2559 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2560 vmx_capability.ept, vmx_capability.vpid);
2561 }
1c3d14fe
YS
2562
2563 min = 0;
2564#ifdef CONFIG_X86_64
2565 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2566#endif
468d472f 2567 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS
2568 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2569 &_vmexit_control) < 0)
002c7f7c 2570 return -EIO;
1c3d14fe 2571
468d472f
SY
2572 min = 0;
2573 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS
2574 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2575 &_vmentry_control) < 0)
002c7f7c 2576 return -EIO;
6aa8b732 2577
c68876fd 2578 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS
2579
2580 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2581 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2582 return -EIO;
1c3d14fe
YS
2583
2584#ifdef CONFIG_X86_64
2585 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2586 if (vmx_msr_high & (1u<<16))
002c7f7c 2587 return -EIO;
1c3d14fe
YS
2588#endif
2589
2590 /* Require Write-Back (WB) memory type for VMCS accesses. */
2591 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2592 return -EIO;
1c3d14fe 2593
002c7f7c
YS
2594 vmcs_conf->size = vmx_msr_high & 0x1fff;
2595 vmcs_conf->order = get_order(vmcs_config.size);
2596 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2597
002c7f7c
YS
2598 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2599 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2600 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS
2601 vmcs_conf->vmexit_ctrl = _vmexit_control;
2602 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2603
110312c8
AK
2604 cpu_has_load_ia32_efer =
2605 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2606 VM_ENTRY_LOAD_IA32_EFER)
2607 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2608 VM_EXIT_LOAD_IA32_EFER);
2609
8bf00a52
GN
2610 cpu_has_load_perf_global_ctrl =
2611 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2612 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2613 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2614 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2615
2616 /*
2617 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2618 * but due to arrata below it can't be used. Workaround is to use
2619 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2620 *
2621 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2622 *
2623 * AAK155 (model 26)
2624 * AAP115 (model 30)
2625 * AAT100 (model 37)
2626 * BC86,AAY89,BD102 (model 44)
2627 * BA97 (model 46)
2628 *
2629 */
2630 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2631 switch (boot_cpu_data.x86_model) {
2632 case 26:
2633 case 30:
2634 case 37:
2635 case 44:
2636 case 46:
2637 cpu_has_load_perf_global_ctrl = false;
2638 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2639 "does not work properly. Using workaround\n");
2640 break;
2641 default:
2642 break;
2643 }
2644 }
2645
1c3d14fe 2646 return 0;
c68876fd 2647}
6aa8b732
AK
2648
2649static struct vmcs *alloc_vmcs_cpu(int cpu)
2650{
2651 int node = cpu_to_node(cpu);
2652 struct page *pages;
2653 struct vmcs *vmcs;
2654
6484eb3e 2655 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK
2656 if (!pages)
2657 return NULL;
2658 vmcs = page_address(pages);
1c3d14fe
YS
2659 memset(vmcs, 0, vmcs_config.size);
2660 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK
2661 return vmcs;
2662}
2663
2664static struct vmcs *alloc_vmcs(void)
2665{
d3b2c338 2666 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK
2667}
2668
2669static void free_vmcs(struct vmcs *vmcs)
2670{
1c3d14fe 2671 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK
2672}
2673
d462b819
NHE
2674/*
2675 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2676 */
2677static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2678{
2679 if (!loaded_vmcs->vmcs)
2680 return;
2681 loaded_vmcs_clear(loaded_vmcs);
2682 free_vmcs(loaded_vmcs->vmcs);
2683 loaded_vmcs->vmcs = NULL;
2684}
2685
39959588 2686static void free_kvm_area(void)
6aa8b732
AK
2687{
2688 int cpu;
2689
3230bb47 2690 for_each_possible_cpu(cpu) {
6aa8b732 2691 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA
2692 per_cpu(vmxarea, cpu) = NULL;
2693 }
6aa8b732
AK
2694}
2695
6aa8b732
AK
2696static __init int alloc_kvm_area(void)
2697{
2698 int cpu;
2699
3230bb47 2700 for_each_possible_cpu(cpu) {
6aa8b732
AK
2701 struct vmcs *vmcs;
2702
2703 vmcs = alloc_vmcs_cpu(cpu);
2704 if (!vmcs) {
2705 free_kvm_area();
2706 return -ENOMEM;
2707 }
2708
2709 per_cpu(vmxarea, cpu) = vmcs;
2710 }
2711 return 0;
2712}
2713
2714static __init int hardware_setup(void)
2715{
002c7f7c
YS
2716 if (setup_vmcs_config(&vmcs_config) < 0)
2717 return -EIO;
50a37eb4
JR
2718
2719 if (boot_cpu_has(X86_FEATURE_NX))
2720 kvm_enable_efer_bits(EFER_NX);
2721
93ba03c2
SY
2722 if (!cpu_has_vmx_vpid())
2723 enable_vpid = 0;
2724
4bc9b982
SY
2725 if (!cpu_has_vmx_ept() ||
2726 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2727 enable_ept = 0;
3a624e29 2728 enable_unrestricted_guest = 0;
83c3a331 2729 enable_ept_ad_bits = 0;
3a624e29
NK
2730 }
2731
83c3a331
XH
2732 if (!cpu_has_vmx_ept_ad_bits())
2733 enable_ept_ad_bits = 0;
2734
3a624e29
NK
2735 if (!cpu_has_vmx_unrestricted_guest())
2736 enable_unrestricted_guest = 0;
93ba03c2
SY
2737
2738 if (!cpu_has_vmx_flexpriority())
2739 flexpriority_enabled = 0;
2740
95ba8273
GN
2741 if (!cpu_has_vmx_tpr_shadow())
2742 kvm_x86_ops->update_cr8_intercept = NULL;
2743
54dee993
MT
2744 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2745 kvm_disable_largepages();
2746
4b8d54f9
ZE
2747 if (!cpu_has_vmx_ple())
2748 ple_gap = 0;
2749
b87a51ae
NHE
2750 if (nested)
2751 nested_vmx_setup_ctls_msrs();
2752
6aa8b732
AK
2753 return alloc_kvm_area();
2754}
2755
2756static __exit void hardware_unsetup(void)
2757{
2758 free_kvm_area();
2759}
2760
f5f7b2fe 2761static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2762{
772e0318 2763 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2764 struct kvm_segment tmp = *save;
6aa8b732 2765
c865c43d
AK
2766 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2767 tmp.base = vmcs_readl(sf->base);
2768 tmp.selector = vmcs_read16(sf->selector);
a4d3326c 2769 tmp.dpl = tmp.selector & SELECTOR_RPL_MASK;
c865c43d 2770 tmp.s = 1;
6aa8b732 2771 }
c865c43d 2772 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK
2773}
2774
2775static void enter_pmode(struct kvm_vcpu *vcpu)
2776{
2777 unsigned long flags;
a89a8fb9 2778 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2779
a89a8fb9 2780 vmx->emulation_required = 1;
7ffd92c5 2781 vmx->rmode.vm86_active = 0;
6aa8b732 2782
2fb92db1
AK
2783 vmx_segment_cache_clear(vmx);
2784
f5f7b2fe 2785 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK
2786
2787 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK
2788 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2789 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK
2790 vmcs_writel(GUEST_RFLAGS, flags);
2791
66aee91a
RR
2792 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2793 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK
2794
2795 update_exception_bitmap(vcpu);
2796
a89a8fb9
MG
2797 if (emulate_invalid_guest_state)
2798 return;
2799
f5f7b2fe
AK
2800 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2801 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2802 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2803 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2804
2fb92db1
AK
2805 vmx_segment_cache_clear(vmx);
2806
6aa8b732
AK
2807 vmcs_write16(GUEST_SS_SELECTOR, 0);
2808 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2809
2810 vmcs_write16(GUEST_CS_SELECTOR,
2811 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2812 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2813}
2814
d77c26fc 2815static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2816{
bfc6d222 2817 if (!kvm->arch.tss_addr) {
bc6678a3 2818 struct kvm_memslots *slots;
28a37544 2819 struct kvm_memory_slot *slot;
bc6678a3
MT
2820 gfn_t base_gfn;
2821
90d83dc3 2822 slots = kvm_memslots(kvm);
28a37544
XG
2823 slot = id_to_memslot(slots, 0);
2824 base_gfn = slot->base_gfn + slot->npages - 3;
2825
cbc94022
IE
2826 return base_gfn << PAGE_SHIFT;
2827 }
bfc6d222 2828 return kvm->arch.tss_addr;
6aa8b732
AK
2829}
2830
f5f7b2fe 2831static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2832{
772e0318 2833 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2834
15b00f32 2835 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2836 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK
2837 vmcs_write32(sf->limit, 0xffff);
2838 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN
2839 if (save->base & 0xf)
2840 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2841 " aligned when entering protected mode (seg=%d)",
2842 seg);
6aa8b732
AK
2843}
2844
2845static void enter_rmode(struct kvm_vcpu *vcpu)
2846{
2847 unsigned long flags;
a89a8fb9 2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2849 struct kvm_segment var;
6aa8b732 2850
3a624e29
NK
2851 if (enable_unrestricted_guest)
2852 return;
2853
f5f7b2fe
AK
2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN
2859 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2860 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2861
a89a8fb9 2862 vmx->emulation_required = 1;
7ffd92c5 2863 vmx->rmode.vm86_active = 1;
6aa8b732 2864
baa7e81e 2865
776e58ea
GN
2866 /*
2867 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2868 * vcpu. Call it here with phys address pointing 16M below 4G.
2869 */
2870 if (!vcpu->kvm->arch.tss_addr) {
2871 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2872 "called before entering vcpu\n");
2873 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2874 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2875 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2876 }
2877
2fb92db1
AK
2878 vmx_segment_cache_clear(vmx);
2879
6aa8b732 2880 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2881 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK
2882 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2883
2884 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2885 vmx->rmode.save_rflags = flags;
6aa8b732 2886
053de044 2887 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK
2888
2889 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2890 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK
2891 update_exception_bitmap(vcpu);
2892
a89a8fb9
MG
2893 if (emulate_invalid_guest_state)
2894 goto continue_rmode;
2895
b246dd5d
OW
2896 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2897 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2898
2899 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2900 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2901
2902 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2903 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2904
2905 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2906 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2907
b246dd5d
OW
2908 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2909 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2910
b246dd5d
OW
2911 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2912 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2913
a89a8fb9 2914continue_rmode:
8668a3c4 2915 kvm_mmu_reset_context(vcpu);
6aa8b732
AK
2916}
2917
401d10de
AS
2918static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2919{
2920 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK
2921 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2922
2923 if (!msr)
2924 return;
401d10de 2925
44ea2b17
AK
2926 /*
2927 * Force kernel_gs_base reloading before EFER changes, as control
2928 * of this msr depends on is_long_mode().
2929 */
2930 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2931 vcpu->arch.efer = efer;
401d10de
AS
2932 if (efer & EFER_LMA) {
2933 vmcs_write32(VM_ENTRY_CONTROLS,
2934 vmcs_read32(VM_ENTRY_CONTROLS) |
2935 VM_ENTRY_IA32E_MODE);
2936 msr->data = efer;
2937 } else {
2938 vmcs_write32(VM_ENTRY_CONTROLS,
2939 vmcs_read32(VM_ENTRY_CONTROLS) &
2940 ~VM_ENTRY_IA32E_MODE);
2941
2942 msr->data = efer & ~EFER_LME;
2943 }
2944 setup_msrs(vmx);
2945}
2946
05b3e0c2 2947#ifdef CONFIG_X86_64
6aa8b732
AK
2948
2949static void enter_lmode(struct kvm_vcpu *vcpu)
2950{
2951 u32 guest_tr_ar;
2952
2fb92db1
AK
2953 vmx_segment_cache_clear(to_vmx(vcpu));
2954
6aa8b732
AK
2955 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2956 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK
2957 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2958 __func__);
6aa8b732
AK
2959 vmcs_write32(GUEST_TR_AR_BYTES,
2960 (guest_tr_ar & ~AR_TYPE_MASK)
2961 | AR_TYPE_BUSY_64_TSS);
2962 }
da38f438 2963 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK
2964}
2965
2966static void exit_lmode(struct kvm_vcpu *vcpu)
2967{
6aa8b732
AK
2968 vmcs_write32(VM_ENTRY_CONTROLS,
2969 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2970 & ~VM_ENTRY_IA32E_MODE);
da38f438 2971 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK
2972}
2973
2974#endif
2975
2384d2b3
SY
2976static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2977{
b9d762fa 2978 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG
2979 if (enable_ept) {
2980 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2981 return;
4e1096d2 2982 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2983 }
2384d2b3
SY
2984}
2985
e8467fda
AK
2986static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2987{
2988 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2989
2990 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2991 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2992}
2993
aff48baa
AK
2994static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2995{
2996 if (enable_ept && is_paging(vcpu))
2997 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2998 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2999}
3000
25c4c276 3001static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3002{
fc78f519
AK
3003 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3004
3005 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3006 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK
3007}
3008
1439442c
SY
3009static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3010{
6de4f3ad
AK
3011 if (!test_bit(VCPU_EXREG_PDPTR,
3012 (unsigned long *)&vcpu->arch.regs_dirty))
3013 return;
3014
1439442c 3015 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR
3016 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3017 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3018 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3019 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY
3020 }
3021}
3022
8f5d549f
AK
3023static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3024{
3025 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR
3026 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3027 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3028 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3029 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3030 }
6de4f3ad
AK
3031
3032 __set_bit(VCPU_EXREG_PDPTR,
3033 (unsigned long *)&vcpu->arch.regs_avail);
3034 __set_bit(VCPU_EXREG_PDPTR,
3035 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK
3036}
3037
5e1746d6 3038static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY
3039
3040static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3041 unsigned long cr0,
3042 struct kvm_vcpu *vcpu)
3043{
5233dd51
MT
3044 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3045 vmx_decache_cr3(vcpu);
1439442c
SY
3046 if (!(cr0 & X86_CR0_PG)) {
3047 /* From paging/starting to nonpaging */
3048 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3049 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY
3050 (CPU_BASED_CR3_LOAD_EXITING |
3051 CPU_BASED_CR3_STORE_EXITING));
3052 vcpu->arch.cr0 = cr0;
fc78f519 3053 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY
3054 } else if (!is_paging(vcpu)) {
3055 /* From nonpaging to paging */
3056 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3057 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY
3058 ~(CPU_BASED_CR3_LOAD_EXITING |
3059 CPU_BASED_CR3_STORE_EXITING));
3060 vcpu->arch.cr0 = cr0;
fc78f519 3061 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3062 }
95eb84a7
SY
3063
3064 if (!(cr0 & X86_CR0_WP))
3065 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY
3066}
3067
6aa8b732
AK
3068static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3069{
7ffd92c5 3070 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK
3071 unsigned long hw_cr0;
3072
3073 if (enable_unrestricted_guest)
3074 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3075 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3076 else
3077 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3078
7ffd92c5 3079 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK
3080 enter_pmode(vcpu);
3081
7ffd92c5 3082 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK
3083 enter_rmode(vcpu);
3084
05b3e0c2 3085#ifdef CONFIG_X86_64
f6801dff 3086 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3087 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3088 enter_lmode(vcpu);
707d92fa 3089 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK
3090 exit_lmode(vcpu);
3091 }
3092#endif
3093
089d034e 3094 if (enable_ept)
1439442c
SY
3095 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3096
02daab21 3097 if (!vcpu->fpu_active)
81231c69 3098 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3099
6aa8b732 3100 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3101 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3102 vcpu->arch.cr0 = cr0;
69c73028 3103 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK
3104}
3105
1439442c
SY
3106static u64 construct_eptp(unsigned long root_hpa)
3107{
3108 u64 eptp;
3109
3110 /* TODO write the value reading from MSR */
3111 eptp = VMX_EPT_DEFAULT_MT |
3112 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH
3113 if (enable_ept_ad_bits)
3114 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY
3115 eptp |= (root_hpa & PAGE_MASK);
3116
3117 return eptp;
3118}
3119
6aa8b732
AK
3120static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3121{
1439442c
SY
3122 unsigned long guest_cr3;
3123 u64 eptp;
3124
3125 guest_cr3 = cr3;
089d034e 3126 if (enable_ept) {
1439442c
SY
3127 eptp = construct_eptp(cr3);
3128 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3129 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3130 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3131 ept_load_pdptrs(vcpu);
1439442c
SY
3132 }
3133
2384d2b3 3134 vmx_flush_tlb(vcpu);
1439442c 3135 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK
3136}
3137
5e1746d6 3138static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3139{
7ffd92c5 3140 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY
3141 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3142
5e1746d6
NHE
3143 if (cr4 & X86_CR4_VMXE) {
3144 /*
3145 * To use VMXON (and later other VMX instructions), a guest
3146 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3147 * So basically the check on whether to allow nested VMX
3148 * is here.
3149 */
3150 if (!nested_vmx_allowed(vcpu))
3151 return 1;
3152 } else if (to_vmx(vcpu)->nested.vmxon)
3153 return 1;
3154
ad312c7c 3155 vcpu->arch.cr4 = cr4;
bc23008b
AK
3156 if (enable_ept) {
3157 if (!is_paging(vcpu)) {
3158 hw_cr4 &= ~X86_CR4_PAE;
3159 hw_cr4 |= X86_CR4_PSE;
3160 } else if (!(cr4 & X86_CR4_PAE)) {
3161 hw_cr4 &= ~X86_CR4_PAE;
3162 }
3163 }
1439442c
SY
3164
3165 vmcs_writel(CR4_READ_SHADOW, cr4);
3166 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3167 return 0;
6aa8b732
AK
3168}
3169
6aa8b732
AK
3170static void vmx_get_segment(struct kvm_vcpu *vcpu,
3171 struct kvm_segment *var, int seg)
3172{
a9179499 3173 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK
3174 u32 ar;
3175
c6ad1153 3176 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3177 *var = vmx->rmode.segs[seg];
a9179499 3178 if (seg == VCPU_SREG_TR
2fb92db1 3179 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3180 return;
1390a28b
AK
3181 var->base = vmx_read_guest_seg_base(vmx, seg);
3182 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3183 return;
a9179499 3184 }
2fb92db1
AK
3185 var->base = vmx_read_guest_seg_base(vmx, seg);
3186 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3187 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3188 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3189 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK
3190 ar = 0;
3191 var->type = ar & 15;
3192 var->s = (ar >> 4) & 1;
3193 var->dpl = (ar >> 5) & 3;
3194 var->present = (ar >> 7) & 1;
3195 var->avl = (ar >> 12) & 1;
3196 var->l = (ar >> 13) & 1;
3197 var->db = (ar >> 14) & 1;
3198 var->g = (ar >> 15) & 1;
3199 var->unusable = (ar >> 16) & 1;
3200}
3201
a9179499
AK
3202static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3203{
a9179499
AK
3204 struct kvm_segment s;
3205
3206 if (to_vmx(vcpu)->rmode.vm86_active) {
3207 vmx_get_segment(vcpu, &s, seg);
3208 return s.base;
3209 }
2fb92db1 3210 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK
3211}
3212
69c73028 3213static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3214{
3eeb3288 3215 if (!is_protmode(vcpu))
2e4d2653
IE
3216 return 0;
3217
f4c63e5d
AK
3218 if (!is_long_mode(vcpu)
3219 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE
3220 return 3;
3221
2fb92db1 3222 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE
3223}
3224
69c73028
AK
3225static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3226{
d881e6f6
AK
3227 struct vcpu_vmx *vmx = to_vmx(vcpu);
3228
3229 /*
3230 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3231 * fail; use the cache instead.
3232 */
3233 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3234 return vmx->cpl;
3235 }
3236
69c73028
AK
3237 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3238 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3239 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3240 }
d881e6f6
AK
3241
3242 return vmx->cpl;
69c73028
AK
3243}
3244
3245
653e3108 3246static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3247{
6aa8b732
AK
3248 u32 ar;
3249
f0495f9b 3250 if (var->unusable || !var->present)
6aa8b732
AK
3251 ar = 1 << 16;
3252 else {
3253 ar = var->type & 15;
3254 ar |= (var->s & 1) << 4;
3255 ar |= (var->dpl & 3) << 5;
3256 ar |= (var->present & 1) << 7;
3257 ar |= (var->avl & 1) << 12;
3258 ar |= (var->l & 1) << 13;
3259 ar |= (var->db & 1) << 14;
3260 ar |= (var->g & 1) << 15;
3261 }
653e3108
AK
3262
3263 return ar;
3264}
3265
3266static void vmx_set_segment(struct kvm_vcpu *vcpu,
3267 struct kvm_segment *var, int seg)
3268{
7ffd92c5 3269 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3270 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
39dcfb95 3271 u32 ar = 0;
653e3108 3272
2fb92db1 3273 vmx_segment_cache_clear(vmx);
1ecd50a9 3274 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3275
1ecd50a9
GN
3276 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3277 vmx->rmode.segs[seg] = *var;
3278 if (seg == VCPU_SREG_TR)
3279 vmcs_write16(sf->selector, var->selector);
3280 else if (var->s)
3281 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
653e3108
AK
3282 return;
3283 }
1ecd50a9 3284
653e3108
AK
3285 vmcs_writel(sf->base, var->base);
3286 vmcs_write32(sf->limit, var->limit);
3287 vmcs_write16(sf->selector, var->selector);
1ecd50a9 3288 ar = vmx_segment_access_rights(var);
3a624e29
NK
3289
3290 /*
3291 * Fix the "Accessed" bit in AR field of segment registers for older
3292 * qemu binaries.
3293 * IA32 arch specifies that at the time of processor reset the
3294 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3295 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK
3296 * state vmexit when "unrestricted guest" mode is turned on.
3297 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3298 * tree. Newer qemu binaries with that qemu fix would not need this
3299 * kvm hack.
3300 */
3301 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3302 ar |= 0x1; /* Accessed */
3303
6aa8b732
AK
3304 vmcs_write32(sf->ar_bytes, ar);
3305}
3306
6aa8b732
AK
3307static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3308{
2fb92db1 3309 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK
3310
3311 *db = (ar >> 14) & 1;
3312 *l = (ar >> 13) & 1;
3313}
3314
89a27f4d 3315static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3316{
89a27f4d
GN
3317 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3318 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK
3319}
3320
89a27f4d 3321static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3322{
89a27f4d
GN
3323 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3324 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK
3325}
3326
89a27f4d 3327static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3328{
89a27f4d
GN
3329 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3330 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK
3331}
3332
89a27f4d 3333static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3334{
89a27f4d
GN
3335 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3336 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK
3337}
3338
648dfaa7
MG
3339static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3340{
3341 struct kvm_segment var;
3342 u32 ar;
3343
3344 vmx_get_segment(vcpu, &var, seg);
07f42f5f
GN
3345 var.dpl = 0x3;
3346 var.g = 0;
3347 var.db = 0;
0647f4aa
GN
3348 if (seg == VCPU_SREG_CS)
3349 var.type = 0x3;
648dfaa7
MG
3350 ar = vmx_segment_access_rights(&var);
3351
3352 if (var.base != (var.selector << 4))
3353 return false;
e2a610d7 3354 if (var.limit < 0xffff)
648dfaa7 3355 return false;
07f42f5f 3356 if (ar != 0xf3)
648dfaa7
MG
3357 return false;
3358
3359 return true;
3360}
3361
3362static bool code_segment_valid(struct kvm_vcpu *vcpu)
3363{
3364 struct kvm_segment cs;
3365 unsigned int cs_rpl;
3366
3367 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3368 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3369
1872a3f4
AK
3370 if (cs.unusable)
3371 return false;
648dfaa7
MG
3372 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3373 return false;
3374 if (!cs.s)
3375 return false;
1872a3f4 3376 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG
3377 if (cs.dpl > cs_rpl)
3378 return false;
1872a3f4 3379 } else {
648dfaa7
MG
3380 if (cs.dpl != cs_rpl)
3381 return false;
3382 }
3383 if (!cs.present)
3384 return false;
3385
3386 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3387 return true;
3388}
3389
3390static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3391{
3392 struct kvm_segment ss;
3393 unsigned int ss_rpl;
3394
3395 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3396 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3397
1872a3f4
AK
3398 if (ss.unusable)
3399 return true;
3400 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG
3401 return false;
3402 if (!ss.s)
3403 return false;
3404 if (ss.dpl != ss_rpl) /* DPL != RPL */
3405 return false;
3406 if (!ss.present)
3407 return false;
3408
3409 return true;
3410}
3411
3412static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3413{
3414 struct kvm_segment var;
3415 unsigned int rpl;
3416
3417 vmx_get_segment(vcpu, &var, seg);
3418 rpl = var.selector & SELECTOR_RPL_MASK;
3419
1872a3f4
AK
3420 if (var.unusable)
3421 return true;
648dfaa7
MG
3422 if (!var.s)
3423 return false;
3424 if (!var.present)
3425 return false;
3426 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3427 if (var.dpl < rpl) /* DPL < RPL */
3428 return false;
3429 }
3430
3431 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3432 * rights flags
3433 */
3434 return true;
3435}
3436
3437static bool tr_valid(struct kvm_vcpu *vcpu)
3438{
3439 struct kvm_segment tr;
3440
3441 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3442
1872a3f4
AK
3443 if (tr.unusable)
3444 return false;
648dfaa7
MG
3445 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3446 return false;
1872a3f4 3447 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG
3448 return false;
3449 if (!tr.present)
3450 return false;
3451
3452 return true;
3453}
3454
3455static bool ldtr_valid(struct kvm_vcpu *vcpu)
3456{
3457 struct kvm_segment ldtr;
3458
3459 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3460
1872a3f4
AK
3461 if (ldtr.unusable)
3462 return true;
648dfaa7
MG
3463 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3464 return false;
3465 if (ldtr.type != 2)
3466 return false;
3467 if (!ldtr.present)
3468 return false;
3469
3470 return true;
3471}
3472
3473static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3474{
3475 struct kvm_segment cs, ss;
3476
3477 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3478 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3479
3480 return ((cs.selector & SELECTOR_RPL_MASK) ==
3481 (ss.selector & SELECTOR_RPL_MASK));
3482}
3483
3484/*
3485 * Check if guest state is valid. Returns true if valid, false if
3486 * not.
3487 * We assume that registers are always usable
3488 */
3489static bool guest_state_valid(struct kvm_vcpu *vcpu)
3490{
3491 /* real mode guest state checks */
3eeb3288 3492 if (!is_protmode(vcpu)) {
648dfaa7
MG
3493 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3494 return false;
3495 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3496 return false;
3497 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3498 return false;
3499 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3500 return false;
3501 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3502 return false;
3503 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3504 return false;
3505 } else {
3506 /* protected mode guest state checks */
3507 if (!cs_ss_rpl_check(vcpu))
3508 return false;
3509 if (!code_segment_valid(vcpu))
3510 return false;
3511 if (!stack_segment_valid(vcpu))
3512 return false;
3513 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3514 return false;
3515 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3516 return false;
3517 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3518 return false;
3519 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3520 return false;
3521 if (!tr_valid(vcpu))
3522 return false;
3523 if (!ldtr_valid(vcpu))
3524 return false;
3525 }
3526 /* TODO:
3527 * - Add checks on RIP
3528 * - Add checks on RFLAGS
3529 */
3530
3531 return true;
3532}
3533
d77c26fc 3534static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3535{
40dcaa9f 3536 gfn_t fn;
195aefde 3537 u16 data = 0;
40dcaa9f 3538 int r, idx, ret = 0;
6aa8b732 3539
40dcaa9f
XG
3540 idx = srcu_read_lock(&kvm->srcu);
3541 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE
3542 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3543 if (r < 0)
10589a46 3544 goto out;
195aefde 3545 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY
3546 r = kvm_write_guest_page(kvm, fn++, &data,
3547 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3548 if (r < 0)
10589a46 3549 goto out;
195aefde
IE
3550 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3551 if (r < 0)
10589a46 3552 goto out;
195aefde
IE
3553 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3554 if (r < 0)
10589a46 3555 goto out;
195aefde 3556 data = ~0;
10589a46
MT
3557 r = kvm_write_guest_page(kvm, fn, &data,
3558 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3559 sizeof(u8));
195aefde 3560 if (r < 0)
10589a46
MT
3561 goto out;
3562
3563 ret = 1;
3564out:
40dcaa9f 3565 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3566 return ret;
6aa8b732
AK
3567}
3568
b7ebfb05
SY
3569static int init_rmode_identity_map(struct kvm *kvm)
3570{
40dcaa9f 3571 int i, idx, r, ret;
b7ebfb05
SY
3572 pfn_t identity_map_pfn;
3573 u32 tmp;
3574
089d034e 3575 if (!enable_ept)
b7ebfb05
SY
3576 return 1;
3577 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3578 printk(KERN_ERR "EPT: identity-mapping pagetable "
3579 "haven't been allocated!\n");
3580 return 0;
3581 }
3582 if (likely(kvm->arch.ept_identity_pagetable_done))
3583 return 1;
3584 ret = 0;
b927a3ce 3585 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3586 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY
3587 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3588 if (r < 0)
3589 goto out;
3590 /* Set up identity-mapping pagetable for EPT in real mode */
3591 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3592 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3593 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3594 r = kvm_write_guest_page(kvm, identity_map_pfn,
3595 &tmp, i * sizeof(tmp), sizeof(tmp));
3596 if (r < 0)
3597 goto out;
3598 }
3599 kvm->arch.ept_identity_pagetable_done = true;
3600 ret = 1;
3601out:
40dcaa9f 3602 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY
3603 return ret;
3604}
3605
6aa8b732
AK
3606static void seg_setup(int seg)
3607{
772e0318 3608 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3609 unsigned int ar;
6aa8b732
AK
3610
3611 vmcs_write16(sf->selector, 0);
3612 vmcs_writel(sf->base, 0);
3613 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK
3614 if (enable_unrestricted_guest) {
3615 ar = 0x93;
3616 if (seg == VCPU_SREG_CS)
3617 ar |= 0x08; /* code segment */
3618 } else
3619 ar = 0xf3;
3620
3621 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK
3622}
3623
f78e0e2e
SY
3624static int alloc_apic_access_page(struct kvm *kvm)
3625{
4484141a 3626 struct page *page;
f78e0e2e
SY
3627 struct kvm_userspace_memory_region kvm_userspace_mem;
3628 int r = 0;
3629
79fac95e 3630 mutex_lock(&kvm->slots_lock);
bfc6d222 3631 if (kvm->arch.apic_access_page)
f78e0e2e
SY
3632 goto out;
3633 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3634 kvm_userspace_mem.flags = 0;
3635 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3636 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3637 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
f78e0e2e
SY
3638 if (r)
3639 goto out;
72dc67a6 3640
4484141a
XG
3641 page = gfn_to_page(kvm, 0xfee00);
3642 if (is_error_page(page)) {
3643 r = -EFAULT;
3644 goto out;
3645 }
3646
3647 kvm->arch.apic_access_page = page;
f78e0e2e 3648out:
79fac95e 3649 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY
3650 return r;
3651}
3652
b7ebfb05
SY
3653static int alloc_identity_pagetable(struct kvm *kvm)
3654{
4484141a 3655 struct page *page;
b7ebfb05
SY
3656 struct kvm_userspace_memory_region kvm_userspace_mem;
3657 int r = 0;
3658
79fac95e 3659 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY
3660 if (kvm->arch.ept_identity_pagetable)
3661 goto out;
3662 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3663 kvm_userspace_mem.flags = 0;
b927a3ce
SY
3664 kvm_userspace_mem.guest_phys_addr =
3665 kvm->arch.ept_identity_map_addr;
b7ebfb05 3666 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3667 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
b7ebfb05
SY
3668 if (r)
3669 goto out;
3670
4484141a
XG
3671 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3672 if (is_error_page(page)) {
3673 r = -EFAULT;
3674 goto out;
3675 }
3676
3677 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3678out:
79fac95e 3679 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY
3680 return r;
3681}
3682
2384d2b3
SY
3683static void allocate_vpid(struct vcpu_vmx *vmx)
3684{
3685 int vpid;
3686
3687 vmx->vpid = 0;
919818ab 3688 if (!enable_vpid)
2384d2b3
SY
3689 return;
3690 spin_lock(&vmx_vpid_lock);
3691 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3692 if (vpid < VMX_NR_VPIDS) {
3693 vmx->vpid = vpid;
3694 __set_bit(vpid, vmx_vpid_bitmap);
3695 }
3696 spin_unlock(&vmx_vpid_lock);
3697}
3698
cdbecfc3
LJ
3699static void free_vpid(struct vcpu_vmx *vmx)
3700{
3701 if (!enable_vpid)
3702 return;
3703 spin_lock(&vmx_vpid_lock);
3704 if (vmx->vpid != 0)
3705 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3706 spin_unlock(&vmx_vpid_lock);
3707}
3708
5897297b 3709static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3710{
3e7c73e9 3711 int f = sizeof(unsigned long);
25c5f225
SY
3712
3713 if (!cpu_has_vmx_msr_bitmap())
3714 return;
3715
3716 /*
3717 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3718 * have the write-low and read-high bitmap offsets the wrong way round.
3719 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3720 */
25c5f225 3721 if (msr <= 0x1fff) {
3e7c73e9
AK
3722 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3723 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY
3724 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3725 msr &= 0x1fff;
3e7c73e9
AK
3726 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3727 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3728 }
25c5f225
SY
3729}
3730
5897297b
AK
3731static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3732{
3733 if (!longmode_only)
3734 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3735 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3736}
3737
a3a8ff8e
NHE
3738/*
3739 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3740 * will not change in the lifetime of the guest.
3741 * Note that host-state that does change is set elsewhere. E.g., host-state
3742 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3743 */
3744static void vmx_set_constant_host_state(void)
3745{
3746 u32 low32, high32;
3747 unsigned long tmpl;
3748 struct desc_ptr dt;
3749
b1a74bf8 3750 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE
3751 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3752 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3753
3754 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK
3755#ifdef CONFIG_X86_64
3756 /*
3757 * Load null selectors, so we can avoid reloading them in
3758 * __vmx_load_host_state(), in case userspace uses the null selectors
3759 * too (the expected case).
3760 */
3761 vmcs_write16(HOST_DS_SELECTOR, 0);
3762 vmcs_write16(HOST_ES_SELECTOR, 0);
3763#else
a3a8ff8e
NHE
3764 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3765 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3766#endif
a3a8ff8e
NHE
3767 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3768 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3769
3770 native_store_idt(&dt);
3771 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3772
83287ea4 3773 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE
3774
3775 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3776 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3777 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3778 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3779
3780 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3781 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3782 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3783 }
3784}
3785
bf8179a0
NHE
3786static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3787{
3788 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3789 if (enable_ept)
3790 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE
3791 if (is_guest_mode(&vmx->vcpu))
3792 vmx->vcpu.arch.cr4_guest_owned_bits &=
3793 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE
3794 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3795}
3796
3797static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3798{
3799 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3800 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3801 exec_control &= ~CPU_BASED_TPR_SHADOW;
3802#ifdef CONFIG_X86_64
3803 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3804 CPU_BASED_CR8_LOAD_EXITING;
3805#endif
3806 }
3807 if (!enable_ept)
3808 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3809 CPU_BASED_CR3_LOAD_EXITING |
3810 CPU_BASED_INVLPG_EXITING;
3811 return exec_control;
3812}
3813
3814static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3815{
3816 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3817 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3818 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3819 if (vmx->vpid == 0)
3820 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3821 if (!enable_ept) {
3822 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3823 enable_unrestricted_guest = 0;
ad756a16
MJ
3824 /* Enable INVPCID for non-ept guests may cause performance regression. */
3825 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE
3826 }
3827 if (!enable_unrestricted_guest)
3828 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3829 if (!ple_gap)
3830 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3831 return exec_control;
3832}
3833
ce88decf
XG
3834static void ept_set_mmio_spte_mask(void)
3835{
3836 /*
3837 * EPT Misconfigurations can be generated if the value of bits 2:0
3838 * of an EPT paging-structure entry is 110b (write/execute).
3839 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3840 * spte.
3841 */
3842 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3843}
3844
6aa8b732
AK
3845/*
3846 * Sets up the vmcs for emulated real mode.
3847 */
8b9cf98c 3848static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3849{
2e4ce7f5 3850#ifdef CONFIG_X86_64
6aa8b732 3851 unsigned long a;
2e4ce7f5 3852#endif
6aa8b732 3853 int i;
6aa8b732 3854
6aa8b732 3855 /* I/O */
3e7c73e9
AK
3856 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3857 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3858
25c5f225 3859 if (cpu_has_vmx_msr_bitmap())
5897297b 3860 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3861
6aa8b732
AK
3862 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3863
6aa8b732 3864 /* Control */
1c3d14fe
YS
3865 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3866 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3867
bf8179a0 3868 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3869
83ff3b9d 3870 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE
3871 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3872 vmx_secondary_exec_control(vmx));
83ff3b9d 3873 }
f78e0e2e 3874
4b8d54f9
ZE
3875 if (ple_gap) {
3876 vmcs_write32(PLE_GAP, ple_gap);
3877 vmcs_write32(PLE_WINDOW, ple_window);
3878 }
3879
c3707958
XG
3880 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3881 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK
3882 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3883
9581d442
AK
3884 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3885 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3886 vmx_set_constant_host_state();
05b3e0c2 3887#ifdef CONFIG_X86_64
6aa8b732
AK
3888 rdmsrl(MSR_FS_BASE, a);
3889 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3890 rdmsrl(MSR_GS_BASE, a);
3891 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3892#else
3893 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3894 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3895#endif
3896
2cc51560
ED
3897 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3898 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3899 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3900 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3901 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3902
468d472f 3903 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE
3904 u32 msr_low, msr_high;
3905 u64 host_pat;
468d472f
SY
3906 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3907 host_pat = msr_low | ((u64) msr_high << 32);
3908 /* Write the default value follow host pat */
3909 vmcs_write64(GUEST_IA32_PAT, host_pat);
3910 /* Keep arch.pat sync with GUEST_IA32_PAT */
3911 vmx->vcpu.arch.pat = host_pat;
3912 }
3913
6aa8b732
AK
3914 for (i = 0; i < NR_VMX_MSR; ++i) {
3915 u32 index = vmx_msr_index[i];
3916 u32 data_low, data_high;
a2fa3e9f 3917 int j = vmx->nmsrs;
6aa8b732
AK
3918
3919 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3920 continue;
432bd6cb
AK
3921 if (wrmsr_safe(index, data_low, data_high) < 0)
3922 continue;
26bb0981
AK
3923 vmx->guest_msrs[j].index = i;
3924 vmx->guest_msrs[j].data = 0;
d5696725 3925 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3926 ++vmx->nmsrs;
6aa8b732 3927 }
6aa8b732 3928
1c3d14fe 3929 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK
3930
3931 /* 22.2.1, 20.8.1 */
1c3d14fe
YS
3932 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3933
e00c8cf2 3934 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3935 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK
3936
3937 return 0;
3938}
3939
3940static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3941{
3942 struct vcpu_vmx *vmx = to_vmx(vcpu);
3943 u64 msr;
4b9d3a04 3944 int ret;
e00c8cf2 3945
7ffd92c5 3946 vmx->rmode.vm86_active = 0;
e00c8cf2 3947
3b86cd99
JK
3948 vmx->soft_vnmi_blocked = 0;
3949
ad312c7c 3950 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3951 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3952 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3953 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK
3954 msr |= MSR_IA32_APICBASE_BSP;
3955 kvm_set_apic_base(&vmx->vcpu, msr);
3956
2fb92db1
AK
3957 vmx_segment_cache_clear(vmx);
3958
5706be0d 3959 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK
3960 /*
3961 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3962 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3963 */
c5af89b6 3964 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK
3965 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3966 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3967 } else {
ad312c7c
ZX
3968 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3969 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3970 }
e00c8cf2
AK
3971
3972 seg_setup(VCPU_SREG_DS);
3973 seg_setup(VCPU_SREG_ES);
3974 seg_setup(VCPU_SREG_FS);
3975 seg_setup(VCPU_SREG_GS);
3976 seg_setup(VCPU_SREG_SS);
3977
3978 vmcs_write16(GUEST_TR_SELECTOR, 0);
3979 vmcs_writel(GUEST_TR_BASE, 0);
3980 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3981 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3982
3983 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3984 vmcs_writel(GUEST_LDTR_BASE, 0);
3985 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3986 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3987
3988 vmcs_write32(GUEST_SYSENTER_CS, 0);
3989 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3990 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3991
3992 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3993 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3994 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3995 else
5fdbf976 3996 kvm_rip_write(vcpu, 0);
e00c8cf2 3997
e00c8cf2
AK
3998 vmcs_writel(GUEST_GDTR_BASE, 0);
3999 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4000
4001 vmcs_writel(GUEST_IDTR_BASE, 0);
4002 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4003
443381a8 4004 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK
4005 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4006 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4007
e00c8cf2
AK
4008 /* Special registers */
4009 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4010
4011 setup_msrs(vmx);
4012
6aa8b732
AK
4013 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4014
f78e0e2e
SY
4015 if (cpu_has_vmx_tpr_shadow()) {
4016 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4017 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4018 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4019 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY
4020 vmcs_write32(TPR_THRESHOLD, 0);
4021 }
4022
4023 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4024 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4025 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4026
2384d2b3
SY
4027 if (vmx->vpid != 0)
4028 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4029
fa40052c 4030 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4031 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4032 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4033 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4034 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4035 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR
4036 vmx_fpu_activate(&vmx->vcpu);
4037 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4038
b9d762fa 4039 vpid_sync_context(vmx);
2384d2b3 4040
3200f405 4041 ret = 0;
6aa8b732 4042
a89a8fb9
MG
4043 /* HACK: Don't enable emulation on guest boot/reset */
4044 vmx->emulation_required = 0;
4045
6aa8b732
AK
4046 return ret;
4047}
4048
b6f1250e
NHE
4049/*
4050 * In nested virtualization, check if L1 asked to exit on external interrupts.
4051 * For most existing hypervisors, this will always return true.
4052 */
4053static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4054{
4055 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4056 PIN_BASED_EXT_INTR_MASK;
4057}
4058
3b86cd99
JK
4059static void enable_irq_window(struct kvm_vcpu *vcpu)
4060{
4061 u32 cpu_based_vm_exec_control;
d6185f20
NHE
4062 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4063 /*
4064 * We get here if vmx_interrupt_allowed() said we can't
4065 * inject to L1 now because L2 must run. Ask L2 to exit
4066 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4067 */
d6185f20 4068 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4069 return;
d6185f20 4070 }
3b86cd99
JK
4071
4072 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4073 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4074 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4075}
4076
4077static void enable_nmi_window(struct kvm_vcpu *vcpu)
4078{
4079 u32 cpu_based_vm_exec_control;
4080
4081 if (!cpu_has_virtual_nmis()) {
4082 enable_irq_window(vcpu);
4083 return;
4084 }
4085
30bd0c4c
AK
4086 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4087 enable_irq_window(vcpu);
4088 return;
4089 }
3b86cd99
JK
4090 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4091 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4092 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4093}
4094
66fd3f7f 4095static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4096{
9c8cba37 4097 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN
4098 uint32_t intr;
4099 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4100
229456fc 4101 trace_kvm_inj_virq(irq);
2714d1d3 4102
fa89a817 4103 ++vcpu->stat.irq_injections;
7ffd92c5 4104 if (vmx->rmode.vm86_active) {
71f9833b
SH
4105 int inc_eip = 0;
4106 if (vcpu->arch.interrupt.soft)
4107 inc_eip = vcpu->arch.event_exit_inst_len;
4108 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4109 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED
4110 return;
4111 }
66fd3f7f
GN
4112 intr = irq | INTR_INFO_VALID_MASK;
4113 if (vcpu->arch.interrupt.soft) {
4114 intr |= INTR_TYPE_SOFT_INTR;
4115 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4116 vmx->vcpu.arch.event_exit_inst_len);
4117 } else
4118 intr |= INTR_TYPE_EXT_INTR;
4119 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED
4120}
4121
f08864b4
SY
4122static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4123{
66a5a347
JK
4124 struct vcpu_vmx *vmx = to_vmx(vcpu);
4125
0b6ac343
NHE
4126 if (is_guest_mode(vcpu))
4127 return;
4128
3b86cd99
JK
4129 if (!cpu_has_virtual_nmis()) {
4130 /*
4131 * Tracking the NMI-blocked state in software is built upon
4132 * finding the next open IRQ window. This, in turn, depends on
4133 * well-behaving guests: They have to keep IRQs disabled at
4134 * least as long as the NMI handler runs. Otherwise we may
4135 * cause NMI nesting, maybe breaking the guest. But as this is
4136 * highly unlikely, we can live with the residual risk.
4137 */
4138 vmx->soft_vnmi_blocked = 1;
4139 vmx->vnmi_blocked_time = 0;
4140 }
4141
487b391d 4142 ++vcpu->stat.nmi_injections;
9d58b931 4143 vmx->nmi_known_unmasked = false;
7ffd92c5 4144 if (vmx->rmode.vm86_active) {
71f9833b 4145 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4146 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK
4147 return;
4148 }
f08864b4
SY
4149 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4150 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY
4151}
4152
c4282df9 4153static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4154{
3b86cd99 4155 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4156 return 0;
33f089ca 4157
c4282df9 4158 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK
4159 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4160 | GUEST_INTR_STATE_NMI));
33f089ca
JK
4161}
4162
3cfc3092
JK
4163static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4164{
4165 if (!cpu_has_virtual_nmis())
4166 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK
4167 if (to_vmx(vcpu)->nmi_known_unmasked)
4168 return false;
c332c83a 4169 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK
4170}
4171
4172static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4173{
4174 struct vcpu_vmx *vmx = to_vmx(vcpu);
4175
4176 if (!cpu_has_virtual_nmis()) {
4177 if (vmx->soft_vnmi_blocked != masked) {
4178 vmx->soft_vnmi_blocked = masked;
4179 vmx->vnmi_blocked_time = 0;
4180 }
4181 } else {
9d58b931 4182 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK
4183 if (masked)
4184 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4185 GUEST_INTR_STATE_NMI);
4186 else
4187 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4188 GUEST_INTR_STATE_NMI);
4189 }
4190}
4191
78646121
GN
4192static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4193{
b6f1250e 4194 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE
4195 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4196 if (to_vmx(vcpu)->nested.nested_run_pending ||
4197 (vmcs12->idt_vectoring_info_field &
4198 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE
4199 return 0;
4200 nested_vmx_vmexit(vcpu);
b6f1250e
NHE
4201 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4202 vmcs12->vm_exit_intr_info = 0;
4203 /* fall through to normal code, but now in L1, not L2 */
4204 }
4205
c4282df9
GN
4206 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4207 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4208 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN
4209}
4210
cbc94022
IE
4211static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4212{
4213 int ret;
4214 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4215 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE
4216 .guest_phys_addr = addr,
4217 .memory_size = PAGE_SIZE * 3,
4218 .flags = 0,
4219 };
4220
f82a8cfe 4221 ret = kvm_set_memory_region(kvm, &tss_mem, false);
cbc94022
IE
4222 if (ret)
4223 return ret;
bfc6d222 4224 kvm->arch.tss_addr = addr;
93ea5388
GN
4225 if (!init_rmode_tss(kvm))
4226 return -ENOMEM;
4227
cbc94022
IE
4228 return 0;
4229}
4230
6aa8b732
AK
4231static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4232 int vec, u32 err_code)
4233{
b3f37707
NK
4234 /*
4235 * Instruction with address size override prefix opcode 0x67
4236 * Cause the #SS fault with 0 error code in VM86 mode.
4237 */
4238 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4239 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4240 return 1;
77ab6db0
JK
4241 /*
4242 * Forward all other exceptions that are valid in real mode.
4243 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4244 * the required debugging infrastructure rework.
4245 */
4246 switch (vec) {
77ab6db0 4247 case DB_VECTOR:
d0bfb940
JK
4248 if (vcpu->guest_debug &
4249 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4250 return 0;
4251 kvm_queue_exception(vcpu, vec);
4252 return 1;
77ab6db0 4253 case BP_VECTOR:
c573cd22
JK
4254 /*
4255 * Update instruction length as we may reinject the exception
4256 * from user space while in guest debugging mode.
4257 */
4258 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4259 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK
4260 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4261 return 0;
4262 /* fall through */
4263 case DE_VECTOR:
77ab6db0
JK
4264 case OF_VECTOR:
4265 case BR_VECTOR:
4266 case UD_VECTOR:
4267 case DF_VECTOR:
4268 case SS_VECTOR:
4269 case GP_VECTOR:
4270 case MF_VECTOR:
4271 kvm_queue_exception(vcpu, vec);
4272 return 1;
4273 }
6aa8b732
AK
4274 return 0;
4275}
4276
a0861c02
AK
4277/*
4278 * Trigger machine check on the host. We assume all the MSRs are already set up
4279 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4280 * We pass a fake environment to the machine check handler because we want
4281 * the guest to be always treated like user space, no matter what context
4282 * it used internally.
4283 */
4284static void kvm_machine_check(void)
4285{
4286#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4287 struct pt_regs regs = {
4288 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4289 .flags = X86_EFLAGS_IF,
4290 };
4291
4292 do_machine_check(&regs, 0);
4293#endif
4294}
4295
851ba692 4296static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK
4297{
4298 /* already handled by vcpu_run */
4299 return 1;
4300}
4301
851ba692 4302static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4303{
1155f76a 4304 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4305 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4306 u32 intr_info, ex_no, error_code;
42dbaa5a 4307 unsigned long cr2, rip, dr6;
6aa8b732
AK
4308 u32 vect_info;
4309 enum emulation_result er;
4310
1155f76a 4311 vect_info = vmx->idt_vectoring_info;
88786475 4312 intr_info = vmx->exit_intr_info;
6aa8b732 4313
a0861c02 4314 if (is_machine_check(intr_info))
851ba692 4315 return handle_machine_check(vcpu);
a0861c02 4316
e4a41889 4317 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4318 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL
4319
4320 if (is_no_device(intr_info)) {
5fd86fcf 4321 vmx_fpu_activate(vcpu);
2ab455cc
AL
4322 return 1;
4323 }
4324
7aa81cc0 4325 if (is_invalid_opcode(intr_info)) {
51d8b661 4326 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4327 if (er != EMULATE_DONE)
7ee5d940 4328 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL
4329 return 1;
4330 }
4331
6aa8b732 4332 error_code = 0;
2e11384c 4333 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4334 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG
4335
4336 /*
4337 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4338 * MMIO, it is better to report an internal error.
4339 * See the comments in vmx_handle_exit.
4340 */
4341 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4342 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4343 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4344 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4345 vcpu->run->internal.ndata = 2;
4346 vcpu->run->internal.data[0] = vect_info;
4347 vcpu->run->internal.data[1] = intr_info;
4348 return 0;
4349 }
4350
6aa8b732 4351 if (is_page_fault(intr_info)) {
1439442c 4352 /* EPT won't cause page fault directly */
cf3ace79 4353 BUG_ON(enable_ept);
6aa8b732 4354 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT
4355 trace_kvm_page_fault(cr2, error_code);
4356
3298b75c 4357 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4358 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4359 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK
4360 }
4361
7ffd92c5 4362 if (vmx->rmode.vm86_active &&
6aa8b732 4363 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4364 error_code)) {
ad312c7c
ZX
4365 if (vcpu->arch.halt_request) {
4366 vcpu->arch.halt_request = 0;
72d6e5a0
AK
4367 return kvm_emulate_halt(vcpu);
4368 }
6aa8b732 4369 return 1;
72d6e5a0 4370 }
6aa8b732 4371
d0bfb940 4372 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK
4373 switch (ex_no) {
4374 case DB_VECTOR:
4375 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4376 if (!(vcpu->guest_debug &
4377 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4378 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4379 kvm_queue_exception(vcpu, DB_VECTOR);
4380 return 1;
4381 }
4382 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4383 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4384 /* fall through */
4385 case BP_VECTOR:
c573cd22
JK
4386 /*
4387 * Update instruction length as we may reinject #BP from
4388 * user space while in guest debugging mode. Reading it for
4389 * #DB as well causes no harm, it is not used in that case.
4390 */
4391 vmx->vcpu.arch.event_exit_inst_len =
4392 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4393 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4394 rip = kvm_rip_read(vcpu);
d0bfb940
JK
4395 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4396 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK
4397 break;
4398 default:
d0bfb940
JK
4399 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4400 kvm_run->ex.exception = ex_no;
4401 kvm_run->ex.error_code = error_code;
42dbaa5a 4402 break;
6aa8b732 4403 }
6aa8b732
AK
4404 return 0;
4405}
4406
851ba692 4407static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4408{
1165f5fe 4409 ++vcpu->stat.irq_exits;
6aa8b732
AK
4410 return 1;
4411}
4412
851ba692 4413static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4414{
851ba692 4415 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK
4416 return 0;
4417}
6aa8b732 4418
851ba692 4419static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4420{
bfdaab09 4421 unsigned long exit_qualification;
34c33d16 4422 int size, in, string;
039576c0 4423 unsigned port;
6aa8b732 4424
bfdaab09 4425 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4426 string = (exit_qualification & 16) != 0;
cf8f70bf 4427 in = (exit_qualification & 8) != 0;
e70669ab 4428
cf8f70bf 4429 ++vcpu->stat.io_exits;
e70669ab 4430
cf8f70bf 4431 if (string || in)
51d8b661 4432 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4433
cf8f70bf
GN
4434 port = exit_qualification >> 16;
4435 size = (exit_qualification & 7) + 1;
e93f36bc 4436 skip_emulated_instruction(vcpu);
cf8f70bf
GN
4437
4438 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK
4439}
4440
102d8325
IM
4441static void
4442vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4443{
4444 /*
4445 * Patch in the VMCALL instruction:
4446 */
4447 hypercall[0] = 0x0f;
4448 hypercall[1] = 0x01;
4449 hypercall[2] = 0xc1;
102d8325
IM
4450}
4451
0fa06071 4452/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE
4453static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4454{
4455 if (to_vmx(vcpu)->nested.vmxon &&
4456 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4457 return 1;
4458
4459 if (is_guest_mode(vcpu)) {
4460 /*
4461 * We get here when L2 changed cr0 in a way that did not change
4462 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4463 * but did change L0 shadowed bits. This can currently happen
4464 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4465 * loading) while pretending to allow the guest to change it.
4466 */
4467 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4468 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4469 return 1;
4470 vmcs_writel(CR0_READ_SHADOW, val);
4471 return 0;
4472 } else
4473 return kvm_set_cr0(vcpu, val);
4474}
4475
4476static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4477{
4478 if (is_guest_mode(vcpu)) {
4479 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4480 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4481 return 1;
4482 vmcs_writel(CR4_READ_SHADOW, val);
4483 return 0;
4484 } else
4485 return kvm_set_cr4(vcpu, val);
4486}
4487
4488/* called to set cr0 as approriate for clts instruction exit. */
4489static void handle_clts(struct kvm_vcpu *vcpu)
4490{
4491 if (is_guest_mode(vcpu)) {
4492 /*
4493 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4494 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4495 * just pretend it's off (also in arch.cr0 for fpu_activate).
4496 */
4497 vmcs_writel(CR0_READ_SHADOW,
4498 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4499 vcpu->arch.cr0 &= ~X86_CR0_TS;
4500 } else
4501 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4502}
4503
851ba692 4504static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4505{
229456fc 4506 unsigned long exit_qualification, val;
6aa8b732
AK
4507 int cr;
4508 int reg;
49a9b07e 4509 int err;
6aa8b732 4510
bfdaab09 4511 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK
4512 cr = exit_qualification & 15;
4513 reg = (exit_qualification >> 8) & 15;
4514 switch ((exit_qualification >> 4) & 3) {
4515 case 0: /* mov to cr */
229456fc
MT
4516 val = kvm_register_read(vcpu, reg);
4517 trace_kvm_cr_write(cr, val);
6aa8b732
AK
4518 switch (cr) {
4519 case 0:
eeadf9e7 4520 err = handle_set_cr0(vcpu, val);
db8fcefa 4521 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK
4522 return 1;
4523 case 3:
2390218b 4524 err = kvm_set_cr3(vcpu, val);
db8fcefa 4525 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK
4526 return 1;
4527 case 4:
eeadf9e7 4528 err = handle_set_cr4(vcpu, val);
db8fcefa 4529 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4530 return 1;
0a5fff19
GN
4531 case 8: {
4532 u8 cr8_prev = kvm_get_cr8(vcpu);
4533 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4534 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4535 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN
4536 if (irqchip_in_kernel(vcpu->kvm))
4537 return 1;
4538 if (cr8_prev <= cr8)
4539 return 1;
851ba692 4540 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN
4541 return 0;
4542 }
4b8073e4 4543 }
6aa8b732 4544 break;
25c4c276 4545 case 2: /* clts */
eeadf9e7 4546 handle_clts(vcpu);
4d4ec087 4547 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4548 skip_emulated_instruction(vcpu);
6b52d186 4549 vmx_fpu_activate(vcpu);
25c4c276 4550 return 1;
6aa8b732
AK
4551 case 1: /*mov from cr*/
4552 switch (cr) {
4553 case 3:
9f8fe504
AK
4554 val = kvm_read_cr3(vcpu);
4555 kvm_register_write(vcpu, reg, val);
4556 trace_kvm_cr_read(cr, val);
6aa8b732
AK
4557 skip_emulated_instruction(vcpu);
4558 return 1;
4559 case 8:
229456fc
MT
4560 val = kvm_get_cr8(vcpu);
4561 kvm_register_write(vcpu, reg, val);
4562 trace_kvm_cr_read(cr, val);
6aa8b732
AK
4563 skip_emulated_instruction(vcpu);
4564 return 1;
4565 }
4566 break;
4567 case 3: /* lmsw */
a1f83a74 4568 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4569 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4570 kvm_lmsw(vcpu, val);
6aa8b732
AK
4571
4572 skip_emulated_instruction(vcpu);
4573 return 1;
4574 default:
4575 break;
4576 }
851ba692 4577 vcpu->run->exit_reason = 0;
a737f256 4578 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK
4579 (int)(exit_qualification >> 4) & 3, cr);
4580 return 0;
4581}
4582
851ba692 4583static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4584{
bfdaab09 4585 unsigned long exit_qualification;
6aa8b732
AK
4586 int dr, reg;
4587
f2483415 4588 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK
4589 if (!kvm_require_cpl(vcpu, 0))
4590 return 1;
42dbaa5a
JK
4591 dr = vmcs_readl(GUEST_DR7);
4592 if (dr & DR7_GD) {
4593 /*
4594 * As the vm-exit takes precedence over the debug trap, we
4595 * need to emulate the latter, either for the host or the
4596 * guest debugging itself.
4597 */
4598 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK
4599 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4600 vcpu->run->debug.arch.dr7 = dr;
4601 vcpu->run->debug.arch.pc =
42dbaa5a
JK
4602 vmcs_readl(GUEST_CS_BASE) +
4603 vmcs_readl(GUEST_RIP);
851ba692
AK
4604 vcpu->run->debug.arch.exception = DB_VECTOR;
4605 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK
4606 return 0;
4607 } else {
4608 vcpu->arch.dr7 &= ~DR7_GD;
4609 vcpu->arch.dr6 |= DR6_BD;
4610 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4611 kvm_queue_exception(vcpu, DB_VECTOR);
4612 return 1;
4613 }
4614 }
4615
bfdaab09 4616 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK
4617 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4618 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4619 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN
4620 unsigned long val;
4621 if (!kvm_get_dr(vcpu, dr, &val))
4622 kvm_register_write(vcpu, reg, val);
4623 } else
4624 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK
4625 skip_emulated_instruction(vcpu);
4626 return 1;
4627}
4628
020df079
GN
4629static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4630{
4631 vmcs_writel(GUEST_DR7, val);
4632}
4633
851ba692 4634static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4635{
06465c5a
AK
4636 kvm_emulate_cpuid(vcpu);
4637 return 1;
6aa8b732
AK
4638}
4639
851ba692 4640static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4641{
ad312c7c 4642 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK
4643 u64 data;
4644
4645 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4646 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4647 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
4648 return 1;
4649 }
4650
229456fc 4651 trace_kvm_msr_read(ecx, data);
2714d1d3 4652
6aa8b732 4653 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX
4654 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4655 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK
4656 skip_emulated_instruction(vcpu);
4657 return 1;
4658}
4659
851ba692 4660static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4661{
8fe8ab46 4662 struct msr_data msr;
ad312c7c
ZX
4663 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4664 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4665 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4666
8fe8ab46
WA
4667 msr.data = data;
4668 msr.index = ecx;
4669 msr.host_initiated = false;
4670 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4671 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4672 kvm_inject_gp(vcpu, 0);
6aa8b732
AK
4673 return 1;
4674 }
4675
59200273 4676 trace_kvm_msr_write(ecx, data);
6aa8b732
AK
4677 skip_emulated_instruction(vcpu);
4678 return 1;
4679}
4680
851ba692 4681static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4682{
3842d135 4683 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS
4684 return 1;
4685}
4686
851ba692 4687static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4688{
85f455f7
ED
4689 u32 cpu_based_vm_exec_control;
4690
4691 /* clear pending irq */
4692 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4693 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4694 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4695
3842d135
AK
4696 kvm_make_request(KVM_REQ_EVENT, vcpu);
4697
a26bf12a 4698 ++vcpu->stat.irq_window_exits;
2714d1d3 4699
c1150d8c
DL
4700 /*
4701 * If the user space waits to inject interrupts, exit as soon as
4702 * possible
4703 */
8061823a 4704 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4705 vcpu->run->request_interrupt_window &&
8061823a 4706 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4707 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL
4708 return 0;
4709 }
6aa8b732
AK
4710 return 1;
4711}
4712
851ba692 4713static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK
4714{
4715 skip_emulated_instruction(vcpu);
d3bef15f 4716 return kvm_emulate_halt(vcpu);
6aa8b732
AK
4717}
4718
851ba692 4719static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4720{
510043da 4721 skip_emulated_instruction(vcpu);
7aa81cc0
AL
4722 kvm_emulate_hypercall(vcpu);
4723 return 1;
c21415e8
IM
4724}
4725
ec25d5e6
GN
4726static int handle_invd(struct kvm_vcpu *vcpu)
4727{
51d8b661 4728 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN
4729}
4730
851ba692 4731static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4732{
f9c617f6 4733 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT
4734
4735 kvm_mmu_invlpg(vcpu, exit_qualification);
4736 skip_emulated_instruction(vcpu);
4737 return 1;
4738}
4739
fee84b07
AK
4740static int handle_rdpmc(struct kvm_vcpu *vcpu)
4741{
4742 int err;
4743
4744 err = kvm_rdpmc(vcpu);
4745 kvm_complete_insn_gp(vcpu, err);
4746
4747 return 1;
4748}
4749
851ba692 4750static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED
4751{
4752 skip_emulated_instruction(vcpu);
f5f48ee1 4753 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED
4754 return 1;
4755}
4756
2acf923e
DC
4757static int handle_xsetbv(struct kvm_vcpu *vcpu)
4758{
4759 u64 new_bv = kvm_read_edx_eax(vcpu);
4760 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4761
4762 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4763 skip_emulated_instruction(vcpu);
4764 return 1;
4765}
4766
851ba692 4767static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4768{
58fbbf26
KT
4769 if (likely(fasteoi)) {
4770 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4771 int access_type, offset;
4772
4773 access_type = exit_qualification & APIC_ACCESS_TYPE;
4774 offset = exit_qualification & APIC_ACCESS_OFFSET;
4775 /*
4776 * Sane guest uses MOV to write EOI, with written value
4777 * not cared. So make a short-circuit here by avoiding
4778 * heavy instruction emulation.
4779 */
4780 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4781 (offset == APIC_EOI)) {
4782 kvm_lapic_set_eoi(vcpu);
4783 skip_emulated_instruction(vcpu);
4784 return 1;
4785 }
4786 }
51d8b661 4787 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY
4788}
4789
851ba692 4790static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4791{
60637aac 4792 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4793 unsigned long exit_qualification;
e269fb21
JK
4794 bool has_error_code = false;
4795 u32 error_code = 0;
37817f29 4796 u16 tss_selector;
7f3d35fd 4797 int reason, type, idt_v, idt_index;
64a7ec06
GN
4798
4799 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4800 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4801 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE
4802
4803 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4804
4805 reason = (u32)exit_qualification >> 30;
64a7ec06
GN
4806 if (reason == TASK_SWITCH_GATE && idt_v) {
4807 switch (type) {
4808 case INTR_TYPE_NMI_INTR:
4809 vcpu->arch.nmi_injected = false;
654f06fc 4810 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN
4811 break;
4812 case INTR_TYPE_EXT_INTR:
66fd3f7f 4813 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN
4814 kvm_clear_interrupt_queue(vcpu);
4815 break;
4816 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK
4817 if (vmx->idt_vectoring_info &
4818 VECTORING_INFO_DELIVER_CODE_MASK) {
4819 has_error_code = true;
4820 error_code =
4821 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4822 }
4823 /* fall through */
64a7ec06
GN
4824 case INTR_TYPE_SOFT_EXCEPTION:
4825 kvm_clear_exception_queue(vcpu);
4826 break;
4827 default:
4828 break;
4829 }
60637aac 4830 }
37817f29
IE
4831 tss_selector = exit_qualification;
4832
64a7ec06
GN
4833 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4834 type != INTR_TYPE_EXT_INTR &&
4835 type != INTR_TYPE_NMI_INTR))
4836 skip_emulated_instruction(vcpu);
4837
7f3d35fd
KW
4838 if (kvm_task_switch(vcpu, tss_selector,
4839 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4840 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN
4841 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4842 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4843 vcpu->run->internal.ndata = 0;
42dbaa5a 4844 return 0;
acb54517 4845 }
42dbaa5a
JK
4846
4847 /* clear all local breakpoint enable flags */
4848 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4849
4850 /*
4851 * TODO: What about debug traps on tss switch?
4852 * Are we supposed to inject them and update dr6?
4853 */
4854
4855 return 1;
37817f29
IE
4856}
4857
851ba692 4858static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4859{
f9c617f6 4860 unsigned long exit_qualification;
1439442c 4861 gpa_t gpa;
4f5982a5 4862 u32 error_code;
1439442c 4863 int gla_validity;
1439442c 4864
f9c617f6 4865 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4866
1439442c
SY
4867 gla_validity = (exit_qualification >> 7) & 0x3;
4868 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4869 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4870 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4871 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4872 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY
4873 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4874 (long unsigned int)exit_qualification);
851ba692
AK
4875 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4876 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4877 return 0;
1439442c
SY
4878 }
4879
4880 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4881 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG
4882
4883 /* It is a write fault? */
4884 error_code = exit_qualification & (1U << 1);
4885 /* ept page table is present? */
4886 error_code |= (exit_qualification >> 3) & 0x1;
4887
4888 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY
4889}
4890
68f89400
MT
4891static u64 ept_rsvd_mask(u64 spte, int level)
4892{
4893 int i;
4894 u64 mask = 0;
4895
4896 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4897 mask |= (1ULL << i);
4898
4899 if (level > 2)
4900 /* bits 7:3 reserved */
4901 mask |= 0xf8;
4902 else if (level == 2) {
4903 if (spte & (1ULL << 7))
4904 /* 2MB ref, bits 20:12 reserved */
4905 mask |= 0x1ff000;
4906 else
4907 /* bits 6:3 reserved */
4908 mask |= 0x78;
4909 }
4910
4911 return mask;
4912}
4913
4914static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4915 int level)
4916{
4917 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4918
4919 /* 010b (write-only) */
4920 WARN_ON((spte & 0x7) == 0x2);
4921
4922 /* 110b (write/execute) */
4923 WARN_ON((spte & 0x7) == 0x6);
4924
4925 /* 100b (execute-only) and value not supported by logical processor */
4926 if (!cpu_has_vmx_ept_execute_only())
4927 WARN_ON((spte & 0x7) == 0x4);
4928
4929 /* not 000b */
4930 if ((spte & 0x7)) {
4931 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4932
4933 if (rsvd_bits != 0) {
4934 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4935 __func__, rsvd_bits);
4936 WARN_ON(1);
4937 }
4938
4939 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4940 u64 ept_mem_type = (spte & 0x38) >> 3;
4941
4942 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4943 ept_mem_type == 7) {
4944 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4945 __func__, ept_mem_type);
4946 WARN_ON(1);
4947 }
4948 }
4949 }
4950}
4951
851ba692 4952static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT
4953{
4954 u64 sptes[4];
ce88decf 4955 int nr_sptes, i, ret;
68f89400
MT
4956 gpa_t gpa;
4957
4958 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4959
ce88decf
XG
4960 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4961 if (likely(ret == 1))
4962 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4963 EMULATE_DONE;
4964 if (unlikely(!ret))
4965 return 1;
4966
4967 /* It is the real ept misconfig */
68f89400
MT
4968 printk(KERN_ERR "EPT: Misconfiguration.\n");
4969 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4970
4971 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4972
4973 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4974 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4975
851ba692
AK
4976 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4977 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT
4978
4979 return 0;
4980}
4981
851ba692 4982static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY
4983{
4984 u32 cpu_based_vm_exec_control;
4985
4986 /* clear pending NMI */
4987 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4988 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4989 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4990 ++vcpu->stat.nmi_window_exits;
3842d135 4991 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY
4992
4993 return 1;
4994}
4995
80ced186 4996static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4997{
8b3079a5
AK
4998 struct vcpu_vmx *vmx = to_vmx(vcpu);
4999 enum emulation_result err = EMULATE_DONE;
80ced186 5000 int ret = 1;
49e9d557
AK
5001 u32 cpu_exec_ctrl;
5002 bool intr_window_requested;
b8405c18 5003 unsigned count = 130;
49e9d557
AK
5004
5005 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5006 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5007
b8405c18 5008 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5009 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK
5010 return handle_interrupt_window(&vmx->vcpu);
5011
de87dcdd
AK
5012 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5013 return 1;
5014
51d8b661 5015 err = emulate_instruction(vcpu, 0);
ea953ef0 5016
80ced186
MG
5017 if (err == EMULATE_DO_MMIO) {
5018 ret = 0;
5019 goto out;
5020 }
1d5a4d9b 5021
de5f70e0
AK
5022 if (err != EMULATE_DONE) {
5023 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5024 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5025 vcpu->run->internal.ndata = 0;
6d77dbfc 5026 return 0;
de5f70e0 5027 }
ea953ef0
MG
5028
5029 if (signal_pending(current))
80ced186 5030 goto out;
ea953ef0
MG
5031 if (need_resched())
5032 schedule();
5033 }
5034
7c068e45 5035 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG
5036out:
5037 return ret;
ea953ef0
MG
5038}
5039
4b8d54f9
ZE
5040/*
5041 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5042 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5043 */
9fb41ba8 5044static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE
5045{
5046 skip_emulated_instruction(vcpu);
5047 kvm_vcpu_on_spin(vcpu);
5048
5049 return 1;
5050}
5051
59708670
SY
5052static int handle_invalid_op(struct kvm_vcpu *vcpu)
5053{
5054 kvm_queue_exception(vcpu, UD_VECTOR);
5055 return 1;
5056}
5057
ff2f6fe9
NHE
5058/*
5059 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5060 * We could reuse a single VMCS for all the L2 guests, but we also want the
5061 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5062 * allows keeping them loaded on the processor, and in the future will allow
5063 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5064 * every entry if they never change.
5065 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5066 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5067 *
5068 * The following functions allocate and free a vmcs02 in this pool.
5069 */
5070
5071/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5072static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5073{
5074 struct vmcs02_list *item;
5075 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5076 if (item->vmptr == vmx->nested.current_vmptr) {
5077 list_move(&item->list, &vmx->nested.vmcs02_pool);
5078 return &item->vmcs02;
5079 }
5080
5081 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5082 /* Recycle the least recently used VMCS. */
5083 item = list_entry(vmx->nested.vmcs02_pool.prev,
5084 struct vmcs02_list, list);
5085 item->vmptr = vmx->nested.current_vmptr;
5086 list_move(&item->list, &vmx->nested.vmcs02_pool);
5087 return &item->vmcs02;
5088 }
5089
5090 /* Create a new VMCS */
5091 item = (struct vmcs02_list *)
5092 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5093 if (!item)
5094 return NULL;
5095 item->vmcs02.vmcs = alloc_vmcs();
5096 if (!item->vmcs02.vmcs) {
5097 kfree(item);
5098 return NULL;
5099 }
5100 loaded_vmcs_init(&item->vmcs02);
5101 item->vmptr = vmx->nested.current_vmptr;
5102 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5103 vmx->nested.vmcs02_num++;
5104 return &item->vmcs02;
5105}
5106
5107/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5108static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5109{
5110 struct vmcs02_list *item;
5111 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5112 if (item->vmptr == vmptr) {
5113 free_loaded_vmcs(&item->vmcs02);
5114 list_del(&item->list);
5115 kfree(item);
5116 vmx->nested.vmcs02_num--;
5117 return;
5118 }
5119}
5120
5121/*
5122 * Free all VMCSs saved for this vcpu, except the one pointed by
5123 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5124 * currently used, if running L2), and vmcs01 when running L2.
5125 */
5126static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5127{
5128 struct vmcs02_list *item, *n;
5129 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5130 if (vmx->loaded_vmcs != &item->vmcs02)
5131 free_loaded_vmcs(&item->vmcs02);
5132 list_del(&item->list);
5133 kfree(item);
5134 }
5135 vmx->nested.vmcs02_num = 0;
5136
5137 if (vmx->loaded_vmcs != &vmx->vmcs01)
5138 free_loaded_vmcs(&vmx->vmcs01);
5139}
5140
ec378aee
NHE
5141/*
5142 * Emulate the VMXON instruction.
5143 * Currently, we just remember that VMX is active, and do not save or even
5144 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5145 * do not currently need to store anything in that guest-allocated memory
5146 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5147 * argument is different from the VMXON pointer (which the spec says they do).
5148 */
5149static int handle_vmon(struct kvm_vcpu *vcpu)
5150{
5151 struct kvm_segment cs;
5152 struct vcpu_vmx *vmx = to_vmx(vcpu);
5153
5154 /* The Intel VMX Instruction Reference lists a bunch of bits that
5155 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5156 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5157 * Otherwise, we should fail with #UD. We test these now:
5158 */
5159 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5160 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5161 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5162 kvm_queue_exception(vcpu, UD_VECTOR);
5163 return 1;
5164 }
5165
5166 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5167 if (is_long_mode(vcpu) && !cs.l) {
5168 kvm_queue_exception(vcpu, UD_VECTOR);
5169 return 1;
5170 }
5171
5172 if (vmx_get_cpl(vcpu)) {
5173 kvm_inject_gp(vcpu, 0);
5174 return 1;
5175 }
5176
ff2f6fe9
NHE
5177 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5178 vmx->nested.vmcs02_num = 0;
5179
ec378aee
NHE
5180 vmx->nested.vmxon = true;
5181
5182 skip_emulated_instruction(vcpu);
5183 return 1;
5184}
5185
5186/*
5187 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5188 * for running VMX instructions (except VMXON, whose prerequisites are
5189 * slightly different). It also specifies what exception to inject otherwise.
5190 */
5191static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5192{
5193 struct kvm_segment cs;
5194 struct vcpu_vmx *vmx = to_vmx(vcpu);
5195
5196 if (!vmx->nested.vmxon) {
5197 kvm_queue_exception(vcpu, UD_VECTOR);
5198 return 0;
5199 }
5200
5201 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5202 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5203 (is_long_mode(vcpu) && !cs.l)) {
5204 kvm_queue_exception(vcpu, UD_VECTOR);
5205 return 0;
5206 }
5207
5208 if (vmx_get_cpl(vcpu)) {
5209 kvm_inject_gp(vcpu, 0);
5210 return 0;
5211 }
5212
5213 return 1;
5214}
5215
5216/*
5217 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5218 * just stops using VMX.
5219 */
5220static void free_nested(struct vcpu_vmx *vmx)
5221{
5222 if (!vmx->nested.vmxon)
5223 return;
5224 vmx->nested.vmxon = false;
a9d30f33
NHE
5225 if (vmx->nested.current_vmptr != -1ull) {
5226 kunmap(vmx->nested.current_vmcs12_page);
5227 nested_release_page(vmx->nested.current_vmcs12_page);
5228 vmx->nested.current_vmptr = -1ull;
5229 vmx->nested.current_vmcs12 = NULL;
5230 }
fe3ef05c
NHE
5231 /* Unpin physical memory we referred to in current vmcs02 */
5232 if (vmx->nested.apic_access_page) {
5233 nested_release_page(vmx->nested.apic_access_page);
5234 vmx->nested.apic_access_page = 0;
5235 }
ff2f6fe9
NHE
5236
5237 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE
5238}
5239
5240/* Emulate the VMXOFF instruction */
5241static int handle_vmoff(struct kvm_vcpu *vcpu)
5242{
5243 if (!nested_vmx_check_permission(vcpu))
5244 return 1;
5245 free_nested(to_vmx(vcpu));
5246 skip_emulated_instruction(vcpu);
5247 return 1;
5248}
5249
064aea77
NHE
5250/*
5251 * Decode the memory-address operand of a vmx instruction, as recorded on an
5252 * exit caused by such an instruction (run by a guest hypervisor).
5253 * On success, returns 0. When the operand is invalid, returns 1 and throws
5254 * #UD or #GP.
5255 */
5256static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5257 unsigned long exit_qualification,
5258 u32 vmx_instruction_info, gva_t *ret)
5259{
5260 /*
5261 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5262 * Execution", on an exit, vmx_instruction_info holds most of the
5263 * addressing components of the operand. Only the displacement part
5264 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5265 * For how an actual address is calculated from all these components,
5266 * refer to Vol. 1, "Operand Addressing".
5267 */
5268 int scaling = vmx_instruction_info & 3;
5269 int addr_size = (vmx_instruction_info >> 7) & 7;
5270 bool is_reg = vmx_instruction_info & (1u << 10);
5271 int seg_reg = (vmx_instruction_info >> 15) & 7;
5272 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5273 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5274 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5275 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5276
5277 if (is_reg) {
5278 kvm_queue_exception(vcpu, UD_VECTOR);
5279 return 1;
5280 }
5281
5282 /* Addr = segment_base + offset */
5283 /* offset = base + [index * scale] + displacement */
5284 *ret = vmx_get_segment_base(vcpu, seg_reg);
5285 if (base_is_valid)
5286 *ret += kvm_register_read(vcpu, base_reg);
5287 if (index_is_valid)
5288 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5289 *ret += exit_qualification; /* holds the displacement */
5290
5291 if (addr_size == 1) /* 32 bit */
5292 *ret &= 0xffffffff;
5293
5294 /*
5295 * TODO: throw #GP (and return 1) in various cases that the VM*
5296 * instructions require it - e.g., offset beyond segment limit,
5297 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5298 * address, and so on. Currently these are not checked.
5299 */
5300 return 0;
5301}
5302
0140caea
NHE
5303/*
5304 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5305 * set the success or error code of an emulated VMX instruction, as specified
5306 * by Vol 2B, VMX Instruction Reference, "Conventions".
5307 */
5308static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5309{
5310 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5311 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5312 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5313}
5314
5315static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5316{
5317 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5318 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5319 X86_EFLAGS_SF | X86_EFLAGS_OF))
5320 | X86_EFLAGS_CF);
5321}
5322
5323static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5324 u32 vm_instruction_error)
5325{
5326 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5327 /*
5328 * failValid writes the error number to the current VMCS, which
5329 * can't be done there isn't a current VMCS.
5330 */
5331 nested_vmx_failInvalid(vcpu);
5332 return;
5333 }
5334 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5335 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5336 X86_EFLAGS_SF | X86_EFLAGS_OF))
5337 | X86_EFLAGS_ZF);
5338 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5339}
5340
27d6c865
NHE
5341/* Emulate the VMCLEAR instruction */
5342static int handle_vmclear(struct kvm_vcpu *vcpu)
5343{
5344 struct vcpu_vmx *vmx = to_vmx(vcpu);
5345 gva_t gva;
5346 gpa_t vmptr;
5347 struct vmcs12 *vmcs12;
5348 struct page *page;
5349 struct x86_exception e;
5350
5351 if (!nested_vmx_check_permission(vcpu))
5352 return 1;
5353
5354 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5355 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5356 return 1;
5357
5358 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5359 sizeof(vmptr), &e)) {
5360 kvm_inject_page_fault(vcpu, &e);
5361 return 1;
5362 }
5363
5364 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5365 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5366 skip_emulated_instruction(vcpu);
5367 return 1;
5368 }
5369
5370 if (vmptr == vmx->nested.current_vmptr) {
5371 kunmap(vmx->nested.current_vmcs12_page);
5372 nested_release_page(vmx->nested.current_vmcs12_page);
5373 vmx->nested.current_vmptr = -1ull;
5374 vmx->nested.current_vmcs12 = NULL;
5375 }
5376
5377 page = nested_get_page(vcpu, vmptr);
5378 if (page == NULL) {
5379 /*
5380 * For accurate processor emulation, VMCLEAR beyond available
5381 * physical memory should do nothing at all. However, it is
5382 * possible that a nested vmx bug, not a guest hypervisor bug,
5383 * resulted in this case, so let's shut down before doing any
5384 * more damage:
5385 */
5386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5387 return 1;
5388 }
5389 vmcs12 = kmap(page);
5390 vmcs12->launch_state = 0;
5391 kunmap(page);
5392 nested_release_page(page);
5393
5394 nested_free_vmcs02(vmx, vmptr);
5395
5396 skip_emulated_instruction(vcpu);
5397 nested_vmx_succeed(vcpu);
5398 return 1;
5399}
5400
cd232ad0
NHE
5401static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5402
5403/* Emulate the VMLAUNCH instruction */
5404static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5405{
5406 return nested_vmx_run(vcpu, true);
5407}
5408
5409/* Emulate the VMRESUME instruction */
5410static int handle_vmresume(struct kvm_vcpu *vcpu)
5411{
5412
5413 return nested_vmx_run(vcpu, false);
5414}
5415
49f705c5
NHE
5416enum vmcs_field_type {
5417 VMCS_FIELD_TYPE_U16 = 0,
5418 VMCS_FIELD_TYPE_U64 = 1,
5419 VMCS_FIELD_TYPE_U32 = 2,
5420 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5421};
5422
5423static inline int vmcs_field_type(unsigned long field)
5424{
5425 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5426 return VMCS_FIELD_TYPE_U32;
5427 return (field >> 13) & 0x3 ;
5428}
5429
5430static inline int vmcs_field_readonly(unsigned long field)
5431{
5432 return (((field >> 10) & 0x3) == 1);
5433}
5434
5435/*
5436 * Read a vmcs12 field. Since these can have varying lengths and we return
5437 * one type, we chose the biggest type (u64) and zero-extend the return value
5438 * to that size. Note that the caller, handle_vmread, might need to use only
5439 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5440 * 64-bit fields are to be returned).
5441 */
5442static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5443 unsigned long field, u64 *ret)
5444{
5445 short offset = vmcs_field_to_offset(field);
5446 char *p;
5447
5448 if (offset < 0)
5449 return 0;
5450
5451 p = ((char *)(get_vmcs12(vcpu))) + offset;
5452
5453 switch (vmcs_field_type(field)) {
5454 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5455 *ret = *((natural_width *)p);
5456 return 1;
5457 case VMCS_FIELD_TYPE_U16:
5458 *ret = *((u16 *)p);
5459 return 1;
5460 case VMCS_FIELD_TYPE_U32:
5461 *ret = *((u32 *)p);
5462 return 1;
5463 case VMCS_FIELD_TYPE_U64:
5464 *ret = *((u64 *)p);
5465 return 1;
5466 default:
5467 return 0; /* can never happen. */
5468 }
5469}
5470
5471/*
5472 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5473 * used before) all generate the same failure when it is missing.
5474 */
5475static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5476{
5477 struct vcpu_vmx *vmx = to_vmx(vcpu);
5478 if (vmx->nested.current_vmptr == -1ull) {
5479 nested_vmx_failInvalid(vcpu);
5480 skip_emulated_instruction(vcpu);
5481 return 0;
5482 }
5483 return 1;
5484}
5485
5486static int handle_vmread(struct kvm_vcpu *vcpu)
5487{
5488 unsigned long field;
5489 u64 field_value;
5490 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5491 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5492 gva_t gva = 0;
5493
5494 if (!nested_vmx_check_permission(vcpu) ||
5495 !nested_vmx_check_vmcs12(vcpu))
5496 return 1;
5497
5498 /* Decode instruction info and find the field to read */
5499 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5500 /* Read the field, zero-extended to a u64 field_value */
5501 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5502 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5503 skip_emulated_instruction(vcpu);
5504 return 1;
5505 }
5506 /*
5507 * Now copy part of this value to register or memory, as requested.
5508 * Note that the number of bits actually copied is 32 or 64 depending
5509 * on the guest's mode (32 or 64 bit), not on the given field's length.
5510 */
5511 if (vmx_instruction_info & (1u << 10)) {
5512 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5513 field_value);
5514 } else {
5515 if (get_vmx_mem_address(vcpu, exit_qualification,
5516 vmx_instruction_info, &gva))
5517 return 1;
5518 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5519 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5520 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5521 }
5522
5523 nested_vmx_succeed(vcpu);
5524 skip_emulated_instruction(vcpu);
5525 return 1;
5526}
5527
5528
5529static int handle_vmwrite(struct kvm_vcpu *vcpu)
5530{
5531 unsigned long field;
5532 gva_t gva;
5533 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5534 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5535 char *p;
5536 short offset;
5537 /* The value to write might be 32 or 64 bits, depending on L1's long
5538 * mode, and eventually we need to write that into a field of several
5539 * possible lengths. The code below first zero-extends the value to 64
5540 * bit (field_value), and then copies only the approriate number of
5541 * bits into the vmcs12 field.
5542 */
5543 u64 field_value = 0;
5544 struct x86_exception e;
5545
5546 if (!nested_vmx_check_permission(vcpu) ||
5547 !nested_vmx_check_vmcs12(vcpu))
5548 return 1;
5549
5550 if (vmx_instruction_info & (1u << 10))
5551 field_value = kvm_register_read(vcpu,
5552 (((vmx_instruction_info) >> 3) & 0xf));
5553 else {
5554 if (get_vmx_mem_address(vcpu, exit_qualification,
5555 vmx_instruction_info, &gva))
5556 return 1;
5557 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5558 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5559 kvm_inject_page_fault(vcpu, &e);
5560 return 1;
5561 }
5562 }
5563
5564
5565 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5566 if (vmcs_field_readonly(field)) {
5567 nested_vmx_failValid(vcpu,
5568 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5569 skip_emulated_instruction(vcpu);
5570 return 1;
5571 }
5572
5573 offset = vmcs_field_to_offset(field);
5574 if (offset < 0) {
5575 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5576 skip_emulated_instruction(vcpu);
5577 return 1;
5578 }
5579 p = ((char *) get_vmcs12(vcpu)) + offset;
5580
5581 switch (vmcs_field_type(field)) {
5582 case VMCS_FIELD_TYPE_U16:
5583 *(u16 *)p = field_value;
5584 break;
5585 case VMCS_FIELD_TYPE_U32:
5586 *(u32 *)p = field_value;
5587 break;
5588 case VMCS_FIELD_TYPE_U64:
5589 *(u64 *)p = field_value;
5590 break;
5591 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5592 *(natural_width *)p = field_value;
5593 break;
5594 default:
5595 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5596 skip_emulated_instruction(vcpu);
5597 return 1;
5598 }
5599
5600 nested_vmx_succeed(vcpu);
5601 skip_emulated_instruction(vcpu);
5602 return 1;
5603}
5604
63846663
NHE
5605/* Emulate the VMPTRLD instruction */
5606static int handle_vmptrld(struct kvm_vcpu *vcpu)
5607{
5608 struct vcpu_vmx *vmx = to_vmx(vcpu);
5609 gva_t gva;
5610 gpa_t vmptr;
5611 struct x86_exception e;
5612
5613 if (!nested_vmx_check_permission(vcpu))
5614 return 1;
5615
5616 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5617 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5618 return 1;
5619
5620 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5621 sizeof(vmptr), &e)) {
5622 kvm_inject_page_fault(vcpu, &e);
5623 return 1;
5624 }
5625
5626 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5627 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5628 skip_emulated_instruction(vcpu);
5629 return 1;
5630 }
5631
5632 if (vmx->nested.current_vmptr != vmptr) {
5633 struct vmcs12 *new_vmcs12;
5634 struct page *page;
5635 page = nested_get_page(vcpu, vmptr);
5636 if (page == NULL) {
5637 nested_vmx_failInvalid(vcpu);
5638 skip_emulated_instruction(vcpu);
5639 return 1;
5640 }
5641 new_vmcs12 = kmap(page);
5642 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5643 kunmap(page);
5644 nested_release_page_clean(page);
5645 nested_vmx_failValid(vcpu,
5646 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5647 skip_emulated_instruction(vcpu);
5648 return 1;
5649 }
5650 if (vmx->nested.current_vmptr != -1ull) {
5651 kunmap(vmx->nested.current_vmcs12_page);
5652 nested_release_page(vmx->nested.current_vmcs12_page);
5653 }
5654
5655 vmx->nested.current_vmptr = vmptr;
5656 vmx->nested.current_vmcs12 = new_vmcs12;
5657 vmx->nested.current_vmcs12_page = page;
5658 }
5659
5660 nested_vmx_succeed(vcpu);
5661 skip_emulated_instruction(vcpu);
5662 return 1;
5663}
5664
6a4d7550
NHE
5665/* Emulate the VMPTRST instruction */
5666static int handle_vmptrst(struct kvm_vcpu *vcpu)
5667{
5668 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5669 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5670 gva_t vmcs_gva;
5671 struct x86_exception e;
5672
5673 if (!nested_vmx_check_permission(vcpu))
5674 return 1;
5675
5676 if (get_vmx_mem_address(vcpu, exit_qualification,
5677 vmx_instruction_info, &vmcs_gva))
5678 return 1;
5679 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5680 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5681 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5682 sizeof(u64), &e)) {
5683 kvm_inject_page_fault(vcpu, &e);
5684 return 1;
5685 }
5686 nested_vmx_succeed(vcpu);
5687 skip_emulated_instruction(vcpu);
5688 return 1;
5689}
5690
6aa8b732
AK
5691/*
5692 * The exit handlers return 1 if the exit was handled fully and guest execution
5693 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5694 * to be done to userspace and return 0.
5695 */
772e0318 5696static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK
5697 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5698 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5699 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5700 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5701 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK
5702 [EXIT_REASON_CR_ACCESS] = handle_cr,
5703 [EXIT_REASON_DR_ACCESS] = handle_dr,
5704 [EXIT_REASON_CPUID] = handle_cpuid,
5705 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5706 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5707 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5708 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5709 [EXIT_REASON_INVD] = handle_invd,
a7052897 5710 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5711 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5712 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5713 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5714 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5715 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5716 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5717 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5718 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5719 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE
5720 [EXIT_REASON_VMOFF] = handle_vmoff,
5721 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY
5722 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5723 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5724 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5725 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5726 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5727 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT
5728 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5729 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5730 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY
5731 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5732 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK
5733};
5734
5735static const int kvm_vmx_max_exit_handlers =
50a3485c 5736 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5737
644d711a
NHE
5738/*
5739 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5740 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5741 * disinterest in the current event (read or write a specific MSR) by using an
5742 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5743 */
5744static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5745 struct vmcs12 *vmcs12, u32 exit_reason)
5746{
5747 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5748 gpa_t bitmap;
5749
5750 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5751 return 1;
5752
5753 /*
5754 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5755 * for the four combinations of read/write and low/high MSR numbers.
5756 * First we need to figure out which of the four to use:
5757 */
5758 bitmap = vmcs12->msr_bitmap;
5759 if (exit_reason == EXIT_REASON_MSR_WRITE)
5760 bitmap += 2048;
5761 if (msr_index >= 0xc0000000) {
5762 msr_index -= 0xc0000000;
5763 bitmap += 1024;
5764 }
5765
5766 /* Then read the msr_index'th bit from this bitmap: */
5767 if (msr_index < 1024*8) {
5768 unsigned char b;
5769 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5770 return 1 & (b >> (msr_index & 7));
5771 } else
5772 return 1; /* let L1 handle the wrong parameter */
5773}
5774
5775/*
5776 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5777 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5778 * intercept (via guest_host_mask etc.) the current event.
5779 */
5780static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5781 struct vmcs12 *vmcs12)
5782{
5783 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5784 int cr = exit_qualification & 15;
5785 int reg = (exit_qualification >> 8) & 15;
5786 unsigned long val = kvm_register_read(vcpu, reg);
5787
5788 switch ((exit_qualification >> 4) & 3) {
5789 case 0: /* mov to cr */
5790 switch (cr) {
5791 case 0:
5792 if (vmcs12->cr0_guest_host_mask &
5793 (val ^ vmcs12->cr0_read_shadow))
5794 return 1;
5795 break;
5796 case 3:
5797 if ((vmcs12->cr3_target_count >= 1 &&
5798 vmcs12->cr3_target_value0 == val) ||
5799 (vmcs12->cr3_target_count >= 2 &&
5800 vmcs12->cr3_target_value1 == val) ||
5801 (vmcs12->cr3_target_count >= 3 &&
5802 vmcs12->cr3_target_value2 == val) ||
5803 (vmcs12->cr3_target_count >= 4 &&
5804 vmcs12->cr3_target_value3 == val))
5805 return 0;
5806 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5807 return 1;
5808 break;
5809 case 4:
5810 if (vmcs12->cr4_guest_host_mask &
5811 (vmcs12->cr4_read_shadow ^ val))
5812 return 1;
5813 break;
5814 case 8:
5815 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5816 return 1;
5817 break;
5818 }
5819 break;
5820 case 2: /* clts */
5821 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5822 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5823 return 1;
5824 break;
5825 case 1: /* mov from cr */
5826 switch (cr) {
5827 case 3:
5828 if (vmcs12->cpu_based_vm_exec_control &
5829 CPU_BASED_CR3_STORE_EXITING)
5830 return 1;
5831 break;
5832 case 8:
5833 if (vmcs12->cpu_based_vm_exec_control &
5834 CPU_BASED_CR8_STORE_EXITING)
5835 return 1;
5836 break;
5837 }
5838 break;
5839 case 3: /* lmsw */
5840 /*
5841 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5842 * cr0. Other attempted changes are ignored, with no exit.
5843 */
5844 if (vmcs12->cr0_guest_host_mask & 0xe &
5845 (val ^ vmcs12->cr0_read_shadow))
5846 return 1;
5847 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5848 !(vmcs12->cr0_read_shadow & 0x1) &&
5849 (val & 0x1))
5850 return 1;
5851 break;
5852 }
5853 return 0;
5854}
5855
5856/*
5857 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5858 * should handle it ourselves in L0 (and then continue L2). Only call this
5859 * when in is_guest_mode (L2).
5860 */
5861static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5862{
5863 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5864 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5865 struct vcpu_vmx *vmx = to_vmx(vcpu);
5866 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5867
5868 if (vmx->nested.nested_run_pending)
5869 return 0;
5870
5871 if (unlikely(vmx->fail)) {
bd80158a
JK
5872 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5873 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE
5874 return 1;
5875 }
5876
5877 switch (exit_reason) {
5878 case EXIT_REASON_EXCEPTION_NMI:
5879 if (!is_exception(intr_info))
5880 return 0;
5881 else if (is_page_fault(intr_info))
5882 return enable_ept;
5883 return vmcs12->exception_bitmap &
5884 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5885 case EXIT_REASON_EXTERNAL_INTERRUPT:
5886 return 0;
5887 case EXIT_REASON_TRIPLE_FAULT:
5888 return 1;
5889 case EXIT_REASON_PENDING_INTERRUPT:
5890 case EXIT_REASON_NMI_WINDOW:
5891 /*
5892 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5893 * (aka Interrupt Window Exiting) only when L1 turned it on,
5894 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5895 * Same for NMI Window Exiting.
5896 */
5897 return 1;
5898 case EXIT_REASON_TASK_SWITCH:
5899 return 1;
5900 case EXIT_REASON_CPUID:
5901 return 1;
5902 case EXIT_REASON_HLT:
5903 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5904 case EXIT_REASON_INVD:
5905 return 1;
5906 case EXIT_REASON_INVLPG:
5907 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5908 case EXIT_REASON_RDPMC:
5909 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5910 case EXIT_REASON_RDTSC:
5911 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5912 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5913 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5914 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5915 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5916 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5917 /*
5918 * VMX instructions trap unconditionally. This allows L1 to
5919 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5920 */
5921 return 1;
5922 case EXIT_REASON_CR_ACCESS:
5923 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5924 case EXIT_REASON_DR_ACCESS:
5925 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5926 case EXIT_REASON_IO_INSTRUCTION:
5927 /* TODO: support IO bitmaps */
5928 return 1;
5929 case EXIT_REASON_MSR_READ:
5930 case EXIT_REASON_MSR_WRITE:
5931 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5932 case EXIT_REASON_INVALID_STATE:
5933 return 1;
5934 case EXIT_REASON_MWAIT_INSTRUCTION:
5935 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5936 case EXIT_REASON_MONITOR_INSTRUCTION:
5937 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5938 case EXIT_REASON_PAUSE_INSTRUCTION:
5939 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5940 nested_cpu_has2(vmcs12,
5941 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5942 case EXIT_REASON_MCE_DURING_VMENTRY:
5943 return 0;
5944 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5945 return 1;
5946 case EXIT_REASON_APIC_ACCESS:
5947 return nested_cpu_has2(vmcs12,
5948 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5949 case EXIT_REASON_EPT_VIOLATION:
5950 case EXIT_REASON_EPT_MISCONFIG:
5951 return 0;
5952 case EXIT_REASON_WBINVD:
5953 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5954 case EXIT_REASON_XSETBV:
5955 return 1;
5956 default:
5957 return 1;
5958 }
5959}
5960
586f9607
AK
5961static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5962{
5963 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5964 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5965}
5966
6aa8b732
AK
5967/*
5968 * The guest has exited. See if we can fix it or if we need userspace
5969 * assistance.
5970 */
851ba692 5971static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5972{
29bd8a78 5973 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5974 u32 exit_reason = vmx->exit_reason;
1155f76a 5975 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5976
80ced186
MG
5977 /* If guest state is invalid, start emulating */
5978 if (vmx->emulation_required && emulate_invalid_guest_state)
5979 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5980
b6f1250e
NHE
5981 /*
5982 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5983 * we did not inject a still-pending event to L1 now because of
5984 * nested_run_pending, we need to re-enable this bit.
5985 */
5986 if (vmx->nested.nested_run_pending)
5987 kvm_make_request(KVM_REQ_EVENT, vcpu);
5988
509c75ea
NHE
5989 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5990 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE
5991 vmx->nested.nested_run_pending = 1;
5992 else
5993 vmx->nested.nested_run_pending = 0;
5994
5995 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5996 nested_vmx_vmexit(vcpu);
5997 return 1;
5998 }
5999
5120702e
MG
6000 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6001 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6002 vcpu->run->fail_entry.hardware_entry_failure_reason
6003 = exit_reason;
6004 return 0;
6005 }
6006
29bd8a78 6007 if (unlikely(vmx->fail)) {
851ba692
AK
6008 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6009 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK
6010 = vmcs_read32(VM_INSTRUCTION_ERROR);
6011 return 0;
6012 }
6aa8b732 6013
b9bf6882
XG
6014 /*
6015 * Note:
6016 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6017 * delivery event since it indicates guest is accessing MMIO.
6018 * The vm-exit can be triggered again after return to guest that
6019 * will cause infinite loop.
6020 */
d77c26fc 6021 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6022 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6023 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG
6024 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6025 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6026 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6027 vcpu->run->internal.ndata = 2;
6028 vcpu->run->internal.data[0] = vectoring_info;
6029 vcpu->run->internal.data[1] = exit_reason;
6030 return 0;
6031 }
3b86cd99 6032
644d711a
NHE
6033 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6034 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6035 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6036 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6037 vmx->soft_vnmi_blocked = 0;
3b86cd99 6038 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6039 vcpu->arch.nmi_pending) {
3b86cd99
JK
6040 /*
6041 * This CPU don't support us in finding the end of an
6042 * NMI-blocked window if the guest runs with IRQs
6043 * disabled. So we pull the trigger after 1 s of
6044 * futile waiting, but inform the user about this.
6045 */
6046 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6047 "state on VCPU %d after 1 s timeout\n",
6048 __func__, vcpu->vcpu_id);
6049 vmx->soft_vnmi_blocked = 0;
3b86cd99 6050 }
3b86cd99
JK
6051 }
6052
6aa8b732
AK
6053 if (exit_reason < kvm_vmx_max_exit_handlers
6054 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6055 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6056 else {
851ba692
AK
6057 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6058 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK
6059 }
6060 return 0;
6061}
6062
95ba8273 6063static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6064{
95ba8273 6065 if (irr == -1 || tpr < irr) {
6e5d865c
YS
6066 vmcs_write32(TPR_THRESHOLD, 0);
6067 return;
6068 }
6069
95ba8273 6070 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS
6071}
6072
51aa01d1 6073static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6074{
00eba012
AK
6075 u32 exit_intr_info;
6076
6077 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6078 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6079 return;
6080
c5ca8e57 6081 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6082 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK
6083
6084 /* Handle machine checks before interrupts are enabled */
00eba012 6085 if (is_machine_check(exit_intr_info))
a0861c02
AK
6086 kvm_machine_check();
6087
20f65983 6088 /* We need to handle NMIs before interrupts are enabled */
00eba012 6089 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY
6090 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6091 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6092 asm("int $2");
ff9d07a0
ZY
6093 kvm_after_handle_nmi(&vmx->vcpu);
6094 }
51aa01d1 6095}
20f65983 6096
51aa01d1
AK
6097static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6098{
c5ca8e57 6099 u32 exit_intr_info;
51aa01d1
AK
6100 bool unblock_nmi;
6101 u8 vector;
6102 bool idtv_info_valid;
6103
6104 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6105
cf393f75 6106 if (cpu_has_virtual_nmis()) {
9d58b931
AK
6107 if (vmx->nmi_known_unmasked)
6108 return;
c5ca8e57
AK
6109 /*
6110 * Can't use vmx->exit_intr_info since we're not sure what
6111 * the exit reason is.
6112 */
6113 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK
6114 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6115 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6116 /*
7b4a25cb 6117 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK
6118 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6119 * a guest IRET fault.
7b4a25cb
GN
6120 * SDM 3: 23.2.2 (September 2008)
6121 * Bit 12 is undefined in any of the following cases:
6122 * If the VM exit sets the valid bit in the IDT-vectoring
6123 * information field.
6124 * If the VM exit is due to a double fault.
cf393f75 6125 */
7b4a25cb
GN
6126 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6127 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK
6128 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6129 GUEST_INTR_STATE_NMI);
9d58b931
AK
6130 else
6131 vmx->nmi_known_unmasked =
6132 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6133 & GUEST_INTR_STATE_NMI);
3b86cd99
JK
6134 } else if (unlikely(vmx->soft_vnmi_blocked))
6135 vmx->vnmi_blocked_time +=
6136 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK
6137}
6138
83422e17
AK
6139static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6140 u32 idt_vectoring_info,
6141 int instr_len_field,
6142 int error_code_field)
51aa01d1 6143{
51aa01d1
AK
6144 u8 vector;
6145 int type;
6146 bool idtv_info_valid;
6147
6148 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6149
37b96e98
GN
6150 vmx->vcpu.arch.nmi_injected = false;
6151 kvm_clear_exception_queue(&vmx->vcpu);
6152 kvm_clear_interrupt_queue(&vmx->vcpu);
6153
6154 if (!idtv_info_valid)
6155 return;
6156
3842d135
AK
6157 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6158
668f612f
AK
6159 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6160 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6161
64a7ec06 6162 switch (type) {
37b96e98
GN
6163 case INTR_TYPE_NMI_INTR:
6164 vmx->vcpu.arch.nmi_injected = true;
668f612f 6165 /*
7b4a25cb 6166 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN
6167 * Clear bit "block by NMI" before VM entry if a NMI
6168 * delivery faulted.
668f612f 6169 */
654f06fc 6170 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6171 break;
37b96e98 6172 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6173 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6174 vmcs_read32(instr_len_field);
66fd3f7f
GN
6175 /* fall through */
6176 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6177 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6178 u32 err = vmcs_read32(error_code_field);
37b96e98 6179 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK
6180 } else
6181 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6182 break;
66fd3f7f
GN
6183 case INTR_TYPE_SOFT_INTR:
6184 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6185 vmcs_read32(instr_len_field);
66fd3f7f 6186 /* fall through */
37b96e98 6187 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN
6188 kvm_queue_interrupt(&vmx->vcpu, vector,
6189 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN
6190 break;
6191 default:
6192 break;
f7d9238f 6193 }
cf393f75
AK
6194}
6195
83422e17
AK
6196static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6197{
66c78ae4
NHE
6198 if (is_guest_mode(&vmx->vcpu))
6199 return;
83422e17
AK
6200 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6201 VM_EXIT_INSTRUCTION_LEN,
6202 IDT_VECTORING_ERROR_CODE);
6203}
6204
b463a6f7
AK
6205static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6206{
66c78ae4
NHE
6207 if (is_guest_mode(vcpu))
6208 return;
b463a6f7
AK
6209 __vmx_complete_interrupts(to_vmx(vcpu),
6210 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6211 VM_ENTRY_INSTRUCTION_LEN,
6212 VM_ENTRY_EXCEPTION_ERROR_CODE);
6213
6214 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6215}
6216
d7cd9796
GN
6217static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6218{
6219 int i, nr_msrs;
6220 struct perf_guest_switch_msr *msrs;
6221
6222 msrs = perf_guest_get_msrs(&nr_msrs);
6223
6224 if (!msrs)
6225 return;
6226
6227 for (i = 0; i < nr_msrs; i++)
6228 if (msrs[i].host == msrs[i].guest)
6229 clear_atomic_switch_msr(vmx, msrs[i].msr);
6230 else
6231 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6232 msrs[i].host);
6233}
6234
a3b5ba49 6235static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6236{
a2fa3e9f 6237 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6238 unsigned long debugctlmsr;
104f226b 6239
66c78ae4
NHE
6240 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6241 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6242 if (vmcs12->idt_vectoring_info_field &
6243 VECTORING_INFO_VALID_MASK) {
6244 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6245 vmcs12->idt_vectoring_info_field);
6246 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6247 vmcs12->vm_exit_instruction_len);
6248 if (vmcs12->idt_vectoring_info_field &
6249 VECTORING_INFO_DELIVER_CODE_MASK)
6250 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6251 vmcs12->idt_vectoring_error_code);
6252 }
6253 }
6254
104f226b
AK
6255 /* Record the guest's net vcpu time for enforced NMI injections. */
6256 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6257 vmx->entry_time = ktime_get();
6258
6259 /* Don't enter VMX if guest state is invalid, let the exit handler
6260 start emulation until we arrive back to a valid state */
6261 if (vmx->emulation_required && emulate_invalid_guest_state)
6262 return;
6263
6264 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6265 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6266 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6267 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6268
6269 /* When single-stepping over STI and MOV SS, we must clear the
6270 * corresponding interruptibility bits in the guest state. Otherwise
6271 * vmentry fails as it then expects bit 14 (BS) in pending debug
6272 * exceptions being set, but that's not correct for the guest debugging
6273 * case. */
6274 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6275 vmx_set_interrupt_shadow(vcpu, 0);
6276
d7cd9796 6277 atomic_switch_perf_msrs(vmx);
2a7921b7 6278 debugctlmsr = get_debugctlmsr();
d7cd9796 6279
d462b819 6280 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6281 asm(
6aa8b732 6282 /* Store host registers */
b188c81f
AK
6283 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6284 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6285 "push %%" _ASM_CX " \n\t"
6286 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6287 "je 1f \n\t"
b188c81f 6288 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6289 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6290 "1: \n\t"
d3edefc0 6291 /* Reload cr2 if changed */
b188c81f
AK
6292 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6293 "mov %%cr2, %%" _ASM_DX " \n\t"
6294 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6295 "je 2f \n\t"
b188c81f 6296 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6297 "2: \n\t"
6aa8b732 6298 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6299 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6300 /* Load guest registers. Don't clobber flags. */
b188c81f
AK
6301 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6302 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6303 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6304 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6305 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6306 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6307#ifdef CONFIG_X86_64
e08aa78a
AK
6308 "mov %c[r8](%0), %%r8 \n\t"
6309 "mov %c[r9](%0), %%r9 \n\t"
6310 "mov %c[r10](%0), %%r10 \n\t"
6311 "mov %c[r11](%0), %%r11 \n\t"
6312 "mov %c[r12](%0), %%r12 \n\t"
6313 "mov %c[r13](%0), %%r13 \n\t"
6314 "mov %c[r14](%0), %%r14 \n\t"
6315 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6316#endif
b188c81f 6317 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6318
6aa8b732 6319 /* Enter guest mode */
83287ea4 6320 "jne 1f \n\t"
4ecac3fd 6321 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK
6322 "jmp 2f \n\t"
6323 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6324 "2: "
6aa8b732 6325 /* Save guest registers, load host registers, keep flags */
b188c81f 6326 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6327 "pop %0 \n\t"
b188c81f
AK
6328 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6329 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6330 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6331 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6332 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6333 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6334 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6335#ifdef CONFIG_X86_64
e08aa78a
AK
6336 "mov %%r8, %c[r8](%0) \n\t"
6337 "mov %%r9, %c[r9](%0) \n\t"
6338 "mov %%r10, %c[r10](%0) \n\t"
6339 "mov %%r11, %c[r11](%0) \n\t"
6340 "mov %%r12, %c[r12](%0) \n\t"
6341 "mov %%r13, %c[r13](%0) \n\t"
6342 "mov %%r14, %c[r14](%0) \n\t"
6343 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6344#endif
b188c81f
AK
6345 "mov %%cr2, %%" _ASM_AX " \n\t"
6346 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6347
b188c81f 6348 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6349 "setbe %c[fail](%0) \n\t"
83287ea4
AK
6350 ".pushsection .rodata \n\t"
6351 ".global vmx_return \n\t"
6352 "vmx_return: " _ASM_PTR " 2b \n\t"
6353 ".popsection"
e08aa78a 6354 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6355 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6356 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6357 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX
6358 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6359 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6360 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6361 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6362 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6363 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6364 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6365#ifdef CONFIG_X86_64
ad312c7c
ZX
6366 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6367 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6368 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6369 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6370 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6371 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6372 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6373 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6374#endif
40712fae
AK
6375 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6376 [wordsize]"i"(sizeof(ulong))
c2036300
LV
6377 : "cc", "memory"
6378#ifdef CONFIG_X86_64
b188c81f 6379 , "rax", "rbx", "rdi", "rsi"
c2036300 6380 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK
6381#else
6382 , "eax", "ebx", "edi", "esi"
c2036300
LV
6383#endif
6384 );
6aa8b732 6385
2a7921b7
GN
6386 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6387 if (debugctlmsr)
6388 update_debugctlmsr(debugctlmsr);
6389
aa67f609
AK
6390#ifndef CONFIG_X86_64
6391 /*
6392 * The sysexit path does not restore ds/es, so we must set them to
6393 * a reasonable value ourselves.
6394 *
6395 * We can't defer this to vmx_load_host_state() since that function
6396 * may be executed in interrupt context, which saves and restore segments
6397 * around it, nullifying its effect.
6398 */
6399 loadsegment(ds, __USER_DS);
6400 loadsegment(es, __USER_DS);
6401#endif
6402
6de4f3ad 6403 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6404 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6405 | (1 << VCPU_EXREG_CPL)
aff48baa 6406 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6407 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6408 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT
6409 vcpu->arch.regs_dirty = 0;
6410
1155f76a
AK
6411 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6412
66c78ae4
NHE
6413 if (is_guest_mode(vcpu)) {
6414 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6415 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6416 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6417 vmcs12->idt_vectoring_error_code =
6418 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6419 vmcs12->vm_exit_instruction_len =
6420 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6421 }
6422 }
6423
d462b819 6424 vmx->loaded_vmcs->launched = 1;
1b6269db 6425
51aa01d1 6426 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6427 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK
6428
6429 vmx_complete_atomic_exit(vmx);
6430 vmx_recover_nmi_blocking(vmx);
cf393f75 6431 vmx_complete_interrupts(vmx);
6aa8b732
AK
6432}
6433
6aa8b732
AK
6434static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6435{
fb3f0f51
RR
6436 struct vcpu_vmx *vmx = to_vmx(vcpu);
6437
cdbecfc3 6438 free_vpid(vmx);
ec378aee 6439 free_nested(vmx);
d462b819 6440 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR
6441 kfree(vmx->guest_msrs);
6442 kvm_vcpu_uninit(vcpu);
a4770347 6443 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK
6444}
6445
fb3f0f51 6446static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6447{
fb3f0f51 6448 int err;
c16f862d 6449 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6450 int cpu;
6aa8b732 6451
a2fa3e9f 6452 if (!vmx)
fb3f0f51
RR
6453 return ERR_PTR(-ENOMEM);
6454
2384d2b3
SY
6455 allocate_vpid(vmx);
6456
fb3f0f51
RR
6457 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6458 if (err)
6459 goto free_vcpu;
965b58a5 6460
a2fa3e9f 6461 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6462 err = -ENOMEM;
fb3f0f51 6463 if (!vmx->guest_msrs) {
fb3f0f51
RR
6464 goto uninit_vcpu;
6465 }
965b58a5 6466
d462b819
NHE
6467 vmx->loaded_vmcs = &vmx->vmcs01;
6468 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6469 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6470 goto free_msrs;
d462b819
NHE
6471 if (!vmm_exclusive)
6472 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6473 loaded_vmcs_init(vmx->loaded_vmcs);
6474 if (!vmm_exclusive)
6475 kvm_cpu_vmxoff();
a2fa3e9f 6476
15ad7146
AK
6477 cpu = get_cpu();
6478 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6479 vmx->vcpu.cpu = cpu;
8b9cf98c 6480 err = vmx_vcpu_setup(vmx);
fb3f0f51 6481 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6482 put_cpu();
fb3f0f51
RR
6483 if (err)
6484 goto free_vmcs;
5e4a0b3c 6485 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK
6486 err = alloc_apic_access_page(kvm);
6487 if (err)
5e4a0b3c 6488 goto free_vmcs;
fb3f0f51 6489
b927a3ce
SY
6490 if (enable_ept) {
6491 if (!kvm->arch.ept_identity_map_addr)
6492 kvm->arch.ept_identity_map_addr =
6493 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6494 err = -ENOMEM;
b7ebfb05
SY
6495 if (alloc_identity_pagetable(kvm) != 0)
6496 goto free_vmcs;
93ea5388
GN
6497 if (!init_rmode_identity_map(kvm))
6498 goto free_vmcs;
b927a3ce 6499 }
b7ebfb05 6500
a9d30f33
NHE
6501 vmx->nested.current_vmptr = -1ull;
6502 vmx->nested.current_vmcs12 = NULL;
6503
fb3f0f51
RR
6504 return &vmx->vcpu;
6505
6506free_vmcs:
5f3fbc34 6507 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6508free_msrs:
fb3f0f51
RR
6509 kfree(vmx->guest_msrs);
6510uninit_vcpu:
6511 kvm_vcpu_uninit(&vmx->vcpu);
6512free_vcpu:
cdbecfc3 6513 free_vpid(vmx);
a4770347 6514 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6515 return ERR_PTR(err);
6aa8b732
AK
6516}
6517
002c7f7c
YS
6518static void __init vmx_check_processor_compat(void *rtn)
6519{
6520 struct vmcs_config vmcs_conf;
6521
6522 *(int *)rtn = 0;
6523 if (setup_vmcs_config(&vmcs_conf) < 0)
6524 *(int *)rtn = -EIO;
6525 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6526 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6527 smp_processor_id());
6528 *(int *)rtn = -EIO;
6529 }
6530}
6531
67253af5
SY
6532static int get_ept_level(void)
6533{
6534 return VMX_EPT_DEFAULT_GAW + 1;
6535}
6536
4b12f0de 6537static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6538{
4b12f0de
SY
6539 u64 ret;
6540
522c68c4
SY
6541 /* For VT-d and EPT combination
6542 * 1. MMIO: always map as UC
6543 * 2. EPT with VT-d:
6544 * a. VT-d without snooping control feature: can't guarantee the
6545 * result, try to trust guest.
6546 * b. VT-d with snooping control feature: snooping control feature of
6547 * VT-d engine can guarantee the cache correctness. Just set it
6548 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6549 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY
6550 * consistent with host MTRR
6551 */
4b12f0de
SY
6552 if (is_mmio)
6553 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY
6554 else if (vcpu->kvm->arch.iommu_domain &&
6555 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6556 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6557 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6558 else
522c68c4 6559 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6560 | VMX_EPT_IPAT_BIT;
4b12f0de
SY
6561
6562 return ret;
64d4d521
SY
6563}
6564
17cc3935 6565static int vmx_get_lpage_level(void)
344f414f 6566{
878403b7
SY
6567 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6568 return PT_DIRECTORY_LEVEL;
6569 else
6570 /* For shadow and EPT supported 1GB page */
6571 return PT_PDPE_LEVEL;
344f414f
JR
6572}
6573
0e851880
SY
6574static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6575{
4e47c7a6
SY
6576 struct kvm_cpuid_entry2 *best;
6577 struct vcpu_vmx *vmx = to_vmx(vcpu);
6578 u32 exec_control;
6579
6580 vmx->rdtscp_enabled = false;
6581 if (vmx_rdtscp_supported()) {
6582 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6583 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6584 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6585 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6586 vmx->rdtscp_enabled = true;
6587 else {
6588 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6589 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6590 exec_control);
6591 }
6592 }
6593 }
ad756a16 6594
ad756a16
MJ
6595 /* Exposing INVPCID only when PCID is exposed */
6596 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6597 if (vmx_invpcid_supported() &&
4f977045 6598 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6599 guest_cpuid_has_pcid(vcpu)) {
29282fde 6600 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ
6601 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6602 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6603 exec_control);
6604 } else {
29282fde
TI
6605 if (cpu_has_secondary_exec_ctrls()) {
6606 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6607 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6608 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6609 exec_control);
6610 }
ad756a16 6611 if (best)
4f977045 6612 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6613 }
0e851880
SY
6614}
6615
d4330ef2
JR
6616static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6617{
7b8050f5
NHE
6618 if (func == 1 && nested)
6619 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR
6620}
6621
fe3ef05c
NHE
6622/*
6623 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6624 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6625 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6626 * guest in a way that will both be appropriate to L1's requests, and our
6627 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6628 * function also has additional necessary side-effects, like setting various
6629 * vcpu->arch fields.
6630 */
6631static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6632{
6633 struct vcpu_vmx *vmx = to_vmx(vcpu);
6634 u32 exec_control;
6635
6636 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6637 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6638 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6639 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6640 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6641 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6642 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6643 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6644 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6645 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6646 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6647 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6648 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6649 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6650 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6651 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6652 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6653 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6654 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6655 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6656 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6657 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6658 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6659 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6660 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6661 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6662 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6663 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6664 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6665 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6666 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6667 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6668 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6669 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6670 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6671 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6672
6673 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6674 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6675 vmcs12->vm_entry_intr_info_field);
6676 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6677 vmcs12->vm_entry_exception_error_code);
6678 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6679 vmcs12->vm_entry_instruction_len);
6680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6681 vmcs12->guest_interruptibility_info);
6682 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6683 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6684 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6685 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6686 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6687 vmcs12->guest_pending_dbg_exceptions);
6688 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6689 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6690
6691 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6692
6693 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6694 (vmcs_config.pin_based_exec_ctrl |
6695 vmcs12->pin_based_vm_exec_control));
6696
6697 /*
6698 * Whether page-faults are trapped is determined by a combination of
6699 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6700 * If enable_ept, L0 doesn't care about page faults and we should
6701 * set all of these to L1's desires. However, if !enable_ept, L0 does
6702 * care about (at least some) page faults, and because it is not easy
6703 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6704 * to exit on each and every L2 page fault. This is done by setting
6705 * MASK=MATCH=0 and (see below) EB.PF=1.
6706 * Note that below we don't need special code to set EB.PF beyond the
6707 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6708 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6709 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6710 *
6711 * A problem with this approach (when !enable_ept) is that L1 may be
6712 * injected with more page faults than it asked for. This could have
6713 * caused problems, but in practice existing hypervisors don't care.
6714 * To fix this, we will need to emulate the PFEC checking (on the L1
6715 * page tables), using walk_addr(), when injecting PFs to L1.
6716 */
6717 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6718 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6719 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6720 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6721
6722 if (cpu_has_secondary_exec_ctrls()) {
6723 u32 exec_control = vmx_secondary_exec_control(vmx);
6724 if (!vmx->rdtscp_enabled)
6725 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6726 /* Take the following fields only from vmcs12 */
6727 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6728 if (nested_cpu_has(vmcs12,
6729 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6730 exec_control |= vmcs12->secondary_vm_exec_control;
6731
6732 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6733 /*
6734 * Translate L1 physical address to host physical
6735 * address for vmcs02. Keep the page pinned, so this
6736 * physical address remains valid. We keep a reference
6737 * to it so we can release it later.
6738 */
6739 if (vmx->nested.apic_access_page) /* shouldn't happen */
6740 nested_release_page(vmx->nested.apic_access_page);
6741 vmx->nested.apic_access_page =
6742 nested_get_page(vcpu, vmcs12->apic_access_addr);
6743 /*
6744 * If translation failed, no matter: This feature asks
6745 * to exit when accessing the given address, and if it
6746 * can never be accessed, this feature won't do
6747 * anything anyway.
6748 */
6749 if (!vmx->nested.apic_access_page)
6750 exec_control &=
6751 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6752 else
6753 vmcs_write64(APIC_ACCESS_ADDR,
6754 page_to_phys(vmx->nested.apic_access_page));
6755 }
6756
6757 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6758 }
6759
6760
6761 /*
6762 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6763 * Some constant fields are set here by vmx_set_constant_host_state().
6764 * Other fields are different per CPU, and will be set later when
6765 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6766 */
6767 vmx_set_constant_host_state();
6768
6769 /*
6770 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6771 * entry, but only if the current (host) sp changed from the value
6772 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6773 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6774 * here we just force the write to happen on entry.
6775 */
6776 vmx->host_rsp = 0;
6777
6778 exec_control = vmx_exec_control(vmx); /* L0's desires */
6779 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6780 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6781 exec_control &= ~CPU_BASED_TPR_SHADOW;
6782 exec_control |= vmcs12->cpu_based_vm_exec_control;
6783 /*
6784 * Merging of IO and MSR bitmaps not currently supported.
6785 * Rather, exit every time.
6786 */
6787 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6788 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6789 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6790
6791 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6792
6793 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6794 * bitwise-or of what L1 wants to trap for L2, and what we want to
6795 * trap. Note that CR0.TS also needs updating - we do this later.
6796 */
6797 update_exception_bitmap(vcpu);
6798 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6799 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6800
6801 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6802 vmcs_write32(VM_EXIT_CONTROLS,
6803 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6804 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6805 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6806
6807 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6808 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6809 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6810 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6811
6812
6813 set_cr4_guest_host_mask(vmx);
6814
27fc51b2
NHE
6815 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6816 vmcs_write64(TSC_OFFSET,
6817 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6818 else
6819 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE
6820
6821 if (enable_vpid) {
6822 /*
6823 * Trivially support vpid by letting L2s share their parent
6824 * L1's vpid. TODO: move to a more elaborate solution, giving
6825 * each L2 its own vpid and exposing the vpid feature to L1.
6826 */
6827 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6828 vmx_flush_tlb(vcpu);
6829 }
6830
6831 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6832 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6833 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6834 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6835 else
6836 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6837 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6838 vmx_set_efer(vcpu, vcpu->arch.efer);
6839
6840 /*
6841 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6842 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6843 * The CR0_READ_SHADOW is what L2 should have expected to read given
6844 * the specifications by L1; It's not enough to take
6845 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6846 * have more bits than L1 expected.
6847 */
6848 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6849 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6850
6851 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6852 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6853
6854 /* shadow page tables on either EPT or shadow page tables */
6855 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6856 kvm_mmu_reset_context(vcpu);
6857
6858 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6859 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6860}
6861
cd232ad0
NHE
6862/*
6863 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6864 * for running an L2 nested guest.
6865 */
6866static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6867{
6868 struct vmcs12 *vmcs12;
6869 struct vcpu_vmx *vmx = to_vmx(vcpu);
6870 int cpu;
6871 struct loaded_vmcs *vmcs02;
6872
6873 if (!nested_vmx_check_permission(vcpu) ||
6874 !nested_vmx_check_vmcs12(vcpu))
6875 return 1;
6876
6877 skip_emulated_instruction(vcpu);
6878 vmcs12 = get_vmcs12(vcpu);
6879
7c177938
NHE
6880 /*
6881 * The nested entry process starts with enforcing various prerequisites
6882 * on vmcs12 as required by the Intel SDM, and act appropriately when
6883 * they fail: As the SDM explains, some conditions should cause the
6884 * instruction to fail, while others will cause the instruction to seem
6885 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6886 * To speed up the normal (success) code path, we should avoid checking
6887 * for misconfigurations which will anyway be caught by the processor
6888 * when using the merged vmcs02.
6889 */
6890 if (vmcs12->launch_state == launch) {
6891 nested_vmx_failValid(vcpu,
6892 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6893 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6894 return 1;
6895 }
6896
6897 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6898 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6899 /*TODO: Also verify bits beyond physical address width are 0*/
6900 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6901 return 1;
6902 }
6903
6904 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6905 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6906 /*TODO: Also verify bits beyond physical address width are 0*/
6907 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6908 return 1;
6909 }
6910
6911 if (vmcs12->vm_entry_msr_load_count > 0 ||
6912 vmcs12->vm_exit_msr_load_count > 0 ||
6913 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK
6914 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6915 __func__);
7c177938
NHE
6916 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6917 return 1;
6918 }
6919
6920 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6921 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6922 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6923 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6924 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6925 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6926 !vmx_control_verify(vmcs12->vm_exit_controls,
6927 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6928 !vmx_control_verify(vmcs12->vm_entry_controls,
6929 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6930 {
6931 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6932 return 1;
6933 }
6934
6935 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6936 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6937 nested_vmx_failValid(vcpu,
6938 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6939 return 1;
6940 }
6941
6942 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6943 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6944 nested_vmx_entry_failure(vcpu, vmcs12,
6945 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6946 return 1;
6947 }
6948 if (vmcs12->vmcs_link_pointer != -1ull) {
6949 nested_vmx_entry_failure(vcpu, vmcs12,
6950 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6951 return 1;
6952 }
6953
6954 /*
6955 * We're finally done with prerequisite checking, and can start with
6956 * the nested entry.
6957 */
6958
cd232ad0
NHE
6959 vmcs02 = nested_get_current_vmcs02(vmx);
6960 if (!vmcs02)
6961 return -ENOMEM;
6962
6963 enter_guest_mode(vcpu);
6964
6965 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6966
6967 cpu = get_cpu();
6968 vmx->loaded_vmcs = vmcs02;
6969 vmx_vcpu_put(vcpu);
6970 vmx_vcpu_load(vcpu, cpu);
6971 vcpu->cpu = cpu;
6972 put_cpu();
6973
6974 vmcs12->launch_state = 1;
6975
6976 prepare_vmcs02(vcpu, vmcs12);
6977
6978 /*
6979 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6980 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6981 * returned as far as L1 is concerned. It will only return (and set
6982 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6983 */
6984 return 1;
6985}
6986
4704d0be
NHE
6987/*
6988 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6989 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6990 * This function returns the new value we should put in vmcs12.guest_cr0.
6991 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6992 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6993 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6994 * didn't trap the bit, because if L1 did, so would L0).
6995 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6996 * been modified by L2, and L1 knows it. So just leave the old value of
6997 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6998 * isn't relevant, because if L0 traps this bit it can set it to anything.
6999 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7000 * changed these bits, and therefore they need to be updated, but L0
7001 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7002 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7003 */
7004static inline unsigned long
7005vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7006{
7007 return
7008 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7009 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7010 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7011 vcpu->arch.cr0_guest_owned_bits));
7012}
7013
7014static inline unsigned long
7015vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7016{
7017 return
7018 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7019 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7020 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7021 vcpu->arch.cr4_guest_owned_bits));
7022}
7023
7024/*
7025 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7026 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7027 * and this function updates it to reflect the changes to the guest state while
7028 * L2 was running (and perhaps made some exits which were handled directly by L0
7029 * without going back to L1), and to reflect the exit reason.
7030 * Note that we do not have to copy here all VMCS fields, just those that
7031 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7032 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7033 * which already writes to vmcs12 directly.
7034 */
7035void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7036{
7037 /* update guest state fields: */
7038 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7039 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7040
7041 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7042 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7043 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7044 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7045
7046 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7047 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7048 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7049 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7050 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7051 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7052 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7053 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7054 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7055 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7056 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7057 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7058 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7059 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7060 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7061 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7062 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7063 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7064 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7065 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7066 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7067 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7068 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7069 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7070 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7071 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7072 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7073 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7074 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7075 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7076 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7077 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7078 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7079 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7080 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7081 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7082
7083 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7084 vmcs12->guest_interruptibility_info =
7085 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7086 vmcs12->guest_pending_dbg_exceptions =
7087 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7088
7089 /* TODO: These cannot have changed unless we have MSR bitmaps and
7090 * the relevant bit asks not to trap the change */
7091 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7092 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7093 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7094 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7095 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7096 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7097
7098 /* update exit information fields: */
7099
7100 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7101 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7102
7103 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7104 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7105 vmcs12->idt_vectoring_info_field =
7106 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7107 vmcs12->idt_vectoring_error_code =
7108 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7109 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7110 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7111
7112 /* clear vm-entry fields which are to be cleared on exit */
7113 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7114 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7115}
7116
7117/*
7118 * A part of what we need to when the nested L2 guest exits and we want to
7119 * run its L1 parent, is to reset L1's guest state to the host state specified
7120 * in vmcs12.
7121 * This function is to be called not only on normal nested exit, but also on
7122 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7123 * Failures During or After Loading Guest State").
7124 * This function should be called when the active VMCS is L1's (vmcs01).
7125 */
7126void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7127{
7128 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7129 vcpu->arch.efer = vmcs12->host_ia32_efer;
7130 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7131 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7132 else
7133 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7134 vmx_set_efer(vcpu, vcpu->arch.efer);
7135
7136 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7137 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7138 /*
7139 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7140 * actually changed, because it depends on the current state of
7141 * fpu_active (which may have changed).
7142 * Note that vmx_set_cr0 refers to efer set above.
7143 */
7144 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7145 /*
7146 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7147 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7148 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7149 */
7150 update_exception_bitmap(vcpu);
7151 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7152 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7153
7154 /*
7155 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7156 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7157 */
7158 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7159 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7160
7161 /* shadow page tables on either EPT or shadow page tables */
7162 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7163 kvm_mmu_reset_context(vcpu);
7164
7165 if (enable_vpid) {
7166 /*
7167 * Trivially support vpid by letting L2s share their parent
7168 * L1's vpid. TODO: move to a more elaborate solution, giving
7169 * each L2 its own vpid and exposing the vpid feature to L1.
7170 */
7171 vmx_flush_tlb(vcpu);
7172 }
7173
7174
7175 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7176 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7177 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7178 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7179 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7180 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7181 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7182 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7183 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7184 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7185 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7186 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7187 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7188 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7189 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7190
7191 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7192 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7193 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7194 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7195 vmcs12->host_ia32_perf_global_ctrl);
7196}
7197
7198/*
7199 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7200 * and modify vmcs12 to make it see what it would expect to see there if
7201 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7202 */
7203static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7204{
7205 struct vcpu_vmx *vmx = to_vmx(vcpu);
7206 int cpu;
7207 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7208
7209 leave_guest_mode(vcpu);
7210 prepare_vmcs12(vcpu, vmcs12);
7211
7212 cpu = get_cpu();
7213 vmx->loaded_vmcs = &vmx->vmcs01;
7214 vmx_vcpu_put(vcpu);
7215 vmx_vcpu_load(vcpu, cpu);
7216 vcpu->cpu = cpu;
7217 put_cpu();
7218
7219 /* if no vmcs02 cache requested, remove the one we used */
7220 if (VMCS02_POOL_SIZE == 0)
7221 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7222
7223 load_vmcs12_host_state(vcpu, vmcs12);
7224
27fc51b2 7225 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE
7226 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7227
7228 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7229 vmx->host_rsp = 0;
7230
7231 /* Unpin physical memory we referred to in vmcs02 */
7232 if (vmx->nested.apic_access_page) {
7233 nested_release_page(vmx->nested.apic_access_page);
7234 vmx->nested.apic_access_page = 0;
7235 }
7236
7237 /*
7238 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7239 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7240 * success or failure flag accordingly.
7241 */
7242 if (unlikely(vmx->fail)) {
7243 vmx->fail = 0;
7244 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7245 } else
7246 nested_vmx_succeed(vcpu);
7247}
7248
7c177938
NHE
7249/*
7250 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7251 * 23.7 "VM-entry failures during or after loading guest state" (this also
7252 * lists the acceptable exit-reason and exit-qualification parameters).
7253 * It should only be called before L2 actually succeeded to run, and when
7254 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7255 */
7256static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7257 struct vmcs12 *vmcs12,
7258 u32 reason, unsigned long qualification)
7259{
7260 load_vmcs12_host_state(vcpu, vmcs12);
7261 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7262 vmcs12->exit_qualification = qualification;
7263 nested_vmx_succeed(vcpu);
7264}
7265
8a76d7f2
JR
7266static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7267 struct x86_instruction_info *info,
7268 enum x86_intercept_stage stage)
7269{
7270 return X86EMUL_CONTINUE;
7271}
7272
cbdd1bea 7273static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK
7274 .cpu_has_kvm_support = cpu_has_kvm_support,
7275 .disabled_by_bios = vmx_disabled_by_bios,
7276 .hardware_setup = hardware_setup,
7277 .hardware_unsetup = hardware_unsetup,
002c7f7c 7278 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK
7279 .hardware_enable = hardware_enable,
7280 .hardware_disable = hardware_disable,
04547156 7281 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK
7282
7283 .vcpu_create = vmx_create_vcpu,
7284 .vcpu_free = vmx_free_vcpu,
04d2cc77 7285 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7286
04d2cc77 7287 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK
7288 .vcpu_load = vmx_vcpu_load,
7289 .vcpu_put = vmx_vcpu_put,
7290
c8639010 7291 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK
7292 .get_msr = vmx_get_msr,
7293 .set_msr = vmx_set_msr,
7294 .get_segment_base = vmx_get_segment_base,
7295 .get_segment = vmx_get_segment,
7296 .set_segment = vmx_set_segment,
2e4d2653 7297 .get_cpl = vmx_get_cpl,
6aa8b732 7298 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7299 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7300 .decache_cr3 = vmx_decache_cr3,
25c4c276 7301 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7302 .set_cr0 = vmx_set_cr0,
6aa8b732
AK
7303 .set_cr3 = vmx_set_cr3,
7304 .set_cr4 = vmx_set_cr4,
6aa8b732 7305 .set_efer = vmx_set_efer,
6aa8b732
AK
7306 .get_idt = vmx_get_idt,
7307 .set_idt = vmx_set_idt,
7308 .get_gdt = vmx_get_gdt,
7309 .set_gdt = vmx_set_gdt,
020df079 7310 .set_dr7 = vmx_set_dr7,
5fdbf976 7311 .cache_reg = vmx_cache_reg,
6aa8b732
AK
7312 .get_rflags = vmx_get_rflags,
7313 .set_rflags = vmx_set_rflags,
ebcbab4c 7314 .fpu_activate = vmx_fpu_activate,
02daab21 7315 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK
7316
7317 .tlb_flush = vmx_flush_tlb,
6aa8b732 7318
6aa8b732 7319 .run = vmx_vcpu_run,
6062d012 7320 .handle_exit = vmx_handle_exit,
6aa8b732 7321 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC
7322 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7323 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7324 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7325 .set_irq = vmx_inject_irq,
95ba8273 7326 .set_nmi = vmx_inject_nmi,
298101da 7327 .queue_exception = vmx_queue_exception,
b463a6f7 7328 .cancel_injection = vmx_cancel_injection,
78646121 7329 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7330 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK
7331 .get_nmi_mask = vmx_get_nmi_mask,
7332 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN
7333 .enable_nmi_window = enable_nmi_window,
7334 .enable_irq_window = enable_irq_window,
7335 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7336
cbc94022 7337 .set_tss_addr = vmx_set_tss_addr,
67253af5 7338 .get_tdp_level = get_ept_level,
4b12f0de 7339 .get_mt_mask = vmx_get_mt_mask,
229456fc 7340
586f9607 7341 .get_exit_info = vmx_get_exit_info,
586f9607 7342
17cc3935 7343 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY
7344
7345 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY
7346
7347 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7348 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR
7349
7350 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY
7351
7352 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7353
4051b188 7354 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7355 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7356 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7357 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7358 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7359 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR
7360
7361 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR
7362
7363 .check_intercept = vmx_check_intercept,
6aa8b732
AK
7364};
7365
7366static int __init vmx_init(void)
7367{
26bb0981
AK
7368 int r, i;
7369
7370 rdmsrl_safe(MSR_EFER, &host_efer);
7371
7372 for (i = 0; i < NR_VMX_MSR; ++i)
7373 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7374
3e7c73e9 7375 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ
7376 if (!vmx_io_bitmap_a)
7377 return -ENOMEM;
7378
2106a548
GC
7379 r = -ENOMEM;
7380
3e7c73e9 7381 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7382 if (!vmx_io_bitmap_b)
fdef3ad1 7383 goto out;
fdef3ad1 7384
5897297b 7385 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7386 if (!vmx_msr_bitmap_legacy)
25c5f225 7387 goto out1;
2106a548 7388
25c5f225 7389
5897297b 7390 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7391 if (!vmx_msr_bitmap_longmode)
5897297b 7392 goto out2;
2106a548 7393
5897297b 7394
fdef3ad1
HQ
7395 /*
7396 * Allow direct access to the PC debug port (it is often used for I/O
7397 * delays, but the vmexits simply slow things down).
7398 */
3e7c73e9
AK
7399 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7400 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7401
3e7c73e9 7402 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7403
5897297b
AK
7404 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7405 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7406
2384d2b3
SY
7407 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7408
0ee75bea
AK
7409 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7410 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7411 if (r)
5897297b 7412 goto out3;
25c5f225 7413
8f536b76
ZY
7414#ifdef CONFIG_KEXEC
7415 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7416 crash_vmclear_local_loaded_vmcss);
7417#endif
7418
5897297b
AK
7419 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7420 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7421 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7422 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7423 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7424 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7425
089d034e 7426 if (enable_ept) {
3f6d8c8a
XH
7427 kvm_mmu_set_mask_ptes(0ull,
7428 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7429 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7430 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7431 ept_set_mmio_spte_mask();
5fdbcb9d
SY
7432 kvm_enable_tdp();
7433 } else
7434 kvm_disable_tdp();
1439442c 7435
fdef3ad1
HQ
7436 return 0;
7437
5897297b
AK
7438out3:
7439 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7440out2:
5897297b 7441 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7442out1:
3e7c73e9 7443 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7444out:
3e7c73e9 7445 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7446 return r;
6aa8b732
AK
7447}
7448
7449static void __exit vmx_exit(void)
7450{
5897297b
AK
7451 free_page((unsigned long)vmx_msr_bitmap_legacy);
7452 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK
7453 free_page((unsigned long)vmx_io_bitmap_b);
7454 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7455
8f536b76
ZY
7456#ifdef CONFIG_KEXEC
7457 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7458 synchronize_rcu();
7459#endif
7460
cb498ea2 7461 kvm_exit();
6aa8b732
AK
7462}
7463
7464module_init(vmx_init)
7465module_exit(vmx_exit)