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kvm/x86: Hyper-V HV_X64_MSR_VP_INDEX export for QEMU.
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 154 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 162 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 163 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 171 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 173 { "largepages", VM_STAT(lpages) },
417bc304
HB		 174 { NULL }
175};
176
2acf923e
DC		 177u64 __read_mostly host_xcr0;
178
b6785def 179static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 180
af585b92
GN		 181static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182{
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186}
187
18863bdd
AK		 188static void kvm_on_user_return(struct user_return_notifier *urn)
189{
190 unsigned slot;
18863bdd
AK		 191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 193 struct kvm_shared_msr_values *values;
18863bdd
AK		 194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
18863bdd
AK		 200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204}
205
2bf78fa7 206static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 207{
18863bdd 208 u64 value;
013f6a5d
MT		 209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 211
2bf78fa7
SY		 212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221}
222
223void kvm_define_shared_msr(unsigned slot, u32 msr)
224{
0123be42 225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 226 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 229}
230EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232static void kvm_shared_msr_cpu_online(void)
233{
234 unsigned i;
18863bdd
AK		 235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 237 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 238}
239
8b3c3104 240int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 241{
013f6a5d
MT		 242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 244 int err;
18863bdd 245
2bf78fa7 246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 247 return 0;
2bf78fa7 248 smsr->values[slot].curr = value;
8b3c3104
AH		 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
18863bdd
AK		 253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
8b3c3104 258 return 0;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
13a34e06 262static void drop_user_return_notifiers(void)
3548bab5 263{
013f6a5d
MT		 264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269}
270
6866b83e
CO		 271u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272{
8a5a87d9 273 return vcpu->arch.apic_base;
6866b83e
CO		 274}
275EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
58cb628d
JK		 277int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278{
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
6866b83e
CO		 297}
298EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
2605fc21 300asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 301{
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304}
305EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
3fd28fce
ED		 307#define EXCPT_BENIGN 0
308#define EXCPT_CONTRIBUTORY 1
309#define EXCPT_PF 2
310
311static int exception_class(int vector)
312{
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326}
327
d6e8c854
NA		 328#define EXCPT_FAULT 0
329#define EXCPT_TRAP 1
330#define EXCPT_ABORT 2
331#define EXCPT_INTERRUPT 3
332
333static int exception_type(int vector)
334{
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351}
352
3fd28fce 353static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
3fd28fce
ED		 356{
357 u32 prev_nr;
358 int class1, class2;
359
3842d135
AK		 360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
3fd28fce
ED		 362 if (!vcpu->arch.exception.pending) {
363 queue:
3ffb2468
NA		 364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
3fd28fce
ED		 366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
3f0fd292 370 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
a8eeb04a 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395}
396
298101da
AK		 397void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
ce7ddec4
JR		 403void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404{
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
db8fcefa 409void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 410{
db8fcefa
AP		 411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415}
416EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 417
6389ee94 418void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 419{
420 ++vcpu->stat.pf_guest;
6389ee94
AK		 421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 423}
27d6c865 424EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 425
ef54bcfe 426static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 427{
6389ee94
AK		 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 430 else
6389ee94 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 432
433 return fault->nested_page_fault;
d4f8cf66
JR		 434}
435
3419ffc8
SY		 436void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437{
7460fb4a
AK		 438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 440}
441EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
298101da
AK		 443void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444{
ce7ddec4 445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 446}
447EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
ce7ddec4
JR		 449void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450{
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452}
453EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
0a79b009
AK		 455/*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 460{
0a79b009
AK		 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
298101da 465}
0a79b009 466EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 467
16f8a6f9
NA		 468bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469{
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475}
476EXPORT_SYMBOL_GPL(kvm_require_dr);
477
ec92fe44
JR		 478/*
479 * This function will be used to read from the physical memory of the currently
54bf36aa 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 481 * can read from guest physical or from the guest's guest physical memory.
482 */
483int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486{
54987b7a 487 struct x86_exception exception;
ec92fe44
JR		 488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
54987b7a 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
54bf36aa 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 499}
500EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
69b0049a 502static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 503 void *data, int offset, int len, u32 access)
504{
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507}
508
a03490ed
CO		 509/*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
ff03a073 512int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 513{
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
ff03a073 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 519
ff03a073
JR		 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 528 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
0f12244f
GN		 628 return 0;
629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 631
2d3ad1f4 632void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 633{
49a9b07e 634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 637
42bdf991
MT		 638static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639{
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646}
647
648static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655}
656
69b0049a 657static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 658{
56c103ec
LJ		 659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 661 u64 valid_bits;
2acf923e
DC		 662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
2acf923e
DC		 666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
46c34cb0
PB		 670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
2acf923e 678 return 1;
46c34cb0 679
390bd528
LJ		 680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
612263b3
CP		 683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
42bdf991 689 kvm_put_guest_xcr0(vcpu);
2acf923e 690 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
2acf923e
DC		 694 return 0;
695}
696
697int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698{
764bcbc5
Z		 699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705}
706EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
a83b29c6 708int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 709{
fc78f519 710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
0f12244f
GN		 714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
a03490ed 716
2acf923e
DC		 717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
c68b734f
YW		 720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
97ec8c06
FW		 723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
afcbf13f 726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 727 return 1;
728
a03490ed 729 if (is_long_mode(vcpu)) {
0f12244f
GN		 730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
a2edf57f
AK		 732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
0f12244f
GN		 736 return 1;
737
ad756a16
MJ		 738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
5e1746d6 747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 748 return 1;
a03490ed 749
ad756a16
MJ		 750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 752 kvm_mmu_reset_context(vcpu);
0f12244f 753
2acf923e 754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 755 kvm_update_cpuid(vcpu);
2acf923e 756
0f12244f
GN		 757 return 0;
758}
2d3ad1f4 759EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 760
2390218b 761int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 762{
ac146235 763#ifdef CONFIG_X86_64
9d88fca7 764 cr3 &= ~CR3_PCID_INVD;
ac146235 765#endif
9d88fca7 766
9f8fe504 767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 768 kvm_mmu_sync_roots(vcpu);
77c3913b 769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 770 return 0;
d835dfec
AK		 771 }
772
a03490ed 773 if (is_long_mode(vcpu)) {
d9f89b88
JK		 774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 778 return 1;
a03490ed 779
0f12244f 780 vcpu->arch.cr3 = cr3;
aff48baa 781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 782 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 783 return 0;
784}
2d3ad1f4 785EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 786
eea1cff9 787int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 788{
0f12244f
GN		 789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
35754c98 791 if (lapic_in_kernel(vcpu))
a03490ed
CO		 792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
ad312c7c 794 vcpu->arch.cr8 = cr8;
0f12244f
GN		 795 return 0;
796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 798
2d3ad1f4 799unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 800{
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 return kvm_lapic_get_cr8(vcpu);
803 else
ad312c7c 804 return vcpu->arch.cr8;
a03490ed 805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 807
ae561ede
NA		 808static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809{
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817}
818
73aaf249
JK		 819static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820{
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823}
824
c8639010
JK		 825static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826{
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 837}
838
6f43ed01
NA		 839static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840{
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846}
847
338dbc97 848static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 849{
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
020df079
GN		 857 /* fall through */
858 case 6:
338dbc97
GN		 859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
6f43ed01 861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 862 kvm_update_dr6(vcpu);
020df079
GN		 863 break;
864 case 5:
020df079
GN		 865 /* fall through */
866 default: /* 7 */
338dbc97
GN		 867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
020df079 869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 870 kvm_update_dr7(vcpu);
020df079
GN		 871 break;
872 }
873
874 return 0;
875}
338dbc97
GN		 876
877int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878{
16f8a6f9 879 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 880 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 881 return 1;
882 }
883 return 0;
338dbc97 884}
020df079
GN		 885EXPORT_SYMBOL_GPL(kvm_set_dr);
886
16f8a6f9 887int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 888{
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
020df079
GN		 894 /* fall through */
895 case 6:
73aaf249
JK		 896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 900 break;
901 case 5:
020df079
GN		 902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
338dbc97
GN		 907 return 0;
908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_get_dr);
910
022cd0e8
AK		 911bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912{
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
c6702c9d 917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923}
924EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
043405e1
CO		 926/*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
e3267cbb 931 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
043405e1 934 */
e3267cbb 935
043405e1
CO		 936static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 938 MSR_STAR,
043405e1
CO		 939#ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941#endif
b3897a49 942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 944};
945
946static unsigned num_msrs_to_save;
947
62ef68bb
PB		 948static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 955 HV_X64_MSR_RESET,
11c4b1ca 956 HV_X64_MSR_VP_INDEX,
62ef68bb
PB		 957 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
958 MSR_KVM_PV_EOI_EN,
959
ba904635 960 MSR_IA32_TSC_ADJUST,
a3e06bbe 961 MSR_IA32_TSCDEADLINE,
043405e1 962 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 963 MSR_IA32_MCG_STATUS,
964 MSR_IA32_MCG_CTL,
64d60670 965 MSR_IA32_SMBASE,
043405e1
CO		 966};
967
62ef68bb
PB		 968static unsigned num_emulated_msrs;
969
384bb783 970bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 971{
b69e8cae 972 if (efer & efer_reserved_bits)
384bb783 973 return false;
15c4a640 974
1b2fd70c
AG		 975 if (efer & EFER_FFXSR) {
976 struct kvm_cpuid_entry2 *feat;
977
978 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 979 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 980 return false;
1b2fd70c
AG		 981 }
982
d8017474
AG		 983 if (efer & EFER_SVME) {
984 struct kvm_cpuid_entry2 *feat;
985
986 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 987 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 988 return false;
d8017474
AG		 989 }
990
384bb783
JK		 991 return true;
992}
993EXPORT_SYMBOL_GPL(kvm_valid_efer);
994
995static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
996{
997 u64 old_efer = vcpu->arch.efer;
998
999 if (!kvm_valid_efer(vcpu, efer))
1000 return 1;
1001
1002 if (is_paging(vcpu)
1003 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1004 return 1;
1005
15c4a640 1006 efer &= ~EFER_LMA;
f6801dff 1007 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1008
a3d204e2
SY		 1009 kvm_x86_ops->set_efer(vcpu, efer);
1010
aad82703
SY		 1011 /* Update reserved bits */
1012 if ((efer ^ old_efer) & EFER_NX)
1013 kvm_mmu_reset_context(vcpu);
1014
b69e8cae 1015 return 0;
15c4a640
CO		 1016}
1017
f2b4b7dd
JR		 1018void kvm_enable_efer_bits(u64 mask)
1019{
1020 efer_reserved_bits &= ~mask;
1021}
1022EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1023
15c4a640
CO		 1024/*
1025 * Writes msr value into into the appropriate "register".
1026 * Returns 0 on success, non-0 otherwise.
1027 * Assumes vcpu_load() was already called.
1028 */
8fe8ab46 1029int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1030{
854e8bb1
NA		 1031 switch (msr->index) {
1032 case MSR_FS_BASE:
1033 case MSR_GS_BASE:
1034 case MSR_KERNEL_GS_BASE:
1035 case MSR_CSTAR:
1036 case MSR_LSTAR:
1037 if (is_noncanonical_address(msr->data))
1038 return 1;
1039 break;
1040 case MSR_IA32_SYSENTER_EIP:
1041 case MSR_IA32_SYSENTER_ESP:
1042 /*
1043 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1044 * non-canonical address is written on Intel but not on
1045 * AMD (which ignores the top 32-bits, because it does
1046 * not implement 64-bit SYSENTER).
1047 *
1048 * 64-bit code should hence be able to write a non-canonical
1049 * value on AMD. Making the address canonical ensures that
1050 * vmentry does not fail on Intel after writing a non-canonical
1051 * value, and that something deterministic happens if the guest
1052 * invokes 64-bit SYSENTER.
1053 */
1054 msr->data = get_canonical(msr->data);
1055 }
8fe8ab46 1056 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1057}
854e8bb1 1058EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1059
313a3dc7
CO		 1060/*
1061 * Adapt set_msr() to msr_io()'s calling convention
1062 */
609e36d3
PB		 1063static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1064{
1065 struct msr_data msr;
1066 int r;
1067
1068 msr.index = index;
1069 msr.host_initiated = true;
1070 r = kvm_get_msr(vcpu, &msr);
1071 if (r)
1072 return r;
1073
1074 *data = msr.data;
1075 return 0;
1076}
1077
313a3dc7
CO		 1078static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1079{
8fe8ab46
WA		 1080 struct msr_data msr;
1081
1082 msr.data = *data;
1083 msr.index = index;
1084 msr.host_initiated = true;
1085 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1086}
1087
16e8d74d
MT		 1088#ifdef CONFIG_X86_64
1089struct pvclock_gtod_data {
1090 seqcount_t seq;
1091
1092 struct { /* extract of a clocksource struct */
1093 int vclock_mode;
1094 cycle_t cycle_last;
1095 cycle_t mask;
1096 u32 mult;
1097 u32 shift;
1098 } clock;
1099
cbcf2dd3
TG		 1100 u64 boot_ns;
1101 u64 nsec_base;
16e8d74d
MT		 1102};
1103
1104static struct pvclock_gtod_data pvclock_gtod_data;
1105
1106static void update_pvclock_gtod(struct timekeeper *tk)
1107{
1108 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1109 u64 boot_ns;
1110
876e7881 1111 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1112
1113 write_seqcount_begin(&vdata->seq);
1114
1115 /* copy pvclock gtod data */
876e7881
PZ		 1116 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1117 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1118 vdata->clock.mask = tk->tkr_mono.mask;
1119 vdata->clock.mult = tk->tkr_mono.mult;
1120 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1121
cbcf2dd3 1122 vdata->boot_ns = boot_ns;
876e7881 1123 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1124
1125 write_seqcount_end(&vdata->seq);
1126}
1127#endif
1128
bab5bb39
NK		 1129void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1130{
1131 /*
1132 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1133 * vcpu_enter_guest. This function is only called from
1134 * the physical CPU that is running vcpu.
1135 */
1136 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1137}
16e8d74d 1138
18068523
GOC		 1139static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1140{
9ed3c444
AK		 1141 int version;
1142 int r;
50d0a0f9 1143 struct pvclock_wall_clock wc;
923de3cf 1144 struct timespec boot;
18068523
GOC		 1145
1146 if (!wall_clock)
1147 return;
1148
9ed3c444
AK		 1149 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1150 if (r)
1151 return;
1152
1153 if (version & 1)
1154 ++version; /* first time write, random junk */
1155
1156 ++version;
18068523 1157
18068523
GOC		 1158 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1159
50d0a0f9
GH		 1160 /*
1161 * The guest calculates current wall clock time by adding
34c238a1 1162 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1163 * wall clock specified here. guest system time equals host
1164 * system time for us, thus we must fill in host boot time here.
1165 */
923de3cf 1166 getboottime(&boot);
50d0a0f9 1167
4b648665
BR		 1168 if (kvm->arch.kvmclock_offset) {
1169 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1170 boot = timespec_sub(boot, ts);
1171 }
50d0a0f9
GH		 1172 wc.sec = boot.tv_sec;
1173 wc.nsec = boot.tv_nsec;
1174 wc.version = version;
18068523
GOC		 1175
1176 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1177
1178 version++;
1179 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1180}
1181
50d0a0f9
GH		 1182static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1183{
1184 uint32_t quotient, remainder;
1185
1186 /* Don't try to replace with do_div(), this one calculates
1187 * "(dividend << 32) / divisor" */
1188 __asm__ ( "divl %4"
1189 : "=a" (quotient), "=d" (remainder)
1190 : "0" (0), "1" (dividend), "r" (divisor) );
1191 return quotient;
1192}
1193
5f4e3f88
ZA		 1194static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1195 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1196{
5f4e3f88 1197 uint64_t scaled64;
50d0a0f9
GH		 1198 int32_t shift = 0;
1199 uint64_t tps64;
1200 uint32_t tps32;
1201
5f4e3f88
ZA		 1202 tps64 = base_khz * 1000LL;
1203 scaled64 = scaled_khz * 1000LL;
50933623 1204 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1205 tps64 >>= 1;
1206 shift--;
1207 }
1208
1209 tps32 = (uint32_t)tps64;
50933623
JK		 1210 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1211 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1212 scaled64 >>= 1;
1213 else
1214 tps32 <<= 1;
50d0a0f9
GH		 1215 shift++;
1216 }
1217
5f4e3f88
ZA		 1218 *pshift = shift;
1219 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1220
5f4e3f88
ZA		 1221 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1222 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1223}
1224
d828199e 1225#ifdef CONFIG_X86_64
16e8d74d 1226static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1227#endif
16e8d74d 1228
c8076604 1229static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1230static unsigned long max_tsc_khz;
c8076604 1231
cc578287 1232static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1233{
cc578287
ZA		 1234 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1235 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1236}
1237
cc578287 1238static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1239{
cc578287
ZA		 1240 u64 v = (u64)khz * (1000000 + ppm);
1241 do_div(v, 1000000);
1242 return v;
1e993611
JR		 1243}
1244
cc578287 1245static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1246{
cc578287
ZA		 1247 u32 thresh_lo, thresh_hi;
1248 int use_scaling = 0;
217fc9cf 1249
03ba32ca
MT		 1250 /* tsc_khz can be zero if TSC calibration fails */
1251 if (this_tsc_khz == 0)
1252 return;
1253
c285545f
ZA		 1254 /* Compute a scale to convert nanoseconds in TSC cycles */
1255 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1256 &vcpu->arch.virtual_tsc_shift,
1257 &vcpu->arch.virtual_tsc_mult);
1258 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1259
1260 /*
1261 * Compute the variation in TSC rate which is acceptable
1262 * within the range of tolerance and decide if the
1263 * rate being applied is within that bounds of the hardware
1264 * rate. If so, no scaling or compensation need be done.
1265 */
1266 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1267 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1268 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1269 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1270 use_scaling = 1;
1271 }
1272 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1273}
1274
1275static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1276{
e26101b1 1277 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1278 vcpu->arch.virtual_tsc_mult,
1279 vcpu->arch.virtual_tsc_shift);
e26101b1 1280 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1281 return tsc;
1282}
1283
69b0049a 1284static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1285{
1286#ifdef CONFIG_X86_64
1287 bool vcpus_matched;
b48aa97e
MT		 1288 struct kvm_arch *ka = &vcpu->kvm->arch;
1289 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1290
1291 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1292 atomic_read(&vcpu->kvm->online_vcpus));
1293
7f187922
MT		 1294 /*
1295 * Once the masterclock is enabled, always perform request in
1296 * order to update it.
1297 *
1298 * In order to enable masterclock, the host clocksource must be TSC
1299 * and the vcpus need to have matched TSCs. When that happens,
1300 * perform request to enable masterclock.
1301 */
1302 if (ka->use_master_clock ||
1303 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1304 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1305
1306 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1307 atomic_read(&vcpu->kvm->online_vcpus),
1308 ka->use_master_clock, gtod->clock.vclock_mode);
1309#endif
1310}
1311
ba904635
WA		 1312static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1313{
1314 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1315 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1316}
1317
8fe8ab46 1318void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1319{
1320 struct kvm *kvm = vcpu->kvm;
f38e098f 1321 u64 offset, ns, elapsed;
99e3e30a 1322 unsigned long flags;
02626b6a 1323 s64 usdiff;
b48aa97e 1324 bool matched;
0d3da0d2 1325 bool already_matched;
8fe8ab46 1326 u64 data = msr->data;
99e3e30a 1327
038f8c11 1328 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1329 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1330 ns = get_kernel_ns();
f38e098f 1331 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1332
03ba32ca 1333 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1334 int faulted = 0;
1335
03ba32ca
MT		 1336 /* n.b - signed multiplication and division required */
1337 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1338#ifdef CONFIG_X86_64
03ba32ca 1339 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1340#else
03ba32ca 1341 /* do_div() only does unsigned */
8915aa27
MT		 1342 asm("1: idivl %[divisor]\n"
1343 "2: xor %%edx, %%edx\n"
1344 " movl $0, %[faulted]\n"
1345 "3:\n"
1346 ".section .fixup,\"ax\"\n"
1347 "4: movl $1, %[faulted]\n"
1348 " jmp 3b\n"
1349 ".previous\n"
1350
1351 _ASM_EXTABLE(1b, 4b)
1352
1353 : "=A"(usdiff), [faulted] "=r" (faulted)
1354 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1355
5d3cb0f6 1356#endif
03ba32ca
MT		 1357 do_div(elapsed, 1000);
1358 usdiff -= elapsed;
1359 if (usdiff < 0)
1360 usdiff = -usdiff;
8915aa27
MT		 1361
1362 /* idivl overflow => difference is larger than USEC_PER_SEC */
1363 if (faulted)
1364 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1365 } else
1366 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1367
1368 /*
5d3cb0f6
ZA		 1369 * Special case: TSC write with a small delta (1 second) of virtual
1370 * cycle time against real time is interpreted as an attempt to
1371 * synchronize the CPU.
1372 *
1373 * For a reliable TSC, we can match TSC offsets, and for an unstable
1374 * TSC, we add elapsed time in this computation. We could let the
1375 * compensation code attempt to catch up if we fall behind, but
1376 * it's better to try to match offsets from the beginning.
1377 */
02626b6a 1378 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1379 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1380 if (!check_tsc_unstable()) {
e26101b1 1381 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1382 pr_debug("kvm: matched tsc offset for %llu\n", data);
1383 } else {
857e4099 1384 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1385 data += delta;
1386 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1387 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1388 }
b48aa97e 1389 matched = true;
0d3da0d2 1390 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1391 } else {
1392 /*
1393 * We split periods of matched TSC writes into generations.
1394 * For each generation, we track the original measured
1395 * nanosecond time, offset, and write, so if TSCs are in
1396 * sync, we can match exact offset, and if not, we can match
4a969980 1397 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1398 *
1399 * These values are tracked in kvm->arch.cur_xxx variables.
1400 */
1401 kvm->arch.cur_tsc_generation++;
1402 kvm->arch.cur_tsc_nsec = ns;
1403 kvm->arch.cur_tsc_write = data;
1404 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1405 matched = false;
0d3da0d2 1406 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1407 kvm->arch.cur_tsc_generation, data);
f38e098f 1408 }
e26101b1
ZA		 1409
1410 /*
1411 * We also track th most recent recorded KHZ, write and time to
1412 * allow the matching interval to be extended at each write.
1413 */
f38e098f
ZA		 1414 kvm->arch.last_tsc_nsec = ns;
1415 kvm->arch.last_tsc_write = data;
5d3cb0f6 1416 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1417
b183aa58 1418 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1419
1420 /* Keep track of which generation this VCPU has synchronized to */
1421 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1422 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1423 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1424
ba904635
WA		 1425 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1426 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1427 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1428 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1429
1430 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1431 if (!matched) {
b48aa97e 1432 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1433 } else if (!already_matched) {
1434 kvm->arch.nr_vcpus_matched_tsc++;
1435 }
b48aa97e
MT		 1436
1437 kvm_track_tsc_matching(vcpu);
1438 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1439}
e26101b1 1440
99e3e30a
ZA		 1441EXPORT_SYMBOL_GPL(kvm_write_tsc);
1442
d828199e
MT		 1443#ifdef CONFIG_X86_64
1444
1445static cycle_t read_tsc(void)
1446{
03b9730b
AL		 1447 cycle_t ret = (cycle_t)rdtsc_ordered();
1448 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1449
1450 if (likely(ret >= last))
1451 return ret;
1452
1453 /*
1454 * GCC likes to generate cmov here, but this branch is extremely
1455 * predictable (it's just a funciton of time and the likely is
1456 * very likely) and there's a data dependence, so force GCC
1457 * to generate a branch instead. I don't barrier() because
1458 * we don't actually need a barrier, and if this function
1459 * ever gets inlined it will generate worse code.
1460 */
1461 asm volatile ("");
1462 return last;
1463}
1464
1465static inline u64 vgettsc(cycle_t *cycle_now)
1466{
1467 long v;
1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1469
1470 *cycle_now = read_tsc();
1471
1472 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1473 return v * gtod->clock.mult;
1474}
1475
cbcf2dd3 1476static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1477{
cbcf2dd3 1478 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1479 unsigned long seq;
d828199e 1480 int mode;
cbcf2dd3 1481 u64 ns;
d828199e 1482
d828199e
MT		 1483 do {
1484 seq = read_seqcount_begin(&gtod->seq);
1485 mode = gtod->clock.vclock_mode;
cbcf2dd3 1486 ns = gtod->nsec_base;
d828199e
MT		 1487 ns += vgettsc(cycle_now);
1488 ns >>= gtod->clock.shift;
cbcf2dd3 1489 ns += gtod->boot_ns;
d828199e 1490 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1491 *t = ns;
d828199e
MT		 1492
1493 return mode;
1494}
1495
1496/* returns true if host is using tsc clocksource */
1497static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1498{
d828199e
MT		 1499 /* checked again under seqlock below */
1500 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1501 return false;
1502
cbcf2dd3 1503 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1504}
1505#endif
1506
1507/*
1508 *
b48aa97e
MT		 1509 * Assuming a stable TSC across physical CPUS, and a stable TSC
1510 * across virtual CPUs, the following condition is possible.
1511 * Each numbered line represents an event visible to both
d828199e
MT		 1512 * CPUs at the next numbered event.
1513 *
1514 * "timespecX" represents host monotonic time. "tscX" represents
1515 * RDTSC value.
1516 *
1517 * VCPU0 on CPU0 | VCPU1 on CPU1
1518 *
1519 * 1. read timespec0,tsc0
1520 * 2. | timespec1 = timespec0 + N
1521 * | tsc1 = tsc0 + M
1522 * 3. transition to guest | transition to guest
1523 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1524 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1525 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1526 *
1527 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1528 *
1529 * - ret0 < ret1
1530 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1531 * ...
1532 * - 0 < N - M => M < N
1533 *
1534 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1535 * always the case (the difference between two distinct xtime instances
1536 * might be smaller then the difference between corresponding TSC reads,
1537 * when updating guest vcpus pvclock areas).
1538 *
1539 * To avoid that problem, do not allow visibility of distinct
1540 * system_timestamp/tsc_timestamp values simultaneously: use a master
1541 * copy of host monotonic time values. Update that master copy
1542 * in lockstep.
1543 *
b48aa97e 1544 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1545 *
1546 */
1547
1548static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1549{
1550#ifdef CONFIG_X86_64
1551 struct kvm_arch *ka = &kvm->arch;
1552 int vclock_mode;
b48aa97e
MT		 1553 bool host_tsc_clocksource, vcpus_matched;
1554
1555 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1556 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1557
1558 /*
1559 * If the host uses TSC clock, then passthrough TSC as stable
1560 * to the guest.
1561 */
b48aa97e 1562 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1563 &ka->master_kernel_ns,
1564 &ka->master_cycle_now);
1565
16a96021 1566 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1567 && !backwards_tsc_observed
1568 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1569
d828199e
MT		 1570 if (ka->use_master_clock)
1571 atomic_set(&kvm_guest_has_master_clock, 1);
1572
1573 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1574 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1575 vcpus_matched);
d828199e
MT		 1576#endif
1577}
1578
2e762ff7
MT		 1579static void kvm_gen_update_masterclock(struct kvm *kvm)
1580{
1581#ifdef CONFIG_X86_64
1582 int i;
1583 struct kvm_vcpu *vcpu;
1584 struct kvm_arch *ka = &kvm->arch;
1585
1586 spin_lock(&ka->pvclock_gtod_sync_lock);
1587 kvm_make_mclock_inprogress_request(kvm);
1588 /* no guest entries from this point */
1589 pvclock_update_vm_gtod_copy(kvm);
1590
1591 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1592 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1593
1594 /* guest entries allowed */
1595 kvm_for_each_vcpu(i, vcpu, kvm)
1596 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1597
1598 spin_unlock(&ka->pvclock_gtod_sync_lock);
1599#endif
1600}
1601
34c238a1 1602static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1603{
d828199e 1604 unsigned long flags, this_tsc_khz;
18068523 1605 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1606 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1607 s64 kernel_ns;
d828199e 1608 u64 tsc_timestamp, host_tsc;
0b79459b 1609 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1610 u8 pvclock_flags;
d828199e
MT		 1611 bool use_master_clock;
1612
1613 kernel_ns = 0;
1614 host_tsc = 0;
18068523 1615
d828199e
MT		 1616 /*
1617 * If the host uses TSC clock, then passthrough TSC as stable
1618 * to the guest.
1619 */
1620 spin_lock(&ka->pvclock_gtod_sync_lock);
1621 use_master_clock = ka->use_master_clock;
1622 if (use_master_clock) {
1623 host_tsc = ka->master_cycle_now;
1624 kernel_ns = ka->master_kernel_ns;
1625 }
1626 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1627
1628 /* Keep irq disabled to prevent changes to the clock */
1629 local_irq_save(flags);
89cbc767 1630 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1631 if (unlikely(this_tsc_khz == 0)) {
1632 local_irq_restore(flags);
1633 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1634 return 1;
1635 }
d828199e 1636 if (!use_master_clock) {
4ea1636b 1637 host_tsc = rdtsc();
d828199e
MT		 1638 kernel_ns = get_kernel_ns();
1639 }
1640
1641 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1642
c285545f
ZA		 1643 /*
1644 * We may have to catch up the TSC to match elapsed wall clock
1645 * time for two reasons, even if kvmclock is used.
1646 * 1) CPU could have been running below the maximum TSC rate
1647 * 2) Broken TSC compensation resets the base at each VCPU
1648 * entry to avoid unknown leaps of TSC even when running
1649 * again on the same CPU. This may cause apparent elapsed
1650 * time to disappear, and the guest to stand still or run
1651 * very slowly.
1652 */
1653 if (vcpu->tsc_catchup) {
1654 u64 tsc = compute_guest_tsc(v, kernel_ns);
1655 if (tsc > tsc_timestamp) {
f1e2b260 1656 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1657 tsc_timestamp = tsc;
1658 }
50d0a0f9
GH		 1659 }
1660
18068523
GOC		 1661 local_irq_restore(flags);
1662
0b79459b 1663 if (!vcpu->pv_time_enabled)
c285545f 1664 return 0;
18068523 1665
e48672fa 1666 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1667 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1668 &vcpu->hv_clock.tsc_shift,
1669 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1670 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1671 }
1672
1673 /* With all the info we got, fill in the values */
1d5f066e 1674 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1675 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1676 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1677
09a0c3f1
OH		 1678 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1679 &guest_hv_clock, sizeof(guest_hv_clock))))
1680 return 0;
1681
5dca0d91
RK		 1682 /* This VCPU is paused, but it's legal for a guest to read another
1683 * VCPU's kvmclock, so we really have to follow the specification where
1684 * it says that version is odd if data is being modified, and even after
1685 * it is consistent.
1686 *
1687 * Version field updates must be kept separate. This is because
1688 * kvm_write_guest_cached might use a "rep movs" instruction, and
1689 * writes within a string instruction are weakly ordered. So there
1690 * are three writes overall.
1691 *
1692 * As a small optimization, only write the version field in the first
1693 * and third write. The vcpu->pv_time cache is still valid, because the
1694 * version field is the first in the struct.
18068523 1695 */
5dca0d91
RK		 1696 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1697
1698 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1699 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1700 &vcpu->hv_clock,
1701 sizeof(vcpu->hv_clock.version));
1702
1703 smp_wmb();
78c0337a
MT		 1704
1705 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1706 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1707
1708 if (vcpu->pvclock_set_guest_stopped_request) {
1709 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1710 vcpu->pvclock_set_guest_stopped_request = false;
1711 }
1712
d828199e
MT		 1713 /* If the host uses TSC clocksource, then it is stable */
1714 if (use_master_clock)
1715 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1716
78c0337a
MT		 1717 vcpu->hv_clock.flags = pvclock_flags;
1718
ce1a5e60
DM		 1719 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1720
0b79459b
AH		 1721 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1722 &vcpu->hv_clock,
1723 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1724
1725 smp_wmb();
1726
1727 vcpu->hv_clock.version++;
1728 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1729 &vcpu->hv_clock,
1730 sizeof(vcpu->hv_clock.version));
8cfdc000 1731 return 0;
c8076604
GH		 1732}
1733
0061d53d
MT		 1734/*
1735 * kvmclock updates which are isolated to a given vcpu, such as
1736 * vcpu->cpu migration, should not allow system_timestamp from
1737 * the rest of the vcpus to remain static. Otherwise ntp frequency
1738 * correction applies to one vcpu's system_timestamp but not
1739 * the others.
1740 *
1741 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1742 * We need to rate-limit these requests though, as they can
1743 * considerably slow guests that have a large number of vcpus.
1744 * The time for a remote vcpu to update its kvmclock is bound
1745 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1746 */
1747
7e44e449
AJ		 1748#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1749
1750static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1751{
1752 int i;
7e44e449
AJ		 1753 struct delayed_work *dwork = to_delayed_work(work);
1754 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1755 kvmclock_update_work);
1756 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1757 struct kvm_vcpu *vcpu;
1758
1759 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1760 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1761 kvm_vcpu_kick(vcpu);
1762 }
1763}
1764
7e44e449
AJ		 1765static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1766{
1767 struct kvm *kvm = v->kvm;
1768
105b21bb 1769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1771 KVMCLOCK_UPDATE_DELAY);
1772}
1773
332967a3
AJ		 1774#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1775
1776static void kvmclock_sync_fn(struct work_struct *work)
1777{
1778 struct delayed_work *dwork = to_delayed_work(work);
1779 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1780 kvmclock_sync_work);
1781 struct kvm *kvm = container_of(ka, struct kvm, arch);
1782
630994b3
MT		 1783 if (!kvmclock_periodic_sync)
1784 return;
1785
332967a3
AJ		 1786 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1787 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1788 KVMCLOCK_SYNC_PERIOD);
1789}
1790
890ca9ae 1791static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1792{
890ca9ae
HY		 1793 u64 mcg_cap = vcpu->arch.mcg_cap;
1794 unsigned bank_num = mcg_cap & 0xff;
1795
15c4a640 1796 switch (msr) {
15c4a640 1797 case MSR_IA32_MCG_STATUS:
890ca9ae 1798 vcpu->arch.mcg_status = data;
15c4a640 1799 break;
c7ac679c 1800 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1801 if (!(mcg_cap & MCG_CTL_P))
1802 return 1;
1803 if (data != 0 && data != ~(u64)0)
1804 return -1;
1805 vcpu->arch.mcg_ctl = data;
1806 break;
1807 default:
1808 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1809 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1810 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1811 /* only 0 or all 1s can be written to IA32_MCi_CTL
1812 * some Linux kernels though clear bit 10 in bank 4 to
1813 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1814 * this to avoid an uncatched #GP in the guest
1815 */
890ca9ae 1816 if ((offset & 0x3) == 0 &&
114be429 1817 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1818 return -1;
1819 vcpu->arch.mce_banks[offset] = data;
1820 break;
1821 }
1822 return 1;
1823 }
1824 return 0;
1825}
1826
ffde22ac
ES		 1827static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1828{
1829 struct kvm *kvm = vcpu->kvm;
1830 int lm = is_long_mode(vcpu);
1831 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1832 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1833 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1834 : kvm->arch.xen_hvm_config.blob_size_32;
1835 u32 page_num = data & ~PAGE_MASK;
1836 u64 page_addr = data & PAGE_MASK;
1837 u8 *page;
1838 int r;
1839
1840 r = -E2BIG;
1841 if (page_num >= blob_size)
1842 goto out;
1843 r = -ENOMEM;
ff5c2c03
SL		 1844 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1845 if (IS_ERR(page)) {
1846 r = PTR_ERR(page);
ffde22ac 1847 goto out;
ff5c2c03 1848 }
54bf36aa 1849 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1850 goto out_free;
1851 r = 0;
1852out_free:
1853 kfree(page);
1854out:
1855 return r;
1856}
1857
344d9588
GN		 1858static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1859{
1860 gpa_t gpa = data & ~0x3f;
1861
4a969980 1862 /* Bits 2:5 are reserved, Should be zero */
6adba527 1863 if (data & 0x3c)
344d9588
GN		 1864 return 1;
1865
1866 vcpu->arch.apf.msr_val = data;
1867
1868 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1869 kvm_clear_async_pf_completion_queue(vcpu);
1870 kvm_async_pf_hash_reset(vcpu);
1871 return 0;
1872 }
1873
8f964525
AH		 1874 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1875 sizeof(u32)))
344d9588
GN		 1876 return 1;
1877
6adba527 1878 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1879 kvm_async_pf_wakeup_all(vcpu);
1880 return 0;
1881}
1882
12f9a48f
GC		 1883static void kvmclock_reset(struct kvm_vcpu *vcpu)
1884{
0b79459b 1885 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1886}
1887
c9aaa895
GC		 1888static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1889{
1890 u64 delta;
1891
1892 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1893 return;
1894
1895 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1896 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1897 vcpu->arch.st.accum_steal = delta;
1898}
1899
1900static void record_steal_time(struct kvm_vcpu *vcpu)
1901{
1902 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1903 return;
1904
1905 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1906 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1907 return;
1908
1909 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1910 vcpu->arch.st.steal.version += 2;
1911 vcpu->arch.st.accum_steal = 0;
1912
1913 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1914 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1915}
1916
8fe8ab46 1917int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1918{
5753785f 1919 bool pr = false;
8fe8ab46
WA		 1920 u32 msr = msr_info->index;
1921 u64 data = msr_info->data;
5753785f 1922
15c4a640 1923 switch (msr) {
2e32b719
BP		 1924 case MSR_AMD64_NB_CFG:
1925 case MSR_IA32_UCODE_REV:
1926 case MSR_IA32_UCODE_WRITE:
1927 case MSR_VM_HSAVE_PA:
1928 case MSR_AMD64_PATCH_LOADER:
1929 case MSR_AMD64_BU_CFG2:
1930 break;
1931
15c4a640 1932 case MSR_EFER:
b69e8cae 1933 return set_efer(vcpu, data);
8f1589d9
AP		 1934 case MSR_K7_HWCR:
1935 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1936 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1937 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1938 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1939 if (data != 0) {
a737f256
CD		 1940 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1941 data);
8f1589d9
AP		 1942 return 1;
1943 }
15c4a640 1944 break;
f7c6d140
AP		 1945 case MSR_FAM10H_MMIO_CONF_BASE:
1946 if (data != 0) {
a737f256
CD		 1947 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1948 "0x%llx\n", data);
f7c6d140
AP		 1949 return 1;
1950 }
15c4a640 1951 break;
b5e2fec0
AG		 1952 case MSR_IA32_DEBUGCTLMSR:
1953 if (!data) {
1954 /* We support the non-activated case already */
1955 break;
1956 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1957 /* Values other than LBR and BTF are vendor-specific,
1958 thus reserved and should throw a #GP */
1959 return 1;
1960 }
a737f256
CD		 1961 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1962 __func__, data);
b5e2fec0 1963 break;
9ba075a6 1964 case 0x200 ... 0x2ff:
ff53604b 1965 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1966 case MSR_IA32_APICBASE:
58cb628d 1967 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1968 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1969 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1970 case MSR_IA32_TSCDEADLINE:
1971 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1972 break;
ba904635
WA		 1973 case MSR_IA32_TSC_ADJUST:
1974 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1975 if (!msr_info->host_initiated) {
d913b904 1976 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 1977 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 1978 }
1979 vcpu->arch.ia32_tsc_adjust_msr = data;
1980 }
1981 break;
15c4a640 1982 case MSR_IA32_MISC_ENABLE:
ad312c7c 1983 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1984 break;
64d60670
PB		 1985 case MSR_IA32_SMBASE:
1986 if (!msr_info->host_initiated)
1987 return 1;
1988 vcpu->arch.smbase = data;
1989 break;
11c6bffa 1990 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1991 case MSR_KVM_WALL_CLOCK:
1992 vcpu->kvm->arch.wall_clock = data;
1993 kvm_write_wall_clock(vcpu->kvm, data);
1994 break;
11c6bffa 1995 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1996 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1997 u64 gpa_offset;
54750f2c
MT		 1998 struct kvm_arch *ka = &vcpu->kvm->arch;
1999
12f9a48f 2000 kvmclock_reset(vcpu);
18068523 2001
54750f2c
MT		 2002 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2003 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2004
2005 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2006 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2007 &vcpu->requests);
2008
2009 ka->boot_vcpu_runs_old_kvmclock = tmp;
2010 }
2011
18068523 2012 vcpu->arch.time = data;
0061d53d 2013 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2014
2015 /* we verify if the enable bit is set... */
2016 if (!(data & 1))
2017 break;
2018
0b79459b 2019 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2020
0b79459b 2021 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2022 &vcpu->arch.pv_time, data & ~1ULL,
2023 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2024 vcpu->arch.pv_time_enabled = false;
2025 else
2026 vcpu->arch.pv_time_enabled = true;
32cad84f 2027
18068523
GOC		 2028 break;
2029 }
344d9588
GN		 2030 case MSR_KVM_ASYNC_PF_EN:
2031 if (kvm_pv_enable_async_pf(vcpu, data))
2032 return 1;
2033 break;
c9aaa895
GC		 2034 case MSR_KVM_STEAL_TIME:
2035
2036 if (unlikely(!sched_info_on()))
2037 return 1;
2038
2039 if (data & KVM_STEAL_RESERVED_MASK)
2040 return 1;
2041
2042 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2043 data & KVM_STEAL_VALID_BITS,
2044 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2045 return 1;
2046
2047 vcpu->arch.st.msr_val = data;
2048
2049 if (!(data & KVM_MSR_ENABLED))
2050 break;
2051
2052 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2053
2054 preempt_disable();
2055 accumulate_steal_time(vcpu);
2056 preempt_enable();
2057
2058 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2059
2060 break;
ae7a2a3f
MT		 2061 case MSR_KVM_PV_EOI_EN:
2062 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2063 return 1;
2064 break;
c9aaa895 2065
890ca9ae
HY		 2066 case MSR_IA32_MCG_CTL:
2067 case MSR_IA32_MCG_STATUS:
81760dcc 2068 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2069 return set_msr_mce(vcpu, msr, data);
71db6023 2070
6912ac32
WH		 2071 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2072 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2073 pr = true; /* fall through */
2074 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2075 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2076 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2077 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2078
2079 if (pr || data != 0)
a737f256
CD		 2080 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2081 "0x%x data 0x%llx\n", msr, data);
5753785f 2082 break;
84e0cefa
JS		 2083 case MSR_K7_CLK_CTL:
2084 /*
2085 * Ignore all writes to this no longer documented MSR.
2086 * Writes are only relevant for old K7 processors,
2087 * all pre-dating SVM, but a recommended workaround from
4a969980 2088 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2089 * affected processor models on the command line, hence
2090 * the need to ignore the workaround.
2091 */
2092 break;
55cd8e5a 2093 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2094 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2095 case HV_X64_MSR_CRASH_CTL:
2096 return kvm_hv_set_msr_common(vcpu, msr, data,
2097 msr_info->host_initiated);
91c9c3ed 2098 case MSR_IA32_BBL_CR_CTL3:
2099 /* Drop writes to this legacy MSR -- see rdmsr
2100 * counterpart for further detail.
2101 */
a737f256 2102 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2103 break;
2b036c6b
BO		 2104 case MSR_AMD64_OSVW_ID_LENGTH:
2105 if (!guest_cpuid_has_osvw(vcpu))
2106 return 1;
2107 vcpu->arch.osvw.length = data;
2108 break;
2109 case MSR_AMD64_OSVW_STATUS:
2110 if (!guest_cpuid_has_osvw(vcpu))
2111 return 1;
2112 vcpu->arch.osvw.status = data;
2113 break;
15c4a640 2114 default:
ffde22ac
ES		 2115 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2116 return xen_hvm_config(vcpu, data);
c6702c9d 2117 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2118 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2119 if (!ignore_msrs) {
a737f256
CD		 2120 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2121 msr, data);
ed85c068
AP		 2122 return 1;
2123 } else {
a737f256
CD		 2124 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2125 msr, data);
ed85c068
AP		 2126 break;
2127 }
15c4a640
CO		 2128 }
2129 return 0;
2130}
2131EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2132
2133
2134/*
2135 * Reads an msr value (of 'msr_index') into 'pdata'.
2136 * Returns 0 on success, non-0 otherwise.
2137 * Assumes vcpu_load() was already called.
2138 */
609e36d3 2139int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2140{
609e36d3 2141 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2142}
ff651cb6 2143EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2144
890ca9ae 2145static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2146{
2147 u64 data;
890ca9ae
HY		 2148 u64 mcg_cap = vcpu->arch.mcg_cap;
2149 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2150
2151 switch (msr) {
15c4a640
CO		 2152 case MSR_IA32_P5_MC_ADDR:
2153 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2154 data = 0;
2155 break;
15c4a640 2156 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2157 data = vcpu->arch.mcg_cap;
2158 break;
c7ac679c 2159 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2160 if (!(mcg_cap & MCG_CTL_P))
2161 return 1;
2162 data = vcpu->arch.mcg_ctl;
2163 break;
2164 case MSR_IA32_MCG_STATUS:
2165 data = vcpu->arch.mcg_status;
2166 break;
2167 default:
2168 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2169 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2170 u32 offset = msr - MSR_IA32_MC0_CTL;
2171 data = vcpu->arch.mce_banks[offset];
2172 break;
2173 }
2174 return 1;
2175 }
2176 *pdata = data;
2177 return 0;
2178}
2179
609e36d3 2180int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2181{
609e36d3 2182 switch (msr_info->index) {
890ca9ae 2183 case MSR_IA32_PLATFORM_ID:
15c4a640 2184 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2185 case MSR_IA32_DEBUGCTLMSR:
2186 case MSR_IA32_LASTBRANCHFROMIP:
2187 case MSR_IA32_LASTBRANCHTOIP:
2188 case MSR_IA32_LASTINTFROMIP:
2189 case MSR_IA32_LASTINTTOIP:
60af2ecd 2190 case MSR_K8_SYSCFG:
3afb1121
PB		 2191 case MSR_K8_TSEG_ADDR:
2192 case MSR_K8_TSEG_MASK:
60af2ecd 2193 case MSR_K7_HWCR:
61a6bd67 2194 case MSR_VM_HSAVE_PA:
1fdbd48c 2195 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2196 case MSR_AMD64_NB_CFG:
f7c6d140 2197 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2198 case MSR_AMD64_BU_CFG2:
609e36d3 2199 msr_info->data = 0;
15c4a640 2200 break;
6912ac32
WH		 2201 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2202 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2203 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2204 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2205 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2206 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2207 msr_info->data = 0;
5753785f 2208 break;
742bc670 2209 case MSR_IA32_UCODE_REV:
609e36d3 2210 msr_info->data = 0x100000000ULL;
742bc670 2211 break;
9ba075a6 2212 case MSR_MTRRcap:
9ba075a6 2213 case 0x200 ... 0x2ff:
ff53604b 2214 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2215 case 0xcd: /* fsb frequency */
609e36d3 2216 msr_info->data = 3;
15c4a640 2217 break;
7b914098
JS		 2218 /*
2219 * MSR_EBC_FREQUENCY_ID
2220 * Conservative value valid for even the basic CPU models.
2221 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2222 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2223 * and 266MHz for model 3, or 4. Set Core Clock
2224 * Frequency to System Bus Frequency Ratio to 1 (bits
2225 * 31:24) even though these are only valid for CPU
2226 * models > 2, however guests may end up dividing or
2227 * multiplying by zero otherwise.
2228 */
2229 case MSR_EBC_FREQUENCY_ID:
609e36d3 2230 msr_info->data = 1 << 24;
7b914098 2231 break;
15c4a640 2232 case MSR_IA32_APICBASE:
609e36d3 2233 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2234 break;
0105d1a5 2235 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2236 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2237 break;
a3e06bbe 2238 case MSR_IA32_TSCDEADLINE:
609e36d3 2239 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2240 break;
ba904635 2241 case MSR_IA32_TSC_ADJUST:
609e36d3 2242 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2243 break;
15c4a640 2244 case MSR_IA32_MISC_ENABLE:
609e36d3 2245 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2246 break;
64d60670
PB		 2247 case MSR_IA32_SMBASE:
2248 if (!msr_info->host_initiated)
2249 return 1;
2250 msr_info->data = vcpu->arch.smbase;
15c4a640 2251 break;
847f0ad8
AG		 2252 case MSR_IA32_PERF_STATUS:
2253 /* TSC increment by tick */
609e36d3 2254 msr_info->data = 1000ULL;
847f0ad8 2255 /* CPU multiplier */
b0996ae4 2256 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2257 break;
15c4a640 2258 case MSR_EFER:
609e36d3 2259 msr_info->data = vcpu->arch.efer;
15c4a640 2260 break;
18068523 2261 case MSR_KVM_WALL_CLOCK:
11c6bffa 2262 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2263 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2264 break;
2265 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2266 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2267 msr_info->data = vcpu->arch.time;
18068523 2268 break;
344d9588 2269 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2270 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2271 break;
c9aaa895 2272 case MSR_KVM_STEAL_TIME:
609e36d3 2273 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2274 break;
1d92128f 2275 case MSR_KVM_PV_EOI_EN:
609e36d3 2276 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2277 break;
890ca9ae
HY		 2278 case MSR_IA32_P5_MC_ADDR:
2279 case MSR_IA32_P5_MC_TYPE:
2280 case MSR_IA32_MCG_CAP:
2281 case MSR_IA32_MCG_CTL:
2282 case MSR_IA32_MCG_STATUS:
81760dcc 2283 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2284 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2285 case MSR_K7_CLK_CTL:
2286 /*
2287 * Provide expected ramp-up count for K7. All other
2288 * are set to zero, indicating minimum divisors for
2289 * every field.
2290 *
2291 * This prevents guest kernels on AMD host with CPU
2292 * type 6, model 8 and higher from exploding due to
2293 * the rdmsr failing.
2294 */
609e36d3 2295 msr_info->data = 0x20000000;
84e0cefa 2296 break;
55cd8e5a 2297 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2300 return kvm_hv_get_msr_common(vcpu,
2301 msr_info->index, &msr_info->data);
55cd8e5a 2302 break;
91c9c3ed 2303 case MSR_IA32_BBL_CR_CTL3:
2304 /* This legacy MSR exists but isn't fully documented in current
2305 * silicon. It is however accessed by winxp in very narrow
2306 * scenarios where it sets bit #19, itself documented as
2307 * a "reserved" bit. Best effort attempt to source coherent
2308 * read data here should the balance of the register be
2309 * interpreted by the guest:
2310 *
2311 * L2 cache control register 3: 64GB range, 256KB size,
2312 * enabled, latency 0x1, configured
2313 */
609e36d3 2314 msr_info->data = 0xbe702111;
91c9c3ed 2315 break;
2b036c6b
BO		 2316 case MSR_AMD64_OSVW_ID_LENGTH:
2317 if (!guest_cpuid_has_osvw(vcpu))
2318 return 1;
609e36d3 2319 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2320 break;
2321 case MSR_AMD64_OSVW_STATUS:
2322 if (!guest_cpuid_has_osvw(vcpu))
2323 return 1;
609e36d3 2324 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2325 break;
15c4a640 2326 default:
c6702c9d 2327 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2328 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2329 if (!ignore_msrs) {
609e36d3 2330 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2331 return 1;
2332 } else {
609e36d3
PB		 2333 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2334 msr_info->data = 0;
ed85c068
AP		 2335 }
2336 break;
15c4a640 2337 }
15c4a640
CO		 2338 return 0;
2339}
2340EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2341
313a3dc7
CO		 2342/*
2343 * Read or write a bunch of msrs. All parameters are kernel addresses.
2344 *
2345 * @return number of msrs set successfully.
2346 */
2347static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2348 struct kvm_msr_entry *entries,
2349 int (*do_msr)(struct kvm_vcpu *vcpu,
2350 unsigned index, u64 *data))
2351{
f656ce01 2352 int i, idx;
313a3dc7 2353
f656ce01 2354 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2355 for (i = 0; i < msrs->nmsrs; ++i)
2356 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2357 break;
f656ce01 2358 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2359
313a3dc7
CO		 2360 return i;
2361}
2362
2363/*
2364 * Read or write a bunch of msrs. Parameters are user addresses.
2365 *
2366 * @return number of msrs set successfully.
2367 */
2368static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2369 int (*do_msr)(struct kvm_vcpu *vcpu,
2370 unsigned index, u64 *data),
2371 int writeback)
2372{
2373 struct kvm_msrs msrs;
2374 struct kvm_msr_entry *entries;
2375 int r, n;
2376 unsigned size;
2377
2378 r = -EFAULT;
2379 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2380 goto out;
2381
2382 r = -E2BIG;
2383 if (msrs.nmsrs >= MAX_IO_MSRS)
2384 goto out;
2385
313a3dc7 2386 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2387 entries = memdup_user(user_msrs->entries, size);
2388 if (IS_ERR(entries)) {
2389 r = PTR_ERR(entries);
313a3dc7 2390 goto out;
ff5c2c03 2391 }
313a3dc7
CO		 2392
2393 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2394 if (r < 0)
2395 goto out_free;
2396
2397 r = -EFAULT;
2398 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2399 goto out_free;
2400
2401 r = n;
2402
2403out_free:
7a73c028 2404 kfree(entries);
313a3dc7
CO		 2405out:
2406 return r;
2407}
2408
784aa3d7 2409int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2410{
2411 int r;
2412
2413 switch (ext) {
2414 case KVM_CAP_IRQCHIP:
2415 case KVM_CAP_HLT:
2416 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2417 case KVM_CAP_SET_TSS_ADDR:
07716717 2418 case KVM_CAP_EXT_CPUID:
9c15bb1d 2419 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2420 case KVM_CAP_CLOCKSOURCE:
7837699f 2421 case KVM_CAP_PIT:
a28e4f5a 2422 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2423 case KVM_CAP_MP_STATE:
ed848624 2424 case KVM_CAP_SYNC_MMU:
a355c85c 2425 case KVM_CAP_USER_NMI:
52d939a0 2426 case KVM_CAP_REINJECT_CONTROL:
4925663a 2427 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2428 case KVM_CAP_IOEVENTFD:
f848a5a8 2429 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2430 case KVM_CAP_PIT2:
e9f42757 2431 case KVM_CAP_PIT_STATE2:
b927a3ce 2432 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2433 case KVM_CAP_XEN_HVM:
afbcf7ab 2434 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2435 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2436 case KVM_CAP_HYPERV:
10388a07 2437 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2438 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2439 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2440 case KVM_CAP_DEBUGREGS:
d2be1651 2441 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2442 case KVM_CAP_XSAVE:
344d9588 2443 case KVM_CAP_ASYNC_PF:
92a1f12d 2444 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2445 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2446 case KVM_CAP_READONLY_MEM:
5f66b620 2447 case KVM_CAP_HYPERV_TIME:
100943c5 2448 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2449 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2450 case KVM_CAP_ENABLE_CAP_VM:
2451 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2452 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2453 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2454#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2455 case KVM_CAP_ASSIGN_DEV_IRQ:
2456 case KVM_CAP_PCI_2_3:
2457#endif
018d00d2
ZX		 2458 r = 1;
2459 break;
6d396b55
PB		 2460 case KVM_CAP_X86_SMM:
2461 /* SMBASE is usually relocated above 1M on modern chipsets,
2462 * and SMM handlers might indeed rely on 4G segment limits,
2463 * so do not report SMM to be available if real mode is
2464 * emulated via vm86 mode. Still, do not go to great lengths
2465 * to avoid userspace's usage of the feature, because it is a
2466 * fringe case that is not enabled except via specific settings
2467 * of the module parameters.
2468 */
2469 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2470 break;
542472b5
LV		 2471 case KVM_CAP_COALESCED_MMIO:
2472 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2473 break;
774ead3a
AK		 2474 case KVM_CAP_VAPIC:
2475 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2476 break;
f725230a 2477 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2478 r = KVM_SOFT_MAX_VCPUS;
2479 break;
2480 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2481 r = KVM_MAX_VCPUS;
2482 break;
a988b910 2483 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2484 r = KVM_USER_MEM_SLOTS;
a988b910 2485 break;
a68a6a72
MT		 2486 case KVM_CAP_PV_MMU: /* obsolete */
2487 r = 0;
2f333bcb 2488 break;
4cee4b72 2489#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2490 case KVM_CAP_IOMMU:
a1b60c1c 2491 r = iommu_present(&pci_bus_type);
62c476c7 2492 break;
4cee4b72 2493#endif
890ca9ae
HY		 2494 case KVM_CAP_MCE:
2495 r = KVM_MAX_MCE_BANKS;
2496 break;
2d5b5a66
SY		 2497 case KVM_CAP_XCRS:
2498 r = cpu_has_xsave;
2499 break;
92a1f12d
JR		 2500 case KVM_CAP_TSC_CONTROL:
2501 r = kvm_has_tsc_control;
2502 break;
018d00d2
ZX		 2503 default:
2504 r = 0;
2505 break;
2506 }
2507 return r;
2508
2509}
2510
043405e1
CO		 2511long kvm_arch_dev_ioctl(struct file *filp,
2512 unsigned int ioctl, unsigned long arg)
2513{
2514 void __user *argp = (void __user *)arg;
2515 long r;
2516
2517 switch (ioctl) {
2518 case KVM_GET_MSR_INDEX_LIST: {
2519 struct kvm_msr_list __user *user_msr_list = argp;
2520 struct kvm_msr_list msr_list;
2521 unsigned n;
2522
2523 r = -EFAULT;
2524 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2525 goto out;
2526 n = msr_list.nmsrs;
62ef68bb 2527 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2528 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2529 goto out;
2530 r = -E2BIG;
e125e7b6 2531 if (n < msr_list.nmsrs)
043405e1
CO		 2532 goto out;
2533 r = -EFAULT;
2534 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2535 num_msrs_to_save * sizeof(u32)))
2536 goto out;
e125e7b6 2537 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2538 &emulated_msrs,
62ef68bb 2539 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2540 goto out;
2541 r = 0;
2542 break;
2543 }
9c15bb1d
BP		 2544 case KVM_GET_SUPPORTED_CPUID:
2545 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2546 struct kvm_cpuid2 __user *cpuid_arg = argp;
2547 struct kvm_cpuid2 cpuid;
2548
2549 r = -EFAULT;
2550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2551 goto out;
9c15bb1d
BP		 2552
2553 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2554 ioctl);
674eea0f
AK		 2555 if (r)
2556 goto out;
2557
2558 r = -EFAULT;
2559 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2560 goto out;
2561 r = 0;
2562 break;
2563 }
890ca9ae
HY		 2564 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2565 u64 mce_cap;
2566
2567 mce_cap = KVM_MCE_CAP_SUPPORTED;
2568 r = -EFAULT;
2569 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2570 goto out;
2571 r = 0;
2572 break;
2573 }
043405e1
CO		 2574 default:
2575 r = -EINVAL;
2576 }
2577out:
2578 return r;
2579}
2580
f5f48ee1
SY		 2581static void wbinvd_ipi(void *garbage)
2582{
2583 wbinvd();
2584}
2585
2586static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2587{
e0f0bbc5 2588 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2589}
2590
313a3dc7
CO		 2591void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2592{
f5f48ee1
SY		 2593 /* Address WBINVD may be executed by guest */
2594 if (need_emulate_wbinvd(vcpu)) {
2595 if (kvm_x86_ops->has_wbinvd_exit())
2596 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2597 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2598 smp_call_function_single(vcpu->cpu,
2599 wbinvd_ipi, NULL, 1);
2600 }
2601
313a3dc7 2602 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2603
0dd6a6ed
ZA		 2604 /* Apply any externally detected TSC adjustments (due to suspend) */
2605 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2606 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2607 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2608 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2609 }
8f6055cb 2610
48434c20 2611 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2612 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2613 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2614 if (tsc_delta < 0)
2615 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2616 if (check_tsc_unstable()) {
b183aa58
ZA		 2617 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2618 vcpu->arch.last_guest_tsc);
2619 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2620 vcpu->arch.tsc_catchup = 1;
c285545f 2621 }
d98d07ca
MT		 2622 /*
2623 * On a host with synchronized TSC, there is no need to update
2624 * kvmclock on vcpu->cpu migration
2625 */
2626 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2627 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2628 if (vcpu->cpu != cpu)
2629 kvm_migrate_timers(vcpu);
e48672fa 2630 vcpu->cpu = cpu;
6b7d7e76 2631 }
c9aaa895
GC		 2632
2633 accumulate_steal_time(vcpu);
2634 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2635}
2636
2637void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2638{
02daab21 2639 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2640 kvm_put_guest_fpu(vcpu);
4ea1636b 2641 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2642}
2643
313a3dc7
CO		 2644static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2645 struct kvm_lapic_state *s)
2646{
5a71785d 2647 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2648 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2649
2650 return 0;
2651}
2652
2653static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2654 struct kvm_lapic_state *s)
2655{
64eb0620 2656 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2657 update_cr8_intercept(vcpu);
313a3dc7
CO		 2658
2659 return 0;
2660}
2661
f77bc6a4
ZX		 2662static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2663 struct kvm_interrupt *irq)
2664{
02cdb50f 2665 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2666 return -EINVAL;
1c1a9ce9
SR		 2667
2668 if (!irqchip_in_kernel(vcpu->kvm)) {
2669 kvm_queue_interrupt(vcpu, irq->irq, false);
2670 kvm_make_request(KVM_REQ_EVENT, vcpu);
2671 return 0;
2672 }
2673
2674 /*
2675 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2676 * fail for in-kernel 8259.
2677 */
2678 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2679 return -ENXIO;
f77bc6a4 2680
1c1a9ce9
SR		 2681 if (vcpu->arch.pending_external_vector != -1)
2682 return -EEXIST;
f77bc6a4 2683
1c1a9ce9 2684 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2685 return 0;
2686}
2687
c4abb7c9
JK		 2688static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2689{
c4abb7c9 2690 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2691
2692 return 0;
2693}
2694
f077825a
PB		 2695static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2696{
64d60670
PB		 2697 kvm_make_request(KVM_REQ_SMI, vcpu);
2698
f077825a
PB		 2699 return 0;
2700}
2701
b209749f
AK		 2702static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2703 struct kvm_tpr_access_ctl *tac)
2704{
2705 if (tac->flags)
2706 return -EINVAL;
2707 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2708 return 0;
2709}
2710
890ca9ae
HY		 2711static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2712 u64 mcg_cap)
2713{
2714 int r;
2715 unsigned bank_num = mcg_cap & 0xff, bank;
2716
2717 r = -EINVAL;
a9e38c3e 2718 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2719 goto out;
2720 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2721 goto out;
2722 r = 0;
2723 vcpu->arch.mcg_cap = mcg_cap;
2724 /* Init IA32_MCG_CTL to all 1s */
2725 if (mcg_cap & MCG_CTL_P)
2726 vcpu->arch.mcg_ctl = ~(u64)0;
2727 /* Init IA32_MCi_CTL to all 1s */
2728 for (bank = 0; bank < bank_num; bank++)
2729 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2730out:
2731 return r;
2732}
2733
2734static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2735 struct kvm_x86_mce *mce)
2736{
2737 u64 mcg_cap = vcpu->arch.mcg_cap;
2738 unsigned bank_num = mcg_cap & 0xff;
2739 u64 *banks = vcpu->arch.mce_banks;
2740
2741 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2742 return -EINVAL;
2743 /*
2744 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2745 * reporting is disabled
2746 */
2747 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2748 vcpu->arch.mcg_ctl != ~(u64)0)
2749 return 0;
2750 banks += 4 * mce->bank;
2751 /*
2752 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2753 * reporting is disabled for the bank
2754 */
2755 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2756 return 0;
2757 if (mce->status & MCI_STATUS_UC) {
2758 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2759 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2760 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2761 return 0;
2762 }
2763 if (banks[1] & MCI_STATUS_VAL)
2764 mce->status |= MCI_STATUS_OVER;
2765 banks[2] = mce->addr;
2766 banks[3] = mce->misc;
2767 vcpu->arch.mcg_status = mce->mcg_status;
2768 banks[1] = mce->status;
2769 kvm_queue_exception(vcpu, MC_VECTOR);
2770 } else if (!(banks[1] & MCI_STATUS_VAL)
2771 || !(banks[1] & MCI_STATUS_UC)) {
2772 if (banks[1] & MCI_STATUS_VAL)
2773 mce->status |= MCI_STATUS_OVER;
2774 banks[2] = mce->addr;
2775 banks[3] = mce->misc;
2776 banks[1] = mce->status;
2777 } else
2778 banks[1] |= MCI_STATUS_OVER;
2779 return 0;
2780}
2781
3cfc3092
JK		 2782static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2783 struct kvm_vcpu_events *events)
2784{
7460fb4a 2785 process_nmi(vcpu);
03b82a30
JK		 2786 events->exception.injected =
2787 vcpu->arch.exception.pending &&
2788 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2789 events->exception.nr = vcpu->arch.exception.nr;
2790 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2791 events->exception.pad = 0;
3cfc3092
JK		 2792 events->exception.error_code = vcpu->arch.exception.error_code;
2793
03b82a30
JK		 2794 events->interrupt.injected =
2795 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2796 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2797 events->interrupt.soft = 0;
37ccdcbe 2798 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2799
2800 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2801 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2802 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2803 events->nmi.pad = 0;
3cfc3092 2804
66450a21 2805 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2806
f077825a
PB		 2807 events->smi.smm = is_smm(vcpu);
2808 events->smi.pending = vcpu->arch.smi_pending;
2809 events->smi.smm_inside_nmi =
2810 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2811 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2812
dab4b911 2813 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2814 | KVM_VCPUEVENT_VALID_SHADOW
2815 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2816 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2817}
2818
2819static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2820 struct kvm_vcpu_events *events)
2821{
dab4b911 2822 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2823 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2824 | KVM_VCPUEVENT_VALID_SHADOW
2825 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2826 return -EINVAL;
2827
7460fb4a 2828 process_nmi(vcpu);
3cfc3092
JK		 2829 vcpu->arch.exception.pending = events->exception.injected;
2830 vcpu->arch.exception.nr = events->exception.nr;
2831 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2832 vcpu->arch.exception.error_code = events->exception.error_code;
2833
2834 vcpu->arch.interrupt.pending = events->interrupt.injected;
2835 vcpu->arch.interrupt.nr = events->interrupt.nr;
2836 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2837 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2838 kvm_x86_ops->set_interrupt_shadow(vcpu,
2839 events->interrupt.shadow);
3cfc3092
JK		 2840
2841 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2842 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2843 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2844 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2845
66450a21
JK		 2846 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2847 kvm_vcpu_has_lapic(vcpu))
2848 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2849
f077825a
PB		 2850 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2851 if (events->smi.smm)
2852 vcpu->arch.hflags |= HF_SMM_MASK;
2853 else
2854 vcpu->arch.hflags &= ~HF_SMM_MASK;
2855 vcpu->arch.smi_pending = events->smi.pending;
2856 if (events->smi.smm_inside_nmi)
2857 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2858 else
2859 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2860 if (kvm_vcpu_has_lapic(vcpu)) {
2861 if (events->smi.latched_init)
2862 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2863 else
2864 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2865 }
2866 }
2867
3842d135
AK		 2868 kvm_make_request(KVM_REQ_EVENT, vcpu);
2869
3cfc3092
JK		 2870 return 0;
2871}
2872
a1efbe77
JK		 2873static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2874 struct kvm_debugregs *dbgregs)
2875{
73aaf249
JK		 2876 unsigned long val;
2877
a1efbe77 2878 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2879 kvm_get_dr(vcpu, 6, &val);
73aaf249 2880 dbgregs->dr6 = val;
a1efbe77
JK		 2881 dbgregs->dr7 = vcpu->arch.dr7;
2882 dbgregs->flags = 0;
97e69aa6 2883 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2884}
2885
2886static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2887 struct kvm_debugregs *dbgregs)
2888{
2889 if (dbgregs->flags)
2890 return -EINVAL;
2891
a1efbe77 2892 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2893 kvm_update_dr0123(vcpu);
a1efbe77 2894 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2895 kvm_update_dr6(vcpu);
a1efbe77 2896 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2897 kvm_update_dr7(vcpu);
a1efbe77 2898
a1efbe77
JK		 2899 return 0;
2900}
2901
df1daba7
PB		 2902#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2903
2904static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2905{
c47ada30 2906 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2907 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2908 u64 valid;
2909
2910 /*
2911 * Copy legacy XSAVE area, to avoid complications with CPUID
2912 * leaves 0 and 1 in the loop below.
2913 */
2914 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2915
2916 /* Set XSTATE_BV */
2917 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2918
2919 /*
2920 * Copy each region from the possibly compacted offset to the
2921 * non-compacted offset.
2922 */
2923 valid = xstate_bv & ~XSTATE_FPSSE;
2924 while (valid) {
2925 u64 feature = valid & -valid;
2926 int index = fls64(feature) - 1;
2927 void *src = get_xsave_addr(xsave, feature);
2928
2929 if (src) {
2930 u32 size, offset, ecx, edx;
2931 cpuid_count(XSTATE_CPUID, index,
2932 &size, &offset, &ecx, &edx);
2933 memcpy(dest + offset, src, size);
2934 }
2935
2936 valid -= feature;
2937 }
2938}
2939
2940static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2941{
c47ada30 2942 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2943 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2944 u64 valid;
2945
2946 /*
2947 * Copy legacy XSAVE area, to avoid complications with CPUID
2948 * leaves 0 and 1 in the loop below.
2949 */
2950 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2951
2952 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2953 xsave->header.xfeatures = xstate_bv;
df1daba7 2954 if (cpu_has_xsaves)
3a54450b 2955 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2956
2957 /*
2958 * Copy each region from the non-compacted offset to the
2959 * possibly compacted offset.
2960 */
2961 valid = xstate_bv & ~XSTATE_FPSSE;
2962 while (valid) {
2963 u64 feature = valid & -valid;
2964 int index = fls64(feature) - 1;
2965 void *dest = get_xsave_addr(xsave, feature);
2966
2967 if (dest) {
2968 u32 size, offset, ecx, edx;
2969 cpuid_count(XSTATE_CPUID, index,
2970 &size, &offset, &ecx, &edx);
2971 memcpy(dest, src + offset, size);
ee4100da 2972 }
df1daba7
PB		 2973
2974 valid -= feature;
2975 }
2976}
2977
2d5b5a66
SY		 2978static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2979 struct kvm_xsave *guest_xsave)
2980{
4344ee98 2981 if (cpu_has_xsave) {
df1daba7
PB		 2982 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2983 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2984 } else {
2d5b5a66 2985 memcpy(guest_xsave->region,
7366ed77 2986 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2987 sizeof(struct fxregs_state));
2d5b5a66
SY		 2988 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2989 XSTATE_FPSSE;
2990 }
2991}
2992
2993static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2994 struct kvm_xsave *guest_xsave)
2995{
2996 u64 xstate_bv =
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2998
d7876f1b
PB		 2999 if (cpu_has_xsave) {
3000 /*
3001 * Here we allow setting states that are not present in
3002 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3003 * with old userspace.
3004 */
4ff41732 3005 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3006 return -EINVAL;
df1daba7 3007 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3008 } else {
2d5b5a66
SY		 3009 if (xstate_bv & ~XSTATE_FPSSE)
3010 return -EINVAL;
7366ed77 3011 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3012 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3013 }
3014 return 0;
3015}
3016
3017static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3018 struct kvm_xcrs *guest_xcrs)
3019{
3020 if (!cpu_has_xsave) {
3021 guest_xcrs->nr_xcrs = 0;
3022 return;
3023 }
3024
3025 guest_xcrs->nr_xcrs = 1;
3026 guest_xcrs->flags = 0;
3027 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3028 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3029}
3030
3031static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3032 struct kvm_xcrs *guest_xcrs)
3033{
3034 int i, r = 0;
3035
3036 if (!cpu_has_xsave)
3037 return -EINVAL;
3038
3039 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3040 return -EINVAL;
3041
3042 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3043 /* Only support XCR0 currently */
c67a04cb 3044 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3045 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3046 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3047 break;
3048 }
3049 if (r)
3050 r = -EINVAL;
3051 return r;
3052}
3053
1c0b28c2
EM		 3054/*
3055 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3056 * stopped by the hypervisor. This function will be called from the host only.
3057 * EINVAL is returned when the host attempts to set the flag for a guest that
3058 * does not support pv clocks.
3059 */
3060static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3061{
0b79459b 3062 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3063 return -EINVAL;
51d59c6b 3064 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3066 return 0;
3067}
3068
313a3dc7
CO		 3069long kvm_arch_vcpu_ioctl(struct file *filp,
3070 unsigned int ioctl, unsigned long arg)
3071{
3072 struct kvm_vcpu *vcpu = filp->private_data;
3073 void __user *argp = (void __user *)arg;
3074 int r;
d1ac91d8
AK		 3075 union {
3076 struct kvm_lapic_state *lapic;
3077 struct kvm_xsave *xsave;
3078 struct kvm_xcrs *xcrs;
3079 void *buffer;
3080 } u;
3081
3082 u.buffer = NULL;
313a3dc7
CO		 3083 switch (ioctl) {
3084 case KVM_GET_LAPIC: {
2204ae3c
MT		 3085 r = -EINVAL;
3086 if (!vcpu->arch.apic)
3087 goto out;
d1ac91d8 3088 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3089
b772ff36 3090 r = -ENOMEM;
d1ac91d8 3091 if (!u.lapic)
b772ff36 3092 goto out;
d1ac91d8 3093 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3094 if (r)
3095 goto out;
3096 r = -EFAULT;
d1ac91d8 3097 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3098 goto out;
3099 r = 0;
3100 break;
3101 }
3102 case KVM_SET_LAPIC: {
2204ae3c
MT		 3103 r = -EINVAL;
3104 if (!vcpu->arch.apic)
3105 goto out;
ff5c2c03 3106 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3107 if (IS_ERR(u.lapic))
3108 return PTR_ERR(u.lapic);
ff5c2c03 3109
d1ac91d8 3110 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3111 break;
3112 }
f77bc6a4
ZX		 3113 case KVM_INTERRUPT: {
3114 struct kvm_interrupt irq;
3115
3116 r = -EFAULT;
3117 if (copy_from_user(&irq, argp, sizeof irq))
3118 goto out;
3119 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3120 break;
3121 }
c4abb7c9
JK		 3122 case KVM_NMI: {
3123 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3124 break;
3125 }
f077825a
PB		 3126 case KVM_SMI: {
3127 r = kvm_vcpu_ioctl_smi(vcpu);
3128 break;
3129 }
313a3dc7
CO		 3130 case KVM_SET_CPUID: {
3131 struct kvm_cpuid __user *cpuid_arg = argp;
3132 struct kvm_cpuid cpuid;
3133
3134 r = -EFAULT;
3135 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3136 goto out;
3137 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3138 break;
3139 }
07716717
DK		 3140 case KVM_SET_CPUID2: {
3141 struct kvm_cpuid2 __user *cpuid_arg = argp;
3142 struct kvm_cpuid2 cpuid;
3143
3144 r = -EFAULT;
3145 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3146 goto out;
3147 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3148 cpuid_arg->entries);
07716717
DK		 3149 break;
3150 }
3151 case KVM_GET_CPUID2: {
3152 struct kvm_cpuid2 __user *cpuid_arg = argp;
3153 struct kvm_cpuid2 cpuid;
3154
3155 r = -EFAULT;
3156 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3157 goto out;
3158 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3159 cpuid_arg->entries);
07716717
DK		 3160 if (r)
3161 goto out;
3162 r = -EFAULT;
3163 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3164 goto out;
3165 r = 0;
3166 break;
3167 }
313a3dc7 3168 case KVM_GET_MSRS:
609e36d3 3169 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3170 break;
3171 case KVM_SET_MSRS:
3172 r = msr_io(vcpu, argp, do_set_msr, 0);
3173 break;
b209749f
AK		 3174 case KVM_TPR_ACCESS_REPORTING: {
3175 struct kvm_tpr_access_ctl tac;
3176
3177 r = -EFAULT;
3178 if (copy_from_user(&tac, argp, sizeof tac))
3179 goto out;
3180 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3181 if (r)
3182 goto out;
3183 r = -EFAULT;
3184 if (copy_to_user(argp, &tac, sizeof tac))
3185 goto out;
3186 r = 0;
3187 break;
3188 };
b93463aa
AK		 3189 case KVM_SET_VAPIC_ADDR: {
3190 struct kvm_vapic_addr va;
3191
3192 r = -EINVAL;
35754c98 3193 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3194 goto out;
3195 r = -EFAULT;
3196 if (copy_from_user(&va, argp, sizeof va))
3197 goto out;
fda4e2e8 3198 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3199 break;
3200 }
890ca9ae
HY		 3201 case KVM_X86_SETUP_MCE: {
3202 u64 mcg_cap;
3203
3204 r = -EFAULT;
3205 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3206 goto out;
3207 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3208 break;
3209 }
3210 case KVM_X86_SET_MCE: {
3211 struct kvm_x86_mce mce;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&mce, argp, sizeof mce))
3215 goto out;
3216 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3217 break;
3218 }
3cfc3092
JK		 3219 case KVM_GET_VCPU_EVENTS: {
3220 struct kvm_vcpu_events events;
3221
3222 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3223
3224 r = -EFAULT;
3225 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3226 break;
3227 r = 0;
3228 break;
3229 }
3230 case KVM_SET_VCPU_EVENTS: {
3231 struct kvm_vcpu_events events;
3232
3233 r = -EFAULT;
3234 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3235 break;
3236
3237 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3238 break;
3239 }
a1efbe77
JK		 3240 case KVM_GET_DEBUGREGS: {
3241 struct kvm_debugregs dbgregs;
3242
3243 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3244
3245 r = -EFAULT;
3246 if (copy_to_user(argp, &dbgregs,
3247 sizeof(struct kvm_debugregs)))
3248 break;
3249 r = 0;
3250 break;
3251 }
3252 case KVM_SET_DEBUGREGS: {
3253 struct kvm_debugregs dbgregs;
3254
3255 r = -EFAULT;
3256 if (copy_from_user(&dbgregs, argp,
3257 sizeof(struct kvm_debugregs)))
3258 break;
3259
3260 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3261 break;
3262 }
2d5b5a66 3263 case KVM_GET_XSAVE: {
d1ac91d8 3264 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3265 r = -ENOMEM;
d1ac91d8 3266 if (!u.xsave)
2d5b5a66
SY		 3267 break;
3268
d1ac91d8 3269 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3270
3271 r = -EFAULT;
d1ac91d8 3272 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3273 break;
3274 r = 0;
3275 break;
3276 }
3277 case KVM_SET_XSAVE: {
ff5c2c03 3278 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3279 if (IS_ERR(u.xsave))
3280 return PTR_ERR(u.xsave);
2d5b5a66 3281
d1ac91d8 3282 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3283 break;
3284 }
3285 case KVM_GET_XCRS: {
d1ac91d8 3286 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3287 r = -ENOMEM;
d1ac91d8 3288 if (!u.xcrs)
2d5b5a66
SY		 3289 break;
3290
d1ac91d8 3291 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3292
3293 r = -EFAULT;
d1ac91d8 3294 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3295 sizeof(struct kvm_xcrs)))
3296 break;
3297 r = 0;
3298 break;
3299 }
3300 case KVM_SET_XCRS: {
ff5c2c03 3301 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3302 if (IS_ERR(u.xcrs))
3303 return PTR_ERR(u.xcrs);
2d5b5a66 3304
d1ac91d8 3305 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3306 break;
3307 }
92a1f12d
JR		 3308 case KVM_SET_TSC_KHZ: {
3309 u32 user_tsc_khz;
3310
3311 r = -EINVAL;
92a1f12d
JR		 3312 user_tsc_khz = (u32)arg;
3313
3314 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3315 goto out;
3316
cc578287
ZA		 3317 if (user_tsc_khz == 0)
3318 user_tsc_khz = tsc_khz;
3319
3320 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3321
3322 r = 0;
3323 goto out;
3324 }
3325 case KVM_GET_TSC_KHZ: {
cc578287 3326 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3327 goto out;
3328 }
1c0b28c2
EM		 3329 case KVM_KVMCLOCK_CTRL: {
3330 r = kvm_set_guest_paused(vcpu);
3331 goto out;
3332 }
313a3dc7
CO		 3333 default:
3334 r = -EINVAL;
3335 }
3336out:
d1ac91d8 3337 kfree(u.buffer);
313a3dc7
CO		 3338 return r;
3339}
3340
5b1c1493
CO		 3341int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3342{
3343 return VM_FAULT_SIGBUS;
3344}
3345
1fe779f8
CO		 3346static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3347{
3348 int ret;
3349
3350 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3351 return -EINVAL;
1fe779f8
CO		 3352 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3353 return ret;
3354}
3355
b927a3ce
SY		 3356static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3357 u64 ident_addr)
3358{
3359 kvm->arch.ept_identity_map_addr = ident_addr;
3360 return 0;
3361}
3362
1fe779f8
CO		 3363static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3364 u32 kvm_nr_mmu_pages)
3365{
3366 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3367 return -EINVAL;
3368
79fac95e 3369 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3370
3371 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3372 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3373
79fac95e 3374 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3375 return 0;
3376}
3377
3378static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3379{
39de71ec 3380 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3381}
3382
1fe779f8
CO		 3383static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3384{
3385 int r;
3386
3387 r = 0;
3388 switch (chip->chip_id) {
3389 case KVM_IRQCHIP_PIC_MASTER:
3390 memcpy(&chip->chip.pic,
3391 &pic_irqchip(kvm)->pics[0],
3392 sizeof(struct kvm_pic_state));
3393 break;
3394 case KVM_IRQCHIP_PIC_SLAVE:
3395 memcpy(&chip->chip.pic,
3396 &pic_irqchip(kvm)->pics[1],
3397 sizeof(struct kvm_pic_state));
3398 break;
3399 case KVM_IRQCHIP_IOAPIC:
eba0226b 3400 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3401 break;
3402 default:
3403 r = -EINVAL;
3404 break;
3405 }
3406 return r;
3407}
3408
3409static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3410{
3411 int r;
3412
3413 r = 0;
3414 switch (chip->chip_id) {
3415 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3416 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3417 memcpy(&pic_irqchip(kvm)->pics[0],
3418 &chip->chip.pic,
3419 sizeof(struct kvm_pic_state));
f4f51050 3420 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3421 break;
3422 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3423 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3424 memcpy(&pic_irqchip(kvm)->pics[1],
3425 &chip->chip.pic,
3426 sizeof(struct kvm_pic_state));
f4f51050 3427 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3428 break;
3429 case KVM_IRQCHIP_IOAPIC:
eba0226b 3430 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3431 break;
3432 default:
3433 r = -EINVAL;
3434 break;
3435 }
3436 kvm_pic_update_irq(pic_irqchip(kvm));
3437 return r;
3438}
3439
e0f63cb9
SY		 3440static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3441{
3442 int r = 0;
3443
894a9c55 3444 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3445 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3446 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3447 return r;
3448}
3449
3450static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3451{
3452 int r = 0;
3453
894a9c55 3454 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3455 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3456 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3457 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3458 return r;
3459}
3460
3461static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3462{
3463 int r = 0;
3464
3465 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3466 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3467 sizeof(ps->channels));
3468 ps->flags = kvm->arch.vpit->pit_state.flags;
3469 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3470 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3471 return r;
3472}
3473
3474static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3475{
3476 int r = 0, start = 0;
3477 u32 prev_legacy, cur_legacy;
3478 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3479 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3480 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3481 if (!prev_legacy && cur_legacy)
3482 start = 1;
3483 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3484 sizeof(kvm->arch.vpit->pit_state.channels));
3485 kvm->arch.vpit->pit_state.flags = ps->flags;
3486 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3487 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3488 return r;
3489}
3490
52d939a0
MT		 3491static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3492 struct kvm_reinject_control *control)
3493{
3494 if (!kvm->arch.vpit)
3495 return -ENXIO;
894a9c55 3496 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3497 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3498 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3499 return 0;
3500}
3501
95d4c16c 3502/**
60c34612
TY		 3503 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3504 * @kvm: kvm instance
3505 * @log: slot id and address to which we copy the log
95d4c16c 3506 *
e108ff2f
PB		 3507 * Steps 1-4 below provide general overview of dirty page logging. See
3508 * kvm_get_dirty_log_protect() function description for additional details.
3509 *
3510 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3511 * always flush the TLB (step 4) even if previous step failed and the dirty
3512 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3513 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3514 * writes will be marked dirty for next log read.
95d4c16c 3515 *
60c34612
TY		 3516 * 1. Take a snapshot of the bit and clear it if needed.
3517 * 2. Write protect the corresponding page.
e108ff2f
PB		 3518 * 3. Copy the snapshot to the userspace.
3519 * 4. Flush TLB's if needed.
5bb064dc 3520 */
60c34612 3521int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3522{
60c34612 3523 bool is_dirty = false;
e108ff2f 3524 int r;
5bb064dc 3525
79fac95e 3526 mutex_lock(&kvm->slots_lock);
5bb064dc 3527
88178fd4
KH		 3528 /*
3529 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3530 */
3531 if (kvm_x86_ops->flush_log_dirty)
3532 kvm_x86_ops->flush_log_dirty(kvm);
3533
e108ff2f 3534 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3535
3536 /*
3537 * All the TLBs can be flushed out of mmu lock, see the comments in
3538 * kvm_mmu_slot_remove_write_access().
3539 */
e108ff2f 3540 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3541 if (is_dirty)
3542 kvm_flush_remote_tlbs(kvm);
3543
79fac95e 3544 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3545 return r;
3546}
3547
aa2fbe6d
YZ		 3548int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3549 bool line_status)
23d43cf9
CD		 3550{
3551 if (!irqchip_in_kernel(kvm))
3552 return -ENXIO;
3553
3554 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3555 irq_event->irq, irq_event->level,
3556 line_status);
23d43cf9
CD		 3557 return 0;
3558}
3559
90de4a18
NA		 3560static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3561 struct kvm_enable_cap *cap)
3562{
3563 int r;
3564
3565 if (cap->flags)
3566 return -EINVAL;
3567
3568 switch (cap->cap) {
3569 case KVM_CAP_DISABLE_QUIRKS:
3570 kvm->arch.disabled_quirks = cap->args[0];
3571 r = 0;
3572 break;
49df6397
SR		 3573 case KVM_CAP_SPLIT_IRQCHIP: {
3574 mutex_lock(&kvm->lock);
b053b2ae
SR		 3575 r = -EINVAL;
3576 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3577 goto split_irqchip_unlock;
49df6397
SR		 3578 r = -EEXIST;
3579 if (irqchip_in_kernel(kvm))
3580 goto split_irqchip_unlock;
3581 if (atomic_read(&kvm->online_vcpus))
3582 goto split_irqchip_unlock;
3583 r = kvm_setup_empty_irq_routing(kvm);
3584 if (r)
3585 goto split_irqchip_unlock;
3586 /* Pairs with irqchip_in_kernel. */
3587 smp_wmb();
3588 kvm->arch.irqchip_split = true;
b053b2ae 3589 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3590 r = 0;
3591split_irqchip_unlock:
3592 mutex_unlock(&kvm->lock);
3593 break;
3594 }
90de4a18
NA		 3595 default:
3596 r = -EINVAL;
3597 break;
3598 }
3599 return r;
3600}
3601
1fe779f8
CO		 3602long kvm_arch_vm_ioctl(struct file *filp,
3603 unsigned int ioctl, unsigned long arg)
3604{
3605 struct kvm *kvm = filp->private_data;
3606 void __user *argp = (void __user *)arg;
367e1319 3607 int r = -ENOTTY;
f0d66275
DH		 3608 /*
3609 * This union makes it completely explicit to gcc-3.x
3610 * that these two variables' stack usage should be
3611 * combined, not added together.
3612 */
3613 union {
3614 struct kvm_pit_state ps;
e9f42757 3615 struct kvm_pit_state2 ps2;
c5ff41ce 3616 struct kvm_pit_config pit_config;
f0d66275 3617 } u;
1fe779f8
CO		 3618
3619 switch (ioctl) {
3620 case KVM_SET_TSS_ADDR:
3621 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3622 break;
b927a3ce
SY		 3623 case KVM_SET_IDENTITY_MAP_ADDR: {
3624 u64 ident_addr;
3625
3626 r = -EFAULT;
3627 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3628 goto out;
3629 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3630 break;
3631 }
1fe779f8
CO		 3632 case KVM_SET_NR_MMU_PAGES:
3633 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3634 break;
3635 case KVM_GET_NR_MMU_PAGES:
3636 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3637 break;
3ddea128
MT		 3638 case KVM_CREATE_IRQCHIP: {
3639 struct kvm_pic *vpic;
3640
3641 mutex_lock(&kvm->lock);
3642 r = -EEXIST;
3643 if (kvm->arch.vpic)
3644 goto create_irqchip_unlock;
3e515705
AK		 3645 r = -EINVAL;
3646 if (atomic_read(&kvm->online_vcpus))
3647 goto create_irqchip_unlock;
1fe779f8 3648 r = -ENOMEM;
3ddea128
MT		 3649 vpic = kvm_create_pic(kvm);
3650 if (vpic) {
1fe779f8
CO		 3651 r = kvm_ioapic_init(kvm);
3652 if (r) {
175504cd 3653 mutex_lock(&kvm->slots_lock);
71ba994c 3654 kvm_destroy_pic(vpic);
175504cd 3655 mutex_unlock(&kvm->slots_lock);
3ddea128 3656 goto create_irqchip_unlock;
1fe779f8
CO		 3657 }
3658 } else
3ddea128 3659 goto create_irqchip_unlock;
399ec807
AK		 3660 r = kvm_setup_default_irq_routing(kvm);
3661 if (r) {
175504cd 3662 mutex_lock(&kvm->slots_lock);
3ddea128 3663 mutex_lock(&kvm->irq_lock);
72bb2fcd 3664 kvm_ioapic_destroy(kvm);
71ba994c 3665 kvm_destroy_pic(vpic);
3ddea128 3666 mutex_unlock(&kvm->irq_lock);
175504cd 3667 mutex_unlock(&kvm->slots_lock);
71ba994c 3668 goto create_irqchip_unlock;
399ec807 3669 }
71ba994c
PB		 3670 /* Write kvm->irq_routing before kvm->arch.vpic. */
3671 smp_wmb();
3672 kvm->arch.vpic = vpic;
3ddea128
MT		 3673 create_irqchip_unlock:
3674 mutex_unlock(&kvm->lock);
1fe779f8 3675 break;
3ddea128 3676 }
7837699f 3677 case KVM_CREATE_PIT:
c5ff41ce
JK		 3678 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3679 goto create_pit;
3680 case KVM_CREATE_PIT2:
3681 r = -EFAULT;
3682 if (copy_from_user(&u.pit_config, argp,
3683 sizeof(struct kvm_pit_config)))
3684 goto out;
3685 create_pit:
79fac95e 3686 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3687 r = -EEXIST;
3688 if (kvm->arch.vpit)
3689 goto create_pit_unlock;
7837699f 3690 r = -ENOMEM;
c5ff41ce 3691 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3692 if (kvm->arch.vpit)
3693 r = 0;
269e05e4 3694 create_pit_unlock:
79fac95e 3695 mutex_unlock(&kvm->slots_lock);
7837699f 3696 break;
1fe779f8
CO		 3697 case KVM_GET_IRQCHIP: {
3698 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3699 struct kvm_irqchip *chip;
1fe779f8 3700
ff5c2c03
SL		 3701 chip = memdup_user(argp, sizeof(*chip));
3702 if (IS_ERR(chip)) {
3703 r = PTR_ERR(chip);
1fe779f8 3704 goto out;
ff5c2c03
SL		 3705 }
3706
1fe779f8 3707 r = -ENXIO;
49df6397 3708 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3709 goto get_irqchip_out;
3710 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3711 if (r)
f0d66275 3712 goto get_irqchip_out;
1fe779f8 3713 r = -EFAULT;
f0d66275
DH		 3714 if (copy_to_user(argp, chip, sizeof *chip))
3715 goto get_irqchip_out;
1fe779f8 3716 r = 0;
f0d66275
DH		 3717 get_irqchip_out:
3718 kfree(chip);
1fe779f8
CO		 3719 break;
3720 }
3721 case KVM_SET_IRQCHIP: {
3722 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3723 struct kvm_irqchip *chip;
1fe779f8 3724
ff5c2c03
SL		 3725 chip = memdup_user(argp, sizeof(*chip));
3726 if (IS_ERR(chip)) {
3727 r = PTR_ERR(chip);
1fe779f8 3728 goto out;
ff5c2c03
SL		 3729 }
3730
1fe779f8 3731 r = -ENXIO;
49df6397 3732 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3733 goto set_irqchip_out;
3734 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3735 if (r)
f0d66275 3736 goto set_irqchip_out;
1fe779f8 3737 r = 0;
f0d66275
DH		 3738 set_irqchip_out:
3739 kfree(chip);
1fe779f8
CO		 3740 break;
3741 }
e0f63cb9 3742 case KVM_GET_PIT: {
e0f63cb9 3743 r = -EFAULT;
f0d66275 3744 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3745 goto out;
3746 r = -ENXIO;
3747 if (!kvm->arch.vpit)
3748 goto out;
f0d66275 3749 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3750 if (r)
3751 goto out;
3752 r = -EFAULT;
f0d66275 3753 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3754 goto out;
3755 r = 0;
3756 break;
3757 }
3758 case KVM_SET_PIT: {
e0f63cb9 3759 r = -EFAULT;
f0d66275 3760 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3761 goto out;
3762 r = -ENXIO;
3763 if (!kvm->arch.vpit)
3764 goto out;
f0d66275 3765 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3766 break;
3767 }
e9f42757
BK		 3768 case KVM_GET_PIT2: {
3769 r = -ENXIO;
3770 if (!kvm->arch.vpit)
3771 goto out;
3772 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3773 if (r)
3774 goto out;
3775 r = -EFAULT;
3776 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3777 goto out;
3778 r = 0;
3779 break;
3780 }
3781 case KVM_SET_PIT2: {
3782 r = -EFAULT;
3783 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3784 goto out;
3785 r = -ENXIO;
3786 if (!kvm->arch.vpit)
3787 goto out;
3788 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3789 break;
3790 }
52d939a0
MT		 3791 case KVM_REINJECT_CONTROL: {
3792 struct kvm_reinject_control control;
3793 r = -EFAULT;
3794 if (copy_from_user(&control, argp, sizeof(control)))
3795 goto out;
3796 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3797 break;
3798 }
d71ba788
PB		 3799 case KVM_SET_BOOT_CPU_ID:
3800 r = 0;
3801 mutex_lock(&kvm->lock);
3802 if (atomic_read(&kvm->online_vcpus) != 0)
3803 r = -EBUSY;
3804 else
3805 kvm->arch.bsp_vcpu_id = arg;
3806 mutex_unlock(&kvm->lock);
3807 break;
ffde22ac
ES		 3808 case KVM_XEN_HVM_CONFIG: {
3809 r = -EFAULT;
3810 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3811 sizeof(struct kvm_xen_hvm_config)))
3812 goto out;
3813 r = -EINVAL;
3814 if (kvm->arch.xen_hvm_config.flags)
3815 goto out;
3816 r = 0;
3817 break;
3818 }
afbcf7ab 3819 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3820 struct kvm_clock_data user_ns;
3821 u64 now_ns;
3822 s64 delta;
3823
3824 r = -EFAULT;
3825 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3826 goto out;
3827
3828 r = -EINVAL;
3829 if (user_ns.flags)
3830 goto out;
3831
3832 r = 0;
395c6b0a 3833 local_irq_disable();
759379dd 3834 now_ns = get_kernel_ns();
afbcf7ab 3835 delta = user_ns.clock - now_ns;
395c6b0a 3836 local_irq_enable();
afbcf7ab 3837 kvm->arch.kvmclock_offset = delta;
2e762ff7 3838 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3839 break;
3840 }
3841 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3842 struct kvm_clock_data user_ns;
3843 u64 now_ns;
3844
395c6b0a 3845 local_irq_disable();
759379dd 3846 now_ns = get_kernel_ns();
afbcf7ab 3847 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3848 local_irq_enable();
afbcf7ab 3849 user_ns.flags = 0;
97e69aa6 3850 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3851
3852 r = -EFAULT;
3853 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3854 goto out;
3855 r = 0;
3856 break;
3857 }
90de4a18
NA		 3858 case KVM_ENABLE_CAP: {
3859 struct kvm_enable_cap cap;
afbcf7ab 3860
90de4a18
NA		 3861 r = -EFAULT;
3862 if (copy_from_user(&cap, argp, sizeof(cap)))
3863 goto out;
3864 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3865 break;
3866 }
1fe779f8 3867 default:
c274e03a 3868 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3869 }
3870out:
3871 return r;
3872}
3873
a16b043c 3874static void kvm_init_msr_list(void)
043405e1
CO		 3875{
3876 u32 dummy[2];
3877 unsigned i, j;
3878
62ef68bb 3879 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3880 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3881 continue;
93c4adc7
PB		 3882
3883 /*
3884 * Even MSRs that are valid in the host may not be exposed
3885 * to the guests in some cases. We could work around this
3886 * in VMX with the generic MSR save/load machinery, but it
3887 * is not really worthwhile since it will really only
3888 * happen with nested virtualization.
3889 */
3890 switch (msrs_to_save[i]) {
3891 case MSR_IA32_BNDCFGS:
3892 if (!kvm_x86_ops->mpx_supported())
3893 continue;
3894 break;
3895 default:
3896 break;
3897 }
3898
043405e1
CO		 3899 if (j < i)
3900 msrs_to_save[j] = msrs_to_save[i];
3901 j++;
3902 }
3903 num_msrs_to_save = j;
62ef68bb
PB		 3904
3905 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3906 switch (emulated_msrs[i]) {
6d396b55
PB		 3907 case MSR_IA32_SMBASE:
3908 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3909 continue;
3910 break;
62ef68bb
PB		 3911 default:
3912 break;
3913 }
3914
3915 if (j < i)
3916 emulated_msrs[j] = emulated_msrs[i];
3917 j++;
3918 }
3919 num_emulated_msrs = j;
043405e1
CO		 3920}
3921
bda9020e
MT		 3922static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3923 const void *v)
bbd9b64e 3924{
70252a10
AK		 3925 int handled = 0;
3926 int n;
3927
3928 do {
3929 n = min(len, 8);
3930 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3931 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3932 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3933 break;
3934 handled += n;
3935 addr += n;
3936 len -= n;
3937 v += n;
3938 } while (len);
bbd9b64e 3939
70252a10 3940 return handled;
bbd9b64e
CO		 3941}
3942
bda9020e 3943static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3944{
70252a10
AK		 3945 int handled = 0;
3946 int n;
3947
3948 do {
3949 n = min(len, 8);
3950 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3951 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3952 addr, n, v))
3953 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3954 break;
3955 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3956 handled += n;
3957 addr += n;
3958 len -= n;
3959 v += n;
3960 } while (len);
bbd9b64e 3961
70252a10 3962 return handled;
bbd9b64e
CO		 3963}
3964
2dafc6c2
GN		 3965static void kvm_set_segment(struct kvm_vcpu *vcpu,
3966 struct kvm_segment *var, int seg)
3967{
3968 kvm_x86_ops->set_segment(vcpu, var, seg);
3969}
3970
3971void kvm_get_segment(struct kvm_vcpu *vcpu,
3972 struct kvm_segment *var, int seg)
3973{
3974 kvm_x86_ops->get_segment(vcpu, var, seg);
3975}
3976
54987b7a
PB		 3977gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3978 struct x86_exception *exception)
02f59dc9
JR		 3979{
3980 gpa_t t_gpa;
02f59dc9
JR		 3981
3982 BUG_ON(!mmu_is_nested(vcpu));
3983
3984 /* NPT walks are always user-walks */
3985 access |= PFERR_USER_MASK;
54987b7a 3986 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3987
3988 return t_gpa;
3989}
3990
ab9ae313
AK		 3991gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3992 struct x86_exception *exception)
1871c602
GN		 3993{
3994 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3995 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3996}
3997
ab9ae313
AK		 3998 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3999 struct x86_exception *exception)
1871c602
GN		 4000{
4001 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4002 access |= PFERR_FETCH_MASK;
ab9ae313 4003 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4004}
4005
ab9ae313
AK		 4006gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4007 struct x86_exception *exception)
1871c602
GN		 4008{
4009 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4010 access |= PFERR_WRITE_MASK;
ab9ae313 4011 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4012}
4013
4014/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4015gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4016 struct x86_exception *exception)
1871c602 4017{
ab9ae313 4018 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4019}
4020
4021static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4022 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4023 struct x86_exception *exception)
bbd9b64e
CO		 4024{
4025 void *data = val;
10589a46 4026 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4027
4028 while (bytes) {
14dfe855 4029 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4030 exception);
bbd9b64e 4031 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4032 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4033 int ret;
4034
bcc55cba 4035 if (gpa == UNMAPPED_GVA)
ab9ae313 4036 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4037 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4038 offset, toread);
10589a46 4039 if (ret < 0) {
c3cd7ffa 4040 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4041 goto out;
4042 }
bbd9b64e 4043
77c2002e
IE		 4044 bytes -= toread;
4045 data += toread;
4046 addr += toread;
bbd9b64e 4047 }
10589a46 4048out:
10589a46 4049 return r;
bbd9b64e 4050}
77c2002e 4051
1871c602 4052/* used for instruction fetching */
0f65dd70
AK		 4053static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4054 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4055 struct x86_exception *exception)
1871c602 4056{
0f65dd70 4057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4058 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4059 unsigned offset;
4060 int ret;
0f65dd70 4061
44583cba
PB		 4062 /* Inline kvm_read_guest_virt_helper for speed. */
4063 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4064 exception);
4065 if (unlikely(gpa == UNMAPPED_GVA))
4066 return X86EMUL_PROPAGATE_FAULT;
4067
4068 offset = addr & (PAGE_SIZE-1);
4069 if (WARN_ON(offset + bytes > PAGE_SIZE))
4070 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4071 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4072 offset, bytes);
44583cba
PB		 4073 if (unlikely(ret < 0))
4074 return X86EMUL_IO_NEEDED;
4075
4076 return X86EMUL_CONTINUE;
1871c602
GN		 4077}
4078
064aea77 4079int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4080 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4081 struct x86_exception *exception)
1871c602 4082{
0f65dd70 4083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4085
1871c602 4086 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4087 exception);
1871c602 4088}
064aea77 4089EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4090
0f65dd70
AK		 4091static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4092 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4093 struct x86_exception *exception)
1871c602 4094{
0f65dd70 4095 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4096 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4097}
4098
6a4d7550 4099int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4100 gva_t addr, void *val,
2dafc6c2 4101 unsigned int bytes,
bcc55cba 4102 struct x86_exception *exception)
77c2002e 4103{
0f65dd70 4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4105 void *data = val;
4106 int r = X86EMUL_CONTINUE;
4107
4108 while (bytes) {
14dfe855
JR		 4109 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4110 PFERR_WRITE_MASK,
ab9ae313 4111 exception);
77c2002e
IE		 4112 unsigned offset = addr & (PAGE_SIZE-1);
4113 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4114 int ret;
4115
bcc55cba 4116 if (gpa == UNMAPPED_GVA)
ab9ae313 4117 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4118 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4119 if (ret < 0) {
c3cd7ffa 4120 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4121 goto out;
4122 }
4123
4124 bytes -= towrite;
4125 data += towrite;
4126 addr += towrite;
4127 }
4128out:
4129 return r;
4130}
6a4d7550 4131EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4132
af7cc7d1
XG		 4133static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4134 gpa_t *gpa, struct x86_exception *exception,
4135 bool write)
4136{
97d64b78
AK		 4137 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4138 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4139
97d64b78 4140 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4141 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4142 vcpu->arch.access, access)) {
bebb106a
XG		 4143 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4144 (gva & (PAGE_SIZE - 1));
4f022648 4145 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4146 return 1;
4147 }
4148
af7cc7d1
XG		 4149 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4150
4151 if (*gpa == UNMAPPED_GVA)
4152 return -1;
4153
4154 /* For APIC access vmexit */
4155 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4156 return 1;
4157
4f022648
XG		 4158 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4159 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4160 return 1;
4f022648 4161 }
bebb106a 4162
af7cc7d1
XG		 4163 return 0;
4164}
4165
3200f405 4166int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4167 const void *val, int bytes)
bbd9b64e
CO		 4168{
4169 int ret;
4170
54bf36aa 4171 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4172 if (ret < 0)
bbd9b64e 4173 return 0;
f57f2ef5 4174 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4175 return 1;
4176}
4177
77d197b2
XG		 4178struct read_write_emulator_ops {
4179 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4180 int bytes);
4181 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4182 void *val, int bytes);
4183 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 int bytes, void *val);
4185 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 void *val, int bytes);
4187 bool write;
4188};
4189
4190static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4191{
4192 if (vcpu->mmio_read_completed) {
77d197b2 4193 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4194 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4195 vcpu->mmio_read_completed = 0;
4196 return 1;
4197 }
4198
4199 return 0;
4200}
4201
4202static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4203 void *val, int bytes)
4204{
54bf36aa 4205 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4206}
4207
4208static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4209 void *val, int bytes)
4210{
4211 return emulator_write_phys(vcpu, gpa, val, bytes);
4212}
4213
4214static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4215{
4216 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4217 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4218}
4219
4220static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4221 void *val, int bytes)
4222{
4223 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4224 return X86EMUL_IO_NEEDED;
4225}
4226
4227static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4228 void *val, int bytes)
4229{
f78146b0
AK		 4230 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4231
87da7e66 4232 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4233 return X86EMUL_CONTINUE;
4234}
4235
0fbe9b0b 4236static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4237 .read_write_prepare = read_prepare,
4238 .read_write_emulate = read_emulate,
4239 .read_write_mmio = vcpu_mmio_read,
4240 .read_write_exit_mmio = read_exit_mmio,
4241};
4242
0fbe9b0b 4243static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4244 .read_write_emulate = write_emulate,
4245 .read_write_mmio = write_mmio,
4246 .read_write_exit_mmio = write_exit_mmio,
4247 .write = true,
4248};
4249
22388a3c
XG		 4250static int emulator_read_write_onepage(unsigned long addr, void *val,
4251 unsigned int bytes,
4252 struct x86_exception *exception,
4253 struct kvm_vcpu *vcpu,
0fbe9b0b 4254 const struct read_write_emulator_ops *ops)
bbd9b64e 4255{
af7cc7d1
XG		 4256 gpa_t gpa;
4257 int handled, ret;
22388a3c 4258 bool write = ops->write;
f78146b0 4259 struct kvm_mmio_fragment *frag;
10589a46 4260
22388a3c 4261 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4262
af7cc7d1 4263 if (ret < 0)
bbd9b64e 4264 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4265
4266 /* For APIC access vmexit */
af7cc7d1 4267 if (ret)
bbd9b64e
CO		 4268 goto mmio;
4269
22388a3c 4270 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4271 return X86EMUL_CONTINUE;
4272
4273mmio:
4274 /*
4275 * Is this MMIO handled locally?
4276 */
22388a3c 4277 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4278 if (handled == bytes)
bbd9b64e 4279 return X86EMUL_CONTINUE;
bbd9b64e 4280
70252a10
AK		 4281 gpa += handled;
4282 bytes -= handled;
4283 val += handled;
4284
87da7e66
XG		 4285 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4286 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4287 frag->gpa = gpa;
4288 frag->data = val;
4289 frag->len = bytes;
f78146b0 4290 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4291}
4292
52eb5a6d
XL		 4293static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4294 unsigned long addr,
22388a3c
XG		 4295 void *val, unsigned int bytes,
4296 struct x86_exception *exception,
0fbe9b0b 4297 const struct read_write_emulator_ops *ops)
bbd9b64e 4298{
0f65dd70 4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4300 gpa_t gpa;
4301 int rc;
4302
4303 if (ops->read_write_prepare &&
4304 ops->read_write_prepare(vcpu, val, bytes))
4305 return X86EMUL_CONTINUE;
4306
4307 vcpu->mmio_nr_fragments = 0;
0f65dd70 4308
bbd9b64e
CO		 4309 /* Crossing a page boundary? */
4310 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4311 int now;
bbd9b64e
CO		 4312
4313 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4314 rc = emulator_read_write_onepage(addr, val, now, exception,
4315 vcpu, ops);
4316
bbd9b64e
CO		 4317 if (rc != X86EMUL_CONTINUE)
4318 return rc;
4319 addr += now;
bac15531
NA		 4320 if (ctxt->mode != X86EMUL_MODE_PROT64)
4321 addr = (u32)addr;
bbd9b64e
CO		 4322 val += now;
4323 bytes -= now;
4324 }
22388a3c 4325
f78146b0
AK		 4326 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4327 vcpu, ops);
4328 if (rc != X86EMUL_CONTINUE)
4329 return rc;
4330
4331 if (!vcpu->mmio_nr_fragments)
4332 return rc;
4333
4334 gpa = vcpu->mmio_fragments[0].gpa;
4335
4336 vcpu->mmio_needed = 1;
4337 vcpu->mmio_cur_fragment = 0;
4338
87da7e66 4339 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4340 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4341 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4342 vcpu->run->mmio.phys_addr = gpa;
4343
4344 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4345}
4346
4347static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4348 unsigned long addr,
4349 void *val,
4350 unsigned int bytes,
4351 struct x86_exception *exception)
4352{
4353 return emulator_read_write(ctxt, addr, val, bytes,
4354 exception, &read_emultor);
4355}
4356
52eb5a6d 4357static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4358 unsigned long addr,
4359 const void *val,
4360 unsigned int bytes,
4361 struct x86_exception *exception)
4362{
4363 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4364 exception, &write_emultor);
bbd9b64e 4365}
bbd9b64e 4366
daea3e73
AK		 4367#define CMPXCHG_TYPE(t, ptr, old, new) \
4368 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4369
4370#ifdef CONFIG_X86_64
4371# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4372#else
4373# define CMPXCHG64(ptr, old, new) \
9749a6c0 4374 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4375#endif
4376
0f65dd70
AK		 4377static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4378 unsigned long addr,
bbd9b64e
CO		 4379 const void *old,
4380 const void *new,
4381 unsigned int bytes,
0f65dd70 4382 struct x86_exception *exception)
bbd9b64e 4383{
0f65dd70 4384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4385 gpa_t gpa;
4386 struct page *page;
4387 char *kaddr;
4388 bool exchanged;
2bacc55c 4389
daea3e73
AK		 4390 /* guests cmpxchg8b have to be emulated atomically */
4391 if (bytes > 8 || (bytes & (bytes - 1)))
4392 goto emul_write;
10589a46 4393
daea3e73 4394 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4395
daea3e73
AK		 4396 if (gpa == UNMAPPED_GVA ||
4397 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4398 goto emul_write;
2bacc55c 4399
daea3e73
AK		 4400 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4401 goto emul_write;
72dc67a6 4402
54bf36aa 4403 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4404 if (is_error_page(page))
c19b8bd6 4405 goto emul_write;
72dc67a6 4406
8fd75e12 4407 kaddr = kmap_atomic(page);
daea3e73
AK		 4408 kaddr += offset_in_page(gpa);
4409 switch (bytes) {
4410 case 1:
4411 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4412 break;
4413 case 2:
4414 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4415 break;
4416 case 4:
4417 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4418 break;
4419 case 8:
4420 exchanged = CMPXCHG64(kaddr, old, new);
4421 break;
4422 default:
4423 BUG();
2bacc55c 4424 }
8fd75e12 4425 kunmap_atomic(kaddr);
daea3e73
AK		 4426 kvm_release_page_dirty(page);
4427
4428 if (!exchanged)
4429 return X86EMUL_CMPXCHG_FAILED;
4430
54bf36aa 4431 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4432 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4433
4434 return X86EMUL_CONTINUE;
4a5f48f6 4435
3200f405 4436emul_write:
daea3e73 4437 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4438
0f65dd70 4439 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4440}
4441
cf8f70bf
GN		 4442static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4443{
4444 /* TODO: String I/O for in kernel device */
4445 int r;
4446
4447 if (vcpu->arch.pio.in)
e32edf4f 4448 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4449 vcpu->arch.pio.size, pd);
4450 else
e32edf4f 4451 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4452 vcpu->arch.pio.port, vcpu->arch.pio.size,
4453 pd);
4454 return r;
4455}
4456
6f6fbe98
XG		 4457static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4458 unsigned short port, void *val,
4459 unsigned int count, bool in)
cf8f70bf 4460{
cf8f70bf 4461 vcpu->arch.pio.port = port;
6f6fbe98 4462 vcpu->arch.pio.in = in;
7972995b 4463 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4464 vcpu->arch.pio.size = size;
4465
4466 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4467 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4468 return 1;
4469 }
4470
4471 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4472 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4473 vcpu->run->io.size = size;
4474 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4475 vcpu->run->io.count = count;
4476 vcpu->run->io.port = port;
4477
4478 return 0;
4479}
4480
6f6fbe98
XG		 4481static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4482 int size, unsigned short port, void *val,
4483 unsigned int count)
cf8f70bf 4484{
ca1d4a9e 4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4486 int ret;
ca1d4a9e 4487
6f6fbe98
XG		 4488 if (vcpu->arch.pio.count)
4489 goto data_avail;
cf8f70bf 4490
6f6fbe98
XG		 4491 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4492 if (ret) {
4493data_avail:
4494 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4495 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4496 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4497 return 1;
4498 }
4499
cf8f70bf
GN		 4500 return 0;
4501}
4502
6f6fbe98
XG		 4503static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4504 int size, unsigned short port,
4505 const void *val, unsigned int count)
4506{
4507 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4508
4509 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4510 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4511 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4512}
4513
bbd9b64e
CO		 4514static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4515{
4516 return kvm_x86_ops->get_segment_base(vcpu, seg);
4517}
4518
3cb16fe7 4519static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4520{
3cb16fe7 4521 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4522}
4523
5cb56059 4524int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4525{
4526 if (!need_emulate_wbinvd(vcpu))
4527 return X86EMUL_CONTINUE;
4528
4529 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4530 int cpu = get_cpu();
4531
4532 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4533 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4534 wbinvd_ipi, NULL, 1);
2eec7343 4535 put_cpu();
f5f48ee1 4536 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4537 } else
4538 wbinvd();
f5f48ee1
SY		 4539 return X86EMUL_CONTINUE;
4540}
5cb56059
JS		 4541
4542int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4543{
4544 kvm_x86_ops->skip_emulated_instruction(vcpu);
4545 return kvm_emulate_wbinvd_noskip(vcpu);
4546}
f5f48ee1
SY		 4547EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4548
5cb56059
JS		 4549
4550
bcaf5cc5
AK		 4551static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4552{
5cb56059 4553 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4554}
4555
52eb5a6d
XL		 4556static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4557 unsigned long *dest)
bbd9b64e 4558{
16f8a6f9 4559 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4560}
4561
52eb5a6d
XL		 4562static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4563 unsigned long value)
bbd9b64e 4564{
338dbc97 4565
717746e3 4566 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4567}
4568
52a46617 4569static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4570{
52a46617 4571 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4572}
4573
717746e3 4574static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4575{
717746e3 4576 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4577 unsigned long value;
4578
4579 switch (cr) {
4580 case 0:
4581 value = kvm_read_cr0(vcpu);
4582 break;
4583 case 2:
4584 value = vcpu->arch.cr2;
4585 break;
4586 case 3:
9f8fe504 4587 value = kvm_read_cr3(vcpu);
52a46617
GN		 4588 break;
4589 case 4:
4590 value = kvm_read_cr4(vcpu);
4591 break;
4592 case 8:
4593 value = kvm_get_cr8(vcpu);
4594 break;
4595 default:
a737f256 4596 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4597 return 0;
4598 }
4599
4600 return value;
4601}
4602
717746e3 4603static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4604{
717746e3 4605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4606 int res = 0;
4607
52a46617
GN		 4608 switch (cr) {
4609 case 0:
49a9b07e 4610 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4611 break;
4612 case 2:
4613 vcpu->arch.cr2 = val;
4614 break;
4615 case 3:
2390218b 4616 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4617 break;
4618 case 4:
a83b29c6 4619 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4620 break;
4621 case 8:
eea1cff9 4622 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4623 break;
4624 default:
a737f256 4625 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4626 res = -1;
52a46617 4627 }
0f12244f
GN		 4628
4629 return res;
52a46617
GN		 4630}
4631
717746e3 4632static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4633{
717746e3 4634 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4635}
4636
4bff1e86 4637static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4638{
4bff1e86 4639 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4640}
4641
4bff1e86 4642static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4643{
4bff1e86 4644 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4645}
4646
1ac9d0cf
AK		 4647static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4648{
4649 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4650}
4651
4652static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4653{
4654 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4655}
4656
4bff1e86
AK		 4657static unsigned long emulator_get_cached_segment_base(
4658 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4659{
4bff1e86 4660 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4661}
4662
1aa36616
AK		 4663static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4664 struct desc_struct *desc, u32 *base3,
4665 int seg)
2dafc6c2
GN		 4666{
4667 struct kvm_segment var;
4668
4bff1e86 4669 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4670 *selector = var.selector;
2dafc6c2 4671
378a8b09
GN		 4672 if (var.unusable) {
4673 memset(desc, 0, sizeof(*desc));
2dafc6c2 4674 return false;
378a8b09 4675 }
2dafc6c2
GN		 4676
4677 if (var.g)
4678 var.limit >>= 12;
4679 set_desc_limit(desc, var.limit);
4680 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4681#ifdef CONFIG_X86_64
4682 if (base3)
4683 *base3 = var.base >> 32;
4684#endif
2dafc6c2
GN		 4685 desc->type = var.type;
4686 desc->s = var.s;
4687 desc->dpl = var.dpl;
4688 desc->p = var.present;
4689 desc->avl = var.avl;
4690 desc->l = var.l;
4691 desc->d = var.db;
4692 desc->g = var.g;
4693
4694 return true;
4695}
4696
1aa36616
AK		 4697static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4698 struct desc_struct *desc, u32 base3,
4699 int seg)
2dafc6c2 4700{
4bff1e86 4701 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4702 struct kvm_segment var;
4703
1aa36616 4704 var.selector = selector;
2dafc6c2 4705 var.base = get_desc_base(desc);
5601d05b
GN		 4706#ifdef CONFIG_X86_64
4707 var.base |= ((u64)base3) << 32;
4708#endif
2dafc6c2
GN		 4709 var.limit = get_desc_limit(desc);
4710 if (desc->g)
4711 var.limit = (var.limit << 12) | 0xfff;
4712 var.type = desc->type;
2dafc6c2
GN		 4713 var.dpl = desc->dpl;
4714 var.db = desc->d;
4715 var.s = desc->s;
4716 var.l = desc->l;
4717 var.g = desc->g;
4718 var.avl = desc->avl;
4719 var.present = desc->p;
4720 var.unusable = !var.present;
4721 var.padding = 0;
4722
4723 kvm_set_segment(vcpu, &var, seg);
4724 return;
4725}
4726
717746e3
AK		 4727static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4728 u32 msr_index, u64 *pdata)
4729{
609e36d3
PB		 4730 struct msr_data msr;
4731 int r;
4732
4733 msr.index = msr_index;
4734 msr.host_initiated = false;
4735 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4736 if (r)
4737 return r;
4738
4739 *pdata = msr.data;
4740 return 0;
717746e3
AK		 4741}
4742
4743static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4744 u32 msr_index, u64 data)
4745{
8fe8ab46
WA		 4746 struct msr_data msr;
4747
4748 msr.data = data;
4749 msr.index = msr_index;
4750 msr.host_initiated = false;
4751 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4752}
4753
64d60670
PB		 4754static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4755{
4756 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4757
4758 return vcpu->arch.smbase;
4759}
4760
4761static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4762{
4763 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4764
4765 vcpu->arch.smbase = smbase;
4766}
4767
67f4d428
NA		 4768static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4769 u32 pmc)
4770{
c6702c9d 4771 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4772}
4773
222d21aa
AK		 4774static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4775 u32 pmc, u64 *pdata)
4776{
c6702c9d 4777 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4778}
4779
6c3287f7
AK		 4780static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4781{
4782 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4783}
4784
5037f6f3
AK		 4785static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4786{
4787 preempt_disable();
5197b808 4788 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4789 /*
4790 * CR0.TS may reference the host fpu state, not the guest fpu state,
4791 * so it may be clear at this point.
4792 */
4793 clts();
4794}
4795
4796static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4797{
4798 preempt_enable();
4799}
4800
2953538e 4801static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4802 struct x86_instruction_info *info,
c4f035c6
AK		 4803 enum x86_intercept_stage stage)
4804{
2953538e 4805 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4806}
4807
0017f93a 4808static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4809 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4810{
0017f93a 4811 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4812}
4813
dd856efa
AK		 4814static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4815{
4816 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4817}
4818
4819static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4820{
4821 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4822}
4823
801806d9
NA		 4824static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4825{
4826 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4827}
4828
0225fb50 4829static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4830 .read_gpr = emulator_read_gpr,
4831 .write_gpr = emulator_write_gpr,
1871c602 4832 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4833 .write_std = kvm_write_guest_virt_system,
1871c602 4834 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4835 .read_emulated = emulator_read_emulated,
4836 .write_emulated = emulator_write_emulated,
4837 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4838 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4839 .pio_in_emulated = emulator_pio_in_emulated,
4840 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4841 .get_segment = emulator_get_segment,
4842 .set_segment = emulator_set_segment,
5951c442 4843 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4844 .get_gdt = emulator_get_gdt,
160ce1f1 4845 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4846 .set_gdt = emulator_set_gdt,
4847 .set_idt = emulator_set_idt,
52a46617
GN		 4848 .get_cr = emulator_get_cr,
4849 .set_cr = emulator_set_cr,
9c537244 4850 .cpl = emulator_get_cpl,
35aa5375
GN		 4851 .get_dr = emulator_get_dr,
4852 .set_dr = emulator_set_dr,
64d60670
PB		 4853 .get_smbase = emulator_get_smbase,
4854 .set_smbase = emulator_set_smbase,
717746e3
AK		 4855 .set_msr = emulator_set_msr,
4856 .get_msr = emulator_get_msr,
67f4d428 4857 .check_pmc = emulator_check_pmc,
222d21aa 4858 .read_pmc = emulator_read_pmc,
6c3287f7 4859 .halt = emulator_halt,
bcaf5cc5 4860 .wbinvd = emulator_wbinvd,
d6aa1000 4861 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4862 .get_fpu = emulator_get_fpu,
4863 .put_fpu = emulator_put_fpu,
c4f035c6 4864 .intercept = emulator_intercept,
bdb42f5a 4865 .get_cpuid = emulator_get_cpuid,
801806d9 4866 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4867};
4868
95cb2295
GN		 4869static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4870{
37ccdcbe 4871 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4872 /*
4873 * an sti; sti; sequence only disable interrupts for the first
4874 * instruction. So, if the last instruction, be it emulated or
4875 * not, left the system with the INT_STI flag enabled, it
4876 * means that the last instruction is an sti. We should not
4877 * leave the flag on in this case. The same goes for mov ss
4878 */
37ccdcbe
PB		 4879 if (int_shadow & mask)
4880 mask = 0;
6addfc42 4881 if (unlikely(int_shadow || mask)) {
95cb2295 4882 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4883 if (!mask)
4884 kvm_make_request(KVM_REQ_EVENT, vcpu);
4885 }
95cb2295
GN		 4886}
4887
ef54bcfe 4888static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4889{
4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4891 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4892 return kvm_propagate_fault(vcpu, &ctxt->exception);
4893
4894 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4895 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4896 ctxt->exception.error_code);
54b8486f 4897 else
da9cb575 4898 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4899 return false;
54b8486f
GN		 4900}
4901
8ec4722d
MG		 4902static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4903{
adf52235 4904 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4905 int cs_db, cs_l;
4906
8ec4722d
MG		 4907 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4908
adf52235
TY		 4909 ctxt->eflags = kvm_get_rflags(vcpu);
4910 ctxt->eip = kvm_rip_read(vcpu);
4911 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4912 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4913 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4914 cs_db ? X86EMUL_MODE_PROT32 :
4915 X86EMUL_MODE_PROT16;
a584539b 4916 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4917 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4918 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4919 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4920
dd856efa 4921 init_decode_cache(ctxt);
7ae441ea 4922 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4923}
4924
71f9833b 4925int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4926{
9d74191a 4927 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4928 int ret;
4929
4930 init_emulate_ctxt(vcpu);
4931
9dac77fa
AK		 4932 ctxt->op_bytes = 2;
4933 ctxt->ad_bytes = 2;
4934 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4935 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4936
4937 if (ret != X86EMUL_CONTINUE)
4938 return EMULATE_FAIL;
4939
9dac77fa 4940 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4941 kvm_rip_write(vcpu, ctxt->eip);
4942 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4943
4944 if (irq == NMI_VECTOR)
7460fb4a 4945 vcpu->arch.nmi_pending = 0;
63995653
MG		 4946 else
4947 vcpu->arch.interrupt.pending = false;
4948
4949 return EMULATE_DONE;
4950}
4951EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4952
6d77dbfc
GN		 4953static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4954{
fc3a9157
JR		 4955 int r = EMULATE_DONE;
4956
6d77dbfc
GN		 4957 ++vcpu->stat.insn_emulation_fail;
4958 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4959 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4960 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4961 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4962 vcpu->run->internal.ndata = 0;
4963 r = EMULATE_FAIL;
4964 }
6d77dbfc 4965 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4966
4967 return r;
6d77dbfc
GN		 4968}
4969
93c05d3e 4970static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4971 bool write_fault_to_shadow_pgtable,
4972 int emulation_type)
a6f177ef 4973{
95b3cf69 4974 gpa_t gpa = cr2;
8e3d9d06 4975 pfn_t pfn;
a6f177ef 4976
991eebf9
GN		 4977 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4978 return false;
4979
95b3cf69
XG		 4980 if (!vcpu->arch.mmu.direct_map) {
4981 /*
4982 * Write permission should be allowed since only
4983 * write access need to be emulated.
4984 */
4985 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4986
95b3cf69
XG		 4987 /*
4988 * If the mapping is invalid in guest, let cpu retry
4989 * it to generate fault.
4990 */
4991 if (gpa == UNMAPPED_GVA)
4992 return true;
4993 }
a6f177ef 4994
8e3d9d06
XG		 4995 /*
4996 * Do not retry the unhandleable instruction if it faults on the
4997 * readonly host memory, otherwise it will goto a infinite loop:
4998 * retry instruction -> write #PF -> emulation fail -> retry
4999 * instruction -> ...
5000 */
5001 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5002
5003 /*
5004 * If the instruction failed on the error pfn, it can not be fixed,
5005 * report the error to userspace.
5006 */
5007 if (is_error_noslot_pfn(pfn))
5008 return false;
5009
5010 kvm_release_pfn_clean(pfn);
5011
5012 /* The instructions are well-emulated on direct mmu. */
5013 if (vcpu->arch.mmu.direct_map) {
5014 unsigned int indirect_shadow_pages;
5015
5016 spin_lock(&vcpu->kvm->mmu_lock);
5017 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5018 spin_unlock(&vcpu->kvm->mmu_lock);
5019
5020 if (indirect_shadow_pages)
5021 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5022
a6f177ef 5023 return true;
8e3d9d06 5024 }
a6f177ef 5025
95b3cf69
XG		 5026 /*
5027 * if emulation was due to access to shadowed page table
5028 * and it failed try to unshadow page and re-enter the
5029 * guest to let CPU execute the instruction.
5030 */
5031 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5032
5033 /*
5034 * If the access faults on its page table, it can not
5035 * be fixed by unprotecting shadow page and it should
5036 * be reported to userspace.
5037 */
5038 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5039}
5040
1cb3f3ae
XG		 5041static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5042 unsigned long cr2, int emulation_type)
5043{
5044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5045 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5046
5047 last_retry_eip = vcpu->arch.last_retry_eip;
5048 last_retry_addr = vcpu->arch.last_retry_addr;
5049
5050 /*
5051 * If the emulation is caused by #PF and it is non-page_table
5052 * writing instruction, it means the VM-EXIT is caused by shadow
5053 * page protected, we can zap the shadow page and retry this
5054 * instruction directly.
5055 *
5056 * Note: if the guest uses a non-page-table modifying instruction
5057 * on the PDE that points to the instruction, then we will unmap
5058 * the instruction and go to an infinite loop. So, we cache the
5059 * last retried eip and the last fault address, if we meet the eip
5060 * and the address again, we can break out of the potential infinite
5061 * loop.
5062 */
5063 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5064
5065 if (!(emulation_type & EMULTYPE_RETRY))
5066 return false;
5067
5068 if (x86_page_table_writing_insn(ctxt))
5069 return false;
5070
5071 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5072 return false;
5073
5074 vcpu->arch.last_retry_eip = ctxt->eip;
5075 vcpu->arch.last_retry_addr = cr2;
5076
5077 if (!vcpu->arch.mmu.direct_map)
5078 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5079
22368028 5080 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5081
5082 return true;
5083}
5084
716d51ab
GN		 5085static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5086static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5087
64d60670 5088static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5089{
64d60670 5090 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5091 /* This is a good place to trace that we are exiting SMM. */
5092 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5093
64d60670
PB		 5094 if (unlikely(vcpu->arch.smi_pending)) {
5095 kvm_make_request(KVM_REQ_SMI, vcpu);
5096 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5097 } else {
5098 /* Process a latched INIT, if any. */
5099 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5100 }
5101 }
699023e2
PB		 5102
5103 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5104}
5105
5106static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5107{
5108 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5109
a584539b 5110 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5111
5112 if (changed & HF_SMM_MASK)
5113 kvm_smm_changed(vcpu);
a584539b
PB		 5114}
5115
4a1e10d5
PB		 5116static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5117 unsigned long *db)
5118{
5119 u32 dr6 = 0;
5120 int i;
5121 u32 enable, rwlen;
5122
5123 enable = dr7;
5124 rwlen = dr7 >> 16;
5125 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5126 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5127 dr6 |= (1 << i);
5128 return dr6;
5129}
5130
6addfc42 5131static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5132{
5133 struct kvm_run *kvm_run = vcpu->run;
5134
5135 /*
6addfc42
PB		 5136 * rflags is the old, "raw" value of the flags. The new value has
5137 * not been saved yet.
663f4c61
PB		 5138 *
5139 * This is correct even for TF set by the guest, because "the
5140 * processor will not generate this exception after the instruction
5141 * that sets the TF flag".
5142 */
663f4c61
PB		 5143 if (unlikely(rflags & X86_EFLAGS_TF)) {
5144 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5145 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5146 DR6_RTM;
663f4c61
PB		 5147 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5148 kvm_run->debug.arch.exception = DB_VECTOR;
5149 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5150 *r = EMULATE_USER_EXIT;
5151 } else {
5152 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5153 /*
5154 * "Certain debug exceptions may clear bit 0-3. The
5155 * remaining contents of the DR6 register are never
5156 * cleared by the processor".
5157 */
5158 vcpu->arch.dr6 &= ~15;
6f43ed01 5159 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5160 kvm_queue_exception(vcpu, DB_VECTOR);
5161 }
5162 }
5163}
5164
4a1e10d5
PB		 5165static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5166{
4a1e10d5
PB		 5167 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5168 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5169 struct kvm_run *kvm_run = vcpu->run;
5170 unsigned long eip = kvm_get_linear_rip(vcpu);
5171 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5172 vcpu->arch.guest_debug_dr7,
5173 vcpu->arch.eff_db);
5174
5175 if (dr6 != 0) {
6f43ed01 5176 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5177 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5178 kvm_run->debug.arch.exception = DB_VECTOR;
5179 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5180 *r = EMULATE_USER_EXIT;
5181 return true;
5182 }
5183 }
5184
4161a569
NA		 5185 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5186 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5187 unsigned long eip = kvm_get_linear_rip(vcpu);
5188 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5189 vcpu->arch.dr7,
5190 vcpu->arch.db);
5191
5192 if (dr6 != 0) {
5193 vcpu->arch.dr6 &= ~15;
6f43ed01 5194 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5195 kvm_queue_exception(vcpu, DB_VECTOR);
5196 *r = EMULATE_DONE;
5197 return true;
5198 }
5199 }
5200
5201 return false;
5202}
5203
51d8b661
AP		 5204int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5205 unsigned long cr2,
dc25e89e
AP		 5206 int emulation_type,
5207 void *insn,
5208 int insn_len)
bbd9b64e 5209{
95cb2295 5210 int r;
9d74191a 5211 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5212 bool writeback = true;
93c05d3e 5213 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5214
93c05d3e
XG		 5215 /*
5216 * Clear write_fault_to_shadow_pgtable here to ensure it is
5217 * never reused.
5218 */
5219 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5220 kvm_clear_exception_queue(vcpu);
8d7d8102 5221
571008da 5222 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5223 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5224
5225 /*
5226 * We will reenter on the same instruction since
5227 * we do not set complete_userspace_io. This does not
5228 * handle watchpoints yet, those would be handled in
5229 * the emulate_ops.
5230 */
5231 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5232 return r;
5233
9d74191a
TY		 5234 ctxt->interruptibility = 0;
5235 ctxt->have_exception = false;
e0ad0b47 5236 ctxt->exception.vector = -1;
9d74191a 5237 ctxt->perm_ok = false;
bbd9b64e 5238
b51e974f 5239 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5240
9d74191a 5241 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5242
e46479f8 5243 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5244 ++vcpu->stat.insn_emulation;
1d2887e2 5245 if (r != EMULATION_OK) {
4005996e
AK		 5246 if (emulation_type & EMULTYPE_TRAP_UD)
5247 return EMULATE_FAIL;
991eebf9
GN		 5248 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5249 emulation_type))
bbd9b64e 5250 return EMULATE_DONE;
6d77dbfc
GN		 5251 if (emulation_type & EMULTYPE_SKIP)
5252 return EMULATE_FAIL;
5253 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5254 }
5255 }
5256
ba8afb6b 5257 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5258 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5259 if (ctxt->eflags & X86_EFLAGS_RF)
5260 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5261 return EMULATE_DONE;
5262 }
5263
1cb3f3ae
XG		 5264 if (retry_instruction(ctxt, cr2, emulation_type))
5265 return EMULATE_DONE;
5266
7ae441ea 5267 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5268 changes registers values during IO operation */
7ae441ea
GN		 5269 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5270 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5271 emulator_invalidate_register_cache(ctxt);
7ae441ea 5272 }
4d2179e1 5273
5cd21917 5274restart:
9d74191a 5275 r = x86_emulate_insn(ctxt);
bbd9b64e 5276
775fde86
JR		 5277 if (r == EMULATION_INTERCEPTED)
5278 return EMULATE_DONE;
5279
d2ddd1c4 5280 if (r == EMULATION_FAILED) {
991eebf9
GN		 5281 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5282 emulation_type))
c3cd7ffa
GN		 5283 return EMULATE_DONE;
5284
6d77dbfc 5285 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5286 }
5287
9d74191a 5288 if (ctxt->have_exception) {
d2ddd1c4 5289 r = EMULATE_DONE;
ef54bcfe
PB		 5290 if (inject_emulated_exception(vcpu))
5291 return r;
d2ddd1c4 5292 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5293 if (!vcpu->arch.pio.in) {
5294 /* FIXME: return into emulator if single-stepping. */
3457e419 5295 vcpu->arch.pio.count = 0;
0912c977 5296 } else {
7ae441ea 5297 writeback = false;
716d51ab
GN		 5298 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5299 }
ac0a48c3 5300 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5301 } else if (vcpu->mmio_needed) {
5302 if (!vcpu->mmio_is_write)
5303 writeback = false;
ac0a48c3 5304 r = EMULATE_USER_EXIT;
716d51ab 5305 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5306 } else if (r == EMULATION_RESTART)
5cd21917 5307 goto restart;
d2ddd1c4
GN		 5308 else
5309 r = EMULATE_DONE;
f850e2e6 5310
7ae441ea 5311 if (writeback) {
6addfc42 5312 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5313 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5314 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5315 if (vcpu->arch.hflags != ctxt->emul_flags)
5316 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5317 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5318 if (r == EMULATE_DONE)
6addfc42 5319 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5320 if (!ctxt->have_exception ||
5321 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5322 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5323
5324 /*
5325 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5326 * do nothing, and it will be requested again as soon as
5327 * the shadow expires. But we still need to check here,
5328 * because POPF has no interrupt shadow.
5329 */
5330 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5331 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5332 } else
5333 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5334
5335 return r;
de7d789a 5336}
51d8b661 5337EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5338
cf8f70bf 5339int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5340{
cf8f70bf 5341 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5342 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5343 size, port, &val, 1);
cf8f70bf 5344 /* do not return to emulator after return from userspace */
7972995b 5345 vcpu->arch.pio.count = 0;
de7d789a
CO		 5346 return ret;
5347}
cf8f70bf 5348EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5349
8cfdc000
ZA		 5350static void tsc_bad(void *info)
5351{
0a3aee0d 5352 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5353}
5354
5355static void tsc_khz_changed(void *data)
c8076604 5356{
8cfdc000
ZA		 5357 struct cpufreq_freqs *freq = data;
5358 unsigned long khz = 0;
5359
5360 if (data)
5361 khz = freq->new;
5362 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5363 khz = cpufreq_quick_get(raw_smp_processor_id());
5364 if (!khz)
5365 khz = tsc_khz;
0a3aee0d 5366 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5367}
5368
c8076604
GH		 5369static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5370 void *data)
5371{
5372 struct cpufreq_freqs *freq = data;
5373 struct kvm *kvm;
5374 struct kvm_vcpu *vcpu;
5375 int i, send_ipi = 0;
5376
8cfdc000
ZA		 5377 /*
5378 * We allow guests to temporarily run on slowing clocks,
5379 * provided we notify them after, or to run on accelerating
5380 * clocks, provided we notify them before. Thus time never
5381 * goes backwards.
5382 *
5383 * However, we have a problem. We can't atomically update
5384 * the frequency of a given CPU from this function; it is
5385 * merely a notifier, which can be called from any CPU.
5386 * Changing the TSC frequency at arbitrary points in time
5387 * requires a recomputation of local variables related to
5388 * the TSC for each VCPU. We must flag these local variables
5389 * to be updated and be sure the update takes place with the
5390 * new frequency before any guests proceed.
5391 *
5392 * Unfortunately, the combination of hotplug CPU and frequency
5393 * change creates an intractable locking scenario; the order
5394 * of when these callouts happen is undefined with respect to
5395 * CPU hotplug, and they can race with each other. As such,
5396 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5397 * undefined; you can actually have a CPU frequency change take
5398 * place in between the computation of X and the setting of the
5399 * variable. To protect against this problem, all updates of
5400 * the per_cpu tsc_khz variable are done in an interrupt
5401 * protected IPI, and all callers wishing to update the value
5402 * must wait for a synchronous IPI to complete (which is trivial
5403 * if the caller is on the CPU already). This establishes the
5404 * necessary total order on variable updates.
5405 *
5406 * Note that because a guest time update may take place
5407 * anytime after the setting of the VCPU's request bit, the
5408 * correct TSC value must be set before the request. However,
5409 * to ensure the update actually makes it to any guest which
5410 * starts running in hardware virtualization between the set
5411 * and the acquisition of the spinlock, we must also ping the
5412 * CPU after setting the request bit.
5413 *
5414 */
5415
c8076604
GH		 5416 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5417 return 0;
5418 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5419 return 0;
8cfdc000
ZA		 5420
5421 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5422
2f303b74 5423 spin_lock(&kvm_lock);
c8076604 5424 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5425 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5426 if (vcpu->cpu != freq->cpu)
5427 continue;
c285545f 5428 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5429 if (vcpu->cpu != smp_processor_id())
8cfdc000 5430 send_ipi = 1;
c8076604
GH		 5431 }
5432 }
2f303b74 5433 spin_unlock(&kvm_lock);
c8076604
GH		 5434
5435 if (freq->old < freq->new && send_ipi) {
5436 /*
5437 * We upscale the frequency. Must make the guest
5438 * doesn't see old kvmclock values while running with
5439 * the new frequency, otherwise we risk the guest sees
5440 * time go backwards.
5441 *
5442 * In case we update the frequency for another cpu
5443 * (which might be in guest context) send an interrupt
5444 * to kick the cpu out of guest context. Next time
5445 * guest context is entered kvmclock will be updated,
5446 * so the guest will not see stale values.
5447 */
8cfdc000 5448 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5449 }
5450 return 0;
5451}
5452
5453static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5454 .notifier_call = kvmclock_cpufreq_notifier
5455};
5456
5457static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5458 unsigned long action, void *hcpu)
5459{
5460 unsigned int cpu = (unsigned long)hcpu;
5461
5462 switch (action) {
5463 case CPU_ONLINE:
5464 case CPU_DOWN_FAILED:
5465 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5466 break;
5467 case CPU_DOWN_PREPARE:
5468 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5469 break;
5470 }
5471 return NOTIFY_OK;
5472}
5473
5474static struct notifier_block kvmclock_cpu_notifier_block = {
5475 .notifier_call = kvmclock_cpu_notifier,
5476 .priority = -INT_MAX
c8076604
GH		 5477};
5478
b820cc0c
ZA		 5479static void kvm_timer_init(void)
5480{
5481 int cpu;
5482
c285545f 5483 max_tsc_khz = tsc_khz;
460dd42e
SB		 5484
5485 cpu_notifier_register_begin();
b820cc0c 5486 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5487#ifdef CONFIG_CPU_FREQ
5488 struct cpufreq_policy policy;
5489 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5490 cpu = get_cpu();
5491 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5492 if (policy.cpuinfo.max_freq)
5493 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5494 put_cpu();
c285545f 5495#endif
b820cc0c
ZA		 5496 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5497 CPUFREQ_TRANSITION_NOTIFIER);
5498 }
c285545f 5499 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5500 for_each_online_cpu(cpu)
5501 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5502
5503 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5504 cpu_notifier_register_done();
5505
b820cc0c
ZA		 5506}
5507
ff9d07a0
ZY		 5508static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5509
f5132b01 5510int kvm_is_in_guest(void)
ff9d07a0 5511{
086c9855 5512 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5513}
5514
5515static int kvm_is_user_mode(void)
5516{
5517 int user_mode = 3;
dcf46b94 5518
086c9855
AS		 5519 if (__this_cpu_read(current_vcpu))
5520 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5521
ff9d07a0
ZY		 5522 return user_mode != 0;
5523}
5524
5525static unsigned long kvm_get_guest_ip(void)
5526{
5527 unsigned long ip = 0;
dcf46b94 5528
086c9855
AS		 5529 if (__this_cpu_read(current_vcpu))
5530 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5531
ff9d07a0
ZY		 5532 return ip;
5533}
5534
5535static struct perf_guest_info_callbacks kvm_guest_cbs = {
5536 .is_in_guest = kvm_is_in_guest,
5537 .is_user_mode = kvm_is_user_mode,
5538 .get_guest_ip = kvm_get_guest_ip,
5539};
5540
5541void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5542{
086c9855 5543 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5544}
5545EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5546
5547void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5548{
086c9855 5549 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5550}
5551EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5552
ce88decf
XG		 5553static void kvm_set_mmio_spte_mask(void)
5554{
5555 u64 mask;
5556 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5557
5558 /*
5559 * Set the reserved bits and the present bit of an paging-structure
5560 * entry to generate page fault with PFER.RSV = 1.
5561 */
885032b9 5562 /* Mask the reserved physical address bits. */
d1431483 5563 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5564
5565 /* Bit 62 is always reserved for 32bit host. */
5566 mask |= 0x3ull << 62;
5567
5568 /* Set the present bit. */
ce88decf
XG		 5569 mask |= 1ull;
5570
5571#ifdef CONFIG_X86_64
5572 /*
5573 * If reserved bit is not supported, clear the present bit to disable
5574 * mmio page fault.
5575 */
5576 if (maxphyaddr == 52)
5577 mask &= ~1ull;
5578#endif
5579
5580 kvm_mmu_set_mmio_spte_mask(mask);
5581}
5582
16e8d74d
MT		 5583#ifdef CONFIG_X86_64
5584static void pvclock_gtod_update_fn(struct work_struct *work)
5585{
d828199e
MT		 5586 struct kvm *kvm;
5587
5588 struct kvm_vcpu *vcpu;
5589 int i;
5590
2f303b74 5591 spin_lock(&kvm_lock);
d828199e
MT		 5592 list_for_each_entry(kvm, &vm_list, vm_list)
5593 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5594 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5595 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5596 spin_unlock(&kvm_lock);
16e8d74d
MT		 5597}
5598
5599static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5600
5601/*
5602 * Notification about pvclock gtod data update.
5603 */
5604static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5605 void *priv)
5606{
5607 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5608 struct timekeeper *tk = priv;
5609
5610 update_pvclock_gtod(tk);
5611
5612 /* disable master clock if host does not trust, or does not
5613 * use, TSC clocksource
5614 */
5615 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5616 atomic_read(&kvm_guest_has_master_clock) != 0)
5617 queue_work(system_long_wq, &pvclock_gtod_work);
5618
5619 return 0;
5620}
5621
5622static struct notifier_block pvclock_gtod_notifier = {
5623 .notifier_call = pvclock_gtod_notify,
5624};
5625#endif
5626
f8c16bba 5627int kvm_arch_init(void *opaque)
043405e1 5628{
b820cc0c 5629 int r;
6b61edf7 5630 struct kvm_x86_ops *ops = opaque;
f8c16bba 5631
f8c16bba
ZX		 5632 if (kvm_x86_ops) {
5633 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5634 r = -EEXIST;
5635 goto out;
f8c16bba
ZX		 5636 }
5637
5638 if (!ops->cpu_has_kvm_support()) {
5639 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5640 r = -EOPNOTSUPP;
5641 goto out;
f8c16bba
ZX		 5642 }
5643 if (ops->disabled_by_bios()) {
5644 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5645 r = -EOPNOTSUPP;
5646 goto out;
f8c16bba
ZX		 5647 }
5648
013f6a5d
MT		 5649 r = -ENOMEM;
5650 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5651 if (!shared_msrs) {
5652 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5653 goto out;
5654 }
5655
97db56ce
AK		 5656 r = kvm_mmu_module_init();
5657 if (r)
013f6a5d 5658 goto out_free_percpu;
97db56ce 5659
ce88decf 5660 kvm_set_mmio_spte_mask();
97db56ce 5661
f8c16bba 5662 kvm_x86_ops = ops;
920c8377 5663
7b52345e 5664 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5665 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5666
b820cc0c 5667 kvm_timer_init();
c8076604 5668
ff9d07a0
ZY		 5669 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5670
2acf923e
DC		 5671 if (cpu_has_xsave)
5672 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5673
c5cc421b 5674 kvm_lapic_init();
16e8d74d
MT		 5675#ifdef CONFIG_X86_64
5676 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5677#endif
5678
f8c16bba 5679 return 0;
56c6d28a 5680
013f6a5d
MT		 5681out_free_percpu:
5682 free_percpu(shared_msrs);
56c6d28a 5683out:
56c6d28a 5684 return r;
043405e1 5685}
8776e519 5686
f8c16bba
ZX		 5687void kvm_arch_exit(void)
5688{
ff9d07a0
ZY		 5689 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5690
888d256e
JK		 5691 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5692 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5693 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5694 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5695#ifdef CONFIG_X86_64
5696 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5697#endif
f8c16bba 5698 kvm_x86_ops = NULL;
56c6d28a 5699 kvm_mmu_module_exit();
013f6a5d 5700 free_percpu(shared_msrs);
56c6d28a 5701}
f8c16bba 5702
5cb56059 5703int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5704{
5705 ++vcpu->stat.halt_exits;
35754c98 5706 if (lapic_in_kernel(vcpu)) {
a4535290 5707 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5708 return 1;
5709 } else {
5710 vcpu->run->exit_reason = KVM_EXIT_HLT;
5711 return 0;
5712 }
5713}
5cb56059
JS		 5714EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5715
5716int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5717{
5718 kvm_x86_ops->skip_emulated_instruction(vcpu);
5719 return kvm_vcpu_halt(vcpu);
5720}
8776e519
HB		 5721EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5722
6aef266c
SV		 5723/*
5724 * kvm_pv_kick_cpu_op: Kick a vcpu.
5725 *
5726 * @apicid - apicid of vcpu to be kicked.
5727 */
5728static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5729{
24d2166b 5730 struct kvm_lapic_irq lapic_irq;
6aef266c 5731
24d2166b
R		 5732 lapic_irq.shorthand = 0;
5733 lapic_irq.dest_mode = 0;
5734 lapic_irq.dest_id = apicid;
93bbf0b8 5735 lapic_irq.msi_redir_hint = false;
6aef266c 5736
24d2166b 5737 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5738 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5739}
5740
8776e519
HB		 5741int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5742{
5743 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5744 int op_64_bit, r = 1;
8776e519 5745
5cb56059
JS		 5746 kvm_x86_ops->skip_emulated_instruction(vcpu);
5747
55cd8e5a
GN		 5748 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5749 return kvm_hv_hypercall(vcpu);
5750
5fdbf976
MT		 5751 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5752 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5753 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5756
229456fc 5757 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5758
a449c7aa
NA		 5759 op_64_bit = is_64_bit_mode(vcpu);
5760 if (!op_64_bit) {
8776e519
HB		 5761 nr &= 0xFFFFFFFF;
5762 a0 &= 0xFFFFFFFF;
5763 a1 &= 0xFFFFFFFF;
5764 a2 &= 0xFFFFFFFF;
5765 a3 &= 0xFFFFFFFF;
5766 }
5767
07708c4a
JK		 5768 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5769 ret = -KVM_EPERM;
5770 goto out;
5771 }
5772
8776e519 5773 switch (nr) {
b93463aa
AK		 5774 case KVM_HC_VAPIC_POLL_IRQ:
5775 ret = 0;
5776 break;
6aef266c
SV		 5777 case KVM_HC_KICK_CPU:
5778 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5779 ret = 0;
5780 break;
8776e519
HB		 5781 default:
5782 ret = -KVM_ENOSYS;
5783 break;
5784 }
07708c4a 5785out:
a449c7aa
NA		 5786 if (!op_64_bit)
5787 ret = (u32)ret;
5fdbf976 5788 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5789 ++vcpu->stat.hypercalls;
2f333bcb 5790 return r;
8776e519
HB		 5791}
5792EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5793
b6785def 5794static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5795{
d6aa1000 5796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5797 char instruction[3];
5fdbf976 5798 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5799
8776e519 5800 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5801
9d74191a 5802 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5803}
5804
b6c7a5dc
HB		 5805/*
5806 * Check if userspace requested an interrupt window, and that the
5807 * interrupt window is open.
5808 *
5809 * No need to exit to userspace if we already have an interrupt queued.
5810 */
851ba692 5811static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5812{
1c1a9ce9
SR		 5813 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5814 return false;
5815
5816 if (kvm_cpu_has_interrupt(vcpu))
5817 return false;
5818
5819 return (irqchip_split(vcpu->kvm)
5820 ? kvm_apic_accept_pic_intr(vcpu)
5821 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5822}
5823
851ba692 5824static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5825{
851ba692
AK		 5826 struct kvm_run *kvm_run = vcpu->run;
5827
91586a3b 5828 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5829 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5830 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5831 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5832 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5833 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5834 kvm_arch_interrupt_allowed(vcpu) &&
5835 !kvm_cpu_has_interrupt(vcpu) &&
5836 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5837 else if (!pic_in_kernel(vcpu->kvm))
5838 kvm_run->ready_for_interrupt_injection =
5839 kvm_apic_accept_pic_intr(vcpu) &&
5840 !kvm_cpu_has_interrupt(vcpu);
5841 else
5842 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5843}
5844
95ba8273
GN		 5845static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5846{
5847 int max_irr, tpr;
5848
5849 if (!kvm_x86_ops->update_cr8_intercept)
5850 return;
5851
88c808fd
AK		 5852 if (!vcpu->arch.apic)
5853 return;
5854
8db3baa2
GN		 5855 if (!vcpu->arch.apic->vapic_addr)
5856 max_irr = kvm_lapic_find_highest_irr(vcpu);
5857 else
5858 max_irr = -1;
95ba8273
GN		 5859
5860 if (max_irr != -1)
5861 max_irr >>= 4;
5862
5863 tpr = kvm_lapic_get_cr8(vcpu);
5864
5865 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5866}
5867
b6b8a145 5868static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5869{
b6b8a145
JK		 5870 int r;
5871
95ba8273 5872 /* try to reinject previous events if any */
b59bb7bd 5873 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5874 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5875 vcpu->arch.exception.has_error_code,
5876 vcpu->arch.exception.error_code);
d6e8c854
NA		 5877
5878 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5879 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5880 X86_EFLAGS_RF);
5881
6bdf0662
NA		 5882 if (vcpu->arch.exception.nr == DB_VECTOR &&
5883 (vcpu->arch.dr7 & DR7_GD)) {
5884 vcpu->arch.dr7 &= ~DR7_GD;
5885 kvm_update_dr7(vcpu);
5886 }
5887
b59bb7bd
GN		 5888 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5889 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5890 vcpu->arch.exception.error_code,
5891 vcpu->arch.exception.reinject);
b6b8a145 5892 return 0;
b59bb7bd
GN		 5893 }
5894
95ba8273
GN		 5895 if (vcpu->arch.nmi_injected) {
5896 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5897 return 0;
95ba8273
GN		 5898 }
5899
5900 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5901 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5902 return 0;
5903 }
5904
5905 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5906 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5907 if (r != 0)
5908 return r;
95ba8273
GN		 5909 }
5910
5911 /* try to inject new event if pending */
5912 if (vcpu->arch.nmi_pending) {
5913 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5914 --vcpu->arch.nmi_pending;
95ba8273
GN		 5915 vcpu->arch.nmi_injected = true;
5916 kvm_x86_ops->set_nmi(vcpu);
5917 }
c7c9c56c 5918 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5919 /*
5920 * Because interrupts can be injected asynchronously, we are
5921 * calling check_nested_events again here to avoid a race condition.
5922 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5923 * proposal and current concerns. Perhaps we should be setting
5924 * KVM_REQ_EVENT only on certain events and not unconditionally?
5925 */
5926 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5927 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5928 if (r != 0)
5929 return r;
5930 }
95ba8273 5931 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5932 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5933 false);
5934 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5935 }
5936 }
b6b8a145 5937 return 0;
95ba8273
GN		 5938}
5939
7460fb4a
AK		 5940static void process_nmi(struct kvm_vcpu *vcpu)
5941{
5942 unsigned limit = 2;
5943
5944 /*
5945 * x86 is limited to one NMI running, and one NMI pending after it.
5946 * If an NMI is already in progress, limit further NMIs to just one.
5947 * Otherwise, allow two (and we'll inject the first one immediately).
5948 */
5949 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5950 limit = 1;
5951
5952 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5953 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5954 kvm_make_request(KVM_REQ_EVENT, vcpu);
5955}
5956
660a5d51
PB		 5957#define put_smstate(type, buf, offset, val) \
5958 *(type *)((buf) + (offset) - 0x7e00) = val
5959
5960static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5961{
5962 u32 flags = 0;
5963 flags |= seg->g << 23;
5964 flags |= seg->db << 22;
5965 flags |= seg->l << 21;
5966 flags |= seg->avl << 20;
5967 flags |= seg->present << 15;
5968 flags |= seg->dpl << 13;
5969 flags |= seg->s << 12;
5970 flags |= seg->type << 8;
5971 return flags;
5972}
5973
5974static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5975{
5976 struct kvm_segment seg;
5977 int offset;
5978
5979 kvm_get_segment(vcpu, &seg, n);
5980 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5981
5982 if (n < 3)
5983 offset = 0x7f84 + n * 12;
5984 else
5985 offset = 0x7f2c + (n - 3) * 12;
5986
5987 put_smstate(u32, buf, offset + 8, seg.base);
5988 put_smstate(u32, buf, offset + 4, seg.limit);
5989 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5990}
5991
efbb288a 5992#ifdef CONFIG_X86_64
660a5d51
PB		 5993static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5994{
5995 struct kvm_segment seg;
5996 int offset;
5997 u16 flags;
5998
5999 kvm_get_segment(vcpu, &seg, n);
6000 offset = 0x7e00 + n * 16;
6001
6002 flags = process_smi_get_segment_flags(&seg) >> 8;
6003 put_smstate(u16, buf, offset, seg.selector);
6004 put_smstate(u16, buf, offset + 2, flags);
6005 put_smstate(u32, buf, offset + 4, seg.limit);
6006 put_smstate(u64, buf, offset + 8, seg.base);
6007}
efbb288a 6008#endif
660a5d51
PB		 6009
6010static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6011{
6012 struct desc_ptr dt;
6013 struct kvm_segment seg;
6014 unsigned long val;
6015 int i;
6016
6017 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6018 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6019 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6020 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6021
6022 for (i = 0; i < 8; i++)
6023 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6024
6025 kvm_get_dr(vcpu, 6, &val);
6026 put_smstate(u32, buf, 0x7fcc, (u32)val);
6027 kvm_get_dr(vcpu, 7, &val);
6028 put_smstate(u32, buf, 0x7fc8, (u32)val);
6029
6030 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6031 put_smstate(u32, buf, 0x7fc4, seg.selector);
6032 put_smstate(u32, buf, 0x7f64, seg.base);
6033 put_smstate(u32, buf, 0x7f60, seg.limit);
6034 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6035
6036 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6037 put_smstate(u32, buf, 0x7fc0, seg.selector);
6038 put_smstate(u32, buf, 0x7f80, seg.base);
6039 put_smstate(u32, buf, 0x7f7c, seg.limit);
6040 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6041
6042 kvm_x86_ops->get_gdt(vcpu, &dt);
6043 put_smstate(u32, buf, 0x7f74, dt.address);
6044 put_smstate(u32, buf, 0x7f70, dt.size);
6045
6046 kvm_x86_ops->get_idt(vcpu, &dt);
6047 put_smstate(u32, buf, 0x7f58, dt.address);
6048 put_smstate(u32, buf, 0x7f54, dt.size);
6049
6050 for (i = 0; i < 6; i++)
6051 process_smi_save_seg_32(vcpu, buf, i);
6052
6053 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6054
6055 /* revision id */
6056 put_smstate(u32, buf, 0x7efc, 0x00020000);
6057 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6058}
6059
6060static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6061{
6062#ifdef CONFIG_X86_64
6063 struct desc_ptr dt;
6064 struct kvm_segment seg;
6065 unsigned long val;
6066 int i;
6067
6068 for (i = 0; i < 16; i++)
6069 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6070
6071 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6072 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6073
6074 kvm_get_dr(vcpu, 6, &val);
6075 put_smstate(u64, buf, 0x7f68, val);
6076 kvm_get_dr(vcpu, 7, &val);
6077 put_smstate(u64, buf, 0x7f60, val);
6078
6079 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6080 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6081 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6082
6083 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6084
6085 /* revision id */
6086 put_smstate(u32, buf, 0x7efc, 0x00020064);
6087
6088 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6089
6090 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6091 put_smstate(u16, buf, 0x7e90, seg.selector);
6092 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6093 put_smstate(u32, buf, 0x7e94, seg.limit);
6094 put_smstate(u64, buf, 0x7e98, seg.base);
6095
6096 kvm_x86_ops->get_idt(vcpu, &dt);
6097 put_smstate(u32, buf, 0x7e84, dt.size);
6098 put_smstate(u64, buf, 0x7e88, dt.address);
6099
6100 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6101 put_smstate(u16, buf, 0x7e70, seg.selector);
6102 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6103 put_smstate(u32, buf, 0x7e74, seg.limit);
6104 put_smstate(u64, buf, 0x7e78, seg.base);
6105
6106 kvm_x86_ops->get_gdt(vcpu, &dt);
6107 put_smstate(u32, buf, 0x7e64, dt.size);
6108 put_smstate(u64, buf, 0x7e68, dt.address);
6109
6110 for (i = 0; i < 6; i++)
6111 process_smi_save_seg_64(vcpu, buf, i);
6112#else
6113 WARN_ON_ONCE(1);
6114#endif
6115}
6116
64d60670
PB		 6117static void process_smi(struct kvm_vcpu *vcpu)
6118{
660a5d51 6119 struct kvm_segment cs, ds;
18c3626e 6120 struct desc_ptr dt;
660a5d51
PB		 6121 char buf[512];
6122 u32 cr0;
6123
64d60670
PB		 6124 if (is_smm(vcpu)) {
6125 vcpu->arch.smi_pending = true;
6126 return;
6127 }
6128
660a5d51
PB		 6129 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6130 vcpu->arch.hflags |= HF_SMM_MASK;
6131 memset(buf, 0, 512);
6132 if (guest_cpuid_has_longmode(vcpu))
6133 process_smi_save_state_64(vcpu, buf);
6134 else
6135 process_smi_save_state_32(vcpu, buf);
6136
54bf36aa 6137 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6138
6139 if (kvm_x86_ops->get_nmi_mask(vcpu))
6140 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6141 else
6142 kvm_x86_ops->set_nmi_mask(vcpu, true);
6143
6144 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6145 kvm_rip_write(vcpu, 0x8000);
6146
6147 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6148 kvm_x86_ops->set_cr0(vcpu, cr0);
6149 vcpu->arch.cr0 = cr0;
6150
6151 kvm_x86_ops->set_cr4(vcpu, 0);
6152
18c3626e
PB		 6153 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6154 dt.address = dt.size = 0;
6155 kvm_x86_ops->set_idt(vcpu, &dt);
6156
660a5d51
PB		 6157 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6158
6159 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6160 cs.base = vcpu->arch.smbase;
6161
6162 ds.selector = 0;
6163 ds.base = 0;
6164
6165 cs.limit = ds.limit = 0xffffffff;
6166 cs.type = ds.type = 0x3;
6167 cs.dpl = ds.dpl = 0;
6168 cs.db = ds.db = 0;
6169 cs.s = ds.s = 1;
6170 cs.l = ds.l = 0;
6171 cs.g = ds.g = 1;
6172 cs.avl = ds.avl = 0;
6173 cs.present = ds.present = 1;
6174 cs.unusable = ds.unusable = 0;
6175 cs.padding = ds.padding = 0;
6176
6177 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6178 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6182 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6183
6184 if (guest_cpuid_has_longmode(vcpu))
6185 kvm_x86_ops->set_efer(vcpu, 0);
6186
6187 kvm_update_cpuid(vcpu);
6188 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6189}
6190
3d81bc7e 6191static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6192{
3d81bc7e
YZ		 6193 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6194 return;
c7c9c56c 6195
3bb345f3 6196 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6197
b053b2ae
SR		 6198 if (irqchip_split(vcpu->kvm))
6199 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6200 else
6201 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
3bb345f3 6202 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6203}
6204
a70656b6
RK		 6205static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6206{
6207 ++vcpu->stat.tlb_flush;
6208 kvm_x86_ops->tlb_flush(vcpu);
6209}
6210
4256f43f
TC		 6211void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6212{
c24ae0dc
TC		 6213 struct page *page = NULL;
6214
35754c98 6215 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6216 return;
6217
4256f43f
TC		 6218 if (!kvm_x86_ops->set_apic_access_page_addr)
6219 return;
6220
c24ae0dc 6221 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6222 if (is_error_page(page))
6223 return;
c24ae0dc
TC		 6224 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6225
6226 /*
6227 * Do not pin apic access page in memory, the MMU notifier
6228 * will call us again if it is migrated or swapped out.
6229 */
6230 put_page(page);
4256f43f
TC		 6231}
6232EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6233
fe71557a
TC		 6234void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6235 unsigned long address)
6236{
c24ae0dc
TC		 6237 /*
6238 * The physical address of apic access page is stored in the VMCS.
6239 * Update it when it becomes invalid.
6240 */
6241 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6242 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6243}
6244
9357d939 6245/*
362c698f 6246 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6247 * exiting to the userspace. Otherwise, the value will be returned to the
6248 * userspace.
6249 */
851ba692 6250static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6251{
6252 int r;
35754c98 6253 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6254 vcpu->run->request_interrupt_window;
730dca42 6255 bool req_immediate_exit = false;
b6c7a5dc 6256
3e007509 6257 if (vcpu->requests) {
a8eeb04a 6258 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6259 kvm_mmu_unload(vcpu);
a8eeb04a 6260 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6261 __kvm_migrate_timers(vcpu);
d828199e
MT		 6262 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6263 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6264 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6265 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6266 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6267 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6268 if (unlikely(r))
6269 goto out;
6270 }
a8eeb04a 6271 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6272 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6273 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6274 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6275 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6276 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6277 r = 0;
6278 goto out;
6279 }
a8eeb04a 6280 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6281 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6282 r = 0;
6283 goto out;
6284 }
a8eeb04a 6285 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6286 vcpu->fpu_active = 0;
6287 kvm_x86_ops->fpu_deactivate(vcpu);
6288 }
af585b92
GN		 6289 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6290 /* Page is swapped out. Do synthetic halt */
6291 vcpu->arch.apf.halted = true;
6292 r = 1;
6293 goto out;
6294 }
c9aaa895
GC		 6295 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6296 record_steal_time(vcpu);
64d60670
PB		 6297 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6298 process_smi(vcpu);
7460fb4a
AK		 6299 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6300 process_nmi(vcpu);
f5132b01 6301 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6302 kvm_pmu_handle_event(vcpu);
f5132b01 6303 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6304 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6305 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6306 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6307 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308 (void *) vcpu->arch.eoi_exit_bitmap)) {
6309 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6310 vcpu->run->eoi.vector =
6311 vcpu->arch.pending_ioapic_eoi;
6312 r = 0;
6313 goto out;
6314 }
6315 }
3d81bc7e
YZ		 6316 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6317 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6318 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6319 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6320 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6321 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6322 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6323 r = 0;
6324 goto out;
6325 }
e516cebb
AS		 6326 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6327 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6328 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6329 r = 0;
6330 goto out;
6331 }
2f52d58c 6332 }
b93463aa 6333
b463a6f7 6334 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6335 kvm_apic_accept_events(vcpu);
6336 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6337 r = 1;
6338 goto out;
6339 }
6340
b6b8a145
JK		 6341 if (inject_pending_event(vcpu, req_int_win) != 0)
6342 req_immediate_exit = true;
b463a6f7 6343 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6344 else if (vcpu->arch.nmi_pending)
c9a7953f 6345 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6346 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6347 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6348
6349 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6350 /*
6351 * Update architecture specific hints for APIC
6352 * virtual interrupt delivery.
6353 */
6354 if (kvm_x86_ops->hwapic_irr_update)
6355 kvm_x86_ops->hwapic_irr_update(vcpu,
6356 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6357 update_cr8_intercept(vcpu);
6358 kvm_lapic_sync_to_vapic(vcpu);
6359 }
6360 }
6361
d8368af8
AK		 6362 r = kvm_mmu_reload(vcpu);
6363 if (unlikely(r)) {
d905c069 6364 goto cancel_injection;
d8368af8
AK		 6365 }
6366
b6c7a5dc
HB		 6367 preempt_disable();
6368
6369 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6370 if (vcpu->fpu_active)
6371 kvm_load_guest_fpu(vcpu);
2acf923e 6372 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6373
6b7e2d09
XG		 6374 vcpu->mode = IN_GUEST_MODE;
6375
01b71917
MT		 6376 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6377
6b7e2d09
XG		 6378 /* We should set ->mode before check ->requests,
6379 * see the comment in make_all_cpus_request.
6380 */
01b71917 6381 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6382
d94e1dc9 6383 local_irq_disable();
32f88400 6384
6b7e2d09 6385 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6386 || need_resched() || signal_pending(current)) {
6b7e2d09 6387 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6388 smp_wmb();
6c142801
AK		 6389 local_irq_enable();
6390 preempt_enable();
01b71917 6391 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6392 r = 1;
d905c069 6393 goto cancel_injection;
6c142801
AK		 6394 }
6395
d6185f20
NHE		 6396 if (req_immediate_exit)
6397 smp_send_reschedule(vcpu->cpu);
6398
ccf73aaf 6399 __kvm_guest_enter();
b6c7a5dc 6400
42dbaa5a 6401 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6402 set_debugreg(0, 7);
6403 set_debugreg(vcpu->arch.eff_db[0], 0);
6404 set_debugreg(vcpu->arch.eff_db[1], 1);
6405 set_debugreg(vcpu->arch.eff_db[2], 2);
6406 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6407 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6408 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6409 }
b6c7a5dc 6410
229456fc 6411 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6412 wait_lapic_expire(vcpu);
851ba692 6413 kvm_x86_ops->run(vcpu);
b6c7a5dc 6414
c77fb5fe
PB		 6415 /*
6416 * Do this here before restoring debug registers on the host. And
6417 * since we do this before handling the vmexit, a DR access vmexit
6418 * can (a) read the correct value of the debug registers, (b) set
6419 * KVM_DEBUGREG_WONT_EXIT again.
6420 */
6421 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6422 int i;
6423
6424 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6425 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6426 for (i = 0; i < KVM_NR_DB_REGS; i++)
6427 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6428 }
6429
24f1e32c
FW		 6430 /*
6431 * If the guest has used debug registers, at least dr7
6432 * will be disabled while returning to the host.
6433 * If we don't have active breakpoints in the host, we don't
6434 * care about the messed up debug address registers. But if
6435 * we have some of them active, restore the old state.
6436 */
59d8eb53 6437 if (hw_breakpoint_active())
24f1e32c 6438 hw_breakpoint_restore();
42dbaa5a 6439
886b470c 6440 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6441 rdtsc());
1d5f066e 6442
6b7e2d09 6443 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6444 smp_wmb();
a547c6db
YZ		 6445
6446 /* Interrupt is enabled by handle_external_intr() */
6447 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6448
6449 ++vcpu->stat.exits;
6450
6451 /*
6452 * We must have an instruction between local_irq_enable() and
6453 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6454 * the interrupt shadow. The stat.exits increment will do nicely.
6455 * But we need to prevent reordering, hence this barrier():
6456 */
6457 barrier();
6458
6459 kvm_guest_exit();
6460
6461 preempt_enable();
6462
f656ce01 6463 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6464
b6c7a5dc
HB		 6465 /*
6466 * Profile KVM exit RIPs:
6467 */
6468 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6469 unsigned long rip = kvm_rip_read(vcpu);
6470 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6471 }
6472
cc578287
ZA		 6473 if (unlikely(vcpu->arch.tsc_always_catchup))
6474 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6475
5cfb1d5a
MT		 6476 if (vcpu->arch.apic_attention)
6477 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6478
851ba692 6479 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6480 return r;
6481
6482cancel_injection:
6483 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6484 if (unlikely(vcpu->arch.apic_attention))
6485 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6486out:
6487 return r;
6488}
b6c7a5dc 6489
362c698f
PB		 6490static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6491{
9c8fd1ba
PB		 6492 if (!kvm_arch_vcpu_runnable(vcpu)) {
6493 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6494 kvm_vcpu_block(vcpu);
6495 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6496 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6497 return 1;
6498 }
362c698f
PB		 6499
6500 kvm_apic_accept_events(vcpu);
6501 switch(vcpu->arch.mp_state) {
6502 case KVM_MP_STATE_HALTED:
6503 vcpu->arch.pv.pv_unhalted = false;
6504 vcpu->arch.mp_state =
6505 KVM_MP_STATE_RUNNABLE;
6506 case KVM_MP_STATE_RUNNABLE:
6507 vcpu->arch.apf.halted = false;
6508 break;
6509 case KVM_MP_STATE_INIT_RECEIVED:
6510 break;
6511 default:
6512 return -EINTR;
6513 break;
6514 }
6515 return 1;
6516}
09cec754 6517
362c698f 6518static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6519{
6520 int r;
f656ce01 6521 struct kvm *kvm = vcpu->kvm;
d7690175 6522
f656ce01 6523 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6524
362c698f 6525 for (;;) {
af585b92
GN		 6526 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6527 !vcpu->arch.apf.halted)
851ba692 6528 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6529 else
6530 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6531 if (r <= 0)
6532 break;
6533
6534 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6535 if (kvm_cpu_has_pending_timer(vcpu))
6536 kvm_inject_pending_timer_irqs(vcpu);
6537
851ba692 6538 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6539 r = 0;
6540 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6541 ++vcpu->stat.request_irq_exits;
362c698f 6542 break;
09cec754 6543 }
af585b92
GN		 6544
6545 kvm_check_async_pf_completion(vcpu);
6546
09cec754
GN		 6547 if (signal_pending(current)) {
6548 r = -EINTR;
851ba692 6549 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6550 ++vcpu->stat.signal_exits;
362c698f 6551 break;
09cec754
GN		 6552 }
6553 if (need_resched()) {
f656ce01 6554 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6555 cond_resched();
f656ce01 6556 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6557 }
b6c7a5dc
HB		 6558 }
6559
f656ce01 6560 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6561
6562 return r;
6563}
6564
716d51ab
GN		 6565static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6566{
6567 int r;
6568 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6569 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6570 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6571 if (r != EMULATE_DONE)
6572 return 0;
6573 return 1;
6574}
6575
6576static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6577{
6578 BUG_ON(!vcpu->arch.pio.count);
6579
6580 return complete_emulated_io(vcpu);
6581}
6582
f78146b0
AK		 6583/*
6584 * Implements the following, as a state machine:
6585 *
6586 * read:
6587 * for each fragment
87da7e66
XG		 6588 * for each mmio piece in the fragment
6589 * write gpa, len
6590 * exit
6591 * copy data
f78146b0
AK		 6592 * execute insn
6593 *
6594 * write:
6595 * for each fragment
87da7e66
XG		 6596 * for each mmio piece in the fragment
6597 * write gpa, len
6598 * copy data
6599 * exit
f78146b0 6600 */
716d51ab 6601static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6602{
6603 struct kvm_run *run = vcpu->run;
f78146b0 6604 struct kvm_mmio_fragment *frag;
87da7e66 6605 unsigned len;
5287f194 6606
716d51ab 6607 BUG_ON(!vcpu->mmio_needed);
5287f194 6608
716d51ab 6609 /* Complete previous fragment */
87da7e66
XG		 6610 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6611 len = min(8u, frag->len);
716d51ab 6612 if (!vcpu->mmio_is_write)
87da7e66
XG		 6613 memcpy(frag->data, run->mmio.data, len);
6614
6615 if (frag->len <= 8) {
6616 /* Switch to the next fragment. */
6617 frag++;
6618 vcpu->mmio_cur_fragment++;
6619 } else {
6620 /* Go forward to the next mmio piece. */
6621 frag->data += len;
6622 frag->gpa += len;
6623 frag->len -= len;
6624 }
6625
a08d3b3b 6626 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6627 vcpu->mmio_needed = 0;
0912c977
PB		 6628
6629 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6630 if (vcpu->mmio_is_write)
716d51ab
GN		 6631 return 1;
6632 vcpu->mmio_read_completed = 1;
6633 return complete_emulated_io(vcpu);
6634 }
87da7e66 6635
716d51ab
GN		 6636 run->exit_reason = KVM_EXIT_MMIO;
6637 run->mmio.phys_addr = frag->gpa;
6638 if (vcpu->mmio_is_write)
87da7e66
XG		 6639 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6640 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6641 run->mmio.is_write = vcpu->mmio_is_write;
6642 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6643 return 0;
5287f194
AK		 6644}
6645
716d51ab 6646
b6c7a5dc
HB		 6647int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6648{
c5bedc68 6649 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6650 int r;
6651 sigset_t sigsaved;
6652
c4d72e2d 6653 fpu__activate_curr(fpu);
e5c30142 6654
ac9f6dc0
AK		 6655 if (vcpu->sigset_active)
6656 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6657
a4535290 6658 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6659 kvm_vcpu_block(vcpu);
66450a21 6660 kvm_apic_accept_events(vcpu);
d7690175 6661 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6662 r = -EAGAIN;
6663 goto out;
b6c7a5dc
HB		 6664 }
6665
b6c7a5dc 6666 /* re-sync apic's tpr */
35754c98 6667 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6668 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6669 r = -EINVAL;
6670 goto out;
6671 }
6672 }
b6c7a5dc 6673
716d51ab
GN		 6674 if (unlikely(vcpu->arch.complete_userspace_io)) {
6675 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6676 vcpu->arch.complete_userspace_io = NULL;
6677 r = cui(vcpu);
6678 if (r <= 0)
6679 goto out;
6680 } else
6681 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6682
362c698f 6683 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6684
6685out:
f1d86e46 6686 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6687 if (vcpu->sigset_active)
6688 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6689
b6c7a5dc
HB		 6690 return r;
6691}
6692
6693int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6694{
7ae441ea
GN		 6695 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6696 /*
6697 * We are here if userspace calls get_regs() in the middle of
6698 * instruction emulation. Registers state needs to be copied
4a969980 6699 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6700 * that usually, but some bad designed PV devices (vmware
6701 * backdoor interface) need this to work
6702 */
dd856efa 6703 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6704 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6705 }
5fdbf976
MT		 6706 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6707 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6708 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6709 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6710 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6711 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6712 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6713 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6714#ifdef CONFIG_X86_64
5fdbf976
MT		 6715 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6716 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6717 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6718 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6719 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6720 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6721 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6722 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6723#endif
6724
5fdbf976 6725 regs->rip = kvm_rip_read(vcpu);
91586a3b 6726 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6727
b6c7a5dc
HB		 6728 return 0;
6729}
6730
6731int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6732{
7ae441ea
GN		 6733 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6734 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6735
5fdbf976
MT		 6736 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6737 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6738 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6739 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6740 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6741 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6742 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6743 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6744#ifdef CONFIG_X86_64
5fdbf976
MT		 6745 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6746 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6747 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6748 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6749 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6750 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6751 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6752 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6753#endif
6754
5fdbf976 6755 kvm_rip_write(vcpu, regs->rip);
91586a3b 6756 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6757
b4f14abd
JK		 6758 vcpu->arch.exception.pending = false;
6759
3842d135
AK		 6760 kvm_make_request(KVM_REQ_EVENT, vcpu);
6761
b6c7a5dc
HB		 6762 return 0;
6763}
6764
b6c7a5dc
HB		 6765void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6766{
6767 struct kvm_segment cs;
6768
3e6e0aab 6769 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6770 *db = cs.db;
6771 *l = cs.l;
6772}
6773EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6774
6775int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6776 struct kvm_sregs *sregs)
6777{
89a27f4d 6778 struct desc_ptr dt;
b6c7a5dc 6779
3e6e0aab
GT		 6780 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6781 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6782 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6783 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6784 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6785 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6786
3e6e0aab
GT		 6787 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6788 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6789
6790 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6791 sregs->idt.limit = dt.size;
6792 sregs->idt.base = dt.address;
b6c7a5dc 6793 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6794 sregs->gdt.limit = dt.size;
6795 sregs->gdt.base = dt.address;
b6c7a5dc 6796
4d4ec087 6797 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6798 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6799 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6800 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6801 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6802 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6803 sregs->apic_base = kvm_get_apic_base(vcpu);
6804
923c61bb 6805 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6806
36752c9b 6807 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6808 set_bit(vcpu->arch.interrupt.nr,
6809 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6810
b6c7a5dc
HB		 6811 return 0;
6812}
6813
62d9f0db
MT		 6814int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6815 struct kvm_mp_state *mp_state)
6816{
66450a21 6817 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6818 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6819 vcpu->arch.pv.pv_unhalted)
6820 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6821 else
6822 mp_state->mp_state = vcpu->arch.mp_state;
6823
62d9f0db
MT		 6824 return 0;
6825}
6826
6827int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6828 struct kvm_mp_state *mp_state)
6829{
66450a21
JK		 6830 if (!kvm_vcpu_has_lapic(vcpu) &&
6831 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6832 return -EINVAL;
6833
6834 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6835 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6836 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6837 } else
6838 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6839 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6840 return 0;
6841}
6842
7f3d35fd
KW		 6843int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6844 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6845{
9d74191a 6846 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6847 int ret;
e01c2426 6848
8ec4722d 6849 init_emulate_ctxt(vcpu);
c697518a 6850
7f3d35fd 6851 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6852 has_error_code, error_code);
c697518a 6853
c697518a 6854 if (ret)
19d04437 6855 return EMULATE_FAIL;
37817f29 6856
9d74191a
TY		 6857 kvm_rip_write(vcpu, ctxt->eip);
6858 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6859 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6860 return EMULATE_DONE;
37817f29
IE		 6861}
6862EXPORT_SYMBOL_GPL(kvm_task_switch);
6863
b6c7a5dc
HB		 6864int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6865 struct kvm_sregs *sregs)
6866{
58cb628d 6867 struct msr_data apic_base_msr;
b6c7a5dc 6868 int mmu_reset_needed = 0;
63f42e02 6869 int pending_vec, max_bits, idx;
89a27f4d 6870 struct desc_ptr dt;
b6c7a5dc 6871
6d1068b3
PM		 6872 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6873 return -EINVAL;
6874
89a27f4d
GN		 6875 dt.size = sregs->idt.limit;
6876 dt.address = sregs->idt.base;
b6c7a5dc 6877 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6878 dt.size = sregs->gdt.limit;
6879 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6880 kvm_x86_ops->set_gdt(vcpu, &dt);
6881
ad312c7c 6882 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6883 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6884 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6885 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6886
2d3ad1f4 6887 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6888
f6801dff 6889 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6890 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6891 apic_base_msr.data = sregs->apic_base;
6892 apic_base_msr.host_initiated = true;
6893 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6894
4d4ec087 6895 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6896 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6897 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6898
fc78f519 6899 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6900 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6901 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6902 kvm_update_cpuid(vcpu);
63f42e02
XG		 6903
6904 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6905 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6906 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6907 mmu_reset_needed = 1;
6908 }
63f42e02 6909 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6910
6911 if (mmu_reset_needed)
6912 kvm_mmu_reset_context(vcpu);
6913
a50abc3b 6914 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6915 pending_vec = find_first_bit(
6916 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6917 if (pending_vec < max_bits) {
66fd3f7f 6918 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6919 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6920 }
6921
3e6e0aab
GT		 6922 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6923 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6924 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6925 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6926 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6927 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6928
3e6e0aab
GT		 6929 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6930 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6931
5f0269f5
ME		 6932 update_cr8_intercept(vcpu);
6933
9c3e4aab 6934 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6935 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6936 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6937 !is_protmode(vcpu))
9c3e4aab
MT		 6938 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6939
3842d135
AK		 6940 kvm_make_request(KVM_REQ_EVENT, vcpu);
6941
b6c7a5dc
HB		 6942 return 0;
6943}
6944
d0bfb940
JK		 6945int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6946 struct kvm_guest_debug *dbg)
b6c7a5dc 6947{
355be0b9 6948 unsigned long rflags;
ae675ef0 6949 int i, r;
b6c7a5dc 6950
4f926bf2
JK		 6951 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6952 r = -EBUSY;
6953 if (vcpu->arch.exception.pending)
2122ff5e 6954 goto out;
4f926bf2
JK		 6955 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6956 kvm_queue_exception(vcpu, DB_VECTOR);
6957 else
6958 kvm_queue_exception(vcpu, BP_VECTOR);
6959 }
6960
91586a3b
JK		 6961 /*
6962 * Read rflags as long as potentially injected trace flags are still
6963 * filtered out.
6964 */
6965 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6966
6967 vcpu->guest_debug = dbg->control;
6968 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6969 vcpu->guest_debug = 0;
6970
6971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6972 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6973 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6974 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6975 } else {
6976 for (i = 0; i < KVM_NR_DB_REGS; i++)
6977 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6978 }
c8639010 6979 kvm_update_dr7(vcpu);
ae675ef0 6980
f92653ee
JK		 6981 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6982 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6983 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6984
91586a3b
JK		 6985 /*
6986 * Trigger an rflags update that will inject or remove the trace
6987 * flags.
6988 */
6989 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6990
c8639010 6991 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6992
4f926bf2 6993 r = 0;
d0bfb940 6994
2122ff5e 6995out:
b6c7a5dc
HB		 6996
6997 return r;
6998}
6999
8b006791
ZX		 7000/*
7001 * Translate a guest virtual address to a guest physical address.
7002 */
7003int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7004 struct kvm_translation *tr)
7005{
7006 unsigned long vaddr = tr->linear_address;
7007 gpa_t gpa;
f656ce01 7008 int idx;
8b006791 7009
f656ce01 7010 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7011 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7012 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7013 tr->physical_address = gpa;
7014 tr->valid = gpa != UNMAPPED_GVA;
7015 tr->writeable = 1;
7016 tr->usermode = 0;
8b006791
ZX		 7017
7018 return 0;
7019}
7020
d0752060
HB		 7021int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7022{
c47ada30 7023 struct fxregs_state *fxsave =
7366ed77 7024 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7025
d0752060
HB		 7026 memcpy(fpu->fpr, fxsave->st_space, 128);
7027 fpu->fcw = fxsave->cwd;
7028 fpu->fsw = fxsave->swd;
7029 fpu->ftwx = fxsave->twd;
7030 fpu->last_opcode = fxsave->fop;
7031 fpu->last_ip = fxsave->rip;
7032 fpu->last_dp = fxsave->rdp;
7033 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7034
d0752060
HB		 7035 return 0;
7036}
7037
7038int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7039{
c47ada30 7040 struct fxregs_state *fxsave =
7366ed77 7041 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7042
d0752060
HB		 7043 memcpy(fxsave->st_space, fpu->fpr, 128);
7044 fxsave->cwd = fpu->fcw;
7045 fxsave->swd = fpu->fsw;
7046 fxsave->twd = fpu->ftwx;
7047 fxsave->fop = fpu->last_opcode;
7048 fxsave->rip = fpu->last_ip;
7049 fxsave->rdp = fpu->last_dp;
7050 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7051
d0752060
HB		 7052 return 0;
7053}
7054
0ee6a517 7055static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7056{
bf935b0b 7057 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7058 if (cpu_has_xsaves)
7366ed77 7059 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7060 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7061
2acf923e
DC		 7062 /*
7063 * Ensure guest xcr0 is valid for loading
7064 */
7065 vcpu->arch.xcr0 = XSTATE_FP;
7066
ad312c7c 7067 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7068}
d0752060
HB		 7069
7070void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7071{
2608d7a1 7072 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7073 return;
7074
2acf923e
DC		 7075 /*
7076 * Restore all possible states in the guest,
7077 * and assume host would use all available bits.
7078 * Guest xcr0 would be loaded later.
7079 */
7080 kvm_put_guest_xcr0(vcpu);
d0752060 7081 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7082 __kernel_fpu_begin();
003e2e8b 7083 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7084 trace_kvm_fpu(1);
d0752060 7085}
d0752060
HB		 7086
7087void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7088{
2acf923e
DC		 7089 kvm_put_guest_xcr0(vcpu);
7090
653f52c3
RR		 7091 if (!vcpu->guest_fpu_loaded) {
7092 vcpu->fpu_counter = 0;
d0752060 7093 return;
653f52c3 7094 }
d0752060
HB		 7095
7096 vcpu->guest_fpu_loaded = 0;
4f836347 7097 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7098 __kernel_fpu_end();
f096ed85 7099 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7100 /*
7101 * If using eager FPU mode, or if the guest is a frequent user
7102 * of the FPU, just leave the FPU active for next time.
7103 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7104 * the FPU in bursts will revert to loading it on demand.
7105 */
a9b4fb7e 7106 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7107 if (++vcpu->fpu_counter < 5)
7108 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7109 }
0c04851c 7110 trace_kvm_fpu(0);
d0752060 7111}
e9b11c17
ZX		 7112
7113void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7114{
12f9a48f 7115 kvmclock_reset(vcpu);
7f1ea208 7116
f5f48ee1 7117 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7118 kvm_x86_ops->vcpu_free(vcpu);
7119}
7120
7121struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7122 unsigned int id)
7123{
c447e76b
LL		 7124 struct kvm_vcpu *vcpu;
7125
6755bae8
ZA		 7126 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7127 printk_once(KERN_WARNING
7128 "kvm: SMP vm created on host with unstable TSC; "
7129 "guest TSC will not be reliable\n");
c447e76b
LL		 7130
7131 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7132
c447e76b 7133 return vcpu;
26e5215f 7134}
e9b11c17 7135
26e5215f
AK		 7136int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7137{
7138 int r;
e9b11c17 7139
19efffa2 7140 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7141 r = vcpu_load(vcpu);
7142 if (r)
7143 return r;
d28bc9dd 7144 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7145 kvm_mmu_setup(vcpu);
e9b11c17 7146 vcpu_put(vcpu);
26e5215f 7147 return r;
e9b11c17
ZX		 7148}
7149
31928aa5 7150void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7151{
8fe8ab46 7152 struct msr_data msr;
332967a3 7153 struct kvm *kvm = vcpu->kvm;
42897d86 7154
31928aa5
DD		 7155 if (vcpu_load(vcpu))
7156 return;
8fe8ab46
WA		 7157 msr.data = 0x0;
7158 msr.index = MSR_IA32_TSC;
7159 msr.host_initiated = true;
7160 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7161 vcpu_put(vcpu);
7162
630994b3
MT		 7163 if (!kvmclock_periodic_sync)
7164 return;
7165
332967a3
AJ		 7166 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7167 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7168}
7169
d40ccc62 7170void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7171{
9fc77441 7172 int r;
344d9588
GN		 7173 vcpu->arch.apf.msr_val = 0;
7174
9fc77441
MT		 7175 r = vcpu_load(vcpu);
7176 BUG_ON(r);
e9b11c17
ZX		 7177 kvm_mmu_unload(vcpu);
7178 vcpu_put(vcpu);
7179
7180 kvm_x86_ops->vcpu_free(vcpu);
7181}
7182
d28bc9dd 7183void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7184{
e69fab5d
PB		 7185 vcpu->arch.hflags = 0;
7186
7460fb4a
AK		 7187 atomic_set(&vcpu->arch.nmi_queued, 0);
7188 vcpu->arch.nmi_pending = 0;
448fa4a9 7189 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7190 kvm_clear_interrupt_queue(vcpu);
7191 kvm_clear_exception_queue(vcpu);
448fa4a9 7192
42dbaa5a 7193 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7194 kvm_update_dr0123(vcpu);
6f43ed01 7195 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7196 kvm_update_dr6(vcpu);
42dbaa5a 7197 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7198 kvm_update_dr7(vcpu);
42dbaa5a 7199
1119022c
NA		 7200 vcpu->arch.cr2 = 0;
7201
3842d135 7202 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7203 vcpu->arch.apf.msr_val = 0;
c9aaa895 7204 vcpu->arch.st.msr_val = 0;
3842d135 7205
12f9a48f
GC		 7206 kvmclock_reset(vcpu);
7207
af585b92
GN		 7208 kvm_clear_async_pf_completion_queue(vcpu);
7209 kvm_async_pf_hash_reset(vcpu);
7210 vcpu->arch.apf.halted = false;
3842d135 7211
64d60670 7212 if (!init_event) {
d28bc9dd 7213 kvm_pmu_reset(vcpu);
64d60670
PB		 7214 vcpu->arch.smbase = 0x30000;
7215 }
f5132b01 7216
66f7b72e
JS		 7217 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7218 vcpu->arch.regs_avail = ~0;
7219 vcpu->arch.regs_dirty = ~0;
7220
d28bc9dd 7221 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7222}
7223
2b4a273b 7224void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7225{
7226 struct kvm_segment cs;
7227
7228 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7229 cs.selector = vector << 8;
7230 cs.base = vector << 12;
7231 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7232 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7233}
7234
13a34e06 7235int kvm_arch_hardware_enable(void)
e9b11c17 7236{
ca84d1a2
ZA		 7237 struct kvm *kvm;
7238 struct kvm_vcpu *vcpu;
7239 int i;
0dd6a6ed
ZA		 7240 int ret;
7241 u64 local_tsc;
7242 u64 max_tsc = 0;
7243 bool stable, backwards_tsc = false;
18863bdd
AK		 7244
7245 kvm_shared_msr_cpu_online();
13a34e06 7246 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7247 if (ret != 0)
7248 return ret;
7249
4ea1636b 7250 local_tsc = rdtsc();
0dd6a6ed
ZA		 7251 stable = !check_tsc_unstable();
7252 list_for_each_entry(kvm, &vm_list, vm_list) {
7253 kvm_for_each_vcpu(i, vcpu, kvm) {
7254 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7255 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7256 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7257 backwards_tsc = true;
7258 if (vcpu->arch.last_host_tsc > max_tsc)
7259 max_tsc = vcpu->arch.last_host_tsc;
7260 }
7261 }
7262 }
7263
7264 /*
7265 * Sometimes, even reliable TSCs go backwards. This happens on
7266 * platforms that reset TSC during suspend or hibernate actions, but
7267 * maintain synchronization. We must compensate. Fortunately, we can
7268 * detect that condition here, which happens early in CPU bringup,
7269 * before any KVM threads can be running. Unfortunately, we can't
7270 * bring the TSCs fully up to date with real time, as we aren't yet far
7271 * enough into CPU bringup that we know how much real time has actually
7272 * elapsed; our helper function, get_kernel_ns() will be using boot
7273 * variables that haven't been updated yet.
7274 *
7275 * So we simply find the maximum observed TSC above, then record the
7276 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7277 * the adjustment will be applied. Note that we accumulate
7278 * adjustments, in case multiple suspend cycles happen before some VCPU
7279 * gets a chance to run again. In the event that no KVM threads get a
7280 * chance to run, we will miss the entire elapsed period, as we'll have
7281 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7282 * loose cycle time. This isn't too big a deal, since the loss will be
7283 * uniform across all VCPUs (not to mention the scenario is extremely
7284 * unlikely). It is possible that a second hibernate recovery happens
7285 * much faster than a first, causing the observed TSC here to be
7286 * smaller; this would require additional padding adjustment, which is
7287 * why we set last_host_tsc to the local tsc observed here.
7288 *
7289 * N.B. - this code below runs only on platforms with reliable TSC,
7290 * as that is the only way backwards_tsc is set above. Also note
7291 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7292 * have the same delta_cyc adjustment applied if backwards_tsc
7293 * is detected. Note further, this adjustment is only done once,
7294 * as we reset last_host_tsc on all VCPUs to stop this from being
7295 * called multiple times (one for each physical CPU bringup).
7296 *
4a969980 7297 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7298 * will be compensated by the logic in vcpu_load, which sets the TSC to
7299 * catchup mode. This will catchup all VCPUs to real time, but cannot
7300 * guarantee that they stay in perfect synchronization.
7301 */
7302 if (backwards_tsc) {
7303 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7304 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7305 list_for_each_entry(kvm, &vm_list, vm_list) {
7306 kvm_for_each_vcpu(i, vcpu, kvm) {
7307 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7308 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7309 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7310 }
7311
7312 /*
7313 * We have to disable TSC offset matching.. if you were
7314 * booting a VM while issuing an S4 host suspend....
7315 * you may have some problem. Solving this issue is
7316 * left as an exercise to the reader.
7317 */
7318 kvm->arch.last_tsc_nsec = 0;
7319 kvm->arch.last_tsc_write = 0;
7320 }
7321
7322 }
7323 return 0;
e9b11c17
ZX		 7324}
7325
13a34e06 7326void kvm_arch_hardware_disable(void)
e9b11c17 7327{
13a34e06
RK		 7328 kvm_x86_ops->hardware_disable();
7329 drop_user_return_notifiers();
e9b11c17
ZX		 7330}
7331
7332int kvm_arch_hardware_setup(void)
7333{
9e9c3fe4
NA		 7334 int r;
7335
7336 r = kvm_x86_ops->hardware_setup();
7337 if (r != 0)
7338 return r;
7339
7340 kvm_init_msr_list();
7341 return 0;
e9b11c17
ZX		 7342}
7343
7344void kvm_arch_hardware_unsetup(void)
7345{
7346 kvm_x86_ops->hardware_unsetup();
7347}
7348
7349void kvm_arch_check_processor_compat(void *rtn)
7350{
7351 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7352}
7353
7354bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7355{
7356 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7357}
7358EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7359
7360bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7361{
7362 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7363}
7364
3e515705
AK		 7365bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7366{
35754c98 7367 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7368}
7369
54e9818f
GN		 7370struct static_key kvm_no_apic_vcpu __read_mostly;
7371
e9b11c17
ZX		 7372int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7373{
7374 struct page *page;
7375 struct kvm *kvm;
7376 int r;
7377
7378 BUG_ON(vcpu->kvm == NULL);
7379 kvm = vcpu->kvm;
7380
6aef266c 7381 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7382 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7383 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7384 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7385 else
a4535290 7386 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7387
7388 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7389 if (!page) {
7390 r = -ENOMEM;
7391 goto fail;
7392 }
ad312c7c 7393 vcpu->arch.pio_data = page_address(page);
e9b11c17 7394
cc578287 7395 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7396
e9b11c17
ZX		 7397 r = kvm_mmu_create(vcpu);
7398 if (r < 0)
7399 goto fail_free_pio_data;
7400
7401 if (irqchip_in_kernel(kvm)) {
7402 r = kvm_create_lapic(vcpu);
7403 if (r < 0)
7404 goto fail_mmu_destroy;
54e9818f
GN		 7405 } else
7406 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7407
890ca9ae
HY		 7408 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7409 GFP_KERNEL);
7410 if (!vcpu->arch.mce_banks) {
7411 r = -ENOMEM;
443c39bc 7412 goto fail_free_lapic;
890ca9ae
HY		 7413 }
7414 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7415
f1797359
WY		 7416 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7417 r = -ENOMEM;
f5f48ee1 7418 goto fail_free_mce_banks;
f1797359 7419 }
f5f48ee1 7420
0ee6a517 7421 fx_init(vcpu);
66f7b72e 7422
ba904635 7423 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7424 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7425
7426 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7427 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7428
5a4f55cd
EK		 7429 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7430
74545705
RK		 7431 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7432
af585b92 7433 kvm_async_pf_hash_reset(vcpu);
f5132b01 7434 kvm_pmu_init(vcpu);
af585b92 7435
1c1a9ce9
SR		 7436 vcpu->arch.pending_external_vector = -1;
7437
e9b11c17 7438 return 0;
0ee6a517 7439
f5f48ee1
SY		 7440fail_free_mce_banks:
7441 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7442fail_free_lapic:
7443 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7444fail_mmu_destroy:
7445 kvm_mmu_destroy(vcpu);
7446fail_free_pio_data:
ad312c7c 7447 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7448fail:
7449 return r;
7450}
7451
7452void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7453{
f656ce01
MT		 7454 int idx;
7455
f5132b01 7456 kvm_pmu_destroy(vcpu);
36cb93fd 7457 kfree(vcpu->arch.mce_banks);
e9b11c17 7458 kvm_free_lapic(vcpu);
f656ce01 7459 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7460 kvm_mmu_destroy(vcpu);
f656ce01 7461 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7462 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7463 if (!lapic_in_kernel(vcpu))
54e9818f 7464 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7465}
d19a9cd2 7466
e790d9ef
RK		 7467void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7468{
ae97a3b8 7469 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7470}
7471
e08b9637 7472int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7473{
e08b9637
CO		 7474 if (type)
7475 return -EINVAL;
7476
6ef768fa 7477 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7478 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7479 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7480 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7481 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7482
5550af4d
SY		 7483 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7484 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7485 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7486 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7487 &kvm->arch.irq_sources_bitmap);
5550af4d 7488
038f8c11 7489 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7490 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7491 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7492
7493 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7494
7e44e449 7495 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7496 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7497
d89f5eff 7498 return 0;
d19a9cd2
ZX		 7499}
7500
7501static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7502{
9fc77441
MT		 7503 int r;
7504 r = vcpu_load(vcpu);
7505 BUG_ON(r);
d19a9cd2
ZX		 7506 kvm_mmu_unload(vcpu);
7507 vcpu_put(vcpu);
7508}
7509
7510static void kvm_free_vcpus(struct kvm *kvm)
7511{
7512 unsigned int i;
988a2cae 7513 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7514
7515 /*
7516 * Unpin any mmu pages first.
7517 */
af585b92
GN		 7518 kvm_for_each_vcpu(i, vcpu, kvm) {
7519 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7520 kvm_unload_vcpu_mmu(vcpu);
af585b92 7521 }
988a2cae
GN		 7522 kvm_for_each_vcpu(i, vcpu, kvm)
7523 kvm_arch_vcpu_free(vcpu);
7524
7525 mutex_lock(&kvm->lock);
7526 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7527 kvm->vcpus[i] = NULL;
d19a9cd2 7528
988a2cae
GN		 7529 atomic_set(&kvm->online_vcpus, 0);
7530 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7531}
7532
ad8ba2cd
SY		 7533void kvm_arch_sync_events(struct kvm *kvm)
7534{
332967a3 7535 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7536 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7537 kvm_free_all_assigned_devices(kvm);
aea924f6 7538 kvm_free_pit(kvm);
ad8ba2cd
SY		 7539}
7540
9da0e4d5
PB		 7541int __x86_set_memory_region(struct kvm *kvm,
7542 const struct kvm_userspace_memory_region *mem)
7543{
7544 int i, r;
7545
7546 /* Called with kvm->slots_lock held. */
7547 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7548
7549 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7550 struct kvm_userspace_memory_region m = *mem;
7551
7552 m.slot |= i << 16;
7553 r = __kvm_set_memory_region(kvm, &m);
7554 if (r < 0)
7555 return r;
7556 }
7557
7558 return 0;
7559}
7560EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7561
7562int x86_set_memory_region(struct kvm *kvm,
7563 const struct kvm_userspace_memory_region *mem)
7564{
7565 int r;
7566
7567 mutex_lock(&kvm->slots_lock);
7568 r = __x86_set_memory_region(kvm, mem);
7569 mutex_unlock(&kvm->slots_lock);
7570
7571 return r;
7572}
7573EXPORT_SYMBOL_GPL(x86_set_memory_region);
7574
d19a9cd2
ZX		 7575void kvm_arch_destroy_vm(struct kvm *kvm)
7576{
27469d29
AH		 7577 if (current->mm == kvm->mm) {
7578 /*
7579 * Free memory regions allocated on behalf of userspace,
7580 * unless the the memory map has changed due to process exit
7581 * or fd copying.
7582 */
7583 struct kvm_userspace_memory_region mem;
7584 memset(&mem, 0, sizeof(mem));
7585 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7586 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7587
7588 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7589 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7590
7591 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7592 x86_set_memory_region(kvm, &mem);
27469d29 7593 }
6eb55818 7594 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7595 kfree(kvm->arch.vpic);
7596 kfree(kvm->arch.vioapic);
d19a9cd2 7597 kvm_free_vcpus(kvm);
1e08ec4a 7598 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7599}
0de10343 7600
5587027c 7601void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7602 struct kvm_memory_slot *dont)
7603{
7604 int i;
7605
d89cc617
TY		 7606 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7607 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7608 kvfree(free->arch.rmap[i]);
d89cc617 7609 free->arch.rmap[i] = NULL;
77d11309 7610 }
d89cc617
TY		 7611 if (i == 0)
7612 continue;
7613
7614 if (!dont || free->arch.lpage_info[i - 1] !=
7615 dont->arch.lpage_info[i - 1]) {
548ef284 7616 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7617 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7618 }
7619 }
7620}
7621
5587027c
AK		 7622int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7623 unsigned long npages)
db3fe4eb
TY		 7624{
7625 int i;
7626
d89cc617 7627 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7628 unsigned long ugfn;
7629 int lpages;
d89cc617 7630 int level = i + 1;
db3fe4eb
TY		 7631
7632 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7633 slot->base_gfn, level) + 1;
7634
d89cc617
TY		 7635 slot->arch.rmap[i] =
7636 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7637 if (!slot->arch.rmap[i])
77d11309 7638 goto out_free;
d89cc617
TY		 7639 if (i == 0)
7640 continue;
77d11309 7641
d89cc617
TY		 7642 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7643 sizeof(*slot->arch.lpage_info[i - 1]));
7644 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7645 goto out_free;
7646
7647 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7648 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7649 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7650 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7651 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7652 /*
7653 * If the gfn and userspace address are not aligned wrt each
7654 * other, or if explicitly asked to, disable large page
7655 * support for this slot
7656 */
7657 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7658 !kvm_largepages_enabled()) {
7659 unsigned long j;
7660
7661 for (j = 0; j < lpages; ++j)
d89cc617 7662 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7663 }
7664 }
7665
7666 return 0;
7667
7668out_free:
d89cc617 7669 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7670 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7671 slot->arch.rmap[i] = NULL;
7672 if (i == 0)
7673 continue;
7674
548ef284 7675 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7676 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7677 }
7678 return -ENOMEM;
7679}
7680
15f46015 7681void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7682{
e6dff7d1
TY		 7683 /*
7684 * memslots->generation has been incremented.
7685 * mmio generation may have reached its maximum value.
7686 */
54bf36aa 7687 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7688}
7689
f7784b8e
MT		 7690int kvm_arch_prepare_memory_region(struct kvm *kvm,
7691 struct kvm_memory_slot *memslot,
09170a49 7692 const struct kvm_userspace_memory_region *mem,
7b6195a9 7693 enum kvm_mr_change change)
0de10343 7694{
7a905b14
TY		 7695 /*
7696 * Only private memory slots need to be mapped here since
7697 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7698 */
7b6195a9 7699 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7700 unsigned long userspace_addr;
604b38ac 7701
7a905b14
TY		 7702 /*
7703 * MAP_SHARED to prevent internal slot pages from being moved
7704 * by fork()/COW.
7705 */
7b6195a9 7706 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7707 PROT_READ | PROT_WRITE,
7708 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7709
7a905b14
TY		 7710 if (IS_ERR((void *)userspace_addr))
7711 return PTR_ERR((void *)userspace_addr);
604b38ac 7712
7a905b14 7713 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7714 }
7715
f7784b8e
MT		 7716 return 0;
7717}
7718
88178fd4
KH		 7719static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7720 struct kvm_memory_slot *new)
7721{
7722 /* Still write protect RO slot */
7723 if (new->flags & KVM_MEM_READONLY) {
7724 kvm_mmu_slot_remove_write_access(kvm, new);
7725 return;
7726 }
7727
7728 /*
7729 * Call kvm_x86_ops dirty logging hooks when they are valid.
7730 *
7731 * kvm_x86_ops->slot_disable_log_dirty is called when:
7732 *
7733 * - KVM_MR_CREATE with dirty logging is disabled
7734 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7735 *
7736 * The reason is, in case of PML, we need to set D-bit for any slots
7737 * with dirty logging disabled in order to eliminate unnecessary GPA
7738 * logging in PML buffer (and potential PML buffer full VMEXT). This
7739 * guarantees leaving PML enabled during guest's lifetime won't have
7740 * any additonal overhead from PML when guest is running with dirty
7741 * logging disabled for memory slots.
7742 *
7743 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7744 * to dirty logging mode.
7745 *
7746 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7747 *
7748 * In case of write protect:
7749 *
7750 * Write protect all pages for dirty logging.
7751 *
7752 * All the sptes including the large sptes which point to this
7753 * slot are set to readonly. We can not create any new large
7754 * spte on this slot until the end of the logging.
7755 *
7756 * See the comments in fast_page_fault().
7757 */
7758 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7759 if (kvm_x86_ops->slot_enable_log_dirty)
7760 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7761 else
7762 kvm_mmu_slot_remove_write_access(kvm, new);
7763 } else {
7764 if (kvm_x86_ops->slot_disable_log_dirty)
7765 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7766 }
7767}
7768
f7784b8e 7769void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7770 const struct kvm_userspace_memory_region *mem,
8482644a 7771 const struct kvm_memory_slot *old,
f36f3f28 7772 const struct kvm_memory_slot *new,
8482644a 7773 enum kvm_mr_change change)
f7784b8e 7774{
8482644a 7775 int nr_mmu_pages = 0;
f7784b8e 7776
f36f3f28 7777 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7778 int ret;
7779
8482644a
TY		 7780 ret = vm_munmap(old->userspace_addr,
7781 old->npages * PAGE_SIZE);
f7784b8e
MT		 7782 if (ret < 0)
7783 printk(KERN_WARNING
7784 "kvm_vm_ioctl_set_memory_region: "
7785 "failed to munmap memory\n");
7786 }
7787
48c0e4e9
XG		 7788 if (!kvm->arch.n_requested_mmu_pages)
7789 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7790
48c0e4e9 7791 if (nr_mmu_pages)
0de10343 7792 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7793
3ea3b7fa
WL		 7794 /*
7795 * Dirty logging tracks sptes in 4k granularity, meaning that large
7796 * sptes have to be split. If live migration is successful, the guest
7797 * in the source machine will be destroyed and large sptes will be
7798 * created in the destination. However, if the guest continues to run
7799 * in the source machine (for example if live migration fails), small
7800 * sptes will remain around and cause bad performance.
7801 *
7802 * Scan sptes if dirty logging has been stopped, dropping those
7803 * which can be collapsed into a single large-page spte. Later
7804 * page faults will create the large-page sptes.
7805 */
7806 if ((change != KVM_MR_DELETE) &&
7807 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7808 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7809 kvm_mmu_zap_collapsible_sptes(kvm, new);
7810
c972f3b1 7811 /*
88178fd4 7812 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7813 *
88178fd4
KH		 7814 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7815 * been zapped so no dirty logging staff is needed for old slot. For
7816 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7817 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7818 *
7819 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7820 */
88178fd4 7821 if (change != KVM_MR_DELETE)
f36f3f28 7822 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7823}
1d737c8a 7824
2df72e9b 7825void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7826{
6ca18b69 7827 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7828}
7829
2df72e9b
MT		 7830void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7831 struct kvm_memory_slot *slot)
7832{
6ca18b69 7833 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7834}
7835
1d737c8a
ZX		 7836int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7837{
b6b8a145
JK		 7838 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7839 kvm_x86_ops->check_nested_events(vcpu, false);
7840
af585b92
GN		 7841 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7842 !vcpu->arch.apf.halted)
7843 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7844 || kvm_apic_has_events(vcpu)
6aef266c 7845 || vcpu->arch.pv.pv_unhalted
7460fb4a 7846 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7847 (kvm_arch_interrupt_allowed(vcpu) &&
7848 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7849}
5736199a 7850
b6d33834 7851int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7852{
b6d33834 7853 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7854}
78646121
GN		 7855
7856int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7857{
7858 return kvm_x86_ops->interrupt_allowed(vcpu);
7859}
229456fc 7860
82b32774 7861unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7862{
82b32774
NA		 7863 if (is_64_bit_mode(vcpu))
7864 return kvm_rip_read(vcpu);
7865 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7866 kvm_rip_read(vcpu));
7867}
7868EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7869
82b32774
NA		 7870bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7871{
7872 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7873}
7874EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7875
94fe45da
JK		 7876unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7877{
7878 unsigned long rflags;
7879
7880 rflags = kvm_x86_ops->get_rflags(vcpu);
7881 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7882 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7883 return rflags;
7884}
7885EXPORT_SYMBOL_GPL(kvm_get_rflags);
7886
6addfc42 7887static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7888{
7889 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7890 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7891 rflags |= X86_EFLAGS_TF;
94fe45da 7892 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7893}
7894
7895void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7896{
7897 __kvm_set_rflags(vcpu, rflags);
3842d135 7898 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7899}
7900EXPORT_SYMBOL_GPL(kvm_set_rflags);
7901
56028d08
GN		 7902void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7903{
7904 int r;
7905
fb67e14f 7906 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7907 work->wakeup_all)
56028d08
GN		 7908 return;
7909
7910 r = kvm_mmu_reload(vcpu);
7911 if (unlikely(r))
7912 return;
7913
fb67e14f
XG		 7914 if (!vcpu->arch.mmu.direct_map &&
7915 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7916 return;
7917
56028d08
GN		 7918 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7919}
7920
af585b92
GN		 7921static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7922{
7923 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7924}
7925
7926static inline u32 kvm_async_pf_next_probe(u32 key)
7927{
7928 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7929}
7930
7931static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7932{
7933 u32 key = kvm_async_pf_hash_fn(gfn);
7934
7935 while (vcpu->arch.apf.gfns[key] != ~0)
7936 key = kvm_async_pf_next_probe(key);
7937
7938 vcpu->arch.apf.gfns[key] = gfn;
7939}
7940
7941static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7942{
7943 int i;
7944 u32 key = kvm_async_pf_hash_fn(gfn);
7945
7946 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7947 (vcpu->arch.apf.gfns[key] != gfn &&
7948 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7949 key = kvm_async_pf_next_probe(key);
7950
7951 return key;
7952}
7953
7954bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7955{
7956 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7957}
7958
7959static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7960{
7961 u32 i, j, k;
7962
7963 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7964 while (true) {
7965 vcpu->arch.apf.gfns[i] = ~0;
7966 do {
7967 j = kvm_async_pf_next_probe(j);
7968 if (vcpu->arch.apf.gfns[j] == ~0)
7969 return;
7970 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7971 /*
7972 * k lies cyclically in ]i,j]
7973 * | i.k.j |
7974 * |....j i.k.| or |.k..j i...|
7975 */
7976 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7977 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7978 i = j;
7979 }
7980}
7981
7c90705b
GN		 7982static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7983{
7984
7985 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7986 sizeof(val));
7987}
7988
af585b92
GN		 7989void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7990 struct kvm_async_pf *work)
7991{
6389ee94
AK		 7992 struct x86_exception fault;
7993
7c90705b 7994 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7995 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7996
7997 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7998 (vcpu->arch.apf.send_user_only &&
7999 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8000 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8001 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8002 fault.vector = PF_VECTOR;
8003 fault.error_code_valid = true;
8004 fault.error_code = 0;
8005 fault.nested_page_fault = false;
8006 fault.address = work->arch.token;
8007 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8008 }
af585b92
GN		 8009}
8010
8011void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8012 struct kvm_async_pf *work)
8013{
6389ee94
AK		 8014 struct x86_exception fault;
8015
7c90705b 8016 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8017 if (work->wakeup_all)
7c90705b
GN		 8018 work->arch.token = ~0; /* broadcast wakeup */
8019 else
8020 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8021
8022 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8023 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8024 fault.vector = PF_VECTOR;
8025 fault.error_code_valid = true;
8026 fault.error_code = 0;
8027 fault.nested_page_fault = false;
8028 fault.address = work->arch.token;
8029 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8030 }
e6d53e3b 8031 vcpu->arch.apf.halted = false;
a4fa1635 8032 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8033}
8034
8035bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8036{
8037 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8038 return true;
8039 else
8040 return !kvm_event_needs_reinjection(vcpu) &&
8041 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8042}
8043
5544eb9b
PB		 8044void kvm_arch_start_assignment(struct kvm *kvm)
8045{
8046 atomic_inc(&kvm->arch.assigned_device_count);
8047}
8048EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8049
8050void kvm_arch_end_assignment(struct kvm *kvm)
8051{
8052 atomic_dec(&kvm->arch.assigned_device_count);
8053}
8054EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8055
8056bool kvm_arch_has_assigned_device(struct kvm *kvm)
8057{
8058 return atomic_read(&kvm->arch.assigned_device_count);
8059}
8060EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8061
e0f0bbc5
AW		 8062void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8063{
8064 atomic_inc(&kvm->arch.noncoherent_dma_count);
8065}
8066EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8067
8068void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8069{
8070 atomic_dec(&kvm->arch.noncoherent_dma_count);
8071}
8072EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8073
8074bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8075{
8076 return atomic_read(&kvm->arch.noncoherent_dma_count);
8077}
8078EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8079
229456fc 8080EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8081EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8082EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8083EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8084EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8085EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
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