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KVM, pkeys: introduce pkru_mask to cache conditions
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
42bdf991 703 kvm_put_guest_xcr0(vcpu);
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP;
727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
a03490ed 743 if (is_long_mode(vcpu)) {
0f12244f
GN		 744 if (!(cr4 & X86_CR4_PAE))
745 return 1;
a2edf57f
AK		 746 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
747 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 748 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
749 kvm_read_cr3(vcpu)))
0f12244f
GN		 750 return 1;
751
ad756a16
MJ		 752 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
753 if (!guest_cpuid_has_pcid(vcpu))
754 return 1;
755
756 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
757 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
758 return 1;
759 }
760
5e1746d6 761 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 762 return 1;
a03490ed 763
ad756a16
MJ		 764 if (((cr4 ^ old_cr4) & pdptr_bits) ||
765 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 766 kvm_mmu_reset_context(vcpu);
0f12244f 767
2acf923e 768 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 769 kvm_update_cpuid(vcpu);
2acf923e 770
0f12244f
GN		 771 return 0;
772}
2d3ad1f4 773EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 774
2390218b 775int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 776{
ac146235 777#ifdef CONFIG_X86_64
9d88fca7 778 cr3 &= ~CR3_PCID_INVD;
ac146235 779#endif
9d88fca7 780
9f8fe504 781 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 782 kvm_mmu_sync_roots(vcpu);
77c3913b 783 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 784 return 0;
d835dfec
AK		 785 }
786
a03490ed 787 if (is_long_mode(vcpu)) {
d9f89b88
JK		 788 if (cr3 & CR3_L_MODE_RESERVED_BITS)
789 return 1;
790 } else if (is_pae(vcpu) && is_paging(vcpu) &&
791 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 792 return 1;
a03490ed 793
0f12244f 794 vcpu->arch.cr3 = cr3;
aff48baa 795 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 796 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 800
eea1cff9 801int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 802{
0f12244f
GN		 803 if (cr8 & CR8_RESERVED_BITS)
804 return 1;
35754c98 805 if (lapic_in_kernel(vcpu))
a03490ed
CO		 806 kvm_lapic_set_tpr(vcpu, cr8);
807 else
ad312c7c 808 vcpu->arch.cr8 = cr8;
0f12244f
GN		 809 return 0;
810}
2d3ad1f4 811EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 812
2d3ad1f4 813unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 814{
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 return kvm_lapic_get_cr8(vcpu);
817 else
ad312c7c 818 return vcpu->arch.cr8;
a03490ed 819}
2d3ad1f4 820EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 821
ae561ede
NA		 822static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
823{
824 int i;
825
826 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
827 for (i = 0; i < KVM_NR_DB_REGS; i++)
828 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
830 }
831}
832
73aaf249
JK		 833static void kvm_update_dr6(struct kvm_vcpu *vcpu)
834{
835 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
836 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
837}
838
c8639010
JK		 839static void kvm_update_dr7(struct kvm_vcpu *vcpu)
840{
841 unsigned long dr7;
842
843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
844 dr7 = vcpu->arch.guest_debug_dr7;
845 else
846 dr7 = vcpu->arch.dr7;
847 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 848 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
849 if (dr7 & DR7_BP_EN_MASK)
850 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 851}
852
6f43ed01
NA		 853static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
854{
855 u64 fixed = DR6_FIXED_1;
856
857 if (!guest_cpuid_has_rtm(vcpu))
858 fixed |= DR6_RTM;
859 return fixed;
860}
861
338dbc97 862static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 863{
864 switch (dr) {
865 case 0 ... 3:
866 vcpu->arch.db[dr] = val;
867 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
868 vcpu->arch.eff_db[dr] = val;
869 break;
870 case 4:
020df079
GN		 871 /* fall through */
872 case 6:
338dbc97
GN		 873 if (val & 0xffffffff00000000ULL)
874 return -1; /* #GP */
6f43ed01 875 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 876 kvm_update_dr6(vcpu);
020df079
GN		 877 break;
878 case 5:
020df079
GN		 879 /* fall through */
880 default: /* 7 */
338dbc97
GN		 881 if (val & 0xffffffff00000000ULL)
882 return -1; /* #GP */
020df079 883 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 884 kvm_update_dr7(vcpu);
020df079
GN		 885 break;
886 }
887
888 return 0;
889}
338dbc97
GN		 890
891int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
892{
16f8a6f9 893 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 894 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 895 return 1;
896 }
897 return 0;
338dbc97 898}
020df079
GN		 899EXPORT_SYMBOL_GPL(kvm_set_dr);
900
16f8a6f9 901int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 902{
903 switch (dr) {
904 case 0 ... 3:
905 *val = vcpu->arch.db[dr];
906 break;
907 case 4:
020df079
GN		 908 /* fall through */
909 case 6:
73aaf249
JK		 910 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
911 *val = vcpu->arch.dr6;
912 else
913 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 914 break;
915 case 5:
020df079
GN		 916 /* fall through */
917 default: /* 7 */
918 *val = vcpu->arch.dr7;
919 break;
920 }
338dbc97
GN		 921 return 0;
922}
020df079
GN		 923EXPORT_SYMBOL_GPL(kvm_get_dr);
924
022cd0e8
AK		 925bool kvm_rdpmc(struct kvm_vcpu *vcpu)
926{
927 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
928 u64 data;
929 int err;
930
c6702c9d 931 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 932 if (err)
933 return err;
934 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
935 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
936 return err;
937}
938EXPORT_SYMBOL_GPL(kvm_rdpmc);
939
043405e1
CO		 940/*
941 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
942 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
943 *
944 * This list is modified at module load time to reflect the
e3267cbb 945 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 946 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
947 * may depend on host virtualization features rather than host cpu features.
043405e1 948 */
e3267cbb 949
043405e1
CO		 950static u32 msrs_to_save[] = {
951 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 952 MSR_STAR,
043405e1
CO		 953#ifdef CONFIG_X86_64
954 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
955#endif
b3897a49 956 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 957 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 958};
959
960static unsigned num_msrs_to_save;
961
62ef68bb
PB		 962static u32 emulated_msrs[] = {
963 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
964 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
965 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
966 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 967 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
968 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 969 HV_X64_MSR_RESET,
11c4b1ca 970 HV_X64_MSR_VP_INDEX,
9eec50b8 971 HV_X64_MSR_VP_RUNTIME,
5c919412 972 HV_X64_MSR_SCONTROL,
1f4b34f8 973 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 974 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
975 MSR_KVM_PV_EOI_EN,
976
ba904635 977 MSR_IA32_TSC_ADJUST,
a3e06bbe 978 MSR_IA32_TSCDEADLINE,
043405e1 979 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 980 MSR_IA32_MCG_STATUS,
981 MSR_IA32_MCG_CTL,
64d60670 982 MSR_IA32_SMBASE,
043405e1
CO		 983};
984
62ef68bb
PB		 985static unsigned num_emulated_msrs;
986
384bb783 987bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 988{
b69e8cae 989 if (efer & efer_reserved_bits)
384bb783 990 return false;
15c4a640 991
1b2fd70c
AG		 992 if (efer & EFER_FFXSR) {
993 struct kvm_cpuid_entry2 *feat;
994
995 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 996 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 997 return false;
1b2fd70c
AG		 998 }
999
d8017474
AG		 1000 if (efer & EFER_SVME) {
1001 struct kvm_cpuid_entry2 *feat;
1002
1003 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1004 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1005 return false;
d8017474
AG		 1006 }
1007
384bb783
JK		 1008 return true;
1009}
1010EXPORT_SYMBOL_GPL(kvm_valid_efer);
1011
1012static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1013{
1014 u64 old_efer = vcpu->arch.efer;
1015
1016 if (!kvm_valid_efer(vcpu, efer))
1017 return 1;
1018
1019 if (is_paging(vcpu)
1020 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1021 return 1;
1022
15c4a640 1023 efer &= ~EFER_LMA;
f6801dff 1024 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1025
a3d204e2
SY		 1026 kvm_x86_ops->set_efer(vcpu, efer);
1027
aad82703
SY		 1028 /* Update reserved bits */
1029 if ((efer ^ old_efer) & EFER_NX)
1030 kvm_mmu_reset_context(vcpu);
1031
b69e8cae 1032 return 0;
15c4a640
CO		 1033}
1034
f2b4b7dd
JR		 1035void kvm_enable_efer_bits(u64 mask)
1036{
1037 efer_reserved_bits &= ~mask;
1038}
1039EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1040
15c4a640
CO		 1041/*
1042 * Writes msr value into into the appropriate "register".
1043 * Returns 0 on success, non-0 otherwise.
1044 * Assumes vcpu_load() was already called.
1045 */
8fe8ab46 1046int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1047{
854e8bb1
NA		 1048 switch (msr->index) {
1049 case MSR_FS_BASE:
1050 case MSR_GS_BASE:
1051 case MSR_KERNEL_GS_BASE:
1052 case MSR_CSTAR:
1053 case MSR_LSTAR:
1054 if (is_noncanonical_address(msr->data))
1055 return 1;
1056 break;
1057 case MSR_IA32_SYSENTER_EIP:
1058 case MSR_IA32_SYSENTER_ESP:
1059 /*
1060 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1061 * non-canonical address is written on Intel but not on
1062 * AMD (which ignores the top 32-bits, because it does
1063 * not implement 64-bit SYSENTER).
1064 *
1065 * 64-bit code should hence be able to write a non-canonical
1066 * value on AMD. Making the address canonical ensures that
1067 * vmentry does not fail on Intel after writing a non-canonical
1068 * value, and that something deterministic happens if the guest
1069 * invokes 64-bit SYSENTER.
1070 */
1071 msr->data = get_canonical(msr->data);
1072 }
8fe8ab46 1073 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1074}
854e8bb1 1075EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1076
313a3dc7
CO		 1077/*
1078 * Adapt set_msr() to msr_io()'s calling convention
1079 */
609e36d3
PB		 1080static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1081{
1082 struct msr_data msr;
1083 int r;
1084
1085 msr.index = index;
1086 msr.host_initiated = true;
1087 r = kvm_get_msr(vcpu, &msr);
1088 if (r)
1089 return r;
1090
1091 *data = msr.data;
1092 return 0;
1093}
1094
313a3dc7
CO		 1095static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1096{
8fe8ab46
WA		 1097 struct msr_data msr;
1098
1099 msr.data = *data;
1100 msr.index = index;
1101 msr.host_initiated = true;
1102 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1103}
1104
16e8d74d
MT		 1105#ifdef CONFIG_X86_64
1106struct pvclock_gtod_data {
1107 seqcount_t seq;
1108
1109 struct { /* extract of a clocksource struct */
1110 int vclock_mode;
1111 cycle_t cycle_last;
1112 cycle_t mask;
1113 u32 mult;
1114 u32 shift;
1115 } clock;
1116
cbcf2dd3
TG		 1117 u64 boot_ns;
1118 u64 nsec_base;
16e8d74d
MT		 1119};
1120
1121static struct pvclock_gtod_data pvclock_gtod_data;
1122
1123static void update_pvclock_gtod(struct timekeeper *tk)
1124{
1125 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1126 u64 boot_ns;
1127
876e7881 1128 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1129
1130 write_seqcount_begin(&vdata->seq);
1131
1132 /* copy pvclock gtod data */
876e7881
PZ		 1133 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1134 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1135 vdata->clock.mask = tk->tkr_mono.mask;
1136 vdata->clock.mult = tk->tkr_mono.mult;
1137 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1138
cbcf2dd3 1139 vdata->boot_ns = boot_ns;
876e7881 1140 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1141
1142 write_seqcount_end(&vdata->seq);
1143}
1144#endif
1145
bab5bb39
NK		 1146void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1147{
1148 /*
1149 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1150 * vcpu_enter_guest. This function is only called from
1151 * the physical CPU that is running vcpu.
1152 */
1153 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1154}
16e8d74d 1155
18068523
GOC		 1156static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1157{
9ed3c444
AK		 1158 int version;
1159 int r;
50d0a0f9 1160 struct pvclock_wall_clock wc;
923de3cf 1161 struct timespec boot;
18068523
GOC		 1162
1163 if (!wall_clock)
1164 return;
1165
9ed3c444
AK		 1166 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1167 if (r)
1168 return;
1169
1170 if (version & 1)
1171 ++version; /* first time write, random junk */
1172
1173 ++version;
18068523 1174
1dab1345
NK		 1175 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1176 return;
18068523 1177
50d0a0f9
GH		 1178 /*
1179 * The guest calculates current wall clock time by adding
34c238a1 1180 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1181 * wall clock specified here. guest system time equals host
1182 * system time for us, thus we must fill in host boot time here.
1183 */
923de3cf 1184 getboottime(&boot);
50d0a0f9 1185
4b648665
BR		 1186 if (kvm->arch.kvmclock_offset) {
1187 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1188 boot = timespec_sub(boot, ts);
1189 }
50d0a0f9
GH		 1190 wc.sec = boot.tv_sec;
1191 wc.nsec = boot.tv_nsec;
1192 wc.version = version;
18068523
GOC		 1193
1194 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1195
1196 version++;
1197 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1198}
1199
50d0a0f9
GH		 1200static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1201{
b51012de
PB		 1202 do_shl32_div32(dividend, divisor);
1203 return dividend;
50d0a0f9
GH		 1204}
1205
3ae13faa 1206static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1207 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1208{
5f4e3f88 1209 uint64_t scaled64;
50d0a0f9
GH		 1210 int32_t shift = 0;
1211 uint64_t tps64;
1212 uint32_t tps32;
1213
3ae13faa
PB		 1214 tps64 = base_hz;
1215 scaled64 = scaled_hz;
50933623 1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1217 tps64 >>= 1;
1218 shift--;
1219 }
1220
1221 tps32 = (uint32_t)tps64;
50933623
JK		 1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1224 scaled64 >>= 1;
1225 else
1226 tps32 <<= 1;
50d0a0f9
GH		 1227 shift++;
1228 }
1229
5f4e3f88
ZA		 1230 *pshift = shift;
1231 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1232
3ae13faa
PB		 1233 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1234 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1235}
1236
d828199e 1237#ifdef CONFIG_X86_64
16e8d74d 1238static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1239#endif
16e8d74d 1240
c8076604 1241static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1242static unsigned long max_tsc_khz;
c8076604 1243
cc578287 1244static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1245{
cc578287
ZA		 1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1248}
1249
cc578287 1250static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1251{
cc578287
ZA		 1252 u64 v = (u64)khz * (1000000 + ppm);
1253 do_div(v, 1000000);
1254 return v;
1e993611
JR		 1255}
1256
381d585c
HZ		 1257static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1258{
1259 u64 ratio;
1260
1261 /* Guest TSC same frequency as host TSC? */
1262 if (!scale) {
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1264 return 0;
1265 }
1266
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1272 return 0;
1273 } else {
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1282
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1285 user_tsc_khz);
1286 return -1;
1287 }
1288
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1290 return 0;
1291}
1292
4941b8cb 1293static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1294{
cc578287
ZA		 1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
217fc9cf 1297
03ba32ca 1298 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1299 if (user_tsc_khz == 0) {
ad721883
HZ		 1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1302 return -1;
ad721883 1303 }
03ba32ca 1304
c285545f 1305 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1306 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1309 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1310
1311 /*
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1316 */
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1319 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1321 use_scaling = 1;
1322 }
4941b8cb 1323 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1324}
1325
1326static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1327{
e26101b1 1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
e26101b1 1331 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1332 return tsc;
1333}
1334
69b0049a 1335static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1336{
1337#ifdef CONFIG_X86_64
1338 bool vcpus_matched;
b48aa97e
MT		 1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1341
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1344
7f187922
MT		 1345 /*
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1348 *
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1352 */
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1356
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1360#endif
1361}
1362
ba904635
WA		 1363static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1364{
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1367}
1368
35181e86
HZ		 1369/*
1370 * Multiply tsc by a fixed point number represented by ratio.
1371 *
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1376 *
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1378 */
1379static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1380{
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1382}
1383
1384u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1385{
1386 u64 _tsc = tsc;
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1388
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1391
1392 return _tsc;
1393}
1394EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1395
07c1419a
HZ		 1396static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1397{
1398 u64 tsc;
1399
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1401
1402 return target_tsc - tsc;
1403}
1404
4ba76538
HZ		 1405u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1406{
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1408}
1409EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1410
8fe8ab46 1411void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1412{
1413 struct kvm *kvm = vcpu->kvm;
f38e098f 1414 u64 offset, ns, elapsed;
99e3e30a 1415 unsigned long flags;
02626b6a 1416 s64 usdiff;
b48aa97e 1417 bool matched;
0d3da0d2 1418 bool already_matched;
8fe8ab46 1419 u64 data = msr->data;
99e3e30a 1420
038f8c11 1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1422 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1423 ns = get_kernel_ns();
f38e098f 1424 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1425
03ba32ca 1426 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1427 int faulted = 0;
1428
03ba32ca
MT		 1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1431#ifdef CONFIG_X86_64
03ba32ca 1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1433#else
03ba32ca 1434 /* do_div() only does unsigned */
8915aa27
MT		 1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1438 "3:\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1441 " jmp 3b\n"
1442 ".previous\n"
1443
1444 _ASM_EXTABLE(1b, 4b)
1445
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1448
5d3cb0f6 1449#endif
03ba32ca
MT		 1450 do_div(elapsed, 1000);
1451 usdiff -= elapsed;
1452 if (usdiff < 0)
1453 usdiff = -usdiff;
8915aa27
MT		 1454
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1456 if (faulted)
1457 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1458 } else
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1460
1461 /*
5d3cb0f6
ZA		 1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1465 *
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1470 */
02626b6a 1471 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1473 if (!check_tsc_unstable()) {
e26101b1 1474 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1476 } else {
857e4099 1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1478 data += delta;
07c1419a 1479 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1481 }
b48aa97e 1482 matched = true;
0d3da0d2 1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1484 } else {
1485 /*
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
4a969980 1490 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1491 *
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1493 */
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1498 matched = false;
0d3da0d2 1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1500 kvm->arch.cur_tsc_generation, data);
f38e098f 1501 }
e26101b1
ZA		 1502
1503 /*
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1506 */
f38e098f
ZA		 1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
5d3cb0f6 1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1510
b183aa58 1511 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1512
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1517
ba904635
WA		 1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1522
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1524 if (!matched) {
b48aa97e 1525 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1528 }
b48aa97e
MT		 1529
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1532}
e26101b1 1533
99e3e30a
ZA		 1534EXPORT_SYMBOL_GPL(kvm_write_tsc);
1535
58ea6767
HZ		 1536static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1537 s64 adjustment)
1538{
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1540}
1541
1542static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1543{
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1548}
1549
d828199e
MT		 1550#ifdef CONFIG_X86_64
1551
1552static cycle_t read_tsc(void)
1553{
03b9730b
AL		 1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1556
1557 if (likely(ret >= last))
1558 return ret;
1559
1560 /*
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1567 */
1568 asm volatile ("");
1569 return last;
1570}
1571
1572static inline u64 vgettsc(cycle_t *cycle_now)
1573{
1574 long v;
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1576
1577 *cycle_now = read_tsc();
1578
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1581}
1582
cbcf2dd3 1583static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1584{
cbcf2dd3 1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1586 unsigned long seq;
d828199e 1587 int mode;
cbcf2dd3 1588 u64 ns;
d828199e 1589
d828199e
MT		 1590 do {
1591 seq = read_seqcount_begin(&gtod->seq);
1592 mode = gtod->clock.vclock_mode;
cbcf2dd3 1593 ns = gtod->nsec_base;
d828199e
MT		 1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
cbcf2dd3 1596 ns += gtod->boot_ns;
d828199e 1597 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1598 *t = ns;
d828199e
MT		 1599
1600 return mode;
1601}
1602
1603/* returns true if host is using tsc clocksource */
1604static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1605{
d828199e
MT		 1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1608 return false;
1609
cbcf2dd3 1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1611}
1612#endif
1613
1614/*
1615 *
b48aa97e
MT		 1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
d828199e
MT		 1619 * CPUs at the next numbered event.
1620 *
1621 * "timespecX" represents host monotonic time. "tscX" represents
1622 * RDTSC value.
1623 *
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1625 *
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1628 * | tsc1 = tsc0 + M
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1633 *
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1635 *
1636 * - ret0 < ret1
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1638 * ...
1639 * - 0 < N - M => M < N
1640 *
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1645 *
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1649 * in lockstep.
1650 *
b48aa97e 1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1652 *
1653 */
1654
1655static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1656{
1657#ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1659 int vclock_mode;
b48aa97e
MT		 1660 bool host_tsc_clocksource, vcpus_matched;
1661
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1664
1665 /*
1666 * If the host uses TSC clock, then passthrough TSC as stable
1667 * to the guest.
1668 */
b48aa97e 1669 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1672
16a96021 1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1676
d828199e
MT		 1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1679
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1682 vcpus_matched);
d828199e
MT		 1683#endif
1684}
1685
2860c4b1
PB		 1686void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1687{
1688 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1689}
1690
2e762ff7
MT		 1691static void kvm_gen_update_masterclock(struct kvm *kvm)
1692{
1693#ifdef CONFIG_X86_64
1694 int i;
1695 struct kvm_vcpu *vcpu;
1696 struct kvm_arch *ka = &kvm->arch;
1697
1698 spin_lock(&ka->pvclock_gtod_sync_lock);
1699 kvm_make_mclock_inprogress_request(kvm);
1700 /* no guest entries from this point */
1701 pvclock_update_vm_gtod_copy(kvm);
1702
1703 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1705
1706 /* guest entries allowed */
1707 kvm_for_each_vcpu(i, vcpu, kvm)
1708 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1709
1710 spin_unlock(&ka->pvclock_gtod_sync_lock);
1711#endif
1712}
1713
34c238a1 1714static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1715{
78db6a50 1716 unsigned long flags, tgt_tsc_khz;
18068523 1717 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1718 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1719 s64 kernel_ns;
d828199e 1720 u64 tsc_timestamp, host_tsc;
0b79459b 1721 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1722 u8 pvclock_flags;
d828199e
MT		 1723 bool use_master_clock;
1724
1725 kernel_ns = 0;
1726 host_tsc = 0;
18068523 1727
d828199e
MT		 1728 /*
1729 * If the host uses TSC clock, then passthrough TSC as stable
1730 * to the guest.
1731 */
1732 spin_lock(&ka->pvclock_gtod_sync_lock);
1733 use_master_clock = ka->use_master_clock;
1734 if (use_master_clock) {
1735 host_tsc = ka->master_cycle_now;
1736 kernel_ns = ka->master_kernel_ns;
1737 }
1738 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1739
1740 /* Keep irq disabled to prevent changes to the clock */
1741 local_irq_save(flags);
78db6a50
PB		 1742 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1743 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1744 local_irq_restore(flags);
1745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1746 return 1;
1747 }
d828199e 1748 if (!use_master_clock) {
4ea1636b 1749 host_tsc = rdtsc();
d828199e
MT		 1750 kernel_ns = get_kernel_ns();
1751 }
1752
4ba76538 1753 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1754
c285545f
ZA		 1755 /*
1756 * We may have to catch up the TSC to match elapsed wall clock
1757 * time for two reasons, even if kvmclock is used.
1758 * 1) CPU could have been running below the maximum TSC rate
1759 * 2) Broken TSC compensation resets the base at each VCPU
1760 * entry to avoid unknown leaps of TSC even when running
1761 * again on the same CPU. This may cause apparent elapsed
1762 * time to disappear, and the guest to stand still or run
1763 * very slowly.
1764 */
1765 if (vcpu->tsc_catchup) {
1766 u64 tsc = compute_guest_tsc(v, kernel_ns);
1767 if (tsc > tsc_timestamp) {
f1e2b260 1768 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1769 tsc_timestamp = tsc;
1770 }
50d0a0f9
GH		 1771 }
1772
18068523
GOC		 1773 local_irq_restore(flags);
1774
0b79459b 1775 if (!vcpu->pv_time_enabled)
c285545f 1776 return 0;
18068523 1777
78db6a50
PB		 1778 if (kvm_has_tsc_control)
1779 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1780
1781 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1782 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1783 &vcpu->hv_clock.tsc_shift,
1784 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1785 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1786 }
1787
1788 /* With all the info we got, fill in the values */
1d5f066e 1789 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1790 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1791 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1792
09a0c3f1
OH		 1793 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1794 &guest_hv_clock, sizeof(guest_hv_clock))))
1795 return 0;
1796
5dca0d91
RK		 1797 /* This VCPU is paused, but it's legal for a guest to read another
1798 * VCPU's kvmclock, so we really have to follow the specification where
1799 * it says that version is odd if data is being modified, and even after
1800 * it is consistent.
1801 *
1802 * Version field updates must be kept separate. This is because
1803 * kvm_write_guest_cached might use a "rep movs" instruction, and
1804 * writes within a string instruction are weakly ordered. So there
1805 * are three writes overall.
1806 *
1807 * As a small optimization, only write the version field in the first
1808 * and third write. The vcpu->pv_time cache is still valid, because the
1809 * version field is the first in the struct.
18068523 1810 */
5dca0d91
RK		 1811 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1812
1813 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1814 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1815 &vcpu->hv_clock,
1816 sizeof(vcpu->hv_clock.version));
1817
1818 smp_wmb();
78c0337a
MT		 1819
1820 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1821 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1822
1823 if (vcpu->pvclock_set_guest_stopped_request) {
1824 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1825 vcpu->pvclock_set_guest_stopped_request = false;
1826 }
1827
d828199e
MT		 1828 /* If the host uses TSC clocksource, then it is stable */
1829 if (use_master_clock)
1830 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1831
78c0337a
MT		 1832 vcpu->hv_clock.flags = pvclock_flags;
1833
ce1a5e60
DM		 1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1835
0b79459b
AH		 1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1839
1840 smp_wmb();
1841
1842 vcpu->hv_clock.version++;
1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
8cfdc000 1846 return 0;
c8076604
GH		 1847}
1848
0061d53d
MT		 1849/*
1850 * kvmclock updates which are isolated to a given vcpu, such as
1851 * vcpu->cpu migration, should not allow system_timestamp from
1852 * the rest of the vcpus to remain static. Otherwise ntp frequency
1853 * correction applies to one vcpu's system_timestamp but not
1854 * the others.
1855 *
1856 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1857 * We need to rate-limit these requests though, as they can
1858 * considerably slow guests that have a large number of vcpus.
1859 * The time for a remote vcpu to update its kvmclock is bound
1860 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1861 */
1862
7e44e449
AJ		 1863#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1864
1865static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1866{
1867 int i;
7e44e449
AJ		 1868 struct delayed_work *dwork = to_delayed_work(work);
1869 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1870 kvmclock_update_work);
1871 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1872 struct kvm_vcpu *vcpu;
1873
1874 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1876 kvm_vcpu_kick(vcpu);
1877 }
1878}
1879
7e44e449
AJ		 1880static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1881{
1882 struct kvm *kvm = v->kvm;
1883
105b21bb 1884 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1885 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1886 KVMCLOCK_UPDATE_DELAY);
1887}
1888
332967a3
AJ		 1889#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1890
1891static void kvmclock_sync_fn(struct work_struct *work)
1892{
1893 struct delayed_work *dwork = to_delayed_work(work);
1894 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1895 kvmclock_sync_work);
1896 struct kvm *kvm = container_of(ka, struct kvm, arch);
1897
630994b3
MT		 1898 if (!kvmclock_periodic_sync)
1899 return;
1900
332967a3
AJ		 1901 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1902 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1903 KVMCLOCK_SYNC_PERIOD);
1904}
1905
890ca9ae 1906static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1907{
890ca9ae
HY		 1908 u64 mcg_cap = vcpu->arch.mcg_cap;
1909 unsigned bank_num = mcg_cap & 0xff;
1910
15c4a640 1911 switch (msr) {
15c4a640 1912 case MSR_IA32_MCG_STATUS:
890ca9ae 1913 vcpu->arch.mcg_status = data;
15c4a640 1914 break;
c7ac679c 1915 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1916 if (!(mcg_cap & MCG_CTL_P))
1917 return 1;
1918 if (data != 0 && data != ~(u64)0)
1919 return -1;
1920 vcpu->arch.mcg_ctl = data;
1921 break;
1922 default:
1923 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1924 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1925 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1926 /* only 0 or all 1s can be written to IA32_MCi_CTL
1927 * some Linux kernels though clear bit 10 in bank 4 to
1928 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1929 * this to avoid an uncatched #GP in the guest
1930 */
890ca9ae 1931 if ((offset & 0x3) == 0 &&
114be429 1932 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1933 return -1;
1934 vcpu->arch.mce_banks[offset] = data;
1935 break;
1936 }
1937 return 1;
1938 }
1939 return 0;
1940}
1941
ffde22ac
ES		 1942static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1943{
1944 struct kvm *kvm = vcpu->kvm;
1945 int lm = is_long_mode(vcpu);
1946 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1947 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1948 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1949 : kvm->arch.xen_hvm_config.blob_size_32;
1950 u32 page_num = data & ~PAGE_MASK;
1951 u64 page_addr = data & PAGE_MASK;
1952 u8 *page;
1953 int r;
1954
1955 r = -E2BIG;
1956 if (page_num >= blob_size)
1957 goto out;
1958 r = -ENOMEM;
ff5c2c03
SL		 1959 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1960 if (IS_ERR(page)) {
1961 r = PTR_ERR(page);
ffde22ac 1962 goto out;
ff5c2c03 1963 }
54bf36aa 1964 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1965 goto out_free;
1966 r = 0;
1967out_free:
1968 kfree(page);
1969out:
1970 return r;
1971}
1972
344d9588
GN		 1973static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1974{
1975 gpa_t gpa = data & ~0x3f;
1976
4a969980 1977 /* Bits 2:5 are reserved, Should be zero */
6adba527 1978 if (data & 0x3c)
344d9588
GN		 1979 return 1;
1980
1981 vcpu->arch.apf.msr_val = data;
1982
1983 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1984 kvm_clear_async_pf_completion_queue(vcpu);
1985 kvm_async_pf_hash_reset(vcpu);
1986 return 0;
1987 }
1988
8f964525
AH		 1989 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1990 sizeof(u32)))
344d9588
GN		 1991 return 1;
1992
6adba527 1993 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1994 kvm_async_pf_wakeup_all(vcpu);
1995 return 0;
1996}
1997
12f9a48f
GC		 1998static void kvmclock_reset(struct kvm_vcpu *vcpu)
1999{
0b79459b 2000 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2001}
2002
c9aaa895
GC		 2003static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2004{
2005 u64 delta;
2006
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2008 return;
2009
2010 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2011 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2012 vcpu->arch.st.accum_steal = delta;
2013}
2014
2015static void record_steal_time(struct kvm_vcpu *vcpu)
2016{
7cae2bed
MT		 2017 accumulate_steal_time(vcpu);
2018
c9aaa895
GC		 2019 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2020 return;
2021
2022 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2023 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2024 return;
2025
2026 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2027 vcpu->arch.st.steal.version += 2;
2028 vcpu->arch.st.accum_steal = 0;
2029
2030 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2031 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2032}
2033
8fe8ab46 2034int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2035{
5753785f 2036 bool pr = false;
8fe8ab46
WA		 2037 u32 msr = msr_info->index;
2038 u64 data = msr_info->data;
5753785f 2039
15c4a640 2040 switch (msr) {
2e32b719
BP		 2041 case MSR_AMD64_NB_CFG:
2042 case MSR_IA32_UCODE_REV:
2043 case MSR_IA32_UCODE_WRITE:
2044 case MSR_VM_HSAVE_PA:
2045 case MSR_AMD64_PATCH_LOADER:
2046 case MSR_AMD64_BU_CFG2:
2047 break;
2048
15c4a640 2049 case MSR_EFER:
b69e8cae 2050 return set_efer(vcpu, data);
8f1589d9
AP		 2051 case MSR_K7_HWCR:
2052 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2053 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2054 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2055 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2056 if (data != 0) {
a737f256
CD		 2057 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2058 data);
8f1589d9
AP		 2059 return 1;
2060 }
15c4a640 2061 break;
f7c6d140
AP		 2062 case MSR_FAM10H_MMIO_CONF_BASE:
2063 if (data != 0) {
a737f256
CD		 2064 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2065 "0x%llx\n", data);
f7c6d140
AP		 2066 return 1;
2067 }
15c4a640 2068 break;
b5e2fec0
AG		 2069 case MSR_IA32_DEBUGCTLMSR:
2070 if (!data) {
2071 /* We support the non-activated case already */
2072 break;
2073 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2074 /* Values other than LBR and BTF are vendor-specific,
2075 thus reserved and should throw a #GP */
2076 return 1;
2077 }
a737f256
CD		 2078 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2079 __func__, data);
b5e2fec0 2080 break;
9ba075a6 2081 case 0x200 ... 0x2ff:
ff53604b 2082 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2083 case MSR_IA32_APICBASE:
58cb628d 2084 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2085 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2086 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2087 case MSR_IA32_TSCDEADLINE:
2088 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2089 break;
ba904635
WA		 2090 case MSR_IA32_TSC_ADJUST:
2091 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2092 if (!msr_info->host_initiated) {
d913b904 2093 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2094 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2095 }
2096 vcpu->arch.ia32_tsc_adjust_msr = data;
2097 }
2098 break;
15c4a640 2099 case MSR_IA32_MISC_ENABLE:
ad312c7c 2100 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2101 break;
64d60670
PB		 2102 case MSR_IA32_SMBASE:
2103 if (!msr_info->host_initiated)
2104 return 1;
2105 vcpu->arch.smbase = data;
2106 break;
11c6bffa 2107 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2108 case MSR_KVM_WALL_CLOCK:
2109 vcpu->kvm->arch.wall_clock = data;
2110 kvm_write_wall_clock(vcpu->kvm, data);
2111 break;
11c6bffa 2112 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2113 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2114 u64 gpa_offset;
54750f2c
MT		 2115 struct kvm_arch *ka = &vcpu->kvm->arch;
2116
12f9a48f 2117 kvmclock_reset(vcpu);
18068523 2118
54750f2c
MT		 2119 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2120 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2121
2122 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2123 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2124 &vcpu->requests);
2125
2126 ka->boot_vcpu_runs_old_kvmclock = tmp;
2127 }
2128
18068523 2129 vcpu->arch.time = data;
0061d53d 2130 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2131
2132 /* we verify if the enable bit is set... */
2133 if (!(data & 1))
2134 break;
2135
0b79459b 2136 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2137
0b79459b 2138 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2139 &vcpu->arch.pv_time, data & ~1ULL,
2140 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2141 vcpu->arch.pv_time_enabled = false;
2142 else
2143 vcpu->arch.pv_time_enabled = true;
32cad84f 2144
18068523
GOC		 2145 break;
2146 }
344d9588
GN		 2147 case MSR_KVM_ASYNC_PF_EN:
2148 if (kvm_pv_enable_async_pf(vcpu, data))
2149 return 1;
2150 break;
c9aaa895
GC		 2151 case MSR_KVM_STEAL_TIME:
2152
2153 if (unlikely(!sched_info_on()))
2154 return 1;
2155
2156 if (data & KVM_STEAL_RESERVED_MASK)
2157 return 1;
2158
2159 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2160 data & KVM_STEAL_VALID_BITS,
2161 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2162 return 1;
2163
2164 vcpu->arch.st.msr_val = data;
2165
2166 if (!(data & KVM_MSR_ENABLED))
2167 break;
2168
c9aaa895
GC		 2169 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2170
2171 break;
ae7a2a3f
MT		 2172 case MSR_KVM_PV_EOI_EN:
2173 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2174 return 1;
2175 break;
c9aaa895 2176
890ca9ae
HY		 2177 case MSR_IA32_MCG_CTL:
2178 case MSR_IA32_MCG_STATUS:
81760dcc 2179 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2180 return set_msr_mce(vcpu, msr, data);
71db6023 2181
6912ac32
WH		 2182 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2183 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2184 pr = true; /* fall through */
2185 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2186 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2187 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2188 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2189
2190 if (pr || data != 0)
a737f256
CD		 2191 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2192 "0x%x data 0x%llx\n", msr, data);
5753785f 2193 break;
84e0cefa
JS		 2194 case MSR_K7_CLK_CTL:
2195 /*
2196 * Ignore all writes to this no longer documented MSR.
2197 * Writes are only relevant for old K7 processors,
2198 * all pre-dating SVM, but a recommended workaround from
4a969980 2199 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2200 * affected processor models on the command line, hence
2201 * the need to ignore the workaround.
2202 */
2203 break;
55cd8e5a 2204 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2205 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2206 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2207 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2208 return kvm_hv_set_msr_common(vcpu, msr, data,
2209 msr_info->host_initiated);
91c9c3ed 2210 case MSR_IA32_BBL_CR_CTL3:
2211 /* Drop writes to this legacy MSR -- see rdmsr
2212 * counterpart for further detail.
2213 */
a737f256 2214 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2215 break;
2b036c6b
BO		 2216 case MSR_AMD64_OSVW_ID_LENGTH:
2217 if (!guest_cpuid_has_osvw(vcpu))
2218 return 1;
2219 vcpu->arch.osvw.length = data;
2220 break;
2221 case MSR_AMD64_OSVW_STATUS:
2222 if (!guest_cpuid_has_osvw(vcpu))
2223 return 1;
2224 vcpu->arch.osvw.status = data;
2225 break;
15c4a640 2226 default:
ffde22ac
ES		 2227 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2228 return xen_hvm_config(vcpu, data);
c6702c9d 2229 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2230 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2231 if (!ignore_msrs) {
a737f256
CD		 2232 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2233 msr, data);
ed85c068
AP		 2234 return 1;
2235 } else {
a737f256
CD		 2236 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2237 msr, data);
ed85c068
AP		 2238 break;
2239 }
15c4a640
CO		 2240 }
2241 return 0;
2242}
2243EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2244
2245
2246/*
2247 * Reads an msr value (of 'msr_index') into 'pdata'.
2248 * Returns 0 on success, non-0 otherwise.
2249 * Assumes vcpu_load() was already called.
2250 */
609e36d3 2251int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2252{
609e36d3 2253 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2254}
ff651cb6 2255EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2256
890ca9ae 2257static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2258{
2259 u64 data;
890ca9ae
HY		 2260 u64 mcg_cap = vcpu->arch.mcg_cap;
2261 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2262
2263 switch (msr) {
15c4a640
CO		 2264 case MSR_IA32_P5_MC_ADDR:
2265 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2266 data = 0;
2267 break;
15c4a640 2268 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2269 data = vcpu->arch.mcg_cap;
2270 break;
c7ac679c 2271 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2272 if (!(mcg_cap & MCG_CTL_P))
2273 return 1;
2274 data = vcpu->arch.mcg_ctl;
2275 break;
2276 case MSR_IA32_MCG_STATUS:
2277 data = vcpu->arch.mcg_status;
2278 break;
2279 default:
2280 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2281 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2282 u32 offset = msr - MSR_IA32_MC0_CTL;
2283 data = vcpu->arch.mce_banks[offset];
2284 break;
2285 }
2286 return 1;
2287 }
2288 *pdata = data;
2289 return 0;
2290}
2291
609e36d3 2292int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2293{
609e36d3 2294 switch (msr_info->index) {
890ca9ae 2295 case MSR_IA32_PLATFORM_ID:
15c4a640 2296 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2297 case MSR_IA32_DEBUGCTLMSR:
2298 case MSR_IA32_LASTBRANCHFROMIP:
2299 case MSR_IA32_LASTBRANCHTOIP:
2300 case MSR_IA32_LASTINTFROMIP:
2301 case MSR_IA32_LASTINTTOIP:
60af2ecd 2302 case MSR_K8_SYSCFG:
3afb1121
PB		 2303 case MSR_K8_TSEG_ADDR:
2304 case MSR_K8_TSEG_MASK:
60af2ecd 2305 case MSR_K7_HWCR:
61a6bd67 2306 case MSR_VM_HSAVE_PA:
1fdbd48c 2307 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2308 case MSR_AMD64_NB_CFG:
f7c6d140 2309 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2310 case MSR_AMD64_BU_CFG2:
609e36d3 2311 msr_info->data = 0;
15c4a640 2312 break;
6912ac32
WH		 2313 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2314 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2315 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2316 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2317 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2318 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2319 msr_info->data = 0;
5753785f 2320 break;
742bc670 2321 case MSR_IA32_UCODE_REV:
609e36d3 2322 msr_info->data = 0x100000000ULL;
742bc670 2323 break;
9ba075a6 2324 case MSR_MTRRcap:
9ba075a6 2325 case 0x200 ... 0x2ff:
ff53604b 2326 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2327 case 0xcd: /* fsb frequency */
609e36d3 2328 msr_info->data = 3;
15c4a640 2329 break;
7b914098
JS		 2330 /*
2331 * MSR_EBC_FREQUENCY_ID
2332 * Conservative value valid for even the basic CPU models.
2333 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2334 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2335 * and 266MHz for model 3, or 4. Set Core Clock
2336 * Frequency to System Bus Frequency Ratio to 1 (bits
2337 * 31:24) even though these are only valid for CPU
2338 * models > 2, however guests may end up dividing or
2339 * multiplying by zero otherwise.
2340 */
2341 case MSR_EBC_FREQUENCY_ID:
609e36d3 2342 msr_info->data = 1 << 24;
7b914098 2343 break;
15c4a640 2344 case MSR_IA32_APICBASE:
609e36d3 2345 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2346 break;
0105d1a5 2347 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2348 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2349 break;
a3e06bbe 2350 case MSR_IA32_TSCDEADLINE:
609e36d3 2351 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2352 break;
ba904635 2353 case MSR_IA32_TSC_ADJUST:
609e36d3 2354 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2355 break;
15c4a640 2356 case MSR_IA32_MISC_ENABLE:
609e36d3 2357 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2358 break;
64d60670
PB		 2359 case MSR_IA32_SMBASE:
2360 if (!msr_info->host_initiated)
2361 return 1;
2362 msr_info->data = vcpu->arch.smbase;
15c4a640 2363 break;
847f0ad8
AG		 2364 case MSR_IA32_PERF_STATUS:
2365 /* TSC increment by tick */
609e36d3 2366 msr_info->data = 1000ULL;
847f0ad8 2367 /* CPU multiplier */
b0996ae4 2368 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2369 break;
15c4a640 2370 case MSR_EFER:
609e36d3 2371 msr_info->data = vcpu->arch.efer;
15c4a640 2372 break;
18068523 2373 case MSR_KVM_WALL_CLOCK:
11c6bffa 2374 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2375 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2376 break;
2377 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2378 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2379 msr_info->data = vcpu->arch.time;
18068523 2380 break;
344d9588 2381 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2382 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2383 break;
c9aaa895 2384 case MSR_KVM_STEAL_TIME:
609e36d3 2385 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2386 break;
1d92128f 2387 case MSR_KVM_PV_EOI_EN:
609e36d3 2388 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2389 break;
890ca9ae
HY		 2390 case MSR_IA32_P5_MC_ADDR:
2391 case MSR_IA32_P5_MC_TYPE:
2392 case MSR_IA32_MCG_CAP:
2393 case MSR_IA32_MCG_CTL:
2394 case MSR_IA32_MCG_STATUS:
81760dcc 2395 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2396 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2397 case MSR_K7_CLK_CTL:
2398 /*
2399 * Provide expected ramp-up count for K7. All other
2400 * are set to zero, indicating minimum divisors for
2401 * every field.
2402 *
2403 * This prevents guest kernels on AMD host with CPU
2404 * type 6, model 8 and higher from exploding due to
2405 * the rdmsr failing.
2406 */
609e36d3 2407 msr_info->data = 0x20000000;
84e0cefa 2408 break;
55cd8e5a 2409 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2410 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2411 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2412 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2413 return kvm_hv_get_msr_common(vcpu,
2414 msr_info->index, &msr_info->data);
55cd8e5a 2415 break;
91c9c3ed 2416 case MSR_IA32_BBL_CR_CTL3:
2417 /* This legacy MSR exists but isn't fully documented in current
2418 * silicon. It is however accessed by winxp in very narrow
2419 * scenarios where it sets bit #19, itself documented as
2420 * a "reserved" bit. Best effort attempt to source coherent
2421 * read data here should the balance of the register be
2422 * interpreted by the guest:
2423 *
2424 * L2 cache control register 3: 64GB range, 256KB size,
2425 * enabled, latency 0x1, configured
2426 */
609e36d3 2427 msr_info->data = 0xbe702111;
91c9c3ed 2428 break;
2b036c6b
BO		 2429 case MSR_AMD64_OSVW_ID_LENGTH:
2430 if (!guest_cpuid_has_osvw(vcpu))
2431 return 1;
609e36d3 2432 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2433 break;
2434 case MSR_AMD64_OSVW_STATUS:
2435 if (!guest_cpuid_has_osvw(vcpu))
2436 return 1;
609e36d3 2437 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2438 break;
15c4a640 2439 default:
c6702c9d 2440 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2441 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2442 if (!ignore_msrs) {
609e36d3 2443 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2444 return 1;
2445 } else {
609e36d3
PB		 2446 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2447 msr_info->data = 0;
ed85c068
AP		 2448 }
2449 break;
15c4a640 2450 }
15c4a640
CO		 2451 return 0;
2452}
2453EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2454
313a3dc7
CO		 2455/*
2456 * Read or write a bunch of msrs. All parameters are kernel addresses.
2457 *
2458 * @return number of msrs set successfully.
2459 */
2460static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2461 struct kvm_msr_entry *entries,
2462 int (*do_msr)(struct kvm_vcpu *vcpu,
2463 unsigned index, u64 *data))
2464{
f656ce01 2465 int i, idx;
313a3dc7 2466
f656ce01 2467 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2468 for (i = 0; i < msrs->nmsrs; ++i)
2469 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2470 break;
f656ce01 2471 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2472
313a3dc7
CO		 2473 return i;
2474}
2475
2476/*
2477 * Read or write a bunch of msrs. Parameters are user addresses.
2478 *
2479 * @return number of msrs set successfully.
2480 */
2481static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2482 int (*do_msr)(struct kvm_vcpu *vcpu,
2483 unsigned index, u64 *data),
2484 int writeback)
2485{
2486 struct kvm_msrs msrs;
2487 struct kvm_msr_entry *entries;
2488 int r, n;
2489 unsigned size;
2490
2491 r = -EFAULT;
2492 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2493 goto out;
2494
2495 r = -E2BIG;
2496 if (msrs.nmsrs >= MAX_IO_MSRS)
2497 goto out;
2498
313a3dc7 2499 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2500 entries = memdup_user(user_msrs->entries, size);
2501 if (IS_ERR(entries)) {
2502 r = PTR_ERR(entries);
313a3dc7 2503 goto out;
ff5c2c03 2504 }
313a3dc7
CO		 2505
2506 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2507 if (r < 0)
2508 goto out_free;
2509
2510 r = -EFAULT;
2511 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2512 goto out_free;
2513
2514 r = n;
2515
2516out_free:
7a73c028 2517 kfree(entries);
313a3dc7
CO		 2518out:
2519 return r;
2520}
2521
784aa3d7 2522int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2523{
2524 int r;
2525
2526 switch (ext) {
2527 case KVM_CAP_IRQCHIP:
2528 case KVM_CAP_HLT:
2529 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2530 case KVM_CAP_SET_TSS_ADDR:
07716717 2531 case KVM_CAP_EXT_CPUID:
9c15bb1d 2532 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2533 case KVM_CAP_CLOCKSOURCE:
7837699f 2534 case KVM_CAP_PIT:
a28e4f5a 2535 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2536 case KVM_CAP_MP_STATE:
ed848624 2537 case KVM_CAP_SYNC_MMU:
a355c85c 2538 case KVM_CAP_USER_NMI:
52d939a0 2539 case KVM_CAP_REINJECT_CONTROL:
4925663a 2540 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2541 case KVM_CAP_IOEVENTFD:
f848a5a8 2542 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2543 case KVM_CAP_PIT2:
e9f42757 2544 case KVM_CAP_PIT_STATE2:
b927a3ce 2545 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2546 case KVM_CAP_XEN_HVM:
afbcf7ab 2547 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2548 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2549 case KVM_CAP_HYPERV:
10388a07 2550 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2551 case KVM_CAP_HYPERV_SPIN:
5c919412 2552 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2553 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2554 case KVM_CAP_DEBUGREGS:
d2be1651 2555 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2556 case KVM_CAP_XSAVE:
344d9588 2557 case KVM_CAP_ASYNC_PF:
92a1f12d 2558 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2559 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2560 case KVM_CAP_READONLY_MEM:
5f66b620 2561 case KVM_CAP_HYPERV_TIME:
100943c5 2562 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2563 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2564 case KVM_CAP_ENABLE_CAP_VM:
2565 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2566 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2567 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2568#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2569 case KVM_CAP_ASSIGN_DEV_IRQ:
2570 case KVM_CAP_PCI_2_3:
2571#endif
018d00d2
ZX		 2572 r = 1;
2573 break;
6d396b55
PB		 2574 case KVM_CAP_X86_SMM:
2575 /* SMBASE is usually relocated above 1M on modern chipsets,
2576 * and SMM handlers might indeed rely on 4G segment limits,
2577 * so do not report SMM to be available if real mode is
2578 * emulated via vm86 mode. Still, do not go to great lengths
2579 * to avoid userspace's usage of the feature, because it is a
2580 * fringe case that is not enabled except via specific settings
2581 * of the module parameters.
2582 */
2583 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2584 break;
542472b5
LV		 2585 case KVM_CAP_COALESCED_MMIO:
2586 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2587 break;
774ead3a
AK		 2588 case KVM_CAP_VAPIC:
2589 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2590 break;
f725230a 2591 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2592 r = KVM_SOFT_MAX_VCPUS;
2593 break;
2594 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2595 r = KVM_MAX_VCPUS;
2596 break;
a988b910 2597 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2598 r = KVM_USER_MEM_SLOTS;
a988b910 2599 break;
a68a6a72
MT		 2600 case KVM_CAP_PV_MMU: /* obsolete */
2601 r = 0;
2f333bcb 2602 break;
4cee4b72 2603#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2604 case KVM_CAP_IOMMU:
a1b60c1c 2605 r = iommu_present(&pci_bus_type);
62c476c7 2606 break;
4cee4b72 2607#endif
890ca9ae
HY		 2608 case KVM_CAP_MCE:
2609 r = KVM_MAX_MCE_BANKS;
2610 break;
2d5b5a66
SY		 2611 case KVM_CAP_XCRS:
2612 r = cpu_has_xsave;
2613 break;
92a1f12d
JR		 2614 case KVM_CAP_TSC_CONTROL:
2615 r = kvm_has_tsc_control;
2616 break;
018d00d2
ZX		 2617 default:
2618 r = 0;
2619 break;
2620 }
2621 return r;
2622
2623}
2624
043405e1
CO		 2625long kvm_arch_dev_ioctl(struct file *filp,
2626 unsigned int ioctl, unsigned long arg)
2627{
2628 void __user *argp = (void __user *)arg;
2629 long r;
2630
2631 switch (ioctl) {
2632 case KVM_GET_MSR_INDEX_LIST: {
2633 struct kvm_msr_list __user *user_msr_list = argp;
2634 struct kvm_msr_list msr_list;
2635 unsigned n;
2636
2637 r = -EFAULT;
2638 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2639 goto out;
2640 n = msr_list.nmsrs;
62ef68bb 2641 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2642 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2643 goto out;
2644 r = -E2BIG;
e125e7b6 2645 if (n < msr_list.nmsrs)
043405e1
CO		 2646 goto out;
2647 r = -EFAULT;
2648 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2649 num_msrs_to_save * sizeof(u32)))
2650 goto out;
e125e7b6 2651 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2652 &emulated_msrs,
62ef68bb 2653 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2654 goto out;
2655 r = 0;
2656 break;
2657 }
9c15bb1d
BP		 2658 case KVM_GET_SUPPORTED_CPUID:
2659 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2660 struct kvm_cpuid2 __user *cpuid_arg = argp;
2661 struct kvm_cpuid2 cpuid;
2662
2663 r = -EFAULT;
2664 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2665 goto out;
9c15bb1d
BP		 2666
2667 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2668 ioctl);
674eea0f
AK		 2669 if (r)
2670 goto out;
2671
2672 r = -EFAULT;
2673 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
890ca9ae
HY		 2678 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2679 u64 mce_cap;
2680
2681 mce_cap = KVM_MCE_CAP_SUPPORTED;
2682 r = -EFAULT;
2683 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2684 goto out;
2685 r = 0;
2686 break;
2687 }
043405e1
CO		 2688 default:
2689 r = -EINVAL;
2690 }
2691out:
2692 return r;
2693}
2694
f5f48ee1
SY		 2695static void wbinvd_ipi(void *garbage)
2696{
2697 wbinvd();
2698}
2699
2700static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2701{
e0f0bbc5 2702 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2703}
2704
2860c4b1
PB		 2705static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2706{
2707 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2708}
2709
313a3dc7
CO		 2710void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2711{
f5f48ee1
SY		 2712 /* Address WBINVD may be executed by guest */
2713 if (need_emulate_wbinvd(vcpu)) {
2714 if (kvm_x86_ops->has_wbinvd_exit())
2715 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2716 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2717 smp_call_function_single(vcpu->cpu,
2718 wbinvd_ipi, NULL, 1);
2719 }
2720
313a3dc7 2721 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2722
0dd6a6ed
ZA		 2723 /* Apply any externally detected TSC adjustments (due to suspend) */
2724 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2725 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2726 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2728 }
8f6055cb 2729
48434c20 2730 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2731 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2732 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2733 if (tsc_delta < 0)
2734 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2735 if (check_tsc_unstable()) {
07c1419a 2736 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2737 vcpu->arch.last_guest_tsc);
2738 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2739 vcpu->arch.tsc_catchup = 1;
c285545f 2740 }
d98d07ca
MT		 2741 /*
2742 * On a host with synchronized TSC, there is no need to update
2743 * kvmclock on vcpu->cpu migration
2744 */
2745 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2746 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2747 if (vcpu->cpu != cpu)
2748 kvm_migrate_timers(vcpu);
e48672fa 2749 vcpu->cpu = cpu;
6b7d7e76 2750 }
c9aaa895 2751
c9aaa895 2752 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2753}
2754
2755void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2756{
02daab21 2757 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2758 kvm_put_guest_fpu(vcpu);
4ea1636b 2759 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2760}
2761
313a3dc7
CO		 2762static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2763 struct kvm_lapic_state *s)
2764{
d62caabb
AS		 2765 if (vcpu->arch.apicv_active)
2766 kvm_x86_ops->sync_pir_to_irr(vcpu);
2767
ad312c7c 2768 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2769
2770 return 0;
2771}
2772
2773static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2774 struct kvm_lapic_state *s)
2775{
64eb0620 2776 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2777 update_cr8_intercept(vcpu);
313a3dc7
CO		 2778
2779 return 0;
2780}
2781
127a457a
MG		 2782static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2783{
2784 return (!lapic_in_kernel(vcpu) ||
2785 kvm_apic_accept_pic_intr(vcpu));
2786}
2787
782d422b
MG		 2788/*
2789 * if userspace requested an interrupt window, check that the
2790 * interrupt window is open.
2791 *
2792 * No need to exit to userspace if we already have an interrupt queued.
2793 */
2794static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2795{
2796 return kvm_arch_interrupt_allowed(vcpu) &&
2797 !kvm_cpu_has_interrupt(vcpu) &&
2798 !kvm_event_needs_reinjection(vcpu) &&
2799 kvm_cpu_accept_dm_intr(vcpu);
2800}
2801
f77bc6a4
ZX		 2802static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2803 struct kvm_interrupt *irq)
2804{
02cdb50f 2805 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2806 return -EINVAL;
1c1a9ce9
SR		 2807
2808 if (!irqchip_in_kernel(vcpu->kvm)) {
2809 kvm_queue_interrupt(vcpu, irq->irq, false);
2810 kvm_make_request(KVM_REQ_EVENT, vcpu);
2811 return 0;
2812 }
2813
2814 /*
2815 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2816 * fail for in-kernel 8259.
2817 */
2818 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2819 return -ENXIO;
f77bc6a4 2820
1c1a9ce9
SR		 2821 if (vcpu->arch.pending_external_vector != -1)
2822 return -EEXIST;
f77bc6a4 2823
1c1a9ce9 2824 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2825 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2826 return 0;
2827}
2828
c4abb7c9
JK		 2829static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2830{
c4abb7c9 2831 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2832
2833 return 0;
2834}
2835
f077825a
PB		 2836static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2837{
64d60670
PB		 2838 kvm_make_request(KVM_REQ_SMI, vcpu);
2839
f077825a
PB		 2840 return 0;
2841}
2842
b209749f
AK		 2843static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2844 struct kvm_tpr_access_ctl *tac)
2845{
2846 if (tac->flags)
2847 return -EINVAL;
2848 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2849 return 0;
2850}
2851
890ca9ae
HY		 2852static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2853 u64 mcg_cap)
2854{
2855 int r;
2856 unsigned bank_num = mcg_cap & 0xff, bank;
2857
2858 r = -EINVAL;
a9e38c3e 2859 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2860 goto out;
2861 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2862 goto out;
2863 r = 0;
2864 vcpu->arch.mcg_cap = mcg_cap;
2865 /* Init IA32_MCG_CTL to all 1s */
2866 if (mcg_cap & MCG_CTL_P)
2867 vcpu->arch.mcg_ctl = ~(u64)0;
2868 /* Init IA32_MCi_CTL to all 1s */
2869 for (bank = 0; bank < bank_num; bank++)
2870 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2871out:
2872 return r;
2873}
2874
2875static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2876 struct kvm_x86_mce *mce)
2877{
2878 u64 mcg_cap = vcpu->arch.mcg_cap;
2879 unsigned bank_num = mcg_cap & 0xff;
2880 u64 *banks = vcpu->arch.mce_banks;
2881
2882 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2883 return -EINVAL;
2884 /*
2885 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2886 * reporting is disabled
2887 */
2888 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2889 vcpu->arch.mcg_ctl != ~(u64)0)
2890 return 0;
2891 banks += 4 * mce->bank;
2892 /*
2893 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2894 * reporting is disabled for the bank
2895 */
2896 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2897 return 0;
2898 if (mce->status & MCI_STATUS_UC) {
2899 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2900 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2901 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2902 return 0;
2903 }
2904 if (banks[1] & MCI_STATUS_VAL)
2905 mce->status |= MCI_STATUS_OVER;
2906 banks[2] = mce->addr;
2907 banks[3] = mce->misc;
2908 vcpu->arch.mcg_status = mce->mcg_status;
2909 banks[1] = mce->status;
2910 kvm_queue_exception(vcpu, MC_VECTOR);
2911 } else if (!(banks[1] & MCI_STATUS_VAL)
2912 || !(banks[1] & MCI_STATUS_UC)) {
2913 if (banks[1] & MCI_STATUS_VAL)
2914 mce->status |= MCI_STATUS_OVER;
2915 banks[2] = mce->addr;
2916 banks[3] = mce->misc;
2917 banks[1] = mce->status;
2918 } else
2919 banks[1] |= MCI_STATUS_OVER;
2920 return 0;
2921}
2922
3cfc3092
JK		 2923static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2924 struct kvm_vcpu_events *events)
2925{
7460fb4a 2926 process_nmi(vcpu);
03b82a30
JK		 2927 events->exception.injected =
2928 vcpu->arch.exception.pending &&
2929 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2930 events->exception.nr = vcpu->arch.exception.nr;
2931 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2932 events->exception.pad = 0;
3cfc3092
JK		 2933 events->exception.error_code = vcpu->arch.exception.error_code;
2934
03b82a30
JK		 2935 events->interrupt.injected =
2936 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2937 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2938 events->interrupt.soft = 0;
37ccdcbe 2939 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2940
2941 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2942 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2943 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2944 events->nmi.pad = 0;
3cfc3092 2945
66450a21 2946 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2947
f077825a
PB		 2948 events->smi.smm = is_smm(vcpu);
2949 events->smi.pending = vcpu->arch.smi_pending;
2950 events->smi.smm_inside_nmi =
2951 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2952 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2953
dab4b911 2954 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2955 | KVM_VCPUEVENT_VALID_SHADOW
2956 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2957 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2958}
2959
2960static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2961 struct kvm_vcpu_events *events)
2962{
dab4b911 2963 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2964 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2965 | KVM_VCPUEVENT_VALID_SHADOW
2966 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2967 return -EINVAL;
2968
7460fb4a 2969 process_nmi(vcpu);
3cfc3092
JK		 2970 vcpu->arch.exception.pending = events->exception.injected;
2971 vcpu->arch.exception.nr = events->exception.nr;
2972 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2973 vcpu->arch.exception.error_code = events->exception.error_code;
2974
2975 vcpu->arch.interrupt.pending = events->interrupt.injected;
2976 vcpu->arch.interrupt.nr = events->interrupt.nr;
2977 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2978 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2979 kvm_x86_ops->set_interrupt_shadow(vcpu,
2980 events->interrupt.shadow);
3cfc3092
JK		 2981
2982 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2983 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2984 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2985 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2986
66450a21 2987 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2988 lapic_in_kernel(vcpu))
66450a21 2989 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2990
f077825a
PB		 2991 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2992 if (events->smi.smm)
2993 vcpu->arch.hflags |= HF_SMM_MASK;
2994 else
2995 vcpu->arch.hflags &= ~HF_SMM_MASK;
2996 vcpu->arch.smi_pending = events->smi.pending;
2997 if (events->smi.smm_inside_nmi)
2998 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2999 else
3000 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3001 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3002 if (events->smi.latched_init)
3003 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3004 else
3005 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3006 }
3007 }
3008
3842d135
AK		 3009 kvm_make_request(KVM_REQ_EVENT, vcpu);
3010
3cfc3092
JK		 3011 return 0;
3012}
3013
a1efbe77
JK		 3014static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3015 struct kvm_debugregs *dbgregs)
3016{
73aaf249
JK		 3017 unsigned long val;
3018
a1efbe77 3019 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3020 kvm_get_dr(vcpu, 6, &val);
73aaf249 3021 dbgregs->dr6 = val;
a1efbe77
JK		 3022 dbgregs->dr7 = vcpu->arch.dr7;
3023 dbgregs->flags = 0;
97e69aa6 3024 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3025}
3026
3027static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3028 struct kvm_debugregs *dbgregs)
3029{
3030 if (dbgregs->flags)
3031 return -EINVAL;
3032
a1efbe77 3033 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3034 kvm_update_dr0123(vcpu);
a1efbe77 3035 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3036 kvm_update_dr6(vcpu);
a1efbe77 3037 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3038 kvm_update_dr7(vcpu);
a1efbe77 3039
a1efbe77
JK		 3040 return 0;
3041}
3042
df1daba7
PB		 3043#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3044
3045static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3046{
c47ada30 3047 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3048 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3049 u64 valid;
3050
3051 /*
3052 * Copy legacy XSAVE area, to avoid complications with CPUID
3053 * leaves 0 and 1 in the loop below.
3054 */
3055 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3056
3057 /* Set XSTATE_BV */
3058 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3059
3060 /*
3061 * Copy each region from the possibly compacted offset to the
3062 * non-compacted offset.
3063 */
d91cab78 3064 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3065 while (valid) {
3066 u64 feature = valid & -valid;
3067 int index = fls64(feature) - 1;
3068 void *src = get_xsave_addr(xsave, feature);
3069
3070 if (src) {
3071 u32 size, offset, ecx, edx;
3072 cpuid_count(XSTATE_CPUID, index,
3073 &size, &offset, &ecx, &edx);
3074 memcpy(dest + offset, src, size);
3075 }
3076
3077 valid -= feature;
3078 }
3079}
3080
3081static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3082{
c47ada30 3083 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3084 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3085 u64 valid;
3086
3087 /*
3088 * Copy legacy XSAVE area, to avoid complications with CPUID
3089 * leaves 0 and 1 in the loop below.
3090 */
3091 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3092
3093 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3094 xsave->header.xfeatures = xstate_bv;
df1daba7 3095 if (cpu_has_xsaves)
3a54450b 3096 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3097
3098 /*
3099 * Copy each region from the non-compacted offset to the
3100 * possibly compacted offset.
3101 */
d91cab78 3102 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3103 while (valid) {
3104 u64 feature = valid & -valid;
3105 int index = fls64(feature) - 1;
3106 void *dest = get_xsave_addr(xsave, feature);
3107
3108 if (dest) {
3109 u32 size, offset, ecx, edx;
3110 cpuid_count(XSTATE_CPUID, index,
3111 &size, &offset, &ecx, &edx);
3112 memcpy(dest, src + offset, size);
ee4100da 3113 }
df1daba7
PB		 3114
3115 valid -= feature;
3116 }
3117}
3118
2d5b5a66
SY		 3119static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3120 struct kvm_xsave *guest_xsave)
3121{
4344ee98 3122 if (cpu_has_xsave) {
df1daba7
PB		 3123 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3124 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3125 } else {
2d5b5a66 3126 memcpy(guest_xsave->region,
7366ed77 3127 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3128 sizeof(struct fxregs_state));
2d5b5a66 3129 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3130 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3131 }
3132}
3133
3134static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3135 struct kvm_xsave *guest_xsave)
3136{
3137 u64 xstate_bv =
3138 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3139
d7876f1b
PB		 3140 if (cpu_has_xsave) {
3141 /*
3142 * Here we allow setting states that are not present in
3143 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3144 * with old userspace.
3145 */
4ff41732 3146 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3147 return -EINVAL;
df1daba7 3148 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3149 } else {
d91cab78 3150 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3151 return -EINVAL;
7366ed77 3152 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3153 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3154 }
3155 return 0;
3156}
3157
3158static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3159 struct kvm_xcrs *guest_xcrs)
3160{
3161 if (!cpu_has_xsave) {
3162 guest_xcrs->nr_xcrs = 0;
3163 return;
3164 }
3165
3166 guest_xcrs->nr_xcrs = 1;
3167 guest_xcrs->flags = 0;
3168 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3169 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3170}
3171
3172static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3173 struct kvm_xcrs *guest_xcrs)
3174{
3175 int i, r = 0;
3176
3177 if (!cpu_has_xsave)
3178 return -EINVAL;
3179
3180 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3181 return -EINVAL;
3182
3183 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3184 /* Only support XCR0 currently */
c67a04cb 3185 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3186 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3187 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3188 break;
3189 }
3190 if (r)
3191 r = -EINVAL;
3192 return r;
3193}
3194
1c0b28c2
EM		 3195/*
3196 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3197 * stopped by the hypervisor. This function will be called from the host only.
3198 * EINVAL is returned when the host attempts to set the flag for a guest that
3199 * does not support pv clocks.
3200 */
3201static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3202{
0b79459b 3203 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3204 return -EINVAL;
51d59c6b 3205 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3206 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3207 return 0;
3208}
3209
5c919412
AS		 3210static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3211 struct kvm_enable_cap *cap)
3212{
3213 if (cap->flags)
3214 return -EINVAL;
3215
3216 switch (cap->cap) {
3217 case KVM_CAP_HYPERV_SYNIC:
3218 return kvm_hv_activate_synic(vcpu);
3219 default:
3220 return -EINVAL;
3221 }
3222}
3223
313a3dc7
CO		 3224long kvm_arch_vcpu_ioctl(struct file *filp,
3225 unsigned int ioctl, unsigned long arg)
3226{
3227 struct kvm_vcpu *vcpu = filp->private_data;
3228 void __user *argp = (void __user *)arg;
3229 int r;
d1ac91d8
AK		 3230 union {
3231 struct kvm_lapic_state *lapic;
3232 struct kvm_xsave *xsave;
3233 struct kvm_xcrs *xcrs;
3234 void *buffer;
3235 } u;
3236
3237 u.buffer = NULL;
313a3dc7
CO		 3238 switch (ioctl) {
3239 case KVM_GET_LAPIC: {
2204ae3c 3240 r = -EINVAL;
bce87cce 3241 if (!lapic_in_kernel(vcpu))
2204ae3c 3242 goto out;
d1ac91d8 3243 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3244
b772ff36 3245 r = -ENOMEM;
d1ac91d8 3246 if (!u.lapic)
b772ff36 3247 goto out;
d1ac91d8 3248 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3249 if (r)
3250 goto out;
3251 r = -EFAULT;
d1ac91d8 3252 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3253 goto out;
3254 r = 0;
3255 break;
3256 }
3257 case KVM_SET_LAPIC: {
2204ae3c 3258 r = -EINVAL;
bce87cce 3259 if (!lapic_in_kernel(vcpu))
2204ae3c 3260 goto out;
ff5c2c03 3261 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3262 if (IS_ERR(u.lapic))
3263 return PTR_ERR(u.lapic);
ff5c2c03 3264
d1ac91d8 3265 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3266 break;
3267 }
f77bc6a4
ZX		 3268 case KVM_INTERRUPT: {
3269 struct kvm_interrupt irq;
3270
3271 r = -EFAULT;
3272 if (copy_from_user(&irq, argp, sizeof irq))
3273 goto out;
3274 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3275 break;
3276 }
c4abb7c9
JK		 3277 case KVM_NMI: {
3278 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3279 break;
3280 }
f077825a
PB		 3281 case KVM_SMI: {
3282 r = kvm_vcpu_ioctl_smi(vcpu);
3283 break;
3284 }
313a3dc7
CO		 3285 case KVM_SET_CPUID: {
3286 struct kvm_cpuid __user *cpuid_arg = argp;
3287 struct kvm_cpuid cpuid;
3288
3289 r = -EFAULT;
3290 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3291 goto out;
3292 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3293 break;
3294 }
07716717
DK		 3295 case KVM_SET_CPUID2: {
3296 struct kvm_cpuid2 __user *cpuid_arg = argp;
3297 struct kvm_cpuid2 cpuid;
3298
3299 r = -EFAULT;
3300 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3301 goto out;
3302 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3303 cpuid_arg->entries);
07716717
DK		 3304 break;
3305 }
3306 case KVM_GET_CPUID2: {
3307 struct kvm_cpuid2 __user *cpuid_arg = argp;
3308 struct kvm_cpuid2 cpuid;
3309
3310 r = -EFAULT;
3311 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3312 goto out;
3313 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3314 cpuid_arg->entries);
07716717
DK		 3315 if (r)
3316 goto out;
3317 r = -EFAULT;
3318 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3319 goto out;
3320 r = 0;
3321 break;
3322 }
313a3dc7 3323 case KVM_GET_MSRS:
609e36d3 3324 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3325 break;
3326 case KVM_SET_MSRS:
3327 r = msr_io(vcpu, argp, do_set_msr, 0);
3328 break;
b209749f
AK		 3329 case KVM_TPR_ACCESS_REPORTING: {
3330 struct kvm_tpr_access_ctl tac;
3331
3332 r = -EFAULT;
3333 if (copy_from_user(&tac, argp, sizeof tac))
3334 goto out;
3335 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3336 if (r)
3337 goto out;
3338 r = -EFAULT;
3339 if (copy_to_user(argp, &tac, sizeof tac))
3340 goto out;
3341 r = 0;
3342 break;
3343 };
b93463aa
AK		 3344 case KVM_SET_VAPIC_ADDR: {
3345 struct kvm_vapic_addr va;
3346
3347 r = -EINVAL;
35754c98 3348 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3349 goto out;
3350 r = -EFAULT;
3351 if (copy_from_user(&va, argp, sizeof va))
3352 goto out;
fda4e2e8 3353 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3354 break;
3355 }
890ca9ae
HY		 3356 case KVM_X86_SETUP_MCE: {
3357 u64 mcg_cap;
3358
3359 r = -EFAULT;
3360 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3361 goto out;
3362 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3363 break;
3364 }
3365 case KVM_X86_SET_MCE: {
3366 struct kvm_x86_mce mce;
3367
3368 r = -EFAULT;
3369 if (copy_from_user(&mce, argp, sizeof mce))
3370 goto out;
3371 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3372 break;
3373 }
3cfc3092
JK		 3374 case KVM_GET_VCPU_EVENTS: {
3375 struct kvm_vcpu_events events;
3376
3377 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3378
3379 r = -EFAULT;
3380 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3381 break;
3382 r = 0;
3383 break;
3384 }
3385 case KVM_SET_VCPU_EVENTS: {
3386 struct kvm_vcpu_events events;
3387
3388 r = -EFAULT;
3389 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3390 break;
3391
3392 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3393 break;
3394 }
a1efbe77
JK		 3395 case KVM_GET_DEBUGREGS: {
3396 struct kvm_debugregs dbgregs;
3397
3398 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3399
3400 r = -EFAULT;
3401 if (copy_to_user(argp, &dbgregs,
3402 sizeof(struct kvm_debugregs)))
3403 break;
3404 r = 0;
3405 break;
3406 }
3407 case KVM_SET_DEBUGREGS: {
3408 struct kvm_debugregs dbgregs;
3409
3410 r = -EFAULT;
3411 if (copy_from_user(&dbgregs, argp,
3412 sizeof(struct kvm_debugregs)))
3413 break;
3414
3415 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3416 break;
3417 }
2d5b5a66 3418 case KVM_GET_XSAVE: {
d1ac91d8 3419 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3420 r = -ENOMEM;
d1ac91d8 3421 if (!u.xsave)
2d5b5a66
SY		 3422 break;
3423
d1ac91d8 3424 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3425
3426 r = -EFAULT;
d1ac91d8 3427 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3428 break;
3429 r = 0;
3430 break;
3431 }
3432 case KVM_SET_XSAVE: {
ff5c2c03 3433 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3434 if (IS_ERR(u.xsave))
3435 return PTR_ERR(u.xsave);
2d5b5a66 3436
d1ac91d8 3437 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3438 break;
3439 }
3440 case KVM_GET_XCRS: {
d1ac91d8 3441 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3442 r = -ENOMEM;
d1ac91d8 3443 if (!u.xcrs)
2d5b5a66
SY		 3444 break;
3445
d1ac91d8 3446 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3447
3448 r = -EFAULT;
d1ac91d8 3449 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3450 sizeof(struct kvm_xcrs)))
3451 break;
3452 r = 0;
3453 break;
3454 }
3455 case KVM_SET_XCRS: {
ff5c2c03 3456 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3457 if (IS_ERR(u.xcrs))
3458 return PTR_ERR(u.xcrs);
2d5b5a66 3459
d1ac91d8 3460 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3461 break;
3462 }
92a1f12d
JR		 3463 case KVM_SET_TSC_KHZ: {
3464 u32 user_tsc_khz;
3465
3466 r = -EINVAL;
92a1f12d
JR		 3467 user_tsc_khz = (u32)arg;
3468
3469 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3470 goto out;
3471
cc578287
ZA		 3472 if (user_tsc_khz == 0)
3473 user_tsc_khz = tsc_khz;
3474
381d585c
HZ		 3475 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3476 r = 0;
92a1f12d 3477
92a1f12d
JR		 3478 goto out;
3479 }
3480 case KVM_GET_TSC_KHZ: {
cc578287 3481 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3482 goto out;
3483 }
1c0b28c2
EM		 3484 case KVM_KVMCLOCK_CTRL: {
3485 r = kvm_set_guest_paused(vcpu);
3486 goto out;
3487 }
5c919412
AS		 3488 case KVM_ENABLE_CAP: {
3489 struct kvm_enable_cap cap;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&cap, argp, sizeof(cap)))
3493 goto out;
3494 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3495 break;
3496 }
313a3dc7
CO		 3497 default:
3498 r = -EINVAL;
3499 }
3500out:
d1ac91d8 3501 kfree(u.buffer);
313a3dc7
CO		 3502 return r;
3503}
3504
5b1c1493
CO		 3505int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3506{
3507 return VM_FAULT_SIGBUS;
3508}
3509
1fe779f8
CO		 3510static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3511{
3512 int ret;
3513
3514 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3515 return -EINVAL;
1fe779f8
CO		 3516 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3517 return ret;
3518}
3519
b927a3ce
SY		 3520static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3521 u64 ident_addr)
3522{
3523 kvm->arch.ept_identity_map_addr = ident_addr;
3524 return 0;
3525}
3526
1fe779f8
CO		 3527static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3528 u32 kvm_nr_mmu_pages)
3529{
3530 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3531 return -EINVAL;
3532
79fac95e 3533 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3534
3535 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3536 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3537
79fac95e 3538 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3539 return 0;
3540}
3541
3542static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3543{
39de71ec 3544 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3545}
3546
1fe779f8
CO		 3547static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3548{
3549 int r;
3550
3551 r = 0;
3552 switch (chip->chip_id) {
3553 case KVM_IRQCHIP_PIC_MASTER:
3554 memcpy(&chip->chip.pic,
3555 &pic_irqchip(kvm)->pics[0],
3556 sizeof(struct kvm_pic_state));
3557 break;
3558 case KVM_IRQCHIP_PIC_SLAVE:
3559 memcpy(&chip->chip.pic,
3560 &pic_irqchip(kvm)->pics[1],
3561 sizeof(struct kvm_pic_state));
3562 break;
3563 case KVM_IRQCHIP_IOAPIC:
eba0226b 3564 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3565 break;
3566 default:
3567 r = -EINVAL;
3568 break;
3569 }
3570 return r;
3571}
3572
3573static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3574{
3575 int r;
3576
3577 r = 0;
3578 switch (chip->chip_id) {
3579 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3580 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3581 memcpy(&pic_irqchip(kvm)->pics[0],
3582 &chip->chip.pic,
3583 sizeof(struct kvm_pic_state));
f4f51050 3584 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3585 break;
3586 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3587 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3588 memcpy(&pic_irqchip(kvm)->pics[1],
3589 &chip->chip.pic,
3590 sizeof(struct kvm_pic_state));
f4f51050 3591 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3592 break;
3593 case KVM_IRQCHIP_IOAPIC:
eba0226b 3594 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3595 break;
3596 default:
3597 r = -EINVAL;
3598 break;
3599 }
3600 kvm_pic_update_irq(pic_irqchip(kvm));
3601 return r;
3602}
3603
e0f63cb9
SY		 3604static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3605{
34f3941c
RK		 3606 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3607
3608 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3609
3610 mutex_lock(&kps->lock);
3611 memcpy(ps, &kps->channels, sizeof(*ps));
3612 mutex_unlock(&kps->lock);
2da29bcc 3613 return 0;
e0f63cb9
SY		 3614}
3615
3616static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3617{
0185604c 3618 int i;
09edea72
RK		 3619 struct kvm_pit *pit = kvm->arch.vpit;
3620
3621 mutex_lock(&pit->pit_state.lock);
34f3941c 3622 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3623 for (i = 0; i < 3; i++)
09edea72
RK		 3624 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3625 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3626 return 0;
e9f42757
BK		 3627}
3628
3629static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3630{
e9f42757
BK		 3631 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3632 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3633 sizeof(ps->channels));
3634 ps->flags = kvm->arch.vpit->pit_state.flags;
3635 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3636 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3637 return 0;
e9f42757
BK		 3638}
3639
3640static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3641{
2da29bcc 3642 int start = 0;
0185604c 3643 int i;
e9f42757 3644 u32 prev_legacy, cur_legacy;
09edea72
RK		 3645 struct kvm_pit *pit = kvm->arch.vpit;
3646
3647 mutex_lock(&pit->pit_state.lock);
3648 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3649 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3650 if (!prev_legacy && cur_legacy)
3651 start = 1;
09edea72
RK		 3652 memcpy(&pit->pit_state.channels, &ps->channels,
3653 sizeof(pit->pit_state.channels));
3654 pit->pit_state.flags = ps->flags;
0185604c 3655 for (i = 0; i < 3; i++)
09edea72 3656 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3657 start && i == 0);
09edea72 3658 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3659 return 0;
e0f63cb9
SY		 3660}
3661
52d939a0
MT		 3662static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3663 struct kvm_reinject_control *control)
3664{
71474e2f
RK		 3665 struct kvm_pit *pit = kvm->arch.vpit;
3666
3667 if (!pit)
52d939a0 3668 return -ENXIO;
b39c90b6 3669
71474e2f
RK		 3670 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3671 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3672 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3673 */
3674 mutex_lock(&pit->pit_state.lock);
3675 kvm_pit_set_reinject(pit, control->pit_reinject);
3676 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3677
52d939a0
MT		 3678 return 0;
3679}
3680
95d4c16c 3681/**
60c34612
TY		 3682 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3683 * @kvm: kvm instance
3684 * @log: slot id and address to which we copy the log
95d4c16c 3685 *
e108ff2f
PB		 3686 * Steps 1-4 below provide general overview of dirty page logging. See
3687 * kvm_get_dirty_log_protect() function description for additional details.
3688 *
3689 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3690 * always flush the TLB (step 4) even if previous step failed and the dirty
3691 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3692 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3693 * writes will be marked dirty for next log read.
95d4c16c 3694 *
60c34612
TY		 3695 * 1. Take a snapshot of the bit and clear it if needed.
3696 * 2. Write protect the corresponding page.
e108ff2f
PB		 3697 * 3. Copy the snapshot to the userspace.
3698 * 4. Flush TLB's if needed.
5bb064dc 3699 */
60c34612 3700int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3701{
60c34612 3702 bool is_dirty = false;
e108ff2f 3703 int r;
5bb064dc 3704
79fac95e 3705 mutex_lock(&kvm->slots_lock);
5bb064dc 3706
88178fd4
KH		 3707 /*
3708 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3709 */
3710 if (kvm_x86_ops->flush_log_dirty)
3711 kvm_x86_ops->flush_log_dirty(kvm);
3712
e108ff2f 3713 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3714
3715 /*
3716 * All the TLBs can be flushed out of mmu lock, see the comments in
3717 * kvm_mmu_slot_remove_write_access().
3718 */
e108ff2f 3719 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3720 if (is_dirty)
3721 kvm_flush_remote_tlbs(kvm);
3722
79fac95e 3723 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3724 return r;
3725}
3726
aa2fbe6d
YZ		 3727int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3728 bool line_status)
23d43cf9
CD		 3729{
3730 if (!irqchip_in_kernel(kvm))
3731 return -ENXIO;
3732
3733 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3734 irq_event->irq, irq_event->level,
3735 line_status);
23d43cf9
CD		 3736 return 0;
3737}
3738
90de4a18
NA		 3739static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3740 struct kvm_enable_cap *cap)
3741{
3742 int r;
3743
3744 if (cap->flags)
3745 return -EINVAL;
3746
3747 switch (cap->cap) {
3748 case KVM_CAP_DISABLE_QUIRKS:
3749 kvm->arch.disabled_quirks = cap->args[0];
3750 r = 0;
3751 break;
49df6397
SR		 3752 case KVM_CAP_SPLIT_IRQCHIP: {
3753 mutex_lock(&kvm->lock);
b053b2ae
SR		 3754 r = -EINVAL;
3755 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3756 goto split_irqchip_unlock;
49df6397
SR		 3757 r = -EEXIST;
3758 if (irqchip_in_kernel(kvm))
3759 goto split_irqchip_unlock;
3760 if (atomic_read(&kvm->online_vcpus))
3761 goto split_irqchip_unlock;
3762 r = kvm_setup_empty_irq_routing(kvm);
3763 if (r)
3764 goto split_irqchip_unlock;
3765 /* Pairs with irqchip_in_kernel. */
3766 smp_wmb();
3767 kvm->arch.irqchip_split = true;
b053b2ae 3768 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3769 r = 0;
3770split_irqchip_unlock:
3771 mutex_unlock(&kvm->lock);
3772 break;
3773 }
90de4a18
NA		 3774 default:
3775 r = -EINVAL;
3776 break;
3777 }
3778 return r;
3779}
3780
1fe779f8
CO		 3781long kvm_arch_vm_ioctl(struct file *filp,
3782 unsigned int ioctl, unsigned long arg)
3783{
3784 struct kvm *kvm = filp->private_data;
3785 void __user *argp = (void __user *)arg;
367e1319 3786 int r = -ENOTTY;
f0d66275
DH		 3787 /*
3788 * This union makes it completely explicit to gcc-3.x
3789 * that these two variables' stack usage should be
3790 * combined, not added together.
3791 */
3792 union {
3793 struct kvm_pit_state ps;
e9f42757 3794 struct kvm_pit_state2 ps2;
c5ff41ce 3795 struct kvm_pit_config pit_config;
f0d66275 3796 } u;
1fe779f8
CO		 3797
3798 switch (ioctl) {
3799 case KVM_SET_TSS_ADDR:
3800 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3801 break;
b927a3ce
SY		 3802 case KVM_SET_IDENTITY_MAP_ADDR: {
3803 u64 ident_addr;
3804
3805 r = -EFAULT;
3806 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3807 goto out;
3808 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3809 break;
3810 }
1fe779f8
CO		 3811 case KVM_SET_NR_MMU_PAGES:
3812 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3813 break;
3814 case KVM_GET_NR_MMU_PAGES:
3815 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3816 break;
3ddea128
MT		 3817 case KVM_CREATE_IRQCHIP: {
3818 struct kvm_pic *vpic;
3819
3820 mutex_lock(&kvm->lock);
3821 r = -EEXIST;
3822 if (kvm->arch.vpic)
3823 goto create_irqchip_unlock;
3e515705
AK		 3824 r = -EINVAL;
3825 if (atomic_read(&kvm->online_vcpus))
3826 goto create_irqchip_unlock;
1fe779f8 3827 r = -ENOMEM;
3ddea128
MT		 3828 vpic = kvm_create_pic(kvm);
3829 if (vpic) {
1fe779f8
CO		 3830 r = kvm_ioapic_init(kvm);
3831 if (r) {
175504cd 3832 mutex_lock(&kvm->slots_lock);
71ba994c 3833 kvm_destroy_pic(vpic);
175504cd 3834 mutex_unlock(&kvm->slots_lock);
3ddea128 3835 goto create_irqchip_unlock;
1fe779f8
CO		 3836 }
3837 } else
3ddea128 3838 goto create_irqchip_unlock;
399ec807
AK		 3839 r = kvm_setup_default_irq_routing(kvm);
3840 if (r) {
175504cd 3841 mutex_lock(&kvm->slots_lock);
3ddea128 3842 mutex_lock(&kvm->irq_lock);
72bb2fcd 3843 kvm_ioapic_destroy(kvm);
71ba994c 3844 kvm_destroy_pic(vpic);
3ddea128 3845 mutex_unlock(&kvm->irq_lock);
175504cd 3846 mutex_unlock(&kvm->slots_lock);
71ba994c 3847 goto create_irqchip_unlock;
399ec807 3848 }
71ba994c
PB		 3849 /* Write kvm->irq_routing before kvm->arch.vpic. */
3850 smp_wmb();
3851 kvm->arch.vpic = vpic;
3ddea128
MT		 3852 create_irqchip_unlock:
3853 mutex_unlock(&kvm->lock);
1fe779f8 3854 break;
3ddea128 3855 }
7837699f 3856 case KVM_CREATE_PIT:
c5ff41ce
JK		 3857 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3858 goto create_pit;
3859 case KVM_CREATE_PIT2:
3860 r = -EFAULT;
3861 if (copy_from_user(&u.pit_config, argp,
3862 sizeof(struct kvm_pit_config)))
3863 goto out;
3864 create_pit:
79fac95e 3865 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3866 r = -EEXIST;
3867 if (kvm->arch.vpit)
3868 goto create_pit_unlock;
7837699f 3869 r = -ENOMEM;
c5ff41ce 3870 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3871 if (kvm->arch.vpit)
3872 r = 0;
269e05e4 3873 create_pit_unlock:
79fac95e 3874 mutex_unlock(&kvm->slots_lock);
7837699f 3875 break;
1fe779f8
CO		 3876 case KVM_GET_IRQCHIP: {
3877 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3878 struct kvm_irqchip *chip;
1fe779f8 3879
ff5c2c03
SL		 3880 chip = memdup_user(argp, sizeof(*chip));
3881 if (IS_ERR(chip)) {
3882 r = PTR_ERR(chip);
1fe779f8 3883 goto out;
ff5c2c03
SL		 3884 }
3885
1fe779f8 3886 r = -ENXIO;
49df6397 3887 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3888 goto get_irqchip_out;
3889 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3890 if (r)
f0d66275 3891 goto get_irqchip_out;
1fe779f8 3892 r = -EFAULT;
f0d66275
DH		 3893 if (copy_to_user(argp, chip, sizeof *chip))
3894 goto get_irqchip_out;
1fe779f8 3895 r = 0;
f0d66275
DH		 3896 get_irqchip_out:
3897 kfree(chip);
1fe779f8
CO		 3898 break;
3899 }
3900 case KVM_SET_IRQCHIP: {
3901 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3902 struct kvm_irqchip *chip;
1fe779f8 3903
ff5c2c03
SL		 3904 chip = memdup_user(argp, sizeof(*chip));
3905 if (IS_ERR(chip)) {
3906 r = PTR_ERR(chip);
1fe779f8 3907 goto out;
ff5c2c03
SL		 3908 }
3909
1fe779f8 3910 r = -ENXIO;
49df6397 3911 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3912 goto set_irqchip_out;
3913 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3914 if (r)
f0d66275 3915 goto set_irqchip_out;
1fe779f8 3916 r = 0;
f0d66275
DH		 3917 set_irqchip_out:
3918 kfree(chip);
1fe779f8
CO		 3919 break;
3920 }
e0f63cb9 3921 case KVM_GET_PIT: {
e0f63cb9 3922 r = -EFAULT;
f0d66275 3923 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3924 goto out;
3925 r = -ENXIO;
3926 if (!kvm->arch.vpit)
3927 goto out;
f0d66275 3928 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3929 if (r)
3930 goto out;
3931 r = -EFAULT;
f0d66275 3932 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3933 goto out;
3934 r = 0;
3935 break;
3936 }
3937 case KVM_SET_PIT: {
e0f63cb9 3938 r = -EFAULT;
f0d66275 3939 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3940 goto out;
3941 r = -ENXIO;
3942 if (!kvm->arch.vpit)
3943 goto out;
f0d66275 3944 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3945 break;
3946 }
e9f42757
BK		 3947 case KVM_GET_PIT2: {
3948 r = -ENXIO;
3949 if (!kvm->arch.vpit)
3950 goto out;
3951 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3952 if (r)
3953 goto out;
3954 r = -EFAULT;
3955 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3956 goto out;
3957 r = 0;
3958 break;
3959 }
3960 case KVM_SET_PIT2: {
3961 r = -EFAULT;
3962 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3963 goto out;
3964 r = -ENXIO;
3965 if (!kvm->arch.vpit)
3966 goto out;
3967 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3968 break;
3969 }
52d939a0
MT		 3970 case KVM_REINJECT_CONTROL: {
3971 struct kvm_reinject_control control;
3972 r = -EFAULT;
3973 if (copy_from_user(&control, argp, sizeof(control)))
3974 goto out;
3975 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3976 break;
3977 }
d71ba788
PB		 3978 case KVM_SET_BOOT_CPU_ID:
3979 r = 0;
3980 mutex_lock(&kvm->lock);
3981 if (atomic_read(&kvm->online_vcpus) != 0)
3982 r = -EBUSY;
3983 else
3984 kvm->arch.bsp_vcpu_id = arg;
3985 mutex_unlock(&kvm->lock);
3986 break;
ffde22ac
ES		 3987 case KVM_XEN_HVM_CONFIG: {
3988 r = -EFAULT;
3989 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3990 sizeof(struct kvm_xen_hvm_config)))
3991 goto out;
3992 r = -EINVAL;
3993 if (kvm->arch.xen_hvm_config.flags)
3994 goto out;
3995 r = 0;
3996 break;
3997 }
afbcf7ab 3998 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3999 struct kvm_clock_data user_ns;
4000 u64 now_ns;
4001 s64 delta;
4002
4003 r = -EFAULT;
4004 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4005 goto out;
4006
4007 r = -EINVAL;
4008 if (user_ns.flags)
4009 goto out;
4010
4011 r = 0;
395c6b0a 4012 local_irq_disable();
759379dd 4013 now_ns = get_kernel_ns();
afbcf7ab 4014 delta = user_ns.clock - now_ns;
395c6b0a 4015 local_irq_enable();
afbcf7ab 4016 kvm->arch.kvmclock_offset = delta;
2e762ff7 4017 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4018 break;
4019 }
4020 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4021 struct kvm_clock_data user_ns;
4022 u64 now_ns;
4023
395c6b0a 4024 local_irq_disable();
759379dd 4025 now_ns = get_kernel_ns();
afbcf7ab 4026 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4027 local_irq_enable();
afbcf7ab 4028 user_ns.flags = 0;
97e69aa6 4029 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4030
4031 r = -EFAULT;
4032 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4033 goto out;
4034 r = 0;
4035 break;
4036 }
90de4a18
NA		 4037 case KVM_ENABLE_CAP: {
4038 struct kvm_enable_cap cap;
afbcf7ab 4039
90de4a18
NA		 4040 r = -EFAULT;
4041 if (copy_from_user(&cap, argp, sizeof(cap)))
4042 goto out;
4043 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4044 break;
4045 }
1fe779f8 4046 default:
c274e03a 4047 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4048 }
4049out:
4050 return r;
4051}
4052
a16b043c 4053static void kvm_init_msr_list(void)
043405e1
CO		 4054{
4055 u32 dummy[2];
4056 unsigned i, j;
4057
62ef68bb 4058 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4059 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4060 continue;
93c4adc7
PB		 4061
4062 /*
4063 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4064 * to the guests in some cases.
93c4adc7
PB		 4065 */
4066 switch (msrs_to_save[i]) {
4067 case MSR_IA32_BNDCFGS:
4068 if (!kvm_x86_ops->mpx_supported())
4069 continue;
4070 break;
9dbe6cf9
PB		 4071 case MSR_TSC_AUX:
4072 if (!kvm_x86_ops->rdtscp_supported())
4073 continue;
4074 break;
93c4adc7
PB		 4075 default:
4076 break;
4077 }
4078
043405e1
CO		 4079 if (j < i)
4080 msrs_to_save[j] = msrs_to_save[i];
4081 j++;
4082 }
4083 num_msrs_to_save = j;
62ef68bb
PB		 4084
4085 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4086 switch (emulated_msrs[i]) {
6d396b55
PB		 4087 case MSR_IA32_SMBASE:
4088 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4089 continue;
4090 break;
62ef68bb
PB		 4091 default:
4092 break;
4093 }
4094
4095 if (j < i)
4096 emulated_msrs[j] = emulated_msrs[i];
4097 j++;
4098 }
4099 num_emulated_msrs = j;
043405e1
CO		 4100}
4101
bda9020e
MT		 4102static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4103 const void *v)
bbd9b64e 4104{
70252a10
AK		 4105 int handled = 0;
4106 int n;
4107
4108 do {
4109 n = min(len, 8);
bce87cce 4110 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4111 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4112 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4113 break;
4114 handled += n;
4115 addr += n;
4116 len -= n;
4117 v += n;
4118 } while (len);
bbd9b64e 4119
70252a10 4120 return handled;
bbd9b64e
CO		 4121}
4122
bda9020e 4123static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4124{
70252a10
AK		 4125 int handled = 0;
4126 int n;
4127
4128 do {
4129 n = min(len, 8);
bce87cce 4130 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4131 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4132 addr, n, v))
4133 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4134 break;
4135 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4136 handled += n;
4137 addr += n;
4138 len -= n;
4139 v += n;
4140 } while (len);
bbd9b64e 4141
70252a10 4142 return handled;
bbd9b64e
CO		 4143}
4144
2dafc6c2
GN		 4145static void kvm_set_segment(struct kvm_vcpu *vcpu,
4146 struct kvm_segment *var, int seg)
4147{
4148 kvm_x86_ops->set_segment(vcpu, var, seg);
4149}
4150
4151void kvm_get_segment(struct kvm_vcpu *vcpu,
4152 struct kvm_segment *var, int seg)
4153{
4154 kvm_x86_ops->get_segment(vcpu, var, seg);
4155}
4156
54987b7a
PB		 4157gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4158 struct x86_exception *exception)
02f59dc9
JR		 4159{
4160 gpa_t t_gpa;
02f59dc9
JR		 4161
4162 BUG_ON(!mmu_is_nested(vcpu));
4163
4164 /* NPT walks are always user-walks */
4165 access |= PFERR_USER_MASK;
54987b7a 4166 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4167
4168 return t_gpa;
4169}
4170
ab9ae313
AK		 4171gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4172 struct x86_exception *exception)
1871c602
GN		 4173{
4174 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4175 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4176}
4177
ab9ae313
AK		 4178 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4179 struct x86_exception *exception)
1871c602
GN		 4180{
4181 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4182 access |= PFERR_FETCH_MASK;
ab9ae313 4183 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4184}
4185
ab9ae313
AK		 4186gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4187 struct x86_exception *exception)
1871c602
GN		 4188{
4189 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4190 access |= PFERR_WRITE_MASK;
ab9ae313 4191 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4192}
4193
4194/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4195gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4196 struct x86_exception *exception)
1871c602 4197{
ab9ae313 4198 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4199}
4200
4201static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4202 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4203 struct x86_exception *exception)
bbd9b64e
CO		 4204{
4205 void *data = val;
10589a46 4206 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4207
4208 while (bytes) {
14dfe855 4209 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4210 exception);
bbd9b64e 4211 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4212 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4213 int ret;
4214
bcc55cba 4215 if (gpa == UNMAPPED_GVA)
ab9ae313 4216 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4217 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4218 offset, toread);
10589a46 4219 if (ret < 0) {
c3cd7ffa 4220 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4221 goto out;
4222 }
bbd9b64e 4223
77c2002e
IE		 4224 bytes -= toread;
4225 data += toread;
4226 addr += toread;
bbd9b64e 4227 }
10589a46 4228out:
10589a46 4229 return r;
bbd9b64e 4230}
77c2002e 4231
1871c602 4232/* used for instruction fetching */
0f65dd70
AK		 4233static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4234 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4235 struct x86_exception *exception)
1871c602 4236{
0f65dd70 4237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4238 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4239 unsigned offset;
4240 int ret;
0f65dd70 4241
44583cba
PB		 4242 /* Inline kvm_read_guest_virt_helper for speed. */
4243 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4244 exception);
4245 if (unlikely(gpa == UNMAPPED_GVA))
4246 return X86EMUL_PROPAGATE_FAULT;
4247
4248 offset = addr & (PAGE_SIZE-1);
4249 if (WARN_ON(offset + bytes > PAGE_SIZE))
4250 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4251 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4252 offset, bytes);
44583cba
PB		 4253 if (unlikely(ret < 0))
4254 return X86EMUL_IO_NEEDED;
4255
4256 return X86EMUL_CONTINUE;
1871c602
GN		 4257}
4258
064aea77 4259int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4260 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4261 struct x86_exception *exception)
1871c602 4262{
0f65dd70 4263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4264 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4265
1871c602 4266 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4267 exception);
1871c602 4268}
064aea77 4269EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4270
0f65dd70
AK		 4271static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4272 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4273 struct x86_exception *exception)
1871c602 4274{
0f65dd70 4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4276 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4277}
4278
7a036a6f
RK		 4279static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4280 unsigned long addr, void *val, unsigned int bytes)
4281{
4282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4283 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4284
4285 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4286}
4287
6a4d7550 4288int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4289 gva_t addr, void *val,
2dafc6c2 4290 unsigned int bytes,
bcc55cba 4291 struct x86_exception *exception)
77c2002e 4292{
0f65dd70 4293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4294 void *data = val;
4295 int r = X86EMUL_CONTINUE;
4296
4297 while (bytes) {
14dfe855
JR		 4298 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4299 PFERR_WRITE_MASK,
ab9ae313 4300 exception);
77c2002e
IE		 4301 unsigned offset = addr & (PAGE_SIZE-1);
4302 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4303 int ret;
4304
bcc55cba 4305 if (gpa == UNMAPPED_GVA)
ab9ae313 4306 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4307 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4308 if (ret < 0) {
c3cd7ffa 4309 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4310 goto out;
4311 }
4312
4313 bytes -= towrite;
4314 data += towrite;
4315 addr += towrite;
4316 }
4317out:
4318 return r;
4319}
6a4d7550 4320EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4321
af7cc7d1
XG		 4322static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4323 gpa_t *gpa, struct x86_exception *exception,
4324 bool write)
4325{
97d64b78
AK		 4326 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4327 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4328
97d64b78 4329 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4330 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4331 vcpu->arch.access, access)) {
bebb106a
XG		 4332 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4333 (gva & (PAGE_SIZE - 1));
4f022648 4334 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4335 return 1;
4336 }
4337
af7cc7d1
XG		 4338 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4339
4340 if (*gpa == UNMAPPED_GVA)
4341 return -1;
4342
4343 /* For APIC access vmexit */
4344 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4345 return 1;
4346
4f022648
XG		 4347 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4348 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4349 return 1;
4f022648 4350 }
bebb106a 4351
af7cc7d1
XG		 4352 return 0;
4353}
4354
3200f405 4355int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4356 const void *val, int bytes)
bbd9b64e
CO		 4357{
4358 int ret;
4359
54bf36aa 4360 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4361 if (ret < 0)
bbd9b64e 4362 return 0;
0eb05bf2 4363 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4364 return 1;
4365}
4366
77d197b2
XG		 4367struct read_write_emulator_ops {
4368 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4369 int bytes);
4370 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4371 void *val, int bytes);
4372 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4373 int bytes, void *val);
4374 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4375 void *val, int bytes);
4376 bool write;
4377};
4378
4379static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4380{
4381 if (vcpu->mmio_read_completed) {
77d197b2 4382 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4383 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4384 vcpu->mmio_read_completed = 0;
4385 return 1;
4386 }
4387
4388 return 0;
4389}
4390
4391static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4392 void *val, int bytes)
4393{
54bf36aa 4394 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4395}
4396
4397static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4398 void *val, int bytes)
4399{
4400 return emulator_write_phys(vcpu, gpa, val, bytes);
4401}
4402
4403static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4404{
4405 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4406 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4407}
4408
4409static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4410 void *val, int bytes)
4411{
4412 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4413 return X86EMUL_IO_NEEDED;
4414}
4415
4416static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4417 void *val, int bytes)
4418{
f78146b0
AK		 4419 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4420
87da7e66 4421 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4422 return X86EMUL_CONTINUE;
4423}
4424
0fbe9b0b 4425static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4426 .read_write_prepare = read_prepare,
4427 .read_write_emulate = read_emulate,
4428 .read_write_mmio = vcpu_mmio_read,
4429 .read_write_exit_mmio = read_exit_mmio,
4430};
4431
0fbe9b0b 4432static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4433 .read_write_emulate = write_emulate,
4434 .read_write_mmio = write_mmio,
4435 .read_write_exit_mmio = write_exit_mmio,
4436 .write = true,
4437};
4438
22388a3c
XG		 4439static int emulator_read_write_onepage(unsigned long addr, void *val,
4440 unsigned int bytes,
4441 struct x86_exception *exception,
4442 struct kvm_vcpu *vcpu,
0fbe9b0b 4443 const struct read_write_emulator_ops *ops)
bbd9b64e 4444{
af7cc7d1
XG		 4445 gpa_t gpa;
4446 int handled, ret;
22388a3c 4447 bool write = ops->write;
f78146b0 4448 struct kvm_mmio_fragment *frag;
10589a46 4449
22388a3c 4450 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4451
af7cc7d1 4452 if (ret < 0)
bbd9b64e 4453 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4454
4455 /* For APIC access vmexit */
af7cc7d1 4456 if (ret)
bbd9b64e
CO		 4457 goto mmio;
4458
22388a3c 4459 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4460 return X86EMUL_CONTINUE;
4461
4462mmio:
4463 /*
4464 * Is this MMIO handled locally?
4465 */
22388a3c 4466 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4467 if (handled == bytes)
bbd9b64e 4468 return X86EMUL_CONTINUE;
bbd9b64e 4469
70252a10
AK		 4470 gpa += handled;
4471 bytes -= handled;
4472 val += handled;
4473
87da7e66
XG		 4474 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4475 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4476 frag->gpa = gpa;
4477 frag->data = val;
4478 frag->len = bytes;
f78146b0 4479 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4480}
4481
52eb5a6d
XL		 4482static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4483 unsigned long addr,
22388a3c
XG		 4484 void *val, unsigned int bytes,
4485 struct x86_exception *exception,
0fbe9b0b 4486 const struct read_write_emulator_ops *ops)
bbd9b64e 4487{
0f65dd70 4488 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4489 gpa_t gpa;
4490 int rc;
4491
4492 if (ops->read_write_prepare &&
4493 ops->read_write_prepare(vcpu, val, bytes))
4494 return X86EMUL_CONTINUE;
4495
4496 vcpu->mmio_nr_fragments = 0;
0f65dd70 4497
bbd9b64e
CO		 4498 /* Crossing a page boundary? */
4499 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4500 int now;
bbd9b64e
CO		 4501
4502 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4503 rc = emulator_read_write_onepage(addr, val, now, exception,
4504 vcpu, ops);
4505
bbd9b64e
CO		 4506 if (rc != X86EMUL_CONTINUE)
4507 return rc;
4508 addr += now;
bac15531
NA		 4509 if (ctxt->mode != X86EMUL_MODE_PROT64)
4510 addr = (u32)addr;
bbd9b64e
CO		 4511 val += now;
4512 bytes -= now;
4513 }
22388a3c 4514
f78146b0
AK		 4515 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4516 vcpu, ops);
4517 if (rc != X86EMUL_CONTINUE)
4518 return rc;
4519
4520 if (!vcpu->mmio_nr_fragments)
4521 return rc;
4522
4523 gpa = vcpu->mmio_fragments[0].gpa;
4524
4525 vcpu->mmio_needed = 1;
4526 vcpu->mmio_cur_fragment = 0;
4527
87da7e66 4528 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4529 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4530 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4531 vcpu->run->mmio.phys_addr = gpa;
4532
4533 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4534}
4535
4536static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4537 unsigned long addr,
4538 void *val,
4539 unsigned int bytes,
4540 struct x86_exception *exception)
4541{
4542 return emulator_read_write(ctxt, addr, val, bytes,
4543 exception, &read_emultor);
4544}
4545
52eb5a6d 4546static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4547 unsigned long addr,
4548 const void *val,
4549 unsigned int bytes,
4550 struct x86_exception *exception)
4551{
4552 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4553 exception, &write_emultor);
bbd9b64e 4554}
bbd9b64e 4555
daea3e73
AK		 4556#define CMPXCHG_TYPE(t, ptr, old, new) \
4557 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4558
4559#ifdef CONFIG_X86_64
4560# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4561#else
4562# define CMPXCHG64(ptr, old, new) \
9749a6c0 4563 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4564#endif
4565
0f65dd70
AK		 4566static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4567 unsigned long addr,
bbd9b64e
CO		 4568 const void *old,
4569 const void *new,
4570 unsigned int bytes,
0f65dd70 4571 struct x86_exception *exception)
bbd9b64e 4572{
0f65dd70 4573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4574 gpa_t gpa;
4575 struct page *page;
4576 char *kaddr;
4577 bool exchanged;
2bacc55c 4578
daea3e73
AK		 4579 /* guests cmpxchg8b have to be emulated atomically */
4580 if (bytes > 8 || (bytes & (bytes - 1)))
4581 goto emul_write;
10589a46 4582
daea3e73 4583 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4584
daea3e73
AK		 4585 if (gpa == UNMAPPED_GVA ||
4586 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4587 goto emul_write;
2bacc55c 4588
daea3e73
AK		 4589 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4590 goto emul_write;
72dc67a6 4591
54bf36aa 4592 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4593 if (is_error_page(page))
c19b8bd6 4594 goto emul_write;
72dc67a6 4595
8fd75e12 4596 kaddr = kmap_atomic(page);
daea3e73
AK		 4597 kaddr += offset_in_page(gpa);
4598 switch (bytes) {
4599 case 1:
4600 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4601 break;
4602 case 2:
4603 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4604 break;
4605 case 4:
4606 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4607 break;
4608 case 8:
4609 exchanged = CMPXCHG64(kaddr, old, new);
4610 break;
4611 default:
4612 BUG();
2bacc55c 4613 }
8fd75e12 4614 kunmap_atomic(kaddr);
daea3e73
AK		 4615 kvm_release_page_dirty(page);
4616
4617 if (!exchanged)
4618 return X86EMUL_CMPXCHG_FAILED;
4619
54bf36aa 4620 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4621 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4622
4623 return X86EMUL_CONTINUE;
4a5f48f6 4624
3200f405 4625emul_write:
daea3e73 4626 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4627
0f65dd70 4628 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4629}
4630
cf8f70bf
GN		 4631static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4632{
4633 /* TODO: String I/O for in kernel device */
4634 int r;
4635
4636 if (vcpu->arch.pio.in)
e32edf4f 4637 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4638 vcpu->arch.pio.size, pd);
4639 else
e32edf4f 4640 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4641 vcpu->arch.pio.port, vcpu->arch.pio.size,
4642 pd);
4643 return r;
4644}
4645
6f6fbe98
XG		 4646static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4647 unsigned short port, void *val,
4648 unsigned int count, bool in)
cf8f70bf 4649{
cf8f70bf 4650 vcpu->arch.pio.port = port;
6f6fbe98 4651 vcpu->arch.pio.in = in;
7972995b 4652 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4653 vcpu->arch.pio.size = size;
4654
4655 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4656 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4657 return 1;
4658 }
4659
4660 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4661 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4662 vcpu->run->io.size = size;
4663 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4664 vcpu->run->io.count = count;
4665 vcpu->run->io.port = port;
4666
4667 return 0;
4668}
4669
6f6fbe98
XG		 4670static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4671 int size, unsigned short port, void *val,
4672 unsigned int count)
cf8f70bf 4673{
ca1d4a9e 4674 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4675 int ret;
ca1d4a9e 4676
6f6fbe98
XG		 4677 if (vcpu->arch.pio.count)
4678 goto data_avail;
cf8f70bf 4679
6f6fbe98
XG		 4680 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4681 if (ret) {
4682data_avail:
4683 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4684 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4685 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4686 return 1;
4687 }
4688
cf8f70bf
GN		 4689 return 0;
4690}
4691
6f6fbe98
XG		 4692static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4693 int size, unsigned short port,
4694 const void *val, unsigned int count)
4695{
4696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4697
4698 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4699 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4700 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4701}
4702
bbd9b64e
CO		 4703static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4704{
4705 return kvm_x86_ops->get_segment_base(vcpu, seg);
4706}
4707
3cb16fe7 4708static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4709{
3cb16fe7 4710 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4711}
4712
5cb56059 4713int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4714{
4715 if (!need_emulate_wbinvd(vcpu))
4716 return X86EMUL_CONTINUE;
4717
4718 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4719 int cpu = get_cpu();
4720
4721 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4722 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4723 wbinvd_ipi, NULL, 1);
2eec7343 4724 put_cpu();
f5f48ee1 4725 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4726 } else
4727 wbinvd();
f5f48ee1
SY		 4728 return X86EMUL_CONTINUE;
4729}
5cb56059
JS		 4730
4731int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4732{
4733 kvm_x86_ops->skip_emulated_instruction(vcpu);
4734 return kvm_emulate_wbinvd_noskip(vcpu);
4735}
f5f48ee1
SY		 4736EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4737
5cb56059
JS		 4738
4739
bcaf5cc5
AK		 4740static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4741{
5cb56059 4742 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4743}
4744
52eb5a6d
XL		 4745static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4746 unsigned long *dest)
bbd9b64e 4747{
16f8a6f9 4748 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4749}
4750
52eb5a6d
XL		 4751static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4752 unsigned long value)
bbd9b64e 4753{
338dbc97 4754
717746e3 4755 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4756}
4757
52a46617 4758static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4759{
52a46617 4760 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4761}
4762
717746e3 4763static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4764{
717746e3 4765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4766 unsigned long value;
4767
4768 switch (cr) {
4769 case 0:
4770 value = kvm_read_cr0(vcpu);
4771 break;
4772 case 2:
4773 value = vcpu->arch.cr2;
4774 break;
4775 case 3:
9f8fe504 4776 value = kvm_read_cr3(vcpu);
52a46617
GN		 4777 break;
4778 case 4:
4779 value = kvm_read_cr4(vcpu);
4780 break;
4781 case 8:
4782 value = kvm_get_cr8(vcpu);
4783 break;
4784 default:
a737f256 4785 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4786 return 0;
4787 }
4788
4789 return value;
4790}
4791
717746e3 4792static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4793{
717746e3 4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4795 int res = 0;
4796
52a46617
GN		 4797 switch (cr) {
4798 case 0:
49a9b07e 4799 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4800 break;
4801 case 2:
4802 vcpu->arch.cr2 = val;
4803 break;
4804 case 3:
2390218b 4805 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4806 break;
4807 case 4:
a83b29c6 4808 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4809 break;
4810 case 8:
eea1cff9 4811 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4812 break;
4813 default:
a737f256 4814 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4815 res = -1;
52a46617 4816 }
0f12244f
GN		 4817
4818 return res;
52a46617
GN		 4819}
4820
717746e3 4821static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4822{
717746e3 4823 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4824}
4825
4bff1e86 4826static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4827{
4bff1e86 4828 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4829}
4830
4bff1e86 4831static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4832{
4bff1e86 4833 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4834}
4835
1ac9d0cf
AK		 4836static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4837{
4838 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4839}
4840
4841static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4842{
4843 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4844}
4845
4bff1e86
AK		 4846static unsigned long emulator_get_cached_segment_base(
4847 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4848{
4bff1e86 4849 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4850}
4851
1aa36616
AK		 4852static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4853 struct desc_struct *desc, u32 *base3,
4854 int seg)
2dafc6c2
GN		 4855{
4856 struct kvm_segment var;
4857
4bff1e86 4858 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4859 *selector = var.selector;
2dafc6c2 4860
378a8b09
GN		 4861 if (var.unusable) {
4862 memset(desc, 0, sizeof(*desc));
2dafc6c2 4863 return false;
378a8b09 4864 }
2dafc6c2
GN		 4865
4866 if (var.g)
4867 var.limit >>= 12;
4868 set_desc_limit(desc, var.limit);
4869 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4870#ifdef CONFIG_X86_64
4871 if (base3)
4872 *base3 = var.base >> 32;
4873#endif
2dafc6c2
GN		 4874 desc->type = var.type;
4875 desc->s = var.s;
4876 desc->dpl = var.dpl;
4877 desc->p = var.present;
4878 desc->avl = var.avl;
4879 desc->l = var.l;
4880 desc->d = var.db;
4881 desc->g = var.g;
4882
4883 return true;
4884}
4885
1aa36616
AK		 4886static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4887 struct desc_struct *desc, u32 base3,
4888 int seg)
2dafc6c2 4889{
4bff1e86 4890 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4891 struct kvm_segment var;
4892
1aa36616 4893 var.selector = selector;
2dafc6c2 4894 var.base = get_desc_base(desc);
5601d05b
GN		 4895#ifdef CONFIG_X86_64
4896 var.base |= ((u64)base3) << 32;
4897#endif
2dafc6c2
GN		 4898 var.limit = get_desc_limit(desc);
4899 if (desc->g)
4900 var.limit = (var.limit << 12) | 0xfff;
4901 var.type = desc->type;
2dafc6c2
GN		 4902 var.dpl = desc->dpl;
4903 var.db = desc->d;
4904 var.s = desc->s;
4905 var.l = desc->l;
4906 var.g = desc->g;
4907 var.avl = desc->avl;
4908 var.present = desc->p;
4909 var.unusable = !var.present;
4910 var.padding = 0;
4911
4912 kvm_set_segment(vcpu, &var, seg);
4913 return;
4914}
4915
717746e3
AK		 4916static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4917 u32 msr_index, u64 *pdata)
4918{
609e36d3
PB		 4919 struct msr_data msr;
4920 int r;
4921
4922 msr.index = msr_index;
4923 msr.host_initiated = false;
4924 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4925 if (r)
4926 return r;
4927
4928 *pdata = msr.data;
4929 return 0;
717746e3
AK		 4930}
4931
4932static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4933 u32 msr_index, u64 data)
4934{
8fe8ab46
WA		 4935 struct msr_data msr;
4936
4937 msr.data = data;
4938 msr.index = msr_index;
4939 msr.host_initiated = false;
4940 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4941}
4942
64d60670
PB		 4943static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4944{
4945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4946
4947 return vcpu->arch.smbase;
4948}
4949
4950static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4951{
4952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4953
4954 vcpu->arch.smbase = smbase;
4955}
4956
67f4d428
NA		 4957static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4958 u32 pmc)
4959{
c6702c9d 4960 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4961}
4962
222d21aa
AK		 4963static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4964 u32 pmc, u64 *pdata)
4965{
c6702c9d 4966 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4967}
4968
6c3287f7
AK		 4969static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4970{
4971 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4972}
4973
5037f6f3
AK		 4974static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4975{
4976 preempt_disable();
5197b808 4977 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4978 /*
4979 * CR0.TS may reference the host fpu state, not the guest fpu state,
4980 * so it may be clear at this point.
4981 */
4982 clts();
4983}
4984
4985static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4986{
4987 preempt_enable();
4988}
4989
2953538e 4990static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4991 struct x86_instruction_info *info,
c4f035c6
AK		 4992 enum x86_intercept_stage stage)
4993{
2953538e 4994 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4995}
4996
0017f93a 4997static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4998 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4999{
0017f93a 5000 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5001}
5002
dd856efa
AK		 5003static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5004{
5005 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5006}
5007
5008static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5009{
5010 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5011}
5012
801806d9
NA		 5013static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5014{
5015 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5016}
5017
0225fb50 5018static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5019 .read_gpr = emulator_read_gpr,
5020 .write_gpr = emulator_write_gpr,
1871c602 5021 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5022 .write_std = kvm_write_guest_virt_system,
7a036a6f 5023 .read_phys = kvm_read_guest_phys_system,
1871c602 5024 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5025 .read_emulated = emulator_read_emulated,
5026 .write_emulated = emulator_write_emulated,
5027 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5028 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5029 .pio_in_emulated = emulator_pio_in_emulated,
5030 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5031 .get_segment = emulator_get_segment,
5032 .set_segment = emulator_set_segment,
5951c442 5033 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5034 .get_gdt = emulator_get_gdt,
160ce1f1 5035 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5036 .set_gdt = emulator_set_gdt,
5037 .set_idt = emulator_set_idt,
52a46617
GN		 5038 .get_cr = emulator_get_cr,
5039 .set_cr = emulator_set_cr,
9c537244 5040 .cpl = emulator_get_cpl,
35aa5375
GN		 5041 .get_dr = emulator_get_dr,
5042 .set_dr = emulator_set_dr,
64d60670
PB		 5043 .get_smbase = emulator_get_smbase,
5044 .set_smbase = emulator_set_smbase,
717746e3
AK		 5045 .set_msr = emulator_set_msr,
5046 .get_msr = emulator_get_msr,
67f4d428 5047 .check_pmc = emulator_check_pmc,
222d21aa 5048 .read_pmc = emulator_read_pmc,
6c3287f7 5049 .halt = emulator_halt,
bcaf5cc5 5050 .wbinvd = emulator_wbinvd,
d6aa1000 5051 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5052 .get_fpu = emulator_get_fpu,
5053 .put_fpu = emulator_put_fpu,
c4f035c6 5054 .intercept = emulator_intercept,
bdb42f5a 5055 .get_cpuid = emulator_get_cpuid,
801806d9 5056 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5057};
5058
95cb2295
GN		 5059static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5060{
37ccdcbe 5061 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5062 /*
5063 * an sti; sti; sequence only disable interrupts for the first
5064 * instruction. So, if the last instruction, be it emulated or
5065 * not, left the system with the INT_STI flag enabled, it
5066 * means that the last instruction is an sti. We should not
5067 * leave the flag on in this case. The same goes for mov ss
5068 */
37ccdcbe
PB		 5069 if (int_shadow & mask)
5070 mask = 0;
6addfc42 5071 if (unlikely(int_shadow || mask)) {
95cb2295 5072 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5073 if (!mask)
5074 kvm_make_request(KVM_REQ_EVENT, vcpu);
5075 }
95cb2295
GN		 5076}
5077
ef54bcfe 5078static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5079{
5080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5081 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5082 return kvm_propagate_fault(vcpu, &ctxt->exception);
5083
5084 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5085 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5086 ctxt->exception.error_code);
54b8486f 5087 else
da9cb575 5088 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5089 return false;
54b8486f
GN		 5090}
5091
8ec4722d
MG		 5092static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5093{
adf52235 5094 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5095 int cs_db, cs_l;
5096
8ec4722d
MG		 5097 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5098
adf52235
TY		 5099 ctxt->eflags = kvm_get_rflags(vcpu);
5100 ctxt->eip = kvm_rip_read(vcpu);
5101 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5102 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5103 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5104 cs_db ? X86EMUL_MODE_PROT32 :
5105 X86EMUL_MODE_PROT16;
a584539b 5106 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5107 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5108 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5109 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5110
dd856efa 5111 init_decode_cache(ctxt);
7ae441ea 5112 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5113}
5114
71f9833b 5115int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5116{
9d74191a 5117 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5118 int ret;
5119
5120 init_emulate_ctxt(vcpu);
5121
9dac77fa
AK		 5122 ctxt->op_bytes = 2;
5123 ctxt->ad_bytes = 2;
5124 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5125 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5126
5127 if (ret != X86EMUL_CONTINUE)
5128 return EMULATE_FAIL;
5129
9dac77fa 5130 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5131 kvm_rip_write(vcpu, ctxt->eip);
5132 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5133
5134 if (irq == NMI_VECTOR)
7460fb4a 5135 vcpu->arch.nmi_pending = 0;
63995653
MG		 5136 else
5137 vcpu->arch.interrupt.pending = false;
5138
5139 return EMULATE_DONE;
5140}
5141EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5142
6d77dbfc
GN		 5143static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5144{
fc3a9157
JR		 5145 int r = EMULATE_DONE;
5146
6d77dbfc
GN		 5147 ++vcpu->stat.insn_emulation_fail;
5148 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5149 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5150 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5151 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5152 vcpu->run->internal.ndata = 0;
5153 r = EMULATE_FAIL;
5154 }
6d77dbfc 5155 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5156
5157 return r;
6d77dbfc
GN		 5158}
5159
93c05d3e 5160static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5161 bool write_fault_to_shadow_pgtable,
5162 int emulation_type)
a6f177ef 5163{
95b3cf69 5164 gpa_t gpa = cr2;
ba049e93 5165 kvm_pfn_t pfn;
a6f177ef 5166
991eebf9
GN		 5167 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5168 return false;
5169
95b3cf69
XG		 5170 if (!vcpu->arch.mmu.direct_map) {
5171 /*
5172 * Write permission should be allowed since only
5173 * write access need to be emulated.
5174 */
5175 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5176
95b3cf69
XG		 5177 /*
5178 * If the mapping is invalid in guest, let cpu retry
5179 * it to generate fault.
5180 */
5181 if (gpa == UNMAPPED_GVA)
5182 return true;
5183 }
a6f177ef 5184
8e3d9d06
XG		 5185 /*
5186 * Do not retry the unhandleable instruction if it faults on the
5187 * readonly host memory, otherwise it will goto a infinite loop:
5188 * retry instruction -> write #PF -> emulation fail -> retry
5189 * instruction -> ...
5190 */
5191 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5192
5193 /*
5194 * If the instruction failed on the error pfn, it can not be fixed,
5195 * report the error to userspace.
5196 */
5197 if (is_error_noslot_pfn(pfn))
5198 return false;
5199
5200 kvm_release_pfn_clean(pfn);
5201
5202 /* The instructions are well-emulated on direct mmu. */
5203 if (vcpu->arch.mmu.direct_map) {
5204 unsigned int indirect_shadow_pages;
5205
5206 spin_lock(&vcpu->kvm->mmu_lock);
5207 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5208 spin_unlock(&vcpu->kvm->mmu_lock);
5209
5210 if (indirect_shadow_pages)
5211 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5212
a6f177ef 5213 return true;
8e3d9d06 5214 }
a6f177ef 5215
95b3cf69
XG		 5216 /*
5217 * if emulation was due to access to shadowed page table
5218 * and it failed try to unshadow page and re-enter the
5219 * guest to let CPU execute the instruction.
5220 */
5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5222
5223 /*
5224 * If the access faults on its page table, it can not
5225 * be fixed by unprotecting shadow page and it should
5226 * be reported to userspace.
5227 */
5228 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5229}
5230
1cb3f3ae
XG		 5231static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5232 unsigned long cr2, int emulation_type)
5233{
5234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5235 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5236
5237 last_retry_eip = vcpu->arch.last_retry_eip;
5238 last_retry_addr = vcpu->arch.last_retry_addr;
5239
5240 /*
5241 * If the emulation is caused by #PF and it is non-page_table
5242 * writing instruction, it means the VM-EXIT is caused by shadow
5243 * page protected, we can zap the shadow page and retry this
5244 * instruction directly.
5245 *
5246 * Note: if the guest uses a non-page-table modifying instruction
5247 * on the PDE that points to the instruction, then we will unmap
5248 * the instruction and go to an infinite loop. So, we cache the
5249 * last retried eip and the last fault address, if we meet the eip
5250 * and the address again, we can break out of the potential infinite
5251 * loop.
5252 */
5253 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5254
5255 if (!(emulation_type & EMULTYPE_RETRY))
5256 return false;
5257
5258 if (x86_page_table_writing_insn(ctxt))
5259 return false;
5260
5261 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5262 return false;
5263
5264 vcpu->arch.last_retry_eip = ctxt->eip;
5265 vcpu->arch.last_retry_addr = cr2;
5266
5267 if (!vcpu->arch.mmu.direct_map)
5268 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5269
22368028 5270 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5271
5272 return true;
5273}
5274
716d51ab
GN		 5275static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5276static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5277
64d60670 5278static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5279{
64d60670 5280 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5281 /* This is a good place to trace that we are exiting SMM. */
5282 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5283
64d60670
PB		 5284 if (unlikely(vcpu->arch.smi_pending)) {
5285 kvm_make_request(KVM_REQ_SMI, vcpu);
5286 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5287 } else {
5288 /* Process a latched INIT, if any. */
5289 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5290 }
5291 }
699023e2
PB		 5292
5293 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5294}
5295
5296static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5297{
5298 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5299
a584539b 5300 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5301
5302 if (changed & HF_SMM_MASK)
5303 kvm_smm_changed(vcpu);
a584539b
PB		 5304}
5305
4a1e10d5
PB		 5306static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5307 unsigned long *db)
5308{
5309 u32 dr6 = 0;
5310 int i;
5311 u32 enable, rwlen;
5312
5313 enable = dr7;
5314 rwlen = dr7 >> 16;
5315 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5316 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5317 dr6 |= (1 << i);
5318 return dr6;
5319}
5320
6addfc42 5321static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5322{
5323 struct kvm_run *kvm_run = vcpu->run;
5324
5325 /*
6addfc42
PB		 5326 * rflags is the old, "raw" value of the flags. The new value has
5327 * not been saved yet.
663f4c61
PB		 5328 *
5329 * This is correct even for TF set by the guest, because "the
5330 * processor will not generate this exception after the instruction
5331 * that sets the TF flag".
5332 */
663f4c61
PB		 5333 if (unlikely(rflags & X86_EFLAGS_TF)) {
5334 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5335 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5336 DR6_RTM;
663f4c61
PB		 5337 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5338 kvm_run->debug.arch.exception = DB_VECTOR;
5339 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5340 *r = EMULATE_USER_EXIT;
5341 } else {
5342 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5343 /*
5344 * "Certain debug exceptions may clear bit 0-3. The
5345 * remaining contents of the DR6 register are never
5346 * cleared by the processor".
5347 */
5348 vcpu->arch.dr6 &= ~15;
6f43ed01 5349 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5350 kvm_queue_exception(vcpu, DB_VECTOR);
5351 }
5352 }
5353}
5354
4a1e10d5
PB		 5355static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5356{
4a1e10d5
PB		 5357 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5358 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5359 struct kvm_run *kvm_run = vcpu->run;
5360 unsigned long eip = kvm_get_linear_rip(vcpu);
5361 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5362 vcpu->arch.guest_debug_dr7,
5363 vcpu->arch.eff_db);
5364
5365 if (dr6 != 0) {
6f43ed01 5366 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5367 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5368 kvm_run->debug.arch.exception = DB_VECTOR;
5369 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5370 *r = EMULATE_USER_EXIT;
5371 return true;
5372 }
5373 }
5374
4161a569
NA		 5375 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5376 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5377 unsigned long eip = kvm_get_linear_rip(vcpu);
5378 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5379 vcpu->arch.dr7,
5380 vcpu->arch.db);
5381
5382 if (dr6 != 0) {
5383 vcpu->arch.dr6 &= ~15;
6f43ed01 5384 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5385 kvm_queue_exception(vcpu, DB_VECTOR);
5386 *r = EMULATE_DONE;
5387 return true;
5388 }
5389 }
5390
5391 return false;
5392}
5393
51d8b661
AP		 5394int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5395 unsigned long cr2,
dc25e89e
AP		 5396 int emulation_type,
5397 void *insn,
5398 int insn_len)
bbd9b64e 5399{
95cb2295 5400 int r;
9d74191a 5401 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5402 bool writeback = true;
93c05d3e 5403 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5404
93c05d3e
XG		 5405 /*
5406 * Clear write_fault_to_shadow_pgtable here to ensure it is
5407 * never reused.
5408 */
5409 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5410 kvm_clear_exception_queue(vcpu);
8d7d8102 5411
571008da 5412 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5413 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5414
5415 /*
5416 * We will reenter on the same instruction since
5417 * we do not set complete_userspace_io. This does not
5418 * handle watchpoints yet, those would be handled in
5419 * the emulate_ops.
5420 */
5421 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5422 return r;
5423
9d74191a
TY		 5424 ctxt->interruptibility = 0;
5425 ctxt->have_exception = false;
e0ad0b47 5426 ctxt->exception.vector = -1;
9d74191a 5427 ctxt->perm_ok = false;
bbd9b64e 5428
b51e974f 5429 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5430
9d74191a 5431 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5432
e46479f8 5433 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5434 ++vcpu->stat.insn_emulation;
1d2887e2 5435 if (r != EMULATION_OK) {
4005996e
AK		 5436 if (emulation_type & EMULTYPE_TRAP_UD)
5437 return EMULATE_FAIL;
991eebf9
GN		 5438 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5439 emulation_type))
bbd9b64e 5440 return EMULATE_DONE;
6d77dbfc
GN		 5441 if (emulation_type & EMULTYPE_SKIP)
5442 return EMULATE_FAIL;
5443 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5444 }
5445 }
5446
ba8afb6b 5447 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5448 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5449 if (ctxt->eflags & X86_EFLAGS_RF)
5450 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5451 return EMULATE_DONE;
5452 }
5453
1cb3f3ae
XG		 5454 if (retry_instruction(ctxt, cr2, emulation_type))
5455 return EMULATE_DONE;
5456
7ae441ea 5457 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5458 changes registers values during IO operation */
7ae441ea
GN		 5459 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5460 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5461 emulator_invalidate_register_cache(ctxt);
7ae441ea 5462 }
4d2179e1 5463
5cd21917 5464restart:
9d74191a 5465 r = x86_emulate_insn(ctxt);
bbd9b64e 5466
775fde86
JR		 5467 if (r == EMULATION_INTERCEPTED)
5468 return EMULATE_DONE;
5469
d2ddd1c4 5470 if (r == EMULATION_FAILED) {
991eebf9
GN		 5471 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5472 emulation_type))
c3cd7ffa
GN		 5473 return EMULATE_DONE;
5474
6d77dbfc 5475 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5476 }
5477
9d74191a 5478 if (ctxt->have_exception) {
d2ddd1c4 5479 r = EMULATE_DONE;
ef54bcfe
PB		 5480 if (inject_emulated_exception(vcpu))
5481 return r;
d2ddd1c4 5482 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5483 if (!vcpu->arch.pio.in) {
5484 /* FIXME: return into emulator if single-stepping. */
3457e419 5485 vcpu->arch.pio.count = 0;
0912c977 5486 } else {
7ae441ea 5487 writeback = false;
716d51ab
GN		 5488 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5489 }
ac0a48c3 5490 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5491 } else if (vcpu->mmio_needed) {
5492 if (!vcpu->mmio_is_write)
5493 writeback = false;
ac0a48c3 5494 r = EMULATE_USER_EXIT;
716d51ab 5495 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5496 } else if (r == EMULATION_RESTART)
5cd21917 5497 goto restart;
d2ddd1c4
GN		 5498 else
5499 r = EMULATE_DONE;
f850e2e6 5500
7ae441ea 5501 if (writeback) {
6addfc42 5502 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5503 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5504 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5505 if (vcpu->arch.hflags != ctxt->emul_flags)
5506 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5507 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5508 if (r == EMULATE_DONE)
6addfc42 5509 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5510 if (!ctxt->have_exception ||
5511 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5512 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5513
5514 /*
5515 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5516 * do nothing, and it will be requested again as soon as
5517 * the shadow expires. But we still need to check here,
5518 * because POPF has no interrupt shadow.
5519 */
5520 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5521 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5522 } else
5523 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5524
5525 return r;
de7d789a 5526}
51d8b661 5527EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5528
cf8f70bf 5529int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5530{
cf8f70bf 5531 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5532 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5533 size, port, &val, 1);
cf8f70bf 5534 /* do not return to emulator after return from userspace */
7972995b 5535 vcpu->arch.pio.count = 0;
de7d789a
CO		 5536 return ret;
5537}
cf8f70bf 5538EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5539
8cfdc000
ZA		 5540static void tsc_bad(void *info)
5541{
0a3aee0d 5542 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5543}
5544
5545static void tsc_khz_changed(void *data)
c8076604 5546{
8cfdc000
ZA		 5547 struct cpufreq_freqs *freq = data;
5548 unsigned long khz = 0;
5549
5550 if (data)
5551 khz = freq->new;
5552 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5553 khz = cpufreq_quick_get(raw_smp_processor_id());
5554 if (!khz)
5555 khz = tsc_khz;
0a3aee0d 5556 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5557}
5558
c8076604
GH		 5559static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5560 void *data)
5561{
5562 struct cpufreq_freqs *freq = data;
5563 struct kvm *kvm;
5564 struct kvm_vcpu *vcpu;
5565 int i, send_ipi = 0;
5566
8cfdc000
ZA		 5567 /*
5568 * We allow guests to temporarily run on slowing clocks,
5569 * provided we notify them after, or to run on accelerating
5570 * clocks, provided we notify them before. Thus time never
5571 * goes backwards.
5572 *
5573 * However, we have a problem. We can't atomically update
5574 * the frequency of a given CPU from this function; it is
5575 * merely a notifier, which can be called from any CPU.
5576 * Changing the TSC frequency at arbitrary points in time
5577 * requires a recomputation of local variables related to
5578 * the TSC for each VCPU. We must flag these local variables
5579 * to be updated and be sure the update takes place with the
5580 * new frequency before any guests proceed.
5581 *
5582 * Unfortunately, the combination of hotplug CPU and frequency
5583 * change creates an intractable locking scenario; the order
5584 * of when these callouts happen is undefined with respect to
5585 * CPU hotplug, and they can race with each other. As such,
5586 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5587 * undefined; you can actually have a CPU frequency change take
5588 * place in between the computation of X and the setting of the
5589 * variable. To protect against this problem, all updates of
5590 * the per_cpu tsc_khz variable are done in an interrupt
5591 * protected IPI, and all callers wishing to update the value
5592 * must wait for a synchronous IPI to complete (which is trivial
5593 * if the caller is on the CPU already). This establishes the
5594 * necessary total order on variable updates.
5595 *
5596 * Note that because a guest time update may take place
5597 * anytime after the setting of the VCPU's request bit, the
5598 * correct TSC value must be set before the request. However,
5599 * to ensure the update actually makes it to any guest which
5600 * starts running in hardware virtualization between the set
5601 * and the acquisition of the spinlock, we must also ping the
5602 * CPU after setting the request bit.
5603 *
5604 */
5605
c8076604
GH		 5606 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5607 return 0;
5608 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5609 return 0;
8cfdc000
ZA		 5610
5611 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5612
2f303b74 5613 spin_lock(&kvm_lock);
c8076604 5614 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5615 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5616 if (vcpu->cpu != freq->cpu)
5617 continue;
c285545f 5618 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5619 if (vcpu->cpu != smp_processor_id())
8cfdc000 5620 send_ipi = 1;
c8076604
GH		 5621 }
5622 }
2f303b74 5623 spin_unlock(&kvm_lock);
c8076604
GH		 5624
5625 if (freq->old < freq->new && send_ipi) {
5626 /*
5627 * We upscale the frequency. Must make the guest
5628 * doesn't see old kvmclock values while running with
5629 * the new frequency, otherwise we risk the guest sees
5630 * time go backwards.
5631 *
5632 * In case we update the frequency for another cpu
5633 * (which might be in guest context) send an interrupt
5634 * to kick the cpu out of guest context. Next time
5635 * guest context is entered kvmclock will be updated,
5636 * so the guest will not see stale values.
5637 */
8cfdc000 5638 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5639 }
5640 return 0;
5641}
5642
5643static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5644 .notifier_call = kvmclock_cpufreq_notifier
5645};
5646
5647static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5648 unsigned long action, void *hcpu)
5649{
5650 unsigned int cpu = (unsigned long)hcpu;
5651
5652 switch (action) {
5653 case CPU_ONLINE:
5654 case CPU_DOWN_FAILED:
5655 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5656 break;
5657 case CPU_DOWN_PREPARE:
5658 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5659 break;
5660 }
5661 return NOTIFY_OK;
5662}
5663
5664static struct notifier_block kvmclock_cpu_notifier_block = {
5665 .notifier_call = kvmclock_cpu_notifier,
5666 .priority = -INT_MAX
c8076604
GH		 5667};
5668
b820cc0c
ZA		 5669static void kvm_timer_init(void)
5670{
5671 int cpu;
5672
c285545f 5673 max_tsc_khz = tsc_khz;
460dd42e
SB		 5674
5675 cpu_notifier_register_begin();
b820cc0c 5676 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5677#ifdef CONFIG_CPU_FREQ
5678 struct cpufreq_policy policy;
5679 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5680 cpu = get_cpu();
5681 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5682 if (policy.cpuinfo.max_freq)
5683 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5684 put_cpu();
c285545f 5685#endif
b820cc0c
ZA		 5686 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5687 CPUFREQ_TRANSITION_NOTIFIER);
5688 }
c285545f 5689 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5690 for_each_online_cpu(cpu)
5691 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5692
5693 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5694 cpu_notifier_register_done();
5695
b820cc0c
ZA		 5696}
5697
ff9d07a0
ZY		 5698static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5699
f5132b01 5700int kvm_is_in_guest(void)
ff9d07a0 5701{
086c9855 5702 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5703}
5704
5705static int kvm_is_user_mode(void)
5706{
5707 int user_mode = 3;
dcf46b94 5708
086c9855
AS		 5709 if (__this_cpu_read(current_vcpu))
5710 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5711
ff9d07a0
ZY		 5712 return user_mode != 0;
5713}
5714
5715static unsigned long kvm_get_guest_ip(void)
5716{
5717 unsigned long ip = 0;
dcf46b94 5718
086c9855
AS		 5719 if (__this_cpu_read(current_vcpu))
5720 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5721
ff9d07a0
ZY		 5722 return ip;
5723}
5724
5725static struct perf_guest_info_callbacks kvm_guest_cbs = {
5726 .is_in_guest = kvm_is_in_guest,
5727 .is_user_mode = kvm_is_user_mode,
5728 .get_guest_ip = kvm_get_guest_ip,
5729};
5730
5731void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5732{
086c9855 5733 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5734}
5735EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5736
5737void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5738{
086c9855 5739 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5740}
5741EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5742
ce88decf
XG		 5743static void kvm_set_mmio_spte_mask(void)
5744{
5745 u64 mask;
5746 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5747
5748 /*
5749 * Set the reserved bits and the present bit of an paging-structure
5750 * entry to generate page fault with PFER.RSV = 1.
5751 */
885032b9 5752 /* Mask the reserved physical address bits. */
d1431483 5753 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5754
5755 /* Bit 62 is always reserved for 32bit host. */
5756 mask |= 0x3ull << 62;
5757
5758 /* Set the present bit. */
ce88decf
XG		 5759 mask |= 1ull;
5760
5761#ifdef CONFIG_X86_64
5762 /*
5763 * If reserved bit is not supported, clear the present bit to disable
5764 * mmio page fault.
5765 */
5766 if (maxphyaddr == 52)
5767 mask &= ~1ull;
5768#endif
5769
5770 kvm_mmu_set_mmio_spte_mask(mask);
5771}
5772
16e8d74d
MT		 5773#ifdef CONFIG_X86_64
5774static void pvclock_gtod_update_fn(struct work_struct *work)
5775{
d828199e
MT		 5776 struct kvm *kvm;
5777
5778 struct kvm_vcpu *vcpu;
5779 int i;
5780
2f303b74 5781 spin_lock(&kvm_lock);
d828199e
MT		 5782 list_for_each_entry(kvm, &vm_list, vm_list)
5783 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5784 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5785 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5786 spin_unlock(&kvm_lock);
16e8d74d
MT		 5787}
5788
5789static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5790
5791/*
5792 * Notification about pvclock gtod data update.
5793 */
5794static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5795 void *priv)
5796{
5797 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5798 struct timekeeper *tk = priv;
5799
5800 update_pvclock_gtod(tk);
5801
5802 /* disable master clock if host does not trust, or does not
5803 * use, TSC clocksource
5804 */
5805 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5806 atomic_read(&kvm_guest_has_master_clock) != 0)
5807 queue_work(system_long_wq, &pvclock_gtod_work);
5808
5809 return 0;
5810}
5811
5812static struct notifier_block pvclock_gtod_notifier = {
5813 .notifier_call = pvclock_gtod_notify,
5814};
5815#endif
5816
f8c16bba 5817int kvm_arch_init(void *opaque)
043405e1 5818{
b820cc0c 5819 int r;
6b61edf7 5820 struct kvm_x86_ops *ops = opaque;
f8c16bba 5821
f8c16bba
ZX		 5822 if (kvm_x86_ops) {
5823 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5824 r = -EEXIST;
5825 goto out;
f8c16bba
ZX		 5826 }
5827
5828 if (!ops->cpu_has_kvm_support()) {
5829 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5830 r = -EOPNOTSUPP;
5831 goto out;
f8c16bba
ZX		 5832 }
5833 if (ops->disabled_by_bios()) {
5834 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5835 r = -EOPNOTSUPP;
5836 goto out;
f8c16bba
ZX		 5837 }
5838
013f6a5d
MT		 5839 r = -ENOMEM;
5840 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5841 if (!shared_msrs) {
5842 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5843 goto out;
5844 }
5845
97db56ce
AK		 5846 r = kvm_mmu_module_init();
5847 if (r)
013f6a5d 5848 goto out_free_percpu;
97db56ce 5849
ce88decf 5850 kvm_set_mmio_spte_mask();
97db56ce 5851
f8c16bba 5852 kvm_x86_ops = ops;
920c8377 5853
7b52345e 5854 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5855 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5856
b820cc0c 5857 kvm_timer_init();
c8076604 5858
ff9d07a0
ZY		 5859 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5860
2acf923e
DC		 5861 if (cpu_has_xsave)
5862 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5863
c5cc421b 5864 kvm_lapic_init();
16e8d74d
MT		 5865#ifdef CONFIG_X86_64
5866 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5867#endif
5868
f8c16bba 5869 return 0;
56c6d28a 5870
013f6a5d
MT		 5871out_free_percpu:
5872 free_percpu(shared_msrs);
56c6d28a 5873out:
56c6d28a 5874 return r;
043405e1 5875}
8776e519 5876
f8c16bba
ZX		 5877void kvm_arch_exit(void)
5878{
ff9d07a0
ZY		 5879 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5880
888d256e
JK		 5881 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5882 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5883 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5884 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5885#ifdef CONFIG_X86_64
5886 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5887#endif
f8c16bba 5888 kvm_x86_ops = NULL;
56c6d28a 5889 kvm_mmu_module_exit();
013f6a5d 5890 free_percpu(shared_msrs);
56c6d28a 5891}
f8c16bba 5892
5cb56059 5893int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5894{
5895 ++vcpu->stat.halt_exits;
35754c98 5896 if (lapic_in_kernel(vcpu)) {
a4535290 5897 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5898 return 1;
5899 } else {
5900 vcpu->run->exit_reason = KVM_EXIT_HLT;
5901 return 0;
5902 }
5903}
5cb56059
JS		 5904EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5905
5906int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5907{
5908 kvm_x86_ops->skip_emulated_instruction(vcpu);
5909 return kvm_vcpu_halt(vcpu);
5910}
8776e519
HB		 5911EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5912
6aef266c
SV		 5913/*
5914 * kvm_pv_kick_cpu_op: Kick a vcpu.
5915 *
5916 * @apicid - apicid of vcpu to be kicked.
5917 */
5918static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5919{
24d2166b 5920 struct kvm_lapic_irq lapic_irq;
6aef266c 5921
24d2166b
R		 5922 lapic_irq.shorthand = 0;
5923 lapic_irq.dest_mode = 0;
5924 lapic_irq.dest_id = apicid;
93bbf0b8 5925 lapic_irq.msi_redir_hint = false;
6aef266c 5926
24d2166b 5927 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5928 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5929}
5930
d62caabb
AS		 5931void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5932{
5933 vcpu->arch.apicv_active = false;
5934 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5935}
5936
8776e519
HB		 5937int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5938{
5939 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5940 int op_64_bit, r = 1;
8776e519 5941
5cb56059
JS		 5942 kvm_x86_ops->skip_emulated_instruction(vcpu);
5943
55cd8e5a
GN		 5944 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5945 return kvm_hv_hypercall(vcpu);
5946
5fdbf976
MT		 5947 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5948 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5949 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5950 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5951 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5952
229456fc 5953 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5954
a449c7aa
NA		 5955 op_64_bit = is_64_bit_mode(vcpu);
5956 if (!op_64_bit) {
8776e519
HB		 5957 nr &= 0xFFFFFFFF;
5958 a0 &= 0xFFFFFFFF;
5959 a1 &= 0xFFFFFFFF;
5960 a2 &= 0xFFFFFFFF;
5961 a3 &= 0xFFFFFFFF;
5962 }
5963
07708c4a
JK		 5964 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5965 ret = -KVM_EPERM;
5966 goto out;
5967 }
5968
8776e519 5969 switch (nr) {
b93463aa
AK		 5970 case KVM_HC_VAPIC_POLL_IRQ:
5971 ret = 0;
5972 break;
6aef266c
SV		 5973 case KVM_HC_KICK_CPU:
5974 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5975 ret = 0;
5976 break;
8776e519
HB		 5977 default:
5978 ret = -KVM_ENOSYS;
5979 break;
5980 }
07708c4a 5981out:
a449c7aa
NA		 5982 if (!op_64_bit)
5983 ret = (u32)ret;
5fdbf976 5984 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5985 ++vcpu->stat.hypercalls;
2f333bcb 5986 return r;
8776e519
HB		 5987}
5988EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5989
b6785def 5990static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5991{
d6aa1000 5992 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5993 char instruction[3];
5fdbf976 5994 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5995
8776e519 5996 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5997
9d74191a 5998 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5999}
6000
851ba692 6001static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6002{
782d422b
MG		 6003 return vcpu->run->request_interrupt_window &&
6004 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6005}
6006
851ba692 6007static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6008{
851ba692
AK		 6009 struct kvm_run *kvm_run = vcpu->run;
6010
91586a3b 6011 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6012 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6013 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6014 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6015 kvm_run->ready_for_interrupt_injection =
6016 pic_in_kernel(vcpu->kvm) ||
782d422b 6017 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6018}
6019
95ba8273
GN		 6020static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6021{
6022 int max_irr, tpr;
6023
6024 if (!kvm_x86_ops->update_cr8_intercept)
6025 return;
6026
bce87cce 6027 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6028 return;
6029
d62caabb
AS		 6030 if (vcpu->arch.apicv_active)
6031 return;
6032
8db3baa2
GN		 6033 if (!vcpu->arch.apic->vapic_addr)
6034 max_irr = kvm_lapic_find_highest_irr(vcpu);
6035 else
6036 max_irr = -1;
95ba8273
GN		 6037
6038 if (max_irr != -1)
6039 max_irr >>= 4;
6040
6041 tpr = kvm_lapic_get_cr8(vcpu);
6042
6043 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6044}
6045
b6b8a145 6046static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6047{
b6b8a145
JK		 6048 int r;
6049
95ba8273 6050 /* try to reinject previous events if any */
b59bb7bd 6051 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6052 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6053 vcpu->arch.exception.has_error_code,
6054 vcpu->arch.exception.error_code);
d6e8c854
NA		 6055
6056 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6057 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6058 X86_EFLAGS_RF);
6059
6bdf0662
NA		 6060 if (vcpu->arch.exception.nr == DB_VECTOR &&
6061 (vcpu->arch.dr7 & DR7_GD)) {
6062 vcpu->arch.dr7 &= ~DR7_GD;
6063 kvm_update_dr7(vcpu);
6064 }
6065
b59bb7bd
GN		 6066 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6067 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6068 vcpu->arch.exception.error_code,
6069 vcpu->arch.exception.reinject);
b6b8a145 6070 return 0;
b59bb7bd
GN		 6071 }
6072
95ba8273
GN		 6073 if (vcpu->arch.nmi_injected) {
6074 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6075 return 0;
95ba8273
GN		 6076 }
6077
6078 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6079 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6080 return 0;
6081 }
6082
6083 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6084 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6085 if (r != 0)
6086 return r;
95ba8273
GN		 6087 }
6088
6089 /* try to inject new event if pending */
6090 if (vcpu->arch.nmi_pending) {
6091 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6092 --vcpu->arch.nmi_pending;
95ba8273
GN		 6093 vcpu->arch.nmi_injected = true;
6094 kvm_x86_ops->set_nmi(vcpu);
6095 }
c7c9c56c 6096 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6097 /*
6098 * Because interrupts can be injected asynchronously, we are
6099 * calling check_nested_events again here to avoid a race condition.
6100 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6101 * proposal and current concerns. Perhaps we should be setting
6102 * KVM_REQ_EVENT only on certain events and not unconditionally?
6103 */
6104 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6105 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6106 if (r != 0)
6107 return r;
6108 }
95ba8273 6109 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6110 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6111 false);
6112 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6113 }
6114 }
b6b8a145 6115 return 0;
95ba8273
GN		 6116}
6117
7460fb4a
AK		 6118static void process_nmi(struct kvm_vcpu *vcpu)
6119{
6120 unsigned limit = 2;
6121
6122 /*
6123 * x86 is limited to one NMI running, and one NMI pending after it.
6124 * If an NMI is already in progress, limit further NMIs to just one.
6125 * Otherwise, allow two (and we'll inject the first one immediately).
6126 */
6127 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6128 limit = 1;
6129
6130 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6131 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6132 kvm_make_request(KVM_REQ_EVENT, vcpu);
6133}
6134
660a5d51
PB		 6135#define put_smstate(type, buf, offset, val) \
6136 *(type *)((buf) + (offset) - 0x7e00) = val
6137
6138static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6139{
6140 u32 flags = 0;
6141 flags |= seg->g << 23;
6142 flags |= seg->db << 22;
6143 flags |= seg->l << 21;
6144 flags |= seg->avl << 20;
6145 flags |= seg->present << 15;
6146 flags |= seg->dpl << 13;
6147 flags |= seg->s << 12;
6148 flags |= seg->type << 8;
6149 return flags;
6150}
6151
6152static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6153{
6154 struct kvm_segment seg;
6155 int offset;
6156
6157 kvm_get_segment(vcpu, &seg, n);
6158 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6159
6160 if (n < 3)
6161 offset = 0x7f84 + n * 12;
6162 else
6163 offset = 0x7f2c + (n - 3) * 12;
6164
6165 put_smstate(u32, buf, offset + 8, seg.base);
6166 put_smstate(u32, buf, offset + 4, seg.limit);
6167 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6168}
6169
efbb288a 6170#ifdef CONFIG_X86_64
660a5d51
PB		 6171static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6172{
6173 struct kvm_segment seg;
6174 int offset;
6175 u16 flags;
6176
6177 kvm_get_segment(vcpu, &seg, n);
6178 offset = 0x7e00 + n * 16;
6179
6180 flags = process_smi_get_segment_flags(&seg) >> 8;
6181 put_smstate(u16, buf, offset, seg.selector);
6182 put_smstate(u16, buf, offset + 2, flags);
6183 put_smstate(u32, buf, offset + 4, seg.limit);
6184 put_smstate(u64, buf, offset + 8, seg.base);
6185}
efbb288a 6186#endif
660a5d51
PB		 6187
6188static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6189{
6190 struct desc_ptr dt;
6191 struct kvm_segment seg;
6192 unsigned long val;
6193 int i;
6194
6195 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6196 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6197 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6198 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6199
6200 for (i = 0; i < 8; i++)
6201 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6202
6203 kvm_get_dr(vcpu, 6, &val);
6204 put_smstate(u32, buf, 0x7fcc, (u32)val);
6205 kvm_get_dr(vcpu, 7, &val);
6206 put_smstate(u32, buf, 0x7fc8, (u32)val);
6207
6208 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6209 put_smstate(u32, buf, 0x7fc4, seg.selector);
6210 put_smstate(u32, buf, 0x7f64, seg.base);
6211 put_smstate(u32, buf, 0x7f60, seg.limit);
6212 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6213
6214 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6215 put_smstate(u32, buf, 0x7fc0, seg.selector);
6216 put_smstate(u32, buf, 0x7f80, seg.base);
6217 put_smstate(u32, buf, 0x7f7c, seg.limit);
6218 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6219
6220 kvm_x86_ops->get_gdt(vcpu, &dt);
6221 put_smstate(u32, buf, 0x7f74, dt.address);
6222 put_smstate(u32, buf, 0x7f70, dt.size);
6223
6224 kvm_x86_ops->get_idt(vcpu, &dt);
6225 put_smstate(u32, buf, 0x7f58, dt.address);
6226 put_smstate(u32, buf, 0x7f54, dt.size);
6227
6228 for (i = 0; i < 6; i++)
6229 process_smi_save_seg_32(vcpu, buf, i);
6230
6231 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6232
6233 /* revision id */
6234 put_smstate(u32, buf, 0x7efc, 0x00020000);
6235 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6236}
6237
6238static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6239{
6240#ifdef CONFIG_X86_64
6241 struct desc_ptr dt;
6242 struct kvm_segment seg;
6243 unsigned long val;
6244 int i;
6245
6246 for (i = 0; i < 16; i++)
6247 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6248
6249 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6250 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6251
6252 kvm_get_dr(vcpu, 6, &val);
6253 put_smstate(u64, buf, 0x7f68, val);
6254 kvm_get_dr(vcpu, 7, &val);
6255 put_smstate(u64, buf, 0x7f60, val);
6256
6257 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6258 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6259 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6260
6261 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6262
6263 /* revision id */
6264 put_smstate(u32, buf, 0x7efc, 0x00020064);
6265
6266 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6267
6268 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6269 put_smstate(u16, buf, 0x7e90, seg.selector);
6270 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6271 put_smstate(u32, buf, 0x7e94, seg.limit);
6272 put_smstate(u64, buf, 0x7e98, seg.base);
6273
6274 kvm_x86_ops->get_idt(vcpu, &dt);
6275 put_smstate(u32, buf, 0x7e84, dt.size);
6276 put_smstate(u64, buf, 0x7e88, dt.address);
6277
6278 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6279 put_smstate(u16, buf, 0x7e70, seg.selector);
6280 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6281 put_smstate(u32, buf, 0x7e74, seg.limit);
6282 put_smstate(u64, buf, 0x7e78, seg.base);
6283
6284 kvm_x86_ops->get_gdt(vcpu, &dt);
6285 put_smstate(u32, buf, 0x7e64, dt.size);
6286 put_smstate(u64, buf, 0x7e68, dt.address);
6287
6288 for (i = 0; i < 6; i++)
6289 process_smi_save_seg_64(vcpu, buf, i);
6290#else
6291 WARN_ON_ONCE(1);
6292#endif
6293}
6294
64d60670
PB		 6295static void process_smi(struct kvm_vcpu *vcpu)
6296{
660a5d51 6297 struct kvm_segment cs, ds;
18c3626e 6298 struct desc_ptr dt;
660a5d51
PB		 6299 char buf[512];
6300 u32 cr0;
6301
64d60670
PB		 6302 if (is_smm(vcpu)) {
6303 vcpu->arch.smi_pending = true;
6304 return;
6305 }
6306
660a5d51
PB		 6307 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6308 vcpu->arch.hflags |= HF_SMM_MASK;
6309 memset(buf, 0, 512);
6310 if (guest_cpuid_has_longmode(vcpu))
6311 process_smi_save_state_64(vcpu, buf);
6312 else
6313 process_smi_save_state_32(vcpu, buf);
6314
54bf36aa 6315 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6316
6317 if (kvm_x86_ops->get_nmi_mask(vcpu))
6318 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6319 else
6320 kvm_x86_ops->set_nmi_mask(vcpu, true);
6321
6322 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6323 kvm_rip_write(vcpu, 0x8000);
6324
6325 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6326 kvm_x86_ops->set_cr0(vcpu, cr0);
6327 vcpu->arch.cr0 = cr0;
6328
6329 kvm_x86_ops->set_cr4(vcpu, 0);
6330
18c3626e
PB		 6331 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6332 dt.address = dt.size = 0;
6333 kvm_x86_ops->set_idt(vcpu, &dt);
6334
660a5d51
PB		 6335 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6336
6337 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6338 cs.base = vcpu->arch.smbase;
6339
6340 ds.selector = 0;
6341 ds.base = 0;
6342
6343 cs.limit = ds.limit = 0xffffffff;
6344 cs.type = ds.type = 0x3;
6345 cs.dpl = ds.dpl = 0;
6346 cs.db = ds.db = 0;
6347 cs.s = ds.s = 1;
6348 cs.l = ds.l = 0;
6349 cs.g = ds.g = 1;
6350 cs.avl = ds.avl = 0;
6351 cs.present = ds.present = 1;
6352 cs.unusable = ds.unusable = 0;
6353 cs.padding = ds.padding = 0;
6354
6355 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6356 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6357 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6358 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6359 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6360 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6361
6362 if (guest_cpuid_has_longmode(vcpu))
6363 kvm_x86_ops->set_efer(vcpu, 0);
6364
6365 kvm_update_cpuid(vcpu);
6366 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6367}
6368
2860c4b1
PB		 6369void kvm_make_scan_ioapic_request(struct kvm *kvm)
6370{
6371 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6372}
6373
3d81bc7e 6374static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6375{
5c919412
AS		 6376 u64 eoi_exit_bitmap[4];
6377
3d81bc7e
YZ		 6378 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6379 return;
c7c9c56c 6380
6308630b 6381 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6382
b053b2ae 6383 if (irqchip_split(vcpu->kvm))
6308630b 6384 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6385 else {
d62caabb
AS		 6386 if (vcpu->arch.apicv_active)
6387 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6388 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6389 }
5c919412
AS		 6390 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6391 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6392 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6393}
6394
a70656b6
RK		 6395static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6396{
6397 ++vcpu->stat.tlb_flush;
6398 kvm_x86_ops->tlb_flush(vcpu);
6399}
6400
4256f43f
TC		 6401void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6402{
c24ae0dc
TC		 6403 struct page *page = NULL;
6404
35754c98 6405 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6406 return;
6407
4256f43f
TC		 6408 if (!kvm_x86_ops->set_apic_access_page_addr)
6409 return;
6410
c24ae0dc 6411 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6412 if (is_error_page(page))
6413 return;
c24ae0dc
TC		 6414 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6415
6416 /*
6417 * Do not pin apic access page in memory, the MMU notifier
6418 * will call us again if it is migrated or swapped out.
6419 */
6420 put_page(page);
4256f43f
TC		 6421}
6422EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6423
fe71557a
TC		 6424void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6425 unsigned long address)
6426{
c24ae0dc
TC		 6427 /*
6428 * The physical address of apic access page is stored in the VMCS.
6429 * Update it when it becomes invalid.
6430 */
6431 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6432 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6433}
6434
9357d939 6435/*
362c698f 6436 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6437 * exiting to the userspace. Otherwise, the value will be returned to the
6438 * userspace.
6439 */
851ba692 6440static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6441{
6442 int r;
62a193ed
MG		 6443 bool req_int_win =
6444 dm_request_for_irq_injection(vcpu) &&
6445 kvm_cpu_accept_dm_intr(vcpu);
6446
730dca42 6447 bool req_immediate_exit = false;
b6c7a5dc 6448
3e007509 6449 if (vcpu->requests) {
a8eeb04a 6450 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6451 kvm_mmu_unload(vcpu);
a8eeb04a 6452 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6453 __kvm_migrate_timers(vcpu);
d828199e
MT		 6454 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6455 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6456 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6457 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6458 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6459 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6460 if (unlikely(r))
6461 goto out;
6462 }
a8eeb04a 6463 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6464 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6465 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6466 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6467 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6468 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6469 r = 0;
6470 goto out;
6471 }
a8eeb04a 6472 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6473 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6474 r = 0;
6475 goto out;
6476 }
a8eeb04a 6477 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6478 vcpu->fpu_active = 0;
6479 kvm_x86_ops->fpu_deactivate(vcpu);
6480 }
af585b92
GN		 6481 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6482 /* Page is swapped out. Do synthetic halt */
6483 vcpu->arch.apf.halted = true;
6484 r = 1;
6485 goto out;
6486 }
c9aaa895
GC		 6487 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6488 record_steal_time(vcpu);
64d60670
PB		 6489 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6490 process_smi(vcpu);
7460fb4a
AK		 6491 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6492 process_nmi(vcpu);
f5132b01 6493 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6494 kvm_pmu_handle_event(vcpu);
f5132b01 6495 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6496 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6497 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6498 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6499 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6500 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6501 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6502 vcpu->run->eoi.vector =
6503 vcpu->arch.pending_ioapic_eoi;
6504 r = 0;
6505 goto out;
6506 }
6507 }
3d81bc7e
YZ		 6508 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6509 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6510 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6511 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6512 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6513 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6514 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6515 r = 0;
6516 goto out;
6517 }
e516cebb
AS		 6518 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6519 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6520 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6521 r = 0;
6522 goto out;
6523 }
db397571
AS		 6524 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6525 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6526 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6527 r = 0;
6528 goto out;
6529 }
f3b138c5
AS		 6530
6531 /*
6532 * KVM_REQ_HV_STIMER has to be processed after
6533 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6534 * depend on the guest clock being up-to-date
6535 */
1f4b34f8
AS		 6536 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6537 kvm_hv_process_stimers(vcpu);
2f52d58c 6538 }
b93463aa 6539
bf9f6ac8
FW		 6540 /*
6541 * KVM_REQ_EVENT is not set when posted interrupts are set by
6542 * VT-d hardware, so we have to update RVI unconditionally.
6543 */
6544 if (kvm_lapic_enabled(vcpu)) {
6545 /*
6546 * Update architecture specific hints for APIC
6547 * virtual interrupt delivery.
6548 */
d62caabb 6549 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6550 kvm_x86_ops->hwapic_irr_update(vcpu,
6551 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6552 }
b93463aa 6553
b463a6f7 6554 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6555 kvm_apic_accept_events(vcpu);
6556 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6557 r = 1;
6558 goto out;
6559 }
6560
b6b8a145
JK		 6561 if (inject_pending_event(vcpu, req_int_win) != 0)
6562 req_immediate_exit = true;
b463a6f7 6563 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6564 else if (vcpu->arch.nmi_pending)
c9a7953f 6565 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6566 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6567 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6568
6569 if (kvm_lapic_enabled(vcpu)) {
6570 update_cr8_intercept(vcpu);
6571 kvm_lapic_sync_to_vapic(vcpu);
6572 }
6573 }
6574
d8368af8
AK		 6575 r = kvm_mmu_reload(vcpu);
6576 if (unlikely(r)) {
d905c069 6577 goto cancel_injection;
d8368af8
AK		 6578 }
6579
b6c7a5dc
HB		 6580 preempt_disable();
6581
6582 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6583 if (vcpu->fpu_active)
6584 kvm_load_guest_fpu(vcpu);
2acf923e 6585 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6586
6b7e2d09
XG		 6587 vcpu->mode = IN_GUEST_MODE;
6588
01b71917
MT		 6589 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6590
6b7e2d09
XG		 6591 /* We should set ->mode before check ->requests,
6592 * see the comment in make_all_cpus_request.
6593 */
01b71917 6594 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6595
d94e1dc9 6596 local_irq_disable();
32f88400 6597
6b7e2d09 6598 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6599 || need_resched() || signal_pending(current)) {
6b7e2d09 6600 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6601 smp_wmb();
6c142801
AK		 6602 local_irq_enable();
6603 preempt_enable();
01b71917 6604 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6605 r = 1;
d905c069 6606 goto cancel_injection;
6c142801
AK		 6607 }
6608
d6185f20
NHE		 6609 if (req_immediate_exit)
6610 smp_send_reschedule(vcpu->cpu);
6611
8b89fe1f
PB		 6612 trace_kvm_entry(vcpu->vcpu_id);
6613 wait_lapic_expire(vcpu);
ccf73aaf 6614 __kvm_guest_enter();
b6c7a5dc 6615
42dbaa5a 6616 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6617 set_debugreg(0, 7);
6618 set_debugreg(vcpu->arch.eff_db[0], 0);
6619 set_debugreg(vcpu->arch.eff_db[1], 1);
6620 set_debugreg(vcpu->arch.eff_db[2], 2);
6621 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6622 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6623 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6624 }
b6c7a5dc 6625
851ba692 6626 kvm_x86_ops->run(vcpu);
b6c7a5dc 6627
c77fb5fe
PB		 6628 /*
6629 * Do this here before restoring debug registers on the host. And
6630 * since we do this before handling the vmexit, a DR access vmexit
6631 * can (a) read the correct value of the debug registers, (b) set
6632 * KVM_DEBUGREG_WONT_EXIT again.
6633 */
6634 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6635 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6636 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6637 kvm_update_dr0123(vcpu);
6638 kvm_update_dr6(vcpu);
6639 kvm_update_dr7(vcpu);
6640 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6641 }
6642
24f1e32c
FW		 6643 /*
6644 * If the guest has used debug registers, at least dr7
6645 * will be disabled while returning to the host.
6646 * If we don't have active breakpoints in the host, we don't
6647 * care about the messed up debug address registers. But if
6648 * we have some of them active, restore the old state.
6649 */
59d8eb53 6650 if (hw_breakpoint_active())
24f1e32c 6651 hw_breakpoint_restore();
42dbaa5a 6652
4ba76538 6653 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6654
6b7e2d09 6655 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6656 smp_wmb();
a547c6db
YZ		 6657
6658 /* Interrupt is enabled by handle_external_intr() */
6659 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6660
6661 ++vcpu->stat.exits;
6662
6663 /*
6664 * We must have an instruction between local_irq_enable() and
6665 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6666 * the interrupt shadow. The stat.exits increment will do nicely.
6667 * But we need to prevent reordering, hence this barrier():
6668 */
6669 barrier();
6670
6671 kvm_guest_exit();
6672
6673 preempt_enable();
6674
f656ce01 6675 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6676
b6c7a5dc
HB		 6677 /*
6678 * Profile KVM exit RIPs:
6679 */
6680 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6681 unsigned long rip = kvm_rip_read(vcpu);
6682 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6683 }
6684
cc578287
ZA		 6685 if (unlikely(vcpu->arch.tsc_always_catchup))
6686 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6687
5cfb1d5a
MT		 6688 if (vcpu->arch.apic_attention)
6689 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6690
851ba692 6691 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6692 return r;
6693
6694cancel_injection:
6695 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6696 if (unlikely(vcpu->arch.apic_attention))
6697 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6698out:
6699 return r;
6700}
b6c7a5dc 6701
362c698f
PB		 6702static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6703{
bf9f6ac8
FW		 6704 if (!kvm_arch_vcpu_runnable(vcpu) &&
6705 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6706 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6707 kvm_vcpu_block(vcpu);
6708 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6709
6710 if (kvm_x86_ops->post_block)
6711 kvm_x86_ops->post_block(vcpu);
6712
9c8fd1ba
PB		 6713 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6714 return 1;
6715 }
362c698f
PB		 6716
6717 kvm_apic_accept_events(vcpu);
6718 switch(vcpu->arch.mp_state) {
6719 case KVM_MP_STATE_HALTED:
6720 vcpu->arch.pv.pv_unhalted = false;
6721 vcpu->arch.mp_state =
6722 KVM_MP_STATE_RUNNABLE;
6723 case KVM_MP_STATE_RUNNABLE:
6724 vcpu->arch.apf.halted = false;
6725 break;
6726 case KVM_MP_STATE_INIT_RECEIVED:
6727 break;
6728 default:
6729 return -EINTR;
6730 break;
6731 }
6732 return 1;
6733}
09cec754 6734
5d9bc648
PB		 6735static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6736{
6737 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6738 !vcpu->arch.apf.halted);
6739}
6740
362c698f 6741static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6742{
6743 int r;
f656ce01 6744 struct kvm *kvm = vcpu->kvm;
d7690175 6745
f656ce01 6746 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6747
362c698f 6748 for (;;) {
58f800d5 6749 if (kvm_vcpu_running(vcpu)) {
851ba692 6750 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6751 } else {
362c698f 6752 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6753 }
6754
09cec754
GN		 6755 if (r <= 0)
6756 break;
6757
6758 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6759 if (kvm_cpu_has_pending_timer(vcpu))
6760 kvm_inject_pending_timer_irqs(vcpu);
6761
782d422b
MG		 6762 if (dm_request_for_irq_injection(vcpu) &&
6763 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6764 r = 0;
6765 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6766 ++vcpu->stat.request_irq_exits;
362c698f 6767 break;
09cec754 6768 }
af585b92
GN		 6769
6770 kvm_check_async_pf_completion(vcpu);
6771
09cec754
GN		 6772 if (signal_pending(current)) {
6773 r = -EINTR;
851ba692 6774 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6775 ++vcpu->stat.signal_exits;
362c698f 6776 break;
09cec754
GN		 6777 }
6778 if (need_resched()) {
f656ce01 6779 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6780 cond_resched();
f656ce01 6781 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6782 }
b6c7a5dc
HB		 6783 }
6784
f656ce01 6785 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6786
6787 return r;
6788}
6789
716d51ab
GN		 6790static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6791{
6792 int r;
6793 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6794 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6795 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6796 if (r != EMULATE_DONE)
6797 return 0;
6798 return 1;
6799}
6800
6801static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6802{
6803 BUG_ON(!vcpu->arch.pio.count);
6804
6805 return complete_emulated_io(vcpu);
6806}
6807
f78146b0
AK		 6808/*
6809 * Implements the following, as a state machine:
6810 *
6811 * read:
6812 * for each fragment
87da7e66
XG		 6813 * for each mmio piece in the fragment
6814 * write gpa, len
6815 * exit
6816 * copy data
f78146b0
AK		 6817 * execute insn
6818 *
6819 * write:
6820 * for each fragment
87da7e66
XG		 6821 * for each mmio piece in the fragment
6822 * write gpa, len
6823 * copy data
6824 * exit
f78146b0 6825 */
716d51ab 6826static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6827{
6828 struct kvm_run *run = vcpu->run;
f78146b0 6829 struct kvm_mmio_fragment *frag;
87da7e66 6830 unsigned len;
5287f194 6831
716d51ab 6832 BUG_ON(!vcpu->mmio_needed);
5287f194 6833
716d51ab 6834 /* Complete previous fragment */
87da7e66
XG		 6835 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6836 len = min(8u, frag->len);
716d51ab 6837 if (!vcpu->mmio_is_write)
87da7e66
XG		 6838 memcpy(frag->data, run->mmio.data, len);
6839
6840 if (frag->len <= 8) {
6841 /* Switch to the next fragment. */
6842 frag++;
6843 vcpu->mmio_cur_fragment++;
6844 } else {
6845 /* Go forward to the next mmio piece. */
6846 frag->data += len;
6847 frag->gpa += len;
6848 frag->len -= len;
6849 }
6850
a08d3b3b 6851 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6852 vcpu->mmio_needed = 0;
0912c977
PB		 6853
6854 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6855 if (vcpu->mmio_is_write)
716d51ab
GN		 6856 return 1;
6857 vcpu->mmio_read_completed = 1;
6858 return complete_emulated_io(vcpu);
6859 }
87da7e66 6860
716d51ab
GN		 6861 run->exit_reason = KVM_EXIT_MMIO;
6862 run->mmio.phys_addr = frag->gpa;
6863 if (vcpu->mmio_is_write)
87da7e66
XG		 6864 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6865 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6866 run->mmio.is_write = vcpu->mmio_is_write;
6867 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6868 return 0;
5287f194
AK		 6869}
6870
716d51ab 6871
b6c7a5dc
HB		 6872int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6873{
c5bedc68 6874 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6875 int r;
6876 sigset_t sigsaved;
6877
c4d72e2d 6878 fpu__activate_curr(fpu);
e5c30142 6879
ac9f6dc0
AK		 6880 if (vcpu->sigset_active)
6881 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6882
a4535290 6883 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6884 kvm_vcpu_block(vcpu);
66450a21 6885 kvm_apic_accept_events(vcpu);
d7690175 6886 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6887 r = -EAGAIN;
6888 goto out;
b6c7a5dc
HB		 6889 }
6890
b6c7a5dc 6891 /* re-sync apic's tpr */
35754c98 6892 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6893 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6894 r = -EINVAL;
6895 goto out;
6896 }
6897 }
b6c7a5dc 6898
716d51ab
GN		 6899 if (unlikely(vcpu->arch.complete_userspace_io)) {
6900 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6901 vcpu->arch.complete_userspace_io = NULL;
6902 r = cui(vcpu);
6903 if (r <= 0)
6904 goto out;
6905 } else
6906 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6907
362c698f 6908 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6909
6910out:
f1d86e46 6911 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6912 if (vcpu->sigset_active)
6913 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6914
b6c7a5dc
HB		 6915 return r;
6916}
6917
6918int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6919{
7ae441ea
GN		 6920 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6921 /*
6922 * We are here if userspace calls get_regs() in the middle of
6923 * instruction emulation. Registers state needs to be copied
4a969980 6924 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6925 * that usually, but some bad designed PV devices (vmware
6926 * backdoor interface) need this to work
6927 */
dd856efa 6928 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6929 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6930 }
5fdbf976
MT		 6931 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6932 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6933 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6934 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6935 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6936 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6937 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6938 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6939#ifdef CONFIG_X86_64
5fdbf976
MT		 6940 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6941 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6942 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6943 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6944 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6945 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6946 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6947 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6948#endif
6949
5fdbf976 6950 regs->rip = kvm_rip_read(vcpu);
91586a3b 6951 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6952
b6c7a5dc
HB		 6953 return 0;
6954}
6955
6956int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6957{
7ae441ea
GN		 6958 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6959 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6960
5fdbf976
MT		 6961 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6962 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6963 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6964 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6965 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6966 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6967 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6968 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6969#ifdef CONFIG_X86_64
5fdbf976
MT		 6970 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6971 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6972 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6973 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6974 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6975 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6976 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6977 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6978#endif
6979
5fdbf976 6980 kvm_rip_write(vcpu, regs->rip);
91586a3b 6981 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6982
b4f14abd
JK		 6983 vcpu->arch.exception.pending = false;
6984
3842d135
AK		 6985 kvm_make_request(KVM_REQ_EVENT, vcpu);
6986
b6c7a5dc
HB		 6987 return 0;
6988}
6989
b6c7a5dc
HB		 6990void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6991{
6992 struct kvm_segment cs;
6993
3e6e0aab 6994 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6995 *db = cs.db;
6996 *l = cs.l;
6997}
6998EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6999
7000int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7001 struct kvm_sregs *sregs)
7002{
89a27f4d 7003 struct desc_ptr dt;
b6c7a5dc 7004
3e6e0aab
GT		 7005 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7006 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7007 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7008 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7009 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7010 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7011
3e6e0aab
GT		 7012 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7013 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7014
7015 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7016 sregs->idt.limit = dt.size;
7017 sregs->idt.base = dt.address;
b6c7a5dc 7018 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7019 sregs->gdt.limit = dt.size;
7020 sregs->gdt.base = dt.address;
b6c7a5dc 7021
4d4ec087 7022 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7023 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7024 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7025 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7026 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7027 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7028 sregs->apic_base = kvm_get_apic_base(vcpu);
7029
923c61bb 7030 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7031
36752c9b 7032 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7033 set_bit(vcpu->arch.interrupt.nr,
7034 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7035
b6c7a5dc
HB		 7036 return 0;
7037}
7038
62d9f0db
MT		 7039int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7040 struct kvm_mp_state *mp_state)
7041{
66450a21 7042 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7043 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7044 vcpu->arch.pv.pv_unhalted)
7045 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7046 else
7047 mp_state->mp_state = vcpu->arch.mp_state;
7048
62d9f0db
MT		 7049 return 0;
7050}
7051
7052int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7053 struct kvm_mp_state *mp_state)
7054{
bce87cce 7055 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7056 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7057 return -EINVAL;
7058
7059 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7060 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7061 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7062 } else
7063 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7064 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7065 return 0;
7066}
7067
7f3d35fd
KW		 7068int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7069 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7070{
9d74191a 7071 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7072 int ret;
e01c2426 7073
8ec4722d 7074 init_emulate_ctxt(vcpu);
c697518a 7075
7f3d35fd 7076 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7077 has_error_code, error_code);
c697518a 7078
c697518a 7079 if (ret)
19d04437 7080 return EMULATE_FAIL;
37817f29 7081
9d74191a
TY		 7082 kvm_rip_write(vcpu, ctxt->eip);
7083 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7084 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7085 return EMULATE_DONE;
37817f29
IE		 7086}
7087EXPORT_SYMBOL_GPL(kvm_task_switch);
7088
b6c7a5dc
HB		 7089int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7090 struct kvm_sregs *sregs)
7091{
58cb628d 7092 struct msr_data apic_base_msr;
b6c7a5dc 7093 int mmu_reset_needed = 0;
63f42e02 7094 int pending_vec, max_bits, idx;
89a27f4d 7095 struct desc_ptr dt;
b6c7a5dc 7096
6d1068b3
PM		 7097 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7098 return -EINVAL;
7099
89a27f4d
GN		 7100 dt.size = sregs->idt.limit;
7101 dt.address = sregs->idt.base;
b6c7a5dc 7102 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7103 dt.size = sregs->gdt.limit;
7104 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7105 kvm_x86_ops->set_gdt(vcpu, &dt);
7106
ad312c7c 7107 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7108 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7109 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7110 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7111
2d3ad1f4 7112 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7113
f6801dff 7114 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7115 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7116 apic_base_msr.data = sregs->apic_base;
7117 apic_base_msr.host_initiated = true;
7118 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7119
4d4ec087 7120 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7121 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7122 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7123
fc78f519 7124 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7125 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7126 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7127 kvm_update_cpuid(vcpu);
63f42e02
XG		 7128
7129 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7130 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7131 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7132 mmu_reset_needed = 1;
7133 }
63f42e02 7134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7135
7136 if (mmu_reset_needed)
7137 kvm_mmu_reset_context(vcpu);
7138
a50abc3b 7139 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7140 pending_vec = find_first_bit(
7141 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7142 if (pending_vec < max_bits) {
66fd3f7f 7143 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7144 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7145 }
7146
3e6e0aab
GT		 7147 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7148 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7149 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7150 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7151 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7152 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7153
3e6e0aab
GT		 7154 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7155 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7156
5f0269f5
ME		 7157 update_cr8_intercept(vcpu);
7158
9c3e4aab 7159 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7160 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7161 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7162 !is_protmode(vcpu))
9c3e4aab
MT		 7163 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7164
3842d135
AK		 7165 kvm_make_request(KVM_REQ_EVENT, vcpu);
7166
b6c7a5dc
HB		 7167 return 0;
7168}
7169
d0bfb940
JK		 7170int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7171 struct kvm_guest_debug *dbg)
b6c7a5dc 7172{
355be0b9 7173 unsigned long rflags;
ae675ef0 7174 int i, r;
b6c7a5dc 7175
4f926bf2
JK		 7176 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7177 r = -EBUSY;
7178 if (vcpu->arch.exception.pending)
2122ff5e 7179 goto out;
4f926bf2
JK		 7180 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7181 kvm_queue_exception(vcpu, DB_VECTOR);
7182 else
7183 kvm_queue_exception(vcpu, BP_VECTOR);
7184 }
7185
91586a3b
JK		 7186 /*
7187 * Read rflags as long as potentially injected trace flags are still
7188 * filtered out.
7189 */
7190 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7191
7192 vcpu->guest_debug = dbg->control;
7193 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7194 vcpu->guest_debug = 0;
7195
7196 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7197 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7198 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7199 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7200 } else {
7201 for (i = 0; i < KVM_NR_DB_REGS; i++)
7202 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7203 }
c8639010 7204 kvm_update_dr7(vcpu);
ae675ef0 7205
f92653ee
JK		 7206 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7207 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7208 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7209
91586a3b
JK		 7210 /*
7211 * Trigger an rflags update that will inject or remove the trace
7212 * flags.
7213 */
7214 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7215
a96036b8 7216 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7217
4f926bf2 7218 r = 0;
d0bfb940 7219
2122ff5e 7220out:
b6c7a5dc
HB		 7221
7222 return r;
7223}
7224
8b006791
ZX		 7225/*
7226 * Translate a guest virtual address to a guest physical address.
7227 */
7228int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7229 struct kvm_translation *tr)
7230{
7231 unsigned long vaddr = tr->linear_address;
7232 gpa_t gpa;
f656ce01 7233 int idx;
8b006791 7234
f656ce01 7235 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7236 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7237 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7238 tr->physical_address = gpa;
7239 tr->valid = gpa != UNMAPPED_GVA;
7240 tr->writeable = 1;
7241 tr->usermode = 0;
8b006791
ZX		 7242
7243 return 0;
7244}
7245
d0752060
HB		 7246int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7247{
c47ada30 7248 struct fxregs_state *fxsave =
7366ed77 7249 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7250
d0752060
HB		 7251 memcpy(fpu->fpr, fxsave->st_space, 128);
7252 fpu->fcw = fxsave->cwd;
7253 fpu->fsw = fxsave->swd;
7254 fpu->ftwx = fxsave->twd;
7255 fpu->last_opcode = fxsave->fop;
7256 fpu->last_ip = fxsave->rip;
7257 fpu->last_dp = fxsave->rdp;
7258 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7259
d0752060
HB		 7260 return 0;
7261}
7262
7263int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7264{
c47ada30 7265 struct fxregs_state *fxsave =
7366ed77 7266 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7267
d0752060
HB		 7268 memcpy(fxsave->st_space, fpu->fpr, 128);
7269 fxsave->cwd = fpu->fcw;
7270 fxsave->swd = fpu->fsw;
7271 fxsave->twd = fpu->ftwx;
7272 fxsave->fop = fpu->last_opcode;
7273 fxsave->rip = fpu->last_ip;
7274 fxsave->rdp = fpu->last_dp;
7275 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7276
d0752060
HB		 7277 return 0;
7278}
7279
0ee6a517 7280static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7281{
bf935b0b 7282 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7283 if (cpu_has_xsaves)
7366ed77 7284 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7285 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7286
2acf923e
DC		 7287 /*
7288 * Ensure guest xcr0 is valid for loading
7289 */
d91cab78 7290 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7291
ad312c7c 7292 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7293}
d0752060
HB		 7294
7295void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7296{
2608d7a1 7297 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7298 return;
7299
2acf923e
DC		 7300 /*
7301 * Restore all possible states in the guest,
7302 * and assume host would use all available bits.
7303 * Guest xcr0 would be loaded later.
7304 */
7305 kvm_put_guest_xcr0(vcpu);
d0752060 7306 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7307 __kernel_fpu_begin();
003e2e8b 7308 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7309 trace_kvm_fpu(1);
d0752060 7310}
d0752060
HB		 7311
7312void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7313{
2acf923e
DC		 7314 kvm_put_guest_xcr0(vcpu);
7315
653f52c3
RR		 7316 if (!vcpu->guest_fpu_loaded) {
7317 vcpu->fpu_counter = 0;
d0752060 7318 return;
653f52c3 7319 }
d0752060
HB		 7320
7321 vcpu->guest_fpu_loaded = 0;
4f836347 7322 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7323 __kernel_fpu_end();
f096ed85 7324 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7325 /*
7326 * If using eager FPU mode, or if the guest is a frequent user
7327 * of the FPU, just leave the FPU active for next time.
7328 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7329 * the FPU in bursts will revert to loading it on demand.
7330 */
5a5fbdc0 7331 if (!use_eager_fpu()) {
653f52c3
RR		 7332 if (++vcpu->fpu_counter < 5)
7333 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7334 }
0c04851c 7335 trace_kvm_fpu(0);
d0752060 7336}
e9b11c17
ZX		 7337
7338void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7339{
12f9a48f 7340 kvmclock_reset(vcpu);
7f1ea208 7341
f5f48ee1 7342 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7343 kvm_x86_ops->vcpu_free(vcpu);
7344}
7345
7346struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7347 unsigned int id)
7348{
c447e76b
LL		 7349 struct kvm_vcpu *vcpu;
7350
6755bae8
ZA		 7351 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7352 printk_once(KERN_WARNING
7353 "kvm: SMP vm created on host with unstable TSC; "
7354 "guest TSC will not be reliable\n");
c447e76b
LL		 7355
7356 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7357
c447e76b 7358 return vcpu;
26e5215f 7359}
e9b11c17 7360
26e5215f
AK		 7361int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7362{
7363 int r;
e9b11c17 7364
19efffa2 7365 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7366 r = vcpu_load(vcpu);
7367 if (r)
7368 return r;
d28bc9dd 7369 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7370 kvm_mmu_setup(vcpu);
e9b11c17 7371 vcpu_put(vcpu);
26e5215f 7372 return r;
e9b11c17
ZX		 7373}
7374
31928aa5 7375void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7376{
8fe8ab46 7377 struct msr_data msr;
332967a3 7378 struct kvm *kvm = vcpu->kvm;
42897d86 7379
31928aa5
DD		 7380 if (vcpu_load(vcpu))
7381 return;
8fe8ab46
WA		 7382 msr.data = 0x0;
7383 msr.index = MSR_IA32_TSC;
7384 msr.host_initiated = true;
7385 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7386 vcpu_put(vcpu);
7387
630994b3
MT		 7388 if (!kvmclock_periodic_sync)
7389 return;
7390
332967a3
AJ		 7391 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7392 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7393}
7394
d40ccc62 7395void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7396{
9fc77441 7397 int r;
344d9588
GN		 7398 vcpu->arch.apf.msr_val = 0;
7399
9fc77441
MT		 7400 r = vcpu_load(vcpu);
7401 BUG_ON(r);
e9b11c17
ZX		 7402 kvm_mmu_unload(vcpu);
7403 vcpu_put(vcpu);
7404
7405 kvm_x86_ops->vcpu_free(vcpu);
7406}
7407
d28bc9dd 7408void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7409{
e69fab5d
PB		 7410 vcpu->arch.hflags = 0;
7411
7460fb4a
AK		 7412 atomic_set(&vcpu->arch.nmi_queued, 0);
7413 vcpu->arch.nmi_pending = 0;
448fa4a9 7414 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7415 kvm_clear_interrupt_queue(vcpu);
7416 kvm_clear_exception_queue(vcpu);
448fa4a9 7417
42dbaa5a 7418 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7419 kvm_update_dr0123(vcpu);
6f43ed01 7420 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7421 kvm_update_dr6(vcpu);
42dbaa5a 7422 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7423 kvm_update_dr7(vcpu);
42dbaa5a 7424
1119022c
NA		 7425 vcpu->arch.cr2 = 0;
7426
3842d135 7427 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7428 vcpu->arch.apf.msr_val = 0;
c9aaa895 7429 vcpu->arch.st.msr_val = 0;
3842d135 7430
12f9a48f
GC		 7431 kvmclock_reset(vcpu);
7432
af585b92
GN		 7433 kvm_clear_async_pf_completion_queue(vcpu);
7434 kvm_async_pf_hash_reset(vcpu);
7435 vcpu->arch.apf.halted = false;
3842d135 7436
64d60670 7437 if (!init_event) {
d28bc9dd 7438 kvm_pmu_reset(vcpu);
64d60670
PB		 7439 vcpu->arch.smbase = 0x30000;
7440 }
f5132b01 7441
66f7b72e
JS		 7442 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7443 vcpu->arch.regs_avail = ~0;
7444 vcpu->arch.regs_dirty = ~0;
7445
d28bc9dd 7446 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7447}
7448
2b4a273b 7449void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7450{
7451 struct kvm_segment cs;
7452
7453 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7454 cs.selector = vector << 8;
7455 cs.base = vector << 12;
7456 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7457 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7458}
7459
13a34e06 7460int kvm_arch_hardware_enable(void)
e9b11c17 7461{
ca84d1a2
ZA		 7462 struct kvm *kvm;
7463 struct kvm_vcpu *vcpu;
7464 int i;
0dd6a6ed
ZA		 7465 int ret;
7466 u64 local_tsc;
7467 u64 max_tsc = 0;
7468 bool stable, backwards_tsc = false;
18863bdd
AK		 7469
7470 kvm_shared_msr_cpu_online();
13a34e06 7471 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7472 if (ret != 0)
7473 return ret;
7474
4ea1636b 7475 local_tsc = rdtsc();
0dd6a6ed
ZA		 7476 stable = !check_tsc_unstable();
7477 list_for_each_entry(kvm, &vm_list, vm_list) {
7478 kvm_for_each_vcpu(i, vcpu, kvm) {
7479 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7480 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7481 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7482 backwards_tsc = true;
7483 if (vcpu->arch.last_host_tsc > max_tsc)
7484 max_tsc = vcpu->arch.last_host_tsc;
7485 }
7486 }
7487 }
7488
7489 /*
7490 * Sometimes, even reliable TSCs go backwards. This happens on
7491 * platforms that reset TSC during suspend or hibernate actions, but
7492 * maintain synchronization. We must compensate. Fortunately, we can
7493 * detect that condition here, which happens early in CPU bringup,
7494 * before any KVM threads can be running. Unfortunately, we can't
7495 * bring the TSCs fully up to date with real time, as we aren't yet far
7496 * enough into CPU bringup that we know how much real time has actually
7497 * elapsed; our helper function, get_kernel_ns() will be using boot
7498 * variables that haven't been updated yet.
7499 *
7500 * So we simply find the maximum observed TSC above, then record the
7501 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7502 * the adjustment will be applied. Note that we accumulate
7503 * adjustments, in case multiple suspend cycles happen before some VCPU
7504 * gets a chance to run again. In the event that no KVM threads get a
7505 * chance to run, we will miss the entire elapsed period, as we'll have
7506 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7507 * loose cycle time. This isn't too big a deal, since the loss will be
7508 * uniform across all VCPUs (not to mention the scenario is extremely
7509 * unlikely). It is possible that a second hibernate recovery happens
7510 * much faster than a first, causing the observed TSC here to be
7511 * smaller; this would require additional padding adjustment, which is
7512 * why we set last_host_tsc to the local tsc observed here.
7513 *
7514 * N.B. - this code below runs only on platforms with reliable TSC,
7515 * as that is the only way backwards_tsc is set above. Also note
7516 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7517 * have the same delta_cyc adjustment applied if backwards_tsc
7518 * is detected. Note further, this adjustment is only done once,
7519 * as we reset last_host_tsc on all VCPUs to stop this from being
7520 * called multiple times (one for each physical CPU bringup).
7521 *
4a969980 7522 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7523 * will be compensated by the logic in vcpu_load, which sets the TSC to
7524 * catchup mode. This will catchup all VCPUs to real time, but cannot
7525 * guarantee that they stay in perfect synchronization.
7526 */
7527 if (backwards_tsc) {
7528 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7529 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7530 list_for_each_entry(kvm, &vm_list, vm_list) {
7531 kvm_for_each_vcpu(i, vcpu, kvm) {
7532 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7533 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7534 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7535 }
7536
7537 /*
7538 * We have to disable TSC offset matching.. if you were
7539 * booting a VM while issuing an S4 host suspend....
7540 * you may have some problem. Solving this issue is
7541 * left as an exercise to the reader.
7542 */
7543 kvm->arch.last_tsc_nsec = 0;
7544 kvm->arch.last_tsc_write = 0;
7545 }
7546
7547 }
7548 return 0;
e9b11c17
ZX		 7549}
7550
13a34e06 7551void kvm_arch_hardware_disable(void)
e9b11c17 7552{
13a34e06
RK		 7553 kvm_x86_ops->hardware_disable();
7554 drop_user_return_notifiers();
e9b11c17
ZX		 7555}
7556
7557int kvm_arch_hardware_setup(void)
7558{
9e9c3fe4
NA		 7559 int r;
7560
7561 r = kvm_x86_ops->hardware_setup();
7562 if (r != 0)
7563 return r;
7564
35181e86
HZ		 7565 if (kvm_has_tsc_control) {
7566 /*
7567 * Make sure the user can only configure tsc_khz values that
7568 * fit into a signed integer.
7569 * A min value is not calculated needed because it will always
7570 * be 1 on all machines.
7571 */
7572 u64 max = min(0x7fffffffULL,
7573 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7574 kvm_max_guest_tsc_khz = max;
7575
ad721883 7576 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7577 }
ad721883 7578
9e9c3fe4
NA		 7579 kvm_init_msr_list();
7580 return 0;
e9b11c17
ZX		 7581}
7582
7583void kvm_arch_hardware_unsetup(void)
7584{
7585 kvm_x86_ops->hardware_unsetup();
7586}
7587
7588void kvm_arch_check_processor_compat(void *rtn)
7589{
7590 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7591}
7592
7593bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7594{
7595 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7596}
7597EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7598
7599bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7600{
7601 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7602}
7603
3e515705
AK		 7604bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7605{
35754c98 7606 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7607}
7608
54e9818f 7609struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7610EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7611
e9b11c17
ZX		 7612int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7613{
7614 struct page *page;
7615 struct kvm *kvm;
7616 int r;
7617
7618 BUG_ON(vcpu->kvm == NULL);
7619 kvm = vcpu->kvm;
7620
d62caabb 7621 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7622 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7623 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7624 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7626 else
a4535290 7627 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7628
7629 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7630 if (!page) {
7631 r = -ENOMEM;
7632 goto fail;
7633 }
ad312c7c 7634 vcpu->arch.pio_data = page_address(page);
e9b11c17 7635
cc578287 7636 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7637
e9b11c17
ZX		 7638 r = kvm_mmu_create(vcpu);
7639 if (r < 0)
7640 goto fail_free_pio_data;
7641
7642 if (irqchip_in_kernel(kvm)) {
7643 r = kvm_create_lapic(vcpu);
7644 if (r < 0)
7645 goto fail_mmu_destroy;
54e9818f
GN		 7646 } else
7647 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7648
890ca9ae
HY		 7649 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7650 GFP_KERNEL);
7651 if (!vcpu->arch.mce_banks) {
7652 r = -ENOMEM;
443c39bc 7653 goto fail_free_lapic;
890ca9ae
HY		 7654 }
7655 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7656
f1797359
WY		 7657 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7658 r = -ENOMEM;
f5f48ee1 7659 goto fail_free_mce_banks;
f1797359 7660 }
f5f48ee1 7661
0ee6a517 7662 fx_init(vcpu);
66f7b72e 7663
ba904635 7664 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7665 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7666
7667 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7668 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7669
5a4f55cd
EK		 7670 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7671
74545705
RK		 7672 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7673
af585b92 7674 kvm_async_pf_hash_reset(vcpu);
f5132b01 7675 kvm_pmu_init(vcpu);
af585b92 7676
1c1a9ce9
SR		 7677 vcpu->arch.pending_external_vector = -1;
7678
5c919412
AS		 7679 kvm_hv_vcpu_init(vcpu);
7680
e9b11c17 7681 return 0;
0ee6a517 7682
f5f48ee1
SY		 7683fail_free_mce_banks:
7684 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7685fail_free_lapic:
7686 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7687fail_mmu_destroy:
7688 kvm_mmu_destroy(vcpu);
7689fail_free_pio_data:
ad312c7c 7690 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7691fail:
7692 return r;
7693}
7694
7695void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7696{
f656ce01
MT		 7697 int idx;
7698
1f4b34f8 7699 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7700 kvm_pmu_destroy(vcpu);
36cb93fd 7701 kfree(vcpu->arch.mce_banks);
e9b11c17 7702 kvm_free_lapic(vcpu);
f656ce01 7703 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7704 kvm_mmu_destroy(vcpu);
f656ce01 7705 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7706 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7707 if (!lapic_in_kernel(vcpu))
54e9818f 7708 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7709}
d19a9cd2 7710
e790d9ef
RK		 7711void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7712{
ae97a3b8 7713 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7714}
7715
e08b9637 7716int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7717{
e08b9637
CO		 7718 if (type)
7719 return -EINVAL;
7720
6ef768fa 7721 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7722 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7723 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7724 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7725 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7726
5550af4d
SY		 7727 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7728 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7729 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7730 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7731 &kvm->arch.irq_sources_bitmap);
5550af4d 7732
038f8c11 7733 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7734 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7735 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7736
7737 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7738
7e44e449 7739 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7740 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7741
0eb05bf2 7742 kvm_page_track_init(kvm);
13d268ca 7743 kvm_mmu_init_vm(kvm);
0eb05bf2 7744
d89f5eff 7745 return 0;
d19a9cd2
ZX		 7746}
7747
7748static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7749{
9fc77441
MT		 7750 int r;
7751 r = vcpu_load(vcpu);
7752 BUG_ON(r);
d19a9cd2
ZX		 7753 kvm_mmu_unload(vcpu);
7754 vcpu_put(vcpu);
7755}
7756
7757static void kvm_free_vcpus(struct kvm *kvm)
7758{
7759 unsigned int i;
988a2cae 7760 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7761
7762 /*
7763 * Unpin any mmu pages first.
7764 */
af585b92
GN		 7765 kvm_for_each_vcpu(i, vcpu, kvm) {
7766 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7767 kvm_unload_vcpu_mmu(vcpu);
af585b92 7768 }
988a2cae
GN		 7769 kvm_for_each_vcpu(i, vcpu, kvm)
7770 kvm_arch_vcpu_free(vcpu);
7771
7772 mutex_lock(&kvm->lock);
7773 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7774 kvm->vcpus[i] = NULL;
d19a9cd2 7775
988a2cae
GN		 7776 atomic_set(&kvm->online_vcpus, 0);
7777 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7778}
7779
ad8ba2cd
SY		 7780void kvm_arch_sync_events(struct kvm *kvm)
7781{
332967a3 7782 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7783 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7784 kvm_free_all_assigned_devices(kvm);
aea924f6 7785 kvm_free_pit(kvm);
ad8ba2cd
SY		 7786}
7787
1d8007bd 7788int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7789{
7790 int i, r;
25188b99 7791 unsigned long hva;
f0d648bd
PB		 7792 struct kvm_memslots *slots = kvm_memslots(kvm);
7793 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7794
7795 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7796 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7797 return -EINVAL;
9da0e4d5 7798
f0d648bd
PB		 7799 slot = id_to_memslot(slots, id);
7800 if (size) {
7801 if (WARN_ON(slot->npages))
7802 return -EEXIST;
7803
7804 /*
7805 * MAP_SHARED to prevent internal slot pages from being moved
7806 * by fork()/COW.
7807 */
7808 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7809 MAP_SHARED | MAP_ANONYMOUS, 0);
7810 if (IS_ERR((void *)hva))
7811 return PTR_ERR((void *)hva);
7812 } else {
7813 if (!slot->npages)
7814 return 0;
7815
7816 hva = 0;
7817 }
7818
7819 old = *slot;
9da0e4d5 7820 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7821 struct kvm_userspace_memory_region m;
9da0e4d5 7822
1d8007bd
PB		 7823 m.slot = id | (i << 16);
7824 m.flags = 0;
7825 m.guest_phys_addr = gpa;
f0d648bd 7826 m.userspace_addr = hva;
1d8007bd 7827 m.memory_size = size;
9da0e4d5
PB		 7828 r = __kvm_set_memory_region(kvm, &m);
7829 if (r < 0)
7830 return r;
7831 }
7832
f0d648bd
PB		 7833 if (!size) {
7834 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7835 WARN_ON(r < 0);
7836 }
7837
9da0e4d5
PB		 7838 return 0;
7839}
7840EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7841
1d8007bd 7842int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7843{
7844 int r;
7845
7846 mutex_lock(&kvm->slots_lock);
1d8007bd 7847 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7848 mutex_unlock(&kvm->slots_lock);
7849
7850 return r;
7851}
7852EXPORT_SYMBOL_GPL(x86_set_memory_region);
7853
d19a9cd2
ZX		 7854void kvm_arch_destroy_vm(struct kvm *kvm)
7855{
27469d29
AH		 7856 if (current->mm == kvm->mm) {
7857 /*
7858 * Free memory regions allocated on behalf of userspace,
7859 * unless the the memory map has changed due to process exit
7860 * or fd copying.
7861 */
1d8007bd
PB		 7862 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7863 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7864 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7865 }
6eb55818 7866 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7867 kfree(kvm->arch.vpic);
7868 kfree(kvm->arch.vioapic);
d19a9cd2 7869 kvm_free_vcpus(kvm);
1e08ec4a 7870 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7871 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7872}
0de10343 7873
5587027c 7874void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7875 struct kvm_memory_slot *dont)
7876{
7877 int i;
7878
d89cc617
TY		 7879 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7880 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7881 kvfree(free->arch.rmap[i]);
d89cc617 7882 free->arch.rmap[i] = NULL;
77d11309 7883 }
d89cc617
TY		 7884 if (i == 0)
7885 continue;
7886
7887 if (!dont || free->arch.lpage_info[i - 1] !=
7888 dont->arch.lpage_info[i - 1]) {
548ef284 7889 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7890 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7891 }
7892 }
21ebbeda
XG		 7893
7894 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7895}
7896
5587027c
AK		 7897int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7898 unsigned long npages)
db3fe4eb
TY		 7899{
7900 int i;
7901
d89cc617 7902 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7903 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7904 unsigned long ugfn;
7905 int lpages;
d89cc617 7906 int level = i + 1;
db3fe4eb
TY		 7907
7908 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7909 slot->base_gfn, level) + 1;
7910
d89cc617
TY		 7911 slot->arch.rmap[i] =
7912 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7913 if (!slot->arch.rmap[i])
77d11309 7914 goto out_free;
d89cc617
TY		 7915 if (i == 0)
7916 continue;
77d11309 7917
92f94f1e
XG		 7918 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7919 if (!linfo)
db3fe4eb
TY		 7920 goto out_free;
7921
92f94f1e
XG		 7922 slot->arch.lpage_info[i - 1] = linfo;
7923
db3fe4eb 7924 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7925 linfo[0].disallow_lpage = 1;
db3fe4eb 7926 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7927 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7928 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7929 /*
7930 * If the gfn and userspace address are not aligned wrt each
7931 * other, or if explicitly asked to, disable large page
7932 * support for this slot
7933 */
7934 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7935 !kvm_largepages_enabled()) {
7936 unsigned long j;
7937
7938 for (j = 0; j < lpages; ++j)
92f94f1e 7939 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7940 }
7941 }
7942
21ebbeda
XG		 7943 if (kvm_page_track_create_memslot(slot, npages))
7944 goto out_free;
7945
db3fe4eb
TY		 7946 return 0;
7947
7948out_free:
d89cc617 7949 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7950 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7951 slot->arch.rmap[i] = NULL;
7952 if (i == 0)
7953 continue;
7954
548ef284 7955 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7956 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7957 }
7958 return -ENOMEM;
7959}
7960
15f46015 7961void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7962{
e6dff7d1
TY		 7963 /*
7964 * memslots->generation has been incremented.
7965 * mmio generation may have reached its maximum value.
7966 */
54bf36aa 7967 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7968}
7969
f7784b8e
MT		 7970int kvm_arch_prepare_memory_region(struct kvm *kvm,
7971 struct kvm_memory_slot *memslot,
09170a49 7972 const struct kvm_userspace_memory_region *mem,
7b6195a9 7973 enum kvm_mr_change change)
0de10343 7974{
f7784b8e
MT		 7975 return 0;
7976}
7977
88178fd4
KH		 7978static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7979 struct kvm_memory_slot *new)
7980{
7981 /* Still write protect RO slot */
7982 if (new->flags & KVM_MEM_READONLY) {
7983 kvm_mmu_slot_remove_write_access(kvm, new);
7984 return;
7985 }
7986
7987 /*
7988 * Call kvm_x86_ops dirty logging hooks when they are valid.
7989 *
7990 * kvm_x86_ops->slot_disable_log_dirty is called when:
7991 *
7992 * - KVM_MR_CREATE with dirty logging is disabled
7993 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7994 *
7995 * The reason is, in case of PML, we need to set D-bit for any slots
7996 * with dirty logging disabled in order to eliminate unnecessary GPA
7997 * logging in PML buffer (and potential PML buffer full VMEXT). This
7998 * guarantees leaving PML enabled during guest's lifetime won't have
7999 * any additonal overhead from PML when guest is running with dirty
8000 * logging disabled for memory slots.
8001 *
8002 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8003 * to dirty logging mode.
8004 *
8005 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8006 *
8007 * In case of write protect:
8008 *
8009 * Write protect all pages for dirty logging.
8010 *
8011 * All the sptes including the large sptes which point to this
8012 * slot are set to readonly. We can not create any new large
8013 * spte on this slot until the end of the logging.
8014 *
8015 * See the comments in fast_page_fault().
8016 */
8017 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8018 if (kvm_x86_ops->slot_enable_log_dirty)
8019 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8020 else
8021 kvm_mmu_slot_remove_write_access(kvm, new);
8022 } else {
8023 if (kvm_x86_ops->slot_disable_log_dirty)
8024 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8025 }
8026}
8027
f7784b8e 8028void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8029 const struct kvm_userspace_memory_region *mem,
8482644a 8030 const struct kvm_memory_slot *old,
f36f3f28 8031 const struct kvm_memory_slot *new,
8482644a 8032 enum kvm_mr_change change)
f7784b8e 8033{
8482644a 8034 int nr_mmu_pages = 0;
f7784b8e 8035
48c0e4e9
XG		 8036 if (!kvm->arch.n_requested_mmu_pages)
8037 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8038
48c0e4e9 8039 if (nr_mmu_pages)
0de10343 8040 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8041
3ea3b7fa
WL		 8042 /*
8043 * Dirty logging tracks sptes in 4k granularity, meaning that large
8044 * sptes have to be split. If live migration is successful, the guest
8045 * in the source machine will be destroyed and large sptes will be
8046 * created in the destination. However, if the guest continues to run
8047 * in the source machine (for example if live migration fails), small
8048 * sptes will remain around and cause bad performance.
8049 *
8050 * Scan sptes if dirty logging has been stopped, dropping those
8051 * which can be collapsed into a single large-page spte. Later
8052 * page faults will create the large-page sptes.
8053 */
8054 if ((change != KVM_MR_DELETE) &&
8055 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8056 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8057 kvm_mmu_zap_collapsible_sptes(kvm, new);
8058
c972f3b1 8059 /*
88178fd4 8060 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8061 *
88178fd4
KH		 8062 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8063 * been zapped so no dirty logging staff is needed for old slot. For
8064 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8065 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8066 *
8067 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8068 */
88178fd4 8069 if (change != KVM_MR_DELETE)
f36f3f28 8070 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8071}
1d737c8a 8072
2df72e9b 8073void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8074{
6ca18b69 8075 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8076}
8077
2df72e9b
MT		 8078void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8079 struct kvm_memory_slot *slot)
8080{
6ca18b69 8081 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8082}
8083
5d9bc648
PB		 8084static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8085{
8086 if (!list_empty_careful(&vcpu->async_pf.done))
8087 return true;
8088
8089 if (kvm_apic_has_events(vcpu))
8090 return true;
8091
8092 if (vcpu->arch.pv.pv_unhalted)
8093 return true;
8094
8095 if (atomic_read(&vcpu->arch.nmi_queued))
8096 return true;
8097
73917739
PB		 8098 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8099 return true;
8100
5d9bc648
PB		 8101 if (kvm_arch_interrupt_allowed(vcpu) &&
8102 kvm_cpu_has_interrupt(vcpu))
8103 return true;
8104
1f4b34f8
AS		 8105 if (kvm_hv_has_stimer_pending(vcpu))
8106 return true;
8107
5d9bc648
PB		 8108 return false;
8109}
8110
1d737c8a
ZX		 8111int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8112{
b6b8a145
JK		 8113 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8114 kvm_x86_ops->check_nested_events(vcpu, false);
8115
5d9bc648 8116 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8117}
5736199a 8118
b6d33834 8119int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8120{
b6d33834 8121 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8122}
78646121
GN		 8123
8124int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8125{
8126 return kvm_x86_ops->interrupt_allowed(vcpu);
8127}
229456fc 8128
82b32774 8129unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8130{
82b32774
NA		 8131 if (is_64_bit_mode(vcpu))
8132 return kvm_rip_read(vcpu);
8133 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8134 kvm_rip_read(vcpu));
8135}
8136EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8137
82b32774
NA		 8138bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8139{
8140 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8141}
8142EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8143
94fe45da
JK		 8144unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8145{
8146 unsigned long rflags;
8147
8148 rflags = kvm_x86_ops->get_rflags(vcpu);
8149 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8150 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8151 return rflags;
8152}
8153EXPORT_SYMBOL_GPL(kvm_get_rflags);
8154
6addfc42 8155static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8156{
8157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8158 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8159 rflags |= X86_EFLAGS_TF;
94fe45da 8160 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8161}
8162
8163void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8164{
8165 __kvm_set_rflags(vcpu, rflags);
3842d135 8166 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8167}
8168EXPORT_SYMBOL_GPL(kvm_set_rflags);
8169
56028d08
GN		 8170void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8171{
8172 int r;
8173
fb67e14f 8174 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8175 work->wakeup_all)
56028d08
GN		 8176 return;
8177
8178 r = kvm_mmu_reload(vcpu);
8179 if (unlikely(r))
8180 return;
8181
fb67e14f
XG		 8182 if (!vcpu->arch.mmu.direct_map &&
8183 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8184 return;
8185
56028d08
GN		 8186 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8187}
8188
af585b92
GN		 8189static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8190{
8191 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8192}
8193
8194static inline u32 kvm_async_pf_next_probe(u32 key)
8195{
8196 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8197}
8198
8199static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8200{
8201 u32 key = kvm_async_pf_hash_fn(gfn);
8202
8203 while (vcpu->arch.apf.gfns[key] != ~0)
8204 key = kvm_async_pf_next_probe(key);
8205
8206 vcpu->arch.apf.gfns[key] = gfn;
8207}
8208
8209static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8210{
8211 int i;
8212 u32 key = kvm_async_pf_hash_fn(gfn);
8213
8214 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8215 (vcpu->arch.apf.gfns[key] != gfn &&
8216 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8217 key = kvm_async_pf_next_probe(key);
8218
8219 return key;
8220}
8221
8222bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8223{
8224 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8225}
8226
8227static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8228{
8229 u32 i, j, k;
8230
8231 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8232 while (true) {
8233 vcpu->arch.apf.gfns[i] = ~0;
8234 do {
8235 j = kvm_async_pf_next_probe(j);
8236 if (vcpu->arch.apf.gfns[j] == ~0)
8237 return;
8238 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8239 /*
8240 * k lies cyclically in ]i,j]
8241 * | i.k.j |
8242 * |....j i.k.| or |.k..j i...|
8243 */
8244 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8245 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8246 i = j;
8247 }
8248}
8249
7c90705b
GN		 8250static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8251{
8252
8253 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8254 sizeof(val));
8255}
8256
af585b92
GN		 8257void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8258 struct kvm_async_pf *work)
8259{
6389ee94
AK		 8260 struct x86_exception fault;
8261
7c90705b 8262 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8263 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8264
8265 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8266 (vcpu->arch.apf.send_user_only &&
8267 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8268 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8269 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8270 fault.vector = PF_VECTOR;
8271 fault.error_code_valid = true;
8272 fault.error_code = 0;
8273 fault.nested_page_fault = false;
8274 fault.address = work->arch.token;
8275 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8276 }
af585b92
GN		 8277}
8278
8279void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8280 struct kvm_async_pf *work)
8281{
6389ee94
AK		 8282 struct x86_exception fault;
8283
7c90705b 8284 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8285 if (work->wakeup_all)
7c90705b
GN		 8286 work->arch.token = ~0; /* broadcast wakeup */
8287 else
8288 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8289
8290 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8291 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8292 fault.vector = PF_VECTOR;
8293 fault.error_code_valid = true;
8294 fault.error_code = 0;
8295 fault.nested_page_fault = false;
8296 fault.address = work->arch.token;
8297 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8298 }
e6d53e3b 8299 vcpu->arch.apf.halted = false;
a4fa1635 8300 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8301}
8302
8303bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8304{
8305 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8306 return true;
8307 else
8308 return !kvm_event_needs_reinjection(vcpu) &&
8309 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8310}
8311
5544eb9b
PB		 8312void kvm_arch_start_assignment(struct kvm *kvm)
8313{
8314 atomic_inc(&kvm->arch.assigned_device_count);
8315}
8316EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8317
8318void kvm_arch_end_assignment(struct kvm *kvm)
8319{
8320 atomic_dec(&kvm->arch.assigned_device_count);
8321}
8322EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8323
8324bool kvm_arch_has_assigned_device(struct kvm *kvm)
8325{
8326 return atomic_read(&kvm->arch.assigned_device_count);
8327}
8328EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8329
e0f0bbc5
AW		 8330void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8331{
8332 atomic_inc(&kvm->arch.noncoherent_dma_count);
8333}
8334EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8335
8336void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8337{
8338 atomic_dec(&kvm->arch.noncoherent_dma_count);
8339}
8340EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8341
8342bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8343{
8344 return atomic_read(&kvm->arch.noncoherent_dma_count);
8345}
8346EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8347
87276880
FW		 8348int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8349 struct irq_bypass_producer *prod)
8350{
8351 struct kvm_kernel_irqfd *irqfd =
8352 container_of(cons, struct kvm_kernel_irqfd, consumer);
8353
8354 if (kvm_x86_ops->update_pi_irte) {
8355 irqfd->producer = prod;
8356 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8357 prod->irq, irqfd->gsi, 1);
8358 }
8359
8360 return -EINVAL;
8361}
8362
8363void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8364 struct irq_bypass_producer *prod)
8365{
8366 int ret;
8367 struct kvm_kernel_irqfd *irqfd =
8368 container_of(cons, struct kvm_kernel_irqfd, consumer);
8369
8370 if (!kvm_x86_ops->update_pi_irte) {
8371 WARN_ON(irqfd->producer != NULL);
8372 return;
8373 }
8374
8375 WARN_ON(irqfd->producer != prod);
8376 irqfd->producer = NULL;
8377
8378 /*
8379 * When producer of consumer is unregistered, we change back to
8380 * remapped mode, so we can re-use the current implementation
8381 * when the irq is masked/disabed or the consumer side (KVM
8382 * int this case doesn't want to receive the interrupts.
8383 */
8384 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8385 if (ret)
8386 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8387 " fails: %d\n", irqfd->consumer.token, ret);
8388}
8389
8390int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8391 uint32_t guest_irq, bool set)
8392{
8393 if (!kvm_x86_ops->update_pi_irte)
8394 return -EINVAL;
8395
8396 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8397}
8398
52004014
FW		 8399bool kvm_vector_hashing_enabled(void)
8400{
8401 return vector_hashing;
8402}
8403EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8404
229456fc 8405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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