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arch/x86: Use RCU_INIT_POINTER(x, NULL) in kvm/vmx.c
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
3548bab5
AK		 249static void drop_user_return_notifiers(void *ignore)
250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
6389ee94 411void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 417}
418
3419ffc8
SY		 419void kvm_inject_nmi(struct kvm_vcpu *vcpu)
420{
7460fb4a
AK		 421 atomic_inc(&vcpu->arch.nmi_queued);
422 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 423}
424EXPORT_SYMBOL_GPL(kvm_inject_nmi);
425
298101da
AK		 426void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
427{
ce7ddec4 428 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 429}
430EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
431
ce7ddec4
JR		 432void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
433{
434 kvm_multiple_exception(vcpu, nr, true, error_code, true);
435}
436EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
437
0a79b009
AK		 438/*
439 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
440 * a #GP and return false.
441 */
442bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 443{
0a79b009
AK		 444 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
445 return true;
446 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
447 return false;
298101da 448}
0a79b009 449EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 450
ec92fe44
JR		 451/*
452 * This function will be used to read from the physical memory of the currently
453 * running guest. The difference to kvm_read_guest_page is that this function
454 * can read from guest physical or from the guest's guest physical memory.
455 */
456int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
457 gfn_t ngfn, void *data, int offset, int len,
458 u32 access)
459{
460 gfn_t real_gfn;
461 gpa_t ngpa;
462
463 ngpa = gfn_to_gpa(ngfn);
464 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
465 if (real_gfn == UNMAPPED_GVA)
466 return -EFAULT;
467
468 real_gfn = gpa_to_gfn(real_gfn);
469
470 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
471}
472EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
473
3d06b8bf
JR		 474int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
475 void *data, int offset, int len, u32 access)
476{
477 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
478 data, offset, len, access);
479}
480
a03490ed
CO		 481/*
482 * Load the pae pdptrs. Return true is they are all valid.
483 */
ff03a073 484int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 485{
486 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
487 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
488 int i;
489 int ret;
ff03a073 490 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 491
ff03a073
JR		 492 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
493 offset * sizeof(u64), sizeof(pdpte),
494 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 495 if (ret < 0) {
496 ret = 0;
497 goto out;
498 }
499 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 500 if (is_present_gpte(pdpte[i]) &&
20c466b5 501 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 502 ret = 0;
503 goto out;
504 }
505 }
506 ret = 1;
507
ff03a073 508 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 509 __set_bit(VCPU_EXREG_PDPTR,
510 (unsigned long *)&vcpu->arch.regs_avail);
511 __set_bit(VCPU_EXREG_PDPTR,
512 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 513out:
a03490ed
CO		 514
515 return ret;
516}
cc4b6871 517EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 518
d835dfec
AK		 519static bool pdptrs_changed(struct kvm_vcpu *vcpu)
520{
ff03a073 521 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 522 bool changed = true;
3d06b8bf
JR		 523 int offset;
524 gfn_t gfn;
d835dfec
AK		 525 int r;
526
527 if (is_long_mode(vcpu) || !is_pae(vcpu))
528 return false;
529
6de4f3ad
AK		 530 if (!test_bit(VCPU_EXREG_PDPTR,
531 (unsigned long *)&vcpu->arch.regs_avail))
532 return true;
533
9f8fe504
AK		 534 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
535 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 536 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
537 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 538 if (r < 0)
539 goto out;
ff03a073 540 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 541out:
d835dfec
AK		 542
543 return changed;
544}
545
49a9b07e 546int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 547{
aad82703
SY		 548 unsigned long old_cr0 = kvm_read_cr0(vcpu);
549 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
550 X86_CR0_CD | X86_CR0_NW;
551
f9a48e6a
AK		 552 cr0 |= X86_CR0_ET;
553
ab344828 554#ifdef CONFIG_X86_64
0f12244f
GN		 555 if (cr0 & 0xffffffff00000000UL)
556 return 1;
ab344828
GN		 557#endif
558
559 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 560
0f12244f
GN		 561 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
562 return 1;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
565 return 1;
a03490ed
CO		 566
567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
568#ifdef CONFIG_X86_64
f6801dff 569 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 570 int cs_db, cs_l;
571
0f12244f
GN		 572 if (!is_pae(vcpu))
573 return 1;
a03490ed 574 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 575 if (cs_l)
576 return 1;
a03490ed
CO		 577 } else
578#endif
ff03a073 579 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 580 kvm_read_cr3(vcpu)))
0f12244f 581 return 1;
a03490ed
CO		 582 }
583
ad756a16
MJ		 584 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
585 return 1;
586
a03490ed 587 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 588
d170c419 589 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 590 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 591 kvm_async_pf_hash_reset(vcpu);
592 }
e5f3f027 593
aad82703
SY		 594 if ((cr0 ^ old_cr0) & update_bits)
595 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 596 return 0;
597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 599
2d3ad1f4 600void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 601{
49a9b07e 602 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 603}
2d3ad1f4 604EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 605
42bdf991
MT		 606static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
607{
608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
609 !vcpu->guest_xcr0_loaded) {
610 /* kvm_set_xcr() also depends on this */
611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
612 vcpu->guest_xcr0_loaded = 1;
613 }
614}
615
616static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
617{
618 if (vcpu->guest_xcr0_loaded) {
619 if (vcpu->arch.xcr0 != host_xcr0)
620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
621 vcpu->guest_xcr0_loaded = 0;
622 }
623}
624
2acf923e
DC		 625int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
626{
56c103ec
LJ		 627 u64 xcr0 = xcr;
628 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 629 u64 valid_bits;
2acf923e
DC		 630
631 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
632 if (index != XCR_XFEATURE_ENABLED_MASK)
633 return 1;
2acf923e
DC		 634 if (!(xcr0 & XSTATE_FP))
635 return 1;
636 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
637 return 1;
46c34cb0
PB		 638
639 /*
640 * Do not allow the guest to set bits that we do not support
641 * saving. However, xcr0 bit 0 is always set, even if the
642 * emulated CPU does not support XSAVE (see fx_init).
643 */
644 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
645 if (xcr0 & ~valid_bits)
2acf923e 646 return 1;
46c34cb0 647
390bd528
LJ		 648 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
649 return 1;
650
42bdf991 651 kvm_put_guest_xcr0(vcpu);
2acf923e 652 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 653
654 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
655 kvm_update_cpuid(vcpu);
2acf923e
DC		 656 return 0;
657}
658
659int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
660{
764bcbc5
Z		 661 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
662 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 663 kvm_inject_gp(vcpu, 0);
664 return 1;
665 }
666 return 0;
667}
668EXPORT_SYMBOL_GPL(kvm_set_xcr);
669
a83b29c6 670int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 671{
fc78f519 672 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 673 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
674 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 675 if (cr4 & CR4_RESERVED_BITS)
676 return 1;
a03490ed 677
2acf923e
DC		 678 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
679 return 1;
680
c68b734f
YW		 681 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
682 return 1;
683
97ec8c06
FW		 684 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
685 return 1;
686
afcbf13f 687 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 688 return 1;
689
a03490ed 690 if (is_long_mode(vcpu)) {
0f12244f
GN		 691 if (!(cr4 & X86_CR4_PAE))
692 return 1;
a2edf57f
AK		 693 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
694 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 695 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
696 kvm_read_cr3(vcpu)))
0f12244f
GN		 697 return 1;
698
ad756a16
MJ		 699 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
700 if (!guest_cpuid_has_pcid(vcpu))
701 return 1;
702
703 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
704 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
705 return 1;
706 }
707
5e1746d6 708 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 709 return 1;
a03490ed 710
ad756a16
MJ		 711 if (((cr4 ^ old_cr4) & pdptr_bits) ||
712 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 713 kvm_mmu_reset_context(vcpu);
0f12244f 714
97ec8c06
FW		 715 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
716 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
717
2acf923e 718 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 719 kvm_update_cpuid(vcpu);
2acf923e 720
0f12244f
GN		 721 return 0;
722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 724
2390218b 725int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 726{
9f8fe504 727 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 728 kvm_mmu_sync_roots(vcpu);
d835dfec 729 kvm_mmu_flush_tlb(vcpu);
0f12244f 730 return 0;
d835dfec
AK		 731 }
732
a03490ed 733 if (is_long_mode(vcpu)) {
d9f89b88
JK		 734 if (cr3 & CR3_L_MODE_RESERVED_BITS)
735 return 1;
736 } else if (is_pae(vcpu) && is_paging(vcpu) &&
737 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 738 return 1;
a03490ed 739
0f12244f 740 vcpu->arch.cr3 = cr3;
aff48baa 741 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 742 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 743 return 0;
744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 746
eea1cff9 747int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 748{
0f12244f
GN		 749 if (cr8 & CR8_RESERVED_BITS)
750 return 1;
a03490ed
CO		 751 if (irqchip_in_kernel(vcpu->kvm))
752 kvm_lapic_set_tpr(vcpu, cr8);
753 else
ad312c7c 754 vcpu->arch.cr8 = cr8;
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 758
2d3ad1f4 759unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 760{
761 if (irqchip_in_kernel(vcpu->kvm))
762 return kvm_lapic_get_cr8(vcpu);
763 else
ad312c7c 764 return vcpu->arch.cr8;
a03490ed 765}
2d3ad1f4 766EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 767
73aaf249
JK		 768static void kvm_update_dr6(struct kvm_vcpu *vcpu)
769{
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
772}
773
c8639010
JK		 774static void kvm_update_dr7(struct kvm_vcpu *vcpu)
775{
776 unsigned long dr7;
777
778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
779 dr7 = vcpu->arch.guest_debug_dr7;
780 else
781 dr7 = vcpu->arch.dr7;
782 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 783 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
784 if (dr7 & DR7_BP_EN_MASK)
785 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 786}
787
6f43ed01
NA		 788static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
789{
790 u64 fixed = DR6_FIXED_1;
791
792 if (!guest_cpuid_has_rtm(vcpu))
793 fixed |= DR6_RTM;
794 return fixed;
795}
796
338dbc97 797static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 798{
799 switch (dr) {
800 case 0 ... 3:
801 vcpu->arch.db[dr] = val;
802 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
803 vcpu->arch.eff_db[dr] = val;
804 break;
805 case 4:
338dbc97
GN		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
807 return 1; /* #UD */
020df079
GN		 808 /* fall through */
809 case 6:
338dbc97
GN		 810 if (val & 0xffffffff00000000ULL)
811 return -1; /* #GP */
6f43ed01 812 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 813 kvm_update_dr6(vcpu);
020df079
GN		 814 break;
815 case 5:
338dbc97
GN		 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
817 return 1; /* #UD */
020df079
GN		 818 /* fall through */
819 default: /* 7 */
338dbc97
GN		 820 if (val & 0xffffffff00000000ULL)
821 return -1; /* #GP */
020df079 822 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 823 kvm_update_dr7(vcpu);
020df079
GN		 824 break;
825 }
826
827 return 0;
828}
338dbc97
GN		 829
830int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
831{
832 int res;
833
834 res = __kvm_set_dr(vcpu, dr, val);
835 if (res > 0)
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 else if (res < 0)
838 kvm_inject_gp(vcpu, 0);
839
840 return res;
841}
020df079
GN		 842EXPORT_SYMBOL_GPL(kvm_set_dr);
843
338dbc97 844static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 *val = vcpu->arch.db[dr];
849 break;
850 case 4:
338dbc97 851 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 852 return 1;
020df079
GN		 853 /* fall through */
854 case 6:
73aaf249
JK		 855 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
856 *val = vcpu->arch.dr6;
857 else
858 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
338dbc97 861 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 862 return 1;
020df079
GN		 863 /* fall through */
864 default: /* 7 */
865 *val = vcpu->arch.dr7;
866 break;
867 }
868
869 return 0;
870}
338dbc97
GN		 871
872int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
873{
874 if (_kvm_get_dr(vcpu, dr, val)) {
875 kvm_queue_exception(vcpu, UD_VECTOR);
876 return 1;
877 }
878 return 0;
879}
020df079
GN		 880EXPORT_SYMBOL_GPL(kvm_get_dr);
881
022cd0e8
AK		 882bool kvm_rdpmc(struct kvm_vcpu *vcpu)
883{
884 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
885 u64 data;
886 int err;
887
888 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
889 if (err)
890 return err;
891 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
892 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
893 return err;
894}
895EXPORT_SYMBOL_GPL(kvm_rdpmc);
896
043405e1
CO		 897/*
898 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
899 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
900 *
901 * This list is modified at module load time to reflect the
e3267cbb
GC		 902 * capabilities of the host cpu. This capabilities test skips MSRs that are
903 * kvm-specific. Those are put in the beginning of the list.
043405e1 904 */
e3267cbb 905
e984097b 906#define KVM_SAVE_MSRS_BEGIN 12
043405e1 907static u32 msrs_to_save[] = {
e3267cbb 908 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 909 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 910 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 911 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 912 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 913 MSR_KVM_PV_EOI_EN,
043405e1 914 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 915 MSR_STAR,
043405e1
CO		 916#ifdef CONFIG_X86_64
917 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
918#endif
b3897a49 919 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 920 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 921};
922
923static unsigned num_msrs_to_save;
924
f1d24831 925static const u32 emulated_msrs[] = {
ba904635 926 MSR_IA32_TSC_ADJUST,
a3e06bbe 927 MSR_IA32_TSCDEADLINE,
043405e1 928 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 929 MSR_IA32_MCG_STATUS,
930 MSR_IA32_MCG_CTL,
043405e1
CO		 931};
932
384bb783 933bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 934{
b69e8cae 935 if (efer & efer_reserved_bits)
384bb783 936 return false;
15c4a640 937
1b2fd70c
AG		 938 if (efer & EFER_FFXSR) {
939 struct kvm_cpuid_entry2 *feat;
940
941 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 942 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 943 return false;
1b2fd70c
AG		 944 }
945
d8017474
AG		 946 if (efer & EFER_SVME) {
947 struct kvm_cpuid_entry2 *feat;
948
949 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 950 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 951 return false;
d8017474
AG		 952 }
953
384bb783
JK		 954 return true;
955}
956EXPORT_SYMBOL_GPL(kvm_valid_efer);
957
958static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
959{
960 u64 old_efer = vcpu->arch.efer;
961
962 if (!kvm_valid_efer(vcpu, efer))
963 return 1;
964
965 if (is_paging(vcpu)
966 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
967 return 1;
968
15c4a640 969 efer &= ~EFER_LMA;
f6801dff 970 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 971
a3d204e2
SY		 972 kvm_x86_ops->set_efer(vcpu, efer);
973
aad82703
SY		 974 /* Update reserved bits */
975 if ((efer ^ old_efer) & EFER_NX)
976 kvm_mmu_reset_context(vcpu);
977
b69e8cae 978 return 0;
15c4a640
CO		 979}
980
f2b4b7dd
JR		 981void kvm_enable_efer_bits(u64 mask)
982{
983 efer_reserved_bits &= ~mask;
984}
985EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
986
987
15c4a640
CO		 988/*
989 * Writes msr value into into the appropriate "register".
990 * Returns 0 on success, non-0 otherwise.
991 * Assumes vcpu_load() was already called.
992 */
8fe8ab46 993int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 994{
8fe8ab46 995 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 996}
997
313a3dc7
CO		 998/*
999 * Adapt set_msr() to msr_io()'s calling convention
1000 */
1001static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1002{
8fe8ab46
WA		 1003 struct msr_data msr;
1004
1005 msr.data = *data;
1006 msr.index = index;
1007 msr.host_initiated = true;
1008 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1009}
1010
16e8d74d
MT		 1011#ifdef CONFIG_X86_64
1012struct pvclock_gtod_data {
1013 seqcount_t seq;
1014
1015 struct { /* extract of a clocksource struct */
1016 int vclock_mode;
1017 cycle_t cycle_last;
1018 cycle_t mask;
1019 u32 mult;
1020 u32 shift;
1021 } clock;
1022
cbcf2dd3
TG		 1023 u64 boot_ns;
1024 u64 nsec_base;
16e8d74d
MT		 1025};
1026
1027static struct pvclock_gtod_data pvclock_gtod_data;
1028
1029static void update_pvclock_gtod(struct timekeeper *tk)
1030{
1031 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1032 u64 boot_ns;
1033
d28ede83 1034 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1035
1036 write_seqcount_begin(&vdata->seq);
1037
1038 /* copy pvclock gtod data */
d28ede83
TG		 1039 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1040 vdata->clock.cycle_last = tk->tkr.cycle_last;
1041 vdata->clock.mask = tk->tkr.mask;
1042 vdata->clock.mult = tk->tkr.mult;
1043 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1044
cbcf2dd3 1045 vdata->boot_ns = boot_ns;
d28ede83 1046 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1047
1048 write_seqcount_end(&vdata->seq);
1049}
1050#endif
1051
1052
18068523
GOC		 1053static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1054{
9ed3c444
AK		 1055 int version;
1056 int r;
50d0a0f9 1057 struct pvclock_wall_clock wc;
923de3cf 1058 struct timespec boot;
18068523
GOC		 1059
1060 if (!wall_clock)
1061 return;
1062
9ed3c444
AK		 1063 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1064 if (r)
1065 return;
1066
1067 if (version & 1)
1068 ++version; /* first time write, random junk */
1069
1070 ++version;
18068523 1071
18068523
GOC		 1072 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1073
50d0a0f9
GH		 1074 /*
1075 * The guest calculates current wall clock time by adding
34c238a1 1076 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1077 * wall clock specified here. guest system time equals host
1078 * system time for us, thus we must fill in host boot time here.
1079 */
923de3cf 1080 getboottime(&boot);
50d0a0f9 1081
4b648665
BR		 1082 if (kvm->arch.kvmclock_offset) {
1083 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1084 boot = timespec_sub(boot, ts);
1085 }
50d0a0f9
GH		 1086 wc.sec = boot.tv_sec;
1087 wc.nsec = boot.tv_nsec;
1088 wc.version = version;
18068523
GOC		 1089
1090 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1091
1092 version++;
1093 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1094}
1095
50d0a0f9
GH		 1096static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1097{
1098 uint32_t quotient, remainder;
1099
1100 /* Don't try to replace with do_div(), this one calculates
1101 * "(dividend << 32) / divisor" */
1102 __asm__ ( "divl %4"
1103 : "=a" (quotient), "=d" (remainder)
1104 : "0" (0), "1" (dividend), "r" (divisor) );
1105 return quotient;
1106}
1107
5f4e3f88
ZA		 1108static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1109 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1110{
5f4e3f88 1111 uint64_t scaled64;
50d0a0f9
GH		 1112 int32_t shift = 0;
1113 uint64_t tps64;
1114 uint32_t tps32;
1115
5f4e3f88
ZA		 1116 tps64 = base_khz * 1000LL;
1117 scaled64 = scaled_khz * 1000LL;
50933623 1118 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1119 tps64 >>= 1;
1120 shift--;
1121 }
1122
1123 tps32 = (uint32_t)tps64;
50933623
JK		 1124 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1125 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1126 scaled64 >>= 1;
1127 else
1128 tps32 <<= 1;
50d0a0f9
GH		 1129 shift++;
1130 }
1131
5f4e3f88
ZA		 1132 *pshift = shift;
1133 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1134
5f4e3f88
ZA		 1135 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1136 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1137}
1138
759379dd
ZA		 1139static inline u64 get_kernel_ns(void)
1140{
bb0b5812 1141 return ktime_get_boot_ns();
50d0a0f9
GH		 1142}
1143
d828199e 1144#ifdef CONFIG_X86_64
16e8d74d 1145static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1146#endif
16e8d74d 1147
c8076604 1148static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1149unsigned long max_tsc_khz;
c8076604 1150
cc578287 1151static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1152{
cc578287
ZA		 1153 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1154 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1155}
1156
cc578287 1157static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1158{
cc578287
ZA		 1159 u64 v = (u64)khz * (1000000 + ppm);
1160 do_div(v, 1000000);
1161 return v;
1e993611
JR		 1162}
1163
cc578287 1164static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1165{
cc578287
ZA		 1166 u32 thresh_lo, thresh_hi;
1167 int use_scaling = 0;
217fc9cf 1168
03ba32ca
MT		 1169 /* tsc_khz can be zero if TSC calibration fails */
1170 if (this_tsc_khz == 0)
1171 return;
1172
c285545f
ZA		 1173 /* Compute a scale to convert nanoseconds in TSC cycles */
1174 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1175 &vcpu->arch.virtual_tsc_shift,
1176 &vcpu->arch.virtual_tsc_mult);
1177 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1178
1179 /*
1180 * Compute the variation in TSC rate which is acceptable
1181 * within the range of tolerance and decide if the
1182 * rate being applied is within that bounds of the hardware
1183 * rate. If so, no scaling or compensation need be done.
1184 */
1185 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1186 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1187 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1188 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1189 use_scaling = 1;
1190 }
1191 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1192}
1193
1194static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1195{
e26101b1 1196 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1197 vcpu->arch.virtual_tsc_mult,
1198 vcpu->arch.virtual_tsc_shift);
e26101b1 1199 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1200 return tsc;
1201}
1202
b48aa97e
MT		 1203void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1204{
1205#ifdef CONFIG_X86_64
1206 bool vcpus_matched;
1207 bool do_request = false;
1208 struct kvm_arch *ka = &vcpu->kvm->arch;
1209 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1210
1211 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1212 atomic_read(&vcpu->kvm->online_vcpus));
1213
1214 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1215 if (!ka->use_master_clock)
1216 do_request = 1;
1217
1218 if (!vcpus_matched && ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (do_request)
1222 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1223
1224 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1225 atomic_read(&vcpu->kvm->online_vcpus),
1226 ka->use_master_clock, gtod->clock.vclock_mode);
1227#endif
1228}
1229
ba904635
WA		 1230static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1231{
1232 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1233 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1234}
1235
8fe8ab46 1236void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1237{
1238 struct kvm *kvm = vcpu->kvm;
f38e098f 1239 u64 offset, ns, elapsed;
99e3e30a 1240 unsigned long flags;
02626b6a 1241 s64 usdiff;
b48aa97e 1242 bool matched;
0d3da0d2 1243 bool already_matched;
8fe8ab46 1244 u64 data = msr->data;
99e3e30a 1245
038f8c11 1246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1247 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1248 ns = get_kernel_ns();
f38e098f 1249 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1250
03ba32ca 1251 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1252 int faulted = 0;
1253
03ba32ca
MT		 1254 /* n.b - signed multiplication and division required */
1255 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1256#ifdef CONFIG_X86_64
03ba32ca 1257 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1258#else
03ba32ca 1259 /* do_div() only does unsigned */
8915aa27
MT		 1260 asm("1: idivl %[divisor]\n"
1261 "2: xor %%edx, %%edx\n"
1262 " movl $0, %[faulted]\n"
1263 "3:\n"
1264 ".section .fixup,\"ax\"\n"
1265 "4: movl $1, %[faulted]\n"
1266 " jmp 3b\n"
1267 ".previous\n"
1268
1269 _ASM_EXTABLE(1b, 4b)
1270
1271 : "=A"(usdiff), [faulted] "=r" (faulted)
1272 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1273
5d3cb0f6 1274#endif
03ba32ca
MT		 1275 do_div(elapsed, 1000);
1276 usdiff -= elapsed;
1277 if (usdiff < 0)
1278 usdiff = -usdiff;
8915aa27
MT		 1279
1280 /* idivl overflow => difference is larger than USEC_PER_SEC */
1281 if (faulted)
1282 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1283 } else
1284 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1285
1286 /*
5d3cb0f6
ZA		 1287 * Special case: TSC write with a small delta (1 second) of virtual
1288 * cycle time against real time is interpreted as an attempt to
1289 * synchronize the CPU.
1290 *
1291 * For a reliable TSC, we can match TSC offsets, and for an unstable
1292 * TSC, we add elapsed time in this computation. We could let the
1293 * compensation code attempt to catch up if we fall behind, but
1294 * it's better to try to match offsets from the beginning.
1295 */
02626b6a 1296 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1297 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1298 if (!check_tsc_unstable()) {
e26101b1 1299 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1300 pr_debug("kvm: matched tsc offset for %llu\n", data);
1301 } else {
857e4099 1302 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1303 data += delta;
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1306 }
b48aa97e 1307 matched = true;
0d3da0d2 1308 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1309 } else {
1310 /*
1311 * We split periods of matched TSC writes into generations.
1312 * For each generation, we track the original measured
1313 * nanosecond time, offset, and write, so if TSCs are in
1314 * sync, we can match exact offset, and if not, we can match
4a969980 1315 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1316 *
1317 * These values are tracked in kvm->arch.cur_xxx variables.
1318 */
1319 kvm->arch.cur_tsc_generation++;
1320 kvm->arch.cur_tsc_nsec = ns;
1321 kvm->arch.cur_tsc_write = data;
1322 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1323 matched = false;
0d3da0d2 1324 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1325 kvm->arch.cur_tsc_generation, data);
f38e098f 1326 }
e26101b1
ZA		 1327
1328 /*
1329 * We also track th most recent recorded KHZ, write and time to
1330 * allow the matching interval to be extended at each write.
1331 */
f38e098f
ZA		 1332 kvm->arch.last_tsc_nsec = ns;
1333 kvm->arch.last_tsc_write = data;
5d3cb0f6 1334 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1335
b183aa58 1336 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1337
1338 /* Keep track of which generation this VCPU has synchronized to */
1339 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1340 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1341 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1342
ba904635
WA		 1343 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1344 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1345 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1346 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1347
1348 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1349 if (!matched) {
b48aa97e 1350 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1351 } else if (!already_matched) {
1352 kvm->arch.nr_vcpus_matched_tsc++;
1353 }
b48aa97e
MT		 1354
1355 kvm_track_tsc_matching(vcpu);
1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1357}
e26101b1 1358
99e3e30a
ZA		 1359EXPORT_SYMBOL_GPL(kvm_write_tsc);
1360
d828199e
MT		 1361#ifdef CONFIG_X86_64
1362
1363static cycle_t read_tsc(void)
1364{
1365 cycle_t ret;
1366 u64 last;
1367
1368 /*
1369 * Empirically, a fence (of type that depends on the CPU)
1370 * before rdtsc is enough to ensure that rdtsc is ordered
1371 * with respect to loads. The various CPU manuals are unclear
1372 * as to whether rdtsc can be reordered with later loads,
1373 * but no one has ever seen it happen.
1374 */
1375 rdtsc_barrier();
1376 ret = (cycle_t)vget_cycles();
1377
1378 last = pvclock_gtod_data.clock.cycle_last;
1379
1380 if (likely(ret >= last))
1381 return ret;
1382
1383 /*
1384 * GCC likes to generate cmov here, but this branch is extremely
1385 * predictable (it's just a funciton of time and the likely is
1386 * very likely) and there's a data dependence, so force GCC
1387 * to generate a branch instead. I don't barrier() because
1388 * we don't actually need a barrier, and if this function
1389 * ever gets inlined it will generate worse code.
1390 */
1391 asm volatile ("");
1392 return last;
1393}
1394
1395static inline u64 vgettsc(cycle_t *cycle_now)
1396{
1397 long v;
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1399
1400 *cycle_now = read_tsc();
1401
1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1403 return v * gtod->clock.mult;
1404}
1405
cbcf2dd3 1406static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1407{
cbcf2dd3 1408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1409 unsigned long seq;
d828199e 1410 int mode;
cbcf2dd3 1411 u64 ns;
d828199e 1412
d828199e
MT		 1413 do {
1414 seq = read_seqcount_begin(&gtod->seq);
1415 mode = gtod->clock.vclock_mode;
cbcf2dd3 1416 ns = gtod->nsec_base;
d828199e
MT		 1417 ns += vgettsc(cycle_now);
1418 ns >>= gtod->clock.shift;
cbcf2dd3 1419 ns += gtod->boot_ns;
d828199e 1420 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1421 *t = ns;
d828199e
MT		 1422
1423 return mode;
1424}
1425
1426/* returns true if host is using tsc clocksource */
1427static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1428{
d828199e
MT		 1429 /* checked again under seqlock below */
1430 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1431 return false;
1432
cbcf2dd3 1433 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1434}
1435#endif
1436
1437/*
1438 *
b48aa97e
MT		 1439 * Assuming a stable TSC across physical CPUS, and a stable TSC
1440 * across virtual CPUs, the following condition is possible.
1441 * Each numbered line represents an event visible to both
d828199e
MT		 1442 * CPUs at the next numbered event.
1443 *
1444 * "timespecX" represents host monotonic time. "tscX" represents
1445 * RDTSC value.
1446 *
1447 * VCPU0 on CPU0 | VCPU1 on CPU1
1448 *
1449 * 1. read timespec0,tsc0
1450 * 2. | timespec1 = timespec0 + N
1451 * | tsc1 = tsc0 + M
1452 * 3. transition to guest | transition to guest
1453 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1454 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1455 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1456 *
1457 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1458 *
1459 * - ret0 < ret1
1460 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1461 * ...
1462 * - 0 < N - M => M < N
1463 *
1464 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1465 * always the case (the difference between two distinct xtime instances
1466 * might be smaller then the difference between corresponding TSC reads,
1467 * when updating guest vcpus pvclock areas).
1468 *
1469 * To avoid that problem, do not allow visibility of distinct
1470 * system_timestamp/tsc_timestamp values simultaneously: use a master
1471 * copy of host monotonic time values. Update that master copy
1472 * in lockstep.
1473 *
b48aa97e 1474 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1475 *
1476 */
1477
1478static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1479{
1480#ifdef CONFIG_X86_64
1481 struct kvm_arch *ka = &kvm->arch;
1482 int vclock_mode;
b48aa97e
MT		 1483 bool host_tsc_clocksource, vcpus_matched;
1484
1485 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1486 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1487
1488 /*
1489 * If the host uses TSC clock, then passthrough TSC as stable
1490 * to the guest.
1491 */
b48aa97e 1492 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1493 &ka->master_kernel_ns,
1494 &ka->master_cycle_now);
1495
16a96021
MT		 1496 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1497 && !backwards_tsc_observed;
b48aa97e 1498
d828199e
MT		 1499 if (ka->use_master_clock)
1500 atomic_set(&kvm_guest_has_master_clock, 1);
1501
1502 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1503 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1504 vcpus_matched);
d828199e
MT		 1505#endif
1506}
1507
2e762ff7
MT		 1508static void kvm_gen_update_masterclock(struct kvm *kvm)
1509{
1510#ifdef CONFIG_X86_64
1511 int i;
1512 struct kvm_vcpu *vcpu;
1513 struct kvm_arch *ka = &kvm->arch;
1514
1515 spin_lock(&ka->pvclock_gtod_sync_lock);
1516 kvm_make_mclock_inprogress_request(kvm);
1517 /* no guest entries from this point */
1518 pvclock_update_vm_gtod_copy(kvm);
1519
1520 kvm_for_each_vcpu(i, vcpu, kvm)
1521 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1522
1523 /* guest entries allowed */
1524 kvm_for_each_vcpu(i, vcpu, kvm)
1525 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1526
1527 spin_unlock(&ka->pvclock_gtod_sync_lock);
1528#endif
1529}
1530
34c238a1 1531static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1532{
d828199e 1533 unsigned long flags, this_tsc_khz;
18068523 1534 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1535 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1536 s64 kernel_ns;
d828199e 1537 u64 tsc_timestamp, host_tsc;
0b79459b 1538 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1539 u8 pvclock_flags;
d828199e
MT		 1540 bool use_master_clock;
1541
1542 kernel_ns = 0;
1543 host_tsc = 0;
18068523 1544
d828199e
MT		 1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
1549 spin_lock(&ka->pvclock_gtod_sync_lock);
1550 use_master_clock = ka->use_master_clock;
1551 if (use_master_clock) {
1552 host_tsc = ka->master_cycle_now;
1553 kernel_ns = ka->master_kernel_ns;
1554 }
1555 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1556
1557 /* Keep irq disabled to prevent changes to the clock */
1558 local_irq_save(flags);
1559 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1560 if (unlikely(this_tsc_khz == 0)) {
1561 local_irq_restore(flags);
1562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1563 return 1;
1564 }
d828199e
MT		 1565 if (!use_master_clock) {
1566 host_tsc = native_read_tsc();
1567 kernel_ns = get_kernel_ns();
1568 }
1569
1570 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1571
c285545f
ZA		 1572 /*
1573 * We may have to catch up the TSC to match elapsed wall clock
1574 * time for two reasons, even if kvmclock is used.
1575 * 1) CPU could have been running below the maximum TSC rate
1576 * 2) Broken TSC compensation resets the base at each VCPU
1577 * entry to avoid unknown leaps of TSC even when running
1578 * again on the same CPU. This may cause apparent elapsed
1579 * time to disappear, and the guest to stand still or run
1580 * very slowly.
1581 */
1582 if (vcpu->tsc_catchup) {
1583 u64 tsc = compute_guest_tsc(v, kernel_ns);
1584 if (tsc > tsc_timestamp) {
f1e2b260 1585 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1586 tsc_timestamp = tsc;
1587 }
50d0a0f9
GH		 1588 }
1589
18068523
GOC		 1590 local_irq_restore(flags);
1591
0b79459b 1592 if (!vcpu->pv_time_enabled)
c285545f 1593 return 0;
18068523 1594
e48672fa 1595 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1596 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1597 &vcpu->hv_clock.tsc_shift,
1598 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1599 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1600 }
1601
1602 /* With all the info we got, fill in the values */
1d5f066e 1603 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1604 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1605 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1606
18068523
GOC		 1607 /*
1608 * The interface expects us to write an even number signaling that the
1609 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1610 * state, we just increase by 2 at the end.
18068523 1611 */
50d0a0f9 1612 vcpu->hv_clock.version += 2;
18068523 1613
0b79459b
AH		 1614 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1615 &guest_hv_clock, sizeof(guest_hv_clock))))
1616 return 0;
78c0337a
MT		 1617
1618 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1619 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1620
1621 if (vcpu->pvclock_set_guest_stopped_request) {
1622 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1623 vcpu->pvclock_set_guest_stopped_request = false;
1624 }
1625
d828199e
MT		 1626 /* If the host uses TSC clocksource, then it is stable */
1627 if (use_master_clock)
1628 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1629
78c0337a
MT		 1630 vcpu->hv_clock.flags = pvclock_flags;
1631
0b79459b
AH		 1632 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1633 &vcpu->hv_clock,
1634 sizeof(vcpu->hv_clock));
8cfdc000 1635 return 0;
c8076604
GH		 1636}
1637
0061d53d
MT		 1638/*
1639 * kvmclock updates which are isolated to a given vcpu, such as
1640 * vcpu->cpu migration, should not allow system_timestamp from
1641 * the rest of the vcpus to remain static. Otherwise ntp frequency
1642 * correction applies to one vcpu's system_timestamp but not
1643 * the others.
1644 *
1645 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1646 * We need to rate-limit these requests though, as they can
1647 * considerably slow guests that have a large number of vcpus.
1648 * The time for a remote vcpu to update its kvmclock is bound
1649 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1650 */
1651
7e44e449
AJ		 1652#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1653
1654static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1655{
1656 int i;
7e44e449
AJ		 1657 struct delayed_work *dwork = to_delayed_work(work);
1658 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1659 kvmclock_update_work);
1660 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1661 struct kvm_vcpu *vcpu;
1662
1663 kvm_for_each_vcpu(i, vcpu, kvm) {
1664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1665 kvm_vcpu_kick(vcpu);
1666 }
1667}
1668
7e44e449
AJ		 1669static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1670{
1671 struct kvm *kvm = v->kvm;
1672
1673 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1675 KVMCLOCK_UPDATE_DELAY);
1676}
1677
332967a3
AJ		 1678#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1679
1680static void kvmclock_sync_fn(struct work_struct *work)
1681{
1682 struct delayed_work *dwork = to_delayed_work(work);
1683 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1684 kvmclock_sync_work);
1685 struct kvm *kvm = container_of(ka, struct kvm, arch);
1686
1687 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1688 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1689 KVMCLOCK_SYNC_PERIOD);
1690}
1691
9ba075a6
AK		 1692static bool msr_mtrr_valid(unsigned msr)
1693{
1694 switch (msr) {
1695 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1696 case MSR_MTRRfix64K_00000:
1697 case MSR_MTRRfix16K_80000:
1698 case MSR_MTRRfix16K_A0000:
1699 case MSR_MTRRfix4K_C0000:
1700 case MSR_MTRRfix4K_C8000:
1701 case MSR_MTRRfix4K_D0000:
1702 case MSR_MTRRfix4K_D8000:
1703 case MSR_MTRRfix4K_E0000:
1704 case MSR_MTRRfix4K_E8000:
1705 case MSR_MTRRfix4K_F0000:
1706 case MSR_MTRRfix4K_F8000:
1707 case MSR_MTRRdefType:
1708 case MSR_IA32_CR_PAT:
1709 return true;
1710 case 0x2f8:
1711 return true;
1712 }
1713 return false;
1714}
1715
d6289b93
MT		 1716static bool valid_pat_type(unsigned t)
1717{
1718 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1719}
1720
1721static bool valid_mtrr_type(unsigned t)
1722{
1723 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1724}
1725
1726static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1727{
1728 int i;
1729
1730 if (!msr_mtrr_valid(msr))
1731 return false;
1732
1733 if (msr == MSR_IA32_CR_PAT) {
1734 for (i = 0; i < 8; i++)
1735 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1736 return false;
1737 return true;
1738 } else if (msr == MSR_MTRRdefType) {
1739 if (data & ~0xcff)
1740 return false;
1741 return valid_mtrr_type(data & 0xff);
1742 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1743 for (i = 0; i < 8 ; i++)
1744 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1745 return false;
1746 return true;
1747 }
1748
1749 /* variable MTRRs */
1750 return valid_mtrr_type(data & 0xff);
1751}
1752
9ba075a6
AK		 1753static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1754{
0bed3b56
SY		 1755 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1756
d6289b93 1757 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1758 return 1;
1759
0bed3b56
SY		 1760 if (msr == MSR_MTRRdefType) {
1761 vcpu->arch.mtrr_state.def_type = data;
1762 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1763 } else if (msr == MSR_MTRRfix64K_00000)
1764 p[0] = data;
1765 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1766 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1767 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1768 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1769 else if (msr == MSR_IA32_CR_PAT)
1770 vcpu->arch.pat = data;
1771 else { /* Variable MTRRs */
1772 int idx, is_mtrr_mask;
1773 u64 *pt;
1774
1775 idx = (msr - 0x200) / 2;
1776 is_mtrr_mask = msr - 0x200 - 2 * idx;
1777 if (!is_mtrr_mask)
1778 pt =
1779 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1780 else
1781 pt =
1782 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1783 *pt = data;
1784 }
1785
1786 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1787 return 0;
1788}
15c4a640 1789
890ca9ae 1790static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1791{
890ca9ae
HY		 1792 u64 mcg_cap = vcpu->arch.mcg_cap;
1793 unsigned bank_num = mcg_cap & 0xff;
1794
15c4a640 1795 switch (msr) {
15c4a640 1796 case MSR_IA32_MCG_STATUS:
890ca9ae 1797 vcpu->arch.mcg_status = data;
15c4a640 1798 break;
c7ac679c 1799 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1800 if (!(mcg_cap & MCG_CTL_P))
1801 return 1;
1802 if (data != 0 && data != ~(u64)0)
1803 return -1;
1804 vcpu->arch.mcg_ctl = data;
1805 break;
1806 default:
1807 if (msr >= MSR_IA32_MC0_CTL &&
1808 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1809 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1810 /* only 0 or all 1s can be written to IA32_MCi_CTL
1811 * some Linux kernels though clear bit 10 in bank 4 to
1812 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1813 * this to avoid an uncatched #GP in the guest
1814 */
890ca9ae 1815 if ((offset & 0x3) == 0 &&
114be429 1816 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1817 return -1;
1818 vcpu->arch.mce_banks[offset] = data;
1819 break;
1820 }
1821 return 1;
1822 }
1823 return 0;
1824}
1825
ffde22ac
ES		 1826static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1827{
1828 struct kvm *kvm = vcpu->kvm;
1829 int lm = is_long_mode(vcpu);
1830 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1831 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1832 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1833 : kvm->arch.xen_hvm_config.blob_size_32;
1834 u32 page_num = data & ~PAGE_MASK;
1835 u64 page_addr = data & PAGE_MASK;
1836 u8 *page;
1837 int r;
1838
1839 r = -E2BIG;
1840 if (page_num >= blob_size)
1841 goto out;
1842 r = -ENOMEM;
ff5c2c03
SL		 1843 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1844 if (IS_ERR(page)) {
1845 r = PTR_ERR(page);
ffde22ac 1846 goto out;
ff5c2c03 1847 }
ffde22ac
ES		 1848 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1849 goto out_free;
1850 r = 0;
1851out_free:
1852 kfree(page);
1853out:
1854 return r;
1855}
1856
55cd8e5a
GN		 1857static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1858{
1859 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1860}
1861
1862static bool kvm_hv_msr_partition_wide(u32 msr)
1863{
1864 bool r = false;
1865 switch (msr) {
1866 case HV_X64_MSR_GUEST_OS_ID:
1867 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1868 case HV_X64_MSR_REFERENCE_TSC:
1869 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1870 r = true;
1871 break;
1872 }
1873
1874 return r;
1875}
1876
1877static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1878{
1879 struct kvm *kvm = vcpu->kvm;
1880
1881 switch (msr) {
1882 case HV_X64_MSR_GUEST_OS_ID:
1883 kvm->arch.hv_guest_os_id = data;
1884 /* setting guest os id to zero disables hypercall page */
1885 if (!kvm->arch.hv_guest_os_id)
1886 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1887 break;
1888 case HV_X64_MSR_HYPERCALL: {
1889 u64 gfn;
1890 unsigned long addr;
1891 u8 instructions[4];
1892
1893 /* if guest os id is not set hypercall should remain disabled */
1894 if (!kvm->arch.hv_guest_os_id)
1895 break;
1896 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1897 kvm->arch.hv_hypercall = data;
1898 break;
1899 }
1900 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1901 addr = gfn_to_hva(kvm, gfn);
1902 if (kvm_is_error_hva(addr))
1903 return 1;
1904 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1905 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1906 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1907 return 1;
1908 kvm->arch.hv_hypercall = data;
b94b64c9 1909 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1910 break;
1911 }
e984097b
VR		 1912 case HV_X64_MSR_REFERENCE_TSC: {
1913 u64 gfn;
1914 HV_REFERENCE_TSC_PAGE tsc_ref;
1915 memset(&tsc_ref, 0, sizeof(tsc_ref));
1916 kvm->arch.hv_tsc_page = data;
1917 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1918 break;
1919 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1920 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1921 &tsc_ref, sizeof(tsc_ref)))
1922 return 1;
1923 mark_page_dirty(kvm, gfn);
1924 break;
1925 }
55cd8e5a 1926 default:
a737f256
CD		 1927 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1928 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1929 return 1;
1930 }
1931 return 0;
1932}
1933
1934static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1935{
10388a07
GN		 1936 switch (msr) {
1937 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1938 u64 gfn;
10388a07 1939 unsigned long addr;
55cd8e5a 1940
10388a07
GN		 1941 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1942 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1943 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1944 return 1;
10388a07
GN		 1945 break;
1946 }
b3af1e88
VR		 1947 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1948 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1949 if (kvm_is_error_hva(addr))
1950 return 1;
8b0cedff 1951 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1952 return 1;
1953 vcpu->arch.hv_vapic = data;
b3af1e88 1954 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1955 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1956 return 1;
10388a07
GN		 1957 break;
1958 }
1959 case HV_X64_MSR_EOI:
1960 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1961 case HV_X64_MSR_ICR:
1962 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1963 case HV_X64_MSR_TPR:
1964 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1965 default:
a737f256
CD		 1966 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1967 "data 0x%llx\n", msr, data);
10388a07
GN		 1968 return 1;
1969 }
1970
1971 return 0;
55cd8e5a
GN		 1972}
1973
344d9588
GN		 1974static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1975{
1976 gpa_t gpa = data & ~0x3f;
1977
4a969980 1978 /* Bits 2:5 are reserved, Should be zero */
6adba527 1979 if (data & 0x3c)
344d9588
GN		 1980 return 1;
1981
1982 vcpu->arch.apf.msr_val = data;
1983
1984 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1985 kvm_clear_async_pf_completion_queue(vcpu);
1986 kvm_async_pf_hash_reset(vcpu);
1987 return 0;
1988 }
1989
8f964525
AH		 1990 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1991 sizeof(u32)))
344d9588
GN		 1992 return 1;
1993
6adba527 1994 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1995 kvm_async_pf_wakeup_all(vcpu);
1996 return 0;
1997}
1998
12f9a48f
GC		 1999static void kvmclock_reset(struct kvm_vcpu *vcpu)
2000{
0b79459b 2001 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2002}
2003
c9aaa895
GC		 2004static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2005{
2006 u64 delta;
2007
2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2009 return;
2010
2011 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2012 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2013 vcpu->arch.st.accum_steal = delta;
2014}
2015
2016static void record_steal_time(struct kvm_vcpu *vcpu)
2017{
2018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2019 return;
2020
2021 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2022 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2023 return;
2024
2025 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2026 vcpu->arch.st.steal.version += 2;
2027 vcpu->arch.st.accum_steal = 0;
2028
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2031}
2032
8fe8ab46 2033int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2034{
5753785f 2035 bool pr = false;
8fe8ab46
WA		 2036 u32 msr = msr_info->index;
2037 u64 data = msr_info->data;
5753785f 2038
15c4a640 2039 switch (msr) {
2e32b719
BP		 2040 case MSR_AMD64_NB_CFG:
2041 case MSR_IA32_UCODE_REV:
2042 case MSR_IA32_UCODE_WRITE:
2043 case MSR_VM_HSAVE_PA:
2044 case MSR_AMD64_PATCH_LOADER:
2045 case MSR_AMD64_BU_CFG2:
2046 break;
2047
15c4a640 2048 case MSR_EFER:
b69e8cae 2049 return set_efer(vcpu, data);
8f1589d9
AP		 2050 case MSR_K7_HWCR:
2051 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2052 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2053 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2054 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2055 if (data != 0) {
a737f256
CD		 2056 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2057 data);
8f1589d9
AP		 2058 return 1;
2059 }
15c4a640 2060 break;
f7c6d140
AP		 2061 case MSR_FAM10H_MMIO_CONF_BASE:
2062 if (data != 0) {
a737f256
CD		 2063 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2064 "0x%llx\n", data);
f7c6d140
AP		 2065 return 1;
2066 }
15c4a640 2067 break;
b5e2fec0
AG		 2068 case MSR_IA32_DEBUGCTLMSR:
2069 if (!data) {
2070 /* We support the non-activated case already */
2071 break;
2072 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2073 /* Values other than LBR and BTF are vendor-specific,
2074 thus reserved and should throw a #GP */
2075 return 1;
2076 }
a737f256
CD		 2077 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2078 __func__, data);
b5e2fec0 2079 break;
9ba075a6
AK		 2080 case 0x200 ... 0x2ff:
2081 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2082 case MSR_IA32_APICBASE:
58cb628d 2083 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2084 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2085 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2086 case MSR_IA32_TSCDEADLINE:
2087 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2088 break;
ba904635
WA		 2089 case MSR_IA32_TSC_ADJUST:
2090 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2091 if (!msr_info->host_initiated) {
2092 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2093 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2094 }
2095 vcpu->arch.ia32_tsc_adjust_msr = data;
2096 }
2097 break;
15c4a640 2098 case MSR_IA32_MISC_ENABLE:
ad312c7c 2099 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2100 break;
11c6bffa 2101 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2102 case MSR_KVM_WALL_CLOCK:
2103 vcpu->kvm->arch.wall_clock = data;
2104 kvm_write_wall_clock(vcpu->kvm, data);
2105 break;
11c6bffa 2106 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2107 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2108 u64 gpa_offset;
12f9a48f 2109 kvmclock_reset(vcpu);
18068523
GOC		 2110
2111 vcpu->arch.time = data;
0061d53d 2112 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2113
2114 /* we verify if the enable bit is set... */
2115 if (!(data & 1))
2116 break;
2117
0b79459b 2118 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2119
0b79459b 2120 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2121 &vcpu->arch.pv_time, data & ~1ULL,
2122 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2123 vcpu->arch.pv_time_enabled = false;
2124 else
2125 vcpu->arch.pv_time_enabled = true;
32cad84f 2126
18068523
GOC		 2127 break;
2128 }
344d9588
GN		 2129 case MSR_KVM_ASYNC_PF_EN:
2130 if (kvm_pv_enable_async_pf(vcpu, data))
2131 return 1;
2132 break;
c9aaa895
GC		 2133 case MSR_KVM_STEAL_TIME:
2134
2135 if (unlikely(!sched_info_on()))
2136 return 1;
2137
2138 if (data & KVM_STEAL_RESERVED_MASK)
2139 return 1;
2140
2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2142 data & KVM_STEAL_VALID_BITS,
2143 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2144 return 1;
2145
2146 vcpu->arch.st.msr_val = data;
2147
2148 if (!(data & KVM_MSR_ENABLED))
2149 break;
2150
2151 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2152
2153 preempt_disable();
2154 accumulate_steal_time(vcpu);
2155 preempt_enable();
2156
2157 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2158
2159 break;
ae7a2a3f
MT		 2160 case MSR_KVM_PV_EOI_EN:
2161 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2162 return 1;
2163 break;
c9aaa895 2164
890ca9ae
HY		 2165 case MSR_IA32_MCG_CTL:
2166 case MSR_IA32_MCG_STATUS:
2167 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2168 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2169
2170 /* Performance counters are not protected by a CPUID bit,
2171 * so we should check all of them in the generic path for the sake of
2172 * cross vendor migration.
2173 * Writing a zero into the event select MSRs disables them,
2174 * which we perfectly emulate ;-). Any other value should be at least
2175 * reported, some guests depend on them.
2176 */
71db6023
AP		 2177 case MSR_K7_EVNTSEL0:
2178 case MSR_K7_EVNTSEL1:
2179 case MSR_K7_EVNTSEL2:
2180 case MSR_K7_EVNTSEL3:
2181 if (data != 0)
a737f256
CD		 2182 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2183 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2184 break;
2185 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2186 * so we ignore writes to make it happy.
2187 */
71db6023
AP		 2188 case MSR_K7_PERFCTR0:
2189 case MSR_K7_PERFCTR1:
2190 case MSR_K7_PERFCTR2:
2191 case MSR_K7_PERFCTR3:
a737f256
CD		 2192 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2193 "0x%x data 0x%llx\n", msr, data);
71db6023 2194 break;
5753785f
GN		 2195 case MSR_P6_PERFCTR0:
2196 case MSR_P6_PERFCTR1:
2197 pr = true;
2198 case MSR_P6_EVNTSEL0:
2199 case MSR_P6_EVNTSEL1:
2200 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2201 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2202
2203 if (pr || data != 0)
a737f256
CD		 2204 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2205 "0x%x data 0x%llx\n", msr, data);
5753785f 2206 break;
84e0cefa
JS		 2207 case MSR_K7_CLK_CTL:
2208 /*
2209 * Ignore all writes to this no longer documented MSR.
2210 * Writes are only relevant for old K7 processors,
2211 * all pre-dating SVM, but a recommended workaround from
4a969980 2212 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2213 * affected processor models on the command line, hence
2214 * the need to ignore the workaround.
2215 */
2216 break;
55cd8e5a
GN		 2217 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2218 if (kvm_hv_msr_partition_wide(msr)) {
2219 int r;
2220 mutex_lock(&vcpu->kvm->lock);
2221 r = set_msr_hyperv_pw(vcpu, msr, data);
2222 mutex_unlock(&vcpu->kvm->lock);
2223 return r;
2224 } else
2225 return set_msr_hyperv(vcpu, msr, data);
2226 break;
91c9c3ed 2227 case MSR_IA32_BBL_CR_CTL3:
2228 /* Drop writes to this legacy MSR -- see rdmsr
2229 * counterpart for further detail.
2230 */
a737f256 2231 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2232 break;
2b036c6b
BO		 2233 case MSR_AMD64_OSVW_ID_LENGTH:
2234 if (!guest_cpuid_has_osvw(vcpu))
2235 return 1;
2236 vcpu->arch.osvw.length = data;
2237 break;
2238 case MSR_AMD64_OSVW_STATUS:
2239 if (!guest_cpuid_has_osvw(vcpu))
2240 return 1;
2241 vcpu->arch.osvw.status = data;
2242 break;
15c4a640 2243 default:
ffde22ac
ES		 2244 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2245 return xen_hvm_config(vcpu, data);
f5132b01 2246 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2247 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2248 if (!ignore_msrs) {
a737f256
CD		 2249 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2250 msr, data);
ed85c068
AP		 2251 return 1;
2252 } else {
a737f256
CD		 2253 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2254 msr, data);
ed85c068
AP		 2255 break;
2256 }
15c4a640
CO		 2257 }
2258 return 0;
2259}
2260EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2261
2262
2263/*
2264 * Reads an msr value (of 'msr_index') into 'pdata'.
2265 * Returns 0 on success, non-0 otherwise.
2266 * Assumes vcpu_load() was already called.
2267 */
2268int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2269{
2270 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2271}
2272
9ba075a6
AK		 2273static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2274{
0bed3b56
SY		 2275 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2276
9ba075a6
AK		 2277 if (!msr_mtrr_valid(msr))
2278 return 1;
2279
0bed3b56
SY		 2280 if (msr == MSR_MTRRdefType)
2281 *pdata = vcpu->arch.mtrr_state.def_type +
2282 (vcpu->arch.mtrr_state.enabled << 10);
2283 else if (msr == MSR_MTRRfix64K_00000)
2284 *pdata = p[0];
2285 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2286 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2287 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2288 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2289 else if (msr == MSR_IA32_CR_PAT)
2290 *pdata = vcpu->arch.pat;
2291 else { /* Variable MTRRs */
2292 int idx, is_mtrr_mask;
2293 u64 *pt;
2294
2295 idx = (msr - 0x200) / 2;
2296 is_mtrr_mask = msr - 0x200 - 2 * idx;
2297 if (!is_mtrr_mask)
2298 pt =
2299 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2300 else
2301 pt =
2302 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2303 *pdata = *pt;
2304 }
2305
9ba075a6
AK		 2306 return 0;
2307}
2308
890ca9ae 2309static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2310{
2311 u64 data;
890ca9ae
HY		 2312 u64 mcg_cap = vcpu->arch.mcg_cap;
2313 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2314
2315 switch (msr) {
15c4a640
CO		 2316 case MSR_IA32_P5_MC_ADDR:
2317 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2318 data = 0;
2319 break;
15c4a640 2320 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2321 data = vcpu->arch.mcg_cap;
2322 break;
c7ac679c 2323 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2324 if (!(mcg_cap & MCG_CTL_P))
2325 return 1;
2326 data = vcpu->arch.mcg_ctl;
2327 break;
2328 case MSR_IA32_MCG_STATUS:
2329 data = vcpu->arch.mcg_status;
2330 break;
2331 default:
2332 if (msr >= MSR_IA32_MC0_CTL &&
2333 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2334 u32 offset = msr - MSR_IA32_MC0_CTL;
2335 data = vcpu->arch.mce_banks[offset];
2336 break;
2337 }
2338 return 1;
2339 }
2340 *pdata = data;
2341 return 0;
2342}
2343
55cd8e5a
GN		 2344static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2345{
2346 u64 data = 0;
2347 struct kvm *kvm = vcpu->kvm;
2348
2349 switch (msr) {
2350 case HV_X64_MSR_GUEST_OS_ID:
2351 data = kvm->arch.hv_guest_os_id;
2352 break;
2353 case HV_X64_MSR_HYPERCALL:
2354 data = kvm->arch.hv_hypercall;
2355 break;
e984097b
VR		 2356 case HV_X64_MSR_TIME_REF_COUNT: {
2357 data =
2358 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2359 break;
2360 }
2361 case HV_X64_MSR_REFERENCE_TSC:
2362 data = kvm->arch.hv_tsc_page;
2363 break;
55cd8e5a 2364 default:
a737f256 2365 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2366 return 1;
2367 }
2368
2369 *pdata = data;
2370 return 0;
2371}
2372
2373static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2374{
2375 u64 data = 0;
2376
2377 switch (msr) {
2378 case HV_X64_MSR_VP_INDEX: {
2379 int r;
2380 struct kvm_vcpu *v;
684851a1
TY		 2381 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2382 if (v == vcpu) {
55cd8e5a 2383 data = r;
684851a1
TY		 2384 break;
2385 }
2386 }
55cd8e5a
GN		 2387 break;
2388 }
10388a07
GN		 2389 case HV_X64_MSR_EOI:
2390 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2391 case HV_X64_MSR_ICR:
2392 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2393 case HV_X64_MSR_TPR:
2394 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2395 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2396 data = vcpu->arch.hv_vapic;
2397 break;
55cd8e5a 2398 default:
a737f256 2399 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2400 return 1;
2401 }
2402 *pdata = data;
2403 return 0;
2404}
2405
890ca9ae
HY		 2406int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2407{
2408 u64 data;
2409
2410 switch (msr) {
890ca9ae 2411 case MSR_IA32_PLATFORM_ID:
15c4a640 2412 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2413 case MSR_IA32_DEBUGCTLMSR:
2414 case MSR_IA32_LASTBRANCHFROMIP:
2415 case MSR_IA32_LASTBRANCHTOIP:
2416 case MSR_IA32_LASTINTFROMIP:
2417 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2418 case MSR_K8_SYSCFG:
2419 case MSR_K7_HWCR:
61a6bd67 2420 case MSR_VM_HSAVE_PA:
9e699624 2421 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2422 case MSR_K7_EVNTSEL1:
2423 case MSR_K7_EVNTSEL2:
2424 case MSR_K7_EVNTSEL3:
1f3ee616 2425 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2426 case MSR_K7_PERFCTR1:
2427 case MSR_K7_PERFCTR2:
2428 case MSR_K7_PERFCTR3:
1fdbd48c 2429 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2430 case MSR_AMD64_NB_CFG:
f7c6d140 2431 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2432 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2433 data = 0;
2434 break;
5753785f
GN		 2435 case MSR_P6_PERFCTR0:
2436 case MSR_P6_PERFCTR1:
2437 case MSR_P6_EVNTSEL0:
2438 case MSR_P6_EVNTSEL1:
2439 if (kvm_pmu_msr(vcpu, msr))
2440 return kvm_pmu_get_msr(vcpu, msr, pdata);
2441 data = 0;
2442 break;
742bc670
MT		 2443 case MSR_IA32_UCODE_REV:
2444 data = 0x100000000ULL;
2445 break;
9ba075a6
AK		 2446 case MSR_MTRRcap:
2447 data = 0x500 | KVM_NR_VAR_MTRR;
2448 break;
2449 case 0x200 ... 0x2ff:
2450 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2451 case 0xcd: /* fsb frequency */
2452 data = 3;
2453 break;
7b914098
JS		 2454 /*
2455 * MSR_EBC_FREQUENCY_ID
2456 * Conservative value valid for even the basic CPU models.
2457 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2458 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2459 * and 266MHz for model 3, or 4. Set Core Clock
2460 * Frequency to System Bus Frequency Ratio to 1 (bits
2461 * 31:24) even though these are only valid for CPU
2462 * models > 2, however guests may end up dividing or
2463 * multiplying by zero otherwise.
2464 */
2465 case MSR_EBC_FREQUENCY_ID:
2466 data = 1 << 24;
2467 break;
15c4a640
CO		 2468 case MSR_IA32_APICBASE:
2469 data = kvm_get_apic_base(vcpu);
2470 break;
0105d1a5
GN		 2471 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2472 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2473 break;
a3e06bbe
LJ		 2474 case MSR_IA32_TSCDEADLINE:
2475 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2476 break;
ba904635
WA		 2477 case MSR_IA32_TSC_ADJUST:
2478 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2479 break;
15c4a640 2480 case MSR_IA32_MISC_ENABLE:
ad312c7c 2481 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2482 break;
847f0ad8
AG		 2483 case MSR_IA32_PERF_STATUS:
2484 /* TSC increment by tick */
2485 data = 1000ULL;
2486 /* CPU multiplier */
2487 data |= (((uint64_t)4ULL) << 40);
2488 break;
15c4a640 2489 case MSR_EFER:
f6801dff 2490 data = vcpu->arch.efer;
15c4a640 2491 break;
18068523 2492 case MSR_KVM_WALL_CLOCK:
11c6bffa 2493 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2494 data = vcpu->kvm->arch.wall_clock;
2495 break;
2496 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2497 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2498 data = vcpu->arch.time;
2499 break;
344d9588
GN		 2500 case MSR_KVM_ASYNC_PF_EN:
2501 data = vcpu->arch.apf.msr_val;
2502 break;
c9aaa895
GC		 2503 case MSR_KVM_STEAL_TIME:
2504 data = vcpu->arch.st.msr_val;
2505 break;
1d92128f
MT		 2506 case MSR_KVM_PV_EOI_EN:
2507 data = vcpu->arch.pv_eoi.msr_val;
2508 break;
890ca9ae
HY		 2509 case MSR_IA32_P5_MC_ADDR:
2510 case MSR_IA32_P5_MC_TYPE:
2511 case MSR_IA32_MCG_CAP:
2512 case MSR_IA32_MCG_CTL:
2513 case MSR_IA32_MCG_STATUS:
2514 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2515 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2516 case MSR_K7_CLK_CTL:
2517 /*
2518 * Provide expected ramp-up count for K7. All other
2519 * are set to zero, indicating minimum divisors for
2520 * every field.
2521 *
2522 * This prevents guest kernels on AMD host with CPU
2523 * type 6, model 8 and higher from exploding due to
2524 * the rdmsr failing.
2525 */
2526 data = 0x20000000;
2527 break;
55cd8e5a
GN		 2528 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2529 if (kvm_hv_msr_partition_wide(msr)) {
2530 int r;
2531 mutex_lock(&vcpu->kvm->lock);
2532 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2533 mutex_unlock(&vcpu->kvm->lock);
2534 return r;
2535 } else
2536 return get_msr_hyperv(vcpu, msr, pdata);
2537 break;
91c9c3ed 2538 case MSR_IA32_BBL_CR_CTL3:
2539 /* This legacy MSR exists but isn't fully documented in current
2540 * silicon. It is however accessed by winxp in very narrow
2541 * scenarios where it sets bit #19, itself documented as
2542 * a "reserved" bit. Best effort attempt to source coherent
2543 * read data here should the balance of the register be
2544 * interpreted by the guest:
2545 *
2546 * L2 cache control register 3: 64GB range, 256KB size,
2547 * enabled, latency 0x1, configured
2548 */
2549 data = 0xbe702111;
2550 break;
2b036c6b
BO		 2551 case MSR_AMD64_OSVW_ID_LENGTH:
2552 if (!guest_cpuid_has_osvw(vcpu))
2553 return 1;
2554 data = vcpu->arch.osvw.length;
2555 break;
2556 case MSR_AMD64_OSVW_STATUS:
2557 if (!guest_cpuid_has_osvw(vcpu))
2558 return 1;
2559 data = vcpu->arch.osvw.status;
2560 break;
15c4a640 2561 default:
f5132b01
GN		 2562 if (kvm_pmu_msr(vcpu, msr))
2563 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2564 if (!ignore_msrs) {
a737f256 2565 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2566 return 1;
2567 } else {
a737f256 2568 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2569 data = 0;
2570 }
2571 break;
15c4a640
CO		 2572 }
2573 *pdata = data;
2574 return 0;
2575}
2576EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2577
313a3dc7
CO		 2578/*
2579 * Read or write a bunch of msrs. All parameters are kernel addresses.
2580 *
2581 * @return number of msrs set successfully.
2582 */
2583static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2584 struct kvm_msr_entry *entries,
2585 int (*do_msr)(struct kvm_vcpu *vcpu,
2586 unsigned index, u64 *data))
2587{
f656ce01 2588 int i, idx;
313a3dc7 2589
f656ce01 2590 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2591 for (i = 0; i < msrs->nmsrs; ++i)
2592 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2593 break;
f656ce01 2594 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2595
313a3dc7
CO		 2596 return i;
2597}
2598
2599/*
2600 * Read or write a bunch of msrs. Parameters are user addresses.
2601 *
2602 * @return number of msrs set successfully.
2603 */
2604static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2605 int (*do_msr)(struct kvm_vcpu *vcpu,
2606 unsigned index, u64 *data),
2607 int writeback)
2608{
2609 struct kvm_msrs msrs;
2610 struct kvm_msr_entry *entries;
2611 int r, n;
2612 unsigned size;
2613
2614 r = -EFAULT;
2615 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2616 goto out;
2617
2618 r = -E2BIG;
2619 if (msrs.nmsrs >= MAX_IO_MSRS)
2620 goto out;
2621
313a3dc7 2622 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2623 entries = memdup_user(user_msrs->entries, size);
2624 if (IS_ERR(entries)) {
2625 r = PTR_ERR(entries);
313a3dc7 2626 goto out;
ff5c2c03 2627 }
313a3dc7
CO		 2628
2629 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2630 if (r < 0)
2631 goto out_free;
2632
2633 r = -EFAULT;
2634 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2635 goto out_free;
2636
2637 r = n;
2638
2639out_free:
7a73c028 2640 kfree(entries);
313a3dc7
CO		 2641out:
2642 return r;
2643}
2644
784aa3d7 2645int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2646{
2647 int r;
2648
2649 switch (ext) {
2650 case KVM_CAP_IRQCHIP:
2651 case KVM_CAP_HLT:
2652 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2653 case KVM_CAP_SET_TSS_ADDR:
07716717 2654 case KVM_CAP_EXT_CPUID:
9c15bb1d 2655 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2656 case KVM_CAP_CLOCKSOURCE:
7837699f 2657 case KVM_CAP_PIT:
a28e4f5a 2658 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2659 case KVM_CAP_MP_STATE:
ed848624 2660 case KVM_CAP_SYNC_MMU:
a355c85c 2661 case KVM_CAP_USER_NMI:
52d939a0 2662 case KVM_CAP_REINJECT_CONTROL:
4925663a 2663 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2664 case KVM_CAP_IRQFD:
d34e6b17 2665 case KVM_CAP_IOEVENTFD:
f848a5a8 2666 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2667 case KVM_CAP_PIT2:
e9f42757 2668 case KVM_CAP_PIT_STATE2:
b927a3ce 2669 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2670 case KVM_CAP_XEN_HVM:
afbcf7ab 2671 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2672 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2673 case KVM_CAP_HYPERV:
10388a07 2674 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2675 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2676 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2677 case KVM_CAP_DEBUGREGS:
d2be1651 2678 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2679 case KVM_CAP_XSAVE:
344d9588 2680 case KVM_CAP_ASYNC_PF:
92a1f12d 2681 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2682 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2683 case KVM_CAP_READONLY_MEM:
5f66b620 2684 case KVM_CAP_HYPERV_TIME:
100943c5 2685 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2686#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2687 case KVM_CAP_ASSIGN_DEV_IRQ:
2688 case KVM_CAP_PCI_2_3:
2689#endif
018d00d2
ZX		 2690 r = 1;
2691 break;
542472b5
LV		 2692 case KVM_CAP_COALESCED_MMIO:
2693 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2694 break;
774ead3a
AK		 2695 case KVM_CAP_VAPIC:
2696 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2697 break;
f725230a 2698 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2699 r = KVM_SOFT_MAX_VCPUS;
2700 break;
2701 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2702 r = KVM_MAX_VCPUS;
2703 break;
a988b910 2704 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2705 r = KVM_USER_MEM_SLOTS;
a988b910 2706 break;
a68a6a72
MT		 2707 case KVM_CAP_PV_MMU: /* obsolete */
2708 r = 0;
2f333bcb 2709 break;
4cee4b72 2710#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2711 case KVM_CAP_IOMMU:
a1b60c1c 2712 r = iommu_present(&pci_bus_type);
62c476c7 2713 break;
4cee4b72 2714#endif
890ca9ae
HY		 2715 case KVM_CAP_MCE:
2716 r = KVM_MAX_MCE_BANKS;
2717 break;
2d5b5a66
SY		 2718 case KVM_CAP_XCRS:
2719 r = cpu_has_xsave;
2720 break;
92a1f12d
JR		 2721 case KVM_CAP_TSC_CONTROL:
2722 r = kvm_has_tsc_control;
2723 break;
4d25a066
JK		 2724 case KVM_CAP_TSC_DEADLINE_TIMER:
2725 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2726 break;
018d00d2
ZX		 2727 default:
2728 r = 0;
2729 break;
2730 }
2731 return r;
2732
2733}
2734
043405e1
CO		 2735long kvm_arch_dev_ioctl(struct file *filp,
2736 unsigned int ioctl, unsigned long arg)
2737{
2738 void __user *argp = (void __user *)arg;
2739 long r;
2740
2741 switch (ioctl) {
2742 case KVM_GET_MSR_INDEX_LIST: {
2743 struct kvm_msr_list __user *user_msr_list = argp;
2744 struct kvm_msr_list msr_list;
2745 unsigned n;
2746
2747 r = -EFAULT;
2748 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2749 goto out;
2750 n = msr_list.nmsrs;
2751 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2752 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2753 goto out;
2754 r = -E2BIG;
e125e7b6 2755 if (n < msr_list.nmsrs)
043405e1
CO		 2756 goto out;
2757 r = -EFAULT;
2758 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2759 num_msrs_to_save * sizeof(u32)))
2760 goto out;
e125e7b6 2761 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2762 &emulated_msrs,
2763 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2764 goto out;
2765 r = 0;
2766 break;
2767 }
9c15bb1d
BP		 2768 case KVM_GET_SUPPORTED_CPUID:
2769 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2770 struct kvm_cpuid2 __user *cpuid_arg = argp;
2771 struct kvm_cpuid2 cpuid;
2772
2773 r = -EFAULT;
2774 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2775 goto out;
9c15bb1d
BP		 2776
2777 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2778 ioctl);
674eea0f
AK		 2779 if (r)
2780 goto out;
2781
2782 r = -EFAULT;
2783 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2784 goto out;
2785 r = 0;
2786 break;
2787 }
890ca9ae
HY		 2788 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2789 u64 mce_cap;
2790
2791 mce_cap = KVM_MCE_CAP_SUPPORTED;
2792 r = -EFAULT;
2793 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2794 goto out;
2795 r = 0;
2796 break;
2797 }
043405e1
CO		 2798 default:
2799 r = -EINVAL;
2800 }
2801out:
2802 return r;
2803}
2804
f5f48ee1
SY		 2805static void wbinvd_ipi(void *garbage)
2806{
2807 wbinvd();
2808}
2809
2810static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2811{
e0f0bbc5 2812 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2813}
2814
313a3dc7
CO		 2815void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2816{
f5f48ee1
SY		 2817 /* Address WBINVD may be executed by guest */
2818 if (need_emulate_wbinvd(vcpu)) {
2819 if (kvm_x86_ops->has_wbinvd_exit())
2820 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2821 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2822 smp_call_function_single(vcpu->cpu,
2823 wbinvd_ipi, NULL, 1);
2824 }
2825
313a3dc7 2826 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2827
0dd6a6ed
ZA		 2828 /* Apply any externally detected TSC adjustments (due to suspend) */
2829 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2830 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2831 vcpu->arch.tsc_offset_adjustment = 0;
2832 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2833 }
8f6055cb 2834
48434c20 2835 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2836 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2837 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2838 if (tsc_delta < 0)
2839 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2840 if (check_tsc_unstable()) {
b183aa58
ZA		 2841 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2842 vcpu->arch.last_guest_tsc);
2843 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2844 vcpu->arch.tsc_catchup = 1;
c285545f 2845 }
d98d07ca
MT		 2846 /*
2847 * On a host with synchronized TSC, there is no need to update
2848 * kvmclock on vcpu->cpu migration
2849 */
2850 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2851 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2852 if (vcpu->cpu != cpu)
2853 kvm_migrate_timers(vcpu);
e48672fa 2854 vcpu->cpu = cpu;
6b7d7e76 2855 }
c9aaa895
GC		 2856
2857 accumulate_steal_time(vcpu);
2858 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2859}
2860
2861void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2862{
02daab21 2863 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2864 kvm_put_guest_fpu(vcpu);
6f526ec5 2865 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2866}
2867
313a3dc7
CO		 2868static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2869 struct kvm_lapic_state *s)
2870{
5a71785d 2871 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2872 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2873
2874 return 0;
2875}
2876
2877static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2878 struct kvm_lapic_state *s)
2879{
64eb0620 2880 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2881 update_cr8_intercept(vcpu);
313a3dc7
CO		 2882
2883 return 0;
2884}
2885
f77bc6a4
ZX		 2886static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2887 struct kvm_interrupt *irq)
2888{
02cdb50f 2889 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2890 return -EINVAL;
2891 if (irqchip_in_kernel(vcpu->kvm))
2892 return -ENXIO;
f77bc6a4 2893
66fd3f7f 2894 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2895 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2896
f77bc6a4
ZX		 2897 return 0;
2898}
2899
c4abb7c9
JK		 2900static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2901{
c4abb7c9 2902 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2903
2904 return 0;
2905}
2906
b209749f
AK		 2907static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2908 struct kvm_tpr_access_ctl *tac)
2909{
2910 if (tac->flags)
2911 return -EINVAL;
2912 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2913 return 0;
2914}
2915
890ca9ae
HY		 2916static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2917 u64 mcg_cap)
2918{
2919 int r;
2920 unsigned bank_num = mcg_cap & 0xff, bank;
2921
2922 r = -EINVAL;
a9e38c3e 2923 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2924 goto out;
2925 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2926 goto out;
2927 r = 0;
2928 vcpu->arch.mcg_cap = mcg_cap;
2929 /* Init IA32_MCG_CTL to all 1s */
2930 if (mcg_cap & MCG_CTL_P)
2931 vcpu->arch.mcg_ctl = ~(u64)0;
2932 /* Init IA32_MCi_CTL to all 1s */
2933 for (bank = 0; bank < bank_num; bank++)
2934 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2935out:
2936 return r;
2937}
2938
2939static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2940 struct kvm_x86_mce *mce)
2941{
2942 u64 mcg_cap = vcpu->arch.mcg_cap;
2943 unsigned bank_num = mcg_cap & 0xff;
2944 u64 *banks = vcpu->arch.mce_banks;
2945
2946 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2947 return -EINVAL;
2948 /*
2949 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2950 * reporting is disabled
2951 */
2952 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2953 vcpu->arch.mcg_ctl != ~(u64)0)
2954 return 0;
2955 banks += 4 * mce->bank;
2956 /*
2957 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2958 * reporting is disabled for the bank
2959 */
2960 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2961 return 0;
2962 if (mce->status & MCI_STATUS_UC) {
2963 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2964 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2965 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2966 return 0;
2967 }
2968 if (banks[1] & MCI_STATUS_VAL)
2969 mce->status |= MCI_STATUS_OVER;
2970 banks[2] = mce->addr;
2971 banks[3] = mce->misc;
2972 vcpu->arch.mcg_status = mce->mcg_status;
2973 banks[1] = mce->status;
2974 kvm_queue_exception(vcpu, MC_VECTOR);
2975 } else if (!(banks[1] & MCI_STATUS_VAL)
2976 || !(banks[1] & MCI_STATUS_UC)) {
2977 if (banks[1] & MCI_STATUS_VAL)
2978 mce->status |= MCI_STATUS_OVER;
2979 banks[2] = mce->addr;
2980 banks[3] = mce->misc;
2981 banks[1] = mce->status;
2982 } else
2983 banks[1] |= MCI_STATUS_OVER;
2984 return 0;
2985}
2986
3cfc3092
JK		 2987static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2988 struct kvm_vcpu_events *events)
2989{
7460fb4a 2990 process_nmi(vcpu);
03b82a30
JK		 2991 events->exception.injected =
2992 vcpu->arch.exception.pending &&
2993 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2994 events->exception.nr = vcpu->arch.exception.nr;
2995 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2996 events->exception.pad = 0;
3cfc3092
JK		 2997 events->exception.error_code = vcpu->arch.exception.error_code;
2998
03b82a30
JK		 2999 events->interrupt.injected =
3000 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3001 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3002 events->interrupt.soft = 0;
37ccdcbe 3003 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3004
3005 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3006 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3007 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3008 events->nmi.pad = 0;
3cfc3092 3009
66450a21 3010 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3011
dab4b911 3012 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3013 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3014 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3015}
3016
3017static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3018 struct kvm_vcpu_events *events)
3019{
dab4b911 3020 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3021 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3022 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3023 return -EINVAL;
3024
7460fb4a 3025 process_nmi(vcpu);
3cfc3092
JK		 3026 vcpu->arch.exception.pending = events->exception.injected;
3027 vcpu->arch.exception.nr = events->exception.nr;
3028 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3029 vcpu->arch.exception.error_code = events->exception.error_code;
3030
3031 vcpu->arch.interrupt.pending = events->interrupt.injected;
3032 vcpu->arch.interrupt.nr = events->interrupt.nr;
3033 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3034 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3035 kvm_x86_ops->set_interrupt_shadow(vcpu,
3036 events->interrupt.shadow);
3cfc3092
JK		 3037
3038 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3039 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3040 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3041 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3042
66450a21
JK		 3043 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3044 kvm_vcpu_has_lapic(vcpu))
3045 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3046
3842d135
AK		 3047 kvm_make_request(KVM_REQ_EVENT, vcpu);
3048
3cfc3092
JK		 3049 return 0;
3050}
3051
a1efbe77
JK		 3052static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3053 struct kvm_debugregs *dbgregs)
3054{
73aaf249
JK		 3055 unsigned long val;
3056
a1efbe77 3057 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3058 _kvm_get_dr(vcpu, 6, &val);
3059 dbgregs->dr6 = val;
a1efbe77
JK		 3060 dbgregs->dr7 = vcpu->arch.dr7;
3061 dbgregs->flags = 0;
97e69aa6 3062 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3063}
3064
3065static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3066 struct kvm_debugregs *dbgregs)
3067{
3068 if (dbgregs->flags)
3069 return -EINVAL;
3070
a1efbe77
JK		 3071 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3072 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3073 kvm_update_dr6(vcpu);
a1efbe77 3074 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3075 kvm_update_dr7(vcpu);
a1efbe77 3076
a1efbe77
JK		 3077 return 0;
3078}
3079
2d5b5a66
SY		 3080static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3081 struct kvm_xsave *guest_xsave)
3082{
4344ee98 3083 if (cpu_has_xsave) {
2d5b5a66
SY		 3084 memcpy(guest_xsave->region,
3085 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3086 vcpu->arch.guest_xstate_size);
3087 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3088 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3089 } else {
2d5b5a66
SY		 3090 memcpy(guest_xsave->region,
3091 &vcpu->arch.guest_fpu.state->fxsave,
3092 sizeof(struct i387_fxsave_struct));
3093 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3094 XSTATE_FPSSE;
3095 }
3096}
3097
3098static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3099 struct kvm_xsave *guest_xsave)
3100{
3101 u64 xstate_bv =
3102 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3103
d7876f1b
PB		 3104 if (cpu_has_xsave) {
3105 /*
3106 * Here we allow setting states that are not present in
3107 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3108 * with old userspace.
3109 */
4ff41732 3110 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3111 return -EINVAL;
2d5b5a66 3112 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3113 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3114 } else {
2d5b5a66
SY		 3115 if (xstate_bv & ~XSTATE_FPSSE)
3116 return -EINVAL;
3117 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3118 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3119 }
3120 return 0;
3121}
3122
3123static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3124 struct kvm_xcrs *guest_xcrs)
3125{
3126 if (!cpu_has_xsave) {
3127 guest_xcrs->nr_xcrs = 0;
3128 return;
3129 }
3130
3131 guest_xcrs->nr_xcrs = 1;
3132 guest_xcrs->flags = 0;
3133 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3134 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3135}
3136
3137static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3138 struct kvm_xcrs *guest_xcrs)
3139{
3140 int i, r = 0;
3141
3142 if (!cpu_has_xsave)
3143 return -EINVAL;
3144
3145 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3146 return -EINVAL;
3147
3148 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3149 /* Only support XCR0 currently */
c67a04cb 3150 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3151 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3152 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3153 break;
3154 }
3155 if (r)
3156 r = -EINVAL;
3157 return r;
3158}
3159
1c0b28c2
EM		 3160/*
3161 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3162 * stopped by the hypervisor. This function will be called from the host only.
3163 * EINVAL is returned when the host attempts to set the flag for a guest that
3164 * does not support pv clocks.
3165 */
3166static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3167{
0b79459b 3168 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3169 return -EINVAL;
51d59c6b 3170 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3171 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3172 return 0;
3173}
3174
313a3dc7
CO		 3175long kvm_arch_vcpu_ioctl(struct file *filp,
3176 unsigned int ioctl, unsigned long arg)
3177{
3178 struct kvm_vcpu *vcpu = filp->private_data;
3179 void __user *argp = (void __user *)arg;
3180 int r;
d1ac91d8
AK		 3181 union {
3182 struct kvm_lapic_state *lapic;
3183 struct kvm_xsave *xsave;
3184 struct kvm_xcrs *xcrs;
3185 void *buffer;
3186 } u;
3187
3188 u.buffer = NULL;
313a3dc7
CO		 3189 switch (ioctl) {
3190 case KVM_GET_LAPIC: {
2204ae3c
MT		 3191 r = -EINVAL;
3192 if (!vcpu->arch.apic)
3193 goto out;
d1ac91d8 3194 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3195
b772ff36 3196 r = -ENOMEM;
d1ac91d8 3197 if (!u.lapic)
b772ff36 3198 goto out;
d1ac91d8 3199 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3200 if (r)
3201 goto out;
3202 r = -EFAULT;
d1ac91d8 3203 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3204 goto out;
3205 r = 0;
3206 break;
3207 }
3208 case KVM_SET_LAPIC: {
2204ae3c
MT		 3209 r = -EINVAL;
3210 if (!vcpu->arch.apic)
3211 goto out;
ff5c2c03 3212 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3213 if (IS_ERR(u.lapic))
3214 return PTR_ERR(u.lapic);
ff5c2c03 3215
d1ac91d8 3216 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3217 break;
3218 }
f77bc6a4
ZX		 3219 case KVM_INTERRUPT: {
3220 struct kvm_interrupt irq;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&irq, argp, sizeof irq))
3224 goto out;
3225 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3226 break;
3227 }
c4abb7c9
JK		 3228 case KVM_NMI: {
3229 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3230 break;
3231 }
313a3dc7
CO		 3232 case KVM_SET_CPUID: {
3233 struct kvm_cpuid __user *cpuid_arg = argp;
3234 struct kvm_cpuid cpuid;
3235
3236 r = -EFAULT;
3237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3238 goto out;
3239 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3240 break;
3241 }
07716717
DK		 3242 case KVM_SET_CPUID2: {
3243 struct kvm_cpuid2 __user *cpuid_arg = argp;
3244 struct kvm_cpuid2 cpuid;
3245
3246 r = -EFAULT;
3247 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3248 goto out;
3249 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3250 cpuid_arg->entries);
07716717
DK		 3251 break;
3252 }
3253 case KVM_GET_CPUID2: {
3254 struct kvm_cpuid2 __user *cpuid_arg = argp;
3255 struct kvm_cpuid2 cpuid;
3256
3257 r = -EFAULT;
3258 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3259 goto out;
3260 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3261 cpuid_arg->entries);
07716717
DK		 3262 if (r)
3263 goto out;
3264 r = -EFAULT;
3265 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3266 goto out;
3267 r = 0;
3268 break;
3269 }
313a3dc7
CO		 3270 case KVM_GET_MSRS:
3271 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3272 break;
3273 case KVM_SET_MSRS:
3274 r = msr_io(vcpu, argp, do_set_msr, 0);
3275 break;
b209749f
AK		 3276 case KVM_TPR_ACCESS_REPORTING: {
3277 struct kvm_tpr_access_ctl tac;
3278
3279 r = -EFAULT;
3280 if (copy_from_user(&tac, argp, sizeof tac))
3281 goto out;
3282 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3283 if (r)
3284 goto out;
3285 r = -EFAULT;
3286 if (copy_to_user(argp, &tac, sizeof tac))
3287 goto out;
3288 r = 0;
3289 break;
3290 };
b93463aa
AK		 3291 case KVM_SET_VAPIC_ADDR: {
3292 struct kvm_vapic_addr va;
3293
3294 r = -EINVAL;
3295 if (!irqchip_in_kernel(vcpu->kvm))
3296 goto out;
3297 r = -EFAULT;
3298 if (copy_from_user(&va, argp, sizeof va))
3299 goto out;
fda4e2e8 3300 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3301 break;
3302 }
890ca9ae
HY		 3303 case KVM_X86_SETUP_MCE: {
3304 u64 mcg_cap;
3305
3306 r = -EFAULT;
3307 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3308 goto out;
3309 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3310 break;
3311 }
3312 case KVM_X86_SET_MCE: {
3313 struct kvm_x86_mce mce;
3314
3315 r = -EFAULT;
3316 if (copy_from_user(&mce, argp, sizeof mce))
3317 goto out;
3318 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3319 break;
3320 }
3cfc3092
JK		 3321 case KVM_GET_VCPU_EVENTS: {
3322 struct kvm_vcpu_events events;
3323
3324 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3325
3326 r = -EFAULT;
3327 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3328 break;
3329 r = 0;
3330 break;
3331 }
3332 case KVM_SET_VCPU_EVENTS: {
3333 struct kvm_vcpu_events events;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3337 break;
3338
3339 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3340 break;
3341 }
a1efbe77
JK		 3342 case KVM_GET_DEBUGREGS: {
3343 struct kvm_debugregs dbgregs;
3344
3345 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3346
3347 r = -EFAULT;
3348 if (copy_to_user(argp, &dbgregs,
3349 sizeof(struct kvm_debugregs)))
3350 break;
3351 r = 0;
3352 break;
3353 }
3354 case KVM_SET_DEBUGREGS: {
3355 struct kvm_debugregs dbgregs;
3356
3357 r = -EFAULT;
3358 if (copy_from_user(&dbgregs, argp,
3359 sizeof(struct kvm_debugregs)))
3360 break;
3361
3362 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3363 break;
3364 }
2d5b5a66 3365 case KVM_GET_XSAVE: {
d1ac91d8 3366 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3367 r = -ENOMEM;
d1ac91d8 3368 if (!u.xsave)
2d5b5a66
SY		 3369 break;
3370
d1ac91d8 3371 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3372
3373 r = -EFAULT;
d1ac91d8 3374 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3375 break;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_XSAVE: {
ff5c2c03 3380 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3381 if (IS_ERR(u.xsave))
3382 return PTR_ERR(u.xsave);
2d5b5a66 3383
d1ac91d8 3384 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3385 break;
3386 }
3387 case KVM_GET_XCRS: {
d1ac91d8 3388 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3389 r = -ENOMEM;
d1ac91d8 3390 if (!u.xcrs)
2d5b5a66
SY		 3391 break;
3392
d1ac91d8 3393 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3394
3395 r = -EFAULT;
d1ac91d8 3396 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3397 sizeof(struct kvm_xcrs)))
3398 break;
3399 r = 0;
3400 break;
3401 }
3402 case KVM_SET_XCRS: {
ff5c2c03 3403 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3404 if (IS_ERR(u.xcrs))
3405 return PTR_ERR(u.xcrs);
2d5b5a66 3406
d1ac91d8 3407 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3408 break;
3409 }
92a1f12d
JR		 3410 case KVM_SET_TSC_KHZ: {
3411 u32 user_tsc_khz;
3412
3413 r = -EINVAL;
92a1f12d
JR		 3414 user_tsc_khz = (u32)arg;
3415
3416 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3417 goto out;
3418
cc578287
ZA		 3419 if (user_tsc_khz == 0)
3420 user_tsc_khz = tsc_khz;
3421
3422 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3423
3424 r = 0;
3425 goto out;
3426 }
3427 case KVM_GET_TSC_KHZ: {
cc578287 3428 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3429 goto out;
3430 }
1c0b28c2
EM		 3431 case KVM_KVMCLOCK_CTRL: {
3432 r = kvm_set_guest_paused(vcpu);
3433 goto out;
3434 }
313a3dc7
CO		 3435 default:
3436 r = -EINVAL;
3437 }
3438out:
d1ac91d8 3439 kfree(u.buffer);
313a3dc7
CO		 3440 return r;
3441}
3442
5b1c1493
CO		 3443int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3444{
3445 return VM_FAULT_SIGBUS;
3446}
3447
1fe779f8
CO		 3448static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3449{
3450 int ret;
3451
3452 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3453 return -EINVAL;
1fe779f8
CO		 3454 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3455 return ret;
3456}
3457
b927a3ce
SY		 3458static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3459 u64 ident_addr)
3460{
3461 kvm->arch.ept_identity_map_addr = ident_addr;
3462 return 0;
3463}
3464
1fe779f8
CO		 3465static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3466 u32 kvm_nr_mmu_pages)
3467{
3468 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3469 return -EINVAL;
3470
79fac95e 3471 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3472
3473 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3474 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3475
79fac95e 3476 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3477 return 0;
3478}
3479
3480static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3481{
39de71ec 3482 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3483}
3484
1fe779f8
CO		 3485static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3486{
3487 int r;
3488
3489 r = 0;
3490 switch (chip->chip_id) {
3491 case KVM_IRQCHIP_PIC_MASTER:
3492 memcpy(&chip->chip.pic,
3493 &pic_irqchip(kvm)->pics[0],
3494 sizeof(struct kvm_pic_state));
3495 break;
3496 case KVM_IRQCHIP_PIC_SLAVE:
3497 memcpy(&chip->chip.pic,
3498 &pic_irqchip(kvm)->pics[1],
3499 sizeof(struct kvm_pic_state));
3500 break;
3501 case KVM_IRQCHIP_IOAPIC:
eba0226b 3502 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3503 break;
3504 default:
3505 r = -EINVAL;
3506 break;
3507 }
3508 return r;
3509}
3510
3511static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3512{
3513 int r;
3514
3515 r = 0;
3516 switch (chip->chip_id) {
3517 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3518 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3519 memcpy(&pic_irqchip(kvm)->pics[0],
3520 &chip->chip.pic,
3521 sizeof(struct kvm_pic_state));
f4f51050 3522 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3523 break;
3524 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3525 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3526 memcpy(&pic_irqchip(kvm)->pics[1],
3527 &chip->chip.pic,
3528 sizeof(struct kvm_pic_state));
f4f51050 3529 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3530 break;
3531 case KVM_IRQCHIP_IOAPIC:
eba0226b 3532 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3533 break;
3534 default:
3535 r = -EINVAL;
3536 break;
3537 }
3538 kvm_pic_update_irq(pic_irqchip(kvm));
3539 return r;
3540}
3541
e0f63cb9
SY		 3542static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3543{
3544 int r = 0;
3545
894a9c55 3546 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3547 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3548 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3549 return r;
3550}
3551
3552static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3553{
3554 int r = 0;
3555
894a9c55 3556 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3557 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3558 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3559 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3560 return r;
3561}
3562
3563static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3564{
3565 int r = 0;
3566
3567 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3568 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3569 sizeof(ps->channels));
3570 ps->flags = kvm->arch.vpit->pit_state.flags;
3571 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3572 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3573 return r;
3574}
3575
3576static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3577{
3578 int r = 0, start = 0;
3579 u32 prev_legacy, cur_legacy;
3580 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3581 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3582 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3583 if (!prev_legacy && cur_legacy)
3584 start = 1;
3585 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3586 sizeof(kvm->arch.vpit->pit_state.channels));
3587 kvm->arch.vpit->pit_state.flags = ps->flags;
3588 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3589 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3590 return r;
3591}
3592
52d939a0
MT		 3593static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3594 struct kvm_reinject_control *control)
3595{
3596 if (!kvm->arch.vpit)
3597 return -ENXIO;
894a9c55 3598 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3599 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3600 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3601 return 0;
3602}
3603
95d4c16c 3604/**
60c34612
TY		 3605 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3606 * @kvm: kvm instance
3607 * @log: slot id and address to which we copy the log
95d4c16c 3608 *
60c34612
TY		 3609 * We need to keep it in mind that VCPU threads can write to the bitmap
3610 * concurrently. So, to avoid losing data, we keep the following order for
3611 * each bit:
95d4c16c 3612 *
60c34612
TY		 3613 * 1. Take a snapshot of the bit and clear it if needed.
3614 * 2. Write protect the corresponding page.
3615 * 3. Flush TLB's if needed.
3616 * 4. Copy the snapshot to the userspace.
95d4c16c 3617 *
60c34612
TY		 3618 * Between 2 and 3, the guest may write to the page using the remaining TLB
3619 * entry. This is not a problem because the page will be reported dirty at
3620 * step 4 using the snapshot taken before and step 3 ensures that successive
3621 * writes will be logged for the next call.
5bb064dc 3622 */
60c34612 3623int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3624{
7850ac54 3625 int r;
5bb064dc 3626 struct kvm_memory_slot *memslot;
60c34612
TY		 3627 unsigned long n, i;
3628 unsigned long *dirty_bitmap;
3629 unsigned long *dirty_bitmap_buffer;
3630 bool is_dirty = false;
5bb064dc 3631
79fac95e 3632 mutex_lock(&kvm->slots_lock);
5bb064dc 3633
b050b015 3634 r = -EINVAL;
bbacc0c1 3635 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3636 goto out;
3637
28a37544 3638 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3639
3640 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3641 r = -ENOENT;
60c34612 3642 if (!dirty_bitmap)
b050b015
MT		 3643 goto out;
3644
87bf6e7d 3645 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3646
60c34612
TY		 3647 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3648 memset(dirty_bitmap_buffer, 0, n);
b050b015 3649
60c34612 3650 spin_lock(&kvm->mmu_lock);
b050b015 3651
60c34612
TY		 3652 for (i = 0; i < n / sizeof(long); i++) {
3653 unsigned long mask;
3654 gfn_t offset;
cdfca7b3 3655
60c34612
TY		 3656 if (!dirty_bitmap[i])
3657 continue;
b050b015 3658
60c34612 3659 is_dirty = true;
914ebccd 3660
60c34612
TY		 3661 mask = xchg(&dirty_bitmap[i], 0);
3662 dirty_bitmap_buffer[i] = mask;
edde99ce 3663
60c34612
TY		 3664 offset = i * BITS_PER_LONG;
3665 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3666 }
60c34612
TY		 3667
3668 spin_unlock(&kvm->mmu_lock);
3669
198c74f4
XG		 3670 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3671 lockdep_assert_held(&kvm->slots_lock);
3672
3673 /*
3674 * All the TLBs can be flushed out of mmu lock, see the comments in
3675 * kvm_mmu_slot_remove_write_access().
3676 */
3677 if (is_dirty)
3678 kvm_flush_remote_tlbs(kvm);
3679
60c34612
TY		 3680 r = -EFAULT;
3681 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3682 goto out;
b050b015 3683
5bb064dc
ZX		 3684 r = 0;
3685out:
79fac95e 3686 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3687 return r;
3688}
3689
aa2fbe6d
YZ		 3690int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3691 bool line_status)
23d43cf9
CD		 3692{
3693 if (!irqchip_in_kernel(kvm))
3694 return -ENXIO;
3695
3696 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3697 irq_event->irq, irq_event->level,
3698 line_status);
23d43cf9
CD		 3699 return 0;
3700}
3701
1fe779f8
CO		 3702long kvm_arch_vm_ioctl(struct file *filp,
3703 unsigned int ioctl, unsigned long arg)
3704{
3705 struct kvm *kvm = filp->private_data;
3706 void __user *argp = (void __user *)arg;
367e1319 3707 int r = -ENOTTY;
f0d66275
DH		 3708 /*
3709 * This union makes it completely explicit to gcc-3.x
3710 * that these two variables' stack usage should be
3711 * combined, not added together.
3712 */
3713 union {
3714 struct kvm_pit_state ps;
e9f42757 3715 struct kvm_pit_state2 ps2;
c5ff41ce 3716 struct kvm_pit_config pit_config;
f0d66275 3717 } u;
1fe779f8
CO		 3718
3719 switch (ioctl) {
3720 case KVM_SET_TSS_ADDR:
3721 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3722 break;
b927a3ce
SY		 3723 case KVM_SET_IDENTITY_MAP_ADDR: {
3724 u64 ident_addr;
3725
3726 r = -EFAULT;
3727 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3728 goto out;
3729 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3730 break;
3731 }
1fe779f8
CO		 3732 case KVM_SET_NR_MMU_PAGES:
3733 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3734 break;
3735 case KVM_GET_NR_MMU_PAGES:
3736 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3737 break;
3ddea128
MT		 3738 case KVM_CREATE_IRQCHIP: {
3739 struct kvm_pic *vpic;
3740
3741 mutex_lock(&kvm->lock);
3742 r = -EEXIST;
3743 if (kvm->arch.vpic)
3744 goto create_irqchip_unlock;
3e515705
AK		 3745 r = -EINVAL;
3746 if (atomic_read(&kvm->online_vcpus))
3747 goto create_irqchip_unlock;
1fe779f8 3748 r = -ENOMEM;
3ddea128
MT		 3749 vpic = kvm_create_pic(kvm);
3750 if (vpic) {
1fe779f8
CO		 3751 r = kvm_ioapic_init(kvm);
3752 if (r) {
175504cd 3753 mutex_lock(&kvm->slots_lock);
72bb2fcd 3754 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3755 &vpic->dev_master);
3756 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3757 &vpic->dev_slave);
3758 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3759 &vpic->dev_eclr);
175504cd 3760 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3761 kfree(vpic);
3762 goto create_irqchip_unlock;
1fe779f8
CO		 3763 }
3764 } else
3ddea128
MT		 3765 goto create_irqchip_unlock;
3766 smp_wmb();
3767 kvm->arch.vpic = vpic;
3768 smp_wmb();
399ec807
AK		 3769 r = kvm_setup_default_irq_routing(kvm);
3770 if (r) {
175504cd 3771 mutex_lock(&kvm->slots_lock);
3ddea128 3772 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3773 kvm_ioapic_destroy(kvm);
3774 kvm_destroy_pic(kvm);
3ddea128 3775 mutex_unlock(&kvm->irq_lock);
175504cd 3776 mutex_unlock(&kvm->slots_lock);
399ec807 3777 }
3ddea128
MT		 3778 create_irqchip_unlock:
3779 mutex_unlock(&kvm->lock);
1fe779f8 3780 break;
3ddea128 3781 }
7837699f 3782 case KVM_CREATE_PIT:
c5ff41ce
JK		 3783 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3784 goto create_pit;
3785 case KVM_CREATE_PIT2:
3786 r = -EFAULT;
3787 if (copy_from_user(&u.pit_config, argp,
3788 sizeof(struct kvm_pit_config)))
3789 goto out;
3790 create_pit:
79fac95e 3791 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3792 r = -EEXIST;
3793 if (kvm->arch.vpit)
3794 goto create_pit_unlock;
7837699f 3795 r = -ENOMEM;
c5ff41ce 3796 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3797 if (kvm->arch.vpit)
3798 r = 0;
269e05e4 3799 create_pit_unlock:
79fac95e 3800 mutex_unlock(&kvm->slots_lock);
7837699f 3801 break;
1fe779f8
CO		 3802 case KVM_GET_IRQCHIP: {
3803 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3804 struct kvm_irqchip *chip;
1fe779f8 3805
ff5c2c03
SL		 3806 chip = memdup_user(argp, sizeof(*chip));
3807 if (IS_ERR(chip)) {
3808 r = PTR_ERR(chip);
1fe779f8 3809 goto out;
ff5c2c03
SL		 3810 }
3811
1fe779f8
CO		 3812 r = -ENXIO;
3813 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3814 goto get_irqchip_out;
3815 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3816 if (r)
f0d66275 3817 goto get_irqchip_out;
1fe779f8 3818 r = -EFAULT;
f0d66275
DH		 3819 if (copy_to_user(argp, chip, sizeof *chip))
3820 goto get_irqchip_out;
1fe779f8 3821 r = 0;
f0d66275
DH		 3822 get_irqchip_out:
3823 kfree(chip);
1fe779f8
CO		 3824 break;
3825 }
3826 case KVM_SET_IRQCHIP: {
3827 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3828 struct kvm_irqchip *chip;
1fe779f8 3829
ff5c2c03
SL		 3830 chip = memdup_user(argp, sizeof(*chip));
3831 if (IS_ERR(chip)) {
3832 r = PTR_ERR(chip);
1fe779f8 3833 goto out;
ff5c2c03
SL		 3834 }
3835
1fe779f8
CO		 3836 r = -ENXIO;
3837 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3838 goto set_irqchip_out;
3839 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3840 if (r)
f0d66275 3841 goto set_irqchip_out;
1fe779f8 3842 r = 0;
f0d66275
DH		 3843 set_irqchip_out:
3844 kfree(chip);
1fe779f8
CO		 3845 break;
3846 }
e0f63cb9 3847 case KVM_GET_PIT: {
e0f63cb9 3848 r = -EFAULT;
f0d66275 3849 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3850 goto out;
3851 r = -ENXIO;
3852 if (!kvm->arch.vpit)
3853 goto out;
f0d66275 3854 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3855 if (r)
3856 goto out;
3857 r = -EFAULT;
f0d66275 3858 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3859 goto out;
3860 r = 0;
3861 break;
3862 }
3863 case KVM_SET_PIT: {
e0f63cb9 3864 r = -EFAULT;
f0d66275 3865 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3866 goto out;
3867 r = -ENXIO;
3868 if (!kvm->arch.vpit)
3869 goto out;
f0d66275 3870 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3871 break;
3872 }
e9f42757
BK		 3873 case KVM_GET_PIT2: {
3874 r = -ENXIO;
3875 if (!kvm->arch.vpit)
3876 goto out;
3877 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3878 if (r)
3879 goto out;
3880 r = -EFAULT;
3881 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3882 goto out;
3883 r = 0;
3884 break;
3885 }
3886 case KVM_SET_PIT2: {
3887 r = -EFAULT;
3888 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3889 goto out;
3890 r = -ENXIO;
3891 if (!kvm->arch.vpit)
3892 goto out;
3893 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3894 break;
3895 }
52d939a0
MT		 3896 case KVM_REINJECT_CONTROL: {
3897 struct kvm_reinject_control control;
3898 r = -EFAULT;
3899 if (copy_from_user(&control, argp, sizeof(control)))
3900 goto out;
3901 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3902 break;
3903 }
ffde22ac
ES		 3904 case KVM_XEN_HVM_CONFIG: {
3905 r = -EFAULT;
3906 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3907 sizeof(struct kvm_xen_hvm_config)))
3908 goto out;
3909 r = -EINVAL;
3910 if (kvm->arch.xen_hvm_config.flags)
3911 goto out;
3912 r = 0;
3913 break;
3914 }
afbcf7ab 3915 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3916 struct kvm_clock_data user_ns;
3917 u64 now_ns;
3918 s64 delta;
3919
3920 r = -EFAULT;
3921 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3922 goto out;
3923
3924 r = -EINVAL;
3925 if (user_ns.flags)
3926 goto out;
3927
3928 r = 0;
395c6b0a 3929 local_irq_disable();
759379dd 3930 now_ns = get_kernel_ns();
afbcf7ab 3931 delta = user_ns.clock - now_ns;
395c6b0a 3932 local_irq_enable();
afbcf7ab 3933 kvm->arch.kvmclock_offset = delta;
2e762ff7 3934 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3935 break;
3936 }
3937 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3938 struct kvm_clock_data user_ns;
3939 u64 now_ns;
3940
395c6b0a 3941 local_irq_disable();
759379dd 3942 now_ns = get_kernel_ns();
afbcf7ab 3943 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3944 local_irq_enable();
afbcf7ab 3945 user_ns.flags = 0;
97e69aa6 3946 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3947
3948 r = -EFAULT;
3949 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3950 goto out;
3951 r = 0;
3952 break;
3953 }
3954
1fe779f8
CO		 3955 default:
3956 ;
3957 }
3958out:
3959 return r;
3960}
3961
a16b043c 3962static void kvm_init_msr_list(void)
043405e1
CO		 3963{
3964 u32 dummy[2];
3965 unsigned i, j;
3966
e3267cbb
GC		 3967 /* skip the first msrs in the list. KVM-specific */
3968 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3969 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3970 continue;
93c4adc7
PB		 3971
3972 /*
3973 * Even MSRs that are valid in the host may not be exposed
3974 * to the guests in some cases. We could work around this
3975 * in VMX with the generic MSR save/load machinery, but it
3976 * is not really worthwhile since it will really only
3977 * happen with nested virtualization.
3978 */
3979 switch (msrs_to_save[i]) {
3980 case MSR_IA32_BNDCFGS:
3981 if (!kvm_x86_ops->mpx_supported())
3982 continue;
3983 break;
3984 default:
3985 break;
3986 }
3987
043405e1
CO		 3988 if (j < i)
3989 msrs_to_save[j] = msrs_to_save[i];
3990 j++;
3991 }
3992 num_msrs_to_save = j;
3993}
3994
bda9020e
MT		 3995static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3996 const void *v)
bbd9b64e 3997{
70252a10
AK		 3998 int handled = 0;
3999 int n;
4000
4001 do {
4002 n = min(len, 8);
4003 if (!(vcpu->arch.apic &&
4004 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4005 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4006 break;
4007 handled += n;
4008 addr += n;
4009 len -= n;
4010 v += n;
4011 } while (len);
bbd9b64e 4012
70252a10 4013 return handled;
bbd9b64e
CO		 4014}
4015
bda9020e 4016static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4017{
70252a10
AK		 4018 int handled = 0;
4019 int n;
4020
4021 do {
4022 n = min(len, 8);
4023 if (!(vcpu->arch.apic &&
4024 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4025 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4026 break;
4027 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4028 handled += n;
4029 addr += n;
4030 len -= n;
4031 v += n;
4032 } while (len);
bbd9b64e 4033
70252a10 4034 return handled;
bbd9b64e
CO		 4035}
4036
2dafc6c2
GN		 4037static void kvm_set_segment(struct kvm_vcpu *vcpu,
4038 struct kvm_segment *var, int seg)
4039{
4040 kvm_x86_ops->set_segment(vcpu, var, seg);
4041}
4042
4043void kvm_get_segment(struct kvm_vcpu *vcpu,
4044 struct kvm_segment *var, int seg)
4045{
4046 kvm_x86_ops->get_segment(vcpu, var, seg);
4047}
4048
e459e322 4049gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4050{
4051 gpa_t t_gpa;
ab9ae313 4052 struct x86_exception exception;
02f59dc9
JR		 4053
4054 BUG_ON(!mmu_is_nested(vcpu));
4055
4056 /* NPT walks are always user-walks */
4057 access |= PFERR_USER_MASK;
ab9ae313 4058 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4059
4060 return t_gpa;
4061}
4062
ab9ae313
AK		 4063gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4064 struct x86_exception *exception)
1871c602
GN		 4065{
4066 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4067 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4068}
4069
ab9ae313
AK		 4070 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4071 struct x86_exception *exception)
1871c602
GN		 4072{
4073 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4074 access |= PFERR_FETCH_MASK;
ab9ae313 4075 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4076}
4077
ab9ae313
AK		 4078gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4079 struct x86_exception *exception)
1871c602
GN		 4080{
4081 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4082 access |= PFERR_WRITE_MASK;
ab9ae313 4083 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4084}
4085
4086/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4087gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4088 struct x86_exception *exception)
1871c602 4089{
ab9ae313 4090 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4091}
4092
4093static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4094 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4095 struct x86_exception *exception)
bbd9b64e
CO		 4096{
4097 void *data = val;
10589a46 4098 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4099
4100 while (bytes) {
14dfe855 4101 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4102 exception);
bbd9b64e 4103 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4104 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4105 int ret;
4106
bcc55cba 4107 if (gpa == UNMAPPED_GVA)
ab9ae313 4108 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4109 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4110 offset, toread);
10589a46 4111 if (ret < 0) {
c3cd7ffa 4112 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4113 goto out;
4114 }
bbd9b64e 4115
77c2002e
IE		 4116 bytes -= toread;
4117 data += toread;
4118 addr += toread;
bbd9b64e 4119 }
10589a46 4120out:
10589a46 4121 return r;
bbd9b64e 4122}
77c2002e 4123
1871c602 4124/* used for instruction fetching */
0f65dd70
AK		 4125static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4126 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4127 struct x86_exception *exception)
1871c602 4128{
0f65dd70 4129 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4130 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4131 unsigned offset;
4132 int ret;
0f65dd70 4133
44583cba
PB		 4134 /* Inline kvm_read_guest_virt_helper for speed. */
4135 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4136 exception);
4137 if (unlikely(gpa == UNMAPPED_GVA))
4138 return X86EMUL_PROPAGATE_FAULT;
4139
4140 offset = addr & (PAGE_SIZE-1);
4141 if (WARN_ON(offset + bytes > PAGE_SIZE))
4142 bytes = (unsigned)PAGE_SIZE - offset;
4143 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4144 offset, bytes);
4145 if (unlikely(ret < 0))
4146 return X86EMUL_IO_NEEDED;
4147
4148 return X86EMUL_CONTINUE;
1871c602
GN		 4149}
4150
064aea77 4151int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4152 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4153 struct x86_exception *exception)
1871c602 4154{
0f65dd70 4155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4156 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4157
1871c602 4158 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4159 exception);
1871c602 4160}
064aea77 4161EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4162
0f65dd70
AK		 4163static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4164 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4165 struct x86_exception *exception)
1871c602 4166{
0f65dd70 4167 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4168 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4169}
4170
6a4d7550 4171int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4172 gva_t addr, void *val,
2dafc6c2 4173 unsigned int bytes,
bcc55cba 4174 struct x86_exception *exception)
77c2002e 4175{
0f65dd70 4176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4177 void *data = val;
4178 int r = X86EMUL_CONTINUE;
4179
4180 while (bytes) {
14dfe855
JR		 4181 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4182 PFERR_WRITE_MASK,
ab9ae313 4183 exception);
77c2002e
IE		 4184 unsigned offset = addr & (PAGE_SIZE-1);
4185 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4186 int ret;
4187
bcc55cba 4188 if (gpa == UNMAPPED_GVA)
ab9ae313 4189 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4190 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4191 if (ret < 0) {
c3cd7ffa 4192 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4193 goto out;
4194 }
4195
4196 bytes -= towrite;
4197 data += towrite;
4198 addr += towrite;
4199 }
4200out:
4201 return r;
4202}
6a4d7550 4203EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4204
af7cc7d1
XG		 4205static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4206 gpa_t *gpa, struct x86_exception *exception,
4207 bool write)
4208{
97d64b78
AK		 4209 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4210 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4211
97d64b78 4212 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4213 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4214 vcpu->arch.access, access)) {
bebb106a
XG		 4215 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4216 (gva & (PAGE_SIZE - 1));
4f022648 4217 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4218 return 1;
4219 }
4220
af7cc7d1
XG		 4221 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4222
4223 if (*gpa == UNMAPPED_GVA)
4224 return -1;
4225
4226 /* For APIC access vmexit */
4227 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4228 return 1;
4229
4f022648
XG		 4230 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4231 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4232 return 1;
4f022648 4233 }
bebb106a 4234
af7cc7d1
XG		 4235 return 0;
4236}
4237
3200f405 4238int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4239 const void *val, int bytes)
bbd9b64e
CO		 4240{
4241 int ret;
4242
4243 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4244 if (ret < 0)
bbd9b64e 4245 return 0;
f57f2ef5 4246 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4247 return 1;
4248}
4249
77d197b2
XG		 4250struct read_write_emulator_ops {
4251 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4252 int bytes);
4253 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4254 void *val, int bytes);
4255 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4256 int bytes, void *val);
4257 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4258 void *val, int bytes);
4259 bool write;
4260};
4261
4262static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4263{
4264 if (vcpu->mmio_read_completed) {
77d197b2 4265 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4266 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4267 vcpu->mmio_read_completed = 0;
4268 return 1;
4269 }
4270
4271 return 0;
4272}
4273
4274static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4275 void *val, int bytes)
4276{
4277 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4278}
4279
4280static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4281 void *val, int bytes)
4282{
4283 return emulator_write_phys(vcpu, gpa, val, bytes);
4284}
4285
4286static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4287{
4288 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4289 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4290}
4291
4292static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4293 void *val, int bytes)
4294{
4295 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4296 return X86EMUL_IO_NEEDED;
4297}
4298
4299static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4300 void *val, int bytes)
4301{
f78146b0
AK		 4302 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4303
87da7e66 4304 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4305 return X86EMUL_CONTINUE;
4306}
4307
0fbe9b0b 4308static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4309 .read_write_prepare = read_prepare,
4310 .read_write_emulate = read_emulate,
4311 .read_write_mmio = vcpu_mmio_read,
4312 .read_write_exit_mmio = read_exit_mmio,
4313};
4314
0fbe9b0b 4315static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4316 .read_write_emulate = write_emulate,
4317 .read_write_mmio = write_mmio,
4318 .read_write_exit_mmio = write_exit_mmio,
4319 .write = true,
4320};
4321
22388a3c
XG		 4322static int emulator_read_write_onepage(unsigned long addr, void *val,
4323 unsigned int bytes,
4324 struct x86_exception *exception,
4325 struct kvm_vcpu *vcpu,
0fbe9b0b 4326 const struct read_write_emulator_ops *ops)
bbd9b64e 4327{
af7cc7d1
XG		 4328 gpa_t gpa;
4329 int handled, ret;
22388a3c 4330 bool write = ops->write;
f78146b0 4331 struct kvm_mmio_fragment *frag;
10589a46 4332
22388a3c 4333 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4334
af7cc7d1 4335 if (ret < 0)
bbd9b64e 4336 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4337
4338 /* For APIC access vmexit */
af7cc7d1 4339 if (ret)
bbd9b64e
CO		 4340 goto mmio;
4341
22388a3c 4342 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4343 return X86EMUL_CONTINUE;
4344
4345mmio:
4346 /*
4347 * Is this MMIO handled locally?
4348 */
22388a3c 4349 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4350 if (handled == bytes)
bbd9b64e 4351 return X86EMUL_CONTINUE;
bbd9b64e 4352
70252a10
AK		 4353 gpa += handled;
4354 bytes -= handled;
4355 val += handled;
4356
87da7e66
XG		 4357 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4358 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4359 frag->gpa = gpa;
4360 frag->data = val;
4361 frag->len = bytes;
f78146b0 4362 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4363}
4364
22388a3c
XG		 4365int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4366 void *val, unsigned int bytes,
4367 struct x86_exception *exception,
0fbe9b0b 4368 const struct read_write_emulator_ops *ops)
bbd9b64e 4369{
0f65dd70 4370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4371 gpa_t gpa;
4372 int rc;
4373
4374 if (ops->read_write_prepare &&
4375 ops->read_write_prepare(vcpu, val, bytes))
4376 return X86EMUL_CONTINUE;
4377
4378 vcpu->mmio_nr_fragments = 0;
0f65dd70 4379
bbd9b64e
CO		 4380 /* Crossing a page boundary? */
4381 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4382 int now;
bbd9b64e
CO		 4383
4384 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4385 rc = emulator_read_write_onepage(addr, val, now, exception,
4386 vcpu, ops);
4387
bbd9b64e
CO		 4388 if (rc != X86EMUL_CONTINUE)
4389 return rc;
4390 addr += now;
4391 val += now;
4392 bytes -= now;
4393 }
22388a3c 4394
f78146b0
AK		 4395 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4396 vcpu, ops);
4397 if (rc != X86EMUL_CONTINUE)
4398 return rc;
4399
4400 if (!vcpu->mmio_nr_fragments)
4401 return rc;
4402
4403 gpa = vcpu->mmio_fragments[0].gpa;
4404
4405 vcpu->mmio_needed = 1;
4406 vcpu->mmio_cur_fragment = 0;
4407
87da7e66 4408 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4409 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4410 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4411 vcpu->run->mmio.phys_addr = gpa;
4412
4413 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4414}
4415
4416static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4417 unsigned long addr,
4418 void *val,
4419 unsigned int bytes,
4420 struct x86_exception *exception)
4421{
4422 return emulator_read_write(ctxt, addr, val, bytes,
4423 exception, &read_emultor);
4424}
4425
4426int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4427 unsigned long addr,
4428 const void *val,
4429 unsigned int bytes,
4430 struct x86_exception *exception)
4431{
4432 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4433 exception, &write_emultor);
bbd9b64e 4434}
bbd9b64e 4435
daea3e73
AK		 4436#define CMPXCHG_TYPE(t, ptr, old, new) \
4437 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4438
4439#ifdef CONFIG_X86_64
4440# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4441#else
4442# define CMPXCHG64(ptr, old, new) \
9749a6c0 4443 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4444#endif
4445
0f65dd70
AK		 4446static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4447 unsigned long addr,
bbd9b64e
CO		 4448 const void *old,
4449 const void *new,
4450 unsigned int bytes,
0f65dd70 4451 struct x86_exception *exception)
bbd9b64e 4452{
0f65dd70 4453 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4454 gpa_t gpa;
4455 struct page *page;
4456 char *kaddr;
4457 bool exchanged;
2bacc55c 4458
daea3e73
AK		 4459 /* guests cmpxchg8b have to be emulated atomically */
4460 if (bytes > 8 || (bytes & (bytes - 1)))
4461 goto emul_write;
10589a46 4462
daea3e73 4463 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4464
daea3e73
AK		 4465 if (gpa == UNMAPPED_GVA ||
4466 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4467 goto emul_write;
2bacc55c 4468
daea3e73
AK		 4469 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4470 goto emul_write;
72dc67a6 4471
daea3e73 4472 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4473 if (is_error_page(page))
c19b8bd6 4474 goto emul_write;
72dc67a6 4475
8fd75e12 4476 kaddr = kmap_atomic(page);
daea3e73
AK		 4477 kaddr += offset_in_page(gpa);
4478 switch (bytes) {
4479 case 1:
4480 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4481 break;
4482 case 2:
4483 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4484 break;
4485 case 4:
4486 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4487 break;
4488 case 8:
4489 exchanged = CMPXCHG64(kaddr, old, new);
4490 break;
4491 default:
4492 BUG();
2bacc55c 4493 }
8fd75e12 4494 kunmap_atomic(kaddr);
daea3e73
AK		 4495 kvm_release_page_dirty(page);
4496
4497 if (!exchanged)
4498 return X86EMUL_CMPXCHG_FAILED;
4499
d3714010 4500 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4501 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4502
4503 return X86EMUL_CONTINUE;
4a5f48f6 4504
3200f405 4505emul_write:
daea3e73 4506 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4507
0f65dd70 4508 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4509}
4510
cf8f70bf
GN		 4511static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4512{
4513 /* TODO: String I/O for in kernel device */
4514 int r;
4515
4516 if (vcpu->arch.pio.in)
4517 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4518 vcpu->arch.pio.size, pd);
4519 else
4520 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4521 vcpu->arch.pio.port, vcpu->arch.pio.size,
4522 pd);
4523 return r;
4524}
4525
6f6fbe98
XG		 4526static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4527 unsigned short port, void *val,
4528 unsigned int count, bool in)
cf8f70bf 4529{
cf8f70bf 4530 vcpu->arch.pio.port = port;
6f6fbe98 4531 vcpu->arch.pio.in = in;
7972995b 4532 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4533 vcpu->arch.pio.size = size;
4534
4535 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4536 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4537 return 1;
4538 }
4539
4540 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4541 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4542 vcpu->run->io.size = size;
4543 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4544 vcpu->run->io.count = count;
4545 vcpu->run->io.port = port;
4546
4547 return 0;
4548}
4549
6f6fbe98
XG		 4550static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4551 int size, unsigned short port, void *val,
4552 unsigned int count)
cf8f70bf 4553{
ca1d4a9e 4554 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4555 int ret;
ca1d4a9e 4556
6f6fbe98
XG		 4557 if (vcpu->arch.pio.count)
4558 goto data_avail;
cf8f70bf 4559
6f6fbe98
XG		 4560 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4561 if (ret) {
4562data_avail:
4563 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4564 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4565 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4566 return 1;
4567 }
4568
cf8f70bf
GN		 4569 return 0;
4570}
4571
6f6fbe98
XG		 4572static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4573 int size, unsigned short port,
4574 const void *val, unsigned int count)
4575{
4576 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4577
4578 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4579 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4580 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4581}
4582
bbd9b64e
CO		 4583static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4584{
4585 return kvm_x86_ops->get_segment_base(vcpu, seg);
4586}
4587
3cb16fe7 4588static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4589{
3cb16fe7 4590 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4591}
4592
f5f48ee1
SY		 4593int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4594{
4595 if (!need_emulate_wbinvd(vcpu))
4596 return X86EMUL_CONTINUE;
4597
4598 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4599 int cpu = get_cpu();
4600
4601 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4602 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4603 wbinvd_ipi, NULL, 1);
2eec7343 4604 put_cpu();
f5f48ee1 4605 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4606 } else
4607 wbinvd();
f5f48ee1
SY		 4608 return X86EMUL_CONTINUE;
4609}
4610EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4611
bcaf5cc5
AK		 4612static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4613{
4614 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4615}
4616
717746e3 4617int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4618{
717746e3 4619 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4620}
4621
717746e3 4622int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4623{
338dbc97 4624
717746e3 4625 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4626}
4627
52a46617 4628static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4629{
52a46617 4630 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4631}
4632
717746e3 4633static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4634{
717746e3 4635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4636 unsigned long value;
4637
4638 switch (cr) {
4639 case 0:
4640 value = kvm_read_cr0(vcpu);
4641 break;
4642 case 2:
4643 value = vcpu->arch.cr2;
4644 break;
4645 case 3:
9f8fe504 4646 value = kvm_read_cr3(vcpu);
52a46617
GN		 4647 break;
4648 case 4:
4649 value = kvm_read_cr4(vcpu);
4650 break;
4651 case 8:
4652 value = kvm_get_cr8(vcpu);
4653 break;
4654 default:
a737f256 4655 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4656 return 0;
4657 }
4658
4659 return value;
4660}
4661
717746e3 4662static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4663{
717746e3 4664 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4665 int res = 0;
4666
52a46617
GN		 4667 switch (cr) {
4668 case 0:
49a9b07e 4669 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4670 break;
4671 case 2:
4672 vcpu->arch.cr2 = val;
4673 break;
4674 case 3:
2390218b 4675 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4676 break;
4677 case 4:
a83b29c6 4678 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4679 break;
4680 case 8:
eea1cff9 4681 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4682 break;
4683 default:
a737f256 4684 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4685 res = -1;
52a46617 4686 }
0f12244f
GN		 4687
4688 return res;
52a46617
GN		 4689}
4690
717746e3 4691static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4692{
717746e3 4693 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4694}
4695
4bff1e86 4696static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4697{
4bff1e86 4698 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4699}
4700
4bff1e86 4701static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4702{
4bff1e86 4703 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4704}
4705
1ac9d0cf
AK		 4706static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4707{
4708 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4709}
4710
4711static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4712{
4713 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4714}
4715
4bff1e86
AK		 4716static unsigned long emulator_get_cached_segment_base(
4717 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4718{
4bff1e86 4719 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4720}
4721
1aa36616
AK		 4722static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4723 struct desc_struct *desc, u32 *base3,
4724 int seg)
2dafc6c2
GN		 4725{
4726 struct kvm_segment var;
4727
4bff1e86 4728 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4729 *selector = var.selector;
2dafc6c2 4730
378a8b09
GN		 4731 if (var.unusable) {
4732 memset(desc, 0, sizeof(*desc));
2dafc6c2 4733 return false;
378a8b09 4734 }
2dafc6c2
GN		 4735
4736 if (var.g)
4737 var.limit >>= 12;
4738 set_desc_limit(desc, var.limit);
4739 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4740#ifdef CONFIG_X86_64
4741 if (base3)
4742 *base3 = var.base >> 32;
4743#endif
2dafc6c2
GN		 4744 desc->type = var.type;
4745 desc->s = var.s;
4746 desc->dpl = var.dpl;
4747 desc->p = var.present;
4748 desc->avl = var.avl;
4749 desc->l = var.l;
4750 desc->d = var.db;
4751 desc->g = var.g;
4752
4753 return true;
4754}
4755
1aa36616
AK		 4756static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4757 struct desc_struct *desc, u32 base3,
4758 int seg)
2dafc6c2 4759{
4bff1e86 4760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4761 struct kvm_segment var;
4762
1aa36616 4763 var.selector = selector;
2dafc6c2 4764 var.base = get_desc_base(desc);
5601d05b
GN		 4765#ifdef CONFIG_X86_64
4766 var.base |= ((u64)base3) << 32;
4767#endif
2dafc6c2
GN		 4768 var.limit = get_desc_limit(desc);
4769 if (desc->g)
4770 var.limit = (var.limit << 12) | 0xfff;
4771 var.type = desc->type;
2dafc6c2
GN		 4772 var.dpl = desc->dpl;
4773 var.db = desc->d;
4774 var.s = desc->s;
4775 var.l = desc->l;
4776 var.g = desc->g;
4777 var.avl = desc->avl;
4778 var.present = desc->p;
4779 var.unusable = !var.present;
4780 var.padding = 0;
4781
4782 kvm_set_segment(vcpu, &var, seg);
4783 return;
4784}
4785
717746e3
AK		 4786static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4787 u32 msr_index, u64 *pdata)
4788{
4789 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4790}
4791
4792static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4793 u32 msr_index, u64 data)
4794{
8fe8ab46
WA		 4795 struct msr_data msr;
4796
4797 msr.data = data;
4798 msr.index = msr_index;
4799 msr.host_initiated = false;
4800 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4801}
4802
67f4d428
NA		 4803static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4804 u32 pmc)
4805{
4806 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4807}
4808
222d21aa
AK		 4809static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4810 u32 pmc, u64 *pdata)
4811{
4812 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4813}
4814
6c3287f7
AK		 4815static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4816{
4817 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4818}
4819
5037f6f3
AK		 4820static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4821{
4822 preempt_disable();
5197b808 4823 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4824 /*
4825 * CR0.TS may reference the host fpu state, not the guest fpu state,
4826 * so it may be clear at this point.
4827 */
4828 clts();
4829}
4830
4831static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4832{
4833 preempt_enable();
4834}
4835
2953538e 4836static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4837 struct x86_instruction_info *info,
c4f035c6
AK		 4838 enum x86_intercept_stage stage)
4839{
2953538e 4840 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4841}
4842
0017f93a 4843static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4844 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4845{
0017f93a 4846 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4847}
4848
dd856efa
AK		 4849static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4850{
4851 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4852}
4853
4854static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4855{
4856 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4857}
4858
0225fb50 4859static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4860 .read_gpr = emulator_read_gpr,
4861 .write_gpr = emulator_write_gpr,
1871c602 4862 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4863 .write_std = kvm_write_guest_virt_system,
1871c602 4864 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4865 .read_emulated = emulator_read_emulated,
4866 .write_emulated = emulator_write_emulated,
4867 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4868 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4869 .pio_in_emulated = emulator_pio_in_emulated,
4870 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4871 .get_segment = emulator_get_segment,
4872 .set_segment = emulator_set_segment,
5951c442 4873 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4874 .get_gdt = emulator_get_gdt,
160ce1f1 4875 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4876 .set_gdt = emulator_set_gdt,
4877 .set_idt = emulator_set_idt,
52a46617
GN		 4878 .get_cr = emulator_get_cr,
4879 .set_cr = emulator_set_cr,
9c537244 4880 .cpl = emulator_get_cpl,
35aa5375
GN		 4881 .get_dr = emulator_get_dr,
4882 .set_dr = emulator_set_dr,
717746e3
AK		 4883 .set_msr = emulator_set_msr,
4884 .get_msr = emulator_get_msr,
67f4d428 4885 .check_pmc = emulator_check_pmc,
222d21aa 4886 .read_pmc = emulator_read_pmc,
6c3287f7 4887 .halt = emulator_halt,
bcaf5cc5 4888 .wbinvd = emulator_wbinvd,
d6aa1000 4889 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4890 .get_fpu = emulator_get_fpu,
4891 .put_fpu = emulator_put_fpu,
c4f035c6 4892 .intercept = emulator_intercept,
bdb42f5a 4893 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4894};
4895
95cb2295
GN		 4896static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4897{
37ccdcbe 4898 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4899 /*
4900 * an sti; sti; sequence only disable interrupts for the first
4901 * instruction. So, if the last instruction, be it emulated or
4902 * not, left the system with the INT_STI flag enabled, it
4903 * means that the last instruction is an sti. We should not
4904 * leave the flag on in this case. The same goes for mov ss
4905 */
37ccdcbe
PB		 4906 if (int_shadow & mask)
4907 mask = 0;
6addfc42 4908 if (unlikely(int_shadow || mask)) {
95cb2295 4909 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4910 if (!mask)
4911 kvm_make_request(KVM_REQ_EVENT, vcpu);
4912 }
95cb2295
GN		 4913}
4914
54b8486f
GN		 4915static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4916{
4917 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4918 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4919 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4920 else if (ctxt->exception.error_code_valid)
4921 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4922 ctxt->exception.error_code);
54b8486f 4923 else
da9cb575 4924 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4925}
4926
8ec4722d
MG		 4927static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4928{
adf52235 4929 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4930 int cs_db, cs_l;
4931
8ec4722d
MG		 4932 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4933
adf52235
TY		 4934 ctxt->eflags = kvm_get_rflags(vcpu);
4935 ctxt->eip = kvm_rip_read(vcpu);
4936 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4937 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4938 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4939 cs_db ? X86EMUL_MODE_PROT32 :
4940 X86EMUL_MODE_PROT16;
4941 ctxt->guest_mode = is_guest_mode(vcpu);
4942
dd856efa 4943 init_decode_cache(ctxt);
7ae441ea 4944 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4945}
4946
71f9833b 4947int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4948{
9d74191a 4949 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4950 int ret;
4951
4952 init_emulate_ctxt(vcpu);
4953
9dac77fa
AK		 4954 ctxt->op_bytes = 2;
4955 ctxt->ad_bytes = 2;
4956 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4957 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4958
4959 if (ret != X86EMUL_CONTINUE)
4960 return EMULATE_FAIL;
4961
9dac77fa 4962 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4963 kvm_rip_write(vcpu, ctxt->eip);
4964 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4965
4966 if (irq == NMI_VECTOR)
7460fb4a 4967 vcpu->arch.nmi_pending = 0;
63995653
MG		 4968 else
4969 vcpu->arch.interrupt.pending = false;
4970
4971 return EMULATE_DONE;
4972}
4973EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4974
6d77dbfc
GN		 4975static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4976{
fc3a9157
JR		 4977 int r = EMULATE_DONE;
4978
6d77dbfc
GN		 4979 ++vcpu->stat.insn_emulation_fail;
4980 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4981 if (!is_guest_mode(vcpu)) {
4982 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4983 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4984 vcpu->run->internal.ndata = 0;
4985 r = EMULATE_FAIL;
4986 }
6d77dbfc 4987 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4988
4989 return r;
6d77dbfc
GN		 4990}
4991
93c05d3e 4992static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4993 bool write_fault_to_shadow_pgtable,
4994 int emulation_type)
a6f177ef 4995{
95b3cf69 4996 gpa_t gpa = cr2;
8e3d9d06 4997 pfn_t pfn;
a6f177ef 4998
991eebf9
GN		 4999 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5000 return false;
5001
95b3cf69
XG		 5002 if (!vcpu->arch.mmu.direct_map) {
5003 /*
5004 * Write permission should be allowed since only
5005 * write access need to be emulated.
5006 */
5007 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5008
95b3cf69
XG		 5009 /*
5010 * If the mapping is invalid in guest, let cpu retry
5011 * it to generate fault.
5012 */
5013 if (gpa == UNMAPPED_GVA)
5014 return true;
5015 }
a6f177ef 5016
8e3d9d06
XG		 5017 /*
5018 * Do not retry the unhandleable instruction if it faults on the
5019 * readonly host memory, otherwise it will goto a infinite loop:
5020 * retry instruction -> write #PF -> emulation fail -> retry
5021 * instruction -> ...
5022 */
5023 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5024
5025 /*
5026 * If the instruction failed on the error pfn, it can not be fixed,
5027 * report the error to userspace.
5028 */
5029 if (is_error_noslot_pfn(pfn))
5030 return false;
5031
5032 kvm_release_pfn_clean(pfn);
5033
5034 /* The instructions are well-emulated on direct mmu. */
5035 if (vcpu->arch.mmu.direct_map) {
5036 unsigned int indirect_shadow_pages;
5037
5038 spin_lock(&vcpu->kvm->mmu_lock);
5039 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5040 spin_unlock(&vcpu->kvm->mmu_lock);
5041
5042 if (indirect_shadow_pages)
5043 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5044
a6f177ef 5045 return true;
8e3d9d06 5046 }
a6f177ef 5047
95b3cf69
XG		 5048 /*
5049 * if emulation was due to access to shadowed page table
5050 * and it failed try to unshadow page and re-enter the
5051 * guest to let CPU execute the instruction.
5052 */
5053 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5054
5055 /*
5056 * If the access faults on its page table, it can not
5057 * be fixed by unprotecting shadow page and it should
5058 * be reported to userspace.
5059 */
5060 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5061}
5062
1cb3f3ae
XG		 5063static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5064 unsigned long cr2, int emulation_type)
5065{
5066 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5067 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5068
5069 last_retry_eip = vcpu->arch.last_retry_eip;
5070 last_retry_addr = vcpu->arch.last_retry_addr;
5071
5072 /*
5073 * If the emulation is caused by #PF and it is non-page_table
5074 * writing instruction, it means the VM-EXIT is caused by shadow
5075 * page protected, we can zap the shadow page and retry this
5076 * instruction directly.
5077 *
5078 * Note: if the guest uses a non-page-table modifying instruction
5079 * on the PDE that points to the instruction, then we will unmap
5080 * the instruction and go to an infinite loop. So, we cache the
5081 * last retried eip and the last fault address, if we meet the eip
5082 * and the address again, we can break out of the potential infinite
5083 * loop.
5084 */
5085 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5086
5087 if (!(emulation_type & EMULTYPE_RETRY))
5088 return false;
5089
5090 if (x86_page_table_writing_insn(ctxt))
5091 return false;
5092
5093 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5094 return false;
5095
5096 vcpu->arch.last_retry_eip = ctxt->eip;
5097 vcpu->arch.last_retry_addr = cr2;
5098
5099 if (!vcpu->arch.mmu.direct_map)
5100 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5101
22368028 5102 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5103
5104 return true;
5105}
5106
716d51ab
GN		 5107static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5108static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5109
4a1e10d5
PB		 5110static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5111 unsigned long *db)
5112{
5113 u32 dr6 = 0;
5114 int i;
5115 u32 enable, rwlen;
5116
5117 enable = dr7;
5118 rwlen = dr7 >> 16;
5119 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5120 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5121 dr6 |= (1 << i);
5122 return dr6;
5123}
5124
6addfc42 5125static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5126{
5127 struct kvm_run *kvm_run = vcpu->run;
5128
5129 /*
6addfc42
PB		 5130 * rflags is the old, "raw" value of the flags. The new value has
5131 * not been saved yet.
663f4c61
PB		 5132 *
5133 * This is correct even for TF set by the guest, because "the
5134 * processor will not generate this exception after the instruction
5135 * that sets the TF flag".
5136 */
663f4c61
PB		 5137 if (unlikely(rflags & X86_EFLAGS_TF)) {
5138 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5139 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5140 DR6_RTM;
663f4c61
PB		 5141 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5142 kvm_run->debug.arch.exception = DB_VECTOR;
5143 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5144 *r = EMULATE_USER_EXIT;
5145 } else {
5146 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5147 /*
5148 * "Certain debug exceptions may clear bit 0-3. The
5149 * remaining contents of the DR6 register are never
5150 * cleared by the processor".
5151 */
5152 vcpu->arch.dr6 &= ~15;
6f43ed01 5153 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5154 kvm_queue_exception(vcpu, DB_VECTOR);
5155 }
5156 }
5157}
5158
4a1e10d5
PB		 5159static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5160{
5161 struct kvm_run *kvm_run = vcpu->run;
5162 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5163 u32 dr6 = 0;
5164
5165 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5166 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5167 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5168 vcpu->arch.guest_debug_dr7,
5169 vcpu->arch.eff_db);
5170
5171 if (dr6 != 0) {
6f43ed01 5172 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5173 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5174 get_segment_base(vcpu, VCPU_SREG_CS);
5175
5176 kvm_run->debug.arch.exception = DB_VECTOR;
5177 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5178 *r = EMULATE_USER_EXIT;
5179 return true;
5180 }
5181 }
5182
4161a569
NA		 5183 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5184 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5185 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5186 vcpu->arch.dr7,
5187 vcpu->arch.db);
5188
5189 if (dr6 != 0) {
5190 vcpu->arch.dr6 &= ~15;
6f43ed01 5191 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5192 kvm_queue_exception(vcpu, DB_VECTOR);
5193 *r = EMULATE_DONE;
5194 return true;
5195 }
5196 }
5197
5198 return false;
5199}
5200
51d8b661
AP		 5201int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5202 unsigned long cr2,
dc25e89e
AP		 5203 int emulation_type,
5204 void *insn,
5205 int insn_len)
bbd9b64e 5206{
95cb2295 5207 int r;
9d74191a 5208 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5209 bool writeback = true;
93c05d3e 5210 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5211
93c05d3e
XG		 5212 /*
5213 * Clear write_fault_to_shadow_pgtable here to ensure it is
5214 * never reused.
5215 */
5216 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5217 kvm_clear_exception_queue(vcpu);
8d7d8102 5218
571008da 5219 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5220 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5221
5222 /*
5223 * We will reenter on the same instruction since
5224 * we do not set complete_userspace_io. This does not
5225 * handle watchpoints yet, those would be handled in
5226 * the emulate_ops.
5227 */
5228 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5229 return r;
5230
9d74191a
TY		 5231 ctxt->interruptibility = 0;
5232 ctxt->have_exception = false;
5233 ctxt->perm_ok = false;
bbd9b64e 5234
b51e974f 5235 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5236
9d74191a 5237 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5238
e46479f8 5239 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5240 ++vcpu->stat.insn_emulation;
1d2887e2 5241 if (r != EMULATION_OK) {
4005996e
AK		 5242 if (emulation_type & EMULTYPE_TRAP_UD)
5243 return EMULATE_FAIL;
991eebf9
GN		 5244 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5245 emulation_type))
bbd9b64e 5246 return EMULATE_DONE;
6d77dbfc
GN		 5247 if (emulation_type & EMULTYPE_SKIP)
5248 return EMULATE_FAIL;
5249 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5250 }
5251 }
5252
ba8afb6b 5253 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5254 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5255 if (ctxt->eflags & X86_EFLAGS_RF)
5256 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5257 return EMULATE_DONE;
5258 }
5259
1cb3f3ae
XG		 5260 if (retry_instruction(ctxt, cr2, emulation_type))
5261 return EMULATE_DONE;
5262
7ae441ea 5263 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5264 changes registers values during IO operation */
7ae441ea
GN		 5265 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5266 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5267 emulator_invalidate_register_cache(ctxt);
7ae441ea 5268 }
4d2179e1 5269
5cd21917 5270restart:
9d74191a 5271 r = x86_emulate_insn(ctxt);
bbd9b64e 5272
775fde86
JR		 5273 if (r == EMULATION_INTERCEPTED)
5274 return EMULATE_DONE;
5275
d2ddd1c4 5276 if (r == EMULATION_FAILED) {
991eebf9
GN		 5277 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5278 emulation_type))
c3cd7ffa
GN		 5279 return EMULATE_DONE;
5280
6d77dbfc 5281 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5282 }
5283
9d74191a 5284 if (ctxt->have_exception) {
54b8486f 5285 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5286 r = EMULATE_DONE;
5287 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5288 if (!vcpu->arch.pio.in) {
5289 /* FIXME: return into emulator if single-stepping. */
3457e419 5290 vcpu->arch.pio.count = 0;
0912c977 5291 } else {
7ae441ea 5292 writeback = false;
716d51ab
GN		 5293 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5294 }
ac0a48c3 5295 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5296 } else if (vcpu->mmio_needed) {
5297 if (!vcpu->mmio_is_write)
5298 writeback = false;
ac0a48c3 5299 r = EMULATE_USER_EXIT;
716d51ab 5300 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5301 } else if (r == EMULATION_RESTART)
5cd21917 5302 goto restart;
d2ddd1c4
GN		 5303 else
5304 r = EMULATE_DONE;
f850e2e6 5305
7ae441ea 5306 if (writeback) {
6addfc42 5307 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5308 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5309 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5310 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5311 if (r == EMULATE_DONE)
6addfc42
PB		 5312 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5313 __kvm_set_rflags(vcpu, ctxt->eflags);
5314
5315 /*
5316 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5317 * do nothing, and it will be requested again as soon as
5318 * the shadow expires. But we still need to check here,
5319 * because POPF has no interrupt shadow.
5320 */
5321 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5322 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5323 } else
5324 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5325
5326 return r;
de7d789a 5327}
51d8b661 5328EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5329
cf8f70bf 5330int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5331{
cf8f70bf 5332 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5333 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5334 size, port, &val, 1);
cf8f70bf 5335 /* do not return to emulator after return from userspace */
7972995b 5336 vcpu->arch.pio.count = 0;
de7d789a
CO		 5337 return ret;
5338}
cf8f70bf 5339EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5340
8cfdc000
ZA		 5341static void tsc_bad(void *info)
5342{
0a3aee0d 5343 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5344}
5345
5346static void tsc_khz_changed(void *data)
c8076604 5347{
8cfdc000
ZA		 5348 struct cpufreq_freqs *freq = data;
5349 unsigned long khz = 0;
5350
5351 if (data)
5352 khz = freq->new;
5353 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5354 khz = cpufreq_quick_get(raw_smp_processor_id());
5355 if (!khz)
5356 khz = tsc_khz;
0a3aee0d 5357 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5358}
5359
c8076604
GH		 5360static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5361 void *data)
5362{
5363 struct cpufreq_freqs *freq = data;
5364 struct kvm *kvm;
5365 struct kvm_vcpu *vcpu;
5366 int i, send_ipi = 0;
5367
8cfdc000
ZA		 5368 /*
5369 * We allow guests to temporarily run on slowing clocks,
5370 * provided we notify them after, or to run on accelerating
5371 * clocks, provided we notify them before. Thus time never
5372 * goes backwards.
5373 *
5374 * However, we have a problem. We can't atomically update
5375 * the frequency of a given CPU from this function; it is
5376 * merely a notifier, which can be called from any CPU.
5377 * Changing the TSC frequency at arbitrary points in time
5378 * requires a recomputation of local variables related to
5379 * the TSC for each VCPU. We must flag these local variables
5380 * to be updated and be sure the update takes place with the
5381 * new frequency before any guests proceed.
5382 *
5383 * Unfortunately, the combination of hotplug CPU and frequency
5384 * change creates an intractable locking scenario; the order
5385 * of when these callouts happen is undefined with respect to
5386 * CPU hotplug, and they can race with each other. As such,
5387 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5388 * undefined; you can actually have a CPU frequency change take
5389 * place in between the computation of X and the setting of the
5390 * variable. To protect against this problem, all updates of
5391 * the per_cpu tsc_khz variable are done in an interrupt
5392 * protected IPI, and all callers wishing to update the value
5393 * must wait for a synchronous IPI to complete (which is trivial
5394 * if the caller is on the CPU already). This establishes the
5395 * necessary total order on variable updates.
5396 *
5397 * Note that because a guest time update may take place
5398 * anytime after the setting of the VCPU's request bit, the
5399 * correct TSC value must be set before the request. However,
5400 * to ensure the update actually makes it to any guest which
5401 * starts running in hardware virtualization between the set
5402 * and the acquisition of the spinlock, we must also ping the
5403 * CPU after setting the request bit.
5404 *
5405 */
5406
c8076604
GH		 5407 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5408 return 0;
5409 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5410 return 0;
8cfdc000
ZA		 5411
5412 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5413
2f303b74 5414 spin_lock(&kvm_lock);
c8076604 5415 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5416 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5417 if (vcpu->cpu != freq->cpu)
5418 continue;
c285545f 5419 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5420 if (vcpu->cpu != smp_processor_id())
8cfdc000 5421 send_ipi = 1;
c8076604
GH		 5422 }
5423 }
2f303b74 5424 spin_unlock(&kvm_lock);
c8076604
GH		 5425
5426 if (freq->old < freq->new && send_ipi) {
5427 /*
5428 * We upscale the frequency. Must make the guest
5429 * doesn't see old kvmclock values while running with
5430 * the new frequency, otherwise we risk the guest sees
5431 * time go backwards.
5432 *
5433 * In case we update the frequency for another cpu
5434 * (which might be in guest context) send an interrupt
5435 * to kick the cpu out of guest context. Next time
5436 * guest context is entered kvmclock will be updated,
5437 * so the guest will not see stale values.
5438 */
8cfdc000 5439 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5440 }
5441 return 0;
5442}
5443
5444static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5445 .notifier_call = kvmclock_cpufreq_notifier
5446};
5447
5448static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5449 unsigned long action, void *hcpu)
5450{
5451 unsigned int cpu = (unsigned long)hcpu;
5452
5453 switch (action) {
5454 case CPU_ONLINE:
5455 case CPU_DOWN_FAILED:
5456 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5457 break;
5458 case CPU_DOWN_PREPARE:
5459 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5460 break;
5461 }
5462 return NOTIFY_OK;
5463}
5464
5465static struct notifier_block kvmclock_cpu_notifier_block = {
5466 .notifier_call = kvmclock_cpu_notifier,
5467 .priority = -INT_MAX
c8076604
GH		 5468};
5469
b820cc0c
ZA		 5470static void kvm_timer_init(void)
5471{
5472 int cpu;
5473
c285545f 5474 max_tsc_khz = tsc_khz;
460dd42e
SB		 5475
5476 cpu_notifier_register_begin();
b820cc0c 5477 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5478#ifdef CONFIG_CPU_FREQ
5479 struct cpufreq_policy policy;
5480 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5481 cpu = get_cpu();
5482 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5483 if (policy.cpuinfo.max_freq)
5484 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5485 put_cpu();
c285545f 5486#endif
b820cc0c
ZA		 5487 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5488 CPUFREQ_TRANSITION_NOTIFIER);
5489 }
c285545f 5490 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5491 for_each_online_cpu(cpu)
5492 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5493
5494 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5495 cpu_notifier_register_done();
5496
b820cc0c
ZA		 5497}
5498
ff9d07a0
ZY		 5499static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5500
f5132b01 5501int kvm_is_in_guest(void)
ff9d07a0 5502{
086c9855 5503 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5504}
5505
5506static int kvm_is_user_mode(void)
5507{
5508 int user_mode = 3;
dcf46b94 5509
086c9855
AS		 5510 if (__this_cpu_read(current_vcpu))
5511 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5512
ff9d07a0
ZY		 5513 return user_mode != 0;
5514}
5515
5516static unsigned long kvm_get_guest_ip(void)
5517{
5518 unsigned long ip = 0;
dcf46b94 5519
086c9855
AS		 5520 if (__this_cpu_read(current_vcpu))
5521 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5522
ff9d07a0
ZY		 5523 return ip;
5524}
5525
5526static struct perf_guest_info_callbacks kvm_guest_cbs = {
5527 .is_in_guest = kvm_is_in_guest,
5528 .is_user_mode = kvm_is_user_mode,
5529 .get_guest_ip = kvm_get_guest_ip,
5530};
5531
5532void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5533{
086c9855 5534 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5535}
5536EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5537
5538void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5539{
086c9855 5540 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5541}
5542EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5543
ce88decf
XG		 5544static void kvm_set_mmio_spte_mask(void)
5545{
5546 u64 mask;
5547 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5548
5549 /*
5550 * Set the reserved bits and the present bit of an paging-structure
5551 * entry to generate page fault with PFER.RSV = 1.
5552 */
885032b9
XG		 5553 /* Mask the reserved physical address bits. */
5554 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5555
5556 /* Bit 62 is always reserved for 32bit host. */
5557 mask |= 0x3ull << 62;
5558
5559 /* Set the present bit. */
ce88decf
XG		 5560 mask |= 1ull;
5561
5562#ifdef CONFIG_X86_64
5563 /*
5564 * If reserved bit is not supported, clear the present bit to disable
5565 * mmio page fault.
5566 */
5567 if (maxphyaddr == 52)
5568 mask &= ~1ull;
5569#endif
5570
5571 kvm_mmu_set_mmio_spte_mask(mask);
5572}
5573
16e8d74d
MT		 5574#ifdef CONFIG_X86_64
5575static void pvclock_gtod_update_fn(struct work_struct *work)
5576{
d828199e
MT		 5577 struct kvm *kvm;
5578
5579 struct kvm_vcpu *vcpu;
5580 int i;
5581
2f303b74 5582 spin_lock(&kvm_lock);
d828199e
MT		 5583 list_for_each_entry(kvm, &vm_list, vm_list)
5584 kvm_for_each_vcpu(i, vcpu, kvm)
5585 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5586 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5587 spin_unlock(&kvm_lock);
16e8d74d
MT		 5588}
5589
5590static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5591
5592/*
5593 * Notification about pvclock gtod data update.
5594 */
5595static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5596 void *priv)
5597{
5598 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5599 struct timekeeper *tk = priv;
5600
5601 update_pvclock_gtod(tk);
5602
5603 /* disable master clock if host does not trust, or does not
5604 * use, TSC clocksource
5605 */
5606 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5607 atomic_read(&kvm_guest_has_master_clock) != 0)
5608 queue_work(system_long_wq, &pvclock_gtod_work);
5609
5610 return 0;
5611}
5612
5613static struct notifier_block pvclock_gtod_notifier = {
5614 .notifier_call = pvclock_gtod_notify,
5615};
5616#endif
5617
f8c16bba 5618int kvm_arch_init(void *opaque)
043405e1 5619{
b820cc0c 5620 int r;
6b61edf7 5621 struct kvm_x86_ops *ops = opaque;
f8c16bba 5622
f8c16bba
ZX		 5623 if (kvm_x86_ops) {
5624 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5625 r = -EEXIST;
5626 goto out;
f8c16bba
ZX		 5627 }
5628
5629 if (!ops->cpu_has_kvm_support()) {
5630 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5631 r = -EOPNOTSUPP;
5632 goto out;
f8c16bba
ZX		 5633 }
5634 if (ops->disabled_by_bios()) {
5635 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5636 r = -EOPNOTSUPP;
5637 goto out;
f8c16bba
ZX		 5638 }
5639
013f6a5d
MT		 5640 r = -ENOMEM;
5641 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5642 if (!shared_msrs) {
5643 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5644 goto out;
5645 }
5646
97db56ce
AK		 5647 r = kvm_mmu_module_init();
5648 if (r)
013f6a5d 5649 goto out_free_percpu;
97db56ce 5650
ce88decf 5651 kvm_set_mmio_spte_mask();
97db56ce 5652
f8c16bba 5653 kvm_x86_ops = ops;
920c8377
PB		 5654 kvm_init_msr_list();
5655
7b52345e 5656 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5657 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5658
b820cc0c 5659 kvm_timer_init();
c8076604 5660
ff9d07a0
ZY		 5661 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5662
2acf923e
DC		 5663 if (cpu_has_xsave)
5664 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5665
c5cc421b 5666 kvm_lapic_init();
16e8d74d
MT		 5667#ifdef CONFIG_X86_64
5668 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5669#endif
5670
f8c16bba 5671 return 0;
56c6d28a 5672
013f6a5d
MT		 5673out_free_percpu:
5674 free_percpu(shared_msrs);
56c6d28a 5675out:
56c6d28a 5676 return r;
043405e1 5677}
8776e519 5678
f8c16bba
ZX		 5679void kvm_arch_exit(void)
5680{
ff9d07a0
ZY		 5681 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5682
888d256e
JK		 5683 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5684 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5685 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5686 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5687#ifdef CONFIG_X86_64
5688 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5689#endif
f8c16bba 5690 kvm_x86_ops = NULL;
56c6d28a 5691 kvm_mmu_module_exit();
013f6a5d 5692 free_percpu(shared_msrs);
56c6d28a 5693}
f8c16bba 5694
8776e519
HB		 5695int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5696{
5697 ++vcpu->stat.halt_exits;
5698 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5699 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5700 return 1;
5701 } else {
5702 vcpu->run->exit_reason = KVM_EXIT_HLT;
5703 return 0;
5704 }
5705}
5706EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5707
55cd8e5a
GN		 5708int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5709{
5710 u64 param, ingpa, outgpa, ret;
5711 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5712 bool fast, longmode;
55cd8e5a
GN		 5713
5714 /*
5715 * hypercall generates UD from non zero cpl and real mode
5716 * per HYPER-V spec
5717 */
3eeb3288 5718 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5719 kvm_queue_exception(vcpu, UD_VECTOR);
5720 return 0;
5721 }
5722
a449c7aa 5723 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5724
5725 if (!longmode) {
ccd46936
GN		 5726 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5727 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5728 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5729 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5730 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5731 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5732 }
5733#ifdef CONFIG_X86_64
5734 else {
5735 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5736 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5737 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5738 }
5739#endif
5740
5741 code = param & 0xffff;
5742 fast = (param >> 16) & 0x1;
5743 rep_cnt = (param >> 32) & 0xfff;
5744 rep_idx = (param >> 48) & 0xfff;
5745
5746 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5747
c25bc163
GN		 5748 switch (code) {
5749 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5750 kvm_vcpu_on_spin(vcpu);
5751 break;
5752 default:
5753 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5754 break;
5755 }
55cd8e5a
GN		 5756
5757 ret = res | (((u64)rep_done & 0xfff) << 32);
5758 if (longmode) {
5759 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5760 } else {
5761 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5762 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5763 }
5764
5765 return 1;
5766}
5767
6aef266c
SV		 5768/*
5769 * kvm_pv_kick_cpu_op: Kick a vcpu.
5770 *
5771 * @apicid - apicid of vcpu to be kicked.
5772 */
5773static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5774{
24d2166b 5775 struct kvm_lapic_irq lapic_irq;
6aef266c 5776
24d2166b
R		 5777 lapic_irq.shorthand = 0;
5778 lapic_irq.dest_mode = 0;
5779 lapic_irq.dest_id = apicid;
6aef266c 5780
24d2166b
R		 5781 lapic_irq.delivery_mode = APIC_DM_REMRD;
5782 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5783}
5784
8776e519
HB		 5785int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5786{
5787 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5788 int op_64_bit, r = 1;
8776e519 5789
55cd8e5a
GN		 5790 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5791 return kvm_hv_hypercall(vcpu);
5792
5fdbf976
MT		 5793 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5794 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5795 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5796 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5797 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5798
229456fc 5799 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5800
a449c7aa
NA		 5801 op_64_bit = is_64_bit_mode(vcpu);
5802 if (!op_64_bit) {
8776e519
HB		 5803 nr &= 0xFFFFFFFF;
5804 a0 &= 0xFFFFFFFF;
5805 a1 &= 0xFFFFFFFF;
5806 a2 &= 0xFFFFFFFF;
5807 a3 &= 0xFFFFFFFF;
5808 }
5809
07708c4a
JK		 5810 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5811 ret = -KVM_EPERM;
5812 goto out;
5813 }
5814
8776e519 5815 switch (nr) {
b93463aa
AK		 5816 case KVM_HC_VAPIC_POLL_IRQ:
5817 ret = 0;
5818 break;
6aef266c
SV		 5819 case KVM_HC_KICK_CPU:
5820 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5821 ret = 0;
5822 break;
8776e519
HB		 5823 default:
5824 ret = -KVM_ENOSYS;
5825 break;
5826 }
07708c4a 5827out:
a449c7aa
NA		 5828 if (!op_64_bit)
5829 ret = (u32)ret;
5fdbf976 5830 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5831 ++vcpu->stat.hypercalls;
2f333bcb 5832 return r;
8776e519
HB		 5833}
5834EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5835
b6785def 5836static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5837{
d6aa1000 5838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5839 char instruction[3];
5fdbf976 5840 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5841
8776e519 5842 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5843
9d74191a 5844 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5845}
5846
b6c7a5dc
HB		 5847/*
5848 * Check if userspace requested an interrupt window, and that the
5849 * interrupt window is open.
5850 *
5851 * No need to exit to userspace if we already have an interrupt queued.
5852 */
851ba692 5853static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5854{
8061823a 5855 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5856 vcpu->run->request_interrupt_window &&
5df56646 5857 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5858}
5859
851ba692 5860static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5861{
851ba692
AK		 5862 struct kvm_run *kvm_run = vcpu->run;
5863
91586a3b 5864 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5865 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5866 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5867 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5868 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5869 else
b6c7a5dc 5870 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5871 kvm_arch_interrupt_allowed(vcpu) &&
5872 !kvm_cpu_has_interrupt(vcpu) &&
5873 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5874}
5875
95ba8273
GN		 5876static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5877{
5878 int max_irr, tpr;
5879
5880 if (!kvm_x86_ops->update_cr8_intercept)
5881 return;
5882
88c808fd
AK		 5883 if (!vcpu->arch.apic)
5884 return;
5885
8db3baa2
GN		 5886 if (!vcpu->arch.apic->vapic_addr)
5887 max_irr = kvm_lapic_find_highest_irr(vcpu);
5888 else
5889 max_irr = -1;
95ba8273
GN		 5890
5891 if (max_irr != -1)
5892 max_irr >>= 4;
5893
5894 tpr = kvm_lapic_get_cr8(vcpu);
5895
5896 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5897}
5898
b6b8a145 5899static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5900{
b6b8a145
JK		 5901 int r;
5902
95ba8273 5903 /* try to reinject previous events if any */
b59bb7bd 5904 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5905 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5906 vcpu->arch.exception.has_error_code,
5907 vcpu->arch.exception.error_code);
d6e8c854
NA		 5908
5909 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5910 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5911 X86_EFLAGS_RF);
5912
b59bb7bd
GN		 5913 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5914 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5915 vcpu->arch.exception.error_code,
5916 vcpu->arch.exception.reinject);
b6b8a145 5917 return 0;
b59bb7bd
GN		 5918 }
5919
95ba8273
GN		 5920 if (vcpu->arch.nmi_injected) {
5921 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5922 return 0;
95ba8273
GN		 5923 }
5924
5925 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5926 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5927 return 0;
5928 }
5929
5930 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5931 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5932 if (r != 0)
5933 return r;
95ba8273
GN		 5934 }
5935
5936 /* try to inject new event if pending */
5937 if (vcpu->arch.nmi_pending) {
5938 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5939 --vcpu->arch.nmi_pending;
95ba8273
GN		 5940 vcpu->arch.nmi_injected = true;
5941 kvm_x86_ops->set_nmi(vcpu);
5942 }
c7c9c56c 5943 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5944 /*
5945 * Because interrupts can be injected asynchronously, we are
5946 * calling check_nested_events again here to avoid a race condition.
5947 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5948 * proposal and current concerns. Perhaps we should be setting
5949 * KVM_REQ_EVENT only on certain events and not unconditionally?
5950 */
5951 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5952 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5953 if (r != 0)
5954 return r;
5955 }
95ba8273 5956 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5957 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5958 false);
5959 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5960 }
5961 }
b6b8a145 5962 return 0;
95ba8273
GN		 5963}
5964
7460fb4a
AK		 5965static void process_nmi(struct kvm_vcpu *vcpu)
5966{
5967 unsigned limit = 2;
5968
5969 /*
5970 * x86 is limited to one NMI running, and one NMI pending after it.
5971 * If an NMI is already in progress, limit further NMIs to just one.
5972 * Otherwise, allow two (and we'll inject the first one immediately).
5973 */
5974 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5975 limit = 1;
5976
5977 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5978 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5979 kvm_make_request(KVM_REQ_EVENT, vcpu);
5980}
5981
3d81bc7e 5982static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5983{
5984 u64 eoi_exit_bitmap[4];
cf9e65b7 5985 u32 tmr[8];
c7c9c56c 5986
3d81bc7e
YZ		 5987 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5988 return;
c7c9c56c
YZ		 5989
5990 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5991 memset(tmr, 0, 32);
c7c9c56c 5992
cf9e65b7 5993 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5994 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5995 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5996}
5997
9357d939
TY		 5998/*
5999 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6000 * exiting to the userspace. Otherwise, the value will be returned to the
6001 * userspace.
6002 */
851ba692 6003static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6004{
6005 int r;
6a8b1d13 6006 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6007 vcpu->run->request_interrupt_window;
730dca42 6008 bool req_immediate_exit = false;
b6c7a5dc 6009
3e007509 6010 if (vcpu->requests) {
a8eeb04a 6011 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6012 kvm_mmu_unload(vcpu);
a8eeb04a 6013 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6014 __kvm_migrate_timers(vcpu);
d828199e
MT		 6015 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6016 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6017 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6018 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6019 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6020 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6021 if (unlikely(r))
6022 goto out;
6023 }
a8eeb04a 6024 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6025 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6026 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 6027 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 6028 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6029 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6030 r = 0;
6031 goto out;
6032 }
a8eeb04a 6033 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6034 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6035 r = 0;
6036 goto out;
6037 }
a8eeb04a 6038 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6039 vcpu->fpu_active = 0;
6040 kvm_x86_ops->fpu_deactivate(vcpu);
6041 }
af585b92
GN		 6042 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6043 /* Page is swapped out. Do synthetic halt */
6044 vcpu->arch.apf.halted = true;
6045 r = 1;
6046 goto out;
6047 }
c9aaa895
GC		 6048 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6049 record_steal_time(vcpu);
7460fb4a
AK		 6050 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6051 process_nmi(vcpu);
f5132b01
GN		 6052 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6053 kvm_handle_pmu_event(vcpu);
6054 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6055 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6056 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6057 vcpu_scan_ioapic(vcpu);
2f52d58c 6058 }
b93463aa 6059
b463a6f7 6060 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6061 kvm_apic_accept_events(vcpu);
6062 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6063 r = 1;
6064 goto out;
6065 }
6066
b6b8a145
JK		 6067 if (inject_pending_event(vcpu, req_int_win) != 0)
6068 req_immediate_exit = true;
b463a6f7 6069 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6070 else if (vcpu->arch.nmi_pending)
c9a7953f 6071 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6072 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6073 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6074
6075 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6076 /*
6077 * Update architecture specific hints for APIC
6078 * virtual interrupt delivery.
6079 */
6080 if (kvm_x86_ops->hwapic_irr_update)
6081 kvm_x86_ops->hwapic_irr_update(vcpu,
6082 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6083 update_cr8_intercept(vcpu);
6084 kvm_lapic_sync_to_vapic(vcpu);
6085 }
6086 }
6087
d8368af8
AK		 6088 r = kvm_mmu_reload(vcpu);
6089 if (unlikely(r)) {
d905c069 6090 goto cancel_injection;
d8368af8
AK		 6091 }
6092
b6c7a5dc
HB		 6093 preempt_disable();
6094
6095 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6096 if (vcpu->fpu_active)
6097 kvm_load_guest_fpu(vcpu);
2acf923e 6098 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6099
6b7e2d09
XG		 6100 vcpu->mode = IN_GUEST_MODE;
6101
01b71917
MT		 6102 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6103
6b7e2d09
XG		 6104 /* We should set ->mode before check ->requests,
6105 * see the comment in make_all_cpus_request.
6106 */
01b71917 6107 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6108
d94e1dc9 6109 local_irq_disable();
32f88400 6110
6b7e2d09 6111 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6112 || need_resched() || signal_pending(current)) {
6b7e2d09 6113 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6114 smp_wmb();
6c142801
AK		 6115 local_irq_enable();
6116 preempt_enable();
01b71917 6117 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6118 r = 1;
d905c069 6119 goto cancel_injection;
6c142801
AK		 6120 }
6121
d6185f20
NHE		 6122 if (req_immediate_exit)
6123 smp_send_reschedule(vcpu->cpu);
6124
b6c7a5dc
HB		 6125 kvm_guest_enter();
6126
42dbaa5a 6127 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6128 set_debugreg(0, 7);
6129 set_debugreg(vcpu->arch.eff_db[0], 0);
6130 set_debugreg(vcpu->arch.eff_db[1], 1);
6131 set_debugreg(vcpu->arch.eff_db[2], 2);
6132 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6133 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6134 }
b6c7a5dc 6135
229456fc 6136 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6137 kvm_x86_ops->run(vcpu);
b6c7a5dc 6138
c77fb5fe
PB		 6139 /*
6140 * Do this here before restoring debug registers on the host. And
6141 * since we do this before handling the vmexit, a DR access vmexit
6142 * can (a) read the correct value of the debug registers, (b) set
6143 * KVM_DEBUGREG_WONT_EXIT again.
6144 */
6145 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6146 int i;
6147
6148 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6149 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6150 for (i = 0; i < KVM_NR_DB_REGS; i++)
6151 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6152 }
6153
24f1e32c
FW		 6154 /*
6155 * If the guest has used debug registers, at least dr7
6156 * will be disabled while returning to the host.
6157 * If we don't have active breakpoints in the host, we don't
6158 * care about the messed up debug address registers. But if
6159 * we have some of them active, restore the old state.
6160 */
59d8eb53 6161 if (hw_breakpoint_active())
24f1e32c 6162 hw_breakpoint_restore();
42dbaa5a 6163
886b470c
MT		 6164 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6165 native_read_tsc());
1d5f066e 6166
6b7e2d09 6167 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6168 smp_wmb();
a547c6db
YZ		 6169
6170 /* Interrupt is enabled by handle_external_intr() */
6171 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6172
6173 ++vcpu->stat.exits;
6174
6175 /*
6176 * We must have an instruction between local_irq_enable() and
6177 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6178 * the interrupt shadow. The stat.exits increment will do nicely.
6179 * But we need to prevent reordering, hence this barrier():
6180 */
6181 barrier();
6182
6183 kvm_guest_exit();
6184
6185 preempt_enable();
6186
f656ce01 6187 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6188
b6c7a5dc
HB		 6189 /*
6190 * Profile KVM exit RIPs:
6191 */
6192 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6193 unsigned long rip = kvm_rip_read(vcpu);
6194 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6195 }
6196
cc578287
ZA		 6197 if (unlikely(vcpu->arch.tsc_always_catchup))
6198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6199
5cfb1d5a
MT		 6200 if (vcpu->arch.apic_attention)
6201 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6202
851ba692 6203 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6204 return r;
6205
6206cancel_injection:
6207 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6208 if (unlikely(vcpu->arch.apic_attention))
6209 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6210out:
6211 return r;
6212}
b6c7a5dc 6213
09cec754 6214
851ba692 6215static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6216{
6217 int r;
f656ce01 6218 struct kvm *kvm = vcpu->kvm;
d7690175 6219
f656ce01 6220 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6221
6222 r = 1;
6223 while (r > 0) {
af585b92
GN		 6224 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6225 !vcpu->arch.apf.halted)
851ba692 6226 r = vcpu_enter_guest(vcpu);
d7690175 6227 else {
f656ce01 6228 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6229 kvm_vcpu_block(vcpu);
f656ce01 6230 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6231 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6232 kvm_apic_accept_events(vcpu);
09cec754
GN		 6233 switch(vcpu->arch.mp_state) {
6234 case KVM_MP_STATE_HALTED:
6aef266c 6235 vcpu->arch.pv.pv_unhalted = false;
d7690175 6236 vcpu->arch.mp_state =
09cec754
GN		 6237 KVM_MP_STATE_RUNNABLE;
6238 case KVM_MP_STATE_RUNNABLE:
af585b92 6239 vcpu->arch.apf.halted = false;
09cec754 6240 break;
66450a21
JK		 6241 case KVM_MP_STATE_INIT_RECEIVED:
6242 break;
09cec754
GN		 6243 default:
6244 r = -EINTR;
6245 break;
6246 }
6247 }
d7690175
MT		 6248 }
6249
09cec754
GN		 6250 if (r <= 0)
6251 break;
6252
6253 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6254 if (kvm_cpu_has_pending_timer(vcpu))
6255 kvm_inject_pending_timer_irqs(vcpu);
6256
851ba692 6257 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6258 r = -EINTR;
851ba692 6259 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6260 ++vcpu->stat.request_irq_exits;
6261 }
af585b92
GN		 6262
6263 kvm_check_async_pf_completion(vcpu);
6264
09cec754
GN		 6265 if (signal_pending(current)) {
6266 r = -EINTR;
851ba692 6267 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6268 ++vcpu->stat.signal_exits;
6269 }
6270 if (need_resched()) {
f656ce01 6271 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6272 cond_resched();
f656ce01 6273 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6274 }
b6c7a5dc
HB		 6275 }
6276
f656ce01 6277 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6278
6279 return r;
6280}
6281
716d51ab
GN		 6282static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6283{
6284 int r;
6285 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6286 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6287 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6288 if (r != EMULATE_DONE)
6289 return 0;
6290 return 1;
6291}
6292
6293static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6294{
6295 BUG_ON(!vcpu->arch.pio.count);
6296
6297 return complete_emulated_io(vcpu);
6298}
6299
f78146b0
AK		 6300/*
6301 * Implements the following, as a state machine:
6302 *
6303 * read:
6304 * for each fragment
87da7e66
XG		 6305 * for each mmio piece in the fragment
6306 * write gpa, len
6307 * exit
6308 * copy data
f78146b0
AK		 6309 * execute insn
6310 *
6311 * write:
6312 * for each fragment
87da7e66
XG		 6313 * for each mmio piece in the fragment
6314 * write gpa, len
6315 * copy data
6316 * exit
f78146b0 6317 */
716d51ab 6318static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6319{
6320 struct kvm_run *run = vcpu->run;
f78146b0 6321 struct kvm_mmio_fragment *frag;
87da7e66 6322 unsigned len;
5287f194 6323
716d51ab 6324 BUG_ON(!vcpu->mmio_needed);
5287f194 6325
716d51ab 6326 /* Complete previous fragment */
87da7e66
XG		 6327 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6328 len = min(8u, frag->len);
716d51ab 6329 if (!vcpu->mmio_is_write)
87da7e66
XG		 6330 memcpy(frag->data, run->mmio.data, len);
6331
6332 if (frag->len <= 8) {
6333 /* Switch to the next fragment. */
6334 frag++;
6335 vcpu->mmio_cur_fragment++;
6336 } else {
6337 /* Go forward to the next mmio piece. */
6338 frag->data += len;
6339 frag->gpa += len;
6340 frag->len -= len;
6341 }
6342
a08d3b3b 6343 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6344 vcpu->mmio_needed = 0;
0912c977
PB		 6345
6346 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6347 if (vcpu->mmio_is_write)
716d51ab
GN		 6348 return 1;
6349 vcpu->mmio_read_completed = 1;
6350 return complete_emulated_io(vcpu);
6351 }
87da7e66 6352
716d51ab
GN		 6353 run->exit_reason = KVM_EXIT_MMIO;
6354 run->mmio.phys_addr = frag->gpa;
6355 if (vcpu->mmio_is_write)
87da7e66
XG		 6356 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6357 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6358 run->mmio.is_write = vcpu->mmio_is_write;
6359 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6360 return 0;
5287f194
AK		 6361}
6362
716d51ab 6363
b6c7a5dc
HB		 6364int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6365{
6366 int r;
6367 sigset_t sigsaved;
6368
e5c30142
AK		 6369 if (!tsk_used_math(current) && init_fpu(current))
6370 return -ENOMEM;
6371
ac9f6dc0
AK		 6372 if (vcpu->sigset_active)
6373 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6374
a4535290 6375 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6376 kvm_vcpu_block(vcpu);
66450a21 6377 kvm_apic_accept_events(vcpu);
d7690175 6378 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6379 r = -EAGAIN;
6380 goto out;
b6c7a5dc
HB		 6381 }
6382
b6c7a5dc 6383 /* re-sync apic's tpr */
eea1cff9
AP		 6384 if (!irqchip_in_kernel(vcpu->kvm)) {
6385 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6386 r = -EINVAL;
6387 goto out;
6388 }
6389 }
b6c7a5dc 6390
716d51ab
GN		 6391 if (unlikely(vcpu->arch.complete_userspace_io)) {
6392 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6393 vcpu->arch.complete_userspace_io = NULL;
6394 r = cui(vcpu);
6395 if (r <= 0)
6396 goto out;
6397 } else
6398 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6399
851ba692 6400 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6401
6402out:
f1d86e46 6403 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6404 if (vcpu->sigset_active)
6405 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6406
b6c7a5dc
HB		 6407 return r;
6408}
6409
6410int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6411{
7ae441ea
GN		 6412 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6413 /*
6414 * We are here if userspace calls get_regs() in the middle of
6415 * instruction emulation. Registers state needs to be copied
4a969980 6416 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6417 * that usually, but some bad designed PV devices (vmware
6418 * backdoor interface) need this to work
6419 */
dd856efa 6420 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6421 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6422 }
5fdbf976
MT		 6423 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6424 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6425 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6426 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6427 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6428 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6429 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6430 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6431#ifdef CONFIG_X86_64
5fdbf976
MT		 6432 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6433 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6434 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6435 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6436 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6437 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6438 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6439 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6440#endif
6441
5fdbf976 6442 regs->rip = kvm_rip_read(vcpu);
91586a3b 6443 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6444
b6c7a5dc
HB		 6445 return 0;
6446}
6447
6448int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6449{
7ae441ea
GN		 6450 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6451 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6452
5fdbf976
MT		 6453 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6454 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6455 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6456 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6457 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6458 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6459 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6460 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6461#ifdef CONFIG_X86_64
5fdbf976
MT		 6462 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6463 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6464 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6465 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6466 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6467 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6468 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6469 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6470#endif
6471
5fdbf976 6472 kvm_rip_write(vcpu, regs->rip);
91586a3b 6473 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6474
b4f14abd
JK		 6475 vcpu->arch.exception.pending = false;
6476
3842d135
AK		 6477 kvm_make_request(KVM_REQ_EVENT, vcpu);
6478
b6c7a5dc
HB		 6479 return 0;
6480}
6481
b6c7a5dc
HB		 6482void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6483{
6484 struct kvm_segment cs;
6485
3e6e0aab 6486 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6487 *db = cs.db;
6488 *l = cs.l;
6489}
6490EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6491
6492int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6493 struct kvm_sregs *sregs)
6494{
89a27f4d 6495 struct desc_ptr dt;
b6c7a5dc 6496
3e6e0aab
GT		 6497 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6498 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6499 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6500 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6501 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6502 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6503
3e6e0aab
GT		 6504 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6505 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6506
6507 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6508 sregs->idt.limit = dt.size;
6509 sregs->idt.base = dt.address;
b6c7a5dc 6510 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6511 sregs->gdt.limit = dt.size;
6512 sregs->gdt.base = dt.address;
b6c7a5dc 6513
4d4ec087 6514 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6515 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6516 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6517 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6518 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6519 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6520 sregs->apic_base = kvm_get_apic_base(vcpu);
6521
923c61bb 6522 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6523
36752c9b 6524 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6525 set_bit(vcpu->arch.interrupt.nr,
6526 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6527
b6c7a5dc
HB		 6528 return 0;
6529}
6530
62d9f0db
MT		 6531int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6532 struct kvm_mp_state *mp_state)
6533{
66450a21 6534 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6535 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6536 vcpu->arch.pv.pv_unhalted)
6537 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6538 else
6539 mp_state->mp_state = vcpu->arch.mp_state;
6540
62d9f0db
MT		 6541 return 0;
6542}
6543
6544int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6545 struct kvm_mp_state *mp_state)
6546{
66450a21
JK		 6547 if (!kvm_vcpu_has_lapic(vcpu) &&
6548 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6549 return -EINVAL;
6550
6551 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6552 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6553 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6554 } else
6555 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6556 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6557 return 0;
6558}
6559
7f3d35fd
KW		 6560int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6561 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6562{
9d74191a 6563 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6564 int ret;
e01c2426 6565
8ec4722d 6566 init_emulate_ctxt(vcpu);
c697518a 6567
7f3d35fd 6568 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6569 has_error_code, error_code);
c697518a 6570
c697518a 6571 if (ret)
19d04437 6572 return EMULATE_FAIL;
37817f29 6573
9d74191a
TY		 6574 kvm_rip_write(vcpu, ctxt->eip);
6575 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6576 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6577 return EMULATE_DONE;
37817f29
IE		 6578}
6579EXPORT_SYMBOL_GPL(kvm_task_switch);
6580
b6c7a5dc
HB		 6581int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6582 struct kvm_sregs *sregs)
6583{
58cb628d 6584 struct msr_data apic_base_msr;
b6c7a5dc 6585 int mmu_reset_needed = 0;
63f42e02 6586 int pending_vec, max_bits, idx;
89a27f4d 6587 struct desc_ptr dt;
b6c7a5dc 6588
6d1068b3
PM		 6589 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6590 return -EINVAL;
6591
89a27f4d
GN		 6592 dt.size = sregs->idt.limit;
6593 dt.address = sregs->idt.base;
b6c7a5dc 6594 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6595 dt.size = sregs->gdt.limit;
6596 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6597 kvm_x86_ops->set_gdt(vcpu, &dt);
6598
ad312c7c 6599 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6600 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6601 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6602 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6603
2d3ad1f4 6604 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6605
f6801dff 6606 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6607 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6608 apic_base_msr.data = sregs->apic_base;
6609 apic_base_msr.host_initiated = true;
6610 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6611
4d4ec087 6612 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6613 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6614 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6615
fc78f519 6616 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6617 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6618 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6619 kvm_update_cpuid(vcpu);
63f42e02
XG		 6620
6621 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6622 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6623 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6624 mmu_reset_needed = 1;
6625 }
63f42e02 6626 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6627
6628 if (mmu_reset_needed)
6629 kvm_mmu_reset_context(vcpu);
6630
a50abc3b 6631 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6632 pending_vec = find_first_bit(
6633 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6634 if (pending_vec < max_bits) {
66fd3f7f 6635 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6636 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6637 }
6638
3e6e0aab
GT		 6639 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6640 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6641 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6642 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6643 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6644 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6645
3e6e0aab
GT		 6646 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6647 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6648
5f0269f5
ME		 6649 update_cr8_intercept(vcpu);
6650
9c3e4aab 6651 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6652 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6653 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6654 !is_protmode(vcpu))
9c3e4aab
MT		 6655 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6656
3842d135
AK		 6657 kvm_make_request(KVM_REQ_EVENT, vcpu);
6658
b6c7a5dc
HB		 6659 return 0;
6660}
6661
d0bfb940
JK		 6662int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6663 struct kvm_guest_debug *dbg)
b6c7a5dc 6664{
355be0b9 6665 unsigned long rflags;
ae675ef0 6666 int i, r;
b6c7a5dc 6667
4f926bf2
JK		 6668 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6669 r = -EBUSY;
6670 if (vcpu->arch.exception.pending)
2122ff5e 6671 goto out;
4f926bf2
JK		 6672 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6673 kvm_queue_exception(vcpu, DB_VECTOR);
6674 else
6675 kvm_queue_exception(vcpu, BP_VECTOR);
6676 }
6677
91586a3b
JK		 6678 /*
6679 * Read rflags as long as potentially injected trace flags are still
6680 * filtered out.
6681 */
6682 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6683
6684 vcpu->guest_debug = dbg->control;
6685 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6686 vcpu->guest_debug = 0;
6687
6688 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6689 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6690 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6691 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6692 } else {
6693 for (i = 0; i < KVM_NR_DB_REGS; i++)
6694 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6695 }
c8639010 6696 kvm_update_dr7(vcpu);
ae675ef0 6697
f92653ee
JK		 6698 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6699 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6700 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6701
91586a3b
JK		 6702 /*
6703 * Trigger an rflags update that will inject or remove the trace
6704 * flags.
6705 */
6706 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6707
c8639010 6708 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6709
4f926bf2 6710 r = 0;
d0bfb940 6711
2122ff5e 6712out:
b6c7a5dc
HB		 6713
6714 return r;
6715}
6716
8b006791
ZX		 6717/*
6718 * Translate a guest virtual address to a guest physical address.
6719 */
6720int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6721 struct kvm_translation *tr)
6722{
6723 unsigned long vaddr = tr->linear_address;
6724 gpa_t gpa;
f656ce01 6725 int idx;
8b006791 6726
f656ce01 6727 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6728 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6729 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6730 tr->physical_address = gpa;
6731 tr->valid = gpa != UNMAPPED_GVA;
6732 tr->writeable = 1;
6733 tr->usermode = 0;
8b006791
ZX		 6734
6735 return 0;
6736}
6737
d0752060
HB		 6738int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6739{
98918833
SY		 6740 struct i387_fxsave_struct *fxsave =
6741 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6742
d0752060
HB		 6743 memcpy(fpu->fpr, fxsave->st_space, 128);
6744 fpu->fcw = fxsave->cwd;
6745 fpu->fsw = fxsave->swd;
6746 fpu->ftwx = fxsave->twd;
6747 fpu->last_opcode = fxsave->fop;
6748 fpu->last_ip = fxsave->rip;
6749 fpu->last_dp = fxsave->rdp;
6750 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6751
d0752060
HB		 6752 return 0;
6753}
6754
6755int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6756{
98918833
SY		 6757 struct i387_fxsave_struct *fxsave =
6758 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6759
d0752060
HB		 6760 memcpy(fxsave->st_space, fpu->fpr, 128);
6761 fxsave->cwd = fpu->fcw;
6762 fxsave->swd = fpu->fsw;
6763 fxsave->twd = fpu->ftwx;
6764 fxsave->fop = fpu->last_opcode;
6765 fxsave->rip = fpu->last_ip;
6766 fxsave->rdp = fpu->last_dp;
6767 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6768
d0752060
HB		 6769 return 0;
6770}
6771
10ab25cd 6772int fx_init(struct kvm_vcpu *vcpu)
d0752060 6773{
10ab25cd
JK		 6774 int err;
6775
6776 err = fpu_alloc(&vcpu->arch.guest_fpu);
6777 if (err)
6778 return err;
6779
98918833 6780 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6781
2acf923e
DC		 6782 /*
6783 * Ensure guest xcr0 is valid for loading
6784 */
6785 vcpu->arch.xcr0 = XSTATE_FP;
6786
ad312c7c 6787 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6788
6789 return 0;
d0752060
HB		 6790}
6791EXPORT_SYMBOL_GPL(fx_init);
6792
98918833
SY		 6793static void fx_free(struct kvm_vcpu *vcpu)
6794{
6795 fpu_free(&vcpu->arch.guest_fpu);
6796}
6797
d0752060
HB		 6798void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6799{
2608d7a1 6800 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6801 return;
6802
2acf923e
DC		 6803 /*
6804 * Restore all possible states in the guest,
6805 * and assume host would use all available bits.
6806 * Guest xcr0 would be loaded later.
6807 */
6808 kvm_put_guest_xcr0(vcpu);
d0752060 6809 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6810 __kernel_fpu_begin();
98918833 6811 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6812 trace_kvm_fpu(1);
d0752060 6813}
d0752060
HB		 6814
6815void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6816{
2acf923e
DC		 6817 kvm_put_guest_xcr0(vcpu);
6818
d0752060
HB		 6819 if (!vcpu->guest_fpu_loaded)
6820 return;
6821
6822 vcpu->guest_fpu_loaded = 0;
98918833 6823 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6824 __kernel_fpu_end();
f096ed85 6825 ++vcpu->stat.fpu_reload;
a8eeb04a 6826 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6827 trace_kvm_fpu(0);
d0752060 6828}
e9b11c17
ZX		 6829
6830void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6831{
12f9a48f 6832 kvmclock_reset(vcpu);
7f1ea208 6833
f5f48ee1 6834 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6835 fx_free(vcpu);
e9b11c17
ZX		 6836 kvm_x86_ops->vcpu_free(vcpu);
6837}
6838
6839struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6840 unsigned int id)
6841{
6755bae8
ZA		 6842 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6843 printk_once(KERN_WARNING
6844 "kvm: SMP vm created on host with unstable TSC; "
6845 "guest TSC will not be reliable\n");
26e5215f
AK		 6846 return kvm_x86_ops->vcpu_create(kvm, id);
6847}
e9b11c17 6848
26e5215f
AK		 6849int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6850{
6851 int r;
e9b11c17 6852
0bed3b56 6853 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6854 r = vcpu_load(vcpu);
6855 if (r)
6856 return r;
57f252f2 6857 kvm_vcpu_reset(vcpu);
8a3c1a33 6858 kvm_mmu_setup(vcpu);
e9b11c17 6859 vcpu_put(vcpu);
e9b11c17 6860
26e5215f 6861 return r;
e9b11c17
ZX		 6862}
6863
42897d86
MT		 6864int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6865{
6866 int r;
8fe8ab46 6867 struct msr_data msr;
332967a3 6868 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6869
6870 r = vcpu_load(vcpu);
6871 if (r)
6872 return r;
8fe8ab46
WA		 6873 msr.data = 0x0;
6874 msr.index = MSR_IA32_TSC;
6875 msr.host_initiated = true;
6876 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6877 vcpu_put(vcpu);
6878
332967a3
AJ		 6879 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6880 KVMCLOCK_SYNC_PERIOD);
6881
42897d86
MT		 6882 return r;
6883}
6884
d40ccc62 6885void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6886{
9fc77441 6887 int r;
344d9588
GN		 6888 vcpu->arch.apf.msr_val = 0;
6889
9fc77441
MT		 6890 r = vcpu_load(vcpu);
6891 BUG_ON(r);
e9b11c17
ZX		 6892 kvm_mmu_unload(vcpu);
6893 vcpu_put(vcpu);
6894
98918833 6895 fx_free(vcpu);
e9b11c17
ZX		 6896 kvm_x86_ops->vcpu_free(vcpu);
6897}
6898
66450a21 6899void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6900{
7460fb4a
AK		 6901 atomic_set(&vcpu->arch.nmi_queued, 0);
6902 vcpu->arch.nmi_pending = 0;
448fa4a9 6903 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6904 kvm_clear_interrupt_queue(vcpu);
6905 kvm_clear_exception_queue(vcpu);
448fa4a9 6906
42dbaa5a 6907 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6908 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6909 kvm_update_dr6(vcpu);
42dbaa5a 6910 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6911 kvm_update_dr7(vcpu);
42dbaa5a 6912
3842d135 6913 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6914 vcpu->arch.apf.msr_val = 0;
c9aaa895 6915 vcpu->arch.st.msr_val = 0;
3842d135 6916
12f9a48f
GC		 6917 kvmclock_reset(vcpu);
6918
af585b92
GN		 6919 kvm_clear_async_pf_completion_queue(vcpu);
6920 kvm_async_pf_hash_reset(vcpu);
6921 vcpu->arch.apf.halted = false;
3842d135 6922
f5132b01
GN		 6923 kvm_pmu_reset(vcpu);
6924
66f7b72e
JS		 6925 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6926 vcpu->arch.regs_avail = ~0;
6927 vcpu->arch.regs_dirty = ~0;
6928
57f252f2 6929 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6930}
6931
66450a21
JK		 6932void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6933{
6934 struct kvm_segment cs;
6935
6936 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6937 cs.selector = vector << 8;
6938 cs.base = vector << 12;
6939 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6940 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6941}
6942
10474ae8 6943int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6944{
ca84d1a2
ZA		 6945 struct kvm *kvm;
6946 struct kvm_vcpu *vcpu;
6947 int i;
0dd6a6ed
ZA		 6948 int ret;
6949 u64 local_tsc;
6950 u64 max_tsc = 0;
6951 bool stable, backwards_tsc = false;
18863bdd
AK		 6952
6953 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6954 ret = kvm_x86_ops->hardware_enable(garbage);
6955 if (ret != 0)
6956 return ret;
6957
6958 local_tsc = native_read_tsc();
6959 stable = !check_tsc_unstable();
6960 list_for_each_entry(kvm, &vm_list, vm_list) {
6961 kvm_for_each_vcpu(i, vcpu, kvm) {
6962 if (!stable && vcpu->cpu == smp_processor_id())
6963 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6964 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6965 backwards_tsc = true;
6966 if (vcpu->arch.last_host_tsc > max_tsc)
6967 max_tsc = vcpu->arch.last_host_tsc;
6968 }
6969 }
6970 }
6971
6972 /*
6973 * Sometimes, even reliable TSCs go backwards. This happens on
6974 * platforms that reset TSC during suspend or hibernate actions, but
6975 * maintain synchronization. We must compensate. Fortunately, we can
6976 * detect that condition here, which happens early in CPU bringup,
6977 * before any KVM threads can be running. Unfortunately, we can't
6978 * bring the TSCs fully up to date with real time, as we aren't yet far
6979 * enough into CPU bringup that we know how much real time has actually
6980 * elapsed; our helper function, get_kernel_ns() will be using boot
6981 * variables that haven't been updated yet.
6982 *
6983 * So we simply find the maximum observed TSC above, then record the
6984 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6985 * the adjustment will be applied. Note that we accumulate
6986 * adjustments, in case multiple suspend cycles happen before some VCPU
6987 * gets a chance to run again. In the event that no KVM threads get a
6988 * chance to run, we will miss the entire elapsed period, as we'll have
6989 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6990 * loose cycle time. This isn't too big a deal, since the loss will be
6991 * uniform across all VCPUs (not to mention the scenario is extremely
6992 * unlikely). It is possible that a second hibernate recovery happens
6993 * much faster than a first, causing the observed TSC here to be
6994 * smaller; this would require additional padding adjustment, which is
6995 * why we set last_host_tsc to the local tsc observed here.
6996 *
6997 * N.B. - this code below runs only on platforms with reliable TSC,
6998 * as that is the only way backwards_tsc is set above. Also note
6999 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7000 * have the same delta_cyc adjustment applied if backwards_tsc
7001 * is detected. Note further, this adjustment is only done once,
7002 * as we reset last_host_tsc on all VCPUs to stop this from being
7003 * called multiple times (one for each physical CPU bringup).
7004 *
4a969980 7005 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7006 * will be compensated by the logic in vcpu_load, which sets the TSC to
7007 * catchup mode. This will catchup all VCPUs to real time, but cannot
7008 * guarantee that they stay in perfect synchronization.
7009 */
7010 if (backwards_tsc) {
7011 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7012 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7013 list_for_each_entry(kvm, &vm_list, vm_list) {
7014 kvm_for_each_vcpu(i, vcpu, kvm) {
7015 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7016 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 7017 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
7018 &vcpu->requests);
0dd6a6ed
ZA		 7019 }
7020
7021 /*
7022 * We have to disable TSC offset matching.. if you were
7023 * booting a VM while issuing an S4 host suspend....
7024 * you may have some problem. Solving this issue is
7025 * left as an exercise to the reader.
7026 */
7027 kvm->arch.last_tsc_nsec = 0;
7028 kvm->arch.last_tsc_write = 0;
7029 }
7030
7031 }
7032 return 0;
e9b11c17
ZX		 7033}
7034
7035void kvm_arch_hardware_disable(void *garbage)
7036{
7037 kvm_x86_ops->hardware_disable(garbage);
3548bab5 7038 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 7039}
7040
7041int kvm_arch_hardware_setup(void)
7042{
7043 return kvm_x86_ops->hardware_setup();
7044}
7045
7046void kvm_arch_hardware_unsetup(void)
7047{
7048 kvm_x86_ops->hardware_unsetup();
7049}
7050
7051void kvm_arch_check_processor_compat(void *rtn)
7052{
7053 kvm_x86_ops->check_processor_compatibility(rtn);
7054}
7055
3e515705
AK		 7056bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7057{
7058 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7059}
7060
54e9818f
GN		 7061struct static_key kvm_no_apic_vcpu __read_mostly;
7062
e9b11c17
ZX		 7063int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7064{
7065 struct page *page;
7066 struct kvm *kvm;
7067 int r;
7068
7069 BUG_ON(vcpu->kvm == NULL);
7070 kvm = vcpu->kvm;
7071
6aef266c 7072 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7073 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7074 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7075 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7076 else
a4535290 7077 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7078
7079 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7080 if (!page) {
7081 r = -ENOMEM;
7082 goto fail;
7083 }
ad312c7c 7084 vcpu->arch.pio_data = page_address(page);
e9b11c17 7085
cc578287 7086 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7087
e9b11c17
ZX		 7088 r = kvm_mmu_create(vcpu);
7089 if (r < 0)
7090 goto fail_free_pio_data;
7091
7092 if (irqchip_in_kernel(kvm)) {
7093 r = kvm_create_lapic(vcpu);
7094 if (r < 0)
7095 goto fail_mmu_destroy;
54e9818f
GN		 7096 } else
7097 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7098
890ca9ae
HY		 7099 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7100 GFP_KERNEL);
7101 if (!vcpu->arch.mce_banks) {
7102 r = -ENOMEM;
443c39bc 7103 goto fail_free_lapic;
890ca9ae
HY		 7104 }
7105 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7106
f1797359
WY		 7107 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7108 r = -ENOMEM;
f5f48ee1 7109 goto fail_free_mce_banks;
f1797359 7110 }
f5f48ee1 7111
66f7b72e
JS		 7112 r = fx_init(vcpu);
7113 if (r)
7114 goto fail_free_wbinvd_dirty_mask;
7115
ba904635 7116 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7117 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7118
7119 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7120 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7121
af585b92 7122 kvm_async_pf_hash_reset(vcpu);
f5132b01 7123 kvm_pmu_init(vcpu);
af585b92 7124
e9b11c17 7125 return 0;
66f7b72e
JS		 7126fail_free_wbinvd_dirty_mask:
7127 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7128fail_free_mce_banks:
7129 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7130fail_free_lapic:
7131 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7132fail_mmu_destroy:
7133 kvm_mmu_destroy(vcpu);
7134fail_free_pio_data:
ad312c7c 7135 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7136fail:
7137 return r;
7138}
7139
7140void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7141{
f656ce01
MT		 7142 int idx;
7143
f5132b01 7144 kvm_pmu_destroy(vcpu);
36cb93fd 7145 kfree(vcpu->arch.mce_banks);
e9b11c17 7146 kvm_free_lapic(vcpu);
f656ce01 7147 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7148 kvm_mmu_destroy(vcpu);
f656ce01 7149 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7150 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7151 if (!irqchip_in_kernel(vcpu->kvm))
7152 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7153}
d19a9cd2 7154
e08b9637 7155int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7156{
e08b9637
CO		 7157 if (type)
7158 return -EINVAL;
7159
f05e70ac 7160 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7161 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7162 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7163 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7164
5550af4d
SY		 7165 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7166 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7167 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7168 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7169 &kvm->arch.irq_sources_bitmap);
5550af4d 7170
038f8c11 7171 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7172 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7173 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7174
7175 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7176
7e44e449 7177 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7178 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7179
d89f5eff 7180 return 0;
d19a9cd2
ZX		 7181}
7182
7183static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7184{
9fc77441
MT		 7185 int r;
7186 r = vcpu_load(vcpu);
7187 BUG_ON(r);
d19a9cd2
ZX		 7188 kvm_mmu_unload(vcpu);
7189 vcpu_put(vcpu);
7190}
7191
7192static void kvm_free_vcpus(struct kvm *kvm)
7193{
7194 unsigned int i;
988a2cae 7195 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7196
7197 /*
7198 * Unpin any mmu pages first.
7199 */
af585b92
GN		 7200 kvm_for_each_vcpu(i, vcpu, kvm) {
7201 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7202 kvm_unload_vcpu_mmu(vcpu);
af585b92 7203 }
988a2cae
GN		 7204 kvm_for_each_vcpu(i, vcpu, kvm)
7205 kvm_arch_vcpu_free(vcpu);
7206
7207 mutex_lock(&kvm->lock);
7208 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7209 kvm->vcpus[i] = NULL;
d19a9cd2 7210
988a2cae
GN		 7211 atomic_set(&kvm->online_vcpus, 0);
7212 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7213}
7214
ad8ba2cd
SY		 7215void kvm_arch_sync_events(struct kvm *kvm)
7216{
332967a3 7217 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7218 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7219 kvm_free_all_assigned_devices(kvm);
aea924f6 7220 kvm_free_pit(kvm);
ad8ba2cd
SY		 7221}
7222
d19a9cd2
ZX		 7223void kvm_arch_destroy_vm(struct kvm *kvm)
7224{
27469d29
AH		 7225 if (current->mm == kvm->mm) {
7226 /*
7227 * Free memory regions allocated on behalf of userspace,
7228 * unless the the memory map has changed due to process exit
7229 * or fd copying.
7230 */
7231 struct kvm_userspace_memory_region mem;
7232 memset(&mem, 0, sizeof(mem));
7233 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7234 kvm_set_memory_region(kvm, &mem);
7235
7236 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7237 kvm_set_memory_region(kvm, &mem);
7238
7239 mem.slot = TSS_PRIVATE_MEMSLOT;
7240 kvm_set_memory_region(kvm, &mem);
7241 }
6eb55818 7242 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7243 kfree(kvm->arch.vpic);
7244 kfree(kvm->arch.vioapic);
d19a9cd2 7245 kvm_free_vcpus(kvm);
3d45830c
AK		 7246 if (kvm->arch.apic_access_page)
7247 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7248 if (kvm->arch.ept_identity_pagetable)
7249 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7250 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7251}
0de10343 7252
5587027c 7253void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7254 struct kvm_memory_slot *dont)
7255{
7256 int i;
7257
d89cc617
TY		 7258 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7259 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7260 kvm_kvfree(free->arch.rmap[i]);
7261 free->arch.rmap[i] = NULL;
77d11309 7262 }
d89cc617
TY		 7263 if (i == 0)
7264 continue;
7265
7266 if (!dont || free->arch.lpage_info[i - 1] !=
7267 dont->arch.lpage_info[i - 1]) {
7268 kvm_kvfree(free->arch.lpage_info[i - 1]);
7269 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7270 }
7271 }
7272}
7273
5587027c
AK		 7274int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7275 unsigned long npages)
db3fe4eb
TY		 7276{
7277 int i;
7278
d89cc617 7279 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7280 unsigned long ugfn;
7281 int lpages;
d89cc617 7282 int level = i + 1;
db3fe4eb
TY		 7283
7284 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7285 slot->base_gfn, level) + 1;
7286
d89cc617
TY		 7287 slot->arch.rmap[i] =
7288 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7289 if (!slot->arch.rmap[i])
77d11309 7290 goto out_free;
d89cc617
TY		 7291 if (i == 0)
7292 continue;
77d11309 7293
d89cc617
TY		 7294 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7295 sizeof(*slot->arch.lpage_info[i - 1]));
7296 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7297 goto out_free;
7298
7299 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7300 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7301 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7302 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7303 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7304 /*
7305 * If the gfn and userspace address are not aligned wrt each
7306 * other, or if explicitly asked to, disable large page
7307 * support for this slot
7308 */
7309 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7310 !kvm_largepages_enabled()) {
7311 unsigned long j;
7312
7313 for (j = 0; j < lpages; ++j)
d89cc617 7314 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7315 }
7316 }
7317
7318 return 0;
7319
7320out_free:
d89cc617
TY		 7321 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7322 kvm_kvfree(slot->arch.rmap[i]);
7323 slot->arch.rmap[i] = NULL;
7324 if (i == 0)
7325 continue;
7326
7327 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7328 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7329 }
7330 return -ENOMEM;
7331}
7332
e59dbe09
TY		 7333void kvm_arch_memslots_updated(struct kvm *kvm)
7334{
e6dff7d1
TY		 7335 /*
7336 * memslots->generation has been incremented.
7337 * mmio generation may have reached its maximum value.
7338 */
7339 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7340}
7341
f7784b8e
MT		 7342int kvm_arch_prepare_memory_region(struct kvm *kvm,
7343 struct kvm_memory_slot *memslot,
f7784b8e 7344 struct kvm_userspace_memory_region *mem,
7b6195a9 7345 enum kvm_mr_change change)
0de10343 7346{
7a905b14
TY		 7347 /*
7348 * Only private memory slots need to be mapped here since
7349 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7350 */
7b6195a9 7351 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7352 unsigned long userspace_addr;
604b38ac 7353
7a905b14
TY		 7354 /*
7355 * MAP_SHARED to prevent internal slot pages from being moved
7356 * by fork()/COW.
7357 */
7b6195a9 7358 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7359 PROT_READ | PROT_WRITE,
7360 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7361
7a905b14
TY		 7362 if (IS_ERR((void *)userspace_addr))
7363 return PTR_ERR((void *)userspace_addr);
604b38ac 7364
7a905b14 7365 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7366 }
7367
f7784b8e
MT		 7368 return 0;
7369}
7370
7371void kvm_arch_commit_memory_region(struct kvm *kvm,
7372 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7373 const struct kvm_memory_slot *old,
7374 enum kvm_mr_change change)
f7784b8e
MT		 7375{
7376
8482644a 7377 int nr_mmu_pages = 0;
f7784b8e 7378
8482644a 7379 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7380 int ret;
7381
8482644a
TY		 7382 ret = vm_munmap(old->userspace_addr,
7383 old->npages * PAGE_SIZE);
f7784b8e
MT		 7384 if (ret < 0)
7385 printk(KERN_WARNING
7386 "kvm_vm_ioctl_set_memory_region: "
7387 "failed to munmap memory\n");
7388 }
7389
48c0e4e9
XG		 7390 if (!kvm->arch.n_requested_mmu_pages)
7391 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7392
48c0e4e9 7393 if (nr_mmu_pages)
0de10343 7394 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7395 /*
7396 * Write protect all pages for dirty logging.
c126d94f
XG		 7397 *
7398 * All the sptes including the large sptes which point to this
7399 * slot are set to readonly. We can not create any new large
7400 * spte on this slot until the end of the logging.
7401 *
7402 * See the comments in fast_page_fault().
c972f3b1 7403 */
8482644a 7404 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7405 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7406}
1d737c8a 7407
2df72e9b 7408void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7409{
6ca18b69 7410 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7411}
7412
2df72e9b
MT		 7413void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7414 struct kvm_memory_slot *slot)
7415{
6ca18b69 7416 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7417}
7418
1d737c8a
ZX		 7419int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7420{
b6b8a145
JK		 7421 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7422 kvm_x86_ops->check_nested_events(vcpu, false);
7423
af585b92
GN		 7424 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7425 !vcpu->arch.apf.halted)
7426 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7427 || kvm_apic_has_events(vcpu)
6aef266c 7428 || vcpu->arch.pv.pv_unhalted
7460fb4a 7429 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7430 (kvm_arch_interrupt_allowed(vcpu) &&
7431 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7432}
5736199a 7433
b6d33834 7434int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7435{
b6d33834 7436 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7437}
78646121
GN		 7438
7439int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7440{
7441 return kvm_x86_ops->interrupt_allowed(vcpu);
7442}
229456fc 7443
f92653ee
JK		 7444bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7445{
7446 unsigned long current_rip = kvm_rip_read(vcpu) +
7447 get_segment_base(vcpu, VCPU_SREG_CS);
7448
7449 return current_rip == linear_rip;
7450}
7451EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7452
94fe45da
JK		 7453unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7454{
7455 unsigned long rflags;
7456
7457 rflags = kvm_x86_ops->get_rflags(vcpu);
7458 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7459 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7460 return rflags;
7461}
7462EXPORT_SYMBOL_GPL(kvm_get_rflags);
7463
6addfc42 7464static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7465{
7466 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7467 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7468 rflags |= X86_EFLAGS_TF;
94fe45da 7469 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7470}
7471
7472void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7473{
7474 __kvm_set_rflags(vcpu, rflags);
3842d135 7475 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7476}
7477EXPORT_SYMBOL_GPL(kvm_set_rflags);
7478
56028d08
GN		 7479void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7480{
7481 int r;
7482
fb67e14f 7483 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7484 work->wakeup_all)
56028d08
GN		 7485 return;
7486
7487 r = kvm_mmu_reload(vcpu);
7488 if (unlikely(r))
7489 return;
7490
fb67e14f
XG		 7491 if (!vcpu->arch.mmu.direct_map &&
7492 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7493 return;
7494
56028d08
GN		 7495 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7496}
7497
af585b92
GN		 7498static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7499{
7500 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7501}
7502
7503static inline u32 kvm_async_pf_next_probe(u32 key)
7504{
7505 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7506}
7507
7508static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7509{
7510 u32 key = kvm_async_pf_hash_fn(gfn);
7511
7512 while (vcpu->arch.apf.gfns[key] != ~0)
7513 key = kvm_async_pf_next_probe(key);
7514
7515 vcpu->arch.apf.gfns[key] = gfn;
7516}
7517
7518static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7519{
7520 int i;
7521 u32 key = kvm_async_pf_hash_fn(gfn);
7522
7523 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7524 (vcpu->arch.apf.gfns[key] != gfn &&
7525 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7526 key = kvm_async_pf_next_probe(key);
7527
7528 return key;
7529}
7530
7531bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7532{
7533 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7534}
7535
7536static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7537{
7538 u32 i, j, k;
7539
7540 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7541 while (true) {
7542 vcpu->arch.apf.gfns[i] = ~0;
7543 do {
7544 j = kvm_async_pf_next_probe(j);
7545 if (vcpu->arch.apf.gfns[j] == ~0)
7546 return;
7547 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7548 /*
7549 * k lies cyclically in ]i,j]
7550 * | i.k.j |
7551 * |....j i.k.| or |.k..j i...|
7552 */
7553 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7554 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7555 i = j;
7556 }
7557}
7558
7c90705b
GN		 7559static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7560{
7561
7562 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7563 sizeof(val));
7564}
7565
af585b92
GN		 7566void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7567 struct kvm_async_pf *work)
7568{
6389ee94
AK		 7569 struct x86_exception fault;
7570
7c90705b 7571 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7572 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7573
7574 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7575 (vcpu->arch.apf.send_user_only &&
7576 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7577 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7578 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7579 fault.vector = PF_VECTOR;
7580 fault.error_code_valid = true;
7581 fault.error_code = 0;
7582 fault.nested_page_fault = false;
7583 fault.address = work->arch.token;
7584 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7585 }
af585b92
GN		 7586}
7587
7588void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7589 struct kvm_async_pf *work)
7590{
6389ee94
AK		 7591 struct x86_exception fault;
7592
7c90705b 7593 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7594 if (work->wakeup_all)
7c90705b
GN		 7595 work->arch.token = ~0; /* broadcast wakeup */
7596 else
7597 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7598
7599 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7600 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7601 fault.vector = PF_VECTOR;
7602 fault.error_code_valid = true;
7603 fault.error_code = 0;
7604 fault.nested_page_fault = false;
7605 fault.address = work->arch.token;
7606 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7607 }
e6d53e3b 7608 vcpu->arch.apf.halted = false;
a4fa1635 7609 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7610}
7611
7612bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7613{
7614 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7615 return true;
7616 else
7617 return !kvm_event_needs_reinjection(vcpu) &&
7618 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7619}
7620
e0f0bbc5
AW		 7621void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7622{
7623 atomic_inc(&kvm->arch.noncoherent_dma_count);
7624}
7625EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7626
7627void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7628{
7629 atomic_dec(&kvm->arch.noncoherent_dma_count);
7630}
7631EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7632
7633bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7634{
7635 return atomic_read(&kvm->arch.noncoherent_dma_count);
7636}
7637EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7638
229456fc
MT		 7639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7649EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7650EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7651EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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