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KVM: x86: rename argument to kvm_set_tsc_khz
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
42bdf991 703 kvm_put_guest_xcr0(vcpu);
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP;
727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
a03490ed 743 if (is_long_mode(vcpu)) {
0f12244f
GN		 744 if (!(cr4 & X86_CR4_PAE))
745 return 1;
a2edf57f
AK		 746 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
747 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 748 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
749 kvm_read_cr3(vcpu)))
0f12244f
GN		 750 return 1;
751
ad756a16
MJ		 752 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
753 if (!guest_cpuid_has_pcid(vcpu))
754 return 1;
755
756 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
757 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
758 return 1;
759 }
760
5e1746d6 761 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 762 return 1;
a03490ed 763
ad756a16
MJ		 764 if (((cr4 ^ old_cr4) & pdptr_bits) ||
765 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 766 kvm_mmu_reset_context(vcpu);
0f12244f 767
2acf923e 768 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 769 kvm_update_cpuid(vcpu);
2acf923e 770
0f12244f
GN		 771 return 0;
772}
2d3ad1f4 773EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 774
2390218b 775int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 776{
ac146235 777#ifdef CONFIG_X86_64
9d88fca7 778 cr3 &= ~CR3_PCID_INVD;
ac146235 779#endif
9d88fca7 780
9f8fe504 781 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 782 kvm_mmu_sync_roots(vcpu);
77c3913b 783 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 784 return 0;
d835dfec
AK		 785 }
786
a03490ed 787 if (is_long_mode(vcpu)) {
d9f89b88
JK		 788 if (cr3 & CR3_L_MODE_RESERVED_BITS)
789 return 1;
790 } else if (is_pae(vcpu) && is_paging(vcpu) &&
791 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 792 return 1;
a03490ed 793
0f12244f 794 vcpu->arch.cr3 = cr3;
aff48baa 795 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 796 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 800
eea1cff9 801int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 802{
0f12244f
GN		 803 if (cr8 & CR8_RESERVED_BITS)
804 return 1;
35754c98 805 if (lapic_in_kernel(vcpu))
a03490ed
CO		 806 kvm_lapic_set_tpr(vcpu, cr8);
807 else
ad312c7c 808 vcpu->arch.cr8 = cr8;
0f12244f
GN		 809 return 0;
810}
2d3ad1f4 811EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 812
2d3ad1f4 813unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 814{
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 return kvm_lapic_get_cr8(vcpu);
817 else
ad312c7c 818 return vcpu->arch.cr8;
a03490ed 819}
2d3ad1f4 820EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 821
ae561ede
NA		 822static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
823{
824 int i;
825
826 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
827 for (i = 0; i < KVM_NR_DB_REGS; i++)
828 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
830 }
831}
832
73aaf249
JK		 833static void kvm_update_dr6(struct kvm_vcpu *vcpu)
834{
835 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
836 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
837}
838
c8639010
JK		 839static void kvm_update_dr7(struct kvm_vcpu *vcpu)
840{
841 unsigned long dr7;
842
843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
844 dr7 = vcpu->arch.guest_debug_dr7;
845 else
846 dr7 = vcpu->arch.dr7;
847 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 848 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
849 if (dr7 & DR7_BP_EN_MASK)
850 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 851}
852
6f43ed01
NA		 853static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
854{
855 u64 fixed = DR6_FIXED_1;
856
857 if (!guest_cpuid_has_rtm(vcpu))
858 fixed |= DR6_RTM;
859 return fixed;
860}
861
338dbc97 862static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 863{
864 switch (dr) {
865 case 0 ... 3:
866 vcpu->arch.db[dr] = val;
867 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
868 vcpu->arch.eff_db[dr] = val;
869 break;
870 case 4:
020df079
GN		 871 /* fall through */
872 case 6:
338dbc97
GN		 873 if (val & 0xffffffff00000000ULL)
874 return -1; /* #GP */
6f43ed01 875 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 876 kvm_update_dr6(vcpu);
020df079
GN		 877 break;
878 case 5:
020df079
GN		 879 /* fall through */
880 default: /* 7 */
338dbc97
GN		 881 if (val & 0xffffffff00000000ULL)
882 return -1; /* #GP */
020df079 883 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 884 kvm_update_dr7(vcpu);
020df079
GN		 885 break;
886 }
887
888 return 0;
889}
338dbc97
GN		 890
891int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
892{
16f8a6f9 893 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 894 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 895 return 1;
896 }
897 return 0;
338dbc97 898}
020df079
GN		 899EXPORT_SYMBOL_GPL(kvm_set_dr);
900
16f8a6f9 901int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 902{
903 switch (dr) {
904 case 0 ... 3:
905 *val = vcpu->arch.db[dr];
906 break;
907 case 4:
020df079
GN		 908 /* fall through */
909 case 6:
73aaf249
JK		 910 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
911 *val = vcpu->arch.dr6;
912 else
913 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 914 break;
915 case 5:
020df079
GN		 916 /* fall through */
917 default: /* 7 */
918 *val = vcpu->arch.dr7;
919 break;
920 }
338dbc97
GN		 921 return 0;
922}
020df079
GN		 923EXPORT_SYMBOL_GPL(kvm_get_dr);
924
022cd0e8
AK		 925bool kvm_rdpmc(struct kvm_vcpu *vcpu)
926{
927 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
928 u64 data;
929 int err;
930
c6702c9d 931 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 932 if (err)
933 return err;
934 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
935 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
936 return err;
937}
938EXPORT_SYMBOL_GPL(kvm_rdpmc);
939
043405e1
CO		 940/*
941 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
942 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
943 *
944 * This list is modified at module load time to reflect the
e3267cbb 945 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 946 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
947 * may depend on host virtualization features rather than host cpu features.
043405e1 948 */
e3267cbb 949
043405e1
CO		 950static u32 msrs_to_save[] = {
951 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 952 MSR_STAR,
043405e1
CO		 953#ifdef CONFIG_X86_64
954 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
955#endif
b3897a49 956 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 957 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 958};
959
960static unsigned num_msrs_to_save;
961
62ef68bb
PB		 962static u32 emulated_msrs[] = {
963 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
964 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
965 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
966 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 967 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
968 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 969 HV_X64_MSR_RESET,
11c4b1ca 970 HV_X64_MSR_VP_INDEX,
9eec50b8 971 HV_X64_MSR_VP_RUNTIME,
5c919412 972 HV_X64_MSR_SCONTROL,
1f4b34f8 973 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 974 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
975 MSR_KVM_PV_EOI_EN,
976
ba904635 977 MSR_IA32_TSC_ADJUST,
a3e06bbe 978 MSR_IA32_TSCDEADLINE,
043405e1 979 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 980 MSR_IA32_MCG_STATUS,
981 MSR_IA32_MCG_CTL,
64d60670 982 MSR_IA32_SMBASE,
043405e1
CO		 983};
984
62ef68bb
PB		 985static unsigned num_emulated_msrs;
986
384bb783 987bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 988{
b69e8cae 989 if (efer & efer_reserved_bits)
384bb783 990 return false;
15c4a640 991
1b2fd70c
AG		 992 if (efer & EFER_FFXSR) {
993 struct kvm_cpuid_entry2 *feat;
994
995 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 996 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 997 return false;
1b2fd70c
AG		 998 }
999
d8017474
AG		 1000 if (efer & EFER_SVME) {
1001 struct kvm_cpuid_entry2 *feat;
1002
1003 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1004 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1005 return false;
d8017474
AG		 1006 }
1007
384bb783
JK		 1008 return true;
1009}
1010EXPORT_SYMBOL_GPL(kvm_valid_efer);
1011
1012static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1013{
1014 u64 old_efer = vcpu->arch.efer;
1015
1016 if (!kvm_valid_efer(vcpu, efer))
1017 return 1;
1018
1019 if (is_paging(vcpu)
1020 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1021 return 1;
1022
15c4a640 1023 efer &= ~EFER_LMA;
f6801dff 1024 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1025
a3d204e2
SY		 1026 kvm_x86_ops->set_efer(vcpu, efer);
1027
aad82703
SY		 1028 /* Update reserved bits */
1029 if ((efer ^ old_efer) & EFER_NX)
1030 kvm_mmu_reset_context(vcpu);
1031
b69e8cae 1032 return 0;
15c4a640
CO		 1033}
1034
f2b4b7dd
JR		 1035void kvm_enable_efer_bits(u64 mask)
1036{
1037 efer_reserved_bits &= ~mask;
1038}
1039EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1040
15c4a640
CO		 1041/*
1042 * Writes msr value into into the appropriate "register".
1043 * Returns 0 on success, non-0 otherwise.
1044 * Assumes vcpu_load() was already called.
1045 */
8fe8ab46 1046int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1047{
854e8bb1
NA		 1048 switch (msr->index) {
1049 case MSR_FS_BASE:
1050 case MSR_GS_BASE:
1051 case MSR_KERNEL_GS_BASE:
1052 case MSR_CSTAR:
1053 case MSR_LSTAR:
1054 if (is_noncanonical_address(msr->data))
1055 return 1;
1056 break;
1057 case MSR_IA32_SYSENTER_EIP:
1058 case MSR_IA32_SYSENTER_ESP:
1059 /*
1060 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1061 * non-canonical address is written on Intel but not on
1062 * AMD (which ignores the top 32-bits, because it does
1063 * not implement 64-bit SYSENTER).
1064 *
1065 * 64-bit code should hence be able to write a non-canonical
1066 * value on AMD. Making the address canonical ensures that
1067 * vmentry does not fail on Intel after writing a non-canonical
1068 * value, and that something deterministic happens if the guest
1069 * invokes 64-bit SYSENTER.
1070 */
1071 msr->data = get_canonical(msr->data);
1072 }
8fe8ab46 1073 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1074}
854e8bb1 1075EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1076
313a3dc7
CO		 1077/*
1078 * Adapt set_msr() to msr_io()'s calling convention
1079 */
609e36d3
PB		 1080static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1081{
1082 struct msr_data msr;
1083 int r;
1084
1085 msr.index = index;
1086 msr.host_initiated = true;
1087 r = kvm_get_msr(vcpu, &msr);
1088 if (r)
1089 return r;
1090
1091 *data = msr.data;
1092 return 0;
1093}
1094
313a3dc7
CO		 1095static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1096{
8fe8ab46
WA		 1097 struct msr_data msr;
1098
1099 msr.data = *data;
1100 msr.index = index;
1101 msr.host_initiated = true;
1102 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1103}
1104
16e8d74d
MT		 1105#ifdef CONFIG_X86_64
1106struct pvclock_gtod_data {
1107 seqcount_t seq;
1108
1109 struct { /* extract of a clocksource struct */
1110 int vclock_mode;
1111 cycle_t cycle_last;
1112 cycle_t mask;
1113 u32 mult;
1114 u32 shift;
1115 } clock;
1116
cbcf2dd3
TG		 1117 u64 boot_ns;
1118 u64 nsec_base;
16e8d74d
MT		 1119};
1120
1121static struct pvclock_gtod_data pvclock_gtod_data;
1122
1123static void update_pvclock_gtod(struct timekeeper *tk)
1124{
1125 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1126 u64 boot_ns;
1127
876e7881 1128 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1129
1130 write_seqcount_begin(&vdata->seq);
1131
1132 /* copy pvclock gtod data */
876e7881
PZ		 1133 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1134 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1135 vdata->clock.mask = tk->tkr_mono.mask;
1136 vdata->clock.mult = tk->tkr_mono.mult;
1137 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1138
cbcf2dd3 1139 vdata->boot_ns = boot_ns;
876e7881 1140 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1141
1142 write_seqcount_end(&vdata->seq);
1143}
1144#endif
1145
bab5bb39
NK		 1146void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1147{
1148 /*
1149 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1150 * vcpu_enter_guest. This function is only called from
1151 * the physical CPU that is running vcpu.
1152 */
1153 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1154}
16e8d74d 1155
18068523
GOC		 1156static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1157{
9ed3c444
AK		 1158 int version;
1159 int r;
50d0a0f9 1160 struct pvclock_wall_clock wc;
923de3cf 1161 struct timespec boot;
18068523
GOC		 1162
1163 if (!wall_clock)
1164 return;
1165
9ed3c444
AK		 1166 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1167 if (r)
1168 return;
1169
1170 if (version & 1)
1171 ++version; /* first time write, random junk */
1172
1173 ++version;
18068523 1174
1dab1345
NK		 1175 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1176 return;
18068523 1177
50d0a0f9
GH		 1178 /*
1179 * The guest calculates current wall clock time by adding
34c238a1 1180 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1181 * wall clock specified here. guest system time equals host
1182 * system time for us, thus we must fill in host boot time here.
1183 */
923de3cf 1184 getboottime(&boot);
50d0a0f9 1185
4b648665
BR		 1186 if (kvm->arch.kvmclock_offset) {
1187 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1188 boot = timespec_sub(boot, ts);
1189 }
50d0a0f9
GH		 1190 wc.sec = boot.tv_sec;
1191 wc.nsec = boot.tv_nsec;
1192 wc.version = version;
18068523
GOC		 1193
1194 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1195
1196 version++;
1197 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1198}
1199
50d0a0f9
GH		 1200static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1201{
b51012de
PB		 1202 do_shl32_div32(dividend, divisor);
1203 return dividend;
50d0a0f9
GH		 1204}
1205
5f4e3f88
ZA		 1206static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1207 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1208{
5f4e3f88 1209 uint64_t scaled64;
50d0a0f9
GH		 1210 int32_t shift = 0;
1211 uint64_t tps64;
1212 uint32_t tps32;
1213
5f4e3f88
ZA		 1214 tps64 = base_khz * 1000LL;
1215 scaled64 = scaled_khz * 1000LL;
50933623 1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1217 tps64 >>= 1;
1218 shift--;
1219 }
1220
1221 tps32 = (uint32_t)tps64;
50933623
JK		 1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1224 scaled64 >>= 1;
1225 else
1226 tps32 <<= 1;
50d0a0f9
GH		 1227 shift++;
1228 }
1229
5f4e3f88
ZA		 1230 *pshift = shift;
1231 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1232
5f4e3f88
ZA		 1233 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1234 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1235}
1236
d828199e 1237#ifdef CONFIG_X86_64
16e8d74d 1238static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1239#endif
16e8d74d 1240
c8076604 1241static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1242static unsigned long max_tsc_khz;
c8076604 1243
cc578287 1244static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1245{
cc578287
ZA		 1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1248}
1249
cc578287 1250static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1251{
cc578287
ZA		 1252 u64 v = (u64)khz * (1000000 + ppm);
1253 do_div(v, 1000000);
1254 return v;
1e993611
JR		 1255}
1256
381d585c
HZ		 1257static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1258{
1259 u64 ratio;
1260
1261 /* Guest TSC same frequency as host TSC? */
1262 if (!scale) {
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1264 return 0;
1265 }
1266
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1272 return 0;
1273 } else {
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1282
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1285 user_tsc_khz);
1286 return -1;
1287 }
1288
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1290 return 0;
1291}
1292
4941b8cb 1293static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1294{
cc578287
ZA		 1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
217fc9cf 1297
03ba32ca 1298 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1299 if (user_tsc_khz == 0) {
ad721883
HZ		 1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1302 return -1;
ad721883 1303 }
03ba32ca 1304
c285545f 1305 /* Compute a scale to convert nanoseconds in TSC cycles */
4941b8cb 1306 kvm_get_time_scale(user_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1309 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1310
1311 /*
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1316 */
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1319 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1321 use_scaling = 1;
1322 }
4941b8cb 1323 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1324}
1325
1326static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1327{
e26101b1 1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
e26101b1 1331 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1332 return tsc;
1333}
1334
69b0049a 1335static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1336{
1337#ifdef CONFIG_X86_64
1338 bool vcpus_matched;
b48aa97e
MT		 1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1341
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1344
7f187922
MT		 1345 /*
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1348 *
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1352 */
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1356
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1360#endif
1361}
1362
ba904635
WA		 1363static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1364{
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1367}
1368
35181e86
HZ		 1369/*
1370 * Multiply tsc by a fixed point number represented by ratio.
1371 *
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1376 *
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1378 */
1379static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1380{
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1382}
1383
1384u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1385{
1386 u64 _tsc = tsc;
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1388
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1391
1392 return _tsc;
1393}
1394EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1395
07c1419a
HZ		 1396static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1397{
1398 u64 tsc;
1399
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1401
1402 return target_tsc - tsc;
1403}
1404
4ba76538
HZ		 1405u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1406{
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1408}
1409EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1410
8fe8ab46 1411void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1412{
1413 struct kvm *kvm = vcpu->kvm;
f38e098f 1414 u64 offset, ns, elapsed;
99e3e30a 1415 unsigned long flags;
02626b6a 1416 s64 usdiff;
b48aa97e 1417 bool matched;
0d3da0d2 1418 bool already_matched;
8fe8ab46 1419 u64 data = msr->data;
99e3e30a 1420
038f8c11 1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1422 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1423 ns = get_kernel_ns();
f38e098f 1424 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1425
03ba32ca 1426 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1427 int faulted = 0;
1428
03ba32ca
MT		 1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1431#ifdef CONFIG_X86_64
03ba32ca 1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1433#else
03ba32ca 1434 /* do_div() only does unsigned */
8915aa27
MT		 1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1438 "3:\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1441 " jmp 3b\n"
1442 ".previous\n"
1443
1444 _ASM_EXTABLE(1b, 4b)
1445
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1448
5d3cb0f6 1449#endif
03ba32ca
MT		 1450 do_div(elapsed, 1000);
1451 usdiff -= elapsed;
1452 if (usdiff < 0)
1453 usdiff = -usdiff;
8915aa27
MT		 1454
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1456 if (faulted)
1457 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1458 } else
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1460
1461 /*
5d3cb0f6
ZA		 1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1465 *
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1470 */
02626b6a 1471 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1473 if (!check_tsc_unstable()) {
e26101b1 1474 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1476 } else {
857e4099 1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1478 data += delta;
07c1419a 1479 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1481 }
b48aa97e 1482 matched = true;
0d3da0d2 1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1484 } else {
1485 /*
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
4a969980 1490 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1491 *
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1493 */
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1498 matched = false;
0d3da0d2 1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1500 kvm->arch.cur_tsc_generation, data);
f38e098f 1501 }
e26101b1
ZA		 1502
1503 /*
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1506 */
f38e098f
ZA		 1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
5d3cb0f6 1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1510
b183aa58 1511 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1512
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1517
ba904635
WA		 1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1522
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1524 if (!matched) {
b48aa97e 1525 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1528 }
b48aa97e
MT		 1529
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1532}
e26101b1 1533
99e3e30a
ZA		 1534EXPORT_SYMBOL_GPL(kvm_write_tsc);
1535
58ea6767
HZ		 1536static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1537 s64 adjustment)
1538{
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1540}
1541
1542static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1543{
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1548}
1549
d828199e
MT		 1550#ifdef CONFIG_X86_64
1551
1552static cycle_t read_tsc(void)
1553{
03b9730b
AL		 1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1556
1557 if (likely(ret >= last))
1558 return ret;
1559
1560 /*
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1567 */
1568 asm volatile ("");
1569 return last;
1570}
1571
1572static inline u64 vgettsc(cycle_t *cycle_now)
1573{
1574 long v;
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1576
1577 *cycle_now = read_tsc();
1578
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1581}
1582
cbcf2dd3 1583static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1584{
cbcf2dd3 1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1586 unsigned long seq;
d828199e 1587 int mode;
cbcf2dd3 1588 u64 ns;
d828199e 1589
d828199e
MT		 1590 do {
1591 seq = read_seqcount_begin(&gtod->seq);
1592 mode = gtod->clock.vclock_mode;
cbcf2dd3 1593 ns = gtod->nsec_base;
d828199e
MT		 1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
cbcf2dd3 1596 ns += gtod->boot_ns;
d828199e 1597 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1598 *t = ns;
d828199e
MT		 1599
1600 return mode;
1601}
1602
1603/* returns true if host is using tsc clocksource */
1604static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1605{
d828199e
MT		 1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1608 return false;
1609
cbcf2dd3 1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1611}
1612#endif
1613
1614/*
1615 *
b48aa97e
MT		 1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
d828199e
MT		 1619 * CPUs at the next numbered event.
1620 *
1621 * "timespecX" represents host monotonic time. "tscX" represents
1622 * RDTSC value.
1623 *
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1625 *
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1628 * | tsc1 = tsc0 + M
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1633 *
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1635 *
1636 * - ret0 < ret1
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1638 * ...
1639 * - 0 < N - M => M < N
1640 *
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1645 *
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1649 * in lockstep.
1650 *
b48aa97e 1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1652 *
1653 */
1654
1655static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1656{
1657#ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1659 int vclock_mode;
b48aa97e
MT		 1660 bool host_tsc_clocksource, vcpus_matched;
1661
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1664
1665 /*
1666 * If the host uses TSC clock, then passthrough TSC as stable
1667 * to the guest.
1668 */
b48aa97e 1669 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1672
16a96021 1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1676
d828199e
MT		 1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1679
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1682 vcpus_matched);
d828199e
MT		 1683#endif
1684}
1685
2860c4b1
PB		 1686void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1687{
1688 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1689}
1690
2e762ff7
MT		 1691static void kvm_gen_update_masterclock(struct kvm *kvm)
1692{
1693#ifdef CONFIG_X86_64
1694 int i;
1695 struct kvm_vcpu *vcpu;
1696 struct kvm_arch *ka = &kvm->arch;
1697
1698 spin_lock(&ka->pvclock_gtod_sync_lock);
1699 kvm_make_mclock_inprogress_request(kvm);
1700 /* no guest entries from this point */
1701 pvclock_update_vm_gtod_copy(kvm);
1702
1703 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1705
1706 /* guest entries allowed */
1707 kvm_for_each_vcpu(i, vcpu, kvm)
1708 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1709
1710 spin_unlock(&ka->pvclock_gtod_sync_lock);
1711#endif
1712}
1713
34c238a1 1714static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1715{
27cca94e 1716 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1717 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1718 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1719 s64 kernel_ns;
d828199e 1720 u64 tsc_timestamp, host_tsc;
0b79459b 1721 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1722 u8 pvclock_flags;
d828199e
MT		 1723 bool use_master_clock;
1724
1725 kernel_ns = 0;
1726 host_tsc = 0;
18068523 1727
d828199e
MT		 1728 /*
1729 * If the host uses TSC clock, then passthrough TSC as stable
1730 * to the guest.
1731 */
1732 spin_lock(&ka->pvclock_gtod_sync_lock);
1733 use_master_clock = ka->use_master_clock;
1734 if (use_master_clock) {
1735 host_tsc = ka->master_cycle_now;
1736 kernel_ns = ka->master_kernel_ns;
1737 }
1738 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1739
1740 /* Keep irq disabled to prevent changes to the clock */
1741 local_irq_save(flags);
89cbc767 1742 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1743 if (unlikely(this_tsc_khz == 0)) {
1744 local_irq_restore(flags);
1745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1746 return 1;
1747 }
d828199e 1748 if (!use_master_clock) {
4ea1636b 1749 host_tsc = rdtsc();
d828199e
MT		 1750 kernel_ns = get_kernel_ns();
1751 }
1752
4ba76538 1753 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1754
c285545f
ZA		 1755 /*
1756 * We may have to catch up the TSC to match elapsed wall clock
1757 * time for two reasons, even if kvmclock is used.
1758 * 1) CPU could have been running below the maximum TSC rate
1759 * 2) Broken TSC compensation resets the base at each VCPU
1760 * entry to avoid unknown leaps of TSC even when running
1761 * again on the same CPU. This may cause apparent elapsed
1762 * time to disappear, and the guest to stand still or run
1763 * very slowly.
1764 */
1765 if (vcpu->tsc_catchup) {
1766 u64 tsc = compute_guest_tsc(v, kernel_ns);
1767 if (tsc > tsc_timestamp) {
f1e2b260 1768 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1769 tsc_timestamp = tsc;
1770 }
50d0a0f9
GH		 1771 }
1772
18068523
GOC		 1773 local_irq_restore(flags);
1774
0b79459b 1775 if (!vcpu->pv_time_enabled)
c285545f 1776 return 0;
18068523 1777
e48672fa 1778 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1779 tgt_tsc_khz = kvm_has_tsc_control ?
1780 vcpu->virtual_tsc_khz : this_tsc_khz;
1781 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1782 &vcpu->hv_clock.tsc_shift,
1783 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1784 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1785 }
1786
1787 /* With all the info we got, fill in the values */
1d5f066e 1788 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1789 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1790 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1791
09a0c3f1
OH		 1792 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1793 &guest_hv_clock, sizeof(guest_hv_clock))))
1794 return 0;
1795
5dca0d91
RK		 1796 /* This VCPU is paused, but it's legal for a guest to read another
1797 * VCPU's kvmclock, so we really have to follow the specification where
1798 * it says that version is odd if data is being modified, and even after
1799 * it is consistent.
1800 *
1801 * Version field updates must be kept separate. This is because
1802 * kvm_write_guest_cached might use a "rep movs" instruction, and
1803 * writes within a string instruction are weakly ordered. So there
1804 * are three writes overall.
1805 *
1806 * As a small optimization, only write the version field in the first
1807 * and third write. The vcpu->pv_time cache is still valid, because the
1808 * version field is the first in the struct.
18068523 1809 */
5dca0d91
RK		 1810 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1811
1812 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1813 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1814 &vcpu->hv_clock,
1815 sizeof(vcpu->hv_clock.version));
1816
1817 smp_wmb();
78c0337a
MT		 1818
1819 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1820 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1821
1822 if (vcpu->pvclock_set_guest_stopped_request) {
1823 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1824 vcpu->pvclock_set_guest_stopped_request = false;
1825 }
1826
d828199e
MT		 1827 /* If the host uses TSC clocksource, then it is stable */
1828 if (use_master_clock)
1829 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1830
78c0337a
MT		 1831 vcpu->hv_clock.flags = pvclock_flags;
1832
ce1a5e60
DM		 1833 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1834
0b79459b
AH		 1835 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1838
1839 smp_wmb();
1840
1841 vcpu->hv_clock.version++;
1842 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1843 &vcpu->hv_clock,
1844 sizeof(vcpu->hv_clock.version));
8cfdc000 1845 return 0;
c8076604
GH		 1846}
1847
0061d53d
MT		 1848/*
1849 * kvmclock updates which are isolated to a given vcpu, such as
1850 * vcpu->cpu migration, should not allow system_timestamp from
1851 * the rest of the vcpus to remain static. Otherwise ntp frequency
1852 * correction applies to one vcpu's system_timestamp but not
1853 * the others.
1854 *
1855 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1856 * We need to rate-limit these requests though, as they can
1857 * considerably slow guests that have a large number of vcpus.
1858 * The time for a remote vcpu to update its kvmclock is bound
1859 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1860 */
1861
7e44e449
AJ		 1862#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1863
1864static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1865{
1866 int i;
7e44e449
AJ		 1867 struct delayed_work *dwork = to_delayed_work(work);
1868 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1869 kvmclock_update_work);
1870 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1871 struct kvm_vcpu *vcpu;
1872
1873 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1874 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1875 kvm_vcpu_kick(vcpu);
1876 }
1877}
1878
7e44e449
AJ		 1879static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1880{
1881 struct kvm *kvm = v->kvm;
1882
105b21bb 1883 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1884 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1885 KVMCLOCK_UPDATE_DELAY);
1886}
1887
332967a3
AJ		 1888#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1889
1890static void kvmclock_sync_fn(struct work_struct *work)
1891{
1892 struct delayed_work *dwork = to_delayed_work(work);
1893 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1894 kvmclock_sync_work);
1895 struct kvm *kvm = container_of(ka, struct kvm, arch);
1896
630994b3
MT		 1897 if (!kvmclock_periodic_sync)
1898 return;
1899
332967a3
AJ		 1900 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1901 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1902 KVMCLOCK_SYNC_PERIOD);
1903}
1904
890ca9ae 1905static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1906{
890ca9ae
HY		 1907 u64 mcg_cap = vcpu->arch.mcg_cap;
1908 unsigned bank_num = mcg_cap & 0xff;
1909
15c4a640 1910 switch (msr) {
15c4a640 1911 case MSR_IA32_MCG_STATUS:
890ca9ae 1912 vcpu->arch.mcg_status = data;
15c4a640 1913 break;
c7ac679c 1914 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1915 if (!(mcg_cap & MCG_CTL_P))
1916 return 1;
1917 if (data != 0 && data != ~(u64)0)
1918 return -1;
1919 vcpu->arch.mcg_ctl = data;
1920 break;
1921 default:
1922 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1923 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1924 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1925 /* only 0 or all 1s can be written to IA32_MCi_CTL
1926 * some Linux kernels though clear bit 10 in bank 4 to
1927 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1928 * this to avoid an uncatched #GP in the guest
1929 */
890ca9ae 1930 if ((offset & 0x3) == 0 &&
114be429 1931 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1932 return -1;
1933 vcpu->arch.mce_banks[offset] = data;
1934 break;
1935 }
1936 return 1;
1937 }
1938 return 0;
1939}
1940
ffde22ac
ES		 1941static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1942{
1943 struct kvm *kvm = vcpu->kvm;
1944 int lm = is_long_mode(vcpu);
1945 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1946 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1947 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1948 : kvm->arch.xen_hvm_config.blob_size_32;
1949 u32 page_num = data & ~PAGE_MASK;
1950 u64 page_addr = data & PAGE_MASK;
1951 u8 *page;
1952 int r;
1953
1954 r = -E2BIG;
1955 if (page_num >= blob_size)
1956 goto out;
1957 r = -ENOMEM;
ff5c2c03
SL		 1958 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1959 if (IS_ERR(page)) {
1960 r = PTR_ERR(page);
ffde22ac 1961 goto out;
ff5c2c03 1962 }
54bf36aa 1963 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1964 goto out_free;
1965 r = 0;
1966out_free:
1967 kfree(page);
1968out:
1969 return r;
1970}
1971
344d9588
GN		 1972static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1973{
1974 gpa_t gpa = data & ~0x3f;
1975
4a969980 1976 /* Bits 2:5 are reserved, Should be zero */
6adba527 1977 if (data & 0x3c)
344d9588
GN		 1978 return 1;
1979
1980 vcpu->arch.apf.msr_val = data;
1981
1982 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1983 kvm_clear_async_pf_completion_queue(vcpu);
1984 kvm_async_pf_hash_reset(vcpu);
1985 return 0;
1986 }
1987
8f964525
AH		 1988 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1989 sizeof(u32)))
344d9588
GN		 1990 return 1;
1991
6adba527 1992 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1993 kvm_async_pf_wakeup_all(vcpu);
1994 return 0;
1995}
1996
12f9a48f
GC		 1997static void kvmclock_reset(struct kvm_vcpu *vcpu)
1998{
0b79459b 1999 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2000}
2001
c9aaa895
GC		 2002static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2003{
2004 u64 delta;
2005
2006 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2007 return;
2008
2009 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2010 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2011 vcpu->arch.st.accum_steal = delta;
2012}
2013
2014static void record_steal_time(struct kvm_vcpu *vcpu)
2015{
7cae2bed
MT		 2016 accumulate_steal_time(vcpu);
2017
c9aaa895
GC		 2018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2019 return;
2020
2021 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2022 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2023 return;
2024
2025 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2026 vcpu->arch.st.steal.version += 2;
2027 vcpu->arch.st.accum_steal = 0;
2028
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2031}
2032
8fe8ab46 2033int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2034{
5753785f 2035 bool pr = false;
8fe8ab46
WA		 2036 u32 msr = msr_info->index;
2037 u64 data = msr_info->data;
5753785f 2038
15c4a640 2039 switch (msr) {
2e32b719
BP		 2040 case MSR_AMD64_NB_CFG:
2041 case MSR_IA32_UCODE_REV:
2042 case MSR_IA32_UCODE_WRITE:
2043 case MSR_VM_HSAVE_PA:
2044 case MSR_AMD64_PATCH_LOADER:
2045 case MSR_AMD64_BU_CFG2:
2046 break;
2047
15c4a640 2048 case MSR_EFER:
b69e8cae 2049 return set_efer(vcpu, data);
8f1589d9
AP		 2050 case MSR_K7_HWCR:
2051 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2052 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2053 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2054 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2055 if (data != 0) {
a737f256
CD		 2056 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2057 data);
8f1589d9
AP		 2058 return 1;
2059 }
15c4a640 2060 break;
f7c6d140
AP		 2061 case MSR_FAM10H_MMIO_CONF_BASE:
2062 if (data != 0) {
a737f256
CD		 2063 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2064 "0x%llx\n", data);
f7c6d140
AP		 2065 return 1;
2066 }
15c4a640 2067 break;
b5e2fec0
AG		 2068 case MSR_IA32_DEBUGCTLMSR:
2069 if (!data) {
2070 /* We support the non-activated case already */
2071 break;
2072 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2073 /* Values other than LBR and BTF are vendor-specific,
2074 thus reserved and should throw a #GP */
2075 return 1;
2076 }
a737f256
CD		 2077 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2078 __func__, data);
b5e2fec0 2079 break;
9ba075a6 2080 case 0x200 ... 0x2ff:
ff53604b 2081 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2082 case MSR_IA32_APICBASE:
58cb628d 2083 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2084 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2085 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2086 case MSR_IA32_TSCDEADLINE:
2087 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2088 break;
ba904635
WA		 2089 case MSR_IA32_TSC_ADJUST:
2090 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2091 if (!msr_info->host_initiated) {
d913b904 2092 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2093 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2094 }
2095 vcpu->arch.ia32_tsc_adjust_msr = data;
2096 }
2097 break;
15c4a640 2098 case MSR_IA32_MISC_ENABLE:
ad312c7c 2099 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2100 break;
64d60670
PB		 2101 case MSR_IA32_SMBASE:
2102 if (!msr_info->host_initiated)
2103 return 1;
2104 vcpu->arch.smbase = data;
2105 break;
11c6bffa 2106 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2107 case MSR_KVM_WALL_CLOCK:
2108 vcpu->kvm->arch.wall_clock = data;
2109 kvm_write_wall_clock(vcpu->kvm, data);
2110 break;
11c6bffa 2111 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2112 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2113 u64 gpa_offset;
54750f2c
MT		 2114 struct kvm_arch *ka = &vcpu->kvm->arch;
2115
12f9a48f 2116 kvmclock_reset(vcpu);
18068523 2117
54750f2c
MT		 2118 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2119 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2120
2121 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2122 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2123 &vcpu->requests);
2124
2125 ka->boot_vcpu_runs_old_kvmclock = tmp;
2126 }
2127
18068523 2128 vcpu->arch.time = data;
0061d53d 2129 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2130
2131 /* we verify if the enable bit is set... */
2132 if (!(data & 1))
2133 break;
2134
0b79459b 2135 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2136
0b79459b 2137 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2138 &vcpu->arch.pv_time, data & ~1ULL,
2139 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2140 vcpu->arch.pv_time_enabled = false;
2141 else
2142 vcpu->arch.pv_time_enabled = true;
32cad84f 2143
18068523
GOC		 2144 break;
2145 }
344d9588
GN		 2146 case MSR_KVM_ASYNC_PF_EN:
2147 if (kvm_pv_enable_async_pf(vcpu, data))
2148 return 1;
2149 break;
c9aaa895
GC		 2150 case MSR_KVM_STEAL_TIME:
2151
2152 if (unlikely(!sched_info_on()))
2153 return 1;
2154
2155 if (data & KVM_STEAL_RESERVED_MASK)
2156 return 1;
2157
2158 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2159 data & KVM_STEAL_VALID_BITS,
2160 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2161 return 1;
2162
2163 vcpu->arch.st.msr_val = data;
2164
2165 if (!(data & KVM_MSR_ENABLED))
2166 break;
2167
c9aaa895
GC		 2168 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2169
2170 break;
ae7a2a3f
MT		 2171 case MSR_KVM_PV_EOI_EN:
2172 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2173 return 1;
2174 break;
c9aaa895 2175
890ca9ae
HY		 2176 case MSR_IA32_MCG_CTL:
2177 case MSR_IA32_MCG_STATUS:
81760dcc 2178 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2179 return set_msr_mce(vcpu, msr, data);
71db6023 2180
6912ac32
WH		 2181 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2182 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2183 pr = true; /* fall through */
2184 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2185 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2186 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2187 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2188
2189 if (pr || data != 0)
a737f256
CD		 2190 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2191 "0x%x data 0x%llx\n", msr, data);
5753785f 2192 break;
84e0cefa
JS		 2193 case MSR_K7_CLK_CTL:
2194 /*
2195 * Ignore all writes to this no longer documented MSR.
2196 * Writes are only relevant for old K7 processors,
2197 * all pre-dating SVM, but a recommended workaround from
4a969980 2198 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2199 * affected processor models on the command line, hence
2200 * the need to ignore the workaround.
2201 */
2202 break;
55cd8e5a 2203 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2204 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2205 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2206 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2207 return kvm_hv_set_msr_common(vcpu, msr, data,
2208 msr_info->host_initiated);
91c9c3ed 2209 case MSR_IA32_BBL_CR_CTL3:
2210 /* Drop writes to this legacy MSR -- see rdmsr
2211 * counterpart for further detail.
2212 */
a737f256 2213 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2214 break;
2b036c6b
BO		 2215 case MSR_AMD64_OSVW_ID_LENGTH:
2216 if (!guest_cpuid_has_osvw(vcpu))
2217 return 1;
2218 vcpu->arch.osvw.length = data;
2219 break;
2220 case MSR_AMD64_OSVW_STATUS:
2221 if (!guest_cpuid_has_osvw(vcpu))
2222 return 1;
2223 vcpu->arch.osvw.status = data;
2224 break;
15c4a640 2225 default:
ffde22ac
ES		 2226 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2227 return xen_hvm_config(vcpu, data);
c6702c9d 2228 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2229 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2230 if (!ignore_msrs) {
a737f256
CD		 2231 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2232 msr, data);
ed85c068
AP		 2233 return 1;
2234 } else {
a737f256
CD		 2235 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2236 msr, data);
ed85c068
AP		 2237 break;
2238 }
15c4a640
CO		 2239 }
2240 return 0;
2241}
2242EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2243
2244
2245/*
2246 * Reads an msr value (of 'msr_index') into 'pdata'.
2247 * Returns 0 on success, non-0 otherwise.
2248 * Assumes vcpu_load() was already called.
2249 */
609e36d3 2250int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2251{
609e36d3 2252 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2253}
ff651cb6 2254EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2255
890ca9ae 2256static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2257{
2258 u64 data;
890ca9ae
HY		 2259 u64 mcg_cap = vcpu->arch.mcg_cap;
2260 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2261
2262 switch (msr) {
15c4a640
CO		 2263 case MSR_IA32_P5_MC_ADDR:
2264 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2265 data = 0;
2266 break;
15c4a640 2267 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2268 data = vcpu->arch.mcg_cap;
2269 break;
c7ac679c 2270 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2271 if (!(mcg_cap & MCG_CTL_P))
2272 return 1;
2273 data = vcpu->arch.mcg_ctl;
2274 break;
2275 case MSR_IA32_MCG_STATUS:
2276 data = vcpu->arch.mcg_status;
2277 break;
2278 default:
2279 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2280 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2281 u32 offset = msr - MSR_IA32_MC0_CTL;
2282 data = vcpu->arch.mce_banks[offset];
2283 break;
2284 }
2285 return 1;
2286 }
2287 *pdata = data;
2288 return 0;
2289}
2290
609e36d3 2291int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2292{
609e36d3 2293 switch (msr_info->index) {
890ca9ae 2294 case MSR_IA32_PLATFORM_ID:
15c4a640 2295 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2296 case MSR_IA32_DEBUGCTLMSR:
2297 case MSR_IA32_LASTBRANCHFROMIP:
2298 case MSR_IA32_LASTBRANCHTOIP:
2299 case MSR_IA32_LASTINTFROMIP:
2300 case MSR_IA32_LASTINTTOIP:
60af2ecd 2301 case MSR_K8_SYSCFG:
3afb1121
PB		 2302 case MSR_K8_TSEG_ADDR:
2303 case MSR_K8_TSEG_MASK:
60af2ecd 2304 case MSR_K7_HWCR:
61a6bd67 2305 case MSR_VM_HSAVE_PA:
1fdbd48c 2306 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2307 case MSR_AMD64_NB_CFG:
f7c6d140 2308 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2309 case MSR_AMD64_BU_CFG2:
609e36d3 2310 msr_info->data = 0;
15c4a640 2311 break;
6912ac32
WH		 2312 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2313 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2314 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2315 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2316 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2317 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2318 msr_info->data = 0;
5753785f 2319 break;
742bc670 2320 case MSR_IA32_UCODE_REV:
609e36d3 2321 msr_info->data = 0x100000000ULL;
742bc670 2322 break;
9ba075a6 2323 case MSR_MTRRcap:
9ba075a6 2324 case 0x200 ... 0x2ff:
ff53604b 2325 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2326 case 0xcd: /* fsb frequency */
609e36d3 2327 msr_info->data = 3;
15c4a640 2328 break;
7b914098
JS		 2329 /*
2330 * MSR_EBC_FREQUENCY_ID
2331 * Conservative value valid for even the basic CPU models.
2332 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2333 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2334 * and 266MHz for model 3, or 4. Set Core Clock
2335 * Frequency to System Bus Frequency Ratio to 1 (bits
2336 * 31:24) even though these are only valid for CPU
2337 * models > 2, however guests may end up dividing or
2338 * multiplying by zero otherwise.
2339 */
2340 case MSR_EBC_FREQUENCY_ID:
609e36d3 2341 msr_info->data = 1 << 24;
7b914098 2342 break;
15c4a640 2343 case MSR_IA32_APICBASE:
609e36d3 2344 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2345 break;
0105d1a5 2346 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2347 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2348 break;
a3e06bbe 2349 case MSR_IA32_TSCDEADLINE:
609e36d3 2350 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2351 break;
ba904635 2352 case MSR_IA32_TSC_ADJUST:
609e36d3 2353 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2354 break;
15c4a640 2355 case MSR_IA32_MISC_ENABLE:
609e36d3 2356 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2357 break;
64d60670
PB		 2358 case MSR_IA32_SMBASE:
2359 if (!msr_info->host_initiated)
2360 return 1;
2361 msr_info->data = vcpu->arch.smbase;
15c4a640 2362 break;
847f0ad8
AG		 2363 case MSR_IA32_PERF_STATUS:
2364 /* TSC increment by tick */
609e36d3 2365 msr_info->data = 1000ULL;
847f0ad8 2366 /* CPU multiplier */
b0996ae4 2367 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2368 break;
15c4a640 2369 case MSR_EFER:
609e36d3 2370 msr_info->data = vcpu->arch.efer;
15c4a640 2371 break;
18068523 2372 case MSR_KVM_WALL_CLOCK:
11c6bffa 2373 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2374 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2375 break;
2376 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2377 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2378 msr_info->data = vcpu->arch.time;
18068523 2379 break;
344d9588 2380 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2381 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2382 break;
c9aaa895 2383 case MSR_KVM_STEAL_TIME:
609e36d3 2384 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2385 break;
1d92128f 2386 case MSR_KVM_PV_EOI_EN:
609e36d3 2387 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2388 break;
890ca9ae
HY		 2389 case MSR_IA32_P5_MC_ADDR:
2390 case MSR_IA32_P5_MC_TYPE:
2391 case MSR_IA32_MCG_CAP:
2392 case MSR_IA32_MCG_CTL:
2393 case MSR_IA32_MCG_STATUS:
81760dcc 2394 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2395 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2396 case MSR_K7_CLK_CTL:
2397 /*
2398 * Provide expected ramp-up count for K7. All other
2399 * are set to zero, indicating minimum divisors for
2400 * every field.
2401 *
2402 * This prevents guest kernels on AMD host with CPU
2403 * type 6, model 8 and higher from exploding due to
2404 * the rdmsr failing.
2405 */
609e36d3 2406 msr_info->data = 0x20000000;
84e0cefa 2407 break;
55cd8e5a 2408 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2409 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2410 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2411 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2412 return kvm_hv_get_msr_common(vcpu,
2413 msr_info->index, &msr_info->data);
55cd8e5a 2414 break;
91c9c3ed 2415 case MSR_IA32_BBL_CR_CTL3:
2416 /* This legacy MSR exists but isn't fully documented in current
2417 * silicon. It is however accessed by winxp in very narrow
2418 * scenarios where it sets bit #19, itself documented as
2419 * a "reserved" bit. Best effort attempt to source coherent
2420 * read data here should the balance of the register be
2421 * interpreted by the guest:
2422 *
2423 * L2 cache control register 3: 64GB range, 256KB size,
2424 * enabled, latency 0x1, configured
2425 */
609e36d3 2426 msr_info->data = 0xbe702111;
91c9c3ed 2427 break;
2b036c6b
BO		 2428 case MSR_AMD64_OSVW_ID_LENGTH:
2429 if (!guest_cpuid_has_osvw(vcpu))
2430 return 1;
609e36d3 2431 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2432 break;
2433 case MSR_AMD64_OSVW_STATUS:
2434 if (!guest_cpuid_has_osvw(vcpu))
2435 return 1;
609e36d3 2436 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2437 break;
15c4a640 2438 default:
c6702c9d 2439 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2440 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2441 if (!ignore_msrs) {
609e36d3 2442 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2443 return 1;
2444 } else {
609e36d3
PB		 2445 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2446 msr_info->data = 0;
ed85c068
AP		 2447 }
2448 break;
15c4a640 2449 }
15c4a640
CO		 2450 return 0;
2451}
2452EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2453
313a3dc7
CO		 2454/*
2455 * Read or write a bunch of msrs. All parameters are kernel addresses.
2456 *
2457 * @return number of msrs set successfully.
2458 */
2459static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2460 struct kvm_msr_entry *entries,
2461 int (*do_msr)(struct kvm_vcpu *vcpu,
2462 unsigned index, u64 *data))
2463{
f656ce01 2464 int i, idx;
313a3dc7 2465
f656ce01 2466 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2467 for (i = 0; i < msrs->nmsrs; ++i)
2468 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2469 break;
f656ce01 2470 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2471
313a3dc7
CO		 2472 return i;
2473}
2474
2475/*
2476 * Read or write a bunch of msrs. Parameters are user addresses.
2477 *
2478 * @return number of msrs set successfully.
2479 */
2480static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2481 int (*do_msr)(struct kvm_vcpu *vcpu,
2482 unsigned index, u64 *data),
2483 int writeback)
2484{
2485 struct kvm_msrs msrs;
2486 struct kvm_msr_entry *entries;
2487 int r, n;
2488 unsigned size;
2489
2490 r = -EFAULT;
2491 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2492 goto out;
2493
2494 r = -E2BIG;
2495 if (msrs.nmsrs >= MAX_IO_MSRS)
2496 goto out;
2497
313a3dc7 2498 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2499 entries = memdup_user(user_msrs->entries, size);
2500 if (IS_ERR(entries)) {
2501 r = PTR_ERR(entries);
313a3dc7 2502 goto out;
ff5c2c03 2503 }
313a3dc7
CO		 2504
2505 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2506 if (r < 0)
2507 goto out_free;
2508
2509 r = -EFAULT;
2510 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2511 goto out_free;
2512
2513 r = n;
2514
2515out_free:
7a73c028 2516 kfree(entries);
313a3dc7
CO		 2517out:
2518 return r;
2519}
2520
784aa3d7 2521int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2522{
2523 int r;
2524
2525 switch (ext) {
2526 case KVM_CAP_IRQCHIP:
2527 case KVM_CAP_HLT:
2528 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2529 case KVM_CAP_SET_TSS_ADDR:
07716717 2530 case KVM_CAP_EXT_CPUID:
9c15bb1d 2531 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2532 case KVM_CAP_CLOCKSOURCE:
7837699f 2533 case KVM_CAP_PIT:
a28e4f5a 2534 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2535 case KVM_CAP_MP_STATE:
ed848624 2536 case KVM_CAP_SYNC_MMU:
a355c85c 2537 case KVM_CAP_USER_NMI:
52d939a0 2538 case KVM_CAP_REINJECT_CONTROL:
4925663a 2539 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2540 case KVM_CAP_IOEVENTFD:
f848a5a8 2541 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2542 case KVM_CAP_PIT2:
e9f42757 2543 case KVM_CAP_PIT_STATE2:
b927a3ce 2544 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2545 case KVM_CAP_XEN_HVM:
afbcf7ab 2546 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2547 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2548 case KVM_CAP_HYPERV:
10388a07 2549 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2550 case KVM_CAP_HYPERV_SPIN:
5c919412 2551 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2552 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2553 case KVM_CAP_DEBUGREGS:
d2be1651 2554 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2555 case KVM_CAP_XSAVE:
344d9588 2556 case KVM_CAP_ASYNC_PF:
92a1f12d 2557 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2558 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2559 case KVM_CAP_READONLY_MEM:
5f66b620 2560 case KVM_CAP_HYPERV_TIME:
100943c5 2561 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2562 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2563 case KVM_CAP_ENABLE_CAP_VM:
2564 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2565 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2566 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2567#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2568 case KVM_CAP_ASSIGN_DEV_IRQ:
2569 case KVM_CAP_PCI_2_3:
2570#endif
018d00d2
ZX		 2571 r = 1;
2572 break;
6d396b55
PB		 2573 case KVM_CAP_X86_SMM:
2574 /* SMBASE is usually relocated above 1M on modern chipsets,
2575 * and SMM handlers might indeed rely on 4G segment limits,
2576 * so do not report SMM to be available if real mode is
2577 * emulated via vm86 mode. Still, do not go to great lengths
2578 * to avoid userspace's usage of the feature, because it is a
2579 * fringe case that is not enabled except via specific settings
2580 * of the module parameters.
2581 */
2582 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2583 break;
542472b5
LV		 2584 case KVM_CAP_COALESCED_MMIO:
2585 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2586 break;
774ead3a
AK		 2587 case KVM_CAP_VAPIC:
2588 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2589 break;
f725230a 2590 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2591 r = KVM_SOFT_MAX_VCPUS;
2592 break;
2593 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2594 r = KVM_MAX_VCPUS;
2595 break;
a988b910 2596 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2597 r = KVM_USER_MEM_SLOTS;
a988b910 2598 break;
a68a6a72
MT		 2599 case KVM_CAP_PV_MMU: /* obsolete */
2600 r = 0;
2f333bcb 2601 break;
4cee4b72 2602#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2603 case KVM_CAP_IOMMU:
a1b60c1c 2604 r = iommu_present(&pci_bus_type);
62c476c7 2605 break;
4cee4b72 2606#endif
890ca9ae
HY		 2607 case KVM_CAP_MCE:
2608 r = KVM_MAX_MCE_BANKS;
2609 break;
2d5b5a66
SY		 2610 case KVM_CAP_XCRS:
2611 r = cpu_has_xsave;
2612 break;
92a1f12d
JR		 2613 case KVM_CAP_TSC_CONTROL:
2614 r = kvm_has_tsc_control;
2615 break;
018d00d2
ZX		 2616 default:
2617 r = 0;
2618 break;
2619 }
2620 return r;
2621
2622}
2623
043405e1
CO		 2624long kvm_arch_dev_ioctl(struct file *filp,
2625 unsigned int ioctl, unsigned long arg)
2626{
2627 void __user *argp = (void __user *)arg;
2628 long r;
2629
2630 switch (ioctl) {
2631 case KVM_GET_MSR_INDEX_LIST: {
2632 struct kvm_msr_list __user *user_msr_list = argp;
2633 struct kvm_msr_list msr_list;
2634 unsigned n;
2635
2636 r = -EFAULT;
2637 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2638 goto out;
2639 n = msr_list.nmsrs;
62ef68bb 2640 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2641 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2642 goto out;
2643 r = -E2BIG;
e125e7b6 2644 if (n < msr_list.nmsrs)
043405e1
CO		 2645 goto out;
2646 r = -EFAULT;
2647 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2648 num_msrs_to_save * sizeof(u32)))
2649 goto out;
e125e7b6 2650 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2651 &emulated_msrs,
62ef68bb 2652 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2653 goto out;
2654 r = 0;
2655 break;
2656 }
9c15bb1d
BP		 2657 case KVM_GET_SUPPORTED_CPUID:
2658 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2659 struct kvm_cpuid2 __user *cpuid_arg = argp;
2660 struct kvm_cpuid2 cpuid;
2661
2662 r = -EFAULT;
2663 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2664 goto out;
9c15bb1d
BP		 2665
2666 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2667 ioctl);
674eea0f
AK		 2668 if (r)
2669 goto out;
2670
2671 r = -EFAULT;
2672 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2673 goto out;
2674 r = 0;
2675 break;
2676 }
890ca9ae
HY		 2677 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2678 u64 mce_cap;
2679
2680 mce_cap = KVM_MCE_CAP_SUPPORTED;
2681 r = -EFAULT;
2682 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2683 goto out;
2684 r = 0;
2685 break;
2686 }
043405e1
CO		 2687 default:
2688 r = -EINVAL;
2689 }
2690out:
2691 return r;
2692}
2693
f5f48ee1
SY		 2694static void wbinvd_ipi(void *garbage)
2695{
2696 wbinvd();
2697}
2698
2699static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2700{
e0f0bbc5 2701 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2702}
2703
2860c4b1
PB		 2704static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2705{
2706 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2707}
2708
313a3dc7
CO		 2709void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2710{
f5f48ee1
SY		 2711 /* Address WBINVD may be executed by guest */
2712 if (need_emulate_wbinvd(vcpu)) {
2713 if (kvm_x86_ops->has_wbinvd_exit())
2714 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2715 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2716 smp_call_function_single(vcpu->cpu,
2717 wbinvd_ipi, NULL, 1);
2718 }
2719
313a3dc7 2720 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2721
0dd6a6ed
ZA		 2722 /* Apply any externally detected TSC adjustments (due to suspend) */
2723 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2724 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2725 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2726 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2727 }
8f6055cb 2728
48434c20 2729 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2730 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2731 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2732 if (tsc_delta < 0)
2733 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2734 if (check_tsc_unstable()) {
07c1419a 2735 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2736 vcpu->arch.last_guest_tsc);
2737 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2738 vcpu->arch.tsc_catchup = 1;
c285545f 2739 }
d98d07ca
MT		 2740 /*
2741 * On a host with synchronized TSC, there is no need to update
2742 * kvmclock on vcpu->cpu migration
2743 */
2744 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2745 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2746 if (vcpu->cpu != cpu)
2747 kvm_migrate_timers(vcpu);
e48672fa 2748 vcpu->cpu = cpu;
6b7d7e76 2749 }
c9aaa895 2750
c9aaa895 2751 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2752}
2753
2754void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2755{
02daab21 2756 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2757 kvm_put_guest_fpu(vcpu);
4ea1636b 2758 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2759}
2760
313a3dc7
CO		 2761static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2762 struct kvm_lapic_state *s)
2763{
d62caabb
AS		 2764 if (vcpu->arch.apicv_active)
2765 kvm_x86_ops->sync_pir_to_irr(vcpu);
2766
ad312c7c 2767 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2768
2769 return 0;
2770}
2771
2772static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2773 struct kvm_lapic_state *s)
2774{
64eb0620 2775 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2776 update_cr8_intercept(vcpu);
313a3dc7
CO		 2777
2778 return 0;
2779}
2780
127a457a
MG		 2781static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2782{
2783 return (!lapic_in_kernel(vcpu) ||
2784 kvm_apic_accept_pic_intr(vcpu));
2785}
2786
782d422b
MG		 2787/*
2788 * if userspace requested an interrupt window, check that the
2789 * interrupt window is open.
2790 *
2791 * No need to exit to userspace if we already have an interrupt queued.
2792 */
2793static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2794{
2795 return kvm_arch_interrupt_allowed(vcpu) &&
2796 !kvm_cpu_has_interrupt(vcpu) &&
2797 !kvm_event_needs_reinjection(vcpu) &&
2798 kvm_cpu_accept_dm_intr(vcpu);
2799}
2800
f77bc6a4
ZX		 2801static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2802 struct kvm_interrupt *irq)
2803{
02cdb50f 2804 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2805 return -EINVAL;
1c1a9ce9
SR		 2806
2807 if (!irqchip_in_kernel(vcpu->kvm)) {
2808 kvm_queue_interrupt(vcpu, irq->irq, false);
2809 kvm_make_request(KVM_REQ_EVENT, vcpu);
2810 return 0;
2811 }
2812
2813 /*
2814 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2815 * fail for in-kernel 8259.
2816 */
2817 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2818 return -ENXIO;
f77bc6a4 2819
1c1a9ce9
SR		 2820 if (vcpu->arch.pending_external_vector != -1)
2821 return -EEXIST;
f77bc6a4 2822
1c1a9ce9 2823 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2824 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2825 return 0;
2826}
2827
c4abb7c9
JK		 2828static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2829{
c4abb7c9 2830 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2831
2832 return 0;
2833}
2834
f077825a
PB		 2835static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2836{
64d60670
PB		 2837 kvm_make_request(KVM_REQ_SMI, vcpu);
2838
f077825a
PB		 2839 return 0;
2840}
2841
b209749f
AK		 2842static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2843 struct kvm_tpr_access_ctl *tac)
2844{
2845 if (tac->flags)
2846 return -EINVAL;
2847 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2848 return 0;
2849}
2850
890ca9ae
HY		 2851static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2852 u64 mcg_cap)
2853{
2854 int r;
2855 unsigned bank_num = mcg_cap & 0xff, bank;
2856
2857 r = -EINVAL;
a9e38c3e 2858 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2859 goto out;
2860 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2861 goto out;
2862 r = 0;
2863 vcpu->arch.mcg_cap = mcg_cap;
2864 /* Init IA32_MCG_CTL to all 1s */
2865 if (mcg_cap & MCG_CTL_P)
2866 vcpu->arch.mcg_ctl = ~(u64)0;
2867 /* Init IA32_MCi_CTL to all 1s */
2868 for (bank = 0; bank < bank_num; bank++)
2869 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2870out:
2871 return r;
2872}
2873
2874static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2875 struct kvm_x86_mce *mce)
2876{
2877 u64 mcg_cap = vcpu->arch.mcg_cap;
2878 unsigned bank_num = mcg_cap & 0xff;
2879 u64 *banks = vcpu->arch.mce_banks;
2880
2881 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2882 return -EINVAL;
2883 /*
2884 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2885 * reporting is disabled
2886 */
2887 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2888 vcpu->arch.mcg_ctl != ~(u64)0)
2889 return 0;
2890 banks += 4 * mce->bank;
2891 /*
2892 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2893 * reporting is disabled for the bank
2894 */
2895 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2896 return 0;
2897 if (mce->status & MCI_STATUS_UC) {
2898 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2899 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2900 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2901 return 0;
2902 }
2903 if (banks[1] & MCI_STATUS_VAL)
2904 mce->status |= MCI_STATUS_OVER;
2905 banks[2] = mce->addr;
2906 banks[3] = mce->misc;
2907 vcpu->arch.mcg_status = mce->mcg_status;
2908 banks[1] = mce->status;
2909 kvm_queue_exception(vcpu, MC_VECTOR);
2910 } else if (!(banks[1] & MCI_STATUS_VAL)
2911 || !(banks[1] & MCI_STATUS_UC)) {
2912 if (banks[1] & MCI_STATUS_VAL)
2913 mce->status |= MCI_STATUS_OVER;
2914 banks[2] = mce->addr;
2915 banks[3] = mce->misc;
2916 banks[1] = mce->status;
2917 } else
2918 banks[1] |= MCI_STATUS_OVER;
2919 return 0;
2920}
2921
3cfc3092
JK		 2922static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2923 struct kvm_vcpu_events *events)
2924{
7460fb4a 2925 process_nmi(vcpu);
03b82a30
JK		 2926 events->exception.injected =
2927 vcpu->arch.exception.pending &&
2928 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2929 events->exception.nr = vcpu->arch.exception.nr;
2930 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2931 events->exception.pad = 0;
3cfc3092
JK		 2932 events->exception.error_code = vcpu->arch.exception.error_code;
2933
03b82a30
JK		 2934 events->interrupt.injected =
2935 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2936 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2937 events->interrupt.soft = 0;
37ccdcbe 2938 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2939
2940 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2941 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2942 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2943 events->nmi.pad = 0;
3cfc3092 2944
66450a21 2945 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2946
f077825a
PB		 2947 events->smi.smm = is_smm(vcpu);
2948 events->smi.pending = vcpu->arch.smi_pending;
2949 events->smi.smm_inside_nmi =
2950 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2951 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2952
dab4b911 2953 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2954 | KVM_VCPUEVENT_VALID_SHADOW
2955 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2956 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2957}
2958
2959static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2960 struct kvm_vcpu_events *events)
2961{
dab4b911 2962 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2963 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2964 | KVM_VCPUEVENT_VALID_SHADOW
2965 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2966 return -EINVAL;
2967
7460fb4a 2968 process_nmi(vcpu);
3cfc3092
JK		 2969 vcpu->arch.exception.pending = events->exception.injected;
2970 vcpu->arch.exception.nr = events->exception.nr;
2971 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2972 vcpu->arch.exception.error_code = events->exception.error_code;
2973
2974 vcpu->arch.interrupt.pending = events->interrupt.injected;
2975 vcpu->arch.interrupt.nr = events->interrupt.nr;
2976 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2977 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2978 kvm_x86_ops->set_interrupt_shadow(vcpu,
2979 events->interrupt.shadow);
3cfc3092
JK		 2980
2981 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2982 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2983 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2984 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2985
66450a21 2986 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2987 lapic_in_kernel(vcpu))
66450a21 2988 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2989
f077825a
PB		 2990 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2991 if (events->smi.smm)
2992 vcpu->arch.hflags |= HF_SMM_MASK;
2993 else
2994 vcpu->arch.hflags &= ~HF_SMM_MASK;
2995 vcpu->arch.smi_pending = events->smi.pending;
2996 if (events->smi.smm_inside_nmi)
2997 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2998 else
2999 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3000 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3001 if (events->smi.latched_init)
3002 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3003 else
3004 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3005 }
3006 }
3007
3842d135
AK		 3008 kvm_make_request(KVM_REQ_EVENT, vcpu);
3009
3cfc3092
JK		 3010 return 0;
3011}
3012
a1efbe77
JK		 3013static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3014 struct kvm_debugregs *dbgregs)
3015{
73aaf249
JK		 3016 unsigned long val;
3017
a1efbe77 3018 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3019 kvm_get_dr(vcpu, 6, &val);
73aaf249 3020 dbgregs->dr6 = val;
a1efbe77
JK		 3021 dbgregs->dr7 = vcpu->arch.dr7;
3022 dbgregs->flags = 0;
97e69aa6 3023 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3024}
3025
3026static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3027 struct kvm_debugregs *dbgregs)
3028{
3029 if (dbgregs->flags)
3030 return -EINVAL;
3031
a1efbe77 3032 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3033 kvm_update_dr0123(vcpu);
a1efbe77 3034 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3035 kvm_update_dr6(vcpu);
a1efbe77 3036 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3037 kvm_update_dr7(vcpu);
a1efbe77 3038
a1efbe77
JK		 3039 return 0;
3040}
3041
df1daba7
PB		 3042#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3043
3044static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3045{
c47ada30 3046 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3047 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3048 u64 valid;
3049
3050 /*
3051 * Copy legacy XSAVE area, to avoid complications with CPUID
3052 * leaves 0 and 1 in the loop below.
3053 */
3054 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3055
3056 /* Set XSTATE_BV */
3057 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3058
3059 /*
3060 * Copy each region from the possibly compacted offset to the
3061 * non-compacted offset.
3062 */
d91cab78 3063 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3064 while (valid) {
3065 u64 feature = valid & -valid;
3066 int index = fls64(feature) - 1;
3067 void *src = get_xsave_addr(xsave, feature);
3068
3069 if (src) {
3070 u32 size, offset, ecx, edx;
3071 cpuid_count(XSTATE_CPUID, index,
3072 &size, &offset, &ecx, &edx);
3073 memcpy(dest + offset, src, size);
3074 }
3075
3076 valid -= feature;
3077 }
3078}
3079
3080static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3081{
c47ada30 3082 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3083 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3084 u64 valid;
3085
3086 /*
3087 * Copy legacy XSAVE area, to avoid complications with CPUID
3088 * leaves 0 and 1 in the loop below.
3089 */
3090 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3091
3092 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3093 xsave->header.xfeatures = xstate_bv;
df1daba7 3094 if (cpu_has_xsaves)
3a54450b 3095 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3096
3097 /*
3098 * Copy each region from the non-compacted offset to the
3099 * possibly compacted offset.
3100 */
d91cab78 3101 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3102 while (valid) {
3103 u64 feature = valid & -valid;
3104 int index = fls64(feature) - 1;
3105 void *dest = get_xsave_addr(xsave, feature);
3106
3107 if (dest) {
3108 u32 size, offset, ecx, edx;
3109 cpuid_count(XSTATE_CPUID, index,
3110 &size, &offset, &ecx, &edx);
3111 memcpy(dest, src + offset, size);
ee4100da 3112 }
df1daba7
PB		 3113
3114 valid -= feature;
3115 }
3116}
3117
2d5b5a66
SY		 3118static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3119 struct kvm_xsave *guest_xsave)
3120{
4344ee98 3121 if (cpu_has_xsave) {
df1daba7
PB		 3122 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3123 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3124 } else {
2d5b5a66 3125 memcpy(guest_xsave->region,
7366ed77 3126 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3127 sizeof(struct fxregs_state));
2d5b5a66 3128 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3129 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3130 }
3131}
3132
3133static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3134 struct kvm_xsave *guest_xsave)
3135{
3136 u64 xstate_bv =
3137 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3138
d7876f1b
PB		 3139 if (cpu_has_xsave) {
3140 /*
3141 * Here we allow setting states that are not present in
3142 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3143 * with old userspace.
3144 */
4ff41732 3145 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3146 return -EINVAL;
df1daba7 3147 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3148 } else {
d91cab78 3149 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3150 return -EINVAL;
7366ed77 3151 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3152 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3153 }
3154 return 0;
3155}
3156
3157static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3158 struct kvm_xcrs *guest_xcrs)
3159{
3160 if (!cpu_has_xsave) {
3161 guest_xcrs->nr_xcrs = 0;
3162 return;
3163 }
3164
3165 guest_xcrs->nr_xcrs = 1;
3166 guest_xcrs->flags = 0;
3167 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3168 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3169}
3170
3171static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3172 struct kvm_xcrs *guest_xcrs)
3173{
3174 int i, r = 0;
3175
3176 if (!cpu_has_xsave)
3177 return -EINVAL;
3178
3179 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3180 return -EINVAL;
3181
3182 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3183 /* Only support XCR0 currently */
c67a04cb 3184 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3185 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3186 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3187 break;
3188 }
3189 if (r)
3190 r = -EINVAL;
3191 return r;
3192}
3193
1c0b28c2
EM		 3194/*
3195 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3196 * stopped by the hypervisor. This function will be called from the host only.
3197 * EINVAL is returned when the host attempts to set the flag for a guest that
3198 * does not support pv clocks.
3199 */
3200static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3201{
0b79459b 3202 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3203 return -EINVAL;
51d59c6b 3204 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3205 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3206 return 0;
3207}
3208
5c919412
AS		 3209static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3210 struct kvm_enable_cap *cap)
3211{
3212 if (cap->flags)
3213 return -EINVAL;
3214
3215 switch (cap->cap) {
3216 case KVM_CAP_HYPERV_SYNIC:
3217 return kvm_hv_activate_synic(vcpu);
3218 default:
3219 return -EINVAL;
3220 }
3221}
3222
313a3dc7
CO		 3223long kvm_arch_vcpu_ioctl(struct file *filp,
3224 unsigned int ioctl, unsigned long arg)
3225{
3226 struct kvm_vcpu *vcpu = filp->private_data;
3227 void __user *argp = (void __user *)arg;
3228 int r;
d1ac91d8
AK		 3229 union {
3230 struct kvm_lapic_state *lapic;
3231 struct kvm_xsave *xsave;
3232 struct kvm_xcrs *xcrs;
3233 void *buffer;
3234 } u;
3235
3236 u.buffer = NULL;
313a3dc7
CO		 3237 switch (ioctl) {
3238 case KVM_GET_LAPIC: {
2204ae3c 3239 r = -EINVAL;
bce87cce 3240 if (!lapic_in_kernel(vcpu))
2204ae3c 3241 goto out;
d1ac91d8 3242 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3243
b772ff36 3244 r = -ENOMEM;
d1ac91d8 3245 if (!u.lapic)
b772ff36 3246 goto out;
d1ac91d8 3247 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3248 if (r)
3249 goto out;
3250 r = -EFAULT;
d1ac91d8 3251 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3252 goto out;
3253 r = 0;
3254 break;
3255 }
3256 case KVM_SET_LAPIC: {
2204ae3c 3257 r = -EINVAL;
bce87cce 3258 if (!lapic_in_kernel(vcpu))
2204ae3c 3259 goto out;
ff5c2c03 3260 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3261 if (IS_ERR(u.lapic))
3262 return PTR_ERR(u.lapic);
ff5c2c03 3263
d1ac91d8 3264 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3265 break;
3266 }
f77bc6a4
ZX		 3267 case KVM_INTERRUPT: {
3268 struct kvm_interrupt irq;
3269
3270 r = -EFAULT;
3271 if (copy_from_user(&irq, argp, sizeof irq))
3272 goto out;
3273 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3274 break;
3275 }
c4abb7c9
JK		 3276 case KVM_NMI: {
3277 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3278 break;
3279 }
f077825a
PB		 3280 case KVM_SMI: {
3281 r = kvm_vcpu_ioctl_smi(vcpu);
3282 break;
3283 }
313a3dc7
CO		 3284 case KVM_SET_CPUID: {
3285 struct kvm_cpuid __user *cpuid_arg = argp;
3286 struct kvm_cpuid cpuid;
3287
3288 r = -EFAULT;
3289 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3290 goto out;
3291 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3292 break;
3293 }
07716717
DK		 3294 case KVM_SET_CPUID2: {
3295 struct kvm_cpuid2 __user *cpuid_arg = argp;
3296 struct kvm_cpuid2 cpuid;
3297
3298 r = -EFAULT;
3299 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3300 goto out;
3301 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3302 cpuid_arg->entries);
07716717
DK		 3303 break;
3304 }
3305 case KVM_GET_CPUID2: {
3306 struct kvm_cpuid2 __user *cpuid_arg = argp;
3307 struct kvm_cpuid2 cpuid;
3308
3309 r = -EFAULT;
3310 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3311 goto out;
3312 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3313 cpuid_arg->entries);
07716717
DK		 3314 if (r)
3315 goto out;
3316 r = -EFAULT;
3317 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3318 goto out;
3319 r = 0;
3320 break;
3321 }
313a3dc7 3322 case KVM_GET_MSRS:
609e36d3 3323 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3324 break;
3325 case KVM_SET_MSRS:
3326 r = msr_io(vcpu, argp, do_set_msr, 0);
3327 break;
b209749f
AK		 3328 case KVM_TPR_ACCESS_REPORTING: {
3329 struct kvm_tpr_access_ctl tac;
3330
3331 r = -EFAULT;
3332 if (copy_from_user(&tac, argp, sizeof tac))
3333 goto out;
3334 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3335 if (r)
3336 goto out;
3337 r = -EFAULT;
3338 if (copy_to_user(argp, &tac, sizeof tac))
3339 goto out;
3340 r = 0;
3341 break;
3342 };
b93463aa
AK		 3343 case KVM_SET_VAPIC_ADDR: {
3344 struct kvm_vapic_addr va;
3345
3346 r = -EINVAL;
35754c98 3347 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3348 goto out;
3349 r = -EFAULT;
3350 if (copy_from_user(&va, argp, sizeof va))
3351 goto out;
fda4e2e8 3352 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3353 break;
3354 }
890ca9ae
HY		 3355 case KVM_X86_SETUP_MCE: {
3356 u64 mcg_cap;
3357
3358 r = -EFAULT;
3359 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3360 goto out;
3361 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3362 break;
3363 }
3364 case KVM_X86_SET_MCE: {
3365 struct kvm_x86_mce mce;
3366
3367 r = -EFAULT;
3368 if (copy_from_user(&mce, argp, sizeof mce))
3369 goto out;
3370 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3371 break;
3372 }
3cfc3092
JK		 3373 case KVM_GET_VCPU_EVENTS: {
3374 struct kvm_vcpu_events events;
3375
3376 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3377
3378 r = -EFAULT;
3379 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3380 break;
3381 r = 0;
3382 break;
3383 }
3384 case KVM_SET_VCPU_EVENTS: {
3385 struct kvm_vcpu_events events;
3386
3387 r = -EFAULT;
3388 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3389 break;
3390
3391 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3392 break;
3393 }
a1efbe77
JK		 3394 case KVM_GET_DEBUGREGS: {
3395 struct kvm_debugregs dbgregs;
3396
3397 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3398
3399 r = -EFAULT;
3400 if (copy_to_user(argp, &dbgregs,
3401 sizeof(struct kvm_debugregs)))
3402 break;
3403 r = 0;
3404 break;
3405 }
3406 case KVM_SET_DEBUGREGS: {
3407 struct kvm_debugregs dbgregs;
3408
3409 r = -EFAULT;
3410 if (copy_from_user(&dbgregs, argp,
3411 sizeof(struct kvm_debugregs)))
3412 break;
3413
3414 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3415 break;
3416 }
2d5b5a66 3417 case KVM_GET_XSAVE: {
d1ac91d8 3418 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3419 r = -ENOMEM;
d1ac91d8 3420 if (!u.xsave)
2d5b5a66
SY		 3421 break;
3422
d1ac91d8 3423 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3424
3425 r = -EFAULT;
d1ac91d8 3426 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3427 break;
3428 r = 0;
3429 break;
3430 }
3431 case KVM_SET_XSAVE: {
ff5c2c03 3432 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3433 if (IS_ERR(u.xsave))
3434 return PTR_ERR(u.xsave);
2d5b5a66 3435
d1ac91d8 3436 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3437 break;
3438 }
3439 case KVM_GET_XCRS: {
d1ac91d8 3440 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3441 r = -ENOMEM;
d1ac91d8 3442 if (!u.xcrs)
2d5b5a66
SY		 3443 break;
3444
d1ac91d8 3445 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3446
3447 r = -EFAULT;
d1ac91d8 3448 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3449 sizeof(struct kvm_xcrs)))
3450 break;
3451 r = 0;
3452 break;
3453 }
3454 case KVM_SET_XCRS: {
ff5c2c03 3455 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3456 if (IS_ERR(u.xcrs))
3457 return PTR_ERR(u.xcrs);
2d5b5a66 3458
d1ac91d8 3459 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3460 break;
3461 }
92a1f12d
JR		 3462 case KVM_SET_TSC_KHZ: {
3463 u32 user_tsc_khz;
3464
3465 r = -EINVAL;
92a1f12d
JR		 3466 user_tsc_khz = (u32)arg;
3467
3468 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3469 goto out;
3470
cc578287
ZA		 3471 if (user_tsc_khz == 0)
3472 user_tsc_khz = tsc_khz;
3473
381d585c
HZ		 3474 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3475 r = 0;
92a1f12d 3476
92a1f12d
JR		 3477 goto out;
3478 }
3479 case KVM_GET_TSC_KHZ: {
cc578287 3480 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3481 goto out;
3482 }
1c0b28c2
EM		 3483 case KVM_KVMCLOCK_CTRL: {
3484 r = kvm_set_guest_paused(vcpu);
3485 goto out;
3486 }
5c919412
AS		 3487 case KVM_ENABLE_CAP: {
3488 struct kvm_enable_cap cap;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&cap, argp, sizeof(cap)))
3492 goto out;
3493 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3494 break;
3495 }
313a3dc7
CO		 3496 default:
3497 r = -EINVAL;
3498 }
3499out:
d1ac91d8 3500 kfree(u.buffer);
313a3dc7
CO		 3501 return r;
3502}
3503
5b1c1493
CO		 3504int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3505{
3506 return VM_FAULT_SIGBUS;
3507}
3508
1fe779f8
CO		 3509static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3510{
3511 int ret;
3512
3513 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3514 return -EINVAL;
1fe779f8
CO		 3515 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3516 return ret;
3517}
3518
b927a3ce
SY		 3519static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3520 u64 ident_addr)
3521{
3522 kvm->arch.ept_identity_map_addr = ident_addr;
3523 return 0;
3524}
3525
1fe779f8
CO		 3526static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3527 u32 kvm_nr_mmu_pages)
3528{
3529 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3530 return -EINVAL;
3531
79fac95e 3532 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3533
3534 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3535 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3536
79fac95e 3537 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3538 return 0;
3539}
3540
3541static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3542{
39de71ec 3543 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3544}
3545
1fe779f8
CO		 3546static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3547{
3548 int r;
3549
3550 r = 0;
3551 switch (chip->chip_id) {
3552 case KVM_IRQCHIP_PIC_MASTER:
3553 memcpy(&chip->chip.pic,
3554 &pic_irqchip(kvm)->pics[0],
3555 sizeof(struct kvm_pic_state));
3556 break;
3557 case KVM_IRQCHIP_PIC_SLAVE:
3558 memcpy(&chip->chip.pic,
3559 &pic_irqchip(kvm)->pics[1],
3560 sizeof(struct kvm_pic_state));
3561 break;
3562 case KVM_IRQCHIP_IOAPIC:
eba0226b 3563 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3564 break;
3565 default:
3566 r = -EINVAL;
3567 break;
3568 }
3569 return r;
3570}
3571
3572static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3573{
3574 int r;
3575
3576 r = 0;
3577 switch (chip->chip_id) {
3578 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3579 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3580 memcpy(&pic_irqchip(kvm)->pics[0],
3581 &chip->chip.pic,
3582 sizeof(struct kvm_pic_state));
f4f51050 3583 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3584 break;
3585 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3586 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3587 memcpy(&pic_irqchip(kvm)->pics[1],
3588 &chip->chip.pic,
3589 sizeof(struct kvm_pic_state));
f4f51050 3590 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3591 break;
3592 case KVM_IRQCHIP_IOAPIC:
eba0226b 3593 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3594 break;
3595 default:
3596 r = -EINVAL;
3597 break;
3598 }
3599 kvm_pic_update_irq(pic_irqchip(kvm));
3600 return r;
3601}
3602
e0f63cb9
SY		 3603static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3604{
894a9c55 3605 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3606 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3607 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3608 return 0;
e0f63cb9
SY		 3609}
3610
3611static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3612{
0185604c 3613 int i;
894a9c55 3614 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3615 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
0185604c
AH		 3616 for (i = 0; i < 3; i++)
3617 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
e9f42757 3618 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3619 return 0;
e9f42757
BK		 3620}
3621
3622static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3623{
e9f42757
BK		 3624 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3625 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3626 sizeof(ps->channels));
3627 ps->flags = kvm->arch.vpit->pit_state.flags;
3628 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3629 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3630 return 0;
e9f42757
BK		 3631}
3632
3633static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3634{
2da29bcc 3635 int start = 0;
0185604c 3636 int i;
e9f42757
BK		 3637 u32 prev_legacy, cur_legacy;
3638 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3639 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3640 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3641 if (!prev_legacy && cur_legacy)
3642 start = 1;
3643 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3644 sizeof(kvm->arch.vpit->pit_state.channels));
3645 kvm->arch.vpit->pit_state.flags = ps->flags;
0185604c 3646 for (i = 0; i < 3; i++)
e5e57e7a
PB		 3647 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3648 start && i == 0);
894a9c55 3649 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3650 return 0;
e0f63cb9
SY		 3651}
3652
52d939a0
MT		 3653static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3654 struct kvm_reinject_control *control)
3655{
3656 if (!kvm->arch.vpit)
3657 return -ENXIO;
894a9c55 3658 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3659 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3660 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3661 return 0;
3662}
3663
95d4c16c 3664/**
60c34612
TY		 3665 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3666 * @kvm: kvm instance
3667 * @log: slot id and address to which we copy the log
95d4c16c 3668 *
e108ff2f
PB		 3669 * Steps 1-4 below provide general overview of dirty page logging. See
3670 * kvm_get_dirty_log_protect() function description for additional details.
3671 *
3672 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3673 * always flush the TLB (step 4) even if previous step failed and the dirty
3674 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3675 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3676 * writes will be marked dirty for next log read.
95d4c16c 3677 *
60c34612
TY		 3678 * 1. Take a snapshot of the bit and clear it if needed.
3679 * 2. Write protect the corresponding page.
e108ff2f
PB		 3680 * 3. Copy the snapshot to the userspace.
3681 * 4. Flush TLB's if needed.
5bb064dc 3682 */
60c34612 3683int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3684{
60c34612 3685 bool is_dirty = false;
e108ff2f 3686 int r;
5bb064dc 3687
79fac95e 3688 mutex_lock(&kvm->slots_lock);
5bb064dc 3689
88178fd4
KH		 3690 /*
3691 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3692 */
3693 if (kvm_x86_ops->flush_log_dirty)
3694 kvm_x86_ops->flush_log_dirty(kvm);
3695
e108ff2f 3696 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3697
3698 /*
3699 * All the TLBs can be flushed out of mmu lock, see the comments in
3700 * kvm_mmu_slot_remove_write_access().
3701 */
e108ff2f 3702 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3703 if (is_dirty)
3704 kvm_flush_remote_tlbs(kvm);
3705
79fac95e 3706 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3707 return r;
3708}
3709
aa2fbe6d
YZ		 3710int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3711 bool line_status)
23d43cf9
CD		 3712{
3713 if (!irqchip_in_kernel(kvm))
3714 return -ENXIO;
3715
3716 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3717 irq_event->irq, irq_event->level,
3718 line_status);
23d43cf9
CD		 3719 return 0;
3720}
3721
90de4a18
NA		 3722static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3723 struct kvm_enable_cap *cap)
3724{
3725 int r;
3726
3727 if (cap->flags)
3728 return -EINVAL;
3729
3730 switch (cap->cap) {
3731 case KVM_CAP_DISABLE_QUIRKS:
3732 kvm->arch.disabled_quirks = cap->args[0];
3733 r = 0;
3734 break;
49df6397
SR		 3735 case KVM_CAP_SPLIT_IRQCHIP: {
3736 mutex_lock(&kvm->lock);
b053b2ae
SR		 3737 r = -EINVAL;
3738 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3739 goto split_irqchip_unlock;
49df6397
SR		 3740 r = -EEXIST;
3741 if (irqchip_in_kernel(kvm))
3742 goto split_irqchip_unlock;
3743 if (atomic_read(&kvm->online_vcpus))
3744 goto split_irqchip_unlock;
3745 r = kvm_setup_empty_irq_routing(kvm);
3746 if (r)
3747 goto split_irqchip_unlock;
3748 /* Pairs with irqchip_in_kernel. */
3749 smp_wmb();
3750 kvm->arch.irqchip_split = true;
b053b2ae 3751 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3752 r = 0;
3753split_irqchip_unlock:
3754 mutex_unlock(&kvm->lock);
3755 break;
3756 }
90de4a18
NA		 3757 default:
3758 r = -EINVAL;
3759 break;
3760 }
3761 return r;
3762}
3763
1fe779f8
CO		 3764long kvm_arch_vm_ioctl(struct file *filp,
3765 unsigned int ioctl, unsigned long arg)
3766{
3767 struct kvm *kvm = filp->private_data;
3768 void __user *argp = (void __user *)arg;
367e1319 3769 int r = -ENOTTY;
f0d66275
DH		 3770 /*
3771 * This union makes it completely explicit to gcc-3.x
3772 * that these two variables' stack usage should be
3773 * combined, not added together.
3774 */
3775 union {
3776 struct kvm_pit_state ps;
e9f42757 3777 struct kvm_pit_state2 ps2;
c5ff41ce 3778 struct kvm_pit_config pit_config;
f0d66275 3779 } u;
1fe779f8
CO		 3780
3781 switch (ioctl) {
3782 case KVM_SET_TSS_ADDR:
3783 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3784 break;
b927a3ce
SY		 3785 case KVM_SET_IDENTITY_MAP_ADDR: {
3786 u64 ident_addr;
3787
3788 r = -EFAULT;
3789 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3790 goto out;
3791 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3792 break;
3793 }
1fe779f8
CO		 3794 case KVM_SET_NR_MMU_PAGES:
3795 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3796 break;
3797 case KVM_GET_NR_MMU_PAGES:
3798 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3799 break;
3ddea128
MT		 3800 case KVM_CREATE_IRQCHIP: {
3801 struct kvm_pic *vpic;
3802
3803 mutex_lock(&kvm->lock);
3804 r = -EEXIST;
3805 if (kvm->arch.vpic)
3806 goto create_irqchip_unlock;
3e515705
AK		 3807 r = -EINVAL;
3808 if (atomic_read(&kvm->online_vcpus))
3809 goto create_irqchip_unlock;
1fe779f8 3810 r = -ENOMEM;
3ddea128
MT		 3811 vpic = kvm_create_pic(kvm);
3812 if (vpic) {
1fe779f8
CO		 3813 r = kvm_ioapic_init(kvm);
3814 if (r) {
175504cd 3815 mutex_lock(&kvm->slots_lock);
71ba994c 3816 kvm_destroy_pic(vpic);
175504cd 3817 mutex_unlock(&kvm->slots_lock);
3ddea128 3818 goto create_irqchip_unlock;
1fe779f8
CO		 3819 }
3820 } else
3ddea128 3821 goto create_irqchip_unlock;
399ec807
AK		 3822 r = kvm_setup_default_irq_routing(kvm);
3823 if (r) {
175504cd 3824 mutex_lock(&kvm->slots_lock);
3ddea128 3825 mutex_lock(&kvm->irq_lock);
72bb2fcd 3826 kvm_ioapic_destroy(kvm);
71ba994c 3827 kvm_destroy_pic(vpic);
3ddea128 3828 mutex_unlock(&kvm->irq_lock);
175504cd 3829 mutex_unlock(&kvm->slots_lock);
71ba994c 3830 goto create_irqchip_unlock;
399ec807 3831 }
71ba994c
PB		 3832 /* Write kvm->irq_routing before kvm->arch.vpic. */
3833 smp_wmb();
3834 kvm->arch.vpic = vpic;
3ddea128
MT		 3835 create_irqchip_unlock:
3836 mutex_unlock(&kvm->lock);
1fe779f8 3837 break;
3ddea128 3838 }
7837699f 3839 case KVM_CREATE_PIT:
c5ff41ce
JK		 3840 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3841 goto create_pit;
3842 case KVM_CREATE_PIT2:
3843 r = -EFAULT;
3844 if (copy_from_user(&u.pit_config, argp,
3845 sizeof(struct kvm_pit_config)))
3846 goto out;
3847 create_pit:
79fac95e 3848 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3849 r = -EEXIST;
3850 if (kvm->arch.vpit)
3851 goto create_pit_unlock;
7837699f 3852 r = -ENOMEM;
c5ff41ce 3853 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3854 if (kvm->arch.vpit)
3855 r = 0;
269e05e4 3856 create_pit_unlock:
79fac95e 3857 mutex_unlock(&kvm->slots_lock);
7837699f 3858 break;
1fe779f8
CO		 3859 case KVM_GET_IRQCHIP: {
3860 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3861 struct kvm_irqchip *chip;
1fe779f8 3862
ff5c2c03
SL		 3863 chip = memdup_user(argp, sizeof(*chip));
3864 if (IS_ERR(chip)) {
3865 r = PTR_ERR(chip);
1fe779f8 3866 goto out;
ff5c2c03
SL		 3867 }
3868
1fe779f8 3869 r = -ENXIO;
49df6397 3870 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3871 goto get_irqchip_out;
3872 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3873 if (r)
f0d66275 3874 goto get_irqchip_out;
1fe779f8 3875 r = -EFAULT;
f0d66275
DH		 3876 if (copy_to_user(argp, chip, sizeof *chip))
3877 goto get_irqchip_out;
1fe779f8 3878 r = 0;
f0d66275
DH		 3879 get_irqchip_out:
3880 kfree(chip);
1fe779f8
CO		 3881 break;
3882 }
3883 case KVM_SET_IRQCHIP: {
3884 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3885 struct kvm_irqchip *chip;
1fe779f8 3886
ff5c2c03
SL		 3887 chip = memdup_user(argp, sizeof(*chip));
3888 if (IS_ERR(chip)) {
3889 r = PTR_ERR(chip);
1fe779f8 3890 goto out;
ff5c2c03
SL		 3891 }
3892
1fe779f8 3893 r = -ENXIO;
49df6397 3894 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3895 goto set_irqchip_out;
3896 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3897 if (r)
f0d66275 3898 goto set_irqchip_out;
1fe779f8 3899 r = 0;
f0d66275
DH		 3900 set_irqchip_out:
3901 kfree(chip);
1fe779f8
CO		 3902 break;
3903 }
e0f63cb9 3904 case KVM_GET_PIT: {
e0f63cb9 3905 r = -EFAULT;
f0d66275 3906 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3907 goto out;
3908 r = -ENXIO;
3909 if (!kvm->arch.vpit)
3910 goto out;
f0d66275 3911 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3912 if (r)
3913 goto out;
3914 r = -EFAULT;
f0d66275 3915 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3916 goto out;
3917 r = 0;
3918 break;
3919 }
3920 case KVM_SET_PIT: {
e0f63cb9 3921 r = -EFAULT;
f0d66275 3922 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3923 goto out;
3924 r = -ENXIO;
3925 if (!kvm->arch.vpit)
3926 goto out;
f0d66275 3927 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3928 break;
3929 }
e9f42757
BK		 3930 case KVM_GET_PIT2: {
3931 r = -ENXIO;
3932 if (!kvm->arch.vpit)
3933 goto out;
3934 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3935 if (r)
3936 goto out;
3937 r = -EFAULT;
3938 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3939 goto out;
3940 r = 0;
3941 break;
3942 }
3943 case KVM_SET_PIT2: {
3944 r = -EFAULT;
3945 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3946 goto out;
3947 r = -ENXIO;
3948 if (!kvm->arch.vpit)
3949 goto out;
3950 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3951 break;
3952 }
52d939a0
MT		 3953 case KVM_REINJECT_CONTROL: {
3954 struct kvm_reinject_control control;
3955 r = -EFAULT;
3956 if (copy_from_user(&control, argp, sizeof(control)))
3957 goto out;
3958 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3959 break;
3960 }
d71ba788
PB		 3961 case KVM_SET_BOOT_CPU_ID:
3962 r = 0;
3963 mutex_lock(&kvm->lock);
3964 if (atomic_read(&kvm->online_vcpus) != 0)
3965 r = -EBUSY;
3966 else
3967 kvm->arch.bsp_vcpu_id = arg;
3968 mutex_unlock(&kvm->lock);
3969 break;
ffde22ac
ES		 3970 case KVM_XEN_HVM_CONFIG: {
3971 r = -EFAULT;
3972 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3973 sizeof(struct kvm_xen_hvm_config)))
3974 goto out;
3975 r = -EINVAL;
3976 if (kvm->arch.xen_hvm_config.flags)
3977 goto out;
3978 r = 0;
3979 break;
3980 }
afbcf7ab 3981 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3982 struct kvm_clock_data user_ns;
3983 u64 now_ns;
3984 s64 delta;
3985
3986 r = -EFAULT;
3987 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3988 goto out;
3989
3990 r = -EINVAL;
3991 if (user_ns.flags)
3992 goto out;
3993
3994 r = 0;
395c6b0a 3995 local_irq_disable();
759379dd 3996 now_ns = get_kernel_ns();
afbcf7ab 3997 delta = user_ns.clock - now_ns;
395c6b0a 3998 local_irq_enable();
afbcf7ab 3999 kvm->arch.kvmclock_offset = delta;
2e762ff7 4000 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4001 break;
4002 }
4003 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4004 struct kvm_clock_data user_ns;
4005 u64 now_ns;
4006
395c6b0a 4007 local_irq_disable();
759379dd 4008 now_ns = get_kernel_ns();
afbcf7ab 4009 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4010 local_irq_enable();
afbcf7ab 4011 user_ns.flags = 0;
97e69aa6 4012 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4013
4014 r = -EFAULT;
4015 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4016 goto out;
4017 r = 0;
4018 break;
4019 }
90de4a18
NA		 4020 case KVM_ENABLE_CAP: {
4021 struct kvm_enable_cap cap;
afbcf7ab 4022
90de4a18
NA		 4023 r = -EFAULT;
4024 if (copy_from_user(&cap, argp, sizeof(cap)))
4025 goto out;
4026 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4027 break;
4028 }
1fe779f8 4029 default:
c274e03a 4030 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4031 }
4032out:
4033 return r;
4034}
4035
a16b043c 4036static void kvm_init_msr_list(void)
043405e1
CO		 4037{
4038 u32 dummy[2];
4039 unsigned i, j;
4040
62ef68bb 4041 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4042 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4043 continue;
93c4adc7
PB		 4044
4045 /*
4046 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4047 * to the guests in some cases.
93c4adc7
PB		 4048 */
4049 switch (msrs_to_save[i]) {
4050 case MSR_IA32_BNDCFGS:
4051 if (!kvm_x86_ops->mpx_supported())
4052 continue;
4053 break;
9dbe6cf9
PB		 4054 case MSR_TSC_AUX:
4055 if (!kvm_x86_ops->rdtscp_supported())
4056 continue;
4057 break;
93c4adc7
PB		 4058 default:
4059 break;
4060 }
4061
043405e1
CO		 4062 if (j < i)
4063 msrs_to_save[j] = msrs_to_save[i];
4064 j++;
4065 }
4066 num_msrs_to_save = j;
62ef68bb
PB		 4067
4068 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4069 switch (emulated_msrs[i]) {
6d396b55
PB		 4070 case MSR_IA32_SMBASE:
4071 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4072 continue;
4073 break;
62ef68bb
PB		 4074 default:
4075 break;
4076 }
4077
4078 if (j < i)
4079 emulated_msrs[j] = emulated_msrs[i];
4080 j++;
4081 }
4082 num_emulated_msrs = j;
043405e1
CO		 4083}
4084
bda9020e
MT		 4085static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4086 const void *v)
bbd9b64e 4087{
70252a10
AK		 4088 int handled = 0;
4089 int n;
4090
4091 do {
4092 n = min(len, 8);
bce87cce 4093 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4094 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4095 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4096 break;
4097 handled += n;
4098 addr += n;
4099 len -= n;
4100 v += n;
4101 } while (len);
bbd9b64e 4102
70252a10 4103 return handled;
bbd9b64e
CO		 4104}
4105
bda9020e 4106static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4107{
70252a10
AK		 4108 int handled = 0;
4109 int n;
4110
4111 do {
4112 n = min(len, 8);
bce87cce 4113 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4114 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4115 addr, n, v))
4116 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4117 break;
4118 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4119 handled += n;
4120 addr += n;
4121 len -= n;
4122 v += n;
4123 } while (len);
bbd9b64e 4124
70252a10 4125 return handled;
bbd9b64e
CO		 4126}
4127
2dafc6c2
GN		 4128static void kvm_set_segment(struct kvm_vcpu *vcpu,
4129 struct kvm_segment *var, int seg)
4130{
4131 kvm_x86_ops->set_segment(vcpu, var, seg);
4132}
4133
4134void kvm_get_segment(struct kvm_vcpu *vcpu,
4135 struct kvm_segment *var, int seg)
4136{
4137 kvm_x86_ops->get_segment(vcpu, var, seg);
4138}
4139
54987b7a
PB		 4140gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4141 struct x86_exception *exception)
02f59dc9
JR		 4142{
4143 gpa_t t_gpa;
02f59dc9
JR		 4144
4145 BUG_ON(!mmu_is_nested(vcpu));
4146
4147 /* NPT walks are always user-walks */
4148 access |= PFERR_USER_MASK;
54987b7a 4149 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4150
4151 return t_gpa;
4152}
4153
ab9ae313
AK		 4154gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4155 struct x86_exception *exception)
1871c602
GN		 4156{
4157 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4158 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4159}
4160
ab9ae313
AK		 4161 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4162 struct x86_exception *exception)
1871c602
GN		 4163{
4164 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4165 access |= PFERR_FETCH_MASK;
ab9ae313 4166 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4167}
4168
ab9ae313
AK		 4169gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4170 struct x86_exception *exception)
1871c602
GN		 4171{
4172 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4173 access |= PFERR_WRITE_MASK;
ab9ae313 4174 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4175}
4176
4177/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4178gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4179 struct x86_exception *exception)
1871c602 4180{
ab9ae313 4181 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4182}
4183
4184static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4185 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4186 struct x86_exception *exception)
bbd9b64e
CO		 4187{
4188 void *data = val;
10589a46 4189 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4190
4191 while (bytes) {
14dfe855 4192 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4193 exception);
bbd9b64e 4194 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4195 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4196 int ret;
4197
bcc55cba 4198 if (gpa == UNMAPPED_GVA)
ab9ae313 4199 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4200 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4201 offset, toread);
10589a46 4202 if (ret < 0) {
c3cd7ffa 4203 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4204 goto out;
4205 }
bbd9b64e 4206
77c2002e
IE		 4207 bytes -= toread;
4208 data += toread;
4209 addr += toread;
bbd9b64e 4210 }
10589a46 4211out:
10589a46 4212 return r;
bbd9b64e 4213}
77c2002e 4214
1871c602 4215/* used for instruction fetching */
0f65dd70
AK		 4216static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4217 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4218 struct x86_exception *exception)
1871c602 4219{
0f65dd70 4220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4222 unsigned offset;
4223 int ret;
0f65dd70 4224
44583cba
PB		 4225 /* Inline kvm_read_guest_virt_helper for speed. */
4226 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4227 exception);
4228 if (unlikely(gpa == UNMAPPED_GVA))
4229 return X86EMUL_PROPAGATE_FAULT;
4230
4231 offset = addr & (PAGE_SIZE-1);
4232 if (WARN_ON(offset + bytes > PAGE_SIZE))
4233 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4234 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4235 offset, bytes);
44583cba
PB		 4236 if (unlikely(ret < 0))
4237 return X86EMUL_IO_NEEDED;
4238
4239 return X86EMUL_CONTINUE;
1871c602
GN		 4240}
4241
064aea77 4242int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4243 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4244 struct x86_exception *exception)
1871c602 4245{
0f65dd70 4246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4247 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4248
1871c602 4249 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4250 exception);
1871c602 4251}
064aea77 4252EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4253
0f65dd70
AK		 4254static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4255 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4256 struct x86_exception *exception)
1871c602 4257{
0f65dd70 4258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4259 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4260}
4261
7a036a6f
RK		 4262static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4263 unsigned long addr, void *val, unsigned int bytes)
4264{
4265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4266 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4267
4268 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4269}
4270
6a4d7550 4271int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4272 gva_t addr, void *val,
2dafc6c2 4273 unsigned int bytes,
bcc55cba 4274 struct x86_exception *exception)
77c2002e 4275{
0f65dd70 4276 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4277 void *data = val;
4278 int r = X86EMUL_CONTINUE;
4279
4280 while (bytes) {
14dfe855
JR		 4281 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4282 PFERR_WRITE_MASK,
ab9ae313 4283 exception);
77c2002e
IE		 4284 unsigned offset = addr & (PAGE_SIZE-1);
4285 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4286 int ret;
4287
bcc55cba 4288 if (gpa == UNMAPPED_GVA)
ab9ae313 4289 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4290 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4291 if (ret < 0) {
c3cd7ffa 4292 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4293 goto out;
4294 }
4295
4296 bytes -= towrite;
4297 data += towrite;
4298 addr += towrite;
4299 }
4300out:
4301 return r;
4302}
6a4d7550 4303EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4304
af7cc7d1
XG		 4305static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4306 gpa_t *gpa, struct x86_exception *exception,
4307 bool write)
4308{
97d64b78
AK		 4309 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4310 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4311
97d64b78 4312 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4313 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4314 vcpu->arch.access, access)) {
bebb106a
XG		 4315 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4316 (gva & (PAGE_SIZE - 1));
4f022648 4317 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4318 return 1;
4319 }
4320
af7cc7d1
XG		 4321 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4322
4323 if (*gpa == UNMAPPED_GVA)
4324 return -1;
4325
4326 /* For APIC access vmexit */
4327 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4328 return 1;
4329
4f022648
XG		 4330 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4331 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4332 return 1;
4f022648 4333 }
bebb106a 4334
af7cc7d1
XG		 4335 return 0;
4336}
4337
3200f405 4338int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4339 const void *val, int bytes)
bbd9b64e
CO		 4340{
4341 int ret;
4342
54bf36aa 4343 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4344 if (ret < 0)
bbd9b64e 4345 return 0;
f57f2ef5 4346 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4347 return 1;
4348}
4349
77d197b2
XG		 4350struct read_write_emulator_ops {
4351 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4352 int bytes);
4353 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4354 void *val, int bytes);
4355 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4356 int bytes, void *val);
4357 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4358 void *val, int bytes);
4359 bool write;
4360};
4361
4362static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4363{
4364 if (vcpu->mmio_read_completed) {
77d197b2 4365 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4366 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4367 vcpu->mmio_read_completed = 0;
4368 return 1;
4369 }
4370
4371 return 0;
4372}
4373
4374static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4375 void *val, int bytes)
4376{
54bf36aa 4377 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4378}
4379
4380static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 void *val, int bytes)
4382{
4383 return emulator_write_phys(vcpu, gpa, val, bytes);
4384}
4385
4386static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4387{
4388 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4389 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4390}
4391
4392static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4393 void *val, int bytes)
4394{
4395 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4396 return X86EMUL_IO_NEEDED;
4397}
4398
4399static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes)
4401{
f78146b0
AK		 4402 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4403
87da7e66 4404 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4405 return X86EMUL_CONTINUE;
4406}
4407
0fbe9b0b 4408static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4409 .read_write_prepare = read_prepare,
4410 .read_write_emulate = read_emulate,
4411 .read_write_mmio = vcpu_mmio_read,
4412 .read_write_exit_mmio = read_exit_mmio,
4413};
4414
0fbe9b0b 4415static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4416 .read_write_emulate = write_emulate,
4417 .read_write_mmio = write_mmio,
4418 .read_write_exit_mmio = write_exit_mmio,
4419 .write = true,
4420};
4421
22388a3c
XG		 4422static int emulator_read_write_onepage(unsigned long addr, void *val,
4423 unsigned int bytes,
4424 struct x86_exception *exception,
4425 struct kvm_vcpu *vcpu,
0fbe9b0b 4426 const struct read_write_emulator_ops *ops)
bbd9b64e 4427{
af7cc7d1
XG		 4428 gpa_t gpa;
4429 int handled, ret;
22388a3c 4430 bool write = ops->write;
f78146b0 4431 struct kvm_mmio_fragment *frag;
10589a46 4432
22388a3c 4433 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4434
af7cc7d1 4435 if (ret < 0)
bbd9b64e 4436 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4437
4438 /* For APIC access vmexit */
af7cc7d1 4439 if (ret)
bbd9b64e
CO		 4440 goto mmio;
4441
22388a3c 4442 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4443 return X86EMUL_CONTINUE;
4444
4445mmio:
4446 /*
4447 * Is this MMIO handled locally?
4448 */
22388a3c 4449 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4450 if (handled == bytes)
bbd9b64e 4451 return X86EMUL_CONTINUE;
bbd9b64e 4452
70252a10
AK		 4453 gpa += handled;
4454 bytes -= handled;
4455 val += handled;
4456
87da7e66
XG		 4457 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4458 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4459 frag->gpa = gpa;
4460 frag->data = val;
4461 frag->len = bytes;
f78146b0 4462 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4463}
4464
52eb5a6d
XL		 4465static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4466 unsigned long addr,
22388a3c
XG		 4467 void *val, unsigned int bytes,
4468 struct x86_exception *exception,
0fbe9b0b 4469 const struct read_write_emulator_ops *ops)
bbd9b64e 4470{
0f65dd70 4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4472 gpa_t gpa;
4473 int rc;
4474
4475 if (ops->read_write_prepare &&
4476 ops->read_write_prepare(vcpu, val, bytes))
4477 return X86EMUL_CONTINUE;
4478
4479 vcpu->mmio_nr_fragments = 0;
0f65dd70 4480
bbd9b64e
CO		 4481 /* Crossing a page boundary? */
4482 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4483 int now;
bbd9b64e
CO		 4484
4485 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4486 rc = emulator_read_write_onepage(addr, val, now, exception,
4487 vcpu, ops);
4488
bbd9b64e
CO		 4489 if (rc != X86EMUL_CONTINUE)
4490 return rc;
4491 addr += now;
bac15531
NA		 4492 if (ctxt->mode != X86EMUL_MODE_PROT64)
4493 addr = (u32)addr;
bbd9b64e
CO		 4494 val += now;
4495 bytes -= now;
4496 }
22388a3c 4497
f78146b0
AK		 4498 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4499 vcpu, ops);
4500 if (rc != X86EMUL_CONTINUE)
4501 return rc;
4502
4503 if (!vcpu->mmio_nr_fragments)
4504 return rc;
4505
4506 gpa = vcpu->mmio_fragments[0].gpa;
4507
4508 vcpu->mmio_needed = 1;
4509 vcpu->mmio_cur_fragment = 0;
4510
87da7e66 4511 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4512 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4513 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4514 vcpu->run->mmio.phys_addr = gpa;
4515
4516 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4517}
4518
4519static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4520 unsigned long addr,
4521 void *val,
4522 unsigned int bytes,
4523 struct x86_exception *exception)
4524{
4525 return emulator_read_write(ctxt, addr, val, bytes,
4526 exception, &read_emultor);
4527}
4528
52eb5a6d 4529static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4530 unsigned long addr,
4531 const void *val,
4532 unsigned int bytes,
4533 struct x86_exception *exception)
4534{
4535 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4536 exception, &write_emultor);
bbd9b64e 4537}
bbd9b64e 4538
daea3e73
AK		 4539#define CMPXCHG_TYPE(t, ptr, old, new) \
4540 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4541
4542#ifdef CONFIG_X86_64
4543# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4544#else
4545# define CMPXCHG64(ptr, old, new) \
9749a6c0 4546 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4547#endif
4548
0f65dd70
AK		 4549static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4550 unsigned long addr,
bbd9b64e
CO		 4551 const void *old,
4552 const void *new,
4553 unsigned int bytes,
0f65dd70 4554 struct x86_exception *exception)
bbd9b64e 4555{
0f65dd70 4556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4557 gpa_t gpa;
4558 struct page *page;
4559 char *kaddr;
4560 bool exchanged;
2bacc55c 4561
daea3e73
AK		 4562 /* guests cmpxchg8b have to be emulated atomically */
4563 if (bytes > 8 || (bytes & (bytes - 1)))
4564 goto emul_write;
10589a46 4565
daea3e73 4566 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4567
daea3e73
AK		 4568 if (gpa == UNMAPPED_GVA ||
4569 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4570 goto emul_write;
2bacc55c 4571
daea3e73
AK		 4572 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4573 goto emul_write;
72dc67a6 4574
54bf36aa 4575 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4576 if (is_error_page(page))
c19b8bd6 4577 goto emul_write;
72dc67a6 4578
8fd75e12 4579 kaddr = kmap_atomic(page);
daea3e73
AK		 4580 kaddr += offset_in_page(gpa);
4581 switch (bytes) {
4582 case 1:
4583 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4584 break;
4585 case 2:
4586 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4587 break;
4588 case 4:
4589 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4590 break;
4591 case 8:
4592 exchanged = CMPXCHG64(kaddr, old, new);
4593 break;
4594 default:
4595 BUG();
2bacc55c 4596 }
8fd75e12 4597 kunmap_atomic(kaddr);
daea3e73
AK		 4598 kvm_release_page_dirty(page);
4599
4600 if (!exchanged)
4601 return X86EMUL_CMPXCHG_FAILED;
4602
54bf36aa 4603 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4604 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4605
4606 return X86EMUL_CONTINUE;
4a5f48f6 4607
3200f405 4608emul_write:
daea3e73 4609 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4610
0f65dd70 4611 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4612}
4613
cf8f70bf
GN		 4614static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4615{
4616 /* TODO: String I/O for in kernel device */
4617 int r;
4618
4619 if (vcpu->arch.pio.in)
e32edf4f 4620 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4621 vcpu->arch.pio.size, pd);
4622 else
e32edf4f 4623 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4624 vcpu->arch.pio.port, vcpu->arch.pio.size,
4625 pd);
4626 return r;
4627}
4628
6f6fbe98
XG		 4629static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4630 unsigned short port, void *val,
4631 unsigned int count, bool in)
cf8f70bf 4632{
cf8f70bf 4633 vcpu->arch.pio.port = port;
6f6fbe98 4634 vcpu->arch.pio.in = in;
7972995b 4635 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4636 vcpu->arch.pio.size = size;
4637
4638 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4639 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4640 return 1;
4641 }
4642
4643 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4644 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4645 vcpu->run->io.size = size;
4646 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4647 vcpu->run->io.count = count;
4648 vcpu->run->io.port = port;
4649
4650 return 0;
4651}
4652
6f6fbe98
XG		 4653static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4654 int size, unsigned short port, void *val,
4655 unsigned int count)
cf8f70bf 4656{
ca1d4a9e 4657 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4658 int ret;
ca1d4a9e 4659
6f6fbe98
XG		 4660 if (vcpu->arch.pio.count)
4661 goto data_avail;
cf8f70bf 4662
6f6fbe98
XG		 4663 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4664 if (ret) {
4665data_avail:
4666 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4667 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4668 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4669 return 1;
4670 }
4671
cf8f70bf
GN		 4672 return 0;
4673}
4674
6f6fbe98
XG		 4675static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4676 int size, unsigned short port,
4677 const void *val, unsigned int count)
4678{
4679 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4680
4681 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4682 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4683 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4684}
4685
bbd9b64e
CO		 4686static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4687{
4688 return kvm_x86_ops->get_segment_base(vcpu, seg);
4689}
4690
3cb16fe7 4691static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4692{
3cb16fe7 4693 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4694}
4695
5cb56059 4696int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4697{
4698 if (!need_emulate_wbinvd(vcpu))
4699 return X86EMUL_CONTINUE;
4700
4701 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4702 int cpu = get_cpu();
4703
4704 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4705 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4706 wbinvd_ipi, NULL, 1);
2eec7343 4707 put_cpu();
f5f48ee1 4708 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4709 } else
4710 wbinvd();
f5f48ee1
SY		 4711 return X86EMUL_CONTINUE;
4712}
5cb56059
JS		 4713
4714int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4715{
4716 kvm_x86_ops->skip_emulated_instruction(vcpu);
4717 return kvm_emulate_wbinvd_noskip(vcpu);
4718}
f5f48ee1
SY		 4719EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4720
5cb56059
JS		 4721
4722
bcaf5cc5
AK		 4723static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4724{
5cb56059 4725 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4726}
4727
52eb5a6d
XL		 4728static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4729 unsigned long *dest)
bbd9b64e 4730{
16f8a6f9 4731 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4732}
4733
52eb5a6d
XL		 4734static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4735 unsigned long value)
bbd9b64e 4736{
338dbc97 4737
717746e3 4738 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4739}
4740
52a46617 4741static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4742{
52a46617 4743 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4744}
4745
717746e3 4746static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4747{
717746e3 4748 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4749 unsigned long value;
4750
4751 switch (cr) {
4752 case 0:
4753 value = kvm_read_cr0(vcpu);
4754 break;
4755 case 2:
4756 value = vcpu->arch.cr2;
4757 break;
4758 case 3:
9f8fe504 4759 value = kvm_read_cr3(vcpu);
52a46617
GN		 4760 break;
4761 case 4:
4762 value = kvm_read_cr4(vcpu);
4763 break;
4764 case 8:
4765 value = kvm_get_cr8(vcpu);
4766 break;
4767 default:
a737f256 4768 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4769 return 0;
4770 }
4771
4772 return value;
4773}
4774
717746e3 4775static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4776{
717746e3 4777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4778 int res = 0;
4779
52a46617
GN		 4780 switch (cr) {
4781 case 0:
49a9b07e 4782 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4783 break;
4784 case 2:
4785 vcpu->arch.cr2 = val;
4786 break;
4787 case 3:
2390218b 4788 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4789 break;
4790 case 4:
a83b29c6 4791 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4792 break;
4793 case 8:
eea1cff9 4794 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4795 break;
4796 default:
a737f256 4797 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4798 res = -1;
52a46617 4799 }
0f12244f
GN		 4800
4801 return res;
52a46617
GN		 4802}
4803
717746e3 4804static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4805{
717746e3 4806 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4807}
4808
4bff1e86 4809static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4810{
4bff1e86 4811 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4812}
4813
4bff1e86 4814static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4815{
4bff1e86 4816 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4817}
4818
1ac9d0cf
AK		 4819static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4820{
4821 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4822}
4823
4824static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4825{
4826 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4827}
4828
4bff1e86
AK		 4829static unsigned long emulator_get_cached_segment_base(
4830 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4831{
4bff1e86 4832 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4833}
4834
1aa36616
AK		 4835static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4836 struct desc_struct *desc, u32 *base3,
4837 int seg)
2dafc6c2
GN		 4838{
4839 struct kvm_segment var;
4840
4bff1e86 4841 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4842 *selector = var.selector;
2dafc6c2 4843
378a8b09
GN		 4844 if (var.unusable) {
4845 memset(desc, 0, sizeof(*desc));
2dafc6c2 4846 return false;
378a8b09 4847 }
2dafc6c2
GN		 4848
4849 if (var.g)
4850 var.limit >>= 12;
4851 set_desc_limit(desc, var.limit);
4852 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4853#ifdef CONFIG_X86_64
4854 if (base3)
4855 *base3 = var.base >> 32;
4856#endif
2dafc6c2
GN		 4857 desc->type = var.type;
4858 desc->s = var.s;
4859 desc->dpl = var.dpl;
4860 desc->p = var.present;
4861 desc->avl = var.avl;
4862 desc->l = var.l;
4863 desc->d = var.db;
4864 desc->g = var.g;
4865
4866 return true;
4867}
4868
1aa36616
AK		 4869static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4870 struct desc_struct *desc, u32 base3,
4871 int seg)
2dafc6c2 4872{
4bff1e86 4873 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4874 struct kvm_segment var;
4875
1aa36616 4876 var.selector = selector;
2dafc6c2 4877 var.base = get_desc_base(desc);
5601d05b
GN		 4878#ifdef CONFIG_X86_64
4879 var.base |= ((u64)base3) << 32;
4880#endif
2dafc6c2
GN		 4881 var.limit = get_desc_limit(desc);
4882 if (desc->g)
4883 var.limit = (var.limit << 12) | 0xfff;
4884 var.type = desc->type;
2dafc6c2
GN		 4885 var.dpl = desc->dpl;
4886 var.db = desc->d;
4887 var.s = desc->s;
4888 var.l = desc->l;
4889 var.g = desc->g;
4890 var.avl = desc->avl;
4891 var.present = desc->p;
4892 var.unusable = !var.present;
4893 var.padding = 0;
4894
4895 kvm_set_segment(vcpu, &var, seg);
4896 return;
4897}
4898
717746e3
AK		 4899static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4900 u32 msr_index, u64 *pdata)
4901{
609e36d3
PB		 4902 struct msr_data msr;
4903 int r;
4904
4905 msr.index = msr_index;
4906 msr.host_initiated = false;
4907 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4908 if (r)
4909 return r;
4910
4911 *pdata = msr.data;
4912 return 0;
717746e3
AK		 4913}
4914
4915static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4916 u32 msr_index, u64 data)
4917{
8fe8ab46
WA		 4918 struct msr_data msr;
4919
4920 msr.data = data;
4921 msr.index = msr_index;
4922 msr.host_initiated = false;
4923 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4924}
4925
64d60670
PB		 4926static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4927{
4928 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4929
4930 return vcpu->arch.smbase;
4931}
4932
4933static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4934{
4935 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4936
4937 vcpu->arch.smbase = smbase;
4938}
4939
67f4d428
NA		 4940static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4941 u32 pmc)
4942{
c6702c9d 4943 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4944}
4945
222d21aa
AK		 4946static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4947 u32 pmc, u64 *pdata)
4948{
c6702c9d 4949 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4950}
4951
6c3287f7
AK		 4952static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4953{
4954 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4955}
4956
5037f6f3
AK		 4957static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4958{
4959 preempt_disable();
5197b808 4960 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4961 /*
4962 * CR0.TS may reference the host fpu state, not the guest fpu state,
4963 * so it may be clear at this point.
4964 */
4965 clts();
4966}
4967
4968static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4969{
4970 preempt_enable();
4971}
4972
2953538e 4973static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4974 struct x86_instruction_info *info,
c4f035c6
AK		 4975 enum x86_intercept_stage stage)
4976{
2953538e 4977 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4978}
4979
0017f93a 4980static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4981 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4982{
0017f93a 4983 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4984}
4985
dd856efa
AK		 4986static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4987{
4988 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4989}
4990
4991static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4992{
4993 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4994}
4995
801806d9
NA		 4996static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4997{
4998 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4999}
5000
0225fb50 5001static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5002 .read_gpr = emulator_read_gpr,
5003 .write_gpr = emulator_write_gpr,
1871c602 5004 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5005 .write_std = kvm_write_guest_virt_system,
7a036a6f 5006 .read_phys = kvm_read_guest_phys_system,
1871c602 5007 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5008 .read_emulated = emulator_read_emulated,
5009 .write_emulated = emulator_write_emulated,
5010 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5011 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5012 .pio_in_emulated = emulator_pio_in_emulated,
5013 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5014 .get_segment = emulator_get_segment,
5015 .set_segment = emulator_set_segment,
5951c442 5016 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5017 .get_gdt = emulator_get_gdt,
160ce1f1 5018 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5019 .set_gdt = emulator_set_gdt,
5020 .set_idt = emulator_set_idt,
52a46617
GN		 5021 .get_cr = emulator_get_cr,
5022 .set_cr = emulator_set_cr,
9c537244 5023 .cpl = emulator_get_cpl,
35aa5375
GN		 5024 .get_dr = emulator_get_dr,
5025 .set_dr = emulator_set_dr,
64d60670
PB		 5026 .get_smbase = emulator_get_smbase,
5027 .set_smbase = emulator_set_smbase,
717746e3
AK		 5028 .set_msr = emulator_set_msr,
5029 .get_msr = emulator_get_msr,
67f4d428 5030 .check_pmc = emulator_check_pmc,
222d21aa 5031 .read_pmc = emulator_read_pmc,
6c3287f7 5032 .halt = emulator_halt,
bcaf5cc5 5033 .wbinvd = emulator_wbinvd,
d6aa1000 5034 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5035 .get_fpu = emulator_get_fpu,
5036 .put_fpu = emulator_put_fpu,
c4f035c6 5037 .intercept = emulator_intercept,
bdb42f5a 5038 .get_cpuid = emulator_get_cpuid,
801806d9 5039 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5040};
5041
95cb2295
GN		 5042static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5043{
37ccdcbe 5044 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5045 /*
5046 * an sti; sti; sequence only disable interrupts for the first
5047 * instruction. So, if the last instruction, be it emulated or
5048 * not, left the system with the INT_STI flag enabled, it
5049 * means that the last instruction is an sti. We should not
5050 * leave the flag on in this case. The same goes for mov ss
5051 */
37ccdcbe
PB		 5052 if (int_shadow & mask)
5053 mask = 0;
6addfc42 5054 if (unlikely(int_shadow || mask)) {
95cb2295 5055 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5056 if (!mask)
5057 kvm_make_request(KVM_REQ_EVENT, vcpu);
5058 }
95cb2295
GN		 5059}
5060
ef54bcfe 5061static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5062{
5063 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5064 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5065 return kvm_propagate_fault(vcpu, &ctxt->exception);
5066
5067 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5068 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5069 ctxt->exception.error_code);
54b8486f 5070 else
da9cb575 5071 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5072 return false;
54b8486f
GN		 5073}
5074
8ec4722d
MG		 5075static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5076{
adf52235 5077 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5078 int cs_db, cs_l;
5079
8ec4722d
MG		 5080 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5081
adf52235
TY		 5082 ctxt->eflags = kvm_get_rflags(vcpu);
5083 ctxt->eip = kvm_rip_read(vcpu);
5084 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5085 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5086 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5087 cs_db ? X86EMUL_MODE_PROT32 :
5088 X86EMUL_MODE_PROT16;
a584539b 5089 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5090 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5091 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5092 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5093
dd856efa 5094 init_decode_cache(ctxt);
7ae441ea 5095 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5096}
5097
71f9833b 5098int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5099{
9d74191a 5100 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5101 int ret;
5102
5103 init_emulate_ctxt(vcpu);
5104
9dac77fa
AK		 5105 ctxt->op_bytes = 2;
5106 ctxt->ad_bytes = 2;
5107 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5108 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5109
5110 if (ret != X86EMUL_CONTINUE)
5111 return EMULATE_FAIL;
5112
9dac77fa 5113 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5114 kvm_rip_write(vcpu, ctxt->eip);
5115 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5116
5117 if (irq == NMI_VECTOR)
7460fb4a 5118 vcpu->arch.nmi_pending = 0;
63995653
MG		 5119 else
5120 vcpu->arch.interrupt.pending = false;
5121
5122 return EMULATE_DONE;
5123}
5124EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5125
6d77dbfc
GN		 5126static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5127{
fc3a9157
JR		 5128 int r = EMULATE_DONE;
5129
6d77dbfc
GN		 5130 ++vcpu->stat.insn_emulation_fail;
5131 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5132 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5133 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5134 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5135 vcpu->run->internal.ndata = 0;
5136 r = EMULATE_FAIL;
5137 }
6d77dbfc 5138 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5139
5140 return r;
6d77dbfc
GN		 5141}
5142
93c05d3e 5143static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5144 bool write_fault_to_shadow_pgtable,
5145 int emulation_type)
a6f177ef 5146{
95b3cf69 5147 gpa_t gpa = cr2;
ba049e93 5148 kvm_pfn_t pfn;
a6f177ef 5149
991eebf9
GN		 5150 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5151 return false;
5152
95b3cf69
XG		 5153 if (!vcpu->arch.mmu.direct_map) {
5154 /*
5155 * Write permission should be allowed since only
5156 * write access need to be emulated.
5157 */
5158 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5159
95b3cf69
XG		 5160 /*
5161 * If the mapping is invalid in guest, let cpu retry
5162 * it to generate fault.
5163 */
5164 if (gpa == UNMAPPED_GVA)
5165 return true;
5166 }
a6f177ef 5167
8e3d9d06
XG		 5168 /*
5169 * Do not retry the unhandleable instruction if it faults on the
5170 * readonly host memory, otherwise it will goto a infinite loop:
5171 * retry instruction -> write #PF -> emulation fail -> retry
5172 * instruction -> ...
5173 */
5174 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5175
5176 /*
5177 * If the instruction failed on the error pfn, it can not be fixed,
5178 * report the error to userspace.
5179 */
5180 if (is_error_noslot_pfn(pfn))
5181 return false;
5182
5183 kvm_release_pfn_clean(pfn);
5184
5185 /* The instructions are well-emulated on direct mmu. */
5186 if (vcpu->arch.mmu.direct_map) {
5187 unsigned int indirect_shadow_pages;
5188
5189 spin_lock(&vcpu->kvm->mmu_lock);
5190 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5191 spin_unlock(&vcpu->kvm->mmu_lock);
5192
5193 if (indirect_shadow_pages)
5194 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5195
a6f177ef 5196 return true;
8e3d9d06 5197 }
a6f177ef 5198
95b3cf69
XG		 5199 /*
5200 * if emulation was due to access to shadowed page table
5201 * and it failed try to unshadow page and re-enter the
5202 * guest to let CPU execute the instruction.
5203 */
5204 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5205
5206 /*
5207 * If the access faults on its page table, it can not
5208 * be fixed by unprotecting shadow page and it should
5209 * be reported to userspace.
5210 */
5211 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5212}
5213
1cb3f3ae
XG		 5214static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5215 unsigned long cr2, int emulation_type)
5216{
5217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5218 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5219
5220 last_retry_eip = vcpu->arch.last_retry_eip;
5221 last_retry_addr = vcpu->arch.last_retry_addr;
5222
5223 /*
5224 * If the emulation is caused by #PF and it is non-page_table
5225 * writing instruction, it means the VM-EXIT is caused by shadow
5226 * page protected, we can zap the shadow page and retry this
5227 * instruction directly.
5228 *
5229 * Note: if the guest uses a non-page-table modifying instruction
5230 * on the PDE that points to the instruction, then we will unmap
5231 * the instruction and go to an infinite loop. So, we cache the
5232 * last retried eip and the last fault address, if we meet the eip
5233 * and the address again, we can break out of the potential infinite
5234 * loop.
5235 */
5236 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5237
5238 if (!(emulation_type & EMULTYPE_RETRY))
5239 return false;
5240
5241 if (x86_page_table_writing_insn(ctxt))
5242 return false;
5243
5244 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5245 return false;
5246
5247 vcpu->arch.last_retry_eip = ctxt->eip;
5248 vcpu->arch.last_retry_addr = cr2;
5249
5250 if (!vcpu->arch.mmu.direct_map)
5251 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5252
22368028 5253 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5254
5255 return true;
5256}
5257
716d51ab
GN		 5258static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5259static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5260
64d60670 5261static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5262{
64d60670 5263 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5264 /* This is a good place to trace that we are exiting SMM. */
5265 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5266
64d60670
PB		 5267 if (unlikely(vcpu->arch.smi_pending)) {
5268 kvm_make_request(KVM_REQ_SMI, vcpu);
5269 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5270 } else {
5271 /* Process a latched INIT, if any. */
5272 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5273 }
5274 }
699023e2
PB		 5275
5276 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5277}
5278
5279static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5280{
5281 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5282
a584539b 5283 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5284
5285 if (changed & HF_SMM_MASK)
5286 kvm_smm_changed(vcpu);
a584539b
PB		 5287}
5288
4a1e10d5
PB		 5289static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5290 unsigned long *db)
5291{
5292 u32 dr6 = 0;
5293 int i;
5294 u32 enable, rwlen;
5295
5296 enable = dr7;
5297 rwlen = dr7 >> 16;
5298 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5299 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5300 dr6 |= (1 << i);
5301 return dr6;
5302}
5303
6addfc42 5304static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5305{
5306 struct kvm_run *kvm_run = vcpu->run;
5307
5308 /*
6addfc42
PB		 5309 * rflags is the old, "raw" value of the flags. The new value has
5310 * not been saved yet.
663f4c61
PB		 5311 *
5312 * This is correct even for TF set by the guest, because "the
5313 * processor will not generate this exception after the instruction
5314 * that sets the TF flag".
5315 */
663f4c61
PB		 5316 if (unlikely(rflags & X86_EFLAGS_TF)) {
5317 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5318 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5319 DR6_RTM;
663f4c61
PB		 5320 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5321 kvm_run->debug.arch.exception = DB_VECTOR;
5322 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5323 *r = EMULATE_USER_EXIT;
5324 } else {
5325 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5326 /*
5327 * "Certain debug exceptions may clear bit 0-3. The
5328 * remaining contents of the DR6 register are never
5329 * cleared by the processor".
5330 */
5331 vcpu->arch.dr6 &= ~15;
6f43ed01 5332 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5333 kvm_queue_exception(vcpu, DB_VECTOR);
5334 }
5335 }
5336}
5337
4a1e10d5
PB		 5338static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5339{
4a1e10d5
PB		 5340 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5341 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5342 struct kvm_run *kvm_run = vcpu->run;
5343 unsigned long eip = kvm_get_linear_rip(vcpu);
5344 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5345 vcpu->arch.guest_debug_dr7,
5346 vcpu->arch.eff_db);
5347
5348 if (dr6 != 0) {
6f43ed01 5349 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5350 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5351 kvm_run->debug.arch.exception = DB_VECTOR;
5352 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5353 *r = EMULATE_USER_EXIT;
5354 return true;
5355 }
5356 }
5357
4161a569
NA		 5358 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5359 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5360 unsigned long eip = kvm_get_linear_rip(vcpu);
5361 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5362 vcpu->arch.dr7,
5363 vcpu->arch.db);
5364
5365 if (dr6 != 0) {
5366 vcpu->arch.dr6 &= ~15;
6f43ed01 5367 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5368 kvm_queue_exception(vcpu, DB_VECTOR);
5369 *r = EMULATE_DONE;
5370 return true;
5371 }
5372 }
5373
5374 return false;
5375}
5376
51d8b661
AP		 5377int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5378 unsigned long cr2,
dc25e89e
AP		 5379 int emulation_type,
5380 void *insn,
5381 int insn_len)
bbd9b64e 5382{
95cb2295 5383 int r;
9d74191a 5384 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5385 bool writeback = true;
93c05d3e 5386 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5387
93c05d3e
XG		 5388 /*
5389 * Clear write_fault_to_shadow_pgtable here to ensure it is
5390 * never reused.
5391 */
5392 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5393 kvm_clear_exception_queue(vcpu);
8d7d8102 5394
571008da 5395 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5396 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5397
5398 /*
5399 * We will reenter on the same instruction since
5400 * we do not set complete_userspace_io. This does not
5401 * handle watchpoints yet, those would be handled in
5402 * the emulate_ops.
5403 */
5404 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5405 return r;
5406
9d74191a
TY		 5407 ctxt->interruptibility = 0;
5408 ctxt->have_exception = false;
e0ad0b47 5409 ctxt->exception.vector = -1;
9d74191a 5410 ctxt->perm_ok = false;
bbd9b64e 5411
b51e974f 5412 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5413
9d74191a 5414 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5415
e46479f8 5416 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5417 ++vcpu->stat.insn_emulation;
1d2887e2 5418 if (r != EMULATION_OK) {
4005996e
AK		 5419 if (emulation_type & EMULTYPE_TRAP_UD)
5420 return EMULATE_FAIL;
991eebf9
GN		 5421 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5422 emulation_type))
bbd9b64e 5423 return EMULATE_DONE;
6d77dbfc
GN		 5424 if (emulation_type & EMULTYPE_SKIP)
5425 return EMULATE_FAIL;
5426 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5427 }
5428 }
5429
ba8afb6b 5430 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5431 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5432 if (ctxt->eflags & X86_EFLAGS_RF)
5433 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5434 return EMULATE_DONE;
5435 }
5436
1cb3f3ae
XG		 5437 if (retry_instruction(ctxt, cr2, emulation_type))
5438 return EMULATE_DONE;
5439
7ae441ea 5440 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5441 changes registers values during IO operation */
7ae441ea
GN		 5442 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5443 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5444 emulator_invalidate_register_cache(ctxt);
7ae441ea 5445 }
4d2179e1 5446
5cd21917 5447restart:
9d74191a 5448 r = x86_emulate_insn(ctxt);
bbd9b64e 5449
775fde86
JR		 5450 if (r == EMULATION_INTERCEPTED)
5451 return EMULATE_DONE;
5452
d2ddd1c4 5453 if (r == EMULATION_FAILED) {
991eebf9
GN		 5454 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5455 emulation_type))
c3cd7ffa
GN		 5456 return EMULATE_DONE;
5457
6d77dbfc 5458 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5459 }
5460
9d74191a 5461 if (ctxt->have_exception) {
d2ddd1c4 5462 r = EMULATE_DONE;
ef54bcfe
PB		 5463 if (inject_emulated_exception(vcpu))
5464 return r;
d2ddd1c4 5465 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5466 if (!vcpu->arch.pio.in) {
5467 /* FIXME: return into emulator if single-stepping. */
3457e419 5468 vcpu->arch.pio.count = 0;
0912c977 5469 } else {
7ae441ea 5470 writeback = false;
716d51ab
GN		 5471 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5472 }
ac0a48c3 5473 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5474 } else if (vcpu->mmio_needed) {
5475 if (!vcpu->mmio_is_write)
5476 writeback = false;
ac0a48c3 5477 r = EMULATE_USER_EXIT;
716d51ab 5478 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5479 } else if (r == EMULATION_RESTART)
5cd21917 5480 goto restart;
d2ddd1c4
GN		 5481 else
5482 r = EMULATE_DONE;
f850e2e6 5483
7ae441ea 5484 if (writeback) {
6addfc42 5485 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5486 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5487 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5488 if (vcpu->arch.hflags != ctxt->emul_flags)
5489 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5490 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5491 if (r == EMULATE_DONE)
6addfc42 5492 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5493 if (!ctxt->have_exception ||
5494 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5495 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5496
5497 /*
5498 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5499 * do nothing, and it will be requested again as soon as
5500 * the shadow expires. But we still need to check here,
5501 * because POPF has no interrupt shadow.
5502 */
5503 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5504 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5505 } else
5506 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5507
5508 return r;
de7d789a 5509}
51d8b661 5510EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5511
cf8f70bf 5512int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5513{
cf8f70bf 5514 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5515 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5516 size, port, &val, 1);
cf8f70bf 5517 /* do not return to emulator after return from userspace */
7972995b 5518 vcpu->arch.pio.count = 0;
de7d789a
CO		 5519 return ret;
5520}
cf8f70bf 5521EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5522
8cfdc000
ZA		 5523static void tsc_bad(void *info)
5524{
0a3aee0d 5525 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5526}
5527
5528static void tsc_khz_changed(void *data)
c8076604 5529{
8cfdc000
ZA		 5530 struct cpufreq_freqs *freq = data;
5531 unsigned long khz = 0;
5532
5533 if (data)
5534 khz = freq->new;
5535 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5536 khz = cpufreq_quick_get(raw_smp_processor_id());
5537 if (!khz)
5538 khz = tsc_khz;
0a3aee0d 5539 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5540}
5541
c8076604
GH		 5542static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5543 void *data)
5544{
5545 struct cpufreq_freqs *freq = data;
5546 struct kvm *kvm;
5547 struct kvm_vcpu *vcpu;
5548 int i, send_ipi = 0;
5549
8cfdc000
ZA		 5550 /*
5551 * We allow guests to temporarily run on slowing clocks,
5552 * provided we notify them after, or to run on accelerating
5553 * clocks, provided we notify them before. Thus time never
5554 * goes backwards.
5555 *
5556 * However, we have a problem. We can't atomically update
5557 * the frequency of a given CPU from this function; it is
5558 * merely a notifier, which can be called from any CPU.
5559 * Changing the TSC frequency at arbitrary points in time
5560 * requires a recomputation of local variables related to
5561 * the TSC for each VCPU. We must flag these local variables
5562 * to be updated and be sure the update takes place with the
5563 * new frequency before any guests proceed.
5564 *
5565 * Unfortunately, the combination of hotplug CPU and frequency
5566 * change creates an intractable locking scenario; the order
5567 * of when these callouts happen is undefined with respect to
5568 * CPU hotplug, and they can race with each other. As such,
5569 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5570 * undefined; you can actually have a CPU frequency change take
5571 * place in between the computation of X and the setting of the
5572 * variable. To protect against this problem, all updates of
5573 * the per_cpu tsc_khz variable are done in an interrupt
5574 * protected IPI, and all callers wishing to update the value
5575 * must wait for a synchronous IPI to complete (which is trivial
5576 * if the caller is on the CPU already). This establishes the
5577 * necessary total order on variable updates.
5578 *
5579 * Note that because a guest time update may take place
5580 * anytime after the setting of the VCPU's request bit, the
5581 * correct TSC value must be set before the request. However,
5582 * to ensure the update actually makes it to any guest which
5583 * starts running in hardware virtualization between the set
5584 * and the acquisition of the spinlock, we must also ping the
5585 * CPU after setting the request bit.
5586 *
5587 */
5588
c8076604
GH		 5589 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5590 return 0;
5591 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5592 return 0;
8cfdc000
ZA		 5593
5594 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5595
2f303b74 5596 spin_lock(&kvm_lock);
c8076604 5597 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5598 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5599 if (vcpu->cpu != freq->cpu)
5600 continue;
c285545f 5601 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5602 if (vcpu->cpu != smp_processor_id())
8cfdc000 5603 send_ipi = 1;
c8076604
GH		 5604 }
5605 }
2f303b74 5606 spin_unlock(&kvm_lock);
c8076604
GH		 5607
5608 if (freq->old < freq->new && send_ipi) {
5609 /*
5610 * We upscale the frequency. Must make the guest
5611 * doesn't see old kvmclock values while running with
5612 * the new frequency, otherwise we risk the guest sees
5613 * time go backwards.
5614 *
5615 * In case we update the frequency for another cpu
5616 * (which might be in guest context) send an interrupt
5617 * to kick the cpu out of guest context. Next time
5618 * guest context is entered kvmclock will be updated,
5619 * so the guest will not see stale values.
5620 */
8cfdc000 5621 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5622 }
5623 return 0;
5624}
5625
5626static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5627 .notifier_call = kvmclock_cpufreq_notifier
5628};
5629
5630static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5631 unsigned long action, void *hcpu)
5632{
5633 unsigned int cpu = (unsigned long)hcpu;
5634
5635 switch (action) {
5636 case CPU_ONLINE:
5637 case CPU_DOWN_FAILED:
5638 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5639 break;
5640 case CPU_DOWN_PREPARE:
5641 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5642 break;
5643 }
5644 return NOTIFY_OK;
5645}
5646
5647static struct notifier_block kvmclock_cpu_notifier_block = {
5648 .notifier_call = kvmclock_cpu_notifier,
5649 .priority = -INT_MAX
c8076604
GH		 5650};
5651
b820cc0c
ZA		 5652static void kvm_timer_init(void)
5653{
5654 int cpu;
5655
c285545f 5656 max_tsc_khz = tsc_khz;
460dd42e
SB		 5657
5658 cpu_notifier_register_begin();
b820cc0c 5659 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5660#ifdef CONFIG_CPU_FREQ
5661 struct cpufreq_policy policy;
5662 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5663 cpu = get_cpu();
5664 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5665 if (policy.cpuinfo.max_freq)
5666 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5667 put_cpu();
c285545f 5668#endif
b820cc0c
ZA		 5669 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5670 CPUFREQ_TRANSITION_NOTIFIER);
5671 }
c285545f 5672 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5673 for_each_online_cpu(cpu)
5674 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5675
5676 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5677 cpu_notifier_register_done();
5678
b820cc0c
ZA		 5679}
5680
ff9d07a0
ZY		 5681static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5682
f5132b01 5683int kvm_is_in_guest(void)
ff9d07a0 5684{
086c9855 5685 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5686}
5687
5688static int kvm_is_user_mode(void)
5689{
5690 int user_mode = 3;
dcf46b94 5691
086c9855
AS		 5692 if (__this_cpu_read(current_vcpu))
5693 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5694
ff9d07a0
ZY		 5695 return user_mode != 0;
5696}
5697
5698static unsigned long kvm_get_guest_ip(void)
5699{
5700 unsigned long ip = 0;
dcf46b94 5701
086c9855
AS		 5702 if (__this_cpu_read(current_vcpu))
5703 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5704
ff9d07a0
ZY		 5705 return ip;
5706}
5707
5708static struct perf_guest_info_callbacks kvm_guest_cbs = {
5709 .is_in_guest = kvm_is_in_guest,
5710 .is_user_mode = kvm_is_user_mode,
5711 .get_guest_ip = kvm_get_guest_ip,
5712};
5713
5714void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5715{
086c9855 5716 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5717}
5718EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5719
5720void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5721{
086c9855 5722 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5723}
5724EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5725
ce88decf
XG		 5726static void kvm_set_mmio_spte_mask(void)
5727{
5728 u64 mask;
5729 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5730
5731 /*
5732 * Set the reserved bits and the present bit of an paging-structure
5733 * entry to generate page fault with PFER.RSV = 1.
5734 */
885032b9 5735 /* Mask the reserved physical address bits. */
d1431483 5736 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5737
5738 /* Bit 62 is always reserved for 32bit host. */
5739 mask |= 0x3ull << 62;
5740
5741 /* Set the present bit. */
ce88decf
XG		 5742 mask |= 1ull;
5743
5744#ifdef CONFIG_X86_64
5745 /*
5746 * If reserved bit is not supported, clear the present bit to disable
5747 * mmio page fault.
5748 */
5749 if (maxphyaddr == 52)
5750 mask &= ~1ull;
5751#endif
5752
5753 kvm_mmu_set_mmio_spte_mask(mask);
5754}
5755
16e8d74d
MT		 5756#ifdef CONFIG_X86_64
5757static void pvclock_gtod_update_fn(struct work_struct *work)
5758{
d828199e
MT		 5759 struct kvm *kvm;
5760
5761 struct kvm_vcpu *vcpu;
5762 int i;
5763
2f303b74 5764 spin_lock(&kvm_lock);
d828199e
MT		 5765 list_for_each_entry(kvm, &vm_list, vm_list)
5766 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5767 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5768 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5769 spin_unlock(&kvm_lock);
16e8d74d
MT		 5770}
5771
5772static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5773
5774/*
5775 * Notification about pvclock gtod data update.
5776 */
5777static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5778 void *priv)
5779{
5780 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5781 struct timekeeper *tk = priv;
5782
5783 update_pvclock_gtod(tk);
5784
5785 /* disable master clock if host does not trust, or does not
5786 * use, TSC clocksource
5787 */
5788 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5789 atomic_read(&kvm_guest_has_master_clock) != 0)
5790 queue_work(system_long_wq, &pvclock_gtod_work);
5791
5792 return 0;
5793}
5794
5795static struct notifier_block pvclock_gtod_notifier = {
5796 .notifier_call = pvclock_gtod_notify,
5797};
5798#endif
5799
f8c16bba 5800int kvm_arch_init(void *opaque)
043405e1 5801{
b820cc0c 5802 int r;
6b61edf7 5803 struct kvm_x86_ops *ops = opaque;
f8c16bba 5804
f8c16bba
ZX		 5805 if (kvm_x86_ops) {
5806 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5807 r = -EEXIST;
5808 goto out;
f8c16bba
ZX		 5809 }
5810
5811 if (!ops->cpu_has_kvm_support()) {
5812 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5813 r = -EOPNOTSUPP;
5814 goto out;
f8c16bba
ZX		 5815 }
5816 if (ops->disabled_by_bios()) {
5817 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5818 r = -EOPNOTSUPP;
5819 goto out;
f8c16bba
ZX		 5820 }
5821
013f6a5d
MT		 5822 r = -ENOMEM;
5823 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5824 if (!shared_msrs) {
5825 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5826 goto out;
5827 }
5828
97db56ce
AK		 5829 r = kvm_mmu_module_init();
5830 if (r)
013f6a5d 5831 goto out_free_percpu;
97db56ce 5832
ce88decf 5833 kvm_set_mmio_spte_mask();
97db56ce 5834
f8c16bba 5835 kvm_x86_ops = ops;
920c8377 5836
7b52345e 5837 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5838 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5839
b820cc0c 5840 kvm_timer_init();
c8076604 5841
ff9d07a0
ZY		 5842 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5843
2acf923e
DC		 5844 if (cpu_has_xsave)
5845 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5846
c5cc421b 5847 kvm_lapic_init();
16e8d74d
MT		 5848#ifdef CONFIG_X86_64
5849 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5850#endif
5851
f8c16bba 5852 return 0;
56c6d28a 5853
013f6a5d
MT		 5854out_free_percpu:
5855 free_percpu(shared_msrs);
56c6d28a 5856out:
56c6d28a 5857 return r;
043405e1 5858}
8776e519 5859
f8c16bba
ZX		 5860void kvm_arch_exit(void)
5861{
ff9d07a0
ZY		 5862 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5863
888d256e
JK		 5864 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5865 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5866 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5867 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5868#ifdef CONFIG_X86_64
5869 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5870#endif
f8c16bba 5871 kvm_x86_ops = NULL;
56c6d28a 5872 kvm_mmu_module_exit();
013f6a5d 5873 free_percpu(shared_msrs);
56c6d28a 5874}
f8c16bba 5875
5cb56059 5876int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5877{
5878 ++vcpu->stat.halt_exits;
35754c98 5879 if (lapic_in_kernel(vcpu)) {
a4535290 5880 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5881 return 1;
5882 } else {
5883 vcpu->run->exit_reason = KVM_EXIT_HLT;
5884 return 0;
5885 }
5886}
5cb56059
JS		 5887EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5888
5889int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5890{
5891 kvm_x86_ops->skip_emulated_instruction(vcpu);
5892 return kvm_vcpu_halt(vcpu);
5893}
8776e519
HB		 5894EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5895
6aef266c
SV		 5896/*
5897 * kvm_pv_kick_cpu_op: Kick a vcpu.
5898 *
5899 * @apicid - apicid of vcpu to be kicked.
5900 */
5901static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5902{
24d2166b 5903 struct kvm_lapic_irq lapic_irq;
6aef266c 5904
24d2166b
R		 5905 lapic_irq.shorthand = 0;
5906 lapic_irq.dest_mode = 0;
5907 lapic_irq.dest_id = apicid;
93bbf0b8 5908 lapic_irq.msi_redir_hint = false;
6aef266c 5909
24d2166b 5910 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5911 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5912}
5913
d62caabb
AS		 5914void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5915{
5916 vcpu->arch.apicv_active = false;
5917 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5918}
5919
8776e519
HB		 5920int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5921{
5922 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5923 int op_64_bit, r = 1;
8776e519 5924
5cb56059
JS		 5925 kvm_x86_ops->skip_emulated_instruction(vcpu);
5926
55cd8e5a
GN		 5927 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5928 return kvm_hv_hypercall(vcpu);
5929
5fdbf976
MT		 5930 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5931 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5932 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5933 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5934 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5935
229456fc 5936 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5937
a449c7aa
NA		 5938 op_64_bit = is_64_bit_mode(vcpu);
5939 if (!op_64_bit) {
8776e519
HB		 5940 nr &= 0xFFFFFFFF;
5941 a0 &= 0xFFFFFFFF;
5942 a1 &= 0xFFFFFFFF;
5943 a2 &= 0xFFFFFFFF;
5944 a3 &= 0xFFFFFFFF;
5945 }
5946
07708c4a
JK		 5947 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5948 ret = -KVM_EPERM;
5949 goto out;
5950 }
5951
8776e519 5952 switch (nr) {
b93463aa
AK		 5953 case KVM_HC_VAPIC_POLL_IRQ:
5954 ret = 0;
5955 break;
6aef266c
SV		 5956 case KVM_HC_KICK_CPU:
5957 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5958 ret = 0;
5959 break;
8776e519
HB		 5960 default:
5961 ret = -KVM_ENOSYS;
5962 break;
5963 }
07708c4a 5964out:
a449c7aa
NA		 5965 if (!op_64_bit)
5966 ret = (u32)ret;
5fdbf976 5967 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5968 ++vcpu->stat.hypercalls;
2f333bcb 5969 return r;
8776e519
HB		 5970}
5971EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5972
b6785def 5973static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5974{
d6aa1000 5975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5976 char instruction[3];
5fdbf976 5977 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5978
8776e519 5979 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5980
9d74191a 5981 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5982}
5983
851ba692 5984static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5985{
782d422b
MG		 5986 return vcpu->run->request_interrupt_window &&
5987 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5988}
5989
851ba692 5990static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5991{
851ba692
AK		 5992 struct kvm_run *kvm_run = vcpu->run;
5993
91586a3b 5994 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5995 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5996 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5997 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 5998 kvm_run->ready_for_interrupt_injection =
5999 pic_in_kernel(vcpu->kvm) ||
782d422b 6000 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6001}
6002
95ba8273
GN		 6003static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6004{
6005 int max_irr, tpr;
6006
6007 if (!kvm_x86_ops->update_cr8_intercept)
6008 return;
6009
bce87cce 6010 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6011 return;
6012
d62caabb
AS		 6013 if (vcpu->arch.apicv_active)
6014 return;
6015
8db3baa2
GN		 6016 if (!vcpu->arch.apic->vapic_addr)
6017 max_irr = kvm_lapic_find_highest_irr(vcpu);
6018 else
6019 max_irr = -1;
95ba8273
GN		 6020
6021 if (max_irr != -1)
6022 max_irr >>= 4;
6023
6024 tpr = kvm_lapic_get_cr8(vcpu);
6025
6026 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6027}
6028
b6b8a145 6029static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6030{
b6b8a145
JK		 6031 int r;
6032
95ba8273 6033 /* try to reinject previous events if any */
b59bb7bd 6034 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6035 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6036 vcpu->arch.exception.has_error_code,
6037 vcpu->arch.exception.error_code);
d6e8c854
NA		 6038
6039 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6040 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6041 X86_EFLAGS_RF);
6042
6bdf0662
NA		 6043 if (vcpu->arch.exception.nr == DB_VECTOR &&
6044 (vcpu->arch.dr7 & DR7_GD)) {
6045 vcpu->arch.dr7 &= ~DR7_GD;
6046 kvm_update_dr7(vcpu);
6047 }
6048
b59bb7bd
GN		 6049 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6050 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6051 vcpu->arch.exception.error_code,
6052 vcpu->arch.exception.reinject);
b6b8a145 6053 return 0;
b59bb7bd
GN		 6054 }
6055
95ba8273
GN		 6056 if (vcpu->arch.nmi_injected) {
6057 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6058 return 0;
95ba8273
GN		 6059 }
6060
6061 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6062 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6063 return 0;
6064 }
6065
6066 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6067 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6068 if (r != 0)
6069 return r;
95ba8273
GN		 6070 }
6071
6072 /* try to inject new event if pending */
6073 if (vcpu->arch.nmi_pending) {
6074 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6075 --vcpu->arch.nmi_pending;
95ba8273
GN		 6076 vcpu->arch.nmi_injected = true;
6077 kvm_x86_ops->set_nmi(vcpu);
6078 }
c7c9c56c 6079 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6080 /*
6081 * Because interrupts can be injected asynchronously, we are
6082 * calling check_nested_events again here to avoid a race condition.
6083 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6084 * proposal and current concerns. Perhaps we should be setting
6085 * KVM_REQ_EVENT only on certain events and not unconditionally?
6086 */
6087 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6088 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6089 if (r != 0)
6090 return r;
6091 }
95ba8273 6092 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6093 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6094 false);
6095 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6096 }
6097 }
b6b8a145 6098 return 0;
95ba8273
GN		 6099}
6100
7460fb4a
AK		 6101static void process_nmi(struct kvm_vcpu *vcpu)
6102{
6103 unsigned limit = 2;
6104
6105 /*
6106 * x86 is limited to one NMI running, and one NMI pending after it.
6107 * If an NMI is already in progress, limit further NMIs to just one.
6108 * Otherwise, allow two (and we'll inject the first one immediately).
6109 */
6110 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6111 limit = 1;
6112
6113 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6114 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6115 kvm_make_request(KVM_REQ_EVENT, vcpu);
6116}
6117
660a5d51
PB		 6118#define put_smstate(type, buf, offset, val) \
6119 *(type *)((buf) + (offset) - 0x7e00) = val
6120
6121static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6122{
6123 u32 flags = 0;
6124 flags |= seg->g << 23;
6125 flags |= seg->db << 22;
6126 flags |= seg->l << 21;
6127 flags |= seg->avl << 20;
6128 flags |= seg->present << 15;
6129 flags |= seg->dpl << 13;
6130 flags |= seg->s << 12;
6131 flags |= seg->type << 8;
6132 return flags;
6133}
6134
6135static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6136{
6137 struct kvm_segment seg;
6138 int offset;
6139
6140 kvm_get_segment(vcpu, &seg, n);
6141 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6142
6143 if (n < 3)
6144 offset = 0x7f84 + n * 12;
6145 else
6146 offset = 0x7f2c + (n - 3) * 12;
6147
6148 put_smstate(u32, buf, offset + 8, seg.base);
6149 put_smstate(u32, buf, offset + 4, seg.limit);
6150 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6151}
6152
efbb288a 6153#ifdef CONFIG_X86_64
660a5d51
PB		 6154static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6155{
6156 struct kvm_segment seg;
6157 int offset;
6158 u16 flags;
6159
6160 kvm_get_segment(vcpu, &seg, n);
6161 offset = 0x7e00 + n * 16;
6162
6163 flags = process_smi_get_segment_flags(&seg) >> 8;
6164 put_smstate(u16, buf, offset, seg.selector);
6165 put_smstate(u16, buf, offset + 2, flags);
6166 put_smstate(u32, buf, offset + 4, seg.limit);
6167 put_smstate(u64, buf, offset + 8, seg.base);
6168}
efbb288a 6169#endif
660a5d51
PB		 6170
6171static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6172{
6173 struct desc_ptr dt;
6174 struct kvm_segment seg;
6175 unsigned long val;
6176 int i;
6177
6178 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6179 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6180 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6181 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6182
6183 for (i = 0; i < 8; i++)
6184 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6185
6186 kvm_get_dr(vcpu, 6, &val);
6187 put_smstate(u32, buf, 0x7fcc, (u32)val);
6188 kvm_get_dr(vcpu, 7, &val);
6189 put_smstate(u32, buf, 0x7fc8, (u32)val);
6190
6191 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6192 put_smstate(u32, buf, 0x7fc4, seg.selector);
6193 put_smstate(u32, buf, 0x7f64, seg.base);
6194 put_smstate(u32, buf, 0x7f60, seg.limit);
6195 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6196
6197 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6198 put_smstate(u32, buf, 0x7fc0, seg.selector);
6199 put_smstate(u32, buf, 0x7f80, seg.base);
6200 put_smstate(u32, buf, 0x7f7c, seg.limit);
6201 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6202
6203 kvm_x86_ops->get_gdt(vcpu, &dt);
6204 put_smstate(u32, buf, 0x7f74, dt.address);
6205 put_smstate(u32, buf, 0x7f70, dt.size);
6206
6207 kvm_x86_ops->get_idt(vcpu, &dt);
6208 put_smstate(u32, buf, 0x7f58, dt.address);
6209 put_smstate(u32, buf, 0x7f54, dt.size);
6210
6211 for (i = 0; i < 6; i++)
6212 process_smi_save_seg_32(vcpu, buf, i);
6213
6214 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6215
6216 /* revision id */
6217 put_smstate(u32, buf, 0x7efc, 0x00020000);
6218 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6219}
6220
6221static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6222{
6223#ifdef CONFIG_X86_64
6224 struct desc_ptr dt;
6225 struct kvm_segment seg;
6226 unsigned long val;
6227 int i;
6228
6229 for (i = 0; i < 16; i++)
6230 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6231
6232 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6233 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6234
6235 kvm_get_dr(vcpu, 6, &val);
6236 put_smstate(u64, buf, 0x7f68, val);
6237 kvm_get_dr(vcpu, 7, &val);
6238 put_smstate(u64, buf, 0x7f60, val);
6239
6240 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6241 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6242 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6243
6244 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6245
6246 /* revision id */
6247 put_smstate(u32, buf, 0x7efc, 0x00020064);
6248
6249 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6250
6251 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6252 put_smstate(u16, buf, 0x7e90, seg.selector);
6253 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6254 put_smstate(u32, buf, 0x7e94, seg.limit);
6255 put_smstate(u64, buf, 0x7e98, seg.base);
6256
6257 kvm_x86_ops->get_idt(vcpu, &dt);
6258 put_smstate(u32, buf, 0x7e84, dt.size);
6259 put_smstate(u64, buf, 0x7e88, dt.address);
6260
6261 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6262 put_smstate(u16, buf, 0x7e70, seg.selector);
6263 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6264 put_smstate(u32, buf, 0x7e74, seg.limit);
6265 put_smstate(u64, buf, 0x7e78, seg.base);
6266
6267 kvm_x86_ops->get_gdt(vcpu, &dt);
6268 put_smstate(u32, buf, 0x7e64, dt.size);
6269 put_smstate(u64, buf, 0x7e68, dt.address);
6270
6271 for (i = 0; i < 6; i++)
6272 process_smi_save_seg_64(vcpu, buf, i);
6273#else
6274 WARN_ON_ONCE(1);
6275#endif
6276}
6277
64d60670
PB		 6278static void process_smi(struct kvm_vcpu *vcpu)
6279{
660a5d51 6280 struct kvm_segment cs, ds;
18c3626e 6281 struct desc_ptr dt;
660a5d51
PB		 6282 char buf[512];
6283 u32 cr0;
6284
64d60670
PB		 6285 if (is_smm(vcpu)) {
6286 vcpu->arch.smi_pending = true;
6287 return;
6288 }
6289
660a5d51
PB		 6290 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6291 vcpu->arch.hflags |= HF_SMM_MASK;
6292 memset(buf, 0, 512);
6293 if (guest_cpuid_has_longmode(vcpu))
6294 process_smi_save_state_64(vcpu, buf);
6295 else
6296 process_smi_save_state_32(vcpu, buf);
6297
54bf36aa 6298 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6299
6300 if (kvm_x86_ops->get_nmi_mask(vcpu))
6301 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6302 else
6303 kvm_x86_ops->set_nmi_mask(vcpu, true);
6304
6305 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6306 kvm_rip_write(vcpu, 0x8000);
6307
6308 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6309 kvm_x86_ops->set_cr0(vcpu, cr0);
6310 vcpu->arch.cr0 = cr0;
6311
6312 kvm_x86_ops->set_cr4(vcpu, 0);
6313
18c3626e
PB		 6314 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6315 dt.address = dt.size = 0;
6316 kvm_x86_ops->set_idt(vcpu, &dt);
6317
660a5d51
PB		 6318 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6319
6320 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6321 cs.base = vcpu->arch.smbase;
6322
6323 ds.selector = 0;
6324 ds.base = 0;
6325
6326 cs.limit = ds.limit = 0xffffffff;
6327 cs.type = ds.type = 0x3;
6328 cs.dpl = ds.dpl = 0;
6329 cs.db = ds.db = 0;
6330 cs.s = ds.s = 1;
6331 cs.l = ds.l = 0;
6332 cs.g = ds.g = 1;
6333 cs.avl = ds.avl = 0;
6334 cs.present = ds.present = 1;
6335 cs.unusable = ds.unusable = 0;
6336 cs.padding = ds.padding = 0;
6337
6338 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6339 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6340 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6341 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6342 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6343 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6344
6345 if (guest_cpuid_has_longmode(vcpu))
6346 kvm_x86_ops->set_efer(vcpu, 0);
6347
6348 kvm_update_cpuid(vcpu);
6349 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6350}
6351
2860c4b1
PB		 6352void kvm_make_scan_ioapic_request(struct kvm *kvm)
6353{
6354 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6355}
6356
3d81bc7e 6357static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6358{
5c919412
AS		 6359 u64 eoi_exit_bitmap[4];
6360
3d81bc7e
YZ		 6361 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6362 return;
c7c9c56c 6363
6308630b 6364 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6365
b053b2ae 6366 if (irqchip_split(vcpu->kvm))
6308630b 6367 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6368 else {
d62caabb
AS		 6369 if (vcpu->arch.apicv_active)
6370 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6371 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6372 }
5c919412
AS		 6373 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6374 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6375 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6376}
6377
a70656b6
RK		 6378static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6379{
6380 ++vcpu->stat.tlb_flush;
6381 kvm_x86_ops->tlb_flush(vcpu);
6382}
6383
4256f43f
TC		 6384void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6385{
c24ae0dc
TC		 6386 struct page *page = NULL;
6387
35754c98 6388 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6389 return;
6390
4256f43f
TC		 6391 if (!kvm_x86_ops->set_apic_access_page_addr)
6392 return;
6393
c24ae0dc 6394 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6395 if (is_error_page(page))
6396 return;
c24ae0dc
TC		 6397 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6398
6399 /*
6400 * Do not pin apic access page in memory, the MMU notifier
6401 * will call us again if it is migrated or swapped out.
6402 */
6403 put_page(page);
4256f43f
TC		 6404}
6405EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6406
fe71557a
TC		 6407void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6408 unsigned long address)
6409{
c24ae0dc
TC		 6410 /*
6411 * The physical address of apic access page is stored in the VMCS.
6412 * Update it when it becomes invalid.
6413 */
6414 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6415 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6416}
6417
9357d939 6418/*
362c698f 6419 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6420 * exiting to the userspace. Otherwise, the value will be returned to the
6421 * userspace.
6422 */
851ba692 6423static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6424{
6425 int r;
62a193ed
MG		 6426 bool req_int_win =
6427 dm_request_for_irq_injection(vcpu) &&
6428 kvm_cpu_accept_dm_intr(vcpu);
6429
730dca42 6430 bool req_immediate_exit = false;
b6c7a5dc 6431
3e007509 6432 if (vcpu->requests) {
a8eeb04a 6433 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6434 kvm_mmu_unload(vcpu);
a8eeb04a 6435 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6436 __kvm_migrate_timers(vcpu);
d828199e
MT		 6437 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6438 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6439 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6440 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6441 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6442 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6443 if (unlikely(r))
6444 goto out;
6445 }
a8eeb04a 6446 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6447 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6448 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6449 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6450 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6451 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6452 r = 0;
6453 goto out;
6454 }
a8eeb04a 6455 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6456 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6457 r = 0;
6458 goto out;
6459 }
a8eeb04a 6460 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6461 vcpu->fpu_active = 0;
6462 kvm_x86_ops->fpu_deactivate(vcpu);
6463 }
af585b92
GN		 6464 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6465 /* Page is swapped out. Do synthetic halt */
6466 vcpu->arch.apf.halted = true;
6467 r = 1;
6468 goto out;
6469 }
c9aaa895
GC		 6470 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6471 record_steal_time(vcpu);
64d60670
PB		 6472 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6473 process_smi(vcpu);
7460fb4a
AK		 6474 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6475 process_nmi(vcpu);
f5132b01 6476 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6477 kvm_pmu_handle_event(vcpu);
f5132b01 6478 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6479 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6480 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6481 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6482 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6483 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6484 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6485 vcpu->run->eoi.vector =
6486 vcpu->arch.pending_ioapic_eoi;
6487 r = 0;
6488 goto out;
6489 }
6490 }
3d81bc7e
YZ		 6491 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6492 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6493 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6494 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6495 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6496 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6497 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6498 r = 0;
6499 goto out;
6500 }
e516cebb
AS		 6501 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6502 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6503 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6504 r = 0;
6505 goto out;
6506 }
db397571
AS		 6507 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6508 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6509 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6510 r = 0;
6511 goto out;
6512 }
f3b138c5
AS		 6513
6514 /*
6515 * KVM_REQ_HV_STIMER has to be processed after
6516 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6517 * depend on the guest clock being up-to-date
6518 */
1f4b34f8
AS		 6519 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6520 kvm_hv_process_stimers(vcpu);
2f52d58c 6521 }
b93463aa 6522
bf9f6ac8
FW		 6523 /*
6524 * KVM_REQ_EVENT is not set when posted interrupts are set by
6525 * VT-d hardware, so we have to update RVI unconditionally.
6526 */
6527 if (kvm_lapic_enabled(vcpu)) {
6528 /*
6529 * Update architecture specific hints for APIC
6530 * virtual interrupt delivery.
6531 */
d62caabb 6532 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6533 kvm_x86_ops->hwapic_irr_update(vcpu,
6534 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6535 }
b93463aa 6536
b463a6f7 6537 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6538 kvm_apic_accept_events(vcpu);
6539 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6540 r = 1;
6541 goto out;
6542 }
6543
b6b8a145
JK		 6544 if (inject_pending_event(vcpu, req_int_win) != 0)
6545 req_immediate_exit = true;
b463a6f7 6546 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6547 else if (vcpu->arch.nmi_pending)
c9a7953f 6548 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6549 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6550 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6551
6552 if (kvm_lapic_enabled(vcpu)) {
6553 update_cr8_intercept(vcpu);
6554 kvm_lapic_sync_to_vapic(vcpu);
6555 }
6556 }
6557
d8368af8
AK		 6558 r = kvm_mmu_reload(vcpu);
6559 if (unlikely(r)) {
d905c069 6560 goto cancel_injection;
d8368af8
AK		 6561 }
6562
b6c7a5dc
HB		 6563 preempt_disable();
6564
6565 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6566 if (vcpu->fpu_active)
6567 kvm_load_guest_fpu(vcpu);
2acf923e 6568 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6569
6b7e2d09
XG		 6570 vcpu->mode = IN_GUEST_MODE;
6571
01b71917
MT		 6572 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6573
6b7e2d09
XG		 6574 /* We should set ->mode before check ->requests,
6575 * see the comment in make_all_cpus_request.
6576 */
01b71917 6577 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6578
d94e1dc9 6579 local_irq_disable();
32f88400 6580
6b7e2d09 6581 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6582 || need_resched() || signal_pending(current)) {
6b7e2d09 6583 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6584 smp_wmb();
6c142801
AK		 6585 local_irq_enable();
6586 preempt_enable();
01b71917 6587 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6588 r = 1;
d905c069 6589 goto cancel_injection;
6c142801
AK		 6590 }
6591
d6185f20
NHE		 6592 if (req_immediate_exit)
6593 smp_send_reschedule(vcpu->cpu);
6594
8b89fe1f
PB		 6595 trace_kvm_entry(vcpu->vcpu_id);
6596 wait_lapic_expire(vcpu);
ccf73aaf 6597 __kvm_guest_enter();
b6c7a5dc 6598
42dbaa5a 6599 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6600 set_debugreg(0, 7);
6601 set_debugreg(vcpu->arch.eff_db[0], 0);
6602 set_debugreg(vcpu->arch.eff_db[1], 1);
6603 set_debugreg(vcpu->arch.eff_db[2], 2);
6604 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6605 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6606 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6607 }
b6c7a5dc 6608
851ba692 6609 kvm_x86_ops->run(vcpu);
b6c7a5dc 6610
c77fb5fe
PB		 6611 /*
6612 * Do this here before restoring debug registers on the host. And
6613 * since we do this before handling the vmexit, a DR access vmexit
6614 * can (a) read the correct value of the debug registers, (b) set
6615 * KVM_DEBUGREG_WONT_EXIT again.
6616 */
6617 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6618 int i;
6619
6620 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6621 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6622 for (i = 0; i < KVM_NR_DB_REGS; i++)
6623 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6624 }
6625
24f1e32c
FW		 6626 /*
6627 * If the guest has used debug registers, at least dr7
6628 * will be disabled while returning to the host.
6629 * If we don't have active breakpoints in the host, we don't
6630 * care about the messed up debug address registers. But if
6631 * we have some of them active, restore the old state.
6632 */
59d8eb53 6633 if (hw_breakpoint_active())
24f1e32c 6634 hw_breakpoint_restore();
42dbaa5a 6635
4ba76538 6636 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6637
6b7e2d09 6638 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6639 smp_wmb();
a547c6db
YZ		 6640
6641 /* Interrupt is enabled by handle_external_intr() */
6642 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6643
6644 ++vcpu->stat.exits;
6645
6646 /*
6647 * We must have an instruction between local_irq_enable() and
6648 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6649 * the interrupt shadow. The stat.exits increment will do nicely.
6650 * But we need to prevent reordering, hence this barrier():
6651 */
6652 barrier();
6653
6654 kvm_guest_exit();
6655
6656 preempt_enable();
6657
f656ce01 6658 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6659
b6c7a5dc
HB		 6660 /*
6661 * Profile KVM exit RIPs:
6662 */
6663 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6664 unsigned long rip = kvm_rip_read(vcpu);
6665 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6666 }
6667
cc578287
ZA		 6668 if (unlikely(vcpu->arch.tsc_always_catchup))
6669 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6670
5cfb1d5a
MT		 6671 if (vcpu->arch.apic_attention)
6672 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6673
851ba692 6674 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6675 return r;
6676
6677cancel_injection:
6678 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6679 if (unlikely(vcpu->arch.apic_attention))
6680 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6681out:
6682 return r;
6683}
b6c7a5dc 6684
362c698f
PB		 6685static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6686{
bf9f6ac8
FW		 6687 if (!kvm_arch_vcpu_runnable(vcpu) &&
6688 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6689 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6690 kvm_vcpu_block(vcpu);
6691 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6692
6693 if (kvm_x86_ops->post_block)
6694 kvm_x86_ops->post_block(vcpu);
6695
9c8fd1ba
PB		 6696 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6697 return 1;
6698 }
362c698f
PB		 6699
6700 kvm_apic_accept_events(vcpu);
6701 switch(vcpu->arch.mp_state) {
6702 case KVM_MP_STATE_HALTED:
6703 vcpu->arch.pv.pv_unhalted = false;
6704 vcpu->arch.mp_state =
6705 KVM_MP_STATE_RUNNABLE;
6706 case KVM_MP_STATE_RUNNABLE:
6707 vcpu->arch.apf.halted = false;
6708 break;
6709 case KVM_MP_STATE_INIT_RECEIVED:
6710 break;
6711 default:
6712 return -EINTR;
6713 break;
6714 }
6715 return 1;
6716}
09cec754 6717
5d9bc648
PB		 6718static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6719{
6720 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6721 !vcpu->arch.apf.halted);
6722}
6723
362c698f 6724static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6725{
6726 int r;
f656ce01 6727 struct kvm *kvm = vcpu->kvm;
d7690175 6728
f656ce01 6729 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6730
362c698f 6731 for (;;) {
58f800d5 6732 if (kvm_vcpu_running(vcpu)) {
851ba692 6733 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6734 } else {
362c698f 6735 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6736 }
6737
09cec754
GN		 6738 if (r <= 0)
6739 break;
6740
6741 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6742 if (kvm_cpu_has_pending_timer(vcpu))
6743 kvm_inject_pending_timer_irqs(vcpu);
6744
782d422b
MG		 6745 if (dm_request_for_irq_injection(vcpu) &&
6746 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6747 r = 0;
6748 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6749 ++vcpu->stat.request_irq_exits;
362c698f 6750 break;
09cec754 6751 }
af585b92
GN		 6752
6753 kvm_check_async_pf_completion(vcpu);
6754
09cec754
GN		 6755 if (signal_pending(current)) {
6756 r = -EINTR;
851ba692 6757 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6758 ++vcpu->stat.signal_exits;
362c698f 6759 break;
09cec754
GN		 6760 }
6761 if (need_resched()) {
f656ce01 6762 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6763 cond_resched();
f656ce01 6764 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6765 }
b6c7a5dc
HB		 6766 }
6767
f656ce01 6768 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6769
6770 return r;
6771}
6772
716d51ab
GN		 6773static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6774{
6775 int r;
6776 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6777 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6778 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6779 if (r != EMULATE_DONE)
6780 return 0;
6781 return 1;
6782}
6783
6784static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6785{
6786 BUG_ON(!vcpu->arch.pio.count);
6787
6788 return complete_emulated_io(vcpu);
6789}
6790
f78146b0
AK		 6791/*
6792 * Implements the following, as a state machine:
6793 *
6794 * read:
6795 * for each fragment
87da7e66
XG		 6796 * for each mmio piece in the fragment
6797 * write gpa, len
6798 * exit
6799 * copy data
f78146b0
AK		 6800 * execute insn
6801 *
6802 * write:
6803 * for each fragment
87da7e66
XG		 6804 * for each mmio piece in the fragment
6805 * write gpa, len
6806 * copy data
6807 * exit
f78146b0 6808 */
716d51ab 6809static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6810{
6811 struct kvm_run *run = vcpu->run;
f78146b0 6812 struct kvm_mmio_fragment *frag;
87da7e66 6813 unsigned len;
5287f194 6814
716d51ab 6815 BUG_ON(!vcpu->mmio_needed);
5287f194 6816
716d51ab 6817 /* Complete previous fragment */
87da7e66
XG		 6818 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6819 len = min(8u, frag->len);
716d51ab 6820 if (!vcpu->mmio_is_write)
87da7e66
XG		 6821 memcpy(frag->data, run->mmio.data, len);
6822
6823 if (frag->len <= 8) {
6824 /* Switch to the next fragment. */
6825 frag++;
6826 vcpu->mmio_cur_fragment++;
6827 } else {
6828 /* Go forward to the next mmio piece. */
6829 frag->data += len;
6830 frag->gpa += len;
6831 frag->len -= len;
6832 }
6833
a08d3b3b 6834 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6835 vcpu->mmio_needed = 0;
0912c977
PB		 6836
6837 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6838 if (vcpu->mmio_is_write)
716d51ab
GN		 6839 return 1;
6840 vcpu->mmio_read_completed = 1;
6841 return complete_emulated_io(vcpu);
6842 }
87da7e66 6843
716d51ab
GN		 6844 run->exit_reason = KVM_EXIT_MMIO;
6845 run->mmio.phys_addr = frag->gpa;
6846 if (vcpu->mmio_is_write)
87da7e66
XG		 6847 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6848 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6849 run->mmio.is_write = vcpu->mmio_is_write;
6850 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6851 return 0;
5287f194
AK		 6852}
6853
716d51ab 6854
b6c7a5dc
HB		 6855int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6856{
c5bedc68 6857 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6858 int r;
6859 sigset_t sigsaved;
6860
c4d72e2d 6861 fpu__activate_curr(fpu);
e5c30142 6862
ac9f6dc0
AK		 6863 if (vcpu->sigset_active)
6864 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6865
a4535290 6866 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6867 kvm_vcpu_block(vcpu);
66450a21 6868 kvm_apic_accept_events(vcpu);
d7690175 6869 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6870 r = -EAGAIN;
6871 goto out;
b6c7a5dc
HB		 6872 }
6873
b6c7a5dc 6874 /* re-sync apic's tpr */
35754c98 6875 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6876 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6877 r = -EINVAL;
6878 goto out;
6879 }
6880 }
b6c7a5dc 6881
716d51ab
GN		 6882 if (unlikely(vcpu->arch.complete_userspace_io)) {
6883 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6884 vcpu->arch.complete_userspace_io = NULL;
6885 r = cui(vcpu);
6886 if (r <= 0)
6887 goto out;
6888 } else
6889 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6890
362c698f 6891 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6892
6893out:
f1d86e46 6894 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6895 if (vcpu->sigset_active)
6896 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6897
b6c7a5dc
HB		 6898 return r;
6899}
6900
6901int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6902{
7ae441ea
GN		 6903 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6904 /*
6905 * We are here if userspace calls get_regs() in the middle of
6906 * instruction emulation. Registers state needs to be copied
4a969980 6907 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6908 * that usually, but some bad designed PV devices (vmware
6909 * backdoor interface) need this to work
6910 */
dd856efa 6911 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6912 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6913 }
5fdbf976
MT		 6914 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6915 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6916 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6917 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6918 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6919 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6920 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6921 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6922#ifdef CONFIG_X86_64
5fdbf976
MT		 6923 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6924 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6925 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6926 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6927 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6928 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6929 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6930 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6931#endif
6932
5fdbf976 6933 regs->rip = kvm_rip_read(vcpu);
91586a3b 6934 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6935
b6c7a5dc
HB		 6936 return 0;
6937}
6938
6939int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6940{
7ae441ea
GN		 6941 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6942 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6943
5fdbf976
MT		 6944 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6945 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6946 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6947 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6948 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6949 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6950 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6951 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6952#ifdef CONFIG_X86_64
5fdbf976
MT		 6953 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6954 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6955 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6956 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6957 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6958 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6959 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6960 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6961#endif
6962
5fdbf976 6963 kvm_rip_write(vcpu, regs->rip);
91586a3b 6964 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6965
b4f14abd
JK		 6966 vcpu->arch.exception.pending = false;
6967
3842d135
AK		 6968 kvm_make_request(KVM_REQ_EVENT, vcpu);
6969
b6c7a5dc
HB		 6970 return 0;
6971}
6972
b6c7a5dc
HB		 6973void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6974{
6975 struct kvm_segment cs;
6976
3e6e0aab 6977 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6978 *db = cs.db;
6979 *l = cs.l;
6980}
6981EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6982
6983int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6984 struct kvm_sregs *sregs)
6985{
89a27f4d 6986 struct desc_ptr dt;
b6c7a5dc 6987
3e6e0aab
GT		 6988 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6989 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6990 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6991 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6992 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6993 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6994
3e6e0aab
GT		 6995 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6996 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6997
6998 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6999 sregs->idt.limit = dt.size;
7000 sregs->idt.base = dt.address;
b6c7a5dc 7001 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7002 sregs->gdt.limit = dt.size;
7003 sregs->gdt.base = dt.address;
b6c7a5dc 7004
4d4ec087 7005 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7006 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7007 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7008 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7009 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7010 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7011 sregs->apic_base = kvm_get_apic_base(vcpu);
7012
923c61bb 7013 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7014
36752c9b 7015 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7016 set_bit(vcpu->arch.interrupt.nr,
7017 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7018
b6c7a5dc
HB		 7019 return 0;
7020}
7021
62d9f0db
MT		 7022int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7023 struct kvm_mp_state *mp_state)
7024{
66450a21 7025 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7026 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7027 vcpu->arch.pv.pv_unhalted)
7028 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7029 else
7030 mp_state->mp_state = vcpu->arch.mp_state;
7031
62d9f0db
MT		 7032 return 0;
7033}
7034
7035int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7036 struct kvm_mp_state *mp_state)
7037{
bce87cce 7038 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7039 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7040 return -EINVAL;
7041
7042 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7043 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7044 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7045 } else
7046 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7047 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7048 return 0;
7049}
7050
7f3d35fd
KW		 7051int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7052 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7053{
9d74191a 7054 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7055 int ret;
e01c2426 7056
8ec4722d 7057 init_emulate_ctxt(vcpu);
c697518a 7058
7f3d35fd 7059 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7060 has_error_code, error_code);
c697518a 7061
c697518a 7062 if (ret)
19d04437 7063 return EMULATE_FAIL;
37817f29 7064
9d74191a
TY		 7065 kvm_rip_write(vcpu, ctxt->eip);
7066 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7067 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7068 return EMULATE_DONE;
37817f29
IE		 7069}
7070EXPORT_SYMBOL_GPL(kvm_task_switch);
7071
b6c7a5dc
HB		 7072int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7073 struct kvm_sregs *sregs)
7074{
58cb628d 7075 struct msr_data apic_base_msr;
b6c7a5dc 7076 int mmu_reset_needed = 0;
63f42e02 7077 int pending_vec, max_bits, idx;
89a27f4d 7078 struct desc_ptr dt;
b6c7a5dc 7079
6d1068b3
PM		 7080 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7081 return -EINVAL;
7082
89a27f4d
GN		 7083 dt.size = sregs->idt.limit;
7084 dt.address = sregs->idt.base;
b6c7a5dc 7085 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7086 dt.size = sregs->gdt.limit;
7087 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7088 kvm_x86_ops->set_gdt(vcpu, &dt);
7089
ad312c7c 7090 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7091 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7092 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7093 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7094
2d3ad1f4 7095 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7096
f6801dff 7097 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7098 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7099 apic_base_msr.data = sregs->apic_base;
7100 apic_base_msr.host_initiated = true;
7101 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7102
4d4ec087 7103 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7104 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7105 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7106
fc78f519 7107 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7108 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7109 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7110 kvm_update_cpuid(vcpu);
63f42e02
XG		 7111
7112 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7113 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7114 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7115 mmu_reset_needed = 1;
7116 }
63f42e02 7117 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7118
7119 if (mmu_reset_needed)
7120 kvm_mmu_reset_context(vcpu);
7121
a50abc3b 7122 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7123 pending_vec = find_first_bit(
7124 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7125 if (pending_vec < max_bits) {
66fd3f7f 7126 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7127 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7128 }
7129
3e6e0aab
GT		 7130 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7131 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7132 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7133 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7134 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7135 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7136
3e6e0aab
GT		 7137 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7138 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7139
5f0269f5
ME		 7140 update_cr8_intercept(vcpu);
7141
9c3e4aab 7142 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7143 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7144 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7145 !is_protmode(vcpu))
9c3e4aab
MT		 7146 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7147
3842d135
AK		 7148 kvm_make_request(KVM_REQ_EVENT, vcpu);
7149
b6c7a5dc
HB		 7150 return 0;
7151}
7152
d0bfb940
JK		 7153int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7154 struct kvm_guest_debug *dbg)
b6c7a5dc 7155{
355be0b9 7156 unsigned long rflags;
ae675ef0 7157 int i, r;
b6c7a5dc 7158
4f926bf2
JK		 7159 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7160 r = -EBUSY;
7161 if (vcpu->arch.exception.pending)
2122ff5e 7162 goto out;
4f926bf2
JK		 7163 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7164 kvm_queue_exception(vcpu, DB_VECTOR);
7165 else
7166 kvm_queue_exception(vcpu, BP_VECTOR);
7167 }
7168
91586a3b
JK		 7169 /*
7170 * Read rflags as long as potentially injected trace flags are still
7171 * filtered out.
7172 */
7173 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7174
7175 vcpu->guest_debug = dbg->control;
7176 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7177 vcpu->guest_debug = 0;
7178
7179 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7180 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7181 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7182 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7183 } else {
7184 for (i = 0; i < KVM_NR_DB_REGS; i++)
7185 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7186 }
c8639010 7187 kvm_update_dr7(vcpu);
ae675ef0 7188
f92653ee
JK		 7189 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7190 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7191 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7192
91586a3b
JK		 7193 /*
7194 * Trigger an rflags update that will inject or remove the trace
7195 * flags.
7196 */
7197 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7198
a96036b8 7199 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7200
4f926bf2 7201 r = 0;
d0bfb940 7202
2122ff5e 7203out:
b6c7a5dc
HB		 7204
7205 return r;
7206}
7207
8b006791
ZX		 7208/*
7209 * Translate a guest virtual address to a guest physical address.
7210 */
7211int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7212 struct kvm_translation *tr)
7213{
7214 unsigned long vaddr = tr->linear_address;
7215 gpa_t gpa;
f656ce01 7216 int idx;
8b006791 7217
f656ce01 7218 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7219 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7220 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7221 tr->physical_address = gpa;
7222 tr->valid = gpa != UNMAPPED_GVA;
7223 tr->writeable = 1;
7224 tr->usermode = 0;
8b006791
ZX		 7225
7226 return 0;
7227}
7228
d0752060
HB		 7229int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7230{
c47ada30 7231 struct fxregs_state *fxsave =
7366ed77 7232 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7233
d0752060
HB		 7234 memcpy(fpu->fpr, fxsave->st_space, 128);
7235 fpu->fcw = fxsave->cwd;
7236 fpu->fsw = fxsave->swd;
7237 fpu->ftwx = fxsave->twd;
7238 fpu->last_opcode = fxsave->fop;
7239 fpu->last_ip = fxsave->rip;
7240 fpu->last_dp = fxsave->rdp;
7241 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7242
d0752060
HB		 7243 return 0;
7244}
7245
7246int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7247{
c47ada30 7248 struct fxregs_state *fxsave =
7366ed77 7249 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7250
d0752060
HB		 7251 memcpy(fxsave->st_space, fpu->fpr, 128);
7252 fxsave->cwd = fpu->fcw;
7253 fxsave->swd = fpu->fsw;
7254 fxsave->twd = fpu->ftwx;
7255 fxsave->fop = fpu->last_opcode;
7256 fxsave->rip = fpu->last_ip;
7257 fxsave->rdp = fpu->last_dp;
7258 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7259
d0752060
HB		 7260 return 0;
7261}
7262
0ee6a517 7263static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7264{
bf935b0b 7265 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7266 if (cpu_has_xsaves)
7366ed77 7267 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7268 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7269
2acf923e
DC		 7270 /*
7271 * Ensure guest xcr0 is valid for loading
7272 */
d91cab78 7273 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7274
ad312c7c 7275 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7276}
d0752060
HB		 7277
7278void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7279{
2608d7a1 7280 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7281 return;
7282
2acf923e
DC		 7283 /*
7284 * Restore all possible states in the guest,
7285 * and assume host would use all available bits.
7286 * Guest xcr0 would be loaded later.
7287 */
7288 kvm_put_guest_xcr0(vcpu);
d0752060 7289 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7290 __kernel_fpu_begin();
003e2e8b 7291 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7292 trace_kvm_fpu(1);
d0752060 7293}
d0752060
HB		 7294
7295void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7296{
2acf923e
DC		 7297 kvm_put_guest_xcr0(vcpu);
7298
653f52c3
RR		 7299 if (!vcpu->guest_fpu_loaded) {
7300 vcpu->fpu_counter = 0;
d0752060 7301 return;
653f52c3 7302 }
d0752060
HB		 7303
7304 vcpu->guest_fpu_loaded = 0;
4f836347 7305 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7306 __kernel_fpu_end();
f096ed85 7307 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7308 /*
7309 * If using eager FPU mode, or if the guest is a frequent user
7310 * of the FPU, just leave the FPU active for next time.
7311 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7312 * the FPU in bursts will revert to loading it on demand.
7313 */
a9b4fb7e 7314 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7315 if (++vcpu->fpu_counter < 5)
7316 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7317 }
0c04851c 7318 trace_kvm_fpu(0);
d0752060 7319}
e9b11c17
ZX		 7320
7321void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7322{
12f9a48f 7323 kvmclock_reset(vcpu);
7f1ea208 7324
f5f48ee1 7325 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7326 kvm_x86_ops->vcpu_free(vcpu);
7327}
7328
7329struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7330 unsigned int id)
7331{
c447e76b
LL		 7332 struct kvm_vcpu *vcpu;
7333
6755bae8
ZA		 7334 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7335 printk_once(KERN_WARNING
7336 "kvm: SMP vm created on host with unstable TSC; "
7337 "guest TSC will not be reliable\n");
c447e76b
LL		 7338
7339 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7340
c447e76b 7341 return vcpu;
26e5215f 7342}
e9b11c17 7343
26e5215f
AK		 7344int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7345{
7346 int r;
e9b11c17 7347
19efffa2 7348 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7349 r = vcpu_load(vcpu);
7350 if (r)
7351 return r;
d28bc9dd 7352 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7353 kvm_mmu_setup(vcpu);
e9b11c17 7354 vcpu_put(vcpu);
26e5215f 7355 return r;
e9b11c17
ZX		 7356}
7357
31928aa5 7358void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7359{
8fe8ab46 7360 struct msr_data msr;
332967a3 7361 struct kvm *kvm = vcpu->kvm;
42897d86 7362
31928aa5
DD		 7363 if (vcpu_load(vcpu))
7364 return;
8fe8ab46
WA		 7365 msr.data = 0x0;
7366 msr.index = MSR_IA32_TSC;
7367 msr.host_initiated = true;
7368 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7369 vcpu_put(vcpu);
7370
630994b3
MT		 7371 if (!kvmclock_periodic_sync)
7372 return;
7373
332967a3
AJ		 7374 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7375 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7376}
7377
d40ccc62 7378void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7379{
9fc77441 7380 int r;
344d9588
GN		 7381 vcpu->arch.apf.msr_val = 0;
7382
9fc77441
MT		 7383 r = vcpu_load(vcpu);
7384 BUG_ON(r);
e9b11c17
ZX		 7385 kvm_mmu_unload(vcpu);
7386 vcpu_put(vcpu);
7387
7388 kvm_x86_ops->vcpu_free(vcpu);
7389}
7390
d28bc9dd 7391void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7392{
e69fab5d
PB		 7393 vcpu->arch.hflags = 0;
7394
7460fb4a
AK		 7395 atomic_set(&vcpu->arch.nmi_queued, 0);
7396 vcpu->arch.nmi_pending = 0;
448fa4a9 7397 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7398 kvm_clear_interrupt_queue(vcpu);
7399 kvm_clear_exception_queue(vcpu);
448fa4a9 7400
42dbaa5a 7401 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7402 kvm_update_dr0123(vcpu);
6f43ed01 7403 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7404 kvm_update_dr6(vcpu);
42dbaa5a 7405 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7406 kvm_update_dr7(vcpu);
42dbaa5a 7407
1119022c
NA		 7408 vcpu->arch.cr2 = 0;
7409
3842d135 7410 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7411 vcpu->arch.apf.msr_val = 0;
c9aaa895 7412 vcpu->arch.st.msr_val = 0;
3842d135 7413
12f9a48f
GC		 7414 kvmclock_reset(vcpu);
7415
af585b92
GN		 7416 kvm_clear_async_pf_completion_queue(vcpu);
7417 kvm_async_pf_hash_reset(vcpu);
7418 vcpu->arch.apf.halted = false;
3842d135 7419
64d60670 7420 if (!init_event) {
d28bc9dd 7421 kvm_pmu_reset(vcpu);
64d60670
PB		 7422 vcpu->arch.smbase = 0x30000;
7423 }
f5132b01 7424
66f7b72e
JS		 7425 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7426 vcpu->arch.regs_avail = ~0;
7427 vcpu->arch.regs_dirty = ~0;
7428
d28bc9dd 7429 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7430}
7431
2b4a273b 7432void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7433{
7434 struct kvm_segment cs;
7435
7436 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7437 cs.selector = vector << 8;
7438 cs.base = vector << 12;
7439 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7440 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7441}
7442
13a34e06 7443int kvm_arch_hardware_enable(void)
e9b11c17 7444{
ca84d1a2
ZA		 7445 struct kvm *kvm;
7446 struct kvm_vcpu *vcpu;
7447 int i;
0dd6a6ed
ZA		 7448 int ret;
7449 u64 local_tsc;
7450 u64 max_tsc = 0;
7451 bool stable, backwards_tsc = false;
18863bdd
AK		 7452
7453 kvm_shared_msr_cpu_online();
13a34e06 7454 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7455 if (ret != 0)
7456 return ret;
7457
4ea1636b 7458 local_tsc = rdtsc();
0dd6a6ed
ZA		 7459 stable = !check_tsc_unstable();
7460 list_for_each_entry(kvm, &vm_list, vm_list) {
7461 kvm_for_each_vcpu(i, vcpu, kvm) {
7462 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7463 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7464 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7465 backwards_tsc = true;
7466 if (vcpu->arch.last_host_tsc > max_tsc)
7467 max_tsc = vcpu->arch.last_host_tsc;
7468 }
7469 }
7470 }
7471
7472 /*
7473 * Sometimes, even reliable TSCs go backwards. This happens on
7474 * platforms that reset TSC during suspend or hibernate actions, but
7475 * maintain synchronization. We must compensate. Fortunately, we can
7476 * detect that condition here, which happens early in CPU bringup,
7477 * before any KVM threads can be running. Unfortunately, we can't
7478 * bring the TSCs fully up to date with real time, as we aren't yet far
7479 * enough into CPU bringup that we know how much real time has actually
7480 * elapsed; our helper function, get_kernel_ns() will be using boot
7481 * variables that haven't been updated yet.
7482 *
7483 * So we simply find the maximum observed TSC above, then record the
7484 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7485 * the adjustment will be applied. Note that we accumulate
7486 * adjustments, in case multiple suspend cycles happen before some VCPU
7487 * gets a chance to run again. In the event that no KVM threads get a
7488 * chance to run, we will miss the entire elapsed period, as we'll have
7489 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7490 * loose cycle time. This isn't too big a deal, since the loss will be
7491 * uniform across all VCPUs (not to mention the scenario is extremely
7492 * unlikely). It is possible that a second hibernate recovery happens
7493 * much faster than a first, causing the observed TSC here to be
7494 * smaller; this would require additional padding adjustment, which is
7495 * why we set last_host_tsc to the local tsc observed here.
7496 *
7497 * N.B. - this code below runs only on platforms with reliable TSC,
7498 * as that is the only way backwards_tsc is set above. Also note
7499 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7500 * have the same delta_cyc adjustment applied if backwards_tsc
7501 * is detected. Note further, this adjustment is only done once,
7502 * as we reset last_host_tsc on all VCPUs to stop this from being
7503 * called multiple times (one for each physical CPU bringup).
7504 *
4a969980 7505 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7506 * will be compensated by the logic in vcpu_load, which sets the TSC to
7507 * catchup mode. This will catchup all VCPUs to real time, but cannot
7508 * guarantee that they stay in perfect synchronization.
7509 */
7510 if (backwards_tsc) {
7511 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7512 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7513 list_for_each_entry(kvm, &vm_list, vm_list) {
7514 kvm_for_each_vcpu(i, vcpu, kvm) {
7515 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7516 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7517 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7518 }
7519
7520 /*
7521 * We have to disable TSC offset matching.. if you were
7522 * booting a VM while issuing an S4 host suspend....
7523 * you may have some problem. Solving this issue is
7524 * left as an exercise to the reader.
7525 */
7526 kvm->arch.last_tsc_nsec = 0;
7527 kvm->arch.last_tsc_write = 0;
7528 }
7529
7530 }
7531 return 0;
e9b11c17
ZX		 7532}
7533
13a34e06 7534void kvm_arch_hardware_disable(void)
e9b11c17 7535{
13a34e06
RK		 7536 kvm_x86_ops->hardware_disable();
7537 drop_user_return_notifiers();
e9b11c17
ZX		 7538}
7539
7540int kvm_arch_hardware_setup(void)
7541{
9e9c3fe4
NA		 7542 int r;
7543
7544 r = kvm_x86_ops->hardware_setup();
7545 if (r != 0)
7546 return r;
7547
35181e86
HZ		 7548 if (kvm_has_tsc_control) {
7549 /*
7550 * Make sure the user can only configure tsc_khz values that
7551 * fit into a signed integer.
7552 * A min value is not calculated needed because it will always
7553 * be 1 on all machines.
7554 */
7555 u64 max = min(0x7fffffffULL,
7556 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7557 kvm_max_guest_tsc_khz = max;
7558
ad721883 7559 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7560 }
ad721883 7561
9e9c3fe4
NA		 7562 kvm_init_msr_list();
7563 return 0;
e9b11c17
ZX		 7564}
7565
7566void kvm_arch_hardware_unsetup(void)
7567{
7568 kvm_x86_ops->hardware_unsetup();
7569}
7570
7571void kvm_arch_check_processor_compat(void *rtn)
7572{
7573 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7574}
7575
7576bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7577{
7578 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7579}
7580EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7581
7582bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7583{
7584 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7585}
7586
3e515705
AK		 7587bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7588{
35754c98 7589 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7590}
7591
54e9818f 7592struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7593EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7594
e9b11c17
ZX		 7595int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7596{
7597 struct page *page;
7598 struct kvm *kvm;
7599 int r;
7600
7601 BUG_ON(vcpu->kvm == NULL);
7602 kvm = vcpu->kvm;
7603
d62caabb 7604 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7605 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7606 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7607 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7608 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7609 else
a4535290 7610 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7611
7612 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7613 if (!page) {
7614 r = -ENOMEM;
7615 goto fail;
7616 }
ad312c7c 7617 vcpu->arch.pio_data = page_address(page);
e9b11c17 7618
cc578287 7619 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7620
e9b11c17
ZX		 7621 r = kvm_mmu_create(vcpu);
7622 if (r < 0)
7623 goto fail_free_pio_data;
7624
7625 if (irqchip_in_kernel(kvm)) {
7626 r = kvm_create_lapic(vcpu);
7627 if (r < 0)
7628 goto fail_mmu_destroy;
54e9818f
GN		 7629 } else
7630 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7631
890ca9ae
HY		 7632 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7633 GFP_KERNEL);
7634 if (!vcpu->arch.mce_banks) {
7635 r = -ENOMEM;
443c39bc 7636 goto fail_free_lapic;
890ca9ae
HY		 7637 }
7638 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7639
f1797359
WY		 7640 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7641 r = -ENOMEM;
f5f48ee1 7642 goto fail_free_mce_banks;
f1797359 7643 }
f5f48ee1 7644
0ee6a517 7645 fx_init(vcpu);
66f7b72e 7646
ba904635 7647 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7648 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7649
7650 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7651 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7652
5a4f55cd
EK		 7653 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7654
74545705
RK		 7655 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7656
af585b92 7657 kvm_async_pf_hash_reset(vcpu);
f5132b01 7658 kvm_pmu_init(vcpu);
af585b92 7659
1c1a9ce9
SR		 7660 vcpu->arch.pending_external_vector = -1;
7661
5c919412
AS		 7662 kvm_hv_vcpu_init(vcpu);
7663
e9b11c17 7664 return 0;
0ee6a517 7665
f5f48ee1
SY		 7666fail_free_mce_banks:
7667 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7668fail_free_lapic:
7669 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7670fail_mmu_destroy:
7671 kvm_mmu_destroy(vcpu);
7672fail_free_pio_data:
ad312c7c 7673 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7674fail:
7675 return r;
7676}
7677
7678void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7679{
f656ce01
MT		 7680 int idx;
7681
1f4b34f8 7682 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7683 kvm_pmu_destroy(vcpu);
36cb93fd 7684 kfree(vcpu->arch.mce_banks);
e9b11c17 7685 kvm_free_lapic(vcpu);
f656ce01 7686 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7687 kvm_mmu_destroy(vcpu);
f656ce01 7688 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7689 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7690 if (!lapic_in_kernel(vcpu))
54e9818f 7691 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7692}
d19a9cd2 7693
e790d9ef
RK		 7694void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7695{
ae97a3b8 7696 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7697}
7698
e08b9637 7699int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7700{
e08b9637
CO		 7701 if (type)
7702 return -EINVAL;
7703
6ef768fa 7704 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7705 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7706 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7707 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7708 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7709
5550af4d
SY		 7710 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7711 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7712 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7713 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7714 &kvm->arch.irq_sources_bitmap);
5550af4d 7715
038f8c11 7716 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7717 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7718 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7719
7720 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7721
7e44e449 7722 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7723 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7724
d89f5eff 7725 return 0;
d19a9cd2
ZX		 7726}
7727
7728static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7729{
9fc77441
MT		 7730 int r;
7731 r = vcpu_load(vcpu);
7732 BUG_ON(r);
d19a9cd2
ZX		 7733 kvm_mmu_unload(vcpu);
7734 vcpu_put(vcpu);
7735}
7736
7737static void kvm_free_vcpus(struct kvm *kvm)
7738{
7739 unsigned int i;
988a2cae 7740 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7741
7742 /*
7743 * Unpin any mmu pages first.
7744 */
af585b92
GN		 7745 kvm_for_each_vcpu(i, vcpu, kvm) {
7746 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7747 kvm_unload_vcpu_mmu(vcpu);
af585b92 7748 }
988a2cae
GN		 7749 kvm_for_each_vcpu(i, vcpu, kvm)
7750 kvm_arch_vcpu_free(vcpu);
7751
7752 mutex_lock(&kvm->lock);
7753 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7754 kvm->vcpus[i] = NULL;
d19a9cd2 7755
988a2cae
GN		 7756 atomic_set(&kvm->online_vcpus, 0);
7757 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7758}
7759
ad8ba2cd
SY		 7760void kvm_arch_sync_events(struct kvm *kvm)
7761{
332967a3 7762 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7763 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7764 kvm_free_all_assigned_devices(kvm);
aea924f6 7765 kvm_free_pit(kvm);
ad8ba2cd
SY		 7766}
7767
1d8007bd 7768int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7769{
7770 int i, r;
25188b99 7771 unsigned long hva;
f0d648bd
PB		 7772 struct kvm_memslots *slots = kvm_memslots(kvm);
7773 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7774
7775 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7776 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7777 return -EINVAL;
9da0e4d5 7778
f0d648bd
PB		 7779 slot = id_to_memslot(slots, id);
7780 if (size) {
7781 if (WARN_ON(slot->npages))
7782 return -EEXIST;
7783
7784 /*
7785 * MAP_SHARED to prevent internal slot pages from being moved
7786 * by fork()/COW.
7787 */
7788 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7789 MAP_SHARED | MAP_ANONYMOUS, 0);
7790 if (IS_ERR((void *)hva))
7791 return PTR_ERR((void *)hva);
7792 } else {
7793 if (!slot->npages)
7794 return 0;
7795
7796 hva = 0;
7797 }
7798
7799 old = *slot;
9da0e4d5 7800 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7801 struct kvm_userspace_memory_region m;
9da0e4d5 7802
1d8007bd
PB		 7803 m.slot = id | (i << 16);
7804 m.flags = 0;
7805 m.guest_phys_addr = gpa;
f0d648bd 7806 m.userspace_addr = hva;
1d8007bd 7807 m.memory_size = size;
9da0e4d5
PB		 7808 r = __kvm_set_memory_region(kvm, &m);
7809 if (r < 0)
7810 return r;
7811 }
7812
f0d648bd
PB		 7813 if (!size) {
7814 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7815 WARN_ON(r < 0);
7816 }
7817
9da0e4d5
PB		 7818 return 0;
7819}
7820EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7821
1d8007bd 7822int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7823{
7824 int r;
7825
7826 mutex_lock(&kvm->slots_lock);
1d8007bd 7827 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7828 mutex_unlock(&kvm->slots_lock);
7829
7830 return r;
7831}
7832EXPORT_SYMBOL_GPL(x86_set_memory_region);
7833
d19a9cd2
ZX		 7834void kvm_arch_destroy_vm(struct kvm *kvm)
7835{
27469d29
AH		 7836 if (current->mm == kvm->mm) {
7837 /*
7838 * Free memory regions allocated on behalf of userspace,
7839 * unless the the memory map has changed due to process exit
7840 * or fd copying.
7841 */
1d8007bd
PB		 7842 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7843 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7844 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7845 }
6eb55818 7846 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7847 kfree(kvm->arch.vpic);
7848 kfree(kvm->arch.vioapic);
d19a9cd2 7849 kvm_free_vcpus(kvm);
1e08ec4a 7850 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7851}
0de10343 7852
5587027c 7853void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7854 struct kvm_memory_slot *dont)
7855{
7856 int i;
7857
d89cc617
TY		 7858 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7859 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7860 kvfree(free->arch.rmap[i]);
d89cc617 7861 free->arch.rmap[i] = NULL;
77d11309 7862 }
d89cc617
TY		 7863 if (i == 0)
7864 continue;
7865
7866 if (!dont || free->arch.lpage_info[i - 1] !=
7867 dont->arch.lpage_info[i - 1]) {
548ef284 7868 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7869 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7870 }
7871 }
7872}
7873
5587027c
AK		 7874int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7875 unsigned long npages)
db3fe4eb
TY		 7876{
7877 int i;
7878
d89cc617 7879 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7880 unsigned long ugfn;
7881 int lpages;
d89cc617 7882 int level = i + 1;
db3fe4eb
TY		 7883
7884 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7885 slot->base_gfn, level) + 1;
7886
d89cc617
TY		 7887 slot->arch.rmap[i] =
7888 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7889 if (!slot->arch.rmap[i])
77d11309 7890 goto out_free;
d89cc617
TY		 7891 if (i == 0)
7892 continue;
77d11309 7893
d89cc617
TY		 7894 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7895 sizeof(*slot->arch.lpage_info[i - 1]));
7896 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7897 goto out_free;
7898
7899 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7900 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7901 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7902 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7903 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7904 /*
7905 * If the gfn and userspace address are not aligned wrt each
7906 * other, or if explicitly asked to, disable large page
7907 * support for this slot
7908 */
7909 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7910 !kvm_largepages_enabled()) {
7911 unsigned long j;
7912
7913 for (j = 0; j < lpages; ++j)
d89cc617 7914 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7915 }
7916 }
7917
7918 return 0;
7919
7920out_free:
d89cc617 7921 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7922 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7923 slot->arch.rmap[i] = NULL;
7924 if (i == 0)
7925 continue;
7926
548ef284 7927 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7928 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7929 }
7930 return -ENOMEM;
7931}
7932
15f46015 7933void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7934{
e6dff7d1
TY		 7935 /*
7936 * memslots->generation has been incremented.
7937 * mmio generation may have reached its maximum value.
7938 */
54bf36aa 7939 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7940}
7941
f7784b8e
MT		 7942int kvm_arch_prepare_memory_region(struct kvm *kvm,
7943 struct kvm_memory_slot *memslot,
09170a49 7944 const struct kvm_userspace_memory_region *mem,
7b6195a9 7945 enum kvm_mr_change change)
0de10343 7946{
f7784b8e
MT		 7947 return 0;
7948}
7949
88178fd4
KH		 7950static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7951 struct kvm_memory_slot *new)
7952{
7953 /* Still write protect RO slot */
7954 if (new->flags & KVM_MEM_READONLY) {
7955 kvm_mmu_slot_remove_write_access(kvm, new);
7956 return;
7957 }
7958
7959 /*
7960 * Call kvm_x86_ops dirty logging hooks when they are valid.
7961 *
7962 * kvm_x86_ops->slot_disable_log_dirty is called when:
7963 *
7964 * - KVM_MR_CREATE with dirty logging is disabled
7965 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7966 *
7967 * The reason is, in case of PML, we need to set D-bit for any slots
7968 * with dirty logging disabled in order to eliminate unnecessary GPA
7969 * logging in PML buffer (and potential PML buffer full VMEXT). This
7970 * guarantees leaving PML enabled during guest's lifetime won't have
7971 * any additonal overhead from PML when guest is running with dirty
7972 * logging disabled for memory slots.
7973 *
7974 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7975 * to dirty logging mode.
7976 *
7977 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7978 *
7979 * In case of write protect:
7980 *
7981 * Write protect all pages for dirty logging.
7982 *
7983 * All the sptes including the large sptes which point to this
7984 * slot are set to readonly. We can not create any new large
7985 * spte on this slot until the end of the logging.
7986 *
7987 * See the comments in fast_page_fault().
7988 */
7989 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7990 if (kvm_x86_ops->slot_enable_log_dirty)
7991 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7992 else
7993 kvm_mmu_slot_remove_write_access(kvm, new);
7994 } else {
7995 if (kvm_x86_ops->slot_disable_log_dirty)
7996 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7997 }
7998}
7999
f7784b8e 8000void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8001 const struct kvm_userspace_memory_region *mem,
8482644a 8002 const struct kvm_memory_slot *old,
f36f3f28 8003 const struct kvm_memory_slot *new,
8482644a 8004 enum kvm_mr_change change)
f7784b8e 8005{
8482644a 8006 int nr_mmu_pages = 0;
f7784b8e 8007
48c0e4e9
XG		 8008 if (!kvm->arch.n_requested_mmu_pages)
8009 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8010
48c0e4e9 8011 if (nr_mmu_pages)
0de10343 8012 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8013
3ea3b7fa
WL		 8014 /*
8015 * Dirty logging tracks sptes in 4k granularity, meaning that large
8016 * sptes have to be split. If live migration is successful, the guest
8017 * in the source machine will be destroyed and large sptes will be
8018 * created in the destination. However, if the guest continues to run
8019 * in the source machine (for example if live migration fails), small
8020 * sptes will remain around and cause bad performance.
8021 *
8022 * Scan sptes if dirty logging has been stopped, dropping those
8023 * which can be collapsed into a single large-page spte. Later
8024 * page faults will create the large-page sptes.
8025 */
8026 if ((change != KVM_MR_DELETE) &&
8027 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8028 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8029 kvm_mmu_zap_collapsible_sptes(kvm, new);
8030
c972f3b1 8031 /*
88178fd4 8032 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8033 *
88178fd4
KH		 8034 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8035 * been zapped so no dirty logging staff is needed for old slot. For
8036 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8037 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8038 *
8039 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8040 */
88178fd4 8041 if (change != KVM_MR_DELETE)
f36f3f28 8042 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8043}
1d737c8a 8044
2df72e9b 8045void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8046{
6ca18b69 8047 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8048}
8049
2df72e9b
MT		 8050void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8051 struct kvm_memory_slot *slot)
8052{
6ca18b69 8053 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8054}
8055
5d9bc648
PB		 8056static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8057{
8058 if (!list_empty_careful(&vcpu->async_pf.done))
8059 return true;
8060
8061 if (kvm_apic_has_events(vcpu))
8062 return true;
8063
8064 if (vcpu->arch.pv.pv_unhalted)
8065 return true;
8066
8067 if (atomic_read(&vcpu->arch.nmi_queued))
8068 return true;
8069
73917739
PB		 8070 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8071 return true;
8072
5d9bc648
PB		 8073 if (kvm_arch_interrupt_allowed(vcpu) &&
8074 kvm_cpu_has_interrupt(vcpu))
8075 return true;
8076
1f4b34f8
AS		 8077 if (kvm_hv_has_stimer_pending(vcpu))
8078 return true;
8079
5d9bc648
PB		 8080 return false;
8081}
8082
1d737c8a
ZX		 8083int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8084{
b6b8a145
JK		 8085 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8086 kvm_x86_ops->check_nested_events(vcpu, false);
8087
5d9bc648 8088 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8089}
5736199a 8090
b6d33834 8091int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8092{
b6d33834 8093 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8094}
78646121
GN		 8095
8096int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8097{
8098 return kvm_x86_ops->interrupt_allowed(vcpu);
8099}
229456fc 8100
82b32774 8101unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8102{
82b32774
NA		 8103 if (is_64_bit_mode(vcpu))
8104 return kvm_rip_read(vcpu);
8105 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8106 kvm_rip_read(vcpu));
8107}
8108EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8109
82b32774
NA		 8110bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8111{
8112 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8113}
8114EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8115
94fe45da
JK		 8116unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8117{
8118 unsigned long rflags;
8119
8120 rflags = kvm_x86_ops->get_rflags(vcpu);
8121 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8122 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8123 return rflags;
8124}
8125EXPORT_SYMBOL_GPL(kvm_get_rflags);
8126
6addfc42 8127static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8128{
8129 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8130 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8131 rflags |= X86_EFLAGS_TF;
94fe45da 8132 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8133}
8134
8135void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8136{
8137 __kvm_set_rflags(vcpu, rflags);
3842d135 8138 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8139}
8140EXPORT_SYMBOL_GPL(kvm_set_rflags);
8141
56028d08
GN		 8142void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8143{
8144 int r;
8145
fb67e14f 8146 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8147 work->wakeup_all)
56028d08
GN		 8148 return;
8149
8150 r = kvm_mmu_reload(vcpu);
8151 if (unlikely(r))
8152 return;
8153
fb67e14f
XG		 8154 if (!vcpu->arch.mmu.direct_map &&
8155 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8156 return;
8157
56028d08
GN		 8158 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8159}
8160
af585b92
GN		 8161static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8162{
8163 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8164}
8165
8166static inline u32 kvm_async_pf_next_probe(u32 key)
8167{
8168 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8169}
8170
8171static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8172{
8173 u32 key = kvm_async_pf_hash_fn(gfn);
8174
8175 while (vcpu->arch.apf.gfns[key] != ~0)
8176 key = kvm_async_pf_next_probe(key);
8177
8178 vcpu->arch.apf.gfns[key] = gfn;
8179}
8180
8181static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8182{
8183 int i;
8184 u32 key = kvm_async_pf_hash_fn(gfn);
8185
8186 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8187 (vcpu->arch.apf.gfns[key] != gfn &&
8188 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8189 key = kvm_async_pf_next_probe(key);
8190
8191 return key;
8192}
8193
8194bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8195{
8196 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8197}
8198
8199static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8200{
8201 u32 i, j, k;
8202
8203 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8204 while (true) {
8205 vcpu->arch.apf.gfns[i] = ~0;
8206 do {
8207 j = kvm_async_pf_next_probe(j);
8208 if (vcpu->arch.apf.gfns[j] == ~0)
8209 return;
8210 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8211 /*
8212 * k lies cyclically in ]i,j]
8213 * | i.k.j |
8214 * |....j i.k.| or |.k..j i...|
8215 */
8216 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8217 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8218 i = j;
8219 }
8220}
8221
7c90705b
GN		 8222static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8223{
8224
8225 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8226 sizeof(val));
8227}
8228
af585b92
GN		 8229void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8230 struct kvm_async_pf *work)
8231{
6389ee94
AK		 8232 struct x86_exception fault;
8233
7c90705b 8234 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8235 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8236
8237 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8238 (vcpu->arch.apf.send_user_only &&
8239 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8240 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8241 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8242 fault.vector = PF_VECTOR;
8243 fault.error_code_valid = true;
8244 fault.error_code = 0;
8245 fault.nested_page_fault = false;
8246 fault.address = work->arch.token;
8247 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8248 }
af585b92
GN		 8249}
8250
8251void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8252 struct kvm_async_pf *work)
8253{
6389ee94
AK		 8254 struct x86_exception fault;
8255
7c90705b 8256 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8257 if (work->wakeup_all)
7c90705b
GN		 8258 work->arch.token = ~0; /* broadcast wakeup */
8259 else
8260 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8261
8262 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8263 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8264 fault.vector = PF_VECTOR;
8265 fault.error_code_valid = true;
8266 fault.error_code = 0;
8267 fault.nested_page_fault = false;
8268 fault.address = work->arch.token;
8269 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8270 }
e6d53e3b 8271 vcpu->arch.apf.halted = false;
a4fa1635 8272 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8273}
8274
8275bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8276{
8277 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8278 return true;
8279 else
8280 return !kvm_event_needs_reinjection(vcpu) &&
8281 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8282}
8283
5544eb9b
PB		 8284void kvm_arch_start_assignment(struct kvm *kvm)
8285{
8286 atomic_inc(&kvm->arch.assigned_device_count);
8287}
8288EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8289
8290void kvm_arch_end_assignment(struct kvm *kvm)
8291{
8292 atomic_dec(&kvm->arch.assigned_device_count);
8293}
8294EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8295
8296bool kvm_arch_has_assigned_device(struct kvm *kvm)
8297{
8298 return atomic_read(&kvm->arch.assigned_device_count);
8299}
8300EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8301
e0f0bbc5
AW		 8302void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8303{
8304 atomic_inc(&kvm->arch.noncoherent_dma_count);
8305}
8306EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8307
8308void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8309{
8310 atomic_dec(&kvm->arch.noncoherent_dma_count);
8311}
8312EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8313
8314bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8315{
8316 return atomic_read(&kvm->arch.noncoherent_dma_count);
8317}
8318EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8319
87276880
FW		 8320int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8321 struct irq_bypass_producer *prod)
8322{
8323 struct kvm_kernel_irqfd *irqfd =
8324 container_of(cons, struct kvm_kernel_irqfd, consumer);
8325
8326 if (kvm_x86_ops->update_pi_irte) {
8327 irqfd->producer = prod;
8328 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8329 prod->irq, irqfd->gsi, 1);
8330 }
8331
8332 return -EINVAL;
8333}
8334
8335void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8336 struct irq_bypass_producer *prod)
8337{
8338 int ret;
8339 struct kvm_kernel_irqfd *irqfd =
8340 container_of(cons, struct kvm_kernel_irqfd, consumer);
8341
8342 if (!kvm_x86_ops->update_pi_irte) {
8343 WARN_ON(irqfd->producer != NULL);
8344 return;
8345 }
8346
8347 WARN_ON(irqfd->producer != prod);
8348 irqfd->producer = NULL;
8349
8350 /*
8351 * When producer of consumer is unregistered, we change back to
8352 * remapped mode, so we can re-use the current implementation
8353 * when the irq is masked/disabed or the consumer side (KVM
8354 * int this case doesn't want to receive the interrupts.
8355 */
8356 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8357 if (ret)
8358 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8359 " fails: %d\n", irqfd->consumer.token, ret);
8360}
8361
8362int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8363 uint32_t guest_irq, bool set)
8364{
8365 if (!kvm_x86_ops->update_pi_irte)
8366 return -EINVAL;
8367
8368 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8369}
8370
52004014
FW		 8371bool kvm_vector_hashing_enabled(void)
8372{
8373 return vector_hashing;
8374}
8375EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8376
229456fc 8377EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8378EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8379EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8380EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8381EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8382EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8383EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8384EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8385EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8386EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8387EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8388EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8389EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8390EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8391EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8392EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8393EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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