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KVM: introduce kvm->created_vcpus
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 94static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 95static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 96
893590c7 97struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 98EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 99
893590c7 100static bool __read_mostly ignore_msrs = 0;
476bc001 101module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 102
9ed96e87
MT		 103unsigned int min_timer_period_us = 500;
104module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105
630994b3
MT		 106static bool __read_mostly kvmclock_periodic_sync = true;
107module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108
893590c7 109bool __read_mostly kvm_has_tsc_control;
92a1f12d 110EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 111u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 112EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 113u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
114EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
115u64 __read_mostly kvm_max_tsc_scaling_ratio;
116EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 117static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 118
cc578287 119/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 120static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 121module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122
d0659d94 123/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 124unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 125module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126
52004014
FW		 127static bool __read_mostly vector_hashing = true;
128module_param(vector_hashing, bool, S_IRUGO);
129
893590c7 130static bool __read_mostly backwards_tsc_observed = false;
16a96021 131
18863bdd
AK		 132#define KVM_NR_SHARED_MSRS 16
133
134struct kvm_shared_msrs_global {
135 int nr;
2bf78fa7 136 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 137};
138
139struct kvm_shared_msrs {
140 struct user_return_notifier urn;
141 bool registered;
2bf78fa7
SY		 142 struct kvm_shared_msr_values {
143 u64 host;
144 u64 curr;
145 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 149static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 150
417bc304 151struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 152 { "pf_fixed", VCPU_STAT(pf_fixed) },
153 { "pf_guest", VCPU_STAT(pf_guest) },
154 { "tlb_flush", VCPU_STAT(tlb_flush) },
155 { "invlpg", VCPU_STAT(invlpg) },
156 { "exits", VCPU_STAT(exits) },
157 { "io_exits", VCPU_STAT(io_exits) },
158 { "mmio_exits", VCPU_STAT(mmio_exits) },
159 { "signal_exits", VCPU_STAT(signal_exits) },
160 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 161 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 162 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 163 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 164 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 165 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 166 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 167 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 168 { "request_irq", VCPU_STAT(request_irq_exits) },
169 { "irq_exits", VCPU_STAT(irq_exits) },
170 { "host_state_reload", VCPU_STAT(host_state_reload) },
171 { "efer_reload", VCPU_STAT(efer_reload) },
172 { "fpu_reload", VCPU_STAT(fpu_reload) },
173 { "insn_emulation", VCPU_STAT(insn_emulation) },
174 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 175 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 176 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 177 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
178 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
179 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
180 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
181 { "mmu_flooded", VM_STAT(mmu_flooded) },
182 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 183 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 184 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 185 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 186 { "largepages", VM_STAT(lpages) },
417bc304
HB		 187 { NULL }
188};
189
2acf923e
DC		 190u64 __read_mostly host_xcr0;
191
b6785def 192static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 193
af585b92
GN		 194static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
195{
196 int i;
197 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
198 vcpu->arch.apf.gfns[i] = ~0;
199}
200
18863bdd
AK		 201static void kvm_on_user_return(struct user_return_notifier *urn)
202{
203 unsigned slot;
18863bdd
AK		 204 struct kvm_shared_msrs *locals
205 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 206 struct kvm_shared_msr_values *values;
18863bdd
AK		 207
208 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 209 values = &locals->values[slot];
210 if (values->host != values->curr) {
211 wrmsrl(shared_msrs_global.msrs[slot], values->host);
212 values->curr = values->host;
18863bdd
AK		 213 }
214 }
215 locals->registered = false;
216 user_return_notifier_unregister(urn);
217}
218
2bf78fa7 219static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 220{
18863bdd 221 u64 value;
013f6a5d
MT		 222 unsigned int cpu = smp_processor_id();
223 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 224
2bf78fa7
SY		 225 /* only read, and nobody should modify it at this time,
226 * so don't need lock */
227 if (slot >= shared_msrs_global.nr) {
228 printk(KERN_ERR "kvm: invalid MSR slot!");
229 return;
230 }
231 rdmsrl_safe(msr, &value);
232 smsr->values[slot].host = value;
233 smsr->values[slot].curr = value;
234}
235
236void kvm_define_shared_msr(unsigned slot, u32 msr)
237{
0123be42 238 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 239 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 240 if (slot >= shared_msrs_global.nr)
241 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 242}
243EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
244
245static void kvm_shared_msr_cpu_online(void)
246{
247 unsigned i;
18863bdd
AK		 248
249 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 250 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 251}
252
8b3c3104 253int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 254{
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 257 int err;
18863bdd 258
2bf78fa7 259 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 260 return 0;
2bf78fa7 261 smsr->values[slot].curr = value;
8b3c3104
AH		 262 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
263 if (err)
264 return 1;
265
18863bdd
AK		 266 if (!smsr->registered) {
267 smsr->urn.on_user_return = kvm_on_user_return;
268 user_return_notifier_register(&smsr->urn);
269 smsr->registered = true;
270 }
8b3c3104 271 return 0;
18863bdd
AK		 272}
273EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
274
13a34e06 275static void drop_user_return_notifiers(void)
3548bab5 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 279
280 if (smsr->registered)
281 kvm_on_user_return(&smsr->urn);
282}
283
6866b83e
CO		 284u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
285{
8a5a87d9 286 return vcpu->arch.apic_base;
6866b83e
CO		 287}
288EXPORT_SYMBOL_GPL(kvm_get_apic_base);
289
58cb628d
JK		 290int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
291{
292 u64 old_state = vcpu->arch.apic_base &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 new_state = msr_info->data &
295 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
296 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
297 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
298
299 if (!msr_info->host_initiated &&
300 ((msr_info->data & reserved_bits) != 0 ||
301 new_state == X2APIC_ENABLE ||
302 (new_state == MSR_IA32_APICBASE_ENABLE &&
303 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
304 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
305 old_state == 0)))
306 return 1;
307
308 kvm_lapic_set_base(vcpu, msr_info->data);
309 return 0;
6866b83e
CO		 310}
311EXPORT_SYMBOL_GPL(kvm_set_apic_base);
312
2605fc21 313asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 314{
315 /* Fault while not rebooting. We want the trace. */
316 BUG();
317}
318EXPORT_SYMBOL_GPL(kvm_spurious_fault);
319
3fd28fce
ED		 320#define EXCPT_BENIGN 0
321#define EXCPT_CONTRIBUTORY 1
322#define EXCPT_PF 2
323
324static int exception_class(int vector)
325{
326 switch (vector) {
327 case PF_VECTOR:
328 return EXCPT_PF;
329 case DE_VECTOR:
330 case TS_VECTOR:
331 case NP_VECTOR:
332 case SS_VECTOR:
333 case GP_VECTOR:
334 return EXCPT_CONTRIBUTORY;
335 default:
336 break;
337 }
338 return EXCPT_BENIGN;
339}
340
d6e8c854
NA		 341#define EXCPT_FAULT 0
342#define EXCPT_TRAP 1
343#define EXCPT_ABORT 2
344#define EXCPT_INTERRUPT 3
345
346static int exception_type(int vector)
347{
348 unsigned int mask;
349
350 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
351 return EXCPT_INTERRUPT;
352
353 mask = 1 << vector;
354
355 /* #DB is trap, as instruction watchpoints are handled elsewhere */
356 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
357 return EXCPT_TRAP;
358
359 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
360 return EXCPT_ABORT;
361
362 /* Reserved exceptions will result in fault */
363 return EXCPT_FAULT;
364}
365
3fd28fce 366static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 367 unsigned nr, bool has_error, u32 error_code,
368 bool reinject)
3fd28fce
ED		 369{
370 u32 prev_nr;
371 int class1, class2;
372
3842d135
AK		 373 kvm_make_request(KVM_REQ_EVENT, vcpu);
374
3fd28fce
ED		 375 if (!vcpu->arch.exception.pending) {
376 queue:
3ffb2468
NA		 377 if (has_error && !is_protmode(vcpu))
378 has_error = false;
3fd28fce
ED		 379 vcpu->arch.exception.pending = true;
380 vcpu->arch.exception.has_error_code = has_error;
381 vcpu->arch.exception.nr = nr;
382 vcpu->arch.exception.error_code = error_code;
3f0fd292 383 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 384 return;
385 }
386
387 /* to check exception */
388 prev_nr = vcpu->arch.exception.nr;
389 if (prev_nr == DF_VECTOR) {
390 /* triple fault -> shutdown */
a8eeb04a 391 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 392 return;
393 }
394 class1 = exception_class(prev_nr);
395 class2 = exception_class(nr);
396 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
397 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
398 /* generate double fault per SDM Table 5-5 */
399 vcpu->arch.exception.pending = true;
400 vcpu->arch.exception.has_error_code = true;
401 vcpu->arch.exception.nr = DF_VECTOR;
402 vcpu->arch.exception.error_code = 0;
403 } else
404 /* replace previous exception with a new one in a hope
405 that instruction re-execution will regenerate lost
406 exception */
407 goto queue;
408}
409
298101da
AK		 410void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
411{
ce7ddec4 412 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 413}
414EXPORT_SYMBOL_GPL(kvm_queue_exception);
415
ce7ddec4
JR		 416void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
418 kvm_multiple_exception(vcpu, nr, false, 0, true);
419}
420EXPORT_SYMBOL_GPL(kvm_requeue_exception);
421
db8fcefa 422void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 423{
db8fcefa
AP		 424 if (err)
425 kvm_inject_gp(vcpu, 0);
426 else
427 kvm_x86_ops->skip_emulated_instruction(vcpu);
428}
429EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 430
6389ee94 431void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 432{
433 ++vcpu->stat.pf_guest;
6389ee94
AK		 434 vcpu->arch.cr2 = fault->address;
435 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 436}
27d6c865 437EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 438
ef54bcfe 439static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 440{
6389ee94
AK		 441 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
442 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 443 else
6389ee94 444 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 445
446 return fault->nested_page_fault;
d4f8cf66
JR		 447}
448
3419ffc8
SY		 449void kvm_inject_nmi(struct kvm_vcpu *vcpu)
450{
7460fb4a
AK		 451 atomic_inc(&vcpu->arch.nmi_queued);
452 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 453}
454EXPORT_SYMBOL_GPL(kvm_inject_nmi);
455
298101da
AK		 456void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
457{
ce7ddec4 458 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 459}
460EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
461
ce7ddec4
JR		 462void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
464 kvm_multiple_exception(vcpu, nr, true, error_code, true);
465}
466EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
467
0a79b009
AK		 468/*
469 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
470 * a #GP and return false.
471 */
472bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 473{
0a79b009
AK		 474 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
475 return true;
476 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
477 return false;
298101da 478}
0a79b009 479EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 480
16f8a6f9
NA		 481bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
482{
483 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
484 return true;
485
486 kvm_queue_exception(vcpu, UD_VECTOR);
487 return false;
488}
489EXPORT_SYMBOL_GPL(kvm_require_dr);
490
ec92fe44
JR		 491/*
492 * This function will be used to read from the physical memory of the currently
54bf36aa 493 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 494 * can read from guest physical or from the guest's guest physical memory.
495 */
496int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
497 gfn_t ngfn, void *data, int offset, int len,
498 u32 access)
499{
54987b7a 500 struct x86_exception exception;
ec92fe44
JR		 501 gfn_t real_gfn;
502 gpa_t ngpa;
503
504 ngpa = gfn_to_gpa(ngfn);
54987b7a 505 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 506 if (real_gfn == UNMAPPED_GVA)
507 return -EFAULT;
508
509 real_gfn = gpa_to_gfn(real_gfn);
510
54bf36aa 511 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 512}
513EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
514
69b0049a 515static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 516 void *data, int offset, int len, u32 access)
517{
518 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
519 data, offset, len, access);
520}
521
a03490ed
CO		 522/*
523 * Load the pae pdptrs. Return true is they are all valid.
524 */
ff03a073 525int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 526{
527 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
528 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
529 int i;
530 int ret;
ff03a073 531 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 532
ff03a073
JR		 533 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
534 offset * sizeof(u64), sizeof(pdpte),
535 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 536 if (ret < 0) {
537 ret = 0;
538 goto out;
539 }
540 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 541 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 542 (pdpte[i] &
543 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 544 ret = 0;
545 goto out;
546 }
547 }
548 ret = 1;
549
ff03a073 550 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_avail);
553 __set_bit(VCPU_EXREG_PDPTR,
554 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 555out:
a03490ed
CO		 556
557 return ret;
558}
cc4b6871 559EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 560
d835dfec
AK		 561static bool pdptrs_changed(struct kvm_vcpu *vcpu)
562{
ff03a073 563 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 564 bool changed = true;
3d06b8bf
JR		 565 int offset;
566 gfn_t gfn;
d835dfec
AK		 567 int r;
568
569 if (is_long_mode(vcpu) || !is_pae(vcpu))
570 return false;
571
6de4f3ad
AK		 572 if (!test_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail))
574 return true;
575
9f8fe504
AK		 576 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
577 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 578 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
579 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 580 if (r < 0)
581 goto out;
ff03a073 582 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 583out:
d835dfec
AK		 584
585 return changed;
586}
587
49a9b07e 588int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 589{
aad82703 590 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 591 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 592
f9a48e6a
AK		 593 cr0 |= X86_CR0_ET;
594
ab344828 595#ifdef CONFIG_X86_64
0f12244f
GN		 596 if (cr0 & 0xffffffff00000000UL)
597 return 1;
ab344828
GN		 598#endif
599
600 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 601
0f12244f
GN		 602 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
603 return 1;
a03490ed 604
0f12244f
GN		 605 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
606 return 1;
a03490ed
CO		 607
608 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
609#ifdef CONFIG_X86_64
f6801dff 610 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 611 int cs_db, cs_l;
612
0f12244f
GN		 613 if (!is_pae(vcpu))
614 return 1;
a03490ed 615 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 616 if (cs_l)
617 return 1;
a03490ed
CO		 618 } else
619#endif
ff03a073 620 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 621 kvm_read_cr3(vcpu)))
0f12244f 622 return 1;
a03490ed
CO		 623 }
624
ad756a16
MJ		 625 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
626 return 1;
627
a03490ed 628 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 629
d170c419 630 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 631 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 632 kvm_async_pf_hash_reset(vcpu);
633 }
e5f3f027 634
aad82703
SY		 635 if ((cr0 ^ old_cr0) & update_bits)
636 kvm_mmu_reset_context(vcpu);
b18d5431 637
879ae188
LE		 638 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
639 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
640 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 641 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
642
0f12244f
GN		 643 return 0;
644}
2d3ad1f4 645EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 646
2d3ad1f4 647void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 648{
49a9b07e 649 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 652
42bdf991
MT		 653static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
654{
655 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
656 !vcpu->guest_xcr0_loaded) {
657 /* kvm_set_xcr() also depends on this */
658 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
659 vcpu->guest_xcr0_loaded = 1;
660 }
661}
662
663static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
664{
665 if (vcpu->guest_xcr0_loaded) {
666 if (vcpu->arch.xcr0 != host_xcr0)
667 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
668 vcpu->guest_xcr0_loaded = 0;
669 }
670}
671
69b0049a 672static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 673{
56c103ec
LJ		 674 u64 xcr0 = xcr;
675 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 676 u64 valid_bits;
2acf923e
DC		 677
678 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
679 if (index != XCR_XFEATURE_ENABLED_MASK)
680 return 1;
d91cab78 681 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 682 return 1;
d91cab78 683 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 684 return 1;
46c34cb0
PB		 685
686 /*
687 * Do not allow the guest to set bits that we do not support
688 * saving. However, xcr0 bit 0 is always set, even if the
689 * emulated CPU does not support XSAVE (see fx_init).
690 */
d91cab78 691 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 692 if (xcr0 & ~valid_bits)
2acf923e 693 return 1;
46c34cb0 694
d91cab78
DH		 695 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
696 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 697 return 1;
698
d91cab78
DH		 699 if (xcr0 & XFEATURE_MASK_AVX512) {
700 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 701 return 1;
d91cab78 702 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 703 return 1;
704 }
2acf923e 705 vcpu->arch.xcr0 = xcr0;
56c103ec 706
d91cab78 707 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 708 kvm_update_cpuid(vcpu);
2acf923e
DC		 709 return 0;
710}
711
712int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
713{
764bcbc5
Z		 714 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
715 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 716 kvm_inject_gp(vcpu, 0);
717 return 1;
718 }
719 return 0;
720}
721EXPORT_SYMBOL_GPL(kvm_set_xcr);
722
a83b29c6 723int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 724{
fc78f519 725 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 726 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 727 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 728
0f12244f
GN		 729 if (cr4 & CR4_RESERVED_BITS)
730 return 1;
a03490ed 731
2acf923e
DC		 732 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
733 return 1;
734
c68b734f
YW		 735 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
736 return 1;
737
97ec8c06
FW		 738 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
739 return 1;
740
afcbf13f 741 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 742 return 1;
743
b9baba86
HH		 744 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
745 return 1;
746
a03490ed 747 if (is_long_mode(vcpu)) {
0f12244f
GN		 748 if (!(cr4 & X86_CR4_PAE))
749 return 1;
a2edf57f
AK		 750 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
751 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 752 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
753 kvm_read_cr3(vcpu)))
0f12244f
GN		 754 return 1;
755
ad756a16
MJ		 756 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
757 if (!guest_cpuid_has_pcid(vcpu))
758 return 1;
759
760 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
761 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
762 return 1;
763 }
764
5e1746d6 765 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 766 return 1;
a03490ed 767
ad756a16
MJ		 768 if (((cr4 ^ old_cr4) & pdptr_bits) ||
769 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 770 kvm_mmu_reset_context(vcpu);
0f12244f 771
b9baba86 772 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 773 kvm_update_cpuid(vcpu);
2acf923e 774
0f12244f
GN		 775 return 0;
776}
2d3ad1f4 777EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 778
2390218b 779int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 780{
ac146235 781#ifdef CONFIG_X86_64
9d88fca7 782 cr3 &= ~CR3_PCID_INVD;
ac146235 783#endif
9d88fca7 784
9f8fe504 785 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 786 kvm_mmu_sync_roots(vcpu);
77c3913b 787 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 788 return 0;
d835dfec
AK		 789 }
790
a03490ed 791 if (is_long_mode(vcpu)) {
d9f89b88
JK		 792 if (cr3 & CR3_L_MODE_RESERVED_BITS)
793 return 1;
794 } else if (is_pae(vcpu) && is_paging(vcpu) &&
795 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 796 return 1;
a03490ed 797
0f12244f 798 vcpu->arch.cr3 = cr3;
aff48baa 799 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 800 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 801 return 0;
802}
2d3ad1f4 803EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 804
eea1cff9 805int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 806{
0f12244f
GN		 807 if (cr8 & CR8_RESERVED_BITS)
808 return 1;
35754c98 809 if (lapic_in_kernel(vcpu))
a03490ed
CO		 810 kvm_lapic_set_tpr(vcpu, cr8);
811 else
ad312c7c 812 vcpu->arch.cr8 = cr8;
0f12244f
GN		 813 return 0;
814}
2d3ad1f4 815EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 816
2d3ad1f4 817unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 818{
35754c98 819 if (lapic_in_kernel(vcpu))
a03490ed
CO		 820 return kvm_lapic_get_cr8(vcpu);
821 else
ad312c7c 822 return vcpu->arch.cr8;
a03490ed 823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 825
ae561ede
NA		 826static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
827{
828 int i;
829
830 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
831 for (i = 0; i < KVM_NR_DB_REGS; i++)
832 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
833 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
834 }
835}
836
73aaf249
JK		 837static void kvm_update_dr6(struct kvm_vcpu *vcpu)
838{
839 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
840 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
841}
842
c8639010
JK		 843static void kvm_update_dr7(struct kvm_vcpu *vcpu)
844{
845 unsigned long dr7;
846
847 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
848 dr7 = vcpu->arch.guest_debug_dr7;
849 else
850 dr7 = vcpu->arch.dr7;
851 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 852 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
853 if (dr7 & DR7_BP_EN_MASK)
854 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 855}
856
6f43ed01
NA		 857static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
858{
859 u64 fixed = DR6_FIXED_1;
860
861 if (!guest_cpuid_has_rtm(vcpu))
862 fixed |= DR6_RTM;
863 return fixed;
864}
865
338dbc97 866static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 867{
868 switch (dr) {
869 case 0 ... 3:
870 vcpu->arch.db[dr] = val;
871 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
872 vcpu->arch.eff_db[dr] = val;
873 break;
874 case 4:
020df079
GN		 875 /* fall through */
876 case 6:
338dbc97
GN		 877 if (val & 0xffffffff00000000ULL)
878 return -1; /* #GP */
6f43ed01 879 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 880 kvm_update_dr6(vcpu);
020df079
GN		 881 break;
882 case 5:
020df079
GN		 883 /* fall through */
884 default: /* 7 */
338dbc97
GN		 885 if (val & 0xffffffff00000000ULL)
886 return -1; /* #GP */
020df079 887 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 888 kvm_update_dr7(vcpu);
020df079
GN		 889 break;
890 }
891
892 return 0;
893}
338dbc97
GN		 894
895int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
896{
16f8a6f9 897 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 898 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 899 return 1;
900 }
901 return 0;
338dbc97 902}
020df079
GN		 903EXPORT_SYMBOL_GPL(kvm_set_dr);
904
16f8a6f9 905int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 906{
907 switch (dr) {
908 case 0 ... 3:
909 *val = vcpu->arch.db[dr];
910 break;
911 case 4:
020df079
GN		 912 /* fall through */
913 case 6:
73aaf249
JK		 914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
915 *val = vcpu->arch.dr6;
916 else
917 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 918 break;
919 case 5:
020df079
GN		 920 /* fall through */
921 default: /* 7 */
922 *val = vcpu->arch.dr7;
923 break;
924 }
338dbc97
GN		 925 return 0;
926}
020df079
GN		 927EXPORT_SYMBOL_GPL(kvm_get_dr);
928
022cd0e8
AK		 929bool kvm_rdpmc(struct kvm_vcpu *vcpu)
930{
931 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
932 u64 data;
933 int err;
934
c6702c9d 935 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 936 if (err)
937 return err;
938 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
939 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
940 return err;
941}
942EXPORT_SYMBOL_GPL(kvm_rdpmc);
943
043405e1
CO		 944/*
945 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
946 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
947 *
948 * This list is modified at module load time to reflect the
e3267cbb 949 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 950 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
951 * may depend on host virtualization features rather than host cpu features.
043405e1 952 */
e3267cbb 953
043405e1
CO		 954static u32 msrs_to_save[] = {
955 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 956 MSR_STAR,
043405e1
CO		 957#ifdef CONFIG_X86_64
958 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
959#endif
b3897a49 960 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 961 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 962};
963
964static unsigned num_msrs_to_save;
965
62ef68bb
PB		 966static u32 emulated_msrs[] = {
967 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
968 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
969 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
970 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 971 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
972 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 973 HV_X64_MSR_RESET,
11c4b1ca 974 HV_X64_MSR_VP_INDEX,
9eec50b8 975 HV_X64_MSR_VP_RUNTIME,
5c919412 976 HV_X64_MSR_SCONTROL,
1f4b34f8 977 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 978 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
979 MSR_KVM_PV_EOI_EN,
980
ba904635 981 MSR_IA32_TSC_ADJUST,
a3e06bbe 982 MSR_IA32_TSCDEADLINE,
043405e1 983 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 984 MSR_IA32_MCG_STATUS,
985 MSR_IA32_MCG_CTL,
64d60670 986 MSR_IA32_SMBASE,
043405e1
CO		 987};
988
62ef68bb
PB		 989static unsigned num_emulated_msrs;
990
384bb783 991bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 992{
b69e8cae 993 if (efer & efer_reserved_bits)
384bb783 994 return false;
15c4a640 995
1b2fd70c
AG		 996 if (efer & EFER_FFXSR) {
997 struct kvm_cpuid_entry2 *feat;
998
999 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1000 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1001 return false;
1b2fd70c
AG		 1002 }
1003
d8017474
AG		 1004 if (efer & EFER_SVME) {
1005 struct kvm_cpuid_entry2 *feat;
1006
1007 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1008 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1009 return false;
d8017474
AG		 1010 }
1011
384bb783
JK		 1012 return true;
1013}
1014EXPORT_SYMBOL_GPL(kvm_valid_efer);
1015
1016static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1017{
1018 u64 old_efer = vcpu->arch.efer;
1019
1020 if (!kvm_valid_efer(vcpu, efer))
1021 return 1;
1022
1023 if (is_paging(vcpu)
1024 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1025 return 1;
1026
15c4a640 1027 efer &= ~EFER_LMA;
f6801dff 1028 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1029
a3d204e2
SY		 1030 kvm_x86_ops->set_efer(vcpu, efer);
1031
aad82703
SY		 1032 /* Update reserved bits */
1033 if ((efer ^ old_efer) & EFER_NX)
1034 kvm_mmu_reset_context(vcpu);
1035
b69e8cae 1036 return 0;
15c4a640
CO		 1037}
1038
f2b4b7dd
JR		 1039void kvm_enable_efer_bits(u64 mask)
1040{
1041 efer_reserved_bits &= ~mask;
1042}
1043EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1044
15c4a640
CO		 1045/*
1046 * Writes msr value into into the appropriate "register".
1047 * Returns 0 on success, non-0 otherwise.
1048 * Assumes vcpu_load() was already called.
1049 */
8fe8ab46 1050int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1051{
854e8bb1
NA		 1052 switch (msr->index) {
1053 case MSR_FS_BASE:
1054 case MSR_GS_BASE:
1055 case MSR_KERNEL_GS_BASE:
1056 case MSR_CSTAR:
1057 case MSR_LSTAR:
1058 if (is_noncanonical_address(msr->data))
1059 return 1;
1060 break;
1061 case MSR_IA32_SYSENTER_EIP:
1062 case MSR_IA32_SYSENTER_ESP:
1063 /*
1064 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1065 * non-canonical address is written on Intel but not on
1066 * AMD (which ignores the top 32-bits, because it does
1067 * not implement 64-bit SYSENTER).
1068 *
1069 * 64-bit code should hence be able to write a non-canonical
1070 * value on AMD. Making the address canonical ensures that
1071 * vmentry does not fail on Intel after writing a non-canonical
1072 * value, and that something deterministic happens if the guest
1073 * invokes 64-bit SYSENTER.
1074 */
1075 msr->data = get_canonical(msr->data);
1076 }
8fe8ab46 1077 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1078}
854e8bb1 1079EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1080
313a3dc7
CO		 1081/*
1082 * Adapt set_msr() to msr_io()'s calling convention
1083 */
609e36d3
PB		 1084static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085{
1086 struct msr_data msr;
1087 int r;
1088
1089 msr.index = index;
1090 msr.host_initiated = true;
1091 r = kvm_get_msr(vcpu, &msr);
1092 if (r)
1093 return r;
1094
1095 *data = msr.data;
1096 return 0;
1097}
1098
313a3dc7
CO		 1099static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1100{
8fe8ab46
WA		 1101 struct msr_data msr;
1102
1103 msr.data = *data;
1104 msr.index = index;
1105 msr.host_initiated = true;
1106 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1107}
1108
16e8d74d
MT		 1109#ifdef CONFIG_X86_64
1110struct pvclock_gtod_data {
1111 seqcount_t seq;
1112
1113 struct { /* extract of a clocksource struct */
1114 int vclock_mode;
1115 cycle_t cycle_last;
1116 cycle_t mask;
1117 u32 mult;
1118 u32 shift;
1119 } clock;
1120
cbcf2dd3
TG		 1121 u64 boot_ns;
1122 u64 nsec_base;
16e8d74d
MT		 1123};
1124
1125static struct pvclock_gtod_data pvclock_gtod_data;
1126
1127static void update_pvclock_gtod(struct timekeeper *tk)
1128{
1129 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1130 u64 boot_ns;
1131
876e7881 1132 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1133
1134 write_seqcount_begin(&vdata->seq);
1135
1136 /* copy pvclock gtod data */
876e7881
PZ		 1137 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1138 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1139 vdata->clock.mask = tk->tkr_mono.mask;
1140 vdata->clock.mult = tk->tkr_mono.mult;
1141 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1142
cbcf2dd3 1143 vdata->boot_ns = boot_ns;
876e7881 1144 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1145
1146 write_seqcount_end(&vdata->seq);
1147}
1148#endif
1149
bab5bb39
NK		 1150void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1151{
1152 /*
1153 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1154 * vcpu_enter_guest. This function is only called from
1155 * the physical CPU that is running vcpu.
1156 */
1157 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1158}
16e8d74d 1159
18068523
GOC		 1160static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1161{
9ed3c444
AK		 1162 int version;
1163 int r;
50d0a0f9 1164 struct pvclock_wall_clock wc;
923de3cf 1165 struct timespec boot;
18068523
GOC		 1166
1167 if (!wall_clock)
1168 return;
1169
9ed3c444
AK		 1170 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1171 if (r)
1172 return;
1173
1174 if (version & 1)
1175 ++version; /* first time write, random junk */
1176
1177 ++version;
18068523 1178
1dab1345
NK		 1179 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1180 return;
18068523 1181
50d0a0f9
GH		 1182 /*
1183 * The guest calculates current wall clock time by adding
34c238a1 1184 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1185 * wall clock specified here. guest system time equals host
1186 * system time for us, thus we must fill in host boot time here.
1187 */
923de3cf 1188 getboottime(&boot);
50d0a0f9 1189
4b648665
BR		 1190 if (kvm->arch.kvmclock_offset) {
1191 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1192 boot = timespec_sub(boot, ts);
1193 }
50d0a0f9
GH		 1194 wc.sec = boot.tv_sec;
1195 wc.nsec = boot.tv_nsec;
1196 wc.version = version;
18068523
GOC		 1197
1198 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1199
1200 version++;
1201 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1202}
1203
50d0a0f9
GH		 1204static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1205{
b51012de
PB		 1206 do_shl32_div32(dividend, divisor);
1207 return dividend;
50d0a0f9
GH		 1208}
1209
3ae13faa 1210static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1211 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1212{
5f4e3f88 1213 uint64_t scaled64;
50d0a0f9
GH		 1214 int32_t shift = 0;
1215 uint64_t tps64;
1216 uint32_t tps32;
1217
3ae13faa
PB		 1218 tps64 = base_hz;
1219 scaled64 = scaled_hz;
50933623 1220 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1221 tps64 >>= 1;
1222 shift--;
1223 }
1224
1225 tps32 = (uint32_t)tps64;
50933623
JK		 1226 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1227 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1228 scaled64 >>= 1;
1229 else
1230 tps32 <<= 1;
50d0a0f9
GH		 1231 shift++;
1232 }
1233
5f4e3f88
ZA		 1234 *pshift = shift;
1235 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1236
3ae13faa
PB		 1237 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1238 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1239}
1240
d828199e 1241#ifdef CONFIG_X86_64
16e8d74d 1242static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1243#endif
16e8d74d 1244
c8076604 1245static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1246static unsigned long max_tsc_khz;
c8076604 1247
cc578287 1248static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1249{
cc578287
ZA		 1250 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1251 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1252}
1253
cc578287 1254static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1255{
cc578287
ZA		 1256 u64 v = (u64)khz * (1000000 + ppm);
1257 do_div(v, 1000000);
1258 return v;
1e993611
JR		 1259}
1260
381d585c
HZ		 1261static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1262{
1263 u64 ratio;
1264
1265 /* Guest TSC same frequency as host TSC? */
1266 if (!scale) {
1267 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1268 return 0;
1269 }
1270
1271 /* TSC scaling supported? */
1272 if (!kvm_has_tsc_control) {
1273 if (user_tsc_khz > tsc_khz) {
1274 vcpu->arch.tsc_catchup = 1;
1275 vcpu->arch.tsc_always_catchup = 1;
1276 return 0;
1277 } else {
1278 WARN(1, "user requested TSC rate below hardware speed\n");
1279 return -1;
1280 }
1281 }
1282
1283 /* TSC scaling required - calculate ratio */
1284 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1285 user_tsc_khz, tsc_khz);
1286
1287 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1288 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1289 user_tsc_khz);
1290 return -1;
1291 }
1292
1293 vcpu->arch.tsc_scaling_ratio = ratio;
1294 return 0;
1295}
1296
4941b8cb 1297static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1298{
cc578287
ZA		 1299 u32 thresh_lo, thresh_hi;
1300 int use_scaling = 0;
217fc9cf 1301
03ba32ca 1302 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1303 if (user_tsc_khz == 0) {
ad721883
HZ		 1304 /* set tsc_scaling_ratio to a safe value */
1305 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1306 return -1;
ad721883 1307 }
03ba32ca 1308
c285545f 1309 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1310 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1311 &vcpu->arch.virtual_tsc_shift,
1312 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1313 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1314
1315 /*
1316 * Compute the variation in TSC rate which is acceptable
1317 * within the range of tolerance and decide if the
1318 * rate being applied is within that bounds of the hardware
1319 * rate. If so, no scaling or compensation need be done.
1320 */
1321 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1322 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1323 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1324 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1325 use_scaling = 1;
1326 }
4941b8cb 1327 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1328}
1329
1330static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1331{
e26101b1 1332 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1333 vcpu->arch.virtual_tsc_mult,
1334 vcpu->arch.virtual_tsc_shift);
e26101b1 1335 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1336 return tsc;
1337}
1338
69b0049a 1339static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1340{
1341#ifdef CONFIG_X86_64
1342 bool vcpus_matched;
b48aa97e
MT		 1343 struct kvm_arch *ka = &vcpu->kvm->arch;
1344 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1345
1346 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1347 atomic_read(&vcpu->kvm->online_vcpus));
1348
7f187922
MT		 1349 /*
1350 * Once the masterclock is enabled, always perform request in
1351 * order to update it.
1352 *
1353 * In order to enable masterclock, the host clocksource must be TSC
1354 * and the vcpus need to have matched TSCs. When that happens,
1355 * perform request to enable masterclock.
1356 */
1357 if (ka->use_master_clock ||
1358 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1359 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1360
1361 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1362 atomic_read(&vcpu->kvm->online_vcpus),
1363 ka->use_master_clock, gtod->clock.vclock_mode);
1364#endif
1365}
1366
ba904635
WA		 1367static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1368{
1369 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1370 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1371}
1372
35181e86
HZ		 1373/*
1374 * Multiply tsc by a fixed point number represented by ratio.
1375 *
1376 * The most significant 64-N bits (mult) of ratio represent the
1377 * integral part of the fixed point number; the remaining N bits
1378 * (frac) represent the fractional part, ie. ratio represents a fixed
1379 * point number (mult + frac * 2^(-N)).
1380 *
1381 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1382 */
1383static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1384{
1385 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1386}
1387
1388u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1389{
1390 u64 _tsc = tsc;
1391 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1392
1393 if (ratio != kvm_default_tsc_scaling_ratio)
1394 _tsc = __scale_tsc(ratio, tsc);
1395
1396 return _tsc;
1397}
1398EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1399
07c1419a
HZ		 1400static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1401{
1402 u64 tsc;
1403
1404 tsc = kvm_scale_tsc(vcpu, rdtsc());
1405
1406 return target_tsc - tsc;
1407}
1408
4ba76538
HZ		 1409u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1410{
1411 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1412}
1413EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1414
8fe8ab46 1415void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1416{
1417 struct kvm *kvm = vcpu->kvm;
f38e098f 1418 u64 offset, ns, elapsed;
99e3e30a 1419 unsigned long flags;
02626b6a 1420 s64 usdiff;
b48aa97e 1421 bool matched;
0d3da0d2 1422 bool already_matched;
8fe8ab46 1423 u64 data = msr->data;
99e3e30a 1424
038f8c11 1425 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1426 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1427 ns = get_kernel_ns();
f38e098f 1428 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1429
03ba32ca 1430 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1431 int faulted = 0;
1432
03ba32ca
MT		 1433 /* n.b - signed multiplication and division required */
1434 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1435#ifdef CONFIG_X86_64
03ba32ca 1436 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1437#else
03ba32ca 1438 /* do_div() only does unsigned */
8915aa27
MT		 1439 asm("1: idivl %[divisor]\n"
1440 "2: xor %%edx, %%edx\n"
1441 " movl $0, %[faulted]\n"
1442 "3:\n"
1443 ".section .fixup,\"ax\"\n"
1444 "4: movl $1, %[faulted]\n"
1445 " jmp 3b\n"
1446 ".previous\n"
1447
1448 _ASM_EXTABLE(1b, 4b)
1449
1450 : "=A"(usdiff), [faulted] "=r" (faulted)
1451 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1452
5d3cb0f6 1453#endif
03ba32ca
MT		 1454 do_div(elapsed, 1000);
1455 usdiff -= elapsed;
1456 if (usdiff < 0)
1457 usdiff = -usdiff;
8915aa27
MT		 1458
1459 /* idivl overflow => difference is larger than USEC_PER_SEC */
1460 if (faulted)
1461 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1462 } else
1463 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1464
1465 /*
5d3cb0f6
ZA		 1466 * Special case: TSC write with a small delta (1 second) of virtual
1467 * cycle time against real time is interpreted as an attempt to
1468 * synchronize the CPU.
1469 *
1470 * For a reliable TSC, we can match TSC offsets, and for an unstable
1471 * TSC, we add elapsed time in this computation. We could let the
1472 * compensation code attempt to catch up if we fall behind, but
1473 * it's better to try to match offsets from the beginning.
1474 */
02626b6a 1475 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1476 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1477 if (!check_tsc_unstable()) {
e26101b1 1478 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1479 pr_debug("kvm: matched tsc offset for %llu\n", data);
1480 } else {
857e4099 1481 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1482 data += delta;
07c1419a 1483 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1484 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1485 }
b48aa97e 1486 matched = true;
0d3da0d2 1487 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1488 } else {
1489 /*
1490 * We split periods of matched TSC writes into generations.
1491 * For each generation, we track the original measured
1492 * nanosecond time, offset, and write, so if TSCs are in
1493 * sync, we can match exact offset, and if not, we can match
4a969980 1494 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1495 *
1496 * These values are tracked in kvm->arch.cur_xxx variables.
1497 */
1498 kvm->arch.cur_tsc_generation++;
1499 kvm->arch.cur_tsc_nsec = ns;
1500 kvm->arch.cur_tsc_write = data;
1501 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1502 matched = false;
0d3da0d2 1503 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1504 kvm->arch.cur_tsc_generation, data);
f38e098f 1505 }
e26101b1
ZA		 1506
1507 /*
1508 * We also track th most recent recorded KHZ, write and time to
1509 * allow the matching interval to be extended at each write.
1510 */
f38e098f
ZA		 1511 kvm->arch.last_tsc_nsec = ns;
1512 kvm->arch.last_tsc_write = data;
5d3cb0f6 1513 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1514
b183aa58 1515 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1516
1517 /* Keep track of which generation this VCPU has synchronized to */
1518 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1519 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1520 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1521
ba904635
WA		 1522 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1523 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1524 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1525 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1526
1527 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1528 if (!matched) {
b48aa97e 1529 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1530 } else if (!already_matched) {
1531 kvm->arch.nr_vcpus_matched_tsc++;
1532 }
b48aa97e
MT		 1533
1534 kvm_track_tsc_matching(vcpu);
1535 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1536}
e26101b1 1537
99e3e30a
ZA		 1538EXPORT_SYMBOL_GPL(kvm_write_tsc);
1539
58ea6767
HZ		 1540static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1541 s64 adjustment)
1542{
1543 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1544}
1545
1546static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1547{
1548 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1549 WARN_ON(adjustment < 0);
1550 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1551 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1552}
1553
d828199e
MT		 1554#ifdef CONFIG_X86_64
1555
1556static cycle_t read_tsc(void)
1557{
03b9730b
AL		 1558 cycle_t ret = (cycle_t)rdtsc_ordered();
1559 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1560
1561 if (likely(ret >= last))
1562 return ret;
1563
1564 /*
1565 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1566 * predictable (it's just a function of time and the likely is
d828199e
MT		 1567 * very likely) and there's a data dependence, so force GCC
1568 * to generate a branch instead. I don't barrier() because
1569 * we don't actually need a barrier, and if this function
1570 * ever gets inlined it will generate worse code.
1571 */
1572 asm volatile ("");
1573 return last;
1574}
1575
1576static inline u64 vgettsc(cycle_t *cycle_now)
1577{
1578 long v;
1579 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1580
1581 *cycle_now = read_tsc();
1582
1583 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1584 return v * gtod->clock.mult;
1585}
1586
cbcf2dd3 1587static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1588{
cbcf2dd3 1589 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1590 unsigned long seq;
d828199e 1591 int mode;
cbcf2dd3 1592 u64 ns;
d828199e 1593
d828199e
MT		 1594 do {
1595 seq = read_seqcount_begin(&gtod->seq);
1596 mode = gtod->clock.vclock_mode;
cbcf2dd3 1597 ns = gtod->nsec_base;
d828199e
MT		 1598 ns += vgettsc(cycle_now);
1599 ns >>= gtod->clock.shift;
cbcf2dd3 1600 ns += gtod->boot_ns;
d828199e 1601 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1602 *t = ns;
d828199e
MT		 1603
1604 return mode;
1605}
1606
1607/* returns true if host is using tsc clocksource */
1608static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1609{
d828199e
MT		 1610 /* checked again under seqlock below */
1611 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1612 return false;
1613
cbcf2dd3 1614 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1615}
1616#endif
1617
1618/*
1619 *
b48aa97e
MT		 1620 * Assuming a stable TSC across physical CPUS, and a stable TSC
1621 * across virtual CPUs, the following condition is possible.
1622 * Each numbered line represents an event visible to both
d828199e
MT		 1623 * CPUs at the next numbered event.
1624 *
1625 * "timespecX" represents host monotonic time. "tscX" represents
1626 * RDTSC value.
1627 *
1628 * VCPU0 on CPU0 | VCPU1 on CPU1
1629 *
1630 * 1. read timespec0,tsc0
1631 * 2. | timespec1 = timespec0 + N
1632 * | tsc1 = tsc0 + M
1633 * 3. transition to guest | transition to guest
1634 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1635 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1636 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1637 *
1638 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1639 *
1640 * - ret0 < ret1
1641 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1642 * ...
1643 * - 0 < N - M => M < N
1644 *
1645 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1646 * always the case (the difference between two distinct xtime instances
1647 * might be smaller then the difference between corresponding TSC reads,
1648 * when updating guest vcpus pvclock areas).
1649 *
1650 * To avoid that problem, do not allow visibility of distinct
1651 * system_timestamp/tsc_timestamp values simultaneously: use a master
1652 * copy of host monotonic time values. Update that master copy
1653 * in lockstep.
1654 *
b48aa97e 1655 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1656 *
1657 */
1658
1659static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1660{
1661#ifdef CONFIG_X86_64
1662 struct kvm_arch *ka = &kvm->arch;
1663 int vclock_mode;
b48aa97e
MT		 1664 bool host_tsc_clocksource, vcpus_matched;
1665
1666 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1667 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1668
1669 /*
1670 * If the host uses TSC clock, then passthrough TSC as stable
1671 * to the guest.
1672 */
b48aa97e 1673 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1674 &ka->master_kernel_ns,
1675 &ka->master_cycle_now);
1676
16a96021 1677 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1678 && !backwards_tsc_observed
1679 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1680
d828199e
MT		 1681 if (ka->use_master_clock)
1682 atomic_set(&kvm_guest_has_master_clock, 1);
1683
1684 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1685 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1686 vcpus_matched);
d828199e
MT		 1687#endif
1688}
1689
2860c4b1
PB		 1690void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1691{
1692 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1693}
1694
2e762ff7
MT		 1695static void kvm_gen_update_masterclock(struct kvm *kvm)
1696{
1697#ifdef CONFIG_X86_64
1698 int i;
1699 struct kvm_vcpu *vcpu;
1700 struct kvm_arch *ka = &kvm->arch;
1701
1702 spin_lock(&ka->pvclock_gtod_sync_lock);
1703 kvm_make_mclock_inprogress_request(kvm);
1704 /* no guest entries from this point */
1705 pvclock_update_vm_gtod_copy(kvm);
1706
1707 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1708 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1709
1710 /* guest entries allowed */
1711 kvm_for_each_vcpu(i, vcpu, kvm)
1712 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1713
1714 spin_unlock(&ka->pvclock_gtod_sync_lock);
1715#endif
1716}
1717
34c238a1 1718static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1719{
78db6a50 1720 unsigned long flags, tgt_tsc_khz;
18068523 1721 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1722 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1723 s64 kernel_ns;
d828199e 1724 u64 tsc_timestamp, host_tsc;
0b79459b 1725 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1726 u8 pvclock_flags;
d828199e
MT		 1727 bool use_master_clock;
1728
1729 kernel_ns = 0;
1730 host_tsc = 0;
18068523 1731
d828199e
MT		 1732 /*
1733 * If the host uses TSC clock, then passthrough TSC as stable
1734 * to the guest.
1735 */
1736 spin_lock(&ka->pvclock_gtod_sync_lock);
1737 use_master_clock = ka->use_master_clock;
1738 if (use_master_clock) {
1739 host_tsc = ka->master_cycle_now;
1740 kernel_ns = ka->master_kernel_ns;
1741 }
1742 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1743
1744 /* Keep irq disabled to prevent changes to the clock */
1745 local_irq_save(flags);
78db6a50
PB		 1746 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1747 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1748 local_irq_restore(flags);
1749 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1750 return 1;
1751 }
d828199e 1752 if (!use_master_clock) {
4ea1636b 1753 host_tsc = rdtsc();
d828199e
MT		 1754 kernel_ns = get_kernel_ns();
1755 }
1756
4ba76538 1757 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1758
c285545f
ZA		 1759 /*
1760 * We may have to catch up the TSC to match elapsed wall clock
1761 * time for two reasons, even if kvmclock is used.
1762 * 1) CPU could have been running below the maximum TSC rate
1763 * 2) Broken TSC compensation resets the base at each VCPU
1764 * entry to avoid unknown leaps of TSC even when running
1765 * again on the same CPU. This may cause apparent elapsed
1766 * time to disappear, and the guest to stand still or run
1767 * very slowly.
1768 */
1769 if (vcpu->tsc_catchup) {
1770 u64 tsc = compute_guest_tsc(v, kernel_ns);
1771 if (tsc > tsc_timestamp) {
f1e2b260 1772 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1773 tsc_timestamp = tsc;
1774 }
50d0a0f9
GH		 1775 }
1776
18068523
GOC		 1777 local_irq_restore(flags);
1778
0b79459b 1779 if (!vcpu->pv_time_enabled)
c285545f 1780 return 0;
18068523 1781
78db6a50
PB		 1782 if (kvm_has_tsc_control)
1783 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1784
1785 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1786 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1787 &vcpu->hv_clock.tsc_shift,
1788 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1789 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1790 }
1791
1792 /* With all the info we got, fill in the values */
1d5f066e 1793 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1794 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1795 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1796
09a0c3f1
OH		 1797 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1798 &guest_hv_clock, sizeof(guest_hv_clock))))
1799 return 0;
1800
5dca0d91
RK		 1801 /* This VCPU is paused, but it's legal for a guest to read another
1802 * VCPU's kvmclock, so we really have to follow the specification where
1803 * it says that version is odd if data is being modified, and even after
1804 * it is consistent.
1805 *
1806 * Version field updates must be kept separate. This is because
1807 * kvm_write_guest_cached might use a "rep movs" instruction, and
1808 * writes within a string instruction are weakly ordered. So there
1809 * are three writes overall.
1810 *
1811 * As a small optimization, only write the version field in the first
1812 * and third write. The vcpu->pv_time cache is still valid, because the
1813 * version field is the first in the struct.
18068523 1814 */
5dca0d91
RK		 1815 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1816
1817 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1818 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1819 &vcpu->hv_clock,
1820 sizeof(vcpu->hv_clock.version));
1821
1822 smp_wmb();
78c0337a
MT		 1823
1824 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1825 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1826
1827 if (vcpu->pvclock_set_guest_stopped_request) {
1828 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1829 vcpu->pvclock_set_guest_stopped_request = false;
1830 }
1831
d828199e
MT		 1832 /* If the host uses TSC clocksource, then it is stable */
1833 if (use_master_clock)
1834 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1835
78c0337a
MT		 1836 vcpu->hv_clock.flags = pvclock_flags;
1837
ce1a5e60
DM		 1838 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1839
0b79459b
AH		 1840 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 &vcpu->hv_clock,
1842 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1843
1844 smp_wmb();
1845
1846 vcpu->hv_clock.version++;
1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
8cfdc000 1850 return 0;
c8076604
GH		 1851}
1852
0061d53d
MT		 1853/*
1854 * kvmclock updates which are isolated to a given vcpu, such as
1855 * vcpu->cpu migration, should not allow system_timestamp from
1856 * the rest of the vcpus to remain static. Otherwise ntp frequency
1857 * correction applies to one vcpu's system_timestamp but not
1858 * the others.
1859 *
1860 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1861 * We need to rate-limit these requests though, as they can
1862 * considerably slow guests that have a large number of vcpus.
1863 * The time for a remote vcpu to update its kvmclock is bound
1864 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1865 */
1866
7e44e449
AJ		 1867#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1868
1869static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1870{
1871 int i;
7e44e449
AJ		 1872 struct delayed_work *dwork = to_delayed_work(work);
1873 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1874 kvmclock_update_work);
1875 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1876 struct kvm_vcpu *vcpu;
1877
1878 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1879 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1880 kvm_vcpu_kick(vcpu);
1881 }
1882}
1883
7e44e449
AJ		 1884static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1885{
1886 struct kvm *kvm = v->kvm;
1887
105b21bb 1888 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1889 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1890 KVMCLOCK_UPDATE_DELAY);
1891}
1892
332967a3
AJ		 1893#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1894
1895static void kvmclock_sync_fn(struct work_struct *work)
1896{
1897 struct delayed_work *dwork = to_delayed_work(work);
1898 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1899 kvmclock_sync_work);
1900 struct kvm *kvm = container_of(ka, struct kvm, arch);
1901
630994b3
MT		 1902 if (!kvmclock_periodic_sync)
1903 return;
1904
332967a3
AJ		 1905 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1906 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1907 KVMCLOCK_SYNC_PERIOD);
1908}
1909
890ca9ae 1910static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1911{
890ca9ae
HY		 1912 u64 mcg_cap = vcpu->arch.mcg_cap;
1913 unsigned bank_num = mcg_cap & 0xff;
1914
15c4a640 1915 switch (msr) {
15c4a640 1916 case MSR_IA32_MCG_STATUS:
890ca9ae 1917 vcpu->arch.mcg_status = data;
15c4a640 1918 break;
c7ac679c 1919 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1920 if (!(mcg_cap & MCG_CTL_P))
1921 return 1;
1922 if (data != 0 && data != ~(u64)0)
1923 return -1;
1924 vcpu->arch.mcg_ctl = data;
1925 break;
1926 default:
1927 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1928 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1929 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1930 /* only 0 or all 1s can be written to IA32_MCi_CTL
1931 * some Linux kernels though clear bit 10 in bank 4 to
1932 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1933 * this to avoid an uncatched #GP in the guest
1934 */
890ca9ae 1935 if ((offset & 0x3) == 0 &&
114be429 1936 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1937 return -1;
1938 vcpu->arch.mce_banks[offset] = data;
1939 break;
1940 }
1941 return 1;
1942 }
1943 return 0;
1944}
1945
ffde22ac
ES		 1946static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1947{
1948 struct kvm *kvm = vcpu->kvm;
1949 int lm = is_long_mode(vcpu);
1950 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1951 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1952 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1953 : kvm->arch.xen_hvm_config.blob_size_32;
1954 u32 page_num = data & ~PAGE_MASK;
1955 u64 page_addr = data & PAGE_MASK;
1956 u8 *page;
1957 int r;
1958
1959 r = -E2BIG;
1960 if (page_num >= blob_size)
1961 goto out;
1962 r = -ENOMEM;
ff5c2c03
SL		 1963 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1964 if (IS_ERR(page)) {
1965 r = PTR_ERR(page);
ffde22ac 1966 goto out;
ff5c2c03 1967 }
54bf36aa 1968 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1969 goto out_free;
1970 r = 0;
1971out_free:
1972 kfree(page);
1973out:
1974 return r;
1975}
1976
344d9588
GN		 1977static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1978{
1979 gpa_t gpa = data & ~0x3f;
1980
4a969980 1981 /* Bits 2:5 are reserved, Should be zero */
6adba527 1982 if (data & 0x3c)
344d9588
GN		 1983 return 1;
1984
1985 vcpu->arch.apf.msr_val = data;
1986
1987 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1988 kvm_clear_async_pf_completion_queue(vcpu);
1989 kvm_async_pf_hash_reset(vcpu);
1990 return 0;
1991 }
1992
8f964525
AH		 1993 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1994 sizeof(u32)))
344d9588
GN		 1995 return 1;
1996
6adba527 1997 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1998 kvm_async_pf_wakeup_all(vcpu);
1999 return 0;
2000}
2001
12f9a48f
GC		 2002static void kvmclock_reset(struct kvm_vcpu *vcpu)
2003{
0b79459b 2004 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2005}
2006
c9aaa895
GC		 2007static void record_steal_time(struct kvm_vcpu *vcpu)
2008{
2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 return;
2011
2012 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2013 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2014 return;
2015
35f3fae1
WL		 2016 if (vcpu->arch.st.steal.version & 1)
2017 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2018
2019 vcpu->arch.st.steal.version += 1;
2020
2021 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2022 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2023
2024 smp_wmb();
2025
c54cdf14
LC		 2026 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2027 vcpu->arch.st.last_steal;
2028 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2029
2030 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2031 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2032
2033 smp_wmb();
2034
2035 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2036
2037 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2038 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2039}
2040
8fe8ab46 2041int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2042{
5753785f 2043 bool pr = false;
8fe8ab46
WA		 2044 u32 msr = msr_info->index;
2045 u64 data = msr_info->data;
5753785f 2046
15c4a640 2047 switch (msr) {
2e32b719
BP		 2048 case MSR_AMD64_NB_CFG:
2049 case MSR_IA32_UCODE_REV:
2050 case MSR_IA32_UCODE_WRITE:
2051 case MSR_VM_HSAVE_PA:
2052 case MSR_AMD64_PATCH_LOADER:
2053 case MSR_AMD64_BU_CFG2:
2054 break;
2055
15c4a640 2056 case MSR_EFER:
b69e8cae 2057 return set_efer(vcpu, data);
8f1589d9
AP		 2058 case MSR_K7_HWCR:
2059 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2060 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2061 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2062 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2063 if (data != 0) {
a737f256
CD		 2064 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2065 data);
8f1589d9
AP		 2066 return 1;
2067 }
15c4a640 2068 break;
f7c6d140
AP		 2069 case MSR_FAM10H_MMIO_CONF_BASE:
2070 if (data != 0) {
a737f256
CD		 2071 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2072 "0x%llx\n", data);
f7c6d140
AP		 2073 return 1;
2074 }
15c4a640 2075 break;
b5e2fec0
AG		 2076 case MSR_IA32_DEBUGCTLMSR:
2077 if (!data) {
2078 /* We support the non-activated case already */
2079 break;
2080 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2081 /* Values other than LBR and BTF are vendor-specific,
2082 thus reserved and should throw a #GP */
2083 return 1;
2084 }
a737f256
CD		 2085 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2086 __func__, data);
b5e2fec0 2087 break;
9ba075a6 2088 case 0x200 ... 0x2ff:
ff53604b 2089 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2090 case MSR_IA32_APICBASE:
58cb628d 2091 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2092 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2093 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2094 case MSR_IA32_TSCDEADLINE:
2095 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2096 break;
ba904635
WA		 2097 case MSR_IA32_TSC_ADJUST:
2098 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2099 if (!msr_info->host_initiated) {
d913b904 2100 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2101 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2102 }
2103 vcpu->arch.ia32_tsc_adjust_msr = data;
2104 }
2105 break;
15c4a640 2106 case MSR_IA32_MISC_ENABLE:
ad312c7c 2107 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2108 break;
64d60670
PB		 2109 case MSR_IA32_SMBASE:
2110 if (!msr_info->host_initiated)
2111 return 1;
2112 vcpu->arch.smbase = data;
2113 break;
11c6bffa 2114 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2115 case MSR_KVM_WALL_CLOCK:
2116 vcpu->kvm->arch.wall_clock = data;
2117 kvm_write_wall_clock(vcpu->kvm, data);
2118 break;
11c6bffa 2119 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2120 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2121 u64 gpa_offset;
54750f2c
MT		 2122 struct kvm_arch *ka = &vcpu->kvm->arch;
2123
12f9a48f 2124 kvmclock_reset(vcpu);
18068523 2125
54750f2c
MT		 2126 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2127 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2128
2129 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2130 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2131 &vcpu->requests);
2132
2133 ka->boot_vcpu_runs_old_kvmclock = tmp;
2134 }
2135
18068523 2136 vcpu->arch.time = data;
0061d53d 2137 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2138
2139 /* we verify if the enable bit is set... */
2140 if (!(data & 1))
2141 break;
2142
0b79459b 2143 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2144
0b79459b 2145 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2146 &vcpu->arch.pv_time, data & ~1ULL,
2147 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2148 vcpu->arch.pv_time_enabled = false;
2149 else
2150 vcpu->arch.pv_time_enabled = true;
32cad84f 2151
18068523
GOC		 2152 break;
2153 }
344d9588
GN		 2154 case MSR_KVM_ASYNC_PF_EN:
2155 if (kvm_pv_enable_async_pf(vcpu, data))
2156 return 1;
2157 break;
c9aaa895
GC		 2158 case MSR_KVM_STEAL_TIME:
2159
2160 if (unlikely(!sched_info_on()))
2161 return 1;
2162
2163 if (data & KVM_STEAL_RESERVED_MASK)
2164 return 1;
2165
2166 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2167 data & KVM_STEAL_VALID_BITS,
2168 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2169 return 1;
2170
2171 vcpu->arch.st.msr_val = data;
2172
2173 if (!(data & KVM_MSR_ENABLED))
2174 break;
2175
c9aaa895
GC		 2176 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2177
2178 break;
ae7a2a3f
MT		 2179 case MSR_KVM_PV_EOI_EN:
2180 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2181 return 1;
2182 break;
c9aaa895 2183
890ca9ae
HY		 2184 case MSR_IA32_MCG_CTL:
2185 case MSR_IA32_MCG_STATUS:
81760dcc 2186 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2187 return set_msr_mce(vcpu, msr, data);
71db6023 2188
6912ac32
WH		 2189 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2190 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2191 pr = true; /* fall through */
2192 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2193 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2194 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2195 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2196
2197 if (pr || data != 0)
a737f256
CD		 2198 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2199 "0x%x data 0x%llx\n", msr, data);
5753785f 2200 break;
84e0cefa
JS		 2201 case MSR_K7_CLK_CTL:
2202 /*
2203 * Ignore all writes to this no longer documented MSR.
2204 * Writes are only relevant for old K7 processors,
2205 * all pre-dating SVM, but a recommended workaround from
4a969980 2206 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2207 * affected processor models on the command line, hence
2208 * the need to ignore the workaround.
2209 */
2210 break;
55cd8e5a 2211 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2212 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2213 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2214 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2215 return kvm_hv_set_msr_common(vcpu, msr, data,
2216 msr_info->host_initiated);
91c9c3ed 2217 case MSR_IA32_BBL_CR_CTL3:
2218 /* Drop writes to this legacy MSR -- see rdmsr
2219 * counterpart for further detail.
2220 */
a737f256 2221 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2222 break;
2b036c6b
BO		 2223 case MSR_AMD64_OSVW_ID_LENGTH:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.length = data;
2227 break;
2228 case MSR_AMD64_OSVW_STATUS:
2229 if (!guest_cpuid_has_osvw(vcpu))
2230 return 1;
2231 vcpu->arch.osvw.status = data;
2232 break;
15c4a640 2233 default:
ffde22ac
ES		 2234 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2235 return xen_hvm_config(vcpu, data);
c6702c9d 2236 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2237 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2238 if (!ignore_msrs) {
a737f256
CD		 2239 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2240 msr, data);
ed85c068
AP		 2241 return 1;
2242 } else {
a737f256
CD		 2243 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2244 msr, data);
ed85c068
AP		 2245 break;
2246 }
15c4a640
CO		 2247 }
2248 return 0;
2249}
2250EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2251
2252
2253/*
2254 * Reads an msr value (of 'msr_index') into 'pdata'.
2255 * Returns 0 on success, non-0 otherwise.
2256 * Assumes vcpu_load() was already called.
2257 */
609e36d3 2258int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2259{
609e36d3 2260 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2261}
ff651cb6 2262EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2263
890ca9ae 2264static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2265{
2266 u64 data;
890ca9ae
HY		 2267 u64 mcg_cap = vcpu->arch.mcg_cap;
2268 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2269
2270 switch (msr) {
15c4a640
CO		 2271 case MSR_IA32_P5_MC_ADDR:
2272 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2273 data = 0;
2274 break;
15c4a640 2275 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2276 data = vcpu->arch.mcg_cap;
2277 break;
c7ac679c 2278 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2279 if (!(mcg_cap & MCG_CTL_P))
2280 return 1;
2281 data = vcpu->arch.mcg_ctl;
2282 break;
2283 case MSR_IA32_MCG_STATUS:
2284 data = vcpu->arch.mcg_status;
2285 break;
2286 default:
2287 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2288 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2289 u32 offset = msr - MSR_IA32_MC0_CTL;
2290 data = vcpu->arch.mce_banks[offset];
2291 break;
2292 }
2293 return 1;
2294 }
2295 *pdata = data;
2296 return 0;
2297}
2298
609e36d3 2299int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2300{
609e36d3 2301 switch (msr_info->index) {
890ca9ae 2302 case MSR_IA32_PLATFORM_ID:
15c4a640 2303 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2304 case MSR_IA32_DEBUGCTLMSR:
2305 case MSR_IA32_LASTBRANCHFROMIP:
2306 case MSR_IA32_LASTBRANCHTOIP:
2307 case MSR_IA32_LASTINTFROMIP:
2308 case MSR_IA32_LASTINTTOIP:
60af2ecd 2309 case MSR_K8_SYSCFG:
3afb1121
PB		 2310 case MSR_K8_TSEG_ADDR:
2311 case MSR_K8_TSEG_MASK:
60af2ecd 2312 case MSR_K7_HWCR:
61a6bd67 2313 case MSR_VM_HSAVE_PA:
1fdbd48c 2314 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2315 case MSR_AMD64_NB_CFG:
f7c6d140 2316 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2317 case MSR_AMD64_BU_CFG2:
0c2df2a1 2318 case MSR_IA32_PERF_CTL:
609e36d3 2319 msr_info->data = 0;
15c4a640 2320 break;
6912ac32
WH		 2321 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2322 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2323 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2324 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2325 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2326 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2327 msr_info->data = 0;
5753785f 2328 break;
742bc670 2329 case MSR_IA32_UCODE_REV:
609e36d3 2330 msr_info->data = 0x100000000ULL;
742bc670 2331 break;
9ba075a6 2332 case MSR_MTRRcap:
9ba075a6 2333 case 0x200 ... 0x2ff:
ff53604b 2334 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2335 case 0xcd: /* fsb frequency */
609e36d3 2336 msr_info->data = 3;
15c4a640 2337 break;
7b914098
JS		 2338 /*
2339 * MSR_EBC_FREQUENCY_ID
2340 * Conservative value valid for even the basic CPU models.
2341 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2342 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2343 * and 266MHz for model 3, or 4. Set Core Clock
2344 * Frequency to System Bus Frequency Ratio to 1 (bits
2345 * 31:24) even though these are only valid for CPU
2346 * models > 2, however guests may end up dividing or
2347 * multiplying by zero otherwise.
2348 */
2349 case MSR_EBC_FREQUENCY_ID:
609e36d3 2350 msr_info->data = 1 << 24;
7b914098 2351 break;
15c4a640 2352 case MSR_IA32_APICBASE:
609e36d3 2353 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2354 break;
0105d1a5 2355 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2356 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2357 break;
a3e06bbe 2358 case MSR_IA32_TSCDEADLINE:
609e36d3 2359 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2360 break;
ba904635 2361 case MSR_IA32_TSC_ADJUST:
609e36d3 2362 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2363 break;
15c4a640 2364 case MSR_IA32_MISC_ENABLE:
609e36d3 2365 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2366 break;
64d60670
PB		 2367 case MSR_IA32_SMBASE:
2368 if (!msr_info->host_initiated)
2369 return 1;
2370 msr_info->data = vcpu->arch.smbase;
15c4a640 2371 break;
847f0ad8
AG		 2372 case MSR_IA32_PERF_STATUS:
2373 /* TSC increment by tick */
609e36d3 2374 msr_info->data = 1000ULL;
847f0ad8 2375 /* CPU multiplier */
b0996ae4 2376 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2377 break;
15c4a640 2378 case MSR_EFER:
609e36d3 2379 msr_info->data = vcpu->arch.efer;
15c4a640 2380 break;
18068523 2381 case MSR_KVM_WALL_CLOCK:
11c6bffa 2382 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2383 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2384 break;
2385 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2386 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2387 msr_info->data = vcpu->arch.time;
18068523 2388 break;
344d9588 2389 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2390 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2391 break;
c9aaa895 2392 case MSR_KVM_STEAL_TIME:
609e36d3 2393 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2394 break;
1d92128f 2395 case MSR_KVM_PV_EOI_EN:
609e36d3 2396 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2397 break;
890ca9ae
HY		 2398 case MSR_IA32_P5_MC_ADDR:
2399 case MSR_IA32_P5_MC_TYPE:
2400 case MSR_IA32_MCG_CAP:
2401 case MSR_IA32_MCG_CTL:
2402 case MSR_IA32_MCG_STATUS:
81760dcc 2403 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2404 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2405 case MSR_K7_CLK_CTL:
2406 /*
2407 * Provide expected ramp-up count for K7. All other
2408 * are set to zero, indicating minimum divisors for
2409 * every field.
2410 *
2411 * This prevents guest kernels on AMD host with CPU
2412 * type 6, model 8 and higher from exploding due to
2413 * the rdmsr failing.
2414 */
609e36d3 2415 msr_info->data = 0x20000000;
84e0cefa 2416 break;
55cd8e5a 2417 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2418 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2419 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2420 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2421 return kvm_hv_get_msr_common(vcpu,
2422 msr_info->index, &msr_info->data);
55cd8e5a 2423 break;
91c9c3ed 2424 case MSR_IA32_BBL_CR_CTL3:
2425 /* This legacy MSR exists but isn't fully documented in current
2426 * silicon. It is however accessed by winxp in very narrow
2427 * scenarios where it sets bit #19, itself documented as
2428 * a "reserved" bit. Best effort attempt to source coherent
2429 * read data here should the balance of the register be
2430 * interpreted by the guest:
2431 *
2432 * L2 cache control register 3: 64GB range, 256KB size,
2433 * enabled, latency 0x1, configured
2434 */
609e36d3 2435 msr_info->data = 0xbe702111;
91c9c3ed 2436 break;
2b036c6b
BO		 2437 case MSR_AMD64_OSVW_ID_LENGTH:
2438 if (!guest_cpuid_has_osvw(vcpu))
2439 return 1;
609e36d3 2440 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2441 break;
2442 case MSR_AMD64_OSVW_STATUS:
2443 if (!guest_cpuid_has_osvw(vcpu))
2444 return 1;
609e36d3 2445 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2446 break;
15c4a640 2447 default:
c6702c9d 2448 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2449 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2450 if (!ignore_msrs) {
609e36d3 2451 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2452 return 1;
2453 } else {
609e36d3
PB		 2454 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2455 msr_info->data = 0;
ed85c068
AP		 2456 }
2457 break;
15c4a640 2458 }
15c4a640
CO		 2459 return 0;
2460}
2461EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2462
313a3dc7
CO		 2463/*
2464 * Read or write a bunch of msrs. All parameters are kernel addresses.
2465 *
2466 * @return number of msrs set successfully.
2467 */
2468static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2469 struct kvm_msr_entry *entries,
2470 int (*do_msr)(struct kvm_vcpu *vcpu,
2471 unsigned index, u64 *data))
2472{
f656ce01 2473 int i, idx;
313a3dc7 2474
f656ce01 2475 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2476 for (i = 0; i < msrs->nmsrs; ++i)
2477 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2478 break;
f656ce01 2479 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2480
313a3dc7
CO		 2481 return i;
2482}
2483
2484/*
2485 * Read or write a bunch of msrs. Parameters are user addresses.
2486 *
2487 * @return number of msrs set successfully.
2488 */
2489static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2490 int (*do_msr)(struct kvm_vcpu *vcpu,
2491 unsigned index, u64 *data),
2492 int writeback)
2493{
2494 struct kvm_msrs msrs;
2495 struct kvm_msr_entry *entries;
2496 int r, n;
2497 unsigned size;
2498
2499 r = -EFAULT;
2500 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2501 goto out;
2502
2503 r = -E2BIG;
2504 if (msrs.nmsrs >= MAX_IO_MSRS)
2505 goto out;
2506
313a3dc7 2507 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2508 entries = memdup_user(user_msrs->entries, size);
2509 if (IS_ERR(entries)) {
2510 r = PTR_ERR(entries);
313a3dc7 2511 goto out;
ff5c2c03 2512 }
313a3dc7
CO		 2513
2514 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2515 if (r < 0)
2516 goto out_free;
2517
2518 r = -EFAULT;
2519 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2520 goto out_free;
2521
2522 r = n;
2523
2524out_free:
7a73c028 2525 kfree(entries);
313a3dc7
CO		 2526out:
2527 return r;
2528}
2529
784aa3d7 2530int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2531{
2532 int r;
2533
2534 switch (ext) {
2535 case KVM_CAP_IRQCHIP:
2536 case KVM_CAP_HLT:
2537 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2538 case KVM_CAP_SET_TSS_ADDR:
07716717 2539 case KVM_CAP_EXT_CPUID:
9c15bb1d 2540 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2541 case KVM_CAP_CLOCKSOURCE:
7837699f 2542 case KVM_CAP_PIT:
a28e4f5a 2543 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2544 case KVM_CAP_MP_STATE:
ed848624 2545 case KVM_CAP_SYNC_MMU:
a355c85c 2546 case KVM_CAP_USER_NMI:
52d939a0 2547 case KVM_CAP_REINJECT_CONTROL:
4925663a 2548 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2549 case KVM_CAP_IOEVENTFD:
f848a5a8 2550 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2551 case KVM_CAP_PIT2:
e9f42757 2552 case KVM_CAP_PIT_STATE2:
b927a3ce 2553 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2554 case KVM_CAP_XEN_HVM:
afbcf7ab 2555 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2556 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2557 case KVM_CAP_HYPERV:
10388a07 2558 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2559 case KVM_CAP_HYPERV_SPIN:
5c919412 2560 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2561 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2562 case KVM_CAP_DEBUGREGS:
d2be1651 2563 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2564 case KVM_CAP_XSAVE:
344d9588 2565 case KVM_CAP_ASYNC_PF:
92a1f12d 2566 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2567 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2568 case KVM_CAP_READONLY_MEM:
5f66b620 2569 case KVM_CAP_HYPERV_TIME:
100943c5 2570 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2571 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2572 case KVM_CAP_ENABLE_CAP_VM:
2573 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2574 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2575 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2576#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2577 case KVM_CAP_ASSIGN_DEV_IRQ:
2578 case KVM_CAP_PCI_2_3:
2579#endif
018d00d2
ZX		 2580 r = 1;
2581 break;
6d396b55
PB		 2582 case KVM_CAP_X86_SMM:
2583 /* SMBASE is usually relocated above 1M on modern chipsets,
2584 * and SMM handlers might indeed rely on 4G segment limits,
2585 * so do not report SMM to be available if real mode is
2586 * emulated via vm86 mode. Still, do not go to great lengths
2587 * to avoid userspace's usage of the feature, because it is a
2588 * fringe case that is not enabled except via specific settings
2589 * of the module parameters.
2590 */
2591 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2592 break;
542472b5
LV		 2593 case KVM_CAP_COALESCED_MMIO:
2594 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2595 break;
774ead3a
AK		 2596 case KVM_CAP_VAPIC:
2597 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2598 break;
f725230a 2599 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2600 r = KVM_SOFT_MAX_VCPUS;
2601 break;
2602 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2603 r = KVM_MAX_VCPUS;
2604 break;
a988b910 2605 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2606 r = KVM_USER_MEM_SLOTS;
a988b910 2607 break;
a68a6a72
MT		 2608 case KVM_CAP_PV_MMU: /* obsolete */
2609 r = 0;
2f333bcb 2610 break;
4cee4b72 2611#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2612 case KVM_CAP_IOMMU:
a1b60c1c 2613 r = iommu_present(&pci_bus_type);
62c476c7 2614 break;
4cee4b72 2615#endif
890ca9ae
HY		 2616 case KVM_CAP_MCE:
2617 r = KVM_MAX_MCE_BANKS;
2618 break;
2d5b5a66 2619 case KVM_CAP_XCRS:
d366bf7e 2620 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2621 break;
92a1f12d
JR		 2622 case KVM_CAP_TSC_CONTROL:
2623 r = kvm_has_tsc_control;
2624 break;
018d00d2
ZX		 2625 default:
2626 r = 0;
2627 break;
2628 }
2629 return r;
2630
2631}
2632
043405e1
CO		 2633long kvm_arch_dev_ioctl(struct file *filp,
2634 unsigned int ioctl, unsigned long arg)
2635{
2636 void __user *argp = (void __user *)arg;
2637 long r;
2638
2639 switch (ioctl) {
2640 case KVM_GET_MSR_INDEX_LIST: {
2641 struct kvm_msr_list __user *user_msr_list = argp;
2642 struct kvm_msr_list msr_list;
2643 unsigned n;
2644
2645 r = -EFAULT;
2646 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2647 goto out;
2648 n = msr_list.nmsrs;
62ef68bb 2649 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2650 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2651 goto out;
2652 r = -E2BIG;
e125e7b6 2653 if (n < msr_list.nmsrs)
043405e1
CO		 2654 goto out;
2655 r = -EFAULT;
2656 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2657 num_msrs_to_save * sizeof(u32)))
2658 goto out;
e125e7b6 2659 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2660 &emulated_msrs,
62ef68bb 2661 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2662 goto out;
2663 r = 0;
2664 break;
2665 }
9c15bb1d
BP		 2666 case KVM_GET_SUPPORTED_CPUID:
2667 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2668 struct kvm_cpuid2 __user *cpuid_arg = argp;
2669 struct kvm_cpuid2 cpuid;
2670
2671 r = -EFAULT;
2672 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2673 goto out;
9c15bb1d
BP		 2674
2675 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2676 ioctl);
674eea0f
AK		 2677 if (r)
2678 goto out;
2679
2680 r = -EFAULT;
2681 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2682 goto out;
2683 r = 0;
2684 break;
2685 }
890ca9ae
HY		 2686 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2687 u64 mce_cap;
2688
2689 mce_cap = KVM_MCE_CAP_SUPPORTED;
2690 r = -EFAULT;
2691 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2692 goto out;
2693 r = 0;
2694 break;
2695 }
043405e1
CO		 2696 default:
2697 r = -EINVAL;
2698 }
2699out:
2700 return r;
2701}
2702
f5f48ee1
SY		 2703static void wbinvd_ipi(void *garbage)
2704{
2705 wbinvd();
2706}
2707
2708static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2709{
e0f0bbc5 2710 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2711}
2712
2860c4b1
PB		 2713static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2714{
2715 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2716}
2717
313a3dc7
CO		 2718void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2719{
f5f48ee1
SY		 2720 /* Address WBINVD may be executed by guest */
2721 if (need_emulate_wbinvd(vcpu)) {
2722 if (kvm_x86_ops->has_wbinvd_exit())
2723 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2724 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2725 smp_call_function_single(vcpu->cpu,
2726 wbinvd_ipi, NULL, 1);
2727 }
2728
313a3dc7 2729 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2730
0dd6a6ed
ZA		 2731 /* Apply any externally detected TSC adjustments (due to suspend) */
2732 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2733 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2734 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2735 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2736 }
8f6055cb 2737
48434c20 2738 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2739 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2740 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2741 if (tsc_delta < 0)
2742 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2743 if (check_tsc_unstable()) {
07c1419a 2744 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2745 vcpu->arch.last_guest_tsc);
2746 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2747 vcpu->arch.tsc_catchup = 1;
c285545f 2748 }
d98d07ca
MT		 2749 /*
2750 * On a host with synchronized TSC, there is no need to update
2751 * kvmclock on vcpu->cpu migration
2752 */
2753 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2754 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2755 if (vcpu->cpu != cpu)
2756 kvm_migrate_timers(vcpu);
e48672fa 2757 vcpu->cpu = cpu;
6b7d7e76 2758 }
c9aaa895 2759
c9aaa895 2760 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2761}
2762
2763void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2764{
02daab21 2765 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2766 kvm_put_guest_fpu(vcpu);
4ea1636b 2767 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2768}
2769
313a3dc7
CO		 2770static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2771 struct kvm_lapic_state *s)
2772{
d62caabb
AS		 2773 if (vcpu->arch.apicv_active)
2774 kvm_x86_ops->sync_pir_to_irr(vcpu);
2775
ad312c7c 2776 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2777
2778 return 0;
2779}
2780
2781static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2782 struct kvm_lapic_state *s)
2783{
64eb0620 2784 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2785 update_cr8_intercept(vcpu);
313a3dc7
CO		 2786
2787 return 0;
2788}
2789
127a457a
MG		 2790static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2791{
2792 return (!lapic_in_kernel(vcpu) ||
2793 kvm_apic_accept_pic_intr(vcpu));
2794}
2795
782d422b
MG		 2796/*
2797 * if userspace requested an interrupt window, check that the
2798 * interrupt window is open.
2799 *
2800 * No need to exit to userspace if we already have an interrupt queued.
2801 */
2802static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2803{
2804 return kvm_arch_interrupt_allowed(vcpu) &&
2805 !kvm_cpu_has_interrupt(vcpu) &&
2806 !kvm_event_needs_reinjection(vcpu) &&
2807 kvm_cpu_accept_dm_intr(vcpu);
2808}
2809
f77bc6a4
ZX		 2810static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2811 struct kvm_interrupt *irq)
2812{
02cdb50f 2813 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2814 return -EINVAL;
1c1a9ce9
SR		 2815
2816 if (!irqchip_in_kernel(vcpu->kvm)) {
2817 kvm_queue_interrupt(vcpu, irq->irq, false);
2818 kvm_make_request(KVM_REQ_EVENT, vcpu);
2819 return 0;
2820 }
2821
2822 /*
2823 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2824 * fail for in-kernel 8259.
2825 */
2826 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2827 return -ENXIO;
f77bc6a4 2828
1c1a9ce9
SR		 2829 if (vcpu->arch.pending_external_vector != -1)
2830 return -EEXIST;
f77bc6a4 2831
1c1a9ce9 2832 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2833 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2834 return 0;
2835}
2836
c4abb7c9
JK		 2837static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2838{
c4abb7c9 2839 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2840
2841 return 0;
2842}
2843
f077825a
PB		 2844static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2845{
64d60670
PB		 2846 kvm_make_request(KVM_REQ_SMI, vcpu);
2847
f077825a
PB		 2848 return 0;
2849}
2850
b209749f
AK		 2851static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2852 struct kvm_tpr_access_ctl *tac)
2853{
2854 if (tac->flags)
2855 return -EINVAL;
2856 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2857 return 0;
2858}
2859
890ca9ae
HY		 2860static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2861 u64 mcg_cap)
2862{
2863 int r;
2864 unsigned bank_num = mcg_cap & 0xff, bank;
2865
2866 r = -EINVAL;
a9e38c3e 2867 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2868 goto out;
2869 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2870 goto out;
2871 r = 0;
2872 vcpu->arch.mcg_cap = mcg_cap;
2873 /* Init IA32_MCG_CTL to all 1s */
2874 if (mcg_cap & MCG_CTL_P)
2875 vcpu->arch.mcg_ctl = ~(u64)0;
2876 /* Init IA32_MCi_CTL to all 1s */
2877 for (bank = 0; bank < bank_num; bank++)
2878 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2879out:
2880 return r;
2881}
2882
2883static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2884 struct kvm_x86_mce *mce)
2885{
2886 u64 mcg_cap = vcpu->arch.mcg_cap;
2887 unsigned bank_num = mcg_cap & 0xff;
2888 u64 *banks = vcpu->arch.mce_banks;
2889
2890 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2891 return -EINVAL;
2892 /*
2893 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2894 * reporting is disabled
2895 */
2896 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2897 vcpu->arch.mcg_ctl != ~(u64)0)
2898 return 0;
2899 banks += 4 * mce->bank;
2900 /*
2901 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2902 * reporting is disabled for the bank
2903 */
2904 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2905 return 0;
2906 if (mce->status & MCI_STATUS_UC) {
2907 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2908 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2909 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2910 return 0;
2911 }
2912 if (banks[1] & MCI_STATUS_VAL)
2913 mce->status |= MCI_STATUS_OVER;
2914 banks[2] = mce->addr;
2915 banks[3] = mce->misc;
2916 vcpu->arch.mcg_status = mce->mcg_status;
2917 banks[1] = mce->status;
2918 kvm_queue_exception(vcpu, MC_VECTOR);
2919 } else if (!(banks[1] & MCI_STATUS_VAL)
2920 || !(banks[1] & MCI_STATUS_UC)) {
2921 if (banks[1] & MCI_STATUS_VAL)
2922 mce->status |= MCI_STATUS_OVER;
2923 banks[2] = mce->addr;
2924 banks[3] = mce->misc;
2925 banks[1] = mce->status;
2926 } else
2927 banks[1] |= MCI_STATUS_OVER;
2928 return 0;
2929}
2930
3cfc3092
JK		 2931static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2932 struct kvm_vcpu_events *events)
2933{
7460fb4a 2934 process_nmi(vcpu);
03b82a30
JK		 2935 events->exception.injected =
2936 vcpu->arch.exception.pending &&
2937 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2938 events->exception.nr = vcpu->arch.exception.nr;
2939 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2940 events->exception.pad = 0;
3cfc3092
JK		 2941 events->exception.error_code = vcpu->arch.exception.error_code;
2942
03b82a30
JK		 2943 events->interrupt.injected =
2944 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2945 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2946 events->interrupt.soft = 0;
37ccdcbe 2947 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2948
2949 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2950 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2951 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2952 events->nmi.pad = 0;
3cfc3092 2953
66450a21 2954 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2955
f077825a
PB		 2956 events->smi.smm = is_smm(vcpu);
2957 events->smi.pending = vcpu->arch.smi_pending;
2958 events->smi.smm_inside_nmi =
2959 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2960 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2961
dab4b911 2962 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2963 | KVM_VCPUEVENT_VALID_SHADOW
2964 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2965 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2966}
2967
2968static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2969 struct kvm_vcpu_events *events)
2970{
dab4b911 2971 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2972 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2973 | KVM_VCPUEVENT_VALID_SHADOW
2974 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2975 return -EINVAL;
2976
78e546c8
PB		 2977 if (events->exception.injected &&
2978 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2979 return -EINVAL;
2980
7460fb4a 2981 process_nmi(vcpu);
3cfc3092
JK		 2982 vcpu->arch.exception.pending = events->exception.injected;
2983 vcpu->arch.exception.nr = events->exception.nr;
2984 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2985 vcpu->arch.exception.error_code = events->exception.error_code;
2986
2987 vcpu->arch.interrupt.pending = events->interrupt.injected;
2988 vcpu->arch.interrupt.nr = events->interrupt.nr;
2989 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2990 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2991 kvm_x86_ops->set_interrupt_shadow(vcpu,
2992 events->interrupt.shadow);
3cfc3092
JK		 2993
2994 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2995 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2996 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2997 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2998
66450a21 2999 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3000 lapic_in_kernel(vcpu))
66450a21 3001 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3002
f077825a
PB		 3003 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3004 if (events->smi.smm)
3005 vcpu->arch.hflags |= HF_SMM_MASK;
3006 else
3007 vcpu->arch.hflags &= ~HF_SMM_MASK;
3008 vcpu->arch.smi_pending = events->smi.pending;
3009 if (events->smi.smm_inside_nmi)
3010 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3011 else
3012 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3013 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3014 if (events->smi.latched_init)
3015 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3016 else
3017 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3018 }
3019 }
3020
3842d135
AK		 3021 kvm_make_request(KVM_REQ_EVENT, vcpu);
3022
3cfc3092
JK		 3023 return 0;
3024}
3025
a1efbe77
JK		 3026static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3027 struct kvm_debugregs *dbgregs)
3028{
73aaf249
JK		 3029 unsigned long val;
3030
a1efbe77 3031 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3032 kvm_get_dr(vcpu, 6, &val);
73aaf249 3033 dbgregs->dr6 = val;
a1efbe77
JK		 3034 dbgregs->dr7 = vcpu->arch.dr7;
3035 dbgregs->flags = 0;
97e69aa6 3036 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3037}
3038
3039static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3040 struct kvm_debugregs *dbgregs)
3041{
3042 if (dbgregs->flags)
3043 return -EINVAL;
3044
d14bdb55
PB		 3045 if (dbgregs->dr6 & ~0xffffffffull)
3046 return -EINVAL;
3047 if (dbgregs->dr7 & ~0xffffffffull)
3048 return -EINVAL;
3049
a1efbe77 3050 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3051 kvm_update_dr0123(vcpu);
a1efbe77 3052 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3053 kvm_update_dr6(vcpu);
a1efbe77 3054 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3055 kvm_update_dr7(vcpu);
a1efbe77 3056
a1efbe77
JK		 3057 return 0;
3058}
3059
df1daba7
PB		 3060#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3061
3062static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3063{
c47ada30 3064 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3065 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3066 u64 valid;
3067
3068 /*
3069 * Copy legacy XSAVE area, to avoid complications with CPUID
3070 * leaves 0 and 1 in the loop below.
3071 */
3072 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3073
3074 /* Set XSTATE_BV */
3075 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3076
3077 /*
3078 * Copy each region from the possibly compacted offset to the
3079 * non-compacted offset.
3080 */
d91cab78 3081 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3082 while (valid) {
3083 u64 feature = valid & -valid;
3084 int index = fls64(feature) - 1;
3085 void *src = get_xsave_addr(xsave, feature);
3086
3087 if (src) {
3088 u32 size, offset, ecx, edx;
3089 cpuid_count(XSTATE_CPUID, index,
3090 &size, &offset, &ecx, &edx);
3091 memcpy(dest + offset, src, size);
3092 }
3093
3094 valid -= feature;
3095 }
3096}
3097
3098static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3099{
c47ada30 3100 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3101 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3102 u64 valid;
3103
3104 /*
3105 * Copy legacy XSAVE area, to avoid complications with CPUID
3106 * leaves 0 and 1 in the loop below.
3107 */
3108 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3109
3110 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3111 xsave->header.xfeatures = xstate_bv;
782511b0 3112 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3113 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3114
3115 /*
3116 * Copy each region from the non-compacted offset to the
3117 * possibly compacted offset.
3118 */
d91cab78 3119 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3120 while (valid) {
3121 u64 feature = valid & -valid;
3122 int index = fls64(feature) - 1;
3123 void *dest = get_xsave_addr(xsave, feature);
3124
3125 if (dest) {
3126 u32 size, offset, ecx, edx;
3127 cpuid_count(XSTATE_CPUID, index,
3128 &size, &offset, &ecx, &edx);
3129 memcpy(dest, src + offset, size);
ee4100da 3130 }
df1daba7
PB		 3131
3132 valid -= feature;
3133 }
3134}
3135
2d5b5a66
SY		 3136static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3137 struct kvm_xsave *guest_xsave)
3138{
d366bf7e 3139 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3140 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3141 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3142 } else {
2d5b5a66 3143 memcpy(guest_xsave->region,
7366ed77 3144 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3145 sizeof(struct fxregs_state));
2d5b5a66 3146 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3147 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3148 }
3149}
3150
3151static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3152 struct kvm_xsave *guest_xsave)
3153{
3154 u64 xstate_bv =
3155 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3156
d366bf7e 3157 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3158 /*
3159 * Here we allow setting states that are not present in
3160 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3161 * with old userspace.
3162 */
4ff41732 3163 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3164 return -EINVAL;
df1daba7 3165 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3166 } else {
d91cab78 3167 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3168 return -EINVAL;
7366ed77 3169 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3170 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3171 }
3172 return 0;
3173}
3174
3175static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3176 struct kvm_xcrs *guest_xcrs)
3177{
d366bf7e 3178 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3179 guest_xcrs->nr_xcrs = 0;
3180 return;
3181 }
3182
3183 guest_xcrs->nr_xcrs = 1;
3184 guest_xcrs->flags = 0;
3185 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3186 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3187}
3188
3189static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3190 struct kvm_xcrs *guest_xcrs)
3191{
3192 int i, r = 0;
3193
d366bf7e 3194 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3195 return -EINVAL;
3196
3197 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3198 return -EINVAL;
3199
3200 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3201 /* Only support XCR0 currently */
c67a04cb 3202 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3203 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3204 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3205 break;
3206 }
3207 if (r)
3208 r = -EINVAL;
3209 return r;
3210}
3211
1c0b28c2
EM		 3212/*
3213 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3214 * stopped by the hypervisor. This function will be called from the host only.
3215 * EINVAL is returned when the host attempts to set the flag for a guest that
3216 * does not support pv clocks.
3217 */
3218static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3219{
0b79459b 3220 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3221 return -EINVAL;
51d59c6b 3222 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3223 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3224 return 0;
3225}
3226
5c919412
AS		 3227static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3228 struct kvm_enable_cap *cap)
3229{
3230 if (cap->flags)
3231 return -EINVAL;
3232
3233 switch (cap->cap) {
3234 case KVM_CAP_HYPERV_SYNIC:
3235 return kvm_hv_activate_synic(vcpu);
3236 default:
3237 return -EINVAL;
3238 }
3239}
3240
313a3dc7
CO		 3241long kvm_arch_vcpu_ioctl(struct file *filp,
3242 unsigned int ioctl, unsigned long arg)
3243{
3244 struct kvm_vcpu *vcpu = filp->private_data;
3245 void __user *argp = (void __user *)arg;
3246 int r;
d1ac91d8
AK		 3247 union {
3248 struct kvm_lapic_state *lapic;
3249 struct kvm_xsave *xsave;
3250 struct kvm_xcrs *xcrs;
3251 void *buffer;
3252 } u;
3253
3254 u.buffer = NULL;
313a3dc7
CO		 3255 switch (ioctl) {
3256 case KVM_GET_LAPIC: {
2204ae3c 3257 r = -EINVAL;
bce87cce 3258 if (!lapic_in_kernel(vcpu))
2204ae3c 3259 goto out;
d1ac91d8 3260 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3261
b772ff36 3262 r = -ENOMEM;
d1ac91d8 3263 if (!u.lapic)
b772ff36 3264 goto out;
d1ac91d8 3265 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3266 if (r)
3267 goto out;
3268 r = -EFAULT;
d1ac91d8 3269 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3270 goto out;
3271 r = 0;
3272 break;
3273 }
3274 case KVM_SET_LAPIC: {
2204ae3c 3275 r = -EINVAL;
bce87cce 3276 if (!lapic_in_kernel(vcpu))
2204ae3c 3277 goto out;
ff5c2c03 3278 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3279 if (IS_ERR(u.lapic))
3280 return PTR_ERR(u.lapic);
ff5c2c03 3281
d1ac91d8 3282 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3283 break;
3284 }
f77bc6a4
ZX		 3285 case KVM_INTERRUPT: {
3286 struct kvm_interrupt irq;
3287
3288 r = -EFAULT;
3289 if (copy_from_user(&irq, argp, sizeof irq))
3290 goto out;
3291 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3292 break;
3293 }
c4abb7c9
JK		 3294 case KVM_NMI: {
3295 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3296 break;
3297 }
f077825a
PB		 3298 case KVM_SMI: {
3299 r = kvm_vcpu_ioctl_smi(vcpu);
3300 break;
3301 }
313a3dc7
CO		 3302 case KVM_SET_CPUID: {
3303 struct kvm_cpuid __user *cpuid_arg = argp;
3304 struct kvm_cpuid cpuid;
3305
3306 r = -EFAULT;
3307 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3308 goto out;
3309 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3310 break;
3311 }
07716717
DK		 3312 case KVM_SET_CPUID2: {
3313 struct kvm_cpuid2 __user *cpuid_arg = argp;
3314 struct kvm_cpuid2 cpuid;
3315
3316 r = -EFAULT;
3317 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3318 goto out;
3319 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3320 cpuid_arg->entries);
07716717
DK		 3321 break;
3322 }
3323 case KVM_GET_CPUID2: {
3324 struct kvm_cpuid2 __user *cpuid_arg = argp;
3325 struct kvm_cpuid2 cpuid;
3326
3327 r = -EFAULT;
3328 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3329 goto out;
3330 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3331 cpuid_arg->entries);
07716717
DK		 3332 if (r)
3333 goto out;
3334 r = -EFAULT;
3335 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3336 goto out;
3337 r = 0;
3338 break;
3339 }
313a3dc7 3340 case KVM_GET_MSRS:
609e36d3 3341 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3342 break;
3343 case KVM_SET_MSRS:
3344 r = msr_io(vcpu, argp, do_set_msr, 0);
3345 break;
b209749f
AK		 3346 case KVM_TPR_ACCESS_REPORTING: {
3347 struct kvm_tpr_access_ctl tac;
3348
3349 r = -EFAULT;
3350 if (copy_from_user(&tac, argp, sizeof tac))
3351 goto out;
3352 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3353 if (r)
3354 goto out;
3355 r = -EFAULT;
3356 if (copy_to_user(argp, &tac, sizeof tac))
3357 goto out;
3358 r = 0;
3359 break;
3360 };
b93463aa
AK		 3361 case KVM_SET_VAPIC_ADDR: {
3362 struct kvm_vapic_addr va;
3363
3364 r = -EINVAL;
35754c98 3365 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3366 goto out;
3367 r = -EFAULT;
3368 if (copy_from_user(&va, argp, sizeof va))
3369 goto out;
fda4e2e8 3370 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3371 break;
3372 }
890ca9ae
HY		 3373 case KVM_X86_SETUP_MCE: {
3374 u64 mcg_cap;
3375
3376 r = -EFAULT;
3377 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3378 goto out;
3379 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3380 break;
3381 }
3382 case KVM_X86_SET_MCE: {
3383 struct kvm_x86_mce mce;
3384
3385 r = -EFAULT;
3386 if (copy_from_user(&mce, argp, sizeof mce))
3387 goto out;
3388 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3389 break;
3390 }
3cfc3092
JK		 3391 case KVM_GET_VCPU_EVENTS: {
3392 struct kvm_vcpu_events events;
3393
3394 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3395
3396 r = -EFAULT;
3397 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3398 break;
3399 r = 0;
3400 break;
3401 }
3402 case KVM_SET_VCPU_EVENTS: {
3403 struct kvm_vcpu_events events;
3404
3405 r = -EFAULT;
3406 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3407 break;
3408
3409 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3410 break;
3411 }
a1efbe77
JK		 3412 case KVM_GET_DEBUGREGS: {
3413 struct kvm_debugregs dbgregs;
3414
3415 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3416
3417 r = -EFAULT;
3418 if (copy_to_user(argp, &dbgregs,
3419 sizeof(struct kvm_debugregs)))
3420 break;
3421 r = 0;
3422 break;
3423 }
3424 case KVM_SET_DEBUGREGS: {
3425 struct kvm_debugregs dbgregs;
3426
3427 r = -EFAULT;
3428 if (copy_from_user(&dbgregs, argp,
3429 sizeof(struct kvm_debugregs)))
3430 break;
3431
3432 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3433 break;
3434 }
2d5b5a66 3435 case KVM_GET_XSAVE: {
d1ac91d8 3436 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3437 r = -ENOMEM;
d1ac91d8 3438 if (!u.xsave)
2d5b5a66
SY		 3439 break;
3440
d1ac91d8 3441 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3442
3443 r = -EFAULT;
d1ac91d8 3444 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3445 break;
3446 r = 0;
3447 break;
3448 }
3449 case KVM_SET_XSAVE: {
ff5c2c03 3450 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3451 if (IS_ERR(u.xsave))
3452 return PTR_ERR(u.xsave);
2d5b5a66 3453
d1ac91d8 3454 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3455 break;
3456 }
3457 case KVM_GET_XCRS: {
d1ac91d8 3458 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3459 r = -ENOMEM;
d1ac91d8 3460 if (!u.xcrs)
2d5b5a66
SY		 3461 break;
3462
d1ac91d8 3463 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3464
3465 r = -EFAULT;
d1ac91d8 3466 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3467 sizeof(struct kvm_xcrs)))
3468 break;
3469 r = 0;
3470 break;
3471 }
3472 case KVM_SET_XCRS: {
ff5c2c03 3473 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3474 if (IS_ERR(u.xcrs))
3475 return PTR_ERR(u.xcrs);
2d5b5a66 3476
d1ac91d8 3477 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3478 break;
3479 }
92a1f12d
JR		 3480 case KVM_SET_TSC_KHZ: {
3481 u32 user_tsc_khz;
3482
3483 r = -EINVAL;
92a1f12d
JR		 3484 user_tsc_khz = (u32)arg;
3485
3486 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3487 goto out;
3488
cc578287
ZA		 3489 if (user_tsc_khz == 0)
3490 user_tsc_khz = tsc_khz;
3491
381d585c
HZ		 3492 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3493 r = 0;
92a1f12d 3494
92a1f12d
JR		 3495 goto out;
3496 }
3497 case KVM_GET_TSC_KHZ: {
cc578287 3498 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3499 goto out;
3500 }
1c0b28c2
EM		 3501 case KVM_KVMCLOCK_CTRL: {
3502 r = kvm_set_guest_paused(vcpu);
3503 goto out;
3504 }
5c919412
AS		 3505 case KVM_ENABLE_CAP: {
3506 struct kvm_enable_cap cap;
3507
3508 r = -EFAULT;
3509 if (copy_from_user(&cap, argp, sizeof(cap)))
3510 goto out;
3511 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3512 break;
3513 }
313a3dc7
CO		 3514 default:
3515 r = -EINVAL;
3516 }
3517out:
d1ac91d8 3518 kfree(u.buffer);
313a3dc7
CO		 3519 return r;
3520}
3521
5b1c1493
CO		 3522int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3523{
3524 return VM_FAULT_SIGBUS;
3525}
3526
1fe779f8
CO		 3527static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3528{
3529 int ret;
3530
3531 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3532 return -EINVAL;
1fe779f8
CO		 3533 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3534 return ret;
3535}
3536
b927a3ce
SY		 3537static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3538 u64 ident_addr)
3539{
3540 kvm->arch.ept_identity_map_addr = ident_addr;
3541 return 0;
3542}
3543
1fe779f8
CO		 3544static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3545 u32 kvm_nr_mmu_pages)
3546{
3547 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3548 return -EINVAL;
3549
79fac95e 3550 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3551
3552 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3553 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3554
79fac95e 3555 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3556 return 0;
3557}
3558
3559static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3560{
39de71ec 3561 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3562}
3563
1fe779f8
CO		 3564static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3565{
3566 int r;
3567
3568 r = 0;
3569 switch (chip->chip_id) {
3570 case KVM_IRQCHIP_PIC_MASTER:
3571 memcpy(&chip->chip.pic,
3572 &pic_irqchip(kvm)->pics[0],
3573 sizeof(struct kvm_pic_state));
3574 break;
3575 case KVM_IRQCHIP_PIC_SLAVE:
3576 memcpy(&chip->chip.pic,
3577 &pic_irqchip(kvm)->pics[1],
3578 sizeof(struct kvm_pic_state));
3579 break;
3580 case KVM_IRQCHIP_IOAPIC:
eba0226b 3581 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3582 break;
3583 default:
3584 r = -EINVAL;
3585 break;
3586 }
3587 return r;
3588}
3589
3590static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3591{
3592 int r;
3593
3594 r = 0;
3595 switch (chip->chip_id) {
3596 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3597 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3598 memcpy(&pic_irqchip(kvm)->pics[0],
3599 &chip->chip.pic,
3600 sizeof(struct kvm_pic_state));
f4f51050 3601 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3602 break;
3603 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3604 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3605 memcpy(&pic_irqchip(kvm)->pics[1],
3606 &chip->chip.pic,
3607 sizeof(struct kvm_pic_state));
f4f51050 3608 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3609 break;
3610 case KVM_IRQCHIP_IOAPIC:
eba0226b 3611 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3612 break;
3613 default:
3614 r = -EINVAL;
3615 break;
3616 }
3617 kvm_pic_update_irq(pic_irqchip(kvm));
3618 return r;
3619}
3620
e0f63cb9
SY		 3621static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3622{
34f3941c
RK		 3623 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3624
3625 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3626
3627 mutex_lock(&kps->lock);
3628 memcpy(ps, &kps->channels, sizeof(*ps));
3629 mutex_unlock(&kps->lock);
2da29bcc 3630 return 0;
e0f63cb9
SY		 3631}
3632
3633static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3634{
0185604c 3635 int i;
09edea72
RK		 3636 struct kvm_pit *pit = kvm->arch.vpit;
3637
3638 mutex_lock(&pit->pit_state.lock);
34f3941c 3639 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3640 for (i = 0; i < 3; i++)
09edea72
RK		 3641 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3642 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3643 return 0;
e9f42757
BK		 3644}
3645
3646static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3647{
e9f42757
BK		 3648 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3649 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3650 sizeof(ps->channels));
3651 ps->flags = kvm->arch.vpit->pit_state.flags;
3652 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3653 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3654 return 0;
e9f42757
BK		 3655}
3656
3657static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3658{
2da29bcc 3659 int start = 0;
0185604c 3660 int i;
e9f42757 3661 u32 prev_legacy, cur_legacy;
09edea72
RK		 3662 struct kvm_pit *pit = kvm->arch.vpit;
3663
3664 mutex_lock(&pit->pit_state.lock);
3665 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3666 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3667 if (!prev_legacy && cur_legacy)
3668 start = 1;
09edea72
RK		 3669 memcpy(&pit->pit_state.channels, &ps->channels,
3670 sizeof(pit->pit_state.channels));
3671 pit->pit_state.flags = ps->flags;
0185604c 3672 for (i = 0; i < 3; i++)
09edea72 3673 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3674 start && i == 0);
09edea72 3675 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3676 return 0;
e0f63cb9
SY		 3677}
3678
52d939a0
MT		 3679static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3680 struct kvm_reinject_control *control)
3681{
71474e2f
RK		 3682 struct kvm_pit *pit = kvm->arch.vpit;
3683
3684 if (!pit)
52d939a0 3685 return -ENXIO;
b39c90b6 3686
71474e2f
RK		 3687 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3688 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3689 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3690 */
3691 mutex_lock(&pit->pit_state.lock);
3692 kvm_pit_set_reinject(pit, control->pit_reinject);
3693 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3694
52d939a0
MT		 3695 return 0;
3696}
3697
95d4c16c 3698/**
60c34612
TY		 3699 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3700 * @kvm: kvm instance
3701 * @log: slot id and address to which we copy the log
95d4c16c 3702 *
e108ff2f
PB		 3703 * Steps 1-4 below provide general overview of dirty page logging. See
3704 * kvm_get_dirty_log_protect() function description for additional details.
3705 *
3706 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3707 * always flush the TLB (step 4) even if previous step failed and the dirty
3708 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3709 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3710 * writes will be marked dirty for next log read.
95d4c16c 3711 *
60c34612
TY		 3712 * 1. Take a snapshot of the bit and clear it if needed.
3713 * 2. Write protect the corresponding page.
e108ff2f
PB		 3714 * 3. Copy the snapshot to the userspace.
3715 * 4. Flush TLB's if needed.
5bb064dc 3716 */
60c34612 3717int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3718{
60c34612 3719 bool is_dirty = false;
e108ff2f 3720 int r;
5bb064dc 3721
79fac95e 3722 mutex_lock(&kvm->slots_lock);
5bb064dc 3723
88178fd4
KH		 3724 /*
3725 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3726 */
3727 if (kvm_x86_ops->flush_log_dirty)
3728 kvm_x86_ops->flush_log_dirty(kvm);
3729
e108ff2f 3730 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3731
3732 /*
3733 * All the TLBs can be flushed out of mmu lock, see the comments in
3734 * kvm_mmu_slot_remove_write_access().
3735 */
e108ff2f 3736 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3737 if (is_dirty)
3738 kvm_flush_remote_tlbs(kvm);
3739
79fac95e 3740 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3741 return r;
3742}
3743
aa2fbe6d
YZ		 3744int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3745 bool line_status)
23d43cf9
CD		 3746{
3747 if (!irqchip_in_kernel(kvm))
3748 return -ENXIO;
3749
3750 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3751 irq_event->irq, irq_event->level,
3752 line_status);
23d43cf9
CD		 3753 return 0;
3754}
3755
90de4a18
NA		 3756static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3757 struct kvm_enable_cap *cap)
3758{
3759 int r;
3760
3761 if (cap->flags)
3762 return -EINVAL;
3763
3764 switch (cap->cap) {
3765 case KVM_CAP_DISABLE_QUIRKS:
3766 kvm->arch.disabled_quirks = cap->args[0];
3767 r = 0;
3768 break;
49df6397
SR		 3769 case KVM_CAP_SPLIT_IRQCHIP: {
3770 mutex_lock(&kvm->lock);
b053b2ae
SR		 3771 r = -EINVAL;
3772 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3773 goto split_irqchip_unlock;
49df6397
SR		 3774 r = -EEXIST;
3775 if (irqchip_in_kernel(kvm))
3776 goto split_irqchip_unlock;
3777 if (atomic_read(&kvm->online_vcpus))
3778 goto split_irqchip_unlock;
3779 r = kvm_setup_empty_irq_routing(kvm);
3780 if (r)
3781 goto split_irqchip_unlock;
3782 /* Pairs with irqchip_in_kernel. */
3783 smp_wmb();
3784 kvm->arch.irqchip_split = true;
b053b2ae 3785 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3786 r = 0;
3787split_irqchip_unlock:
3788 mutex_unlock(&kvm->lock);
3789 break;
3790 }
90de4a18
NA		 3791 default:
3792 r = -EINVAL;
3793 break;
3794 }
3795 return r;
3796}
3797
1fe779f8
CO		 3798long kvm_arch_vm_ioctl(struct file *filp,
3799 unsigned int ioctl, unsigned long arg)
3800{
3801 struct kvm *kvm = filp->private_data;
3802 void __user *argp = (void __user *)arg;
367e1319 3803 int r = -ENOTTY;
f0d66275
DH		 3804 /*
3805 * This union makes it completely explicit to gcc-3.x
3806 * that these two variables' stack usage should be
3807 * combined, not added together.
3808 */
3809 union {
3810 struct kvm_pit_state ps;
e9f42757 3811 struct kvm_pit_state2 ps2;
c5ff41ce 3812 struct kvm_pit_config pit_config;
f0d66275 3813 } u;
1fe779f8
CO		 3814
3815 switch (ioctl) {
3816 case KVM_SET_TSS_ADDR:
3817 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3818 break;
b927a3ce
SY		 3819 case KVM_SET_IDENTITY_MAP_ADDR: {
3820 u64 ident_addr;
3821
3822 r = -EFAULT;
3823 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3824 goto out;
3825 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3826 break;
3827 }
1fe779f8
CO		 3828 case KVM_SET_NR_MMU_PAGES:
3829 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3830 break;
3831 case KVM_GET_NR_MMU_PAGES:
3832 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3833 break;
3ddea128
MT		 3834 case KVM_CREATE_IRQCHIP: {
3835 struct kvm_pic *vpic;
3836
3837 mutex_lock(&kvm->lock);
3838 r = -EEXIST;
3839 if (kvm->arch.vpic)
3840 goto create_irqchip_unlock;
3e515705
AK		 3841 r = -EINVAL;
3842 if (atomic_read(&kvm->online_vcpus))
3843 goto create_irqchip_unlock;
1fe779f8 3844 r = -ENOMEM;
3ddea128
MT		 3845 vpic = kvm_create_pic(kvm);
3846 if (vpic) {
1fe779f8
CO		 3847 r = kvm_ioapic_init(kvm);
3848 if (r) {
175504cd 3849 mutex_lock(&kvm->slots_lock);
71ba994c 3850 kvm_destroy_pic(vpic);
175504cd 3851 mutex_unlock(&kvm->slots_lock);
3ddea128 3852 goto create_irqchip_unlock;
1fe779f8
CO		 3853 }
3854 } else
3ddea128 3855 goto create_irqchip_unlock;
399ec807
AK		 3856 r = kvm_setup_default_irq_routing(kvm);
3857 if (r) {
175504cd 3858 mutex_lock(&kvm->slots_lock);
3ddea128 3859 mutex_lock(&kvm->irq_lock);
72bb2fcd 3860 kvm_ioapic_destroy(kvm);
71ba994c 3861 kvm_destroy_pic(vpic);
3ddea128 3862 mutex_unlock(&kvm->irq_lock);
175504cd 3863 mutex_unlock(&kvm->slots_lock);
71ba994c 3864 goto create_irqchip_unlock;
399ec807 3865 }
71ba994c
PB		 3866 /* Write kvm->irq_routing before kvm->arch.vpic. */
3867 smp_wmb();
3868 kvm->arch.vpic = vpic;
3ddea128
MT		 3869 create_irqchip_unlock:
3870 mutex_unlock(&kvm->lock);
1fe779f8 3871 break;
3ddea128 3872 }
7837699f 3873 case KVM_CREATE_PIT:
c5ff41ce
JK		 3874 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3875 goto create_pit;
3876 case KVM_CREATE_PIT2:
3877 r = -EFAULT;
3878 if (copy_from_user(&u.pit_config, argp,
3879 sizeof(struct kvm_pit_config)))
3880 goto out;
3881 create_pit:
250715a6 3882 mutex_lock(&kvm->lock);
269e05e4
AK		 3883 r = -EEXIST;
3884 if (kvm->arch.vpit)
3885 goto create_pit_unlock;
7837699f 3886 r = -ENOMEM;
c5ff41ce 3887 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3888 if (kvm->arch.vpit)
3889 r = 0;
269e05e4 3890 create_pit_unlock:
250715a6 3891 mutex_unlock(&kvm->lock);
7837699f 3892 break;
1fe779f8
CO		 3893 case KVM_GET_IRQCHIP: {
3894 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3895 struct kvm_irqchip *chip;
1fe779f8 3896
ff5c2c03
SL		 3897 chip = memdup_user(argp, sizeof(*chip));
3898 if (IS_ERR(chip)) {
3899 r = PTR_ERR(chip);
1fe779f8 3900 goto out;
ff5c2c03
SL		 3901 }
3902
1fe779f8 3903 r = -ENXIO;
49df6397 3904 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3905 goto get_irqchip_out;
3906 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3907 if (r)
f0d66275 3908 goto get_irqchip_out;
1fe779f8 3909 r = -EFAULT;
f0d66275
DH		 3910 if (copy_to_user(argp, chip, sizeof *chip))
3911 goto get_irqchip_out;
1fe779f8 3912 r = 0;
f0d66275
DH		 3913 get_irqchip_out:
3914 kfree(chip);
1fe779f8
CO		 3915 break;
3916 }
3917 case KVM_SET_IRQCHIP: {
3918 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3919 struct kvm_irqchip *chip;
1fe779f8 3920
ff5c2c03
SL		 3921 chip = memdup_user(argp, sizeof(*chip));
3922 if (IS_ERR(chip)) {
3923 r = PTR_ERR(chip);
1fe779f8 3924 goto out;
ff5c2c03
SL		 3925 }
3926
1fe779f8 3927 r = -ENXIO;
49df6397 3928 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3929 goto set_irqchip_out;
3930 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3931 if (r)
f0d66275 3932 goto set_irqchip_out;
1fe779f8 3933 r = 0;
f0d66275
DH		 3934 set_irqchip_out:
3935 kfree(chip);
1fe779f8
CO		 3936 break;
3937 }
e0f63cb9 3938 case KVM_GET_PIT: {
e0f63cb9 3939 r = -EFAULT;
f0d66275 3940 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3941 goto out;
3942 r = -ENXIO;
3943 if (!kvm->arch.vpit)
3944 goto out;
f0d66275 3945 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3946 if (r)
3947 goto out;
3948 r = -EFAULT;
f0d66275 3949 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3950 goto out;
3951 r = 0;
3952 break;
3953 }
3954 case KVM_SET_PIT: {
e0f63cb9 3955 r = -EFAULT;
f0d66275 3956 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3957 goto out;
3958 r = -ENXIO;
3959 if (!kvm->arch.vpit)
3960 goto out;
f0d66275 3961 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3962 break;
3963 }
e9f42757
BK		 3964 case KVM_GET_PIT2: {
3965 r = -ENXIO;
3966 if (!kvm->arch.vpit)
3967 goto out;
3968 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3969 if (r)
3970 goto out;
3971 r = -EFAULT;
3972 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3973 goto out;
3974 r = 0;
3975 break;
3976 }
3977 case KVM_SET_PIT2: {
3978 r = -EFAULT;
3979 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3980 goto out;
3981 r = -ENXIO;
3982 if (!kvm->arch.vpit)
3983 goto out;
3984 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3985 break;
3986 }
52d939a0
MT		 3987 case KVM_REINJECT_CONTROL: {
3988 struct kvm_reinject_control control;
3989 r = -EFAULT;
3990 if (copy_from_user(&control, argp, sizeof(control)))
3991 goto out;
3992 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3993 break;
3994 }
d71ba788
PB		 3995 case KVM_SET_BOOT_CPU_ID:
3996 r = 0;
3997 mutex_lock(&kvm->lock);
3998 if (atomic_read(&kvm->online_vcpus) != 0)
3999 r = -EBUSY;
4000 else
4001 kvm->arch.bsp_vcpu_id = arg;
4002 mutex_unlock(&kvm->lock);
4003 break;
ffde22ac
ES		 4004 case KVM_XEN_HVM_CONFIG: {
4005 r = -EFAULT;
4006 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4007 sizeof(struct kvm_xen_hvm_config)))
4008 goto out;
4009 r = -EINVAL;
4010 if (kvm->arch.xen_hvm_config.flags)
4011 goto out;
4012 r = 0;
4013 break;
4014 }
afbcf7ab 4015 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4016 struct kvm_clock_data user_ns;
4017 u64 now_ns;
4018 s64 delta;
4019
4020 r = -EFAULT;
4021 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4022 goto out;
4023
4024 r = -EINVAL;
4025 if (user_ns.flags)
4026 goto out;
4027
4028 r = 0;
395c6b0a 4029 local_irq_disable();
759379dd 4030 now_ns = get_kernel_ns();
afbcf7ab 4031 delta = user_ns.clock - now_ns;
395c6b0a 4032 local_irq_enable();
afbcf7ab 4033 kvm->arch.kvmclock_offset = delta;
2e762ff7 4034 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4035 break;
4036 }
4037 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4038 struct kvm_clock_data user_ns;
4039 u64 now_ns;
4040
395c6b0a 4041 local_irq_disable();
759379dd 4042 now_ns = get_kernel_ns();
afbcf7ab 4043 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4044 local_irq_enable();
afbcf7ab 4045 user_ns.flags = 0;
97e69aa6 4046 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4047
4048 r = -EFAULT;
4049 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4050 goto out;
4051 r = 0;
4052 break;
4053 }
90de4a18
NA		 4054 case KVM_ENABLE_CAP: {
4055 struct kvm_enable_cap cap;
afbcf7ab 4056
90de4a18
NA		 4057 r = -EFAULT;
4058 if (copy_from_user(&cap, argp, sizeof(cap)))
4059 goto out;
4060 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4061 break;
4062 }
1fe779f8 4063 default:
c274e03a 4064 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4065 }
4066out:
4067 return r;
4068}
4069
a16b043c 4070static void kvm_init_msr_list(void)
043405e1
CO		 4071{
4072 u32 dummy[2];
4073 unsigned i, j;
4074
62ef68bb 4075 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4076 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4077 continue;
93c4adc7
PB		 4078
4079 /*
4080 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4081 * to the guests in some cases.
93c4adc7
PB		 4082 */
4083 switch (msrs_to_save[i]) {
4084 case MSR_IA32_BNDCFGS:
4085 if (!kvm_x86_ops->mpx_supported())
4086 continue;
4087 break;
9dbe6cf9
PB		 4088 case MSR_TSC_AUX:
4089 if (!kvm_x86_ops->rdtscp_supported())
4090 continue;
4091 break;
93c4adc7
PB		 4092 default:
4093 break;
4094 }
4095
043405e1
CO		 4096 if (j < i)
4097 msrs_to_save[j] = msrs_to_save[i];
4098 j++;
4099 }
4100 num_msrs_to_save = j;
62ef68bb
PB		 4101
4102 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4103 switch (emulated_msrs[i]) {
6d396b55
PB		 4104 case MSR_IA32_SMBASE:
4105 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4106 continue;
4107 break;
62ef68bb
PB		 4108 default:
4109 break;
4110 }
4111
4112 if (j < i)
4113 emulated_msrs[j] = emulated_msrs[i];
4114 j++;
4115 }
4116 num_emulated_msrs = j;
043405e1
CO		 4117}
4118
bda9020e
MT		 4119static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4120 const void *v)
bbd9b64e 4121{
70252a10
AK		 4122 int handled = 0;
4123 int n;
4124
4125 do {
4126 n = min(len, 8);
bce87cce 4127 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4128 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4129 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4130 break;
4131 handled += n;
4132 addr += n;
4133 len -= n;
4134 v += n;
4135 } while (len);
bbd9b64e 4136
70252a10 4137 return handled;
bbd9b64e
CO		 4138}
4139
bda9020e 4140static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4141{
70252a10
AK		 4142 int handled = 0;
4143 int n;
4144
4145 do {
4146 n = min(len, 8);
bce87cce 4147 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4148 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4149 addr, n, v))
4150 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4151 break;
4152 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4153 handled += n;
4154 addr += n;
4155 len -= n;
4156 v += n;
4157 } while (len);
bbd9b64e 4158
70252a10 4159 return handled;
bbd9b64e
CO		 4160}
4161
2dafc6c2
GN		 4162static void kvm_set_segment(struct kvm_vcpu *vcpu,
4163 struct kvm_segment *var, int seg)
4164{
4165 kvm_x86_ops->set_segment(vcpu, var, seg);
4166}
4167
4168void kvm_get_segment(struct kvm_vcpu *vcpu,
4169 struct kvm_segment *var, int seg)
4170{
4171 kvm_x86_ops->get_segment(vcpu, var, seg);
4172}
4173
54987b7a
PB		 4174gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4175 struct x86_exception *exception)
02f59dc9
JR		 4176{
4177 gpa_t t_gpa;
02f59dc9
JR		 4178
4179 BUG_ON(!mmu_is_nested(vcpu));
4180
4181 /* NPT walks are always user-walks */
4182 access |= PFERR_USER_MASK;
54987b7a 4183 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4184
4185 return t_gpa;
4186}
4187
ab9ae313
AK		 4188gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4189 struct x86_exception *exception)
1871c602
GN		 4190{
4191 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4192 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4193}
4194
ab9ae313
AK		 4195 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4196 struct x86_exception *exception)
1871c602
GN		 4197{
4198 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4199 access |= PFERR_FETCH_MASK;
ab9ae313 4200 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4201}
4202
ab9ae313
AK		 4203gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4204 struct x86_exception *exception)
1871c602
GN		 4205{
4206 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4207 access |= PFERR_WRITE_MASK;
ab9ae313 4208 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4209}
4210
4211/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4212gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4213 struct x86_exception *exception)
1871c602 4214{
ab9ae313 4215 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4216}
4217
4218static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4219 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4220 struct x86_exception *exception)
bbd9b64e
CO		 4221{
4222 void *data = val;
10589a46 4223 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4224
4225 while (bytes) {
14dfe855 4226 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4227 exception);
bbd9b64e 4228 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4229 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4230 int ret;
4231
bcc55cba 4232 if (gpa == UNMAPPED_GVA)
ab9ae313 4233 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4234 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4235 offset, toread);
10589a46 4236 if (ret < 0) {
c3cd7ffa 4237 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4238 goto out;
4239 }
bbd9b64e 4240
77c2002e
IE		 4241 bytes -= toread;
4242 data += toread;
4243 addr += toread;
bbd9b64e 4244 }
10589a46 4245out:
10589a46 4246 return r;
bbd9b64e 4247}
77c2002e 4248
1871c602 4249/* used for instruction fetching */
0f65dd70
AK		 4250static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4251 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4252 struct x86_exception *exception)
1871c602 4253{
0f65dd70 4254 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4255 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4256 unsigned offset;
4257 int ret;
0f65dd70 4258
44583cba
PB		 4259 /* Inline kvm_read_guest_virt_helper for speed. */
4260 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4261 exception);
4262 if (unlikely(gpa == UNMAPPED_GVA))
4263 return X86EMUL_PROPAGATE_FAULT;
4264
4265 offset = addr & (PAGE_SIZE-1);
4266 if (WARN_ON(offset + bytes > PAGE_SIZE))
4267 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4268 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4269 offset, bytes);
44583cba
PB		 4270 if (unlikely(ret < 0))
4271 return X86EMUL_IO_NEEDED;
4272
4273 return X86EMUL_CONTINUE;
1871c602
GN		 4274}
4275
064aea77 4276int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4277 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4278 struct x86_exception *exception)
1871c602 4279{
0f65dd70 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4281 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4282
1871c602 4283 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4284 exception);
1871c602 4285}
064aea77 4286EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4287
0f65dd70
AK		 4288static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4289 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4290 struct x86_exception *exception)
1871c602 4291{
0f65dd70 4292 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4293 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4294}
4295
7a036a6f
RK		 4296static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4297 unsigned long addr, void *val, unsigned int bytes)
4298{
4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4300 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4301
4302 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4303}
4304
6a4d7550 4305int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4306 gva_t addr, void *val,
2dafc6c2 4307 unsigned int bytes,
bcc55cba 4308 struct x86_exception *exception)
77c2002e 4309{
0f65dd70 4310 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4311 void *data = val;
4312 int r = X86EMUL_CONTINUE;
4313
4314 while (bytes) {
14dfe855
JR		 4315 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4316 PFERR_WRITE_MASK,
ab9ae313 4317 exception);
77c2002e
IE		 4318 unsigned offset = addr & (PAGE_SIZE-1);
4319 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4320 int ret;
4321
bcc55cba 4322 if (gpa == UNMAPPED_GVA)
ab9ae313 4323 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4324 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4325 if (ret < 0) {
c3cd7ffa 4326 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4327 goto out;
4328 }
4329
4330 bytes -= towrite;
4331 data += towrite;
4332 addr += towrite;
4333 }
4334out:
4335 return r;
4336}
6a4d7550 4337EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4338
af7cc7d1
XG		 4339static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4340 gpa_t *gpa, struct x86_exception *exception,
4341 bool write)
4342{
97d64b78
AK		 4343 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4344 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4345
be94f6b7
HH		 4346 /*
4347 * currently PKRU is only applied to ept enabled guest so
4348 * there is no pkey in EPT page table for L1 guest or EPT
4349 * shadow page table for L2 guest.
4350 */
97d64b78 4351 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4352 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4353 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4354 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4355 (gva & (PAGE_SIZE - 1));
4f022648 4356 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4357 return 1;
4358 }
4359
af7cc7d1
XG		 4360 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4361
4362 if (*gpa == UNMAPPED_GVA)
4363 return -1;
4364
4365 /* For APIC access vmexit */
4366 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4367 return 1;
4368
4f022648
XG		 4369 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4370 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4371 return 1;
4f022648 4372 }
bebb106a 4373
af7cc7d1
XG		 4374 return 0;
4375}
4376
3200f405 4377int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4378 const void *val, int bytes)
bbd9b64e
CO		 4379{
4380 int ret;
4381
54bf36aa 4382 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4383 if (ret < 0)
bbd9b64e 4384 return 0;
0eb05bf2 4385 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4386 return 1;
4387}
4388
77d197b2
XG		 4389struct read_write_emulator_ops {
4390 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4391 int bytes);
4392 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4393 void *val, int bytes);
4394 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4395 int bytes, void *val);
4396 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4397 void *val, int bytes);
4398 bool write;
4399};
4400
4401static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4402{
4403 if (vcpu->mmio_read_completed) {
77d197b2 4404 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4405 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4406 vcpu->mmio_read_completed = 0;
4407 return 1;
4408 }
4409
4410 return 0;
4411}
4412
4413static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4415{
54bf36aa 4416 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4417}
4418
4419static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4420 void *val, int bytes)
4421{
4422 return emulator_write_phys(vcpu, gpa, val, bytes);
4423}
4424
4425static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4426{
4427 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4428 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4429}
4430
4431static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4432 void *val, int bytes)
4433{
4434 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4435 return X86EMUL_IO_NEEDED;
4436}
4437
4438static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4439 void *val, int bytes)
4440{
f78146b0
AK		 4441 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4442
87da7e66 4443 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4444 return X86EMUL_CONTINUE;
4445}
4446
0fbe9b0b 4447static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4448 .read_write_prepare = read_prepare,
4449 .read_write_emulate = read_emulate,
4450 .read_write_mmio = vcpu_mmio_read,
4451 .read_write_exit_mmio = read_exit_mmio,
4452};
4453
0fbe9b0b 4454static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4455 .read_write_emulate = write_emulate,
4456 .read_write_mmio = write_mmio,
4457 .read_write_exit_mmio = write_exit_mmio,
4458 .write = true,
4459};
4460
22388a3c
XG		 4461static int emulator_read_write_onepage(unsigned long addr, void *val,
4462 unsigned int bytes,
4463 struct x86_exception *exception,
4464 struct kvm_vcpu *vcpu,
0fbe9b0b 4465 const struct read_write_emulator_ops *ops)
bbd9b64e 4466{
af7cc7d1
XG		 4467 gpa_t gpa;
4468 int handled, ret;
22388a3c 4469 bool write = ops->write;
f78146b0 4470 struct kvm_mmio_fragment *frag;
10589a46 4471
22388a3c 4472 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4473
af7cc7d1 4474 if (ret < 0)
bbd9b64e 4475 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4476
4477 /* For APIC access vmexit */
af7cc7d1 4478 if (ret)
bbd9b64e
CO		 4479 goto mmio;
4480
22388a3c 4481 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4482 return X86EMUL_CONTINUE;
4483
4484mmio:
4485 /*
4486 * Is this MMIO handled locally?
4487 */
22388a3c 4488 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4489 if (handled == bytes)
bbd9b64e 4490 return X86EMUL_CONTINUE;
bbd9b64e 4491
70252a10
AK		 4492 gpa += handled;
4493 bytes -= handled;
4494 val += handled;
4495
87da7e66
XG		 4496 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4497 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4498 frag->gpa = gpa;
4499 frag->data = val;
4500 frag->len = bytes;
f78146b0 4501 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4502}
4503
52eb5a6d
XL		 4504static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4505 unsigned long addr,
22388a3c
XG		 4506 void *val, unsigned int bytes,
4507 struct x86_exception *exception,
0fbe9b0b 4508 const struct read_write_emulator_ops *ops)
bbd9b64e 4509{
0f65dd70 4510 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4511 gpa_t gpa;
4512 int rc;
4513
4514 if (ops->read_write_prepare &&
4515 ops->read_write_prepare(vcpu, val, bytes))
4516 return X86EMUL_CONTINUE;
4517
4518 vcpu->mmio_nr_fragments = 0;
0f65dd70 4519
bbd9b64e
CO		 4520 /* Crossing a page boundary? */
4521 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4522 int now;
bbd9b64e
CO		 4523
4524 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4525 rc = emulator_read_write_onepage(addr, val, now, exception,
4526 vcpu, ops);
4527
bbd9b64e
CO		 4528 if (rc != X86EMUL_CONTINUE)
4529 return rc;
4530 addr += now;
bac15531
NA		 4531 if (ctxt->mode != X86EMUL_MODE_PROT64)
4532 addr = (u32)addr;
bbd9b64e
CO		 4533 val += now;
4534 bytes -= now;
4535 }
22388a3c 4536
f78146b0
AK		 4537 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4538 vcpu, ops);
4539 if (rc != X86EMUL_CONTINUE)
4540 return rc;
4541
4542 if (!vcpu->mmio_nr_fragments)
4543 return rc;
4544
4545 gpa = vcpu->mmio_fragments[0].gpa;
4546
4547 vcpu->mmio_needed = 1;
4548 vcpu->mmio_cur_fragment = 0;
4549
87da7e66 4550 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4551 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4552 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4553 vcpu->run->mmio.phys_addr = gpa;
4554
4555 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4556}
4557
4558static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4559 unsigned long addr,
4560 void *val,
4561 unsigned int bytes,
4562 struct x86_exception *exception)
4563{
4564 return emulator_read_write(ctxt, addr, val, bytes,
4565 exception, &read_emultor);
4566}
4567
52eb5a6d 4568static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4569 unsigned long addr,
4570 const void *val,
4571 unsigned int bytes,
4572 struct x86_exception *exception)
4573{
4574 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4575 exception, &write_emultor);
bbd9b64e 4576}
bbd9b64e 4577
daea3e73
AK		 4578#define CMPXCHG_TYPE(t, ptr, old, new) \
4579 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4580
4581#ifdef CONFIG_X86_64
4582# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4583#else
4584# define CMPXCHG64(ptr, old, new) \
9749a6c0 4585 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4586#endif
4587
0f65dd70
AK		 4588static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4589 unsigned long addr,
bbd9b64e
CO		 4590 const void *old,
4591 const void *new,
4592 unsigned int bytes,
0f65dd70 4593 struct x86_exception *exception)
bbd9b64e 4594{
0f65dd70 4595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4596 gpa_t gpa;
4597 struct page *page;
4598 char *kaddr;
4599 bool exchanged;
2bacc55c 4600
daea3e73
AK		 4601 /* guests cmpxchg8b have to be emulated atomically */
4602 if (bytes > 8 || (bytes & (bytes - 1)))
4603 goto emul_write;
10589a46 4604
daea3e73 4605 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4606
daea3e73
AK		 4607 if (gpa == UNMAPPED_GVA ||
4608 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4609 goto emul_write;
2bacc55c 4610
daea3e73
AK		 4611 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4612 goto emul_write;
72dc67a6 4613
54bf36aa 4614 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4615 if (is_error_page(page))
c19b8bd6 4616 goto emul_write;
72dc67a6 4617
8fd75e12 4618 kaddr = kmap_atomic(page);
daea3e73
AK		 4619 kaddr += offset_in_page(gpa);
4620 switch (bytes) {
4621 case 1:
4622 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4623 break;
4624 case 2:
4625 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4626 break;
4627 case 4:
4628 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4629 break;
4630 case 8:
4631 exchanged = CMPXCHG64(kaddr, old, new);
4632 break;
4633 default:
4634 BUG();
2bacc55c 4635 }
8fd75e12 4636 kunmap_atomic(kaddr);
daea3e73
AK		 4637 kvm_release_page_dirty(page);
4638
4639 if (!exchanged)
4640 return X86EMUL_CMPXCHG_FAILED;
4641
54bf36aa 4642 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4643 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4644
4645 return X86EMUL_CONTINUE;
4a5f48f6 4646
3200f405 4647emul_write:
daea3e73 4648 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4649
0f65dd70 4650 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4651}
4652
cf8f70bf
GN		 4653static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4654{
4655 /* TODO: String I/O for in kernel device */
4656 int r;
4657
4658 if (vcpu->arch.pio.in)
e32edf4f 4659 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4660 vcpu->arch.pio.size, pd);
4661 else
e32edf4f 4662 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4663 vcpu->arch.pio.port, vcpu->arch.pio.size,
4664 pd);
4665 return r;
4666}
4667
6f6fbe98
XG		 4668static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4669 unsigned short port, void *val,
4670 unsigned int count, bool in)
cf8f70bf 4671{
cf8f70bf 4672 vcpu->arch.pio.port = port;
6f6fbe98 4673 vcpu->arch.pio.in = in;
7972995b 4674 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4675 vcpu->arch.pio.size = size;
4676
4677 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4678 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4679 return 1;
4680 }
4681
4682 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4683 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4684 vcpu->run->io.size = size;
4685 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4686 vcpu->run->io.count = count;
4687 vcpu->run->io.port = port;
4688
4689 return 0;
4690}
4691
6f6fbe98
XG		 4692static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4693 int size, unsigned short port, void *val,
4694 unsigned int count)
cf8f70bf 4695{
ca1d4a9e 4696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4697 int ret;
ca1d4a9e 4698
6f6fbe98
XG		 4699 if (vcpu->arch.pio.count)
4700 goto data_avail;
cf8f70bf 4701
6f6fbe98
XG		 4702 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4703 if (ret) {
4704data_avail:
4705 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4706 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4707 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4708 return 1;
4709 }
4710
cf8f70bf
GN		 4711 return 0;
4712}
4713
6f6fbe98
XG		 4714static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4715 int size, unsigned short port,
4716 const void *val, unsigned int count)
4717{
4718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4719
4720 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4721 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4722 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4723}
4724
bbd9b64e
CO		 4725static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4726{
4727 return kvm_x86_ops->get_segment_base(vcpu, seg);
4728}
4729
3cb16fe7 4730static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4731{
3cb16fe7 4732 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4733}
4734
5cb56059 4735int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4736{
4737 if (!need_emulate_wbinvd(vcpu))
4738 return X86EMUL_CONTINUE;
4739
4740 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4741 int cpu = get_cpu();
4742
4743 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4744 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4745 wbinvd_ipi, NULL, 1);
2eec7343 4746 put_cpu();
f5f48ee1 4747 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4748 } else
4749 wbinvd();
f5f48ee1
SY		 4750 return X86EMUL_CONTINUE;
4751}
5cb56059
JS		 4752
4753int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4754{
4755 kvm_x86_ops->skip_emulated_instruction(vcpu);
4756 return kvm_emulate_wbinvd_noskip(vcpu);
4757}
f5f48ee1
SY		 4758EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4759
5cb56059
JS		 4760
4761
bcaf5cc5
AK		 4762static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4763{
5cb56059 4764 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4765}
4766
52eb5a6d
XL		 4767static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4768 unsigned long *dest)
bbd9b64e 4769{
16f8a6f9 4770 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4771}
4772
52eb5a6d
XL		 4773static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4774 unsigned long value)
bbd9b64e 4775{
338dbc97 4776
717746e3 4777 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4778}
4779
52a46617 4780static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4781{
52a46617 4782 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4783}
4784
717746e3 4785static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4786{
717746e3 4787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4788 unsigned long value;
4789
4790 switch (cr) {
4791 case 0:
4792 value = kvm_read_cr0(vcpu);
4793 break;
4794 case 2:
4795 value = vcpu->arch.cr2;
4796 break;
4797 case 3:
9f8fe504 4798 value = kvm_read_cr3(vcpu);
52a46617
GN		 4799 break;
4800 case 4:
4801 value = kvm_read_cr4(vcpu);
4802 break;
4803 case 8:
4804 value = kvm_get_cr8(vcpu);
4805 break;
4806 default:
a737f256 4807 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4808 return 0;
4809 }
4810
4811 return value;
4812}
4813
717746e3 4814static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4815{
717746e3 4816 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4817 int res = 0;
4818
52a46617
GN		 4819 switch (cr) {
4820 case 0:
49a9b07e 4821 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4822 break;
4823 case 2:
4824 vcpu->arch.cr2 = val;
4825 break;
4826 case 3:
2390218b 4827 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4828 break;
4829 case 4:
a83b29c6 4830 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4831 break;
4832 case 8:
eea1cff9 4833 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4834 break;
4835 default:
a737f256 4836 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4837 res = -1;
52a46617 4838 }
0f12244f
GN		 4839
4840 return res;
52a46617
GN		 4841}
4842
717746e3 4843static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4844{
717746e3 4845 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4846}
4847
4bff1e86 4848static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4849{
4bff1e86 4850 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4851}
4852
4bff1e86 4853static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4854{
4bff1e86 4855 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4856}
4857
1ac9d0cf
AK		 4858static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4859{
4860 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4861}
4862
4863static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4864{
4865 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4866}
4867
4bff1e86
AK		 4868static unsigned long emulator_get_cached_segment_base(
4869 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4870{
4bff1e86 4871 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4872}
4873
1aa36616
AK		 4874static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4875 struct desc_struct *desc, u32 *base3,
4876 int seg)
2dafc6c2
GN		 4877{
4878 struct kvm_segment var;
4879
4bff1e86 4880 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4881 *selector = var.selector;
2dafc6c2 4882
378a8b09
GN		 4883 if (var.unusable) {
4884 memset(desc, 0, sizeof(*desc));
2dafc6c2 4885 return false;
378a8b09 4886 }
2dafc6c2
GN		 4887
4888 if (var.g)
4889 var.limit >>= 12;
4890 set_desc_limit(desc, var.limit);
4891 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4892#ifdef CONFIG_X86_64
4893 if (base3)
4894 *base3 = var.base >> 32;
4895#endif
2dafc6c2
GN		 4896 desc->type = var.type;
4897 desc->s = var.s;
4898 desc->dpl = var.dpl;
4899 desc->p = var.present;
4900 desc->avl = var.avl;
4901 desc->l = var.l;
4902 desc->d = var.db;
4903 desc->g = var.g;
4904
4905 return true;
4906}
4907
1aa36616
AK		 4908static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4909 struct desc_struct *desc, u32 base3,
4910 int seg)
2dafc6c2 4911{
4bff1e86 4912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4913 struct kvm_segment var;
4914
1aa36616 4915 var.selector = selector;
2dafc6c2 4916 var.base = get_desc_base(desc);
5601d05b
GN		 4917#ifdef CONFIG_X86_64
4918 var.base |= ((u64)base3) << 32;
4919#endif
2dafc6c2
GN		 4920 var.limit = get_desc_limit(desc);
4921 if (desc->g)
4922 var.limit = (var.limit << 12) | 0xfff;
4923 var.type = desc->type;
2dafc6c2
GN		 4924 var.dpl = desc->dpl;
4925 var.db = desc->d;
4926 var.s = desc->s;
4927 var.l = desc->l;
4928 var.g = desc->g;
4929 var.avl = desc->avl;
4930 var.present = desc->p;
4931 var.unusable = !var.present;
4932 var.padding = 0;
4933
4934 kvm_set_segment(vcpu, &var, seg);
4935 return;
4936}
4937
717746e3
AK		 4938static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4939 u32 msr_index, u64 *pdata)
4940{
609e36d3
PB		 4941 struct msr_data msr;
4942 int r;
4943
4944 msr.index = msr_index;
4945 msr.host_initiated = false;
4946 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4947 if (r)
4948 return r;
4949
4950 *pdata = msr.data;
4951 return 0;
717746e3
AK		 4952}
4953
4954static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4955 u32 msr_index, u64 data)
4956{
8fe8ab46
WA		 4957 struct msr_data msr;
4958
4959 msr.data = data;
4960 msr.index = msr_index;
4961 msr.host_initiated = false;
4962 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4963}
4964
64d60670
PB		 4965static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4966{
4967 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4968
4969 return vcpu->arch.smbase;
4970}
4971
4972static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4973{
4974 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4975
4976 vcpu->arch.smbase = smbase;
4977}
4978
67f4d428
NA		 4979static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4980 u32 pmc)
4981{
c6702c9d 4982 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4983}
4984
222d21aa
AK		 4985static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4986 u32 pmc, u64 *pdata)
4987{
c6702c9d 4988 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4989}
4990
6c3287f7
AK		 4991static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4992{
4993 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4994}
4995
5037f6f3
AK		 4996static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4997{
4998 preempt_disable();
5197b808 4999 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5000 /*
5001 * CR0.TS may reference the host fpu state, not the guest fpu state,
5002 * so it may be clear at this point.
5003 */
5004 clts();
5005}
5006
5007static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5008{
5009 preempt_enable();
5010}
5011
2953538e 5012static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5013 struct x86_instruction_info *info,
c4f035c6
AK		 5014 enum x86_intercept_stage stage)
5015{
2953538e 5016 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5017}
5018
0017f93a 5019static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5020 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5021{
0017f93a 5022 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5023}
5024
dd856efa
AK		 5025static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5026{
5027 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5028}
5029
5030static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5031{
5032 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5033}
5034
801806d9
NA		 5035static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5036{
5037 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5038}
5039
0225fb50 5040static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5041 .read_gpr = emulator_read_gpr,
5042 .write_gpr = emulator_write_gpr,
1871c602 5043 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5044 .write_std = kvm_write_guest_virt_system,
7a036a6f 5045 .read_phys = kvm_read_guest_phys_system,
1871c602 5046 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5047 .read_emulated = emulator_read_emulated,
5048 .write_emulated = emulator_write_emulated,
5049 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5050 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5051 .pio_in_emulated = emulator_pio_in_emulated,
5052 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5053 .get_segment = emulator_get_segment,
5054 .set_segment = emulator_set_segment,
5951c442 5055 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5056 .get_gdt = emulator_get_gdt,
160ce1f1 5057 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5058 .set_gdt = emulator_set_gdt,
5059 .set_idt = emulator_set_idt,
52a46617
GN		 5060 .get_cr = emulator_get_cr,
5061 .set_cr = emulator_set_cr,
9c537244 5062 .cpl = emulator_get_cpl,
35aa5375
GN		 5063 .get_dr = emulator_get_dr,
5064 .set_dr = emulator_set_dr,
64d60670
PB		 5065 .get_smbase = emulator_get_smbase,
5066 .set_smbase = emulator_set_smbase,
717746e3
AK		 5067 .set_msr = emulator_set_msr,
5068 .get_msr = emulator_get_msr,
67f4d428 5069 .check_pmc = emulator_check_pmc,
222d21aa 5070 .read_pmc = emulator_read_pmc,
6c3287f7 5071 .halt = emulator_halt,
bcaf5cc5 5072 .wbinvd = emulator_wbinvd,
d6aa1000 5073 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5074 .get_fpu = emulator_get_fpu,
5075 .put_fpu = emulator_put_fpu,
c4f035c6 5076 .intercept = emulator_intercept,
bdb42f5a 5077 .get_cpuid = emulator_get_cpuid,
801806d9 5078 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5079};
5080
95cb2295
GN		 5081static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5082{
37ccdcbe 5083 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5084 /*
5085 * an sti; sti; sequence only disable interrupts for the first
5086 * instruction. So, if the last instruction, be it emulated or
5087 * not, left the system with the INT_STI flag enabled, it
5088 * means that the last instruction is an sti. We should not
5089 * leave the flag on in this case. The same goes for mov ss
5090 */
37ccdcbe
PB		 5091 if (int_shadow & mask)
5092 mask = 0;
6addfc42 5093 if (unlikely(int_shadow || mask)) {
95cb2295 5094 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5095 if (!mask)
5096 kvm_make_request(KVM_REQ_EVENT, vcpu);
5097 }
95cb2295
GN		 5098}
5099
ef54bcfe 5100static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5101{
5102 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5103 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5104 return kvm_propagate_fault(vcpu, &ctxt->exception);
5105
5106 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5107 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5108 ctxt->exception.error_code);
54b8486f 5109 else
da9cb575 5110 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5111 return false;
54b8486f
GN		 5112}
5113
8ec4722d
MG		 5114static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5115{
adf52235 5116 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5117 int cs_db, cs_l;
5118
8ec4722d
MG		 5119 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5120
adf52235
TY		 5121 ctxt->eflags = kvm_get_rflags(vcpu);
5122 ctxt->eip = kvm_rip_read(vcpu);
5123 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5124 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5125 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5126 cs_db ? X86EMUL_MODE_PROT32 :
5127 X86EMUL_MODE_PROT16;
a584539b 5128 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5129 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5130 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5131 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5132
dd856efa 5133 init_decode_cache(ctxt);
7ae441ea 5134 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5135}
5136
71f9833b 5137int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5138{
9d74191a 5139 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5140 int ret;
5141
5142 init_emulate_ctxt(vcpu);
5143
9dac77fa
AK		 5144 ctxt->op_bytes = 2;
5145 ctxt->ad_bytes = 2;
5146 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5147 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5148
5149 if (ret != X86EMUL_CONTINUE)
5150 return EMULATE_FAIL;
5151
9dac77fa 5152 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5153 kvm_rip_write(vcpu, ctxt->eip);
5154 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5155
5156 if (irq == NMI_VECTOR)
7460fb4a 5157 vcpu->arch.nmi_pending = 0;
63995653
MG		 5158 else
5159 vcpu->arch.interrupt.pending = false;
5160
5161 return EMULATE_DONE;
5162}
5163EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5164
6d77dbfc
GN		 5165static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5166{
fc3a9157
JR		 5167 int r = EMULATE_DONE;
5168
6d77dbfc
GN		 5169 ++vcpu->stat.insn_emulation_fail;
5170 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5171 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5172 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5173 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5174 vcpu->run->internal.ndata = 0;
5175 r = EMULATE_FAIL;
5176 }
6d77dbfc 5177 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5178
5179 return r;
6d77dbfc
GN		 5180}
5181
93c05d3e 5182static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5183 bool write_fault_to_shadow_pgtable,
5184 int emulation_type)
a6f177ef 5185{
95b3cf69 5186 gpa_t gpa = cr2;
ba049e93 5187 kvm_pfn_t pfn;
a6f177ef 5188
991eebf9
GN		 5189 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5190 return false;
5191
95b3cf69
XG		 5192 if (!vcpu->arch.mmu.direct_map) {
5193 /*
5194 * Write permission should be allowed since only
5195 * write access need to be emulated.
5196 */
5197 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5198
95b3cf69
XG		 5199 /*
5200 * If the mapping is invalid in guest, let cpu retry
5201 * it to generate fault.
5202 */
5203 if (gpa == UNMAPPED_GVA)
5204 return true;
5205 }
a6f177ef 5206
8e3d9d06
XG		 5207 /*
5208 * Do not retry the unhandleable instruction if it faults on the
5209 * readonly host memory, otherwise it will goto a infinite loop:
5210 * retry instruction -> write #PF -> emulation fail -> retry
5211 * instruction -> ...
5212 */
5213 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5214
5215 /*
5216 * If the instruction failed on the error pfn, it can not be fixed,
5217 * report the error to userspace.
5218 */
5219 if (is_error_noslot_pfn(pfn))
5220 return false;
5221
5222 kvm_release_pfn_clean(pfn);
5223
5224 /* The instructions are well-emulated on direct mmu. */
5225 if (vcpu->arch.mmu.direct_map) {
5226 unsigned int indirect_shadow_pages;
5227
5228 spin_lock(&vcpu->kvm->mmu_lock);
5229 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5230 spin_unlock(&vcpu->kvm->mmu_lock);
5231
5232 if (indirect_shadow_pages)
5233 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5234
a6f177ef 5235 return true;
8e3d9d06 5236 }
a6f177ef 5237
95b3cf69
XG		 5238 /*
5239 * if emulation was due to access to shadowed page table
5240 * and it failed try to unshadow page and re-enter the
5241 * guest to let CPU execute the instruction.
5242 */
5243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5244
5245 /*
5246 * If the access faults on its page table, it can not
5247 * be fixed by unprotecting shadow page and it should
5248 * be reported to userspace.
5249 */
5250 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5251}
5252
1cb3f3ae
XG		 5253static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5254 unsigned long cr2, int emulation_type)
5255{
5256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5257 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5258
5259 last_retry_eip = vcpu->arch.last_retry_eip;
5260 last_retry_addr = vcpu->arch.last_retry_addr;
5261
5262 /*
5263 * If the emulation is caused by #PF and it is non-page_table
5264 * writing instruction, it means the VM-EXIT is caused by shadow
5265 * page protected, we can zap the shadow page and retry this
5266 * instruction directly.
5267 *
5268 * Note: if the guest uses a non-page-table modifying instruction
5269 * on the PDE that points to the instruction, then we will unmap
5270 * the instruction and go to an infinite loop. So, we cache the
5271 * last retried eip and the last fault address, if we meet the eip
5272 * and the address again, we can break out of the potential infinite
5273 * loop.
5274 */
5275 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5276
5277 if (!(emulation_type & EMULTYPE_RETRY))
5278 return false;
5279
5280 if (x86_page_table_writing_insn(ctxt))
5281 return false;
5282
5283 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5284 return false;
5285
5286 vcpu->arch.last_retry_eip = ctxt->eip;
5287 vcpu->arch.last_retry_addr = cr2;
5288
5289 if (!vcpu->arch.mmu.direct_map)
5290 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5291
22368028 5292 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5293
5294 return true;
5295}
5296
716d51ab
GN		 5297static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5298static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5299
64d60670 5300static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5301{
64d60670 5302 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5303 /* This is a good place to trace that we are exiting SMM. */
5304 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5305
c43203ca
PB		 5306 /* Process a latched INIT or SMI, if any. */
5307 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5308 }
699023e2
PB		 5309
5310 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5311}
5312
5313static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5314{
5315 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5316
a584539b 5317 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5318
5319 if (changed & HF_SMM_MASK)
5320 kvm_smm_changed(vcpu);
a584539b
PB		 5321}
5322
4a1e10d5
PB		 5323static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5324 unsigned long *db)
5325{
5326 u32 dr6 = 0;
5327 int i;
5328 u32 enable, rwlen;
5329
5330 enable = dr7;
5331 rwlen = dr7 >> 16;
5332 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5333 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5334 dr6 |= (1 << i);
5335 return dr6;
5336}
5337
6addfc42 5338static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5339{
5340 struct kvm_run *kvm_run = vcpu->run;
5341
5342 /*
6addfc42
PB		 5343 * rflags is the old, "raw" value of the flags. The new value has
5344 * not been saved yet.
663f4c61
PB		 5345 *
5346 * This is correct even for TF set by the guest, because "the
5347 * processor will not generate this exception after the instruction
5348 * that sets the TF flag".
5349 */
663f4c61
PB		 5350 if (unlikely(rflags & X86_EFLAGS_TF)) {
5351 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5352 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5353 DR6_RTM;
663f4c61
PB		 5354 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5355 kvm_run->debug.arch.exception = DB_VECTOR;
5356 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5357 *r = EMULATE_USER_EXIT;
5358 } else {
5359 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5360 /*
5361 * "Certain debug exceptions may clear bit 0-3. The
5362 * remaining contents of the DR6 register are never
5363 * cleared by the processor".
5364 */
5365 vcpu->arch.dr6 &= ~15;
6f43ed01 5366 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5367 kvm_queue_exception(vcpu, DB_VECTOR);
5368 }
5369 }
5370}
5371
4a1e10d5
PB		 5372static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5373{
4a1e10d5
PB		 5374 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5375 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5376 struct kvm_run *kvm_run = vcpu->run;
5377 unsigned long eip = kvm_get_linear_rip(vcpu);
5378 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5379 vcpu->arch.guest_debug_dr7,
5380 vcpu->arch.eff_db);
5381
5382 if (dr6 != 0) {
6f43ed01 5383 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5384 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5385 kvm_run->debug.arch.exception = DB_VECTOR;
5386 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5387 *r = EMULATE_USER_EXIT;
5388 return true;
5389 }
5390 }
5391
4161a569
NA		 5392 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5393 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5394 unsigned long eip = kvm_get_linear_rip(vcpu);
5395 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5396 vcpu->arch.dr7,
5397 vcpu->arch.db);
5398
5399 if (dr6 != 0) {
5400 vcpu->arch.dr6 &= ~15;
6f43ed01 5401 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5402 kvm_queue_exception(vcpu, DB_VECTOR);
5403 *r = EMULATE_DONE;
5404 return true;
5405 }
5406 }
5407
5408 return false;
5409}
5410
51d8b661
AP		 5411int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5412 unsigned long cr2,
dc25e89e
AP		 5413 int emulation_type,
5414 void *insn,
5415 int insn_len)
bbd9b64e 5416{
95cb2295 5417 int r;
9d74191a 5418 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5419 bool writeback = true;
93c05d3e 5420 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5421
93c05d3e
XG		 5422 /*
5423 * Clear write_fault_to_shadow_pgtable here to ensure it is
5424 * never reused.
5425 */
5426 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5427 kvm_clear_exception_queue(vcpu);
8d7d8102 5428
571008da 5429 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5430 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5431
5432 /*
5433 * We will reenter on the same instruction since
5434 * we do not set complete_userspace_io. This does not
5435 * handle watchpoints yet, those would be handled in
5436 * the emulate_ops.
5437 */
5438 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5439 return r;
5440
9d74191a
TY		 5441 ctxt->interruptibility = 0;
5442 ctxt->have_exception = false;
e0ad0b47 5443 ctxt->exception.vector = -1;
9d74191a 5444 ctxt->perm_ok = false;
bbd9b64e 5445
b51e974f 5446 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5447
9d74191a 5448 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5449
e46479f8 5450 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5451 ++vcpu->stat.insn_emulation;
1d2887e2 5452 if (r != EMULATION_OK) {
4005996e
AK		 5453 if (emulation_type & EMULTYPE_TRAP_UD)
5454 return EMULATE_FAIL;
991eebf9
GN		 5455 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5456 emulation_type))
bbd9b64e 5457 return EMULATE_DONE;
6d77dbfc
GN		 5458 if (emulation_type & EMULTYPE_SKIP)
5459 return EMULATE_FAIL;
5460 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5461 }
5462 }
5463
ba8afb6b 5464 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5465 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5466 if (ctxt->eflags & X86_EFLAGS_RF)
5467 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5468 return EMULATE_DONE;
5469 }
5470
1cb3f3ae
XG		 5471 if (retry_instruction(ctxt, cr2, emulation_type))
5472 return EMULATE_DONE;
5473
7ae441ea 5474 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5475 changes registers values during IO operation */
7ae441ea
GN		 5476 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5477 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5478 emulator_invalidate_register_cache(ctxt);
7ae441ea 5479 }
4d2179e1 5480
5cd21917 5481restart:
9d74191a 5482 r = x86_emulate_insn(ctxt);
bbd9b64e 5483
775fde86
JR		 5484 if (r == EMULATION_INTERCEPTED)
5485 return EMULATE_DONE;
5486
d2ddd1c4 5487 if (r == EMULATION_FAILED) {
991eebf9
GN		 5488 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5489 emulation_type))
c3cd7ffa
GN		 5490 return EMULATE_DONE;
5491
6d77dbfc 5492 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5493 }
5494
9d74191a 5495 if (ctxt->have_exception) {
d2ddd1c4 5496 r = EMULATE_DONE;
ef54bcfe
PB		 5497 if (inject_emulated_exception(vcpu))
5498 return r;
d2ddd1c4 5499 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5500 if (!vcpu->arch.pio.in) {
5501 /* FIXME: return into emulator if single-stepping. */
3457e419 5502 vcpu->arch.pio.count = 0;
0912c977 5503 } else {
7ae441ea 5504 writeback = false;
716d51ab
GN		 5505 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5506 }
ac0a48c3 5507 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5508 } else if (vcpu->mmio_needed) {
5509 if (!vcpu->mmio_is_write)
5510 writeback = false;
ac0a48c3 5511 r = EMULATE_USER_EXIT;
716d51ab 5512 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5513 } else if (r == EMULATION_RESTART)
5cd21917 5514 goto restart;
d2ddd1c4
GN		 5515 else
5516 r = EMULATE_DONE;
f850e2e6 5517
7ae441ea 5518 if (writeback) {
6addfc42 5519 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5520 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5521 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5522 if (vcpu->arch.hflags != ctxt->emul_flags)
5523 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5524 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5525 if (r == EMULATE_DONE)
6addfc42 5526 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5527 if (!ctxt->have_exception ||
5528 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5529 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5530
5531 /*
5532 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5533 * do nothing, and it will be requested again as soon as
5534 * the shadow expires. But we still need to check here,
5535 * because POPF has no interrupt shadow.
5536 */
5537 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5538 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5539 } else
5540 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5541
5542 return r;
de7d789a 5543}
51d8b661 5544EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5545
cf8f70bf 5546int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5547{
cf8f70bf 5548 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5549 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5550 size, port, &val, 1);
cf8f70bf 5551 /* do not return to emulator after return from userspace */
7972995b 5552 vcpu->arch.pio.count = 0;
de7d789a
CO		 5553 return ret;
5554}
cf8f70bf 5555EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5556
8cfdc000
ZA		 5557static void tsc_bad(void *info)
5558{
0a3aee0d 5559 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5560}
5561
5562static void tsc_khz_changed(void *data)
c8076604 5563{
8cfdc000
ZA		 5564 struct cpufreq_freqs *freq = data;
5565 unsigned long khz = 0;
5566
5567 if (data)
5568 khz = freq->new;
5569 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5570 khz = cpufreq_quick_get(raw_smp_processor_id());
5571 if (!khz)
5572 khz = tsc_khz;
0a3aee0d 5573 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5574}
5575
c8076604
GH		 5576static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5577 void *data)
5578{
5579 struct cpufreq_freqs *freq = data;
5580 struct kvm *kvm;
5581 struct kvm_vcpu *vcpu;
5582 int i, send_ipi = 0;
5583
8cfdc000
ZA		 5584 /*
5585 * We allow guests to temporarily run on slowing clocks,
5586 * provided we notify them after, or to run on accelerating
5587 * clocks, provided we notify them before. Thus time never
5588 * goes backwards.
5589 *
5590 * However, we have a problem. We can't atomically update
5591 * the frequency of a given CPU from this function; it is
5592 * merely a notifier, which can be called from any CPU.
5593 * Changing the TSC frequency at arbitrary points in time
5594 * requires a recomputation of local variables related to
5595 * the TSC for each VCPU. We must flag these local variables
5596 * to be updated and be sure the update takes place with the
5597 * new frequency before any guests proceed.
5598 *
5599 * Unfortunately, the combination of hotplug CPU and frequency
5600 * change creates an intractable locking scenario; the order
5601 * of when these callouts happen is undefined with respect to
5602 * CPU hotplug, and they can race with each other. As such,
5603 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5604 * undefined; you can actually have a CPU frequency change take
5605 * place in between the computation of X and the setting of the
5606 * variable. To protect against this problem, all updates of
5607 * the per_cpu tsc_khz variable are done in an interrupt
5608 * protected IPI, and all callers wishing to update the value
5609 * must wait for a synchronous IPI to complete (which is trivial
5610 * if the caller is on the CPU already). This establishes the
5611 * necessary total order on variable updates.
5612 *
5613 * Note that because a guest time update may take place
5614 * anytime after the setting of the VCPU's request bit, the
5615 * correct TSC value must be set before the request. However,
5616 * to ensure the update actually makes it to any guest which
5617 * starts running in hardware virtualization between the set
5618 * and the acquisition of the spinlock, we must also ping the
5619 * CPU after setting the request bit.
5620 *
5621 */
5622
c8076604
GH		 5623 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5624 return 0;
5625 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5626 return 0;
8cfdc000
ZA		 5627
5628 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5629
2f303b74 5630 spin_lock(&kvm_lock);
c8076604 5631 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5632 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5633 if (vcpu->cpu != freq->cpu)
5634 continue;
c285545f 5635 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5636 if (vcpu->cpu != smp_processor_id())
8cfdc000 5637 send_ipi = 1;
c8076604
GH		 5638 }
5639 }
2f303b74 5640 spin_unlock(&kvm_lock);
c8076604
GH		 5641
5642 if (freq->old < freq->new && send_ipi) {
5643 /*
5644 * We upscale the frequency. Must make the guest
5645 * doesn't see old kvmclock values while running with
5646 * the new frequency, otherwise we risk the guest sees
5647 * time go backwards.
5648 *
5649 * In case we update the frequency for another cpu
5650 * (which might be in guest context) send an interrupt
5651 * to kick the cpu out of guest context. Next time
5652 * guest context is entered kvmclock will be updated,
5653 * so the guest will not see stale values.
5654 */
8cfdc000 5655 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5656 }
5657 return 0;
5658}
5659
5660static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5661 .notifier_call = kvmclock_cpufreq_notifier
5662};
5663
5664static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5665 unsigned long action, void *hcpu)
5666{
5667 unsigned int cpu = (unsigned long)hcpu;
5668
5669 switch (action) {
5670 case CPU_ONLINE:
5671 case CPU_DOWN_FAILED:
5672 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5673 break;
5674 case CPU_DOWN_PREPARE:
5675 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5676 break;
5677 }
5678 return NOTIFY_OK;
5679}
5680
5681static struct notifier_block kvmclock_cpu_notifier_block = {
5682 .notifier_call = kvmclock_cpu_notifier,
5683 .priority = -INT_MAX
c8076604
GH		 5684};
5685
b820cc0c
ZA		 5686static void kvm_timer_init(void)
5687{
5688 int cpu;
5689
c285545f 5690 max_tsc_khz = tsc_khz;
460dd42e
SB		 5691
5692 cpu_notifier_register_begin();
b820cc0c 5693 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5694#ifdef CONFIG_CPU_FREQ
5695 struct cpufreq_policy policy;
5696 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5697 cpu = get_cpu();
5698 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5699 if (policy.cpuinfo.max_freq)
5700 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5701 put_cpu();
c285545f 5702#endif
b820cc0c
ZA		 5703 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5704 CPUFREQ_TRANSITION_NOTIFIER);
5705 }
c285545f 5706 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5707 for_each_online_cpu(cpu)
5708 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5709
5710 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5711 cpu_notifier_register_done();
5712
b820cc0c
ZA		 5713}
5714
ff9d07a0
ZY		 5715static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5716
f5132b01 5717int kvm_is_in_guest(void)
ff9d07a0 5718{
086c9855 5719 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5720}
5721
5722static int kvm_is_user_mode(void)
5723{
5724 int user_mode = 3;
dcf46b94 5725
086c9855
AS		 5726 if (__this_cpu_read(current_vcpu))
5727 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5728
ff9d07a0
ZY		 5729 return user_mode != 0;
5730}
5731
5732static unsigned long kvm_get_guest_ip(void)
5733{
5734 unsigned long ip = 0;
dcf46b94 5735
086c9855
AS		 5736 if (__this_cpu_read(current_vcpu))
5737 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5738
ff9d07a0
ZY		 5739 return ip;
5740}
5741
5742static struct perf_guest_info_callbacks kvm_guest_cbs = {
5743 .is_in_guest = kvm_is_in_guest,
5744 .is_user_mode = kvm_is_user_mode,
5745 .get_guest_ip = kvm_get_guest_ip,
5746};
5747
5748void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5749{
086c9855 5750 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5751}
5752EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5753
5754void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5755{
086c9855 5756 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5757}
5758EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5759
ce88decf
XG		 5760static void kvm_set_mmio_spte_mask(void)
5761{
5762 u64 mask;
5763 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5764
5765 /*
5766 * Set the reserved bits and the present bit of an paging-structure
5767 * entry to generate page fault with PFER.RSV = 1.
5768 */
885032b9 5769 /* Mask the reserved physical address bits. */
d1431483 5770 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5771
5772 /* Bit 62 is always reserved for 32bit host. */
5773 mask |= 0x3ull << 62;
5774
5775 /* Set the present bit. */
ce88decf
XG		 5776 mask |= 1ull;
5777
5778#ifdef CONFIG_X86_64
5779 /*
5780 * If reserved bit is not supported, clear the present bit to disable
5781 * mmio page fault.
5782 */
5783 if (maxphyaddr == 52)
5784 mask &= ~1ull;
5785#endif
5786
5787 kvm_mmu_set_mmio_spte_mask(mask);
5788}
5789
16e8d74d
MT		 5790#ifdef CONFIG_X86_64
5791static void pvclock_gtod_update_fn(struct work_struct *work)
5792{
d828199e
MT		 5793 struct kvm *kvm;
5794
5795 struct kvm_vcpu *vcpu;
5796 int i;
5797
2f303b74 5798 spin_lock(&kvm_lock);
d828199e
MT		 5799 list_for_each_entry(kvm, &vm_list, vm_list)
5800 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5801 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5802 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5803 spin_unlock(&kvm_lock);
16e8d74d
MT		 5804}
5805
5806static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5807
5808/*
5809 * Notification about pvclock gtod data update.
5810 */
5811static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5812 void *priv)
5813{
5814 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5815 struct timekeeper *tk = priv;
5816
5817 update_pvclock_gtod(tk);
5818
5819 /* disable master clock if host does not trust, or does not
5820 * use, TSC clocksource
5821 */
5822 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5823 atomic_read(&kvm_guest_has_master_clock) != 0)
5824 queue_work(system_long_wq, &pvclock_gtod_work);
5825
5826 return 0;
5827}
5828
5829static struct notifier_block pvclock_gtod_notifier = {
5830 .notifier_call = pvclock_gtod_notify,
5831};
5832#endif
5833
f8c16bba 5834int kvm_arch_init(void *opaque)
043405e1 5835{
b820cc0c 5836 int r;
6b61edf7 5837 struct kvm_x86_ops *ops = opaque;
f8c16bba 5838
f8c16bba
ZX		 5839 if (kvm_x86_ops) {
5840 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5841 r = -EEXIST;
5842 goto out;
f8c16bba
ZX		 5843 }
5844
5845 if (!ops->cpu_has_kvm_support()) {
5846 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5847 r = -EOPNOTSUPP;
5848 goto out;
f8c16bba
ZX		 5849 }
5850 if (ops->disabled_by_bios()) {
5851 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5852 r = -EOPNOTSUPP;
5853 goto out;
f8c16bba
ZX		 5854 }
5855
013f6a5d
MT		 5856 r = -ENOMEM;
5857 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5858 if (!shared_msrs) {
5859 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5860 goto out;
5861 }
5862
97db56ce
AK		 5863 r = kvm_mmu_module_init();
5864 if (r)
013f6a5d 5865 goto out_free_percpu;
97db56ce 5866
ce88decf 5867 kvm_set_mmio_spte_mask();
97db56ce 5868
f8c16bba 5869 kvm_x86_ops = ops;
920c8377 5870
7b52345e 5871 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5872 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5873
b820cc0c 5874 kvm_timer_init();
c8076604 5875
ff9d07a0
ZY		 5876 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5877
d366bf7e 5878 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5879 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5880
c5cc421b 5881 kvm_lapic_init();
16e8d74d
MT		 5882#ifdef CONFIG_X86_64
5883 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5884#endif
5885
f8c16bba 5886 return 0;
56c6d28a 5887
013f6a5d
MT		 5888out_free_percpu:
5889 free_percpu(shared_msrs);
56c6d28a 5890out:
56c6d28a 5891 return r;
043405e1 5892}
8776e519 5893
f8c16bba
ZX		 5894void kvm_arch_exit(void)
5895{
ff9d07a0
ZY		 5896 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5897
888d256e
JK		 5898 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5899 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5900 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5901 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5902#ifdef CONFIG_X86_64
5903 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5904#endif
f8c16bba 5905 kvm_x86_ops = NULL;
56c6d28a 5906 kvm_mmu_module_exit();
013f6a5d 5907 free_percpu(shared_msrs);
56c6d28a 5908}
f8c16bba 5909
5cb56059 5910int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5911{
5912 ++vcpu->stat.halt_exits;
35754c98 5913 if (lapic_in_kernel(vcpu)) {
a4535290 5914 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5915 return 1;
5916 } else {
5917 vcpu->run->exit_reason = KVM_EXIT_HLT;
5918 return 0;
5919 }
5920}
5cb56059
JS		 5921EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5922
5923int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5924{
5925 kvm_x86_ops->skip_emulated_instruction(vcpu);
5926 return kvm_vcpu_halt(vcpu);
5927}
8776e519
HB		 5928EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5929
6aef266c
SV		 5930/*
5931 * kvm_pv_kick_cpu_op: Kick a vcpu.
5932 *
5933 * @apicid - apicid of vcpu to be kicked.
5934 */
5935static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5936{
24d2166b 5937 struct kvm_lapic_irq lapic_irq;
6aef266c 5938
24d2166b
R		 5939 lapic_irq.shorthand = 0;
5940 lapic_irq.dest_mode = 0;
5941 lapic_irq.dest_id = apicid;
93bbf0b8 5942 lapic_irq.msi_redir_hint = false;
6aef266c 5943
24d2166b 5944 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5945 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5946}
5947
d62caabb
AS		 5948void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5949{
5950 vcpu->arch.apicv_active = false;
5951 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5952}
5953
8776e519
HB		 5954int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5955{
5956 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5957 int op_64_bit, r = 1;
8776e519 5958
5cb56059
JS		 5959 kvm_x86_ops->skip_emulated_instruction(vcpu);
5960
55cd8e5a
GN		 5961 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5962 return kvm_hv_hypercall(vcpu);
5963
5fdbf976
MT		 5964 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5965 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5966 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5967 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5968 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5969
229456fc 5970 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5971
a449c7aa
NA		 5972 op_64_bit = is_64_bit_mode(vcpu);
5973 if (!op_64_bit) {
8776e519
HB		 5974 nr &= 0xFFFFFFFF;
5975 a0 &= 0xFFFFFFFF;
5976 a1 &= 0xFFFFFFFF;
5977 a2 &= 0xFFFFFFFF;
5978 a3 &= 0xFFFFFFFF;
5979 }
5980
07708c4a
JK		 5981 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5982 ret = -KVM_EPERM;
5983 goto out;
5984 }
5985
8776e519 5986 switch (nr) {
b93463aa
AK		 5987 case KVM_HC_VAPIC_POLL_IRQ:
5988 ret = 0;
5989 break;
6aef266c
SV		 5990 case KVM_HC_KICK_CPU:
5991 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5992 ret = 0;
5993 break;
8776e519
HB		 5994 default:
5995 ret = -KVM_ENOSYS;
5996 break;
5997 }
07708c4a 5998out:
a449c7aa
NA		 5999 if (!op_64_bit)
6000 ret = (u32)ret;
5fdbf976 6001 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6002 ++vcpu->stat.hypercalls;
2f333bcb 6003 return r;
8776e519
HB		 6004}
6005EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6006
b6785def 6007static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6008{
d6aa1000 6009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6010 char instruction[3];
5fdbf976 6011 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6012
8776e519 6013 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6014
9d74191a 6015 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6016}
6017
851ba692 6018static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6019{
782d422b
MG		 6020 return vcpu->run->request_interrupt_window &&
6021 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6022}
6023
851ba692 6024static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6025{
851ba692
AK		 6026 struct kvm_run *kvm_run = vcpu->run;
6027
91586a3b 6028 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6029 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6030 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6031 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6032 kvm_run->ready_for_interrupt_injection =
6033 pic_in_kernel(vcpu->kvm) ||
782d422b 6034 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6035}
6036
95ba8273
GN		 6037static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6038{
6039 int max_irr, tpr;
6040
6041 if (!kvm_x86_ops->update_cr8_intercept)
6042 return;
6043
bce87cce 6044 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6045 return;
6046
d62caabb
AS		 6047 if (vcpu->arch.apicv_active)
6048 return;
6049
8db3baa2
GN		 6050 if (!vcpu->arch.apic->vapic_addr)
6051 max_irr = kvm_lapic_find_highest_irr(vcpu);
6052 else
6053 max_irr = -1;
95ba8273
GN		 6054
6055 if (max_irr != -1)
6056 max_irr >>= 4;
6057
6058 tpr = kvm_lapic_get_cr8(vcpu);
6059
6060 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6061}
6062
b6b8a145 6063static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6064{
b6b8a145
JK		 6065 int r;
6066
95ba8273 6067 /* try to reinject previous events if any */
b59bb7bd 6068 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6069 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6070 vcpu->arch.exception.has_error_code,
6071 vcpu->arch.exception.error_code);
d6e8c854
NA		 6072
6073 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6074 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6075 X86_EFLAGS_RF);
6076
6bdf0662
NA		 6077 if (vcpu->arch.exception.nr == DB_VECTOR &&
6078 (vcpu->arch.dr7 & DR7_GD)) {
6079 vcpu->arch.dr7 &= ~DR7_GD;
6080 kvm_update_dr7(vcpu);
6081 }
6082
b59bb7bd
GN		 6083 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6084 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6085 vcpu->arch.exception.error_code,
6086 vcpu->arch.exception.reinject);
b6b8a145 6087 return 0;
b59bb7bd
GN		 6088 }
6089
95ba8273
GN		 6090 if (vcpu->arch.nmi_injected) {
6091 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6092 return 0;
95ba8273
GN		 6093 }
6094
6095 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6096 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6097 return 0;
6098 }
6099
6100 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6101 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6102 if (r != 0)
6103 return r;
95ba8273
GN		 6104 }
6105
6106 /* try to inject new event if pending */
c43203ca
PB		 6107 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6108 vcpu->arch.smi_pending = false;
ee2cd4b7 6109 enter_smm(vcpu);
c43203ca 6110 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6111 --vcpu->arch.nmi_pending;
6112 vcpu->arch.nmi_injected = true;
6113 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6114 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6115 /*
6116 * Because interrupts can be injected asynchronously, we are
6117 * calling check_nested_events again here to avoid a race condition.
6118 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6119 * proposal and current concerns. Perhaps we should be setting
6120 * KVM_REQ_EVENT only on certain events and not unconditionally?
6121 */
6122 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6123 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6124 if (r != 0)
6125 return r;
6126 }
95ba8273 6127 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6128 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6129 false);
6130 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6131 }
6132 }
ee2cd4b7 6133
b6b8a145 6134 return 0;
95ba8273
GN		 6135}
6136
7460fb4a
AK		 6137static void process_nmi(struct kvm_vcpu *vcpu)
6138{
6139 unsigned limit = 2;
6140
6141 /*
6142 * x86 is limited to one NMI running, and one NMI pending after it.
6143 * If an NMI is already in progress, limit further NMIs to just one.
6144 * Otherwise, allow two (and we'll inject the first one immediately).
6145 */
6146 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6147 limit = 1;
6148
6149 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6150 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6151 kvm_make_request(KVM_REQ_EVENT, vcpu);
6152}
6153
660a5d51
PB		 6154#define put_smstate(type, buf, offset, val) \
6155 *(type *)((buf) + (offset) - 0x7e00) = val
6156
ee2cd4b7 6157static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6158{
6159 u32 flags = 0;
6160 flags |= seg->g << 23;
6161 flags |= seg->db << 22;
6162 flags |= seg->l << 21;
6163 flags |= seg->avl << 20;
6164 flags |= seg->present << 15;
6165 flags |= seg->dpl << 13;
6166 flags |= seg->s << 12;
6167 flags |= seg->type << 8;
6168 return flags;
6169}
6170
ee2cd4b7 6171static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6172{
6173 struct kvm_segment seg;
6174 int offset;
6175
6176 kvm_get_segment(vcpu, &seg, n);
6177 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6178
6179 if (n < 3)
6180 offset = 0x7f84 + n * 12;
6181 else
6182 offset = 0x7f2c + (n - 3) * 12;
6183
6184 put_smstate(u32, buf, offset + 8, seg.base);
6185 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6186 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6187}
6188
efbb288a 6189#ifdef CONFIG_X86_64
ee2cd4b7 6190static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6191{
6192 struct kvm_segment seg;
6193 int offset;
6194 u16 flags;
6195
6196 kvm_get_segment(vcpu, &seg, n);
6197 offset = 0x7e00 + n * 16;
6198
ee2cd4b7 6199 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6200 put_smstate(u16, buf, offset, seg.selector);
6201 put_smstate(u16, buf, offset + 2, flags);
6202 put_smstate(u32, buf, offset + 4, seg.limit);
6203 put_smstate(u64, buf, offset + 8, seg.base);
6204}
efbb288a 6205#endif
660a5d51 6206
ee2cd4b7 6207static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6208{
6209 struct desc_ptr dt;
6210 struct kvm_segment seg;
6211 unsigned long val;
6212 int i;
6213
6214 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6215 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6216 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6217 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6218
6219 for (i = 0; i < 8; i++)
6220 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6221
6222 kvm_get_dr(vcpu, 6, &val);
6223 put_smstate(u32, buf, 0x7fcc, (u32)val);
6224 kvm_get_dr(vcpu, 7, &val);
6225 put_smstate(u32, buf, 0x7fc8, (u32)val);
6226
6227 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6228 put_smstate(u32, buf, 0x7fc4, seg.selector);
6229 put_smstate(u32, buf, 0x7f64, seg.base);
6230 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6231 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6232
6233 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6234 put_smstate(u32, buf, 0x7fc0, seg.selector);
6235 put_smstate(u32, buf, 0x7f80, seg.base);
6236 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6237 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6238
6239 kvm_x86_ops->get_gdt(vcpu, &dt);
6240 put_smstate(u32, buf, 0x7f74, dt.address);
6241 put_smstate(u32, buf, 0x7f70, dt.size);
6242
6243 kvm_x86_ops->get_idt(vcpu, &dt);
6244 put_smstate(u32, buf, 0x7f58, dt.address);
6245 put_smstate(u32, buf, 0x7f54, dt.size);
6246
6247 for (i = 0; i < 6; i++)
ee2cd4b7 6248 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6249
6250 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6251
6252 /* revision id */
6253 put_smstate(u32, buf, 0x7efc, 0x00020000);
6254 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6255}
6256
ee2cd4b7 6257static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6258{
6259#ifdef CONFIG_X86_64
6260 struct desc_ptr dt;
6261 struct kvm_segment seg;
6262 unsigned long val;
6263 int i;
6264
6265 for (i = 0; i < 16; i++)
6266 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6267
6268 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6269 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6270
6271 kvm_get_dr(vcpu, 6, &val);
6272 put_smstate(u64, buf, 0x7f68, val);
6273 kvm_get_dr(vcpu, 7, &val);
6274 put_smstate(u64, buf, 0x7f60, val);
6275
6276 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6277 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6278 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6279
6280 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6281
6282 /* revision id */
6283 put_smstate(u32, buf, 0x7efc, 0x00020064);
6284
6285 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6286
6287 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6288 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6289 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6290 put_smstate(u32, buf, 0x7e94, seg.limit);
6291 put_smstate(u64, buf, 0x7e98, seg.base);
6292
6293 kvm_x86_ops->get_idt(vcpu, &dt);
6294 put_smstate(u32, buf, 0x7e84, dt.size);
6295 put_smstate(u64, buf, 0x7e88, dt.address);
6296
6297 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6298 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6299 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6300 put_smstate(u32, buf, 0x7e74, seg.limit);
6301 put_smstate(u64, buf, 0x7e78, seg.base);
6302
6303 kvm_x86_ops->get_gdt(vcpu, &dt);
6304 put_smstate(u32, buf, 0x7e64, dt.size);
6305 put_smstate(u64, buf, 0x7e68, dt.address);
6306
6307 for (i = 0; i < 6; i++)
ee2cd4b7 6308 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6309#else
6310 WARN_ON_ONCE(1);
6311#endif
6312}
6313
ee2cd4b7 6314static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6315{
660a5d51 6316 struct kvm_segment cs, ds;
18c3626e 6317 struct desc_ptr dt;
660a5d51
PB		 6318 char buf[512];
6319 u32 cr0;
6320
660a5d51
PB		 6321 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6322 vcpu->arch.hflags |= HF_SMM_MASK;
6323 memset(buf, 0, 512);
6324 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6325 enter_smm_save_state_64(vcpu, buf);
660a5d51 6326 else
ee2cd4b7 6327 enter_smm_save_state_32(vcpu, buf);
660a5d51 6328
54bf36aa 6329 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6330
6331 if (kvm_x86_ops->get_nmi_mask(vcpu))
6332 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6333 else
6334 kvm_x86_ops->set_nmi_mask(vcpu, true);
6335
6336 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6337 kvm_rip_write(vcpu, 0x8000);
6338
6339 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6340 kvm_x86_ops->set_cr0(vcpu, cr0);
6341 vcpu->arch.cr0 = cr0;
6342
6343 kvm_x86_ops->set_cr4(vcpu, 0);
6344
18c3626e
PB		 6345 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6346 dt.address = dt.size = 0;
6347 kvm_x86_ops->set_idt(vcpu, &dt);
6348
660a5d51
PB		 6349 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6350
6351 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6352 cs.base = vcpu->arch.smbase;
6353
6354 ds.selector = 0;
6355 ds.base = 0;
6356
6357 cs.limit = ds.limit = 0xffffffff;
6358 cs.type = ds.type = 0x3;
6359 cs.dpl = ds.dpl = 0;
6360 cs.db = ds.db = 0;
6361 cs.s = ds.s = 1;
6362 cs.l = ds.l = 0;
6363 cs.g = ds.g = 1;
6364 cs.avl = ds.avl = 0;
6365 cs.present = ds.present = 1;
6366 cs.unusable = ds.unusable = 0;
6367 cs.padding = ds.padding = 0;
6368
6369 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6370 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6371 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6372 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6373 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6374 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6375
6376 if (guest_cpuid_has_longmode(vcpu))
6377 kvm_x86_ops->set_efer(vcpu, 0);
6378
6379 kvm_update_cpuid(vcpu);
6380 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6381}
6382
ee2cd4b7 6383static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6384{
6385 vcpu->arch.smi_pending = true;
6386 kvm_make_request(KVM_REQ_EVENT, vcpu);
6387}
6388
2860c4b1
PB		 6389void kvm_make_scan_ioapic_request(struct kvm *kvm)
6390{
6391 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6392}
6393
3d81bc7e 6394static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6395{
5c919412
AS		 6396 u64 eoi_exit_bitmap[4];
6397
3d81bc7e
YZ		 6398 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6399 return;
c7c9c56c 6400
6308630b 6401 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6402
b053b2ae 6403 if (irqchip_split(vcpu->kvm))
6308630b 6404 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6405 else {
d62caabb
AS		 6406 if (vcpu->arch.apicv_active)
6407 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6408 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6409 }
5c919412
AS		 6410 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6411 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6412 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6413}
6414
a70656b6
RK		 6415static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6416{
6417 ++vcpu->stat.tlb_flush;
6418 kvm_x86_ops->tlb_flush(vcpu);
6419}
6420
4256f43f
TC		 6421void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6422{
c24ae0dc
TC		 6423 struct page *page = NULL;
6424
35754c98 6425 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6426 return;
6427
4256f43f
TC		 6428 if (!kvm_x86_ops->set_apic_access_page_addr)
6429 return;
6430
c24ae0dc 6431 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6432 if (is_error_page(page))
6433 return;
c24ae0dc
TC		 6434 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6435
6436 /*
6437 * Do not pin apic access page in memory, the MMU notifier
6438 * will call us again if it is migrated or swapped out.
6439 */
6440 put_page(page);
4256f43f
TC		 6441}
6442EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6443
fe71557a
TC		 6444void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6445 unsigned long address)
6446{
c24ae0dc
TC		 6447 /*
6448 * The physical address of apic access page is stored in the VMCS.
6449 * Update it when it becomes invalid.
6450 */
6451 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6452 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6453}
6454
9357d939 6455/*
362c698f 6456 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6457 * exiting to the userspace. Otherwise, the value will be returned to the
6458 * userspace.
6459 */
851ba692 6460static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6461{
6462 int r;
62a193ed
MG		 6463 bool req_int_win =
6464 dm_request_for_irq_injection(vcpu) &&
6465 kvm_cpu_accept_dm_intr(vcpu);
6466
730dca42 6467 bool req_immediate_exit = false;
b6c7a5dc 6468
3e007509 6469 if (vcpu->requests) {
a8eeb04a 6470 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6471 kvm_mmu_unload(vcpu);
a8eeb04a 6472 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6473 __kvm_migrate_timers(vcpu);
d828199e
MT		 6474 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6475 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6476 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6477 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6478 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6479 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6480 if (unlikely(r))
6481 goto out;
6482 }
a8eeb04a 6483 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6484 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6485 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6486 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6487 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6488 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6489 r = 0;
6490 goto out;
6491 }
a8eeb04a 6492 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6493 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6494 r = 0;
6495 goto out;
6496 }
a8eeb04a 6497 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6498 vcpu->fpu_active = 0;
6499 kvm_x86_ops->fpu_deactivate(vcpu);
6500 }
af585b92
GN		 6501 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6502 /* Page is swapped out. Do synthetic halt */
6503 vcpu->arch.apf.halted = true;
6504 r = 1;
6505 goto out;
6506 }
c9aaa895
GC		 6507 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6508 record_steal_time(vcpu);
64d60670 6509 if (kvm_check_request(KVM_REQ_SMI, vcpu))
ee2cd4b7 6510 process_smi(vcpu);
7460fb4a
AK		 6511 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6512 process_nmi(vcpu);
f5132b01 6513 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6514 kvm_pmu_handle_event(vcpu);
f5132b01 6515 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6516 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6517 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6518 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6519 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6520 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6521 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6522 vcpu->run->eoi.vector =
6523 vcpu->arch.pending_ioapic_eoi;
6524 r = 0;
6525 goto out;
6526 }
6527 }
3d81bc7e
YZ		 6528 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6529 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6530 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6531 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6532 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6534 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6535 r = 0;
6536 goto out;
6537 }
e516cebb
AS		 6538 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6539 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6540 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6541 r = 0;
6542 goto out;
6543 }
db397571
AS		 6544 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6545 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6546 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6547 r = 0;
6548 goto out;
6549 }
f3b138c5
AS		 6550
6551 /*
6552 * KVM_REQ_HV_STIMER has to be processed after
6553 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6554 * depend on the guest clock being up-to-date
6555 */
1f4b34f8
AS		 6556 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6557 kvm_hv_process_stimers(vcpu);
2f52d58c 6558 }
b93463aa 6559
bf9f6ac8
FW		 6560 /*
6561 * KVM_REQ_EVENT is not set when posted interrupts are set by
6562 * VT-d hardware, so we have to update RVI unconditionally.
6563 */
6564 if (kvm_lapic_enabled(vcpu)) {
6565 /*
6566 * Update architecture specific hints for APIC
6567 * virtual interrupt delivery.
6568 */
d62caabb 6569 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6570 kvm_x86_ops->hwapic_irr_update(vcpu,
6571 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6572 }
b93463aa 6573
b463a6f7 6574 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6575 kvm_apic_accept_events(vcpu);
6576 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6577 r = 1;
6578 goto out;
6579 }
6580
b6b8a145
JK		 6581 if (inject_pending_event(vcpu, req_int_win) != 0)
6582 req_immediate_exit = true;
321c5658 6583 else {
c43203ca
PB		 6584 /* Enable NMI/IRQ window open exits if needed.
6585 *
6586 * SMIs have two cases: 1) they can be nested, and
6587 * then there is nothing to do here because RSM will
6588 * cause a vmexit anyway; 2) or the SMI can be pending
6589 * because inject_pending_event has completed the
6590 * injection of an IRQ or NMI from the previous vmexit,
6591 * and then we request an immediate exit to inject the SMI.
6592 */
6593 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6594 req_immediate_exit = true;
321c5658
YS		 6595 if (vcpu->arch.nmi_pending)
6596 kvm_x86_ops->enable_nmi_window(vcpu);
6597 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6598 kvm_x86_ops->enable_irq_window(vcpu);
6599 }
b463a6f7
AK		 6600
6601 if (kvm_lapic_enabled(vcpu)) {
6602 update_cr8_intercept(vcpu);
6603 kvm_lapic_sync_to_vapic(vcpu);
6604 }
6605 }
6606
d8368af8
AK		 6607 r = kvm_mmu_reload(vcpu);
6608 if (unlikely(r)) {
d905c069 6609 goto cancel_injection;
d8368af8
AK		 6610 }
6611
b6c7a5dc
HB		 6612 preempt_disable();
6613
6614 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6615 if (vcpu->fpu_active)
6616 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6617 vcpu->mode = IN_GUEST_MODE;
6618
01b71917
MT		 6619 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6620
0f127d12
LT		 6621 /*
6622 * We should set ->mode before check ->requests,
6623 * Please see the comment in kvm_make_all_cpus_request.
6624 * This also orders the write to mode from any reads
6625 * to the page tables done while the VCPU is running.
6626 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6627 */
01b71917 6628 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6629
d94e1dc9 6630 local_irq_disable();
32f88400 6631
6b7e2d09 6632 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6633 || need_resched() || signal_pending(current)) {
6b7e2d09 6634 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6635 smp_wmb();
6c142801
AK		 6636 local_irq_enable();
6637 preempt_enable();
01b71917 6638 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6639 r = 1;
d905c069 6640 goto cancel_injection;
6c142801
AK		 6641 }
6642
fc5b7f3b
DM		 6643 kvm_load_guest_xcr0(vcpu);
6644
c43203ca
PB		 6645 if (req_immediate_exit) {
6646 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6647 smp_send_reschedule(vcpu->cpu);
c43203ca 6648 }
d6185f20 6649
8b89fe1f
PB		 6650 trace_kvm_entry(vcpu->vcpu_id);
6651 wait_lapic_expire(vcpu);
ccf73aaf 6652 __kvm_guest_enter();
b6c7a5dc 6653
42dbaa5a 6654 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6655 set_debugreg(0, 7);
6656 set_debugreg(vcpu->arch.eff_db[0], 0);
6657 set_debugreg(vcpu->arch.eff_db[1], 1);
6658 set_debugreg(vcpu->arch.eff_db[2], 2);
6659 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6660 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6661 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6662 }
b6c7a5dc 6663
851ba692 6664 kvm_x86_ops->run(vcpu);
b6c7a5dc 6665
c77fb5fe
PB		 6666 /*
6667 * Do this here before restoring debug registers on the host. And
6668 * since we do this before handling the vmexit, a DR access vmexit
6669 * can (a) read the correct value of the debug registers, (b) set
6670 * KVM_DEBUGREG_WONT_EXIT again.
6671 */
6672 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6673 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6674 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6675 kvm_update_dr0123(vcpu);
6676 kvm_update_dr6(vcpu);
6677 kvm_update_dr7(vcpu);
6678 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6679 }
6680
24f1e32c
FW		 6681 /*
6682 * If the guest has used debug registers, at least dr7
6683 * will be disabled while returning to the host.
6684 * If we don't have active breakpoints in the host, we don't
6685 * care about the messed up debug address registers. But if
6686 * we have some of them active, restore the old state.
6687 */
59d8eb53 6688 if (hw_breakpoint_active())
24f1e32c 6689 hw_breakpoint_restore();
42dbaa5a 6690
4ba76538 6691 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6692
6b7e2d09 6693 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6694 smp_wmb();
a547c6db 6695
fc5b7f3b
DM		 6696 kvm_put_guest_xcr0(vcpu);
6697
a547c6db
YZ		 6698 /* Interrupt is enabled by handle_external_intr() */
6699 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6700
6701 ++vcpu->stat.exits;
6702
6703 /*
6704 * We must have an instruction between local_irq_enable() and
6705 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6706 * the interrupt shadow. The stat.exits increment will do nicely.
6707 * But we need to prevent reordering, hence this barrier():
6708 */
6709 barrier();
6710
6711 kvm_guest_exit();
6712
6713 preempt_enable();
6714
f656ce01 6715 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6716
b6c7a5dc
HB		 6717 /*
6718 * Profile KVM exit RIPs:
6719 */
6720 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6721 unsigned long rip = kvm_rip_read(vcpu);
6722 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6723 }
6724
cc578287
ZA		 6725 if (unlikely(vcpu->arch.tsc_always_catchup))
6726 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6727
5cfb1d5a
MT		 6728 if (vcpu->arch.apic_attention)
6729 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6730
851ba692 6731 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6732 return r;
6733
6734cancel_injection:
6735 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6736 if (unlikely(vcpu->arch.apic_attention))
6737 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6738out:
6739 return r;
6740}
b6c7a5dc 6741
362c698f
PB		 6742static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6743{
bf9f6ac8
FW		 6744 if (!kvm_arch_vcpu_runnable(vcpu) &&
6745 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6746 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6747 kvm_vcpu_block(vcpu);
6748 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6749
6750 if (kvm_x86_ops->post_block)
6751 kvm_x86_ops->post_block(vcpu);
6752
9c8fd1ba
PB		 6753 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6754 return 1;
6755 }
362c698f
PB		 6756
6757 kvm_apic_accept_events(vcpu);
6758 switch(vcpu->arch.mp_state) {
6759 case KVM_MP_STATE_HALTED:
6760 vcpu->arch.pv.pv_unhalted = false;
6761 vcpu->arch.mp_state =
6762 KVM_MP_STATE_RUNNABLE;
6763 case KVM_MP_STATE_RUNNABLE:
6764 vcpu->arch.apf.halted = false;
6765 break;
6766 case KVM_MP_STATE_INIT_RECEIVED:
6767 break;
6768 default:
6769 return -EINTR;
6770 break;
6771 }
6772 return 1;
6773}
09cec754 6774
5d9bc648
PB		 6775static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6776{
6777 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6778 !vcpu->arch.apf.halted);
6779}
6780
362c698f 6781static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6782{
6783 int r;
f656ce01 6784 struct kvm *kvm = vcpu->kvm;
d7690175 6785
f656ce01 6786 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6787
362c698f 6788 for (;;) {
58f800d5 6789 if (kvm_vcpu_running(vcpu)) {
851ba692 6790 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6791 } else {
362c698f 6792 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6793 }
6794
09cec754
GN		 6795 if (r <= 0)
6796 break;
6797
6798 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6799 if (kvm_cpu_has_pending_timer(vcpu))
6800 kvm_inject_pending_timer_irqs(vcpu);
6801
782d422b
MG		 6802 if (dm_request_for_irq_injection(vcpu) &&
6803 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6804 r = 0;
6805 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6806 ++vcpu->stat.request_irq_exits;
362c698f 6807 break;
09cec754 6808 }
af585b92
GN		 6809
6810 kvm_check_async_pf_completion(vcpu);
6811
09cec754
GN		 6812 if (signal_pending(current)) {
6813 r = -EINTR;
851ba692 6814 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6815 ++vcpu->stat.signal_exits;
362c698f 6816 break;
09cec754
GN		 6817 }
6818 if (need_resched()) {
f656ce01 6819 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6820 cond_resched();
f656ce01 6821 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6822 }
b6c7a5dc
HB		 6823 }
6824
f656ce01 6825 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6826
6827 return r;
6828}
6829
716d51ab
GN		 6830static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6831{
6832 int r;
6833 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6834 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6835 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6836 if (r != EMULATE_DONE)
6837 return 0;
6838 return 1;
6839}
6840
6841static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6842{
6843 BUG_ON(!vcpu->arch.pio.count);
6844
6845 return complete_emulated_io(vcpu);
6846}
6847
f78146b0
AK		 6848/*
6849 * Implements the following, as a state machine:
6850 *
6851 * read:
6852 * for each fragment
87da7e66
XG		 6853 * for each mmio piece in the fragment
6854 * write gpa, len
6855 * exit
6856 * copy data
f78146b0
AK		 6857 * execute insn
6858 *
6859 * write:
6860 * for each fragment
87da7e66
XG		 6861 * for each mmio piece in the fragment
6862 * write gpa, len
6863 * copy data
6864 * exit
f78146b0 6865 */
716d51ab 6866static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6867{
6868 struct kvm_run *run = vcpu->run;
f78146b0 6869 struct kvm_mmio_fragment *frag;
87da7e66 6870 unsigned len;
5287f194 6871
716d51ab 6872 BUG_ON(!vcpu->mmio_needed);
5287f194 6873
716d51ab 6874 /* Complete previous fragment */
87da7e66
XG		 6875 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6876 len = min(8u, frag->len);
716d51ab 6877 if (!vcpu->mmio_is_write)
87da7e66
XG		 6878 memcpy(frag->data, run->mmio.data, len);
6879
6880 if (frag->len <= 8) {
6881 /* Switch to the next fragment. */
6882 frag++;
6883 vcpu->mmio_cur_fragment++;
6884 } else {
6885 /* Go forward to the next mmio piece. */
6886 frag->data += len;
6887 frag->gpa += len;
6888 frag->len -= len;
6889 }
6890
a08d3b3b 6891 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6892 vcpu->mmio_needed = 0;
0912c977
PB		 6893
6894 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6895 if (vcpu->mmio_is_write)
716d51ab
GN		 6896 return 1;
6897 vcpu->mmio_read_completed = 1;
6898 return complete_emulated_io(vcpu);
6899 }
87da7e66 6900
716d51ab
GN		 6901 run->exit_reason = KVM_EXIT_MMIO;
6902 run->mmio.phys_addr = frag->gpa;
6903 if (vcpu->mmio_is_write)
87da7e66
XG		 6904 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6905 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6906 run->mmio.is_write = vcpu->mmio_is_write;
6907 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6908 return 0;
5287f194
AK		 6909}
6910
716d51ab 6911
b6c7a5dc
HB		 6912int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6913{
c5bedc68 6914 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6915 int r;
6916 sigset_t sigsaved;
6917
c4d72e2d 6918 fpu__activate_curr(fpu);
e5c30142 6919
ac9f6dc0
AK		 6920 if (vcpu->sigset_active)
6921 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6922
a4535290 6923 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6924 kvm_vcpu_block(vcpu);
66450a21 6925 kvm_apic_accept_events(vcpu);
d7690175 6926 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6927 r = -EAGAIN;
6928 goto out;
b6c7a5dc
HB		 6929 }
6930
b6c7a5dc 6931 /* re-sync apic's tpr */
35754c98 6932 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6933 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6934 r = -EINVAL;
6935 goto out;
6936 }
6937 }
b6c7a5dc 6938
716d51ab
GN		 6939 if (unlikely(vcpu->arch.complete_userspace_io)) {
6940 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6941 vcpu->arch.complete_userspace_io = NULL;
6942 r = cui(vcpu);
6943 if (r <= 0)
6944 goto out;
6945 } else
6946 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6947
362c698f 6948 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6949
6950out:
f1d86e46 6951 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6952 if (vcpu->sigset_active)
6953 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6954
b6c7a5dc
HB		 6955 return r;
6956}
6957
6958int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6959{
7ae441ea
GN		 6960 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6961 /*
6962 * We are here if userspace calls get_regs() in the middle of
6963 * instruction emulation. Registers state needs to be copied
4a969980 6964 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6965 * that usually, but some bad designed PV devices (vmware
6966 * backdoor interface) need this to work
6967 */
dd856efa 6968 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6969 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6970 }
5fdbf976
MT		 6971 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6972 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6973 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6974 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6975 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6976 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6977 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6978 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6979#ifdef CONFIG_X86_64
5fdbf976
MT		 6980 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6981 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6982 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6983 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6984 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6985 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6986 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6987 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6988#endif
6989
5fdbf976 6990 regs->rip = kvm_rip_read(vcpu);
91586a3b 6991 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6992
b6c7a5dc
HB		 6993 return 0;
6994}
6995
6996int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6997{
7ae441ea
GN		 6998 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6999 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7000
5fdbf976
MT		 7001 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7002 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7003 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7004 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7005 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7006 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7007 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7008 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7009#ifdef CONFIG_X86_64
5fdbf976
MT		 7010 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7011 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7012 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7013 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7014 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7015 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7016 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7017 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7018#endif
7019
5fdbf976 7020 kvm_rip_write(vcpu, regs->rip);
91586a3b 7021 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7022
b4f14abd
JK		 7023 vcpu->arch.exception.pending = false;
7024
3842d135
AK		 7025 kvm_make_request(KVM_REQ_EVENT, vcpu);
7026
b6c7a5dc
HB		 7027 return 0;
7028}
7029
b6c7a5dc
HB		 7030void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7031{
7032 struct kvm_segment cs;
7033
3e6e0aab 7034 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7035 *db = cs.db;
7036 *l = cs.l;
7037}
7038EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7039
7040int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7041 struct kvm_sregs *sregs)
7042{
89a27f4d 7043 struct desc_ptr dt;
b6c7a5dc 7044
3e6e0aab
GT		 7045 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7046 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7047 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7048 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7049 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7050 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7051
3e6e0aab
GT		 7052 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7053 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7054
7055 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7056 sregs->idt.limit = dt.size;
7057 sregs->idt.base = dt.address;
b6c7a5dc 7058 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7059 sregs->gdt.limit = dt.size;
7060 sregs->gdt.base = dt.address;
b6c7a5dc 7061
4d4ec087 7062 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7063 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7064 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7065 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7066 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7067 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7068 sregs->apic_base = kvm_get_apic_base(vcpu);
7069
923c61bb 7070 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7071
36752c9b 7072 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7073 set_bit(vcpu->arch.interrupt.nr,
7074 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7075
b6c7a5dc
HB		 7076 return 0;
7077}
7078
62d9f0db
MT		 7079int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7080 struct kvm_mp_state *mp_state)
7081{
66450a21 7082 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7083 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7084 vcpu->arch.pv.pv_unhalted)
7085 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7086 else
7087 mp_state->mp_state = vcpu->arch.mp_state;
7088
62d9f0db
MT		 7089 return 0;
7090}
7091
7092int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7093 struct kvm_mp_state *mp_state)
7094{
bce87cce 7095 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7096 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7097 return -EINVAL;
7098
7099 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7100 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7101 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7102 } else
7103 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7104 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7105 return 0;
7106}
7107
7f3d35fd
KW		 7108int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7109 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7110{
9d74191a 7111 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7112 int ret;
e01c2426 7113
8ec4722d 7114 init_emulate_ctxt(vcpu);
c697518a 7115
7f3d35fd 7116 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7117 has_error_code, error_code);
c697518a 7118
c697518a 7119 if (ret)
19d04437 7120 return EMULATE_FAIL;
37817f29 7121
9d74191a
TY		 7122 kvm_rip_write(vcpu, ctxt->eip);
7123 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7124 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7125 return EMULATE_DONE;
37817f29
IE		 7126}
7127EXPORT_SYMBOL_GPL(kvm_task_switch);
7128
b6c7a5dc
HB		 7129int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7130 struct kvm_sregs *sregs)
7131{
58cb628d 7132 struct msr_data apic_base_msr;
b6c7a5dc 7133 int mmu_reset_needed = 0;
63f42e02 7134 int pending_vec, max_bits, idx;
89a27f4d 7135 struct desc_ptr dt;
b6c7a5dc 7136
6d1068b3
PM		 7137 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7138 return -EINVAL;
7139
89a27f4d
GN		 7140 dt.size = sregs->idt.limit;
7141 dt.address = sregs->idt.base;
b6c7a5dc 7142 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7143 dt.size = sregs->gdt.limit;
7144 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7145 kvm_x86_ops->set_gdt(vcpu, &dt);
7146
ad312c7c 7147 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7148 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7149 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7150 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7151
2d3ad1f4 7152 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7153
f6801dff 7154 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7155 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7156 apic_base_msr.data = sregs->apic_base;
7157 apic_base_msr.host_initiated = true;
7158 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7159
4d4ec087 7160 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7161 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7162 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7163
fc78f519 7164 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7165 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7166 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7167 kvm_update_cpuid(vcpu);
63f42e02
XG		 7168
7169 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7170 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7171 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7172 mmu_reset_needed = 1;
7173 }
63f42e02 7174 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7175
7176 if (mmu_reset_needed)
7177 kvm_mmu_reset_context(vcpu);
7178
a50abc3b 7179 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7180 pending_vec = find_first_bit(
7181 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7182 if (pending_vec < max_bits) {
66fd3f7f 7183 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7184 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7185 }
7186
3e6e0aab
GT		 7187 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7188 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7189 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7190 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7191 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7192 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7193
3e6e0aab
GT		 7194 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7195 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7196
5f0269f5
ME		 7197 update_cr8_intercept(vcpu);
7198
9c3e4aab 7199 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7200 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7201 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7202 !is_protmode(vcpu))
9c3e4aab
MT		 7203 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7204
3842d135
AK		 7205 kvm_make_request(KVM_REQ_EVENT, vcpu);
7206
b6c7a5dc
HB		 7207 return 0;
7208}
7209
d0bfb940
JK		 7210int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7211 struct kvm_guest_debug *dbg)
b6c7a5dc 7212{
355be0b9 7213 unsigned long rflags;
ae675ef0 7214 int i, r;
b6c7a5dc 7215
4f926bf2
JK		 7216 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7217 r = -EBUSY;
7218 if (vcpu->arch.exception.pending)
2122ff5e 7219 goto out;
4f926bf2
JK		 7220 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7221 kvm_queue_exception(vcpu, DB_VECTOR);
7222 else
7223 kvm_queue_exception(vcpu, BP_VECTOR);
7224 }
7225
91586a3b
JK		 7226 /*
7227 * Read rflags as long as potentially injected trace flags are still
7228 * filtered out.
7229 */
7230 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7231
7232 vcpu->guest_debug = dbg->control;
7233 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7234 vcpu->guest_debug = 0;
7235
7236 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7237 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7238 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7239 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7240 } else {
7241 for (i = 0; i < KVM_NR_DB_REGS; i++)
7242 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7243 }
c8639010 7244 kvm_update_dr7(vcpu);
ae675ef0 7245
f92653ee
JK		 7246 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7247 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7248 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7249
91586a3b
JK		 7250 /*
7251 * Trigger an rflags update that will inject or remove the trace
7252 * flags.
7253 */
7254 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7255
a96036b8 7256 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7257
4f926bf2 7258 r = 0;
d0bfb940 7259
2122ff5e 7260out:
b6c7a5dc
HB		 7261
7262 return r;
7263}
7264
8b006791
ZX		 7265/*
7266 * Translate a guest virtual address to a guest physical address.
7267 */
7268int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7269 struct kvm_translation *tr)
7270{
7271 unsigned long vaddr = tr->linear_address;
7272 gpa_t gpa;
f656ce01 7273 int idx;
8b006791 7274
f656ce01 7275 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7276 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7277 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7278 tr->physical_address = gpa;
7279 tr->valid = gpa != UNMAPPED_GVA;
7280 tr->writeable = 1;
7281 tr->usermode = 0;
8b006791
ZX		 7282
7283 return 0;
7284}
7285
d0752060
HB		 7286int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7287{
c47ada30 7288 struct fxregs_state *fxsave =
7366ed77 7289 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7290
d0752060
HB		 7291 memcpy(fpu->fpr, fxsave->st_space, 128);
7292 fpu->fcw = fxsave->cwd;
7293 fpu->fsw = fxsave->swd;
7294 fpu->ftwx = fxsave->twd;
7295 fpu->last_opcode = fxsave->fop;
7296 fpu->last_ip = fxsave->rip;
7297 fpu->last_dp = fxsave->rdp;
7298 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7299
d0752060
HB		 7300 return 0;
7301}
7302
7303int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7304{
c47ada30 7305 struct fxregs_state *fxsave =
7366ed77 7306 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7307
d0752060
HB		 7308 memcpy(fxsave->st_space, fpu->fpr, 128);
7309 fxsave->cwd = fpu->fcw;
7310 fxsave->swd = fpu->fsw;
7311 fxsave->twd = fpu->ftwx;
7312 fxsave->fop = fpu->last_opcode;
7313 fxsave->rip = fpu->last_ip;
7314 fxsave->rdp = fpu->last_dp;
7315 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7316
d0752060
HB		 7317 return 0;
7318}
7319
0ee6a517 7320static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7321{
bf935b0b 7322 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7323 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7324 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7325 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7326
2acf923e
DC		 7327 /*
7328 * Ensure guest xcr0 is valid for loading
7329 */
d91cab78 7330 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7331
ad312c7c 7332 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7333}
d0752060
HB		 7334
7335void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7336{
2608d7a1 7337 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7338 return;
7339
2acf923e
DC		 7340 /*
7341 * Restore all possible states in the guest,
7342 * and assume host would use all available bits.
7343 * Guest xcr0 would be loaded later.
7344 */
d0752060 7345 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7346 __kernel_fpu_begin();
003e2e8b 7347 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7348 trace_kvm_fpu(1);
d0752060 7349}
d0752060
HB		 7350
7351void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7352{
653f52c3
RR		 7353 if (!vcpu->guest_fpu_loaded) {
7354 vcpu->fpu_counter = 0;
d0752060 7355 return;
653f52c3 7356 }
d0752060
HB		 7357
7358 vcpu->guest_fpu_loaded = 0;
4f836347 7359 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7360 __kernel_fpu_end();
f096ed85 7361 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7362 /*
7363 * If using eager FPU mode, or if the guest is a frequent user
7364 * of the FPU, just leave the FPU active for next time.
7365 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7366 * the FPU in bursts will revert to loading it on demand.
7367 */
5a5fbdc0 7368 if (!use_eager_fpu()) {
653f52c3
RR		 7369 if (++vcpu->fpu_counter < 5)
7370 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7371 }
0c04851c 7372 trace_kvm_fpu(0);
d0752060 7373}
e9b11c17
ZX		 7374
7375void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7376{
12f9a48f 7377 kvmclock_reset(vcpu);
7f1ea208 7378
f5f48ee1 7379 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7380 kvm_x86_ops->vcpu_free(vcpu);
7381}
7382
7383struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7384 unsigned int id)
7385{
c447e76b
LL		 7386 struct kvm_vcpu *vcpu;
7387
6755bae8
ZA		 7388 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7389 printk_once(KERN_WARNING
7390 "kvm: SMP vm created on host with unstable TSC; "
7391 "guest TSC will not be reliable\n");
c447e76b
LL		 7392
7393 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7394
c447e76b 7395 return vcpu;
26e5215f 7396}
e9b11c17 7397
26e5215f
AK		 7398int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7399{
7400 int r;
e9b11c17 7401
19efffa2 7402 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7403 r = vcpu_load(vcpu);
7404 if (r)
7405 return r;
d28bc9dd 7406 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7407 kvm_mmu_setup(vcpu);
e9b11c17 7408 vcpu_put(vcpu);
26e5215f 7409 return r;
e9b11c17
ZX		 7410}
7411
31928aa5 7412void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7413{
8fe8ab46 7414 struct msr_data msr;
332967a3 7415 struct kvm *kvm = vcpu->kvm;
42897d86 7416
31928aa5
DD		 7417 if (vcpu_load(vcpu))
7418 return;
8fe8ab46
WA		 7419 msr.data = 0x0;
7420 msr.index = MSR_IA32_TSC;
7421 msr.host_initiated = true;
7422 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7423 vcpu_put(vcpu);
7424
630994b3
MT		 7425 if (!kvmclock_periodic_sync)
7426 return;
7427
332967a3
AJ		 7428 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7429 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7430}
7431
d40ccc62 7432void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7433{
9fc77441 7434 int r;
344d9588
GN		 7435 vcpu->arch.apf.msr_val = 0;
7436
9fc77441
MT		 7437 r = vcpu_load(vcpu);
7438 BUG_ON(r);
e9b11c17
ZX		 7439 kvm_mmu_unload(vcpu);
7440 vcpu_put(vcpu);
7441
7442 kvm_x86_ops->vcpu_free(vcpu);
7443}
7444
d28bc9dd 7445void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7446{
e69fab5d
PB		 7447 vcpu->arch.hflags = 0;
7448
c43203ca 7449 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7450 atomic_set(&vcpu->arch.nmi_queued, 0);
7451 vcpu->arch.nmi_pending = 0;
448fa4a9 7452 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7453 kvm_clear_interrupt_queue(vcpu);
7454 kvm_clear_exception_queue(vcpu);
448fa4a9 7455
42dbaa5a 7456 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7457 kvm_update_dr0123(vcpu);
6f43ed01 7458 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7459 kvm_update_dr6(vcpu);
42dbaa5a 7460 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7461 kvm_update_dr7(vcpu);
42dbaa5a 7462
1119022c
NA		 7463 vcpu->arch.cr2 = 0;
7464
3842d135 7465 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7466 vcpu->arch.apf.msr_val = 0;
c9aaa895 7467 vcpu->arch.st.msr_val = 0;
3842d135 7468
12f9a48f
GC		 7469 kvmclock_reset(vcpu);
7470
af585b92
GN		 7471 kvm_clear_async_pf_completion_queue(vcpu);
7472 kvm_async_pf_hash_reset(vcpu);
7473 vcpu->arch.apf.halted = false;
3842d135 7474
64d60670 7475 if (!init_event) {
d28bc9dd 7476 kvm_pmu_reset(vcpu);
64d60670
PB		 7477 vcpu->arch.smbase = 0x30000;
7478 }
f5132b01 7479
66f7b72e
JS		 7480 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7481 vcpu->arch.regs_avail = ~0;
7482 vcpu->arch.regs_dirty = ~0;
7483
d28bc9dd 7484 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7485}
7486
2b4a273b 7487void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7488{
7489 struct kvm_segment cs;
7490
7491 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7492 cs.selector = vector << 8;
7493 cs.base = vector << 12;
7494 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7495 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7496}
7497
13a34e06 7498int kvm_arch_hardware_enable(void)
e9b11c17 7499{
ca84d1a2
ZA		 7500 struct kvm *kvm;
7501 struct kvm_vcpu *vcpu;
7502 int i;
0dd6a6ed
ZA		 7503 int ret;
7504 u64 local_tsc;
7505 u64 max_tsc = 0;
7506 bool stable, backwards_tsc = false;
18863bdd
AK		 7507
7508 kvm_shared_msr_cpu_online();
13a34e06 7509 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7510 if (ret != 0)
7511 return ret;
7512
4ea1636b 7513 local_tsc = rdtsc();
0dd6a6ed
ZA		 7514 stable = !check_tsc_unstable();
7515 list_for_each_entry(kvm, &vm_list, vm_list) {
7516 kvm_for_each_vcpu(i, vcpu, kvm) {
7517 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7518 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7519 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7520 backwards_tsc = true;
7521 if (vcpu->arch.last_host_tsc > max_tsc)
7522 max_tsc = vcpu->arch.last_host_tsc;
7523 }
7524 }
7525 }
7526
7527 /*
7528 * Sometimes, even reliable TSCs go backwards. This happens on
7529 * platforms that reset TSC during suspend or hibernate actions, but
7530 * maintain synchronization. We must compensate. Fortunately, we can
7531 * detect that condition here, which happens early in CPU bringup,
7532 * before any KVM threads can be running. Unfortunately, we can't
7533 * bring the TSCs fully up to date with real time, as we aren't yet far
7534 * enough into CPU bringup that we know how much real time has actually
7535 * elapsed; our helper function, get_kernel_ns() will be using boot
7536 * variables that haven't been updated yet.
7537 *
7538 * So we simply find the maximum observed TSC above, then record the
7539 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7540 * the adjustment will be applied. Note that we accumulate
7541 * adjustments, in case multiple suspend cycles happen before some VCPU
7542 * gets a chance to run again. In the event that no KVM threads get a
7543 * chance to run, we will miss the entire elapsed period, as we'll have
7544 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7545 * loose cycle time. This isn't too big a deal, since the loss will be
7546 * uniform across all VCPUs (not to mention the scenario is extremely
7547 * unlikely). It is possible that a second hibernate recovery happens
7548 * much faster than a first, causing the observed TSC here to be
7549 * smaller; this would require additional padding adjustment, which is
7550 * why we set last_host_tsc to the local tsc observed here.
7551 *
7552 * N.B. - this code below runs only on platforms with reliable TSC,
7553 * as that is the only way backwards_tsc is set above. Also note
7554 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7555 * have the same delta_cyc adjustment applied if backwards_tsc
7556 * is detected. Note further, this adjustment is only done once,
7557 * as we reset last_host_tsc on all VCPUs to stop this from being
7558 * called multiple times (one for each physical CPU bringup).
7559 *
4a969980 7560 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7561 * will be compensated by the logic in vcpu_load, which sets the TSC to
7562 * catchup mode. This will catchup all VCPUs to real time, but cannot
7563 * guarantee that they stay in perfect synchronization.
7564 */
7565 if (backwards_tsc) {
7566 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7567 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7568 list_for_each_entry(kvm, &vm_list, vm_list) {
7569 kvm_for_each_vcpu(i, vcpu, kvm) {
7570 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7571 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7572 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7573 }
7574
7575 /*
7576 * We have to disable TSC offset matching.. if you were
7577 * booting a VM while issuing an S4 host suspend....
7578 * you may have some problem. Solving this issue is
7579 * left as an exercise to the reader.
7580 */
7581 kvm->arch.last_tsc_nsec = 0;
7582 kvm->arch.last_tsc_write = 0;
7583 }
7584
7585 }
7586 return 0;
e9b11c17
ZX		 7587}
7588
13a34e06 7589void kvm_arch_hardware_disable(void)
e9b11c17 7590{
13a34e06
RK		 7591 kvm_x86_ops->hardware_disable();
7592 drop_user_return_notifiers();
e9b11c17
ZX		 7593}
7594
7595int kvm_arch_hardware_setup(void)
7596{
9e9c3fe4
NA		 7597 int r;
7598
7599 r = kvm_x86_ops->hardware_setup();
7600 if (r != 0)
7601 return r;
7602
35181e86
HZ		 7603 if (kvm_has_tsc_control) {
7604 /*
7605 * Make sure the user can only configure tsc_khz values that
7606 * fit into a signed integer.
7607 * A min value is not calculated needed because it will always
7608 * be 1 on all machines.
7609 */
7610 u64 max = min(0x7fffffffULL,
7611 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7612 kvm_max_guest_tsc_khz = max;
7613
ad721883 7614 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7615 }
ad721883 7616
9e9c3fe4
NA		 7617 kvm_init_msr_list();
7618 return 0;
e9b11c17
ZX		 7619}
7620
7621void kvm_arch_hardware_unsetup(void)
7622{
7623 kvm_x86_ops->hardware_unsetup();
7624}
7625
7626void kvm_arch_check_processor_compat(void *rtn)
7627{
7628 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7629}
7630
7631bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7632{
7633 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7634}
7635EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7636
7637bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7638{
7639 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7640}
7641
3e515705
AK		 7642bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7643{
35754c98 7644 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7645}
7646
54e9818f 7647struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7648EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7649
e9b11c17
ZX		 7650int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7651{
7652 struct page *page;
7653 struct kvm *kvm;
7654 int r;
7655
7656 BUG_ON(vcpu->kvm == NULL);
7657 kvm = vcpu->kvm;
7658
d62caabb 7659 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7660 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7661 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7662 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7663 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7664 else
a4535290 7665 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7666
7667 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7668 if (!page) {
7669 r = -ENOMEM;
7670 goto fail;
7671 }
ad312c7c 7672 vcpu->arch.pio_data = page_address(page);
e9b11c17 7673
cc578287 7674 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7675
e9b11c17
ZX		 7676 r = kvm_mmu_create(vcpu);
7677 if (r < 0)
7678 goto fail_free_pio_data;
7679
7680 if (irqchip_in_kernel(kvm)) {
7681 r = kvm_create_lapic(vcpu);
7682 if (r < 0)
7683 goto fail_mmu_destroy;
54e9818f
GN		 7684 } else
7685 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7686
890ca9ae
HY		 7687 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7688 GFP_KERNEL);
7689 if (!vcpu->arch.mce_banks) {
7690 r = -ENOMEM;
443c39bc 7691 goto fail_free_lapic;
890ca9ae
HY		 7692 }
7693 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7694
f1797359
WY		 7695 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7696 r = -ENOMEM;
f5f48ee1 7697 goto fail_free_mce_banks;
f1797359 7698 }
f5f48ee1 7699
0ee6a517 7700 fx_init(vcpu);
66f7b72e 7701
ba904635 7702 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7703 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7704
7705 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7706 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7707
5a4f55cd
EK		 7708 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7709
74545705
RK		 7710 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7711
af585b92 7712 kvm_async_pf_hash_reset(vcpu);
f5132b01 7713 kvm_pmu_init(vcpu);
af585b92 7714
1c1a9ce9
SR		 7715 vcpu->arch.pending_external_vector = -1;
7716
5c919412
AS		 7717 kvm_hv_vcpu_init(vcpu);
7718
e9b11c17 7719 return 0;
0ee6a517 7720
f5f48ee1
SY		 7721fail_free_mce_banks:
7722 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7723fail_free_lapic:
7724 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7725fail_mmu_destroy:
7726 kvm_mmu_destroy(vcpu);
7727fail_free_pio_data:
ad312c7c 7728 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7729fail:
7730 return r;
7731}
7732
7733void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7734{
f656ce01
MT		 7735 int idx;
7736
1f4b34f8 7737 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7738 kvm_pmu_destroy(vcpu);
36cb93fd 7739 kfree(vcpu->arch.mce_banks);
e9b11c17 7740 kvm_free_lapic(vcpu);
f656ce01 7741 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7742 kvm_mmu_destroy(vcpu);
f656ce01 7743 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7744 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7745 if (!lapic_in_kernel(vcpu))
54e9818f 7746 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7747}
d19a9cd2 7748
e790d9ef
RK		 7749void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7750{
ae97a3b8 7751 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7752}
7753
e08b9637 7754int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7755{
e08b9637
CO		 7756 if (type)
7757 return -EINVAL;
7758
6ef768fa 7759 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7760 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7761 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7762 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7763 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7764
5550af4d
SY		 7765 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7766 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7767 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7768 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7769 &kvm->arch.irq_sources_bitmap);
5550af4d 7770
038f8c11 7771 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7772 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7773 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7774
7775 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7776
7e44e449 7777 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7778 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7779
0eb05bf2 7780 kvm_page_track_init(kvm);
13d268ca 7781 kvm_mmu_init_vm(kvm);
0eb05bf2 7782
03543133
SS		 7783 if (kvm_x86_ops->vm_init)
7784 return kvm_x86_ops->vm_init(kvm);
7785
d89f5eff 7786 return 0;
d19a9cd2
ZX		 7787}
7788
7789static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7790{
9fc77441
MT		 7791 int r;
7792 r = vcpu_load(vcpu);
7793 BUG_ON(r);
d19a9cd2
ZX		 7794 kvm_mmu_unload(vcpu);
7795 vcpu_put(vcpu);
7796}
7797
7798static void kvm_free_vcpus(struct kvm *kvm)
7799{
7800 unsigned int i;
988a2cae 7801 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7802
7803 /*
7804 * Unpin any mmu pages first.
7805 */
af585b92
GN		 7806 kvm_for_each_vcpu(i, vcpu, kvm) {
7807 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7808 kvm_unload_vcpu_mmu(vcpu);
af585b92 7809 }
988a2cae
GN		 7810 kvm_for_each_vcpu(i, vcpu, kvm)
7811 kvm_arch_vcpu_free(vcpu);
7812
7813 mutex_lock(&kvm->lock);
7814 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7815 kvm->vcpus[i] = NULL;
d19a9cd2 7816
988a2cae
GN		 7817 atomic_set(&kvm->online_vcpus, 0);
7818 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7819}
7820
ad8ba2cd
SY		 7821void kvm_arch_sync_events(struct kvm *kvm)
7822{
332967a3 7823 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7824 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7825 kvm_free_all_assigned_devices(kvm);
aea924f6 7826 kvm_free_pit(kvm);
ad8ba2cd
SY		 7827}
7828
1d8007bd 7829int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7830{
7831 int i, r;
25188b99 7832 unsigned long hva;
f0d648bd
PB		 7833 struct kvm_memslots *slots = kvm_memslots(kvm);
7834 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7835
7836 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7837 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7838 return -EINVAL;
9da0e4d5 7839
f0d648bd
PB		 7840 slot = id_to_memslot(slots, id);
7841 if (size) {
b21629da 7842 if (slot->npages)
f0d648bd
PB		 7843 return -EEXIST;
7844
7845 /*
7846 * MAP_SHARED to prevent internal slot pages from being moved
7847 * by fork()/COW.
7848 */
7849 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7850 MAP_SHARED | MAP_ANONYMOUS, 0);
7851 if (IS_ERR((void *)hva))
7852 return PTR_ERR((void *)hva);
7853 } else {
7854 if (!slot->npages)
7855 return 0;
7856
7857 hva = 0;
7858 }
7859
7860 old = *slot;
9da0e4d5 7861 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7862 struct kvm_userspace_memory_region m;
9da0e4d5 7863
1d8007bd
PB		 7864 m.slot = id | (i << 16);
7865 m.flags = 0;
7866 m.guest_phys_addr = gpa;
f0d648bd 7867 m.userspace_addr = hva;
1d8007bd 7868 m.memory_size = size;
9da0e4d5
PB		 7869 r = __kvm_set_memory_region(kvm, &m);
7870 if (r < 0)
7871 return r;
7872 }
7873
f0d648bd
PB		 7874 if (!size) {
7875 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7876 WARN_ON(r < 0);
7877 }
7878
9da0e4d5
PB		 7879 return 0;
7880}
7881EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7882
1d8007bd 7883int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7884{
7885 int r;
7886
7887 mutex_lock(&kvm->slots_lock);
1d8007bd 7888 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7889 mutex_unlock(&kvm->slots_lock);
7890
7891 return r;
7892}
7893EXPORT_SYMBOL_GPL(x86_set_memory_region);
7894
d19a9cd2
ZX		 7895void kvm_arch_destroy_vm(struct kvm *kvm)
7896{
27469d29
AH		 7897 if (current->mm == kvm->mm) {
7898 /*
7899 * Free memory regions allocated on behalf of userspace,
7900 * unless the the memory map has changed due to process exit
7901 * or fd copying.
7902 */
1d8007bd
PB		 7903 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7904 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7905 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7906 }
03543133
SS		 7907 if (kvm_x86_ops->vm_destroy)
7908 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7909 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7910 kfree(kvm->arch.vpic);
7911 kfree(kvm->arch.vioapic);
d19a9cd2 7912 kvm_free_vcpus(kvm);
1e08ec4a 7913 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7914 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7915}
0de10343 7916
5587027c 7917void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7918 struct kvm_memory_slot *dont)
7919{
7920 int i;
7921
d89cc617
TY		 7922 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7923 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7924 kvfree(free->arch.rmap[i]);
d89cc617 7925 free->arch.rmap[i] = NULL;
77d11309 7926 }
d89cc617
TY		 7927 if (i == 0)
7928 continue;
7929
7930 if (!dont || free->arch.lpage_info[i - 1] !=
7931 dont->arch.lpage_info[i - 1]) {
548ef284 7932 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7933 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7934 }
7935 }
21ebbeda
XG		 7936
7937 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7938}
7939
5587027c
AK		 7940int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7941 unsigned long npages)
db3fe4eb
TY		 7942{
7943 int i;
7944
d89cc617 7945 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7946 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7947 unsigned long ugfn;
7948 int lpages;
d89cc617 7949 int level = i + 1;
db3fe4eb
TY		 7950
7951 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7952 slot->base_gfn, level) + 1;
7953
d89cc617
TY		 7954 slot->arch.rmap[i] =
7955 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7956 if (!slot->arch.rmap[i])
77d11309 7957 goto out_free;
d89cc617
TY		 7958 if (i == 0)
7959 continue;
77d11309 7960
92f94f1e
XG		 7961 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7962 if (!linfo)
db3fe4eb
TY		 7963 goto out_free;
7964
92f94f1e
XG		 7965 slot->arch.lpage_info[i - 1] = linfo;
7966
db3fe4eb 7967 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7968 linfo[0].disallow_lpage = 1;
db3fe4eb 7969 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7970 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7971 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7972 /*
7973 * If the gfn and userspace address are not aligned wrt each
7974 * other, or if explicitly asked to, disable large page
7975 * support for this slot
7976 */
7977 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7978 !kvm_largepages_enabled()) {
7979 unsigned long j;
7980
7981 for (j = 0; j < lpages; ++j)
92f94f1e 7982 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7983 }
7984 }
7985
21ebbeda
XG		 7986 if (kvm_page_track_create_memslot(slot, npages))
7987 goto out_free;
7988
db3fe4eb
TY		 7989 return 0;
7990
7991out_free:
d89cc617 7992 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7993 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7994 slot->arch.rmap[i] = NULL;
7995 if (i == 0)
7996 continue;
7997
548ef284 7998 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7999 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8000 }
8001 return -ENOMEM;
8002}
8003
15f46015 8004void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8005{
e6dff7d1
TY		 8006 /*
8007 * memslots->generation has been incremented.
8008 * mmio generation may have reached its maximum value.
8009 */
54bf36aa 8010 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8011}
8012
f7784b8e
MT		 8013int kvm_arch_prepare_memory_region(struct kvm *kvm,
8014 struct kvm_memory_slot *memslot,
09170a49 8015 const struct kvm_userspace_memory_region *mem,
7b6195a9 8016 enum kvm_mr_change change)
0de10343 8017{
f7784b8e
MT		 8018 return 0;
8019}
8020
88178fd4
KH		 8021static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8022 struct kvm_memory_slot *new)
8023{
8024 /* Still write protect RO slot */
8025 if (new->flags & KVM_MEM_READONLY) {
8026 kvm_mmu_slot_remove_write_access(kvm, new);
8027 return;
8028 }
8029
8030 /*
8031 * Call kvm_x86_ops dirty logging hooks when they are valid.
8032 *
8033 * kvm_x86_ops->slot_disable_log_dirty is called when:
8034 *
8035 * - KVM_MR_CREATE with dirty logging is disabled
8036 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8037 *
8038 * The reason is, in case of PML, we need to set D-bit for any slots
8039 * with dirty logging disabled in order to eliminate unnecessary GPA
8040 * logging in PML buffer (and potential PML buffer full VMEXT). This
8041 * guarantees leaving PML enabled during guest's lifetime won't have
8042 * any additonal overhead from PML when guest is running with dirty
8043 * logging disabled for memory slots.
8044 *
8045 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8046 * to dirty logging mode.
8047 *
8048 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8049 *
8050 * In case of write protect:
8051 *
8052 * Write protect all pages for dirty logging.
8053 *
8054 * All the sptes including the large sptes which point to this
8055 * slot are set to readonly. We can not create any new large
8056 * spte on this slot until the end of the logging.
8057 *
8058 * See the comments in fast_page_fault().
8059 */
8060 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8061 if (kvm_x86_ops->slot_enable_log_dirty)
8062 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8063 else
8064 kvm_mmu_slot_remove_write_access(kvm, new);
8065 } else {
8066 if (kvm_x86_ops->slot_disable_log_dirty)
8067 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8068 }
8069}
8070
f7784b8e 8071void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8072 const struct kvm_userspace_memory_region *mem,
8482644a 8073 const struct kvm_memory_slot *old,
f36f3f28 8074 const struct kvm_memory_slot *new,
8482644a 8075 enum kvm_mr_change change)
f7784b8e 8076{
8482644a 8077 int nr_mmu_pages = 0;
f7784b8e 8078
48c0e4e9
XG		 8079 if (!kvm->arch.n_requested_mmu_pages)
8080 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8081
48c0e4e9 8082 if (nr_mmu_pages)
0de10343 8083 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8084
3ea3b7fa
WL		 8085 /*
8086 * Dirty logging tracks sptes in 4k granularity, meaning that large
8087 * sptes have to be split. If live migration is successful, the guest
8088 * in the source machine will be destroyed and large sptes will be
8089 * created in the destination. However, if the guest continues to run
8090 * in the source machine (for example if live migration fails), small
8091 * sptes will remain around and cause bad performance.
8092 *
8093 * Scan sptes if dirty logging has been stopped, dropping those
8094 * which can be collapsed into a single large-page spte. Later
8095 * page faults will create the large-page sptes.
8096 */
8097 if ((change != KVM_MR_DELETE) &&
8098 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8099 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8100 kvm_mmu_zap_collapsible_sptes(kvm, new);
8101
c972f3b1 8102 /*
88178fd4 8103 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8104 *
88178fd4
KH		 8105 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8106 * been zapped so no dirty logging staff is needed for old slot. For
8107 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8108 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8109 *
8110 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8111 */
88178fd4 8112 if (change != KVM_MR_DELETE)
f36f3f28 8113 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8114}
1d737c8a 8115
2df72e9b 8116void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8117{
6ca18b69 8118 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8119}
8120
2df72e9b
MT		 8121void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8122 struct kvm_memory_slot *slot)
8123{
6ca18b69 8124 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8125}
8126
5d9bc648
PB		 8127static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8128{
8129 if (!list_empty_careful(&vcpu->async_pf.done))
8130 return true;
8131
8132 if (kvm_apic_has_events(vcpu))
8133 return true;
8134
8135 if (vcpu->arch.pv.pv_unhalted)
8136 return true;
8137
8138 if (atomic_read(&vcpu->arch.nmi_queued))
8139 return true;
8140
73917739
PB		 8141 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8142 return true;
8143
5d9bc648
PB		 8144 if (kvm_arch_interrupt_allowed(vcpu) &&
8145 kvm_cpu_has_interrupt(vcpu))
8146 return true;
8147
1f4b34f8
AS		 8148 if (kvm_hv_has_stimer_pending(vcpu))
8149 return true;
8150
5d9bc648
PB		 8151 return false;
8152}
8153
1d737c8a
ZX		 8154int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8155{
b6b8a145
JK		 8156 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8157 kvm_x86_ops->check_nested_events(vcpu, false);
8158
5d9bc648 8159 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8160}
5736199a 8161
b6d33834 8162int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8163{
b6d33834 8164 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8165}
78646121
GN		 8166
8167int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8168{
8169 return kvm_x86_ops->interrupt_allowed(vcpu);
8170}
229456fc 8171
82b32774 8172unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8173{
82b32774
NA		 8174 if (is_64_bit_mode(vcpu))
8175 return kvm_rip_read(vcpu);
8176 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8177 kvm_rip_read(vcpu));
8178}
8179EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8180
82b32774
NA		 8181bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8182{
8183 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8184}
8185EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8186
94fe45da
JK		 8187unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8188{
8189 unsigned long rflags;
8190
8191 rflags = kvm_x86_ops->get_rflags(vcpu);
8192 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8193 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8194 return rflags;
8195}
8196EXPORT_SYMBOL_GPL(kvm_get_rflags);
8197
6addfc42 8198static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8199{
8200 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8201 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8202 rflags |= X86_EFLAGS_TF;
94fe45da 8203 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8204}
8205
8206void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8207{
8208 __kvm_set_rflags(vcpu, rflags);
3842d135 8209 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8210}
8211EXPORT_SYMBOL_GPL(kvm_set_rflags);
8212
56028d08
GN		 8213void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8214{
8215 int r;
8216
fb67e14f 8217 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8218 work->wakeup_all)
56028d08
GN		 8219 return;
8220
8221 r = kvm_mmu_reload(vcpu);
8222 if (unlikely(r))
8223 return;
8224
fb67e14f
XG		 8225 if (!vcpu->arch.mmu.direct_map &&
8226 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8227 return;
8228
56028d08
GN		 8229 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8230}
8231
af585b92
GN		 8232static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8233{
8234 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8235}
8236
8237static inline u32 kvm_async_pf_next_probe(u32 key)
8238{
8239 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8240}
8241
8242static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8243{
8244 u32 key = kvm_async_pf_hash_fn(gfn);
8245
8246 while (vcpu->arch.apf.gfns[key] != ~0)
8247 key = kvm_async_pf_next_probe(key);
8248
8249 vcpu->arch.apf.gfns[key] = gfn;
8250}
8251
8252static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8253{
8254 int i;
8255 u32 key = kvm_async_pf_hash_fn(gfn);
8256
8257 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8258 (vcpu->arch.apf.gfns[key] != gfn &&
8259 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8260 key = kvm_async_pf_next_probe(key);
8261
8262 return key;
8263}
8264
8265bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8266{
8267 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8268}
8269
8270static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8271{
8272 u32 i, j, k;
8273
8274 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8275 while (true) {
8276 vcpu->arch.apf.gfns[i] = ~0;
8277 do {
8278 j = kvm_async_pf_next_probe(j);
8279 if (vcpu->arch.apf.gfns[j] == ~0)
8280 return;
8281 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8282 /*
8283 * k lies cyclically in ]i,j]
8284 * | i.k.j |
8285 * |....j i.k.| or |.k..j i...|
8286 */
8287 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8288 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8289 i = j;
8290 }
8291}
8292
7c90705b
GN		 8293static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8294{
8295
8296 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8297 sizeof(val));
8298}
8299
af585b92
GN		 8300void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8301 struct kvm_async_pf *work)
8302{
6389ee94
AK		 8303 struct x86_exception fault;
8304
7c90705b 8305 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8306 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8307
8308 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8309 (vcpu->arch.apf.send_user_only &&
8310 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8311 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8312 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8313 fault.vector = PF_VECTOR;
8314 fault.error_code_valid = true;
8315 fault.error_code = 0;
8316 fault.nested_page_fault = false;
8317 fault.address = work->arch.token;
8318 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8319 }
af585b92
GN		 8320}
8321
8322void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8323 struct kvm_async_pf *work)
8324{
6389ee94
AK		 8325 struct x86_exception fault;
8326
7c90705b 8327 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8328 if (work->wakeup_all)
7c90705b
GN		 8329 work->arch.token = ~0; /* broadcast wakeup */
8330 else
8331 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8332
8333 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8334 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8335 fault.vector = PF_VECTOR;
8336 fault.error_code_valid = true;
8337 fault.error_code = 0;
8338 fault.nested_page_fault = false;
8339 fault.address = work->arch.token;
8340 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8341 }
e6d53e3b 8342 vcpu->arch.apf.halted = false;
a4fa1635 8343 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8344}
8345
8346bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8347{
8348 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8349 return true;
8350 else
8351 return !kvm_event_needs_reinjection(vcpu) &&
8352 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8353}
8354
5544eb9b
PB		 8355void kvm_arch_start_assignment(struct kvm *kvm)
8356{
8357 atomic_inc(&kvm->arch.assigned_device_count);
8358}
8359EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8360
8361void kvm_arch_end_assignment(struct kvm *kvm)
8362{
8363 atomic_dec(&kvm->arch.assigned_device_count);
8364}
8365EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8366
8367bool kvm_arch_has_assigned_device(struct kvm *kvm)
8368{
8369 return atomic_read(&kvm->arch.assigned_device_count);
8370}
8371EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8372
e0f0bbc5
AW		 8373void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8374{
8375 atomic_inc(&kvm->arch.noncoherent_dma_count);
8376}
8377EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8378
8379void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8380{
8381 atomic_dec(&kvm->arch.noncoherent_dma_count);
8382}
8383EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8384
8385bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8386{
8387 return atomic_read(&kvm->arch.noncoherent_dma_count);
8388}
8389EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8390
14717e20
AW		 8391bool kvm_arch_has_irq_bypass(void)
8392{
8393 return kvm_x86_ops->update_pi_irte != NULL;
8394}
8395
87276880
FW		 8396int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8397 struct irq_bypass_producer *prod)
8398{
8399 struct kvm_kernel_irqfd *irqfd =
8400 container_of(cons, struct kvm_kernel_irqfd, consumer);
8401
14717e20 8402 irqfd->producer = prod;
87276880 8403
14717e20
AW		 8404 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8405 prod->irq, irqfd->gsi, 1);
87276880
FW		 8406}
8407
8408void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8409 struct irq_bypass_producer *prod)
8410{
8411 int ret;
8412 struct kvm_kernel_irqfd *irqfd =
8413 container_of(cons, struct kvm_kernel_irqfd, consumer);
8414
87276880
FW		 8415 WARN_ON(irqfd->producer != prod);
8416 irqfd->producer = NULL;
8417
8418 /*
8419 * When producer of consumer is unregistered, we change back to
8420 * remapped mode, so we can re-use the current implementation
bb3541f1 8421 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8422 * int this case doesn't want to receive the interrupts.
8423 */
8424 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8425 if (ret)
8426 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8427 " fails: %d\n", irqfd->consumer.token, ret);
8428}
8429
8430int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8431 uint32_t guest_irq, bool set)
8432{
8433 if (!kvm_x86_ops->update_pi_irte)
8434 return -EINVAL;
8435
8436 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8437}
8438
52004014
FW		 8439bool kvm_vector_hashing_enabled(void)
8440{
8441 return vector_hashing;
8442}
8443EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8444
229456fc 8445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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