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kvm/x86: Show WRMSR data is in hex
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
417bc304
HB		 193 { NULL }
194};
195
2acf923e
DC		 196u64 __read_mostly host_xcr0;
197
b6785def 198static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 199
af585b92
GN		 200static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201{
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205}
206
18863bdd
AK		 207static void kvm_on_user_return(struct user_return_notifier *urn)
208{
209 unsigned slot;
18863bdd
AK		 210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 212 struct kvm_shared_msr_values *values;
18863bdd
AK		 213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
18863bdd
AK		 219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223}
224
2bf78fa7 225static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 226{
18863bdd 227 u64 value;
013f6a5d
MT		 228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 230
2bf78fa7
SY		 231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240}
241
242void kvm_define_shared_msr(unsigned slot, u32 msr)
243{
0123be42 244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 245 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 248}
249EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251static void kvm_shared_msr_cpu_online(void)
252{
253 unsigned i;
18863bdd
AK		 254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 256 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 257}
258
8b3c3104 259int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 263 int err;
18863bdd 264
2bf78fa7 265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 266 return 0;
2bf78fa7 267 smsr->values[slot].curr = value;
8b3c3104
AH		 268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
18863bdd
AK		 272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
8b3c3104 277 return 0;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
13a34e06 281static void drop_user_return_notifiers(void)
3548bab5 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288}
289
6866b83e
CO		 290u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291{
8a5a87d9 292 return vcpu->arch.apic_base;
6866b83e
CO		 293}
294EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
58cb628d
JK		 296int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297{
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
6866b83e
CO		 316}
317EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
2605fc21 319asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 320{
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323}
324EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
3fd28fce
ED		 326#define EXCPT_BENIGN 0
327#define EXCPT_CONTRIBUTORY 1
328#define EXCPT_PF 2
329
330static int exception_class(int vector)
331{
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345}
346
d6e8c854
NA		 347#define EXCPT_FAULT 0
348#define EXCPT_TRAP 1
349#define EXCPT_ABORT 2
350#define EXCPT_INTERRUPT 3
351
352static int exception_type(int vector)
353{
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370}
371
3fd28fce 372static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
3fd28fce
ED		 375{
376 u32 prev_nr;
377 int class1, class2;
378
3842d135
AK		 379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
3fd28fce
ED		 381 if (!vcpu->arch.exception.pending) {
382 queue:
3ffb2468
NA		 383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
3fd28fce
ED		 385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
3f0fd292 389 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
a8eeb04a 397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414}
415
298101da
AK		 416void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
ce7ddec4 418 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 419}
420EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
ce7ddec4
JR		 422void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423{
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425}
426EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
db8fcefa 428void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 429{
db8fcefa
AP		 430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434}
435EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 436
6389ee94 437void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 438{
439 ++vcpu->stat.pf_guest;
6389ee94
AK		 440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 442}
27d6c865 443EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 444
ef54bcfe 445static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 446{
6389ee94
AK		 447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 449 else
6389ee94 450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 451
452 return fault->nested_page_fault;
d4f8cf66
JR		 453}
454
3419ffc8
SY		 455void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456{
7460fb4a
AK		 457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 459}
460EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
298101da
AK		 462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
ce7ddec4 464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 465}
466EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
ce7ddec4
JR		 468void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469{
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471}
472EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
0a79b009
AK		 474/*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 479{
0a79b009
AK		 480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
298101da 484}
0a79b009 485EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 486
16f8a6f9
NA		 487bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488{
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494}
495EXPORT_SYMBOL_GPL(kvm_require_dr);
496
ec92fe44
JR		 497/*
498 * This function will be used to read from the physical memory of the currently
54bf36aa 499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 500 * can read from guest physical or from the guest's guest physical memory.
501 */
502int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505{
54987b7a 506 struct x86_exception exception;
ec92fe44
JR		 507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
54987b7a 511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
54bf36aa 517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
69b0049a 521static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 522 void *data, int offset, int len, u32 access)
523{
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526}
527
a03490ed
CO		 528/*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
ff03a073 531int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 532{
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
ff03a073 537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 538
ff03a073
JR		 539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 547 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
ff03a073 556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 561out:
a03490ed
CO		 562
563 return ret;
564}
cc4b6871 565EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 566
d835dfec
AK		 567static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568{
ff03a073 569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 570 bool changed = true;
3d06b8bf
JR		 571 int offset;
572 gfn_t gfn;
d835dfec
AK		 573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
6de4f3ad
AK		 578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
9f8fe504
AK		 582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 586 if (r < 0)
587 goto out;
ff03a073 588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 589out:
d835dfec
AK		 590
591 return changed;
592}
593
49a9b07e 594int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 595{
aad82703 596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 598
f9a48e6a
AK		 599 cr0 |= X86_CR0_ET;
600
ab344828 601#ifdef CONFIG_X86_64
0f12244f
GN		 602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
ab344828
GN		 604#endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 607
0f12244f
GN		 608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
a03490ed 610
0f12244f
GN		 611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
a03490ed
CO		 613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615#ifdef CONFIG_X86_64
f6801dff 616 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 617 int cs_db, cs_l;
618
0f12244f
GN		 619 if (!is_pae(vcpu))
620 return 1;
a03490ed 621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 622 if (cs_l)
623 return 1;
a03490ed
CO		 624 } else
625#endif
ff03a073 626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 627 kvm_read_cr3(vcpu)))
0f12244f 628 return 1;
a03490ed
CO		 629 }
630
ad756a16
MJ		 631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
a03490ed 634 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 635
d170c419 636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 637 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 638 kvm_async_pf_hash_reset(vcpu);
639 }
e5f3f027 640
aad82703
SY		 641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
b18d5431 643
879ae188
LE		 644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
0f12244f
GN		 649 return 0;
650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 652
2d3ad1f4 653void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 654{
49a9b07e 655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 656}
2d3ad1f4 657EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 658
42bdf991
MT		 659static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660{
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667}
668
669static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670{
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676}
677
69b0049a 678static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 679{
56c103ec
LJ		 680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 682 u64 valid_bits;
2acf923e
DC		 683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
d91cab78 687 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 688 return 1;
d91cab78 689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 690 return 1;
46c34cb0
PB		 691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
d91cab78 697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 698 if (xcr0 & ~valid_bits)
2acf923e 699 return 1;
46c34cb0 700
d91cab78
DH		 701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 703 return 1;
704
d91cab78
DH		 705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 709 return 1;
710 }
2acf923e 711 vcpu->arch.xcr0 = xcr0;
56c103ec 712
d91cab78 713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 714 kvm_update_cpuid(vcpu);
2acf923e
DC		 715 return 0;
716}
717
718int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719{
764bcbc5
Z		 720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
a83b29c6 729int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 730{
fc78f519 731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 734
0f12244f
GN		 735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
a03490ed 737
2acf923e
DC		 738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
c68b734f
YW		 741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
97ec8c06
FW		 744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
afcbf13f 747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 748 return 1;
749
b9baba86
HH		 750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
a03490ed 753 if (is_long_mode(vcpu)) {
0f12244f
GN		 754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
a2edf57f
AK		 756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
0f12244f
GN		 760 return 1;
761
ad756a16
MJ		 762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
5e1746d6 771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 772 return 1;
a03490ed 773
ad756a16
MJ		 774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 776 kvm_mmu_reset_context(vcpu);
0f12244f 777
b9baba86 778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 779 kvm_update_cpuid(vcpu);
2acf923e 780
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 784
2390218b 785int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 786{
ac146235 787#ifdef CONFIG_X86_64
9d88fca7 788 cr3 &= ~CR3_PCID_INVD;
ac146235 789#endif
9d88fca7 790
9f8fe504 791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 792 kvm_mmu_sync_roots(vcpu);
77c3913b 793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 794 return 0;
d835dfec
AK		 795 }
796
a03490ed 797 if (is_long_mode(vcpu)) {
d9f89b88
JK		 798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 802 return 1;
a03490ed 803
0f12244f 804 vcpu->arch.cr3 = cr3;
aff48baa 805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 806 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 807 return 0;
808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 810
eea1cff9 811int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 812{
0f12244f
GN		 813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
ad312c7c 818 vcpu->arch.cr8 = cr8;
0f12244f
GN		 819 return 0;
820}
2d3ad1f4 821EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 822
2d3ad1f4 823unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 824{
35754c98 825 if (lapic_in_kernel(vcpu))
a03490ed
CO		 826 return kvm_lapic_get_cr8(vcpu);
827 else
ad312c7c 828 return vcpu->arch.cr8;
a03490ed 829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 831
ae561ede
NA		 832static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833{
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841}
842
73aaf249
JK		 843static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844{
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847}
848
c8639010
JK		 849static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850{
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 861}
862
6f43ed01
NA		 863static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864{
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870}
871
338dbc97 872static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 873{
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
020df079
GN		 881 /* fall through */
882 case 6:
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
6f43ed01 885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 886 kvm_update_dr6(vcpu);
020df079
GN		 887 break;
888 case 5:
020df079
GN		 889 /* fall through */
890 default: /* 7 */
338dbc97
GN		 891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
020df079 893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 894 kvm_update_dr7(vcpu);
020df079
GN		 895 break;
896 }
897
898 return 0;
899}
338dbc97
GN		 900
901int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902{
16f8a6f9 903 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 904 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 905 return 1;
906 }
907 return 0;
338dbc97 908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_set_dr);
910
16f8a6f9 911int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 912{
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
020df079
GN		 918 /* fall through */
919 case 6:
73aaf249
JK		 920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 924 break;
925 case 5:
020df079
GN		 926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
338dbc97
GN		 931 return 0;
932}
020df079
GN		 933EXPORT_SYMBOL_GPL(kvm_get_dr);
934
022cd0e8
AK		 935bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936{
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
c6702c9d 941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947}
948EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
043405e1
CO		 950/*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
e3267cbb 955 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
043405e1 958 */
e3267cbb 959
043405e1
CO		 960static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 962 MSR_STAR,
043405e1
CO		 963#ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965#endif
b3897a49 966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 968};
969
970static unsigned num_msrs_to_save;
971
62ef68bb
PB		 972static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 979 HV_X64_MSR_RESET,
11c4b1ca 980 HV_X64_MSR_VP_INDEX,
9eec50b8 981 HV_X64_MSR_VP_RUNTIME,
5c919412 982 HV_X64_MSR_SCONTROL,
1f4b34f8 983 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
ba904635 987 MSR_IA32_TSC_ADJUST,
a3e06bbe 988 MSR_IA32_TSCDEADLINE,
043405e1 989 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
c45dcc71 992 MSR_IA32_MCG_EXT_CTL,
64d60670 993 MSR_IA32_SMBASE,
043405e1
CO		 994};
995
62ef68bb
PB		 996static unsigned num_emulated_msrs;
997
384bb783 998bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 999{
b69e8cae 1000 if (efer & efer_reserved_bits)
384bb783 1001 return false;
15c4a640 1002
1b2fd70c
AG		 1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1008 return false;
1b2fd70c
AG		 1009 }
1010
d8017474
AG		 1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1016 return false;
d8017474
AG		 1017 }
1018
384bb783
JK		 1019 return true;
1020}
1021EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024{
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
15c4a640 1034 efer &= ~EFER_LMA;
f6801dff 1035 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1036
a3d204e2
SY		 1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
aad82703
SY		 1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
b69e8cae 1043 return 0;
15c4a640
CO		 1044}
1045
f2b4b7dd
JR		 1046void kvm_enable_efer_bits(u64 mask)
1047{
1048 efer_reserved_bits &= ~mask;
1049}
1050EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
15c4a640
CO		 1052/*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
8fe8ab46 1057int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1058{
854e8bb1
NA		 1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
8fe8ab46 1084 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1085}
854e8bb1 1086EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1087
313a3dc7
CO		 1088/*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
609e36d3
PB		 1091static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092{
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104}
1105
313a3dc7
CO		 1106static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
8fe8ab46
WA		 1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1114}
1115
16e8d74d
MT		 1116#ifdef CONFIG_X86_64
1117struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
cbcf2dd3
TG		 1128 u64 boot_ns;
1129 u64 nsec_base;
16e8d74d
MT		 1130};
1131
1132static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134static void update_pvclock_gtod(struct timekeeper *tk)
1135{
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1137 u64 boot_ns;
1138
876e7881 1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
876e7881
PZ		 1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1149
cbcf2dd3 1150 vdata->boot_ns = boot_ns;
876e7881 1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1152
1153 write_seqcount_end(&vdata->seq);
1154}
1155#endif
1156
bab5bb39
NK		 1157void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158{
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165}
16e8d74d 1166
18068523
GOC		 1167static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168{
9ed3c444
AK		 1169 int version;
1170 int r;
50d0a0f9 1171 struct pvclock_wall_clock wc;
87aeb54f 1172 struct timespec64 boot;
18068523
GOC		 1173
1174 if (!wall_clock)
1175 return;
1176
9ed3c444
AK		 1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
18068523 1185
1dab1345
NK		 1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
18068523 1188
50d0a0f9
GH		 1189 /*
1190 * The guest calculates current wall clock time by adding
34c238a1 1191 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
87aeb54f 1195 getboottime64(&boot);
50d0a0f9 1196
4b648665 1197 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
4b648665 1200 }
87aeb54f 1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
18068523
GOC		 1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1209}
1210
50d0a0f9
GH		 1211static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212{
b51012de
PB		 1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
50d0a0f9
GH		 1215}
1216
3ae13faa 1217static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1218 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1219{
5f4e3f88 1220 uint64_t scaled64;
50d0a0f9
GH		 1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
3ae13faa
PB		 1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
50933623 1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
50933623
JK		 1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
50d0a0f9
GH		 1238 shift++;
1239 }
1240
5f4e3f88
ZA		 1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1243
3ae13faa
PB		 1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1246}
1247
d828199e 1248#ifdef CONFIG_X86_64
16e8d74d 1249static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1250#endif
16e8d74d 1251
c8076604 1252static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1253static unsigned long max_tsc_khz;
c8076604 1254
cc578287 1255static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1256{
cc578287
ZA		 1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1e993611
JR		 1260}
1261
381d585c
HZ		 1262static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263{
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296}
1297
4941b8cb 1298static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1299{
cc578287
ZA		 1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
217fc9cf 1302
03ba32ca 1303 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1304 if (user_tsc_khz == 0) {
ad721883
HZ		 1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1307 return -1;
ad721883 1308 }
03ba32ca 1309
c285545f 1310 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1326 use_scaling = 1;
1327 }
4941b8cb 1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1329}
1330
1331static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332{
e26101b1 1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
e26101b1 1336 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1337 return tsc;
1338}
1339
69b0049a 1340static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1341{
1342#ifdef CONFIG_X86_64
1343 bool vcpus_matched;
b48aa97e
MT		 1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
7f187922
MT		 1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365#endif
1366}
1367
ba904635
WA		 1368static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369{
3e3f5026 1370 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372}
1373
35181e86
HZ		 1374/*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385{
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387}
1388
1389u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390{
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398}
1399EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
07c1419a
HZ		 1401static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402{
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408}
1409
4ba76538
HZ		 1410u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411{
1412 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1413}
1414EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
a545ab6a
LC		 1416static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1417{
1418 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1419 vcpu->arch.tsc_offset = offset;
1420}
1421
8fe8ab46 1422void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1423{
1424 struct kvm *kvm = vcpu->kvm;
f38e098f 1425 u64 offset, ns, elapsed;
99e3e30a 1426 unsigned long flags;
02626b6a 1427 s64 usdiff;
b48aa97e 1428 bool matched;
0d3da0d2 1429 bool already_matched;
8fe8ab46 1430 u64 data = msr->data;
99e3e30a 1431
038f8c11 1432 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1433 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1434 ns = ktime_get_boot_ns();
f38e098f 1435 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1436
03ba32ca 1437 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1438 int faulted = 0;
1439
03ba32ca
MT		 1440 /* n.b - signed multiplication and division required */
1441 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1442#ifdef CONFIG_X86_64
03ba32ca 1443 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1444#else
03ba32ca 1445 /* do_div() only does unsigned */
8915aa27
MT		 1446 asm("1: idivl %[divisor]\n"
1447 "2: xor %%edx, %%edx\n"
1448 " movl $0, %[faulted]\n"
1449 "3:\n"
1450 ".section .fixup,\"ax\"\n"
1451 "4: movl $1, %[faulted]\n"
1452 " jmp 3b\n"
1453 ".previous\n"
1454
1455 _ASM_EXTABLE(1b, 4b)
1456
1457 : "=A"(usdiff), [faulted] "=r" (faulted)
1458 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1459
5d3cb0f6 1460#endif
03ba32ca
MT		 1461 do_div(elapsed, 1000);
1462 usdiff -= elapsed;
1463 if (usdiff < 0)
1464 usdiff = -usdiff;
8915aa27
MT		 1465
1466 /* idivl overflow => difference is larger than USEC_PER_SEC */
1467 if (faulted)
1468 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1469 } else
1470 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1471
1472 /*
5d3cb0f6
ZA		 1473 * Special case: TSC write with a small delta (1 second) of virtual
1474 * cycle time against real time is interpreted as an attempt to
1475 * synchronize the CPU.
1476 *
1477 * For a reliable TSC, we can match TSC offsets, and for an unstable
1478 * TSC, we add elapsed time in this computation. We could let the
1479 * compensation code attempt to catch up if we fall behind, but
1480 * it's better to try to match offsets from the beginning.
1481 */
02626b6a 1482 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1483 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1484 if (!check_tsc_unstable()) {
e26101b1 1485 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1486 pr_debug("kvm: matched tsc offset for %llu\n", data);
1487 } else {
857e4099 1488 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1489 data += delta;
07c1419a 1490 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1491 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1492 }
b48aa97e 1493 matched = true;
0d3da0d2 1494 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1495 } else {
1496 /*
1497 * We split periods of matched TSC writes into generations.
1498 * For each generation, we track the original measured
1499 * nanosecond time, offset, and write, so if TSCs are in
1500 * sync, we can match exact offset, and if not, we can match
4a969980 1501 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1502 *
1503 * These values are tracked in kvm->arch.cur_xxx variables.
1504 */
1505 kvm->arch.cur_tsc_generation++;
1506 kvm->arch.cur_tsc_nsec = ns;
1507 kvm->arch.cur_tsc_write = data;
1508 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1509 matched = false;
0d3da0d2 1510 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1511 kvm->arch.cur_tsc_generation, data);
f38e098f 1512 }
e26101b1
ZA		 1513
1514 /*
1515 * We also track th most recent recorded KHZ, write and time to
1516 * allow the matching interval to be extended at each write.
1517 */
f38e098f
ZA		 1518 kvm->arch.last_tsc_nsec = ns;
1519 kvm->arch.last_tsc_write = data;
5d3cb0f6 1520 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1521
b183aa58 1522 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1523
1524 /* Keep track of which generation this VCPU has synchronized to */
1525 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1526 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1527 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1528
ba904635
WA		 1529 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1530 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1531 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1532 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1533
1534 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1535 if (!matched) {
b48aa97e 1536 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1537 } else if (!already_matched) {
1538 kvm->arch.nr_vcpus_matched_tsc++;
1539 }
b48aa97e
MT		 1540
1541 kvm_track_tsc_matching(vcpu);
1542 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1543}
e26101b1 1544
99e3e30a
ZA		 1545EXPORT_SYMBOL_GPL(kvm_write_tsc);
1546
58ea6767
HZ		 1547static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1548 s64 adjustment)
1549{
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
1553static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1554{
1555 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1556 WARN_ON(adjustment < 0);
1557 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1558 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1559}
1560
d828199e
MT		 1561#ifdef CONFIG_X86_64
1562
1563static cycle_t read_tsc(void)
1564{
03b9730b
AL		 1565 cycle_t ret = (cycle_t)rdtsc_ordered();
1566 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1567
1568 if (likely(ret >= last))
1569 return ret;
1570
1571 /*
1572 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1573 * predictable (it's just a function of time and the likely is
d828199e
MT		 1574 * very likely) and there's a data dependence, so force GCC
1575 * to generate a branch instead. I don't barrier() because
1576 * we don't actually need a barrier, and if this function
1577 * ever gets inlined it will generate worse code.
1578 */
1579 asm volatile ("");
1580 return last;
1581}
1582
1583static inline u64 vgettsc(cycle_t *cycle_now)
1584{
1585 long v;
1586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1587
1588 *cycle_now = read_tsc();
1589
1590 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1591 return v * gtod->clock.mult;
1592}
1593
cbcf2dd3 1594static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1595{
cbcf2dd3 1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1597 unsigned long seq;
d828199e 1598 int mode;
cbcf2dd3 1599 u64 ns;
d828199e 1600
d828199e
MT		 1601 do {
1602 seq = read_seqcount_begin(&gtod->seq);
1603 mode = gtod->clock.vclock_mode;
cbcf2dd3 1604 ns = gtod->nsec_base;
d828199e
MT		 1605 ns += vgettsc(cycle_now);
1606 ns >>= gtod->clock.shift;
cbcf2dd3 1607 ns += gtod->boot_ns;
d828199e 1608 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1609 *t = ns;
d828199e
MT		 1610
1611 return mode;
1612}
1613
1614/* returns true if host is using tsc clocksource */
1615static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1616{
d828199e
MT		 1617 /* checked again under seqlock below */
1618 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1619 return false;
1620
cbcf2dd3 1621 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1622}
1623#endif
1624
1625/*
1626 *
b48aa97e
MT		 1627 * Assuming a stable TSC across physical CPUS, and a stable TSC
1628 * across virtual CPUs, the following condition is possible.
1629 * Each numbered line represents an event visible to both
d828199e
MT		 1630 * CPUs at the next numbered event.
1631 *
1632 * "timespecX" represents host monotonic time. "tscX" represents
1633 * RDTSC value.
1634 *
1635 * VCPU0 on CPU0 | VCPU1 on CPU1
1636 *
1637 * 1. read timespec0,tsc0
1638 * 2. | timespec1 = timespec0 + N
1639 * | tsc1 = tsc0 + M
1640 * 3. transition to guest | transition to guest
1641 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1642 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1643 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1644 *
1645 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1646 *
1647 * - ret0 < ret1
1648 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1649 * ...
1650 * - 0 < N - M => M < N
1651 *
1652 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1653 * always the case (the difference between two distinct xtime instances
1654 * might be smaller then the difference between corresponding TSC reads,
1655 * when updating guest vcpus pvclock areas).
1656 *
1657 * To avoid that problem, do not allow visibility of distinct
1658 * system_timestamp/tsc_timestamp values simultaneously: use a master
1659 * copy of host monotonic time values. Update that master copy
1660 * in lockstep.
1661 *
b48aa97e 1662 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1663 *
1664 */
1665
1666static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1667{
1668#ifdef CONFIG_X86_64
1669 struct kvm_arch *ka = &kvm->arch;
1670 int vclock_mode;
b48aa97e
MT		 1671 bool host_tsc_clocksource, vcpus_matched;
1672
1673 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1674 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1675
1676 /*
1677 * If the host uses TSC clock, then passthrough TSC as stable
1678 * to the guest.
1679 */
b48aa97e 1680 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1681 &ka->master_kernel_ns,
1682 &ka->master_cycle_now);
1683
16a96021 1684 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1685 && !backwards_tsc_observed
1686 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1687
d828199e
MT		 1688 if (ka->use_master_clock)
1689 atomic_set(&kvm_guest_has_master_clock, 1);
1690
1691 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1692 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1693 vcpus_matched);
d828199e
MT		 1694#endif
1695}
1696
2860c4b1
PB		 1697void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1698{
1699 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1700}
1701
2e762ff7
MT		 1702static void kvm_gen_update_masterclock(struct kvm *kvm)
1703{
1704#ifdef CONFIG_X86_64
1705 int i;
1706 struct kvm_vcpu *vcpu;
1707 struct kvm_arch *ka = &kvm->arch;
1708
1709 spin_lock(&ka->pvclock_gtod_sync_lock);
1710 kvm_make_mclock_inprogress_request(kvm);
1711 /* no guest entries from this point */
1712 pvclock_update_vm_gtod_copy(kvm);
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1716
1717 /* guest entries allowed */
1718 kvm_for_each_vcpu(i, vcpu, kvm)
1719 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1720
1721 spin_unlock(&ka->pvclock_gtod_sync_lock);
1722#endif
1723}
1724
108b249c
PB		 1725static u64 __get_kvmclock_ns(struct kvm *kvm)
1726{
1727 struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, 0);
1728 struct kvm_arch *ka = &kvm->arch;
1729 s64 ns;
1730
1731 if (vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT) {
1732 u64 tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1733 ns = __pvclock_read_cycles(&vcpu->arch.hv_clock, tsc);
1734 } else {
1735 ns = ktime_get_boot_ns() + ka->kvmclock_offset;
1736 }
1737
1738 return ns;
1739}
1740
1741u64 get_kvmclock_ns(struct kvm *kvm)
1742{
1743 unsigned long flags;
1744 s64 ns;
1745
1746 local_irq_save(flags);
1747 ns = __get_kvmclock_ns(kvm);
1748 local_irq_restore(flags);
1749
1750 return ns;
1751}
1752
0d6dd2ff
PB		 1753static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1754{
1755 struct kvm_vcpu_arch *vcpu = &v->arch;
1756 struct pvclock_vcpu_time_info guest_hv_clock;
1757
1758 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1759 &guest_hv_clock, sizeof(guest_hv_clock))))
1760 return;
1761
1762 /* This VCPU is paused, but it's legal for a guest to read another
1763 * VCPU's kvmclock, so we really have to follow the specification where
1764 * it says that version is odd if data is being modified, and even after
1765 * it is consistent.
1766 *
1767 * Version field updates must be kept separate. This is because
1768 * kvm_write_guest_cached might use a "rep movs" instruction, and
1769 * writes within a string instruction are weakly ordered. So there
1770 * are three writes overall.
1771 *
1772 * As a small optimization, only write the version field in the first
1773 * and third write. The vcpu->pv_time cache is still valid, because the
1774 * version field is the first in the struct.
1775 */
1776 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1777
1778 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1779 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1780 &vcpu->hv_clock,
1781 sizeof(vcpu->hv_clock.version));
1782
1783 smp_wmb();
1784
1785 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1786 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1787
1788 if (vcpu->pvclock_set_guest_stopped_request) {
1789 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1790 vcpu->pvclock_set_guest_stopped_request = false;
1791 }
1792
1793 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1794
1795 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1796 &vcpu->hv_clock,
1797 sizeof(vcpu->hv_clock));
1798
1799 smp_wmb();
1800
1801 vcpu->hv_clock.version++;
1802 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1803 &vcpu->hv_clock,
1804 sizeof(vcpu->hv_clock.version));
1805}
1806
34c238a1 1807static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1808{
78db6a50 1809 unsigned long flags, tgt_tsc_khz;
18068523 1810 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1811 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1812 s64 kernel_ns;
d828199e 1813 u64 tsc_timestamp, host_tsc;
51d59c6b 1814 u8 pvclock_flags;
d828199e
MT		 1815 bool use_master_clock;
1816
1817 kernel_ns = 0;
1818 host_tsc = 0;
18068523 1819
d828199e
MT		 1820 /*
1821 * If the host uses TSC clock, then passthrough TSC as stable
1822 * to the guest.
1823 */
1824 spin_lock(&ka->pvclock_gtod_sync_lock);
1825 use_master_clock = ka->use_master_clock;
1826 if (use_master_clock) {
1827 host_tsc = ka->master_cycle_now;
1828 kernel_ns = ka->master_kernel_ns;
1829 }
1830 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1831
1832 /* Keep irq disabled to prevent changes to the clock */
1833 local_irq_save(flags);
78db6a50
PB		 1834 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1835 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1836 local_irq_restore(flags);
1837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1838 return 1;
1839 }
d828199e 1840 if (!use_master_clock) {
4ea1636b 1841 host_tsc = rdtsc();
108b249c 1842 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1843 }
1844
4ba76538 1845 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1846
c285545f
ZA		 1847 /*
1848 * We may have to catch up the TSC to match elapsed wall clock
1849 * time for two reasons, even if kvmclock is used.
1850 * 1) CPU could have been running below the maximum TSC rate
1851 * 2) Broken TSC compensation resets the base at each VCPU
1852 * entry to avoid unknown leaps of TSC even when running
1853 * again on the same CPU. This may cause apparent elapsed
1854 * time to disappear, and the guest to stand still or run
1855 * very slowly.
1856 */
1857 if (vcpu->tsc_catchup) {
1858 u64 tsc = compute_guest_tsc(v, kernel_ns);
1859 if (tsc > tsc_timestamp) {
f1e2b260 1860 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1861 tsc_timestamp = tsc;
1862 }
50d0a0f9
GH		 1863 }
1864
18068523
GOC		 1865 local_irq_restore(flags);
1866
0d6dd2ff 1867 /* With all the info we got, fill in the values */
18068523 1868
78db6a50
PB		 1869 if (kvm_has_tsc_control)
1870 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1871
1872 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1873 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1874 &vcpu->hv_clock.tsc_shift,
1875 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1876 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1877 }
1878
1d5f066e 1879 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1880 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1881 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1882
d828199e 1883 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1884 pvclock_flags = 0;
d828199e
MT		 1885 if (use_master_clock)
1886 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1887
78c0337a
MT		 1888 vcpu->hv_clock.flags = pvclock_flags;
1889
095cf55d
PB		 1890 if (vcpu->pv_time_enabled)
1891 kvm_setup_pvclock_page(v);
1892 if (v == kvm_get_vcpu(v->kvm, 0))
1893 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1894 return 0;
c8076604
GH		 1895}
1896
0061d53d
MT		 1897/*
1898 * kvmclock updates which are isolated to a given vcpu, such as
1899 * vcpu->cpu migration, should not allow system_timestamp from
1900 * the rest of the vcpus to remain static. Otherwise ntp frequency
1901 * correction applies to one vcpu's system_timestamp but not
1902 * the others.
1903 *
1904 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1905 * We need to rate-limit these requests though, as they can
1906 * considerably slow guests that have a large number of vcpus.
1907 * The time for a remote vcpu to update its kvmclock is bound
1908 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1909 */
1910
7e44e449
AJ		 1911#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1912
1913static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1914{
1915 int i;
7e44e449
AJ		 1916 struct delayed_work *dwork = to_delayed_work(work);
1917 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1918 kvmclock_update_work);
1919 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1920 struct kvm_vcpu *vcpu;
1921
1922 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1923 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1924 kvm_vcpu_kick(vcpu);
1925 }
1926}
1927
7e44e449
AJ		 1928static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1929{
1930 struct kvm *kvm = v->kvm;
1931
105b21bb 1932 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1933 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1934 KVMCLOCK_UPDATE_DELAY);
1935}
1936
332967a3
AJ		 1937#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1938
1939static void kvmclock_sync_fn(struct work_struct *work)
1940{
1941 struct delayed_work *dwork = to_delayed_work(work);
1942 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1943 kvmclock_sync_work);
1944 struct kvm *kvm = container_of(ka, struct kvm, arch);
1945
630994b3
MT		 1946 if (!kvmclock_periodic_sync)
1947 return;
1948
332967a3
AJ		 1949 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1950 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1951 KVMCLOCK_SYNC_PERIOD);
1952}
1953
890ca9ae 1954static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1955{
890ca9ae
HY		 1956 u64 mcg_cap = vcpu->arch.mcg_cap;
1957 unsigned bank_num = mcg_cap & 0xff;
1958
15c4a640 1959 switch (msr) {
15c4a640 1960 case MSR_IA32_MCG_STATUS:
890ca9ae 1961 vcpu->arch.mcg_status = data;
15c4a640 1962 break;
c7ac679c 1963 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1964 if (!(mcg_cap & MCG_CTL_P))
1965 return 1;
1966 if (data != 0 && data != ~(u64)0)
1967 return -1;
1968 vcpu->arch.mcg_ctl = data;
1969 break;
1970 default:
1971 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1972 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1973 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1974 /* only 0 or all 1s can be written to IA32_MCi_CTL
1975 * some Linux kernels though clear bit 10 in bank 4 to
1976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1977 * this to avoid an uncatched #GP in the guest
1978 */
890ca9ae 1979 if ((offset & 0x3) == 0 &&
114be429 1980 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1981 return -1;
1982 vcpu->arch.mce_banks[offset] = data;
1983 break;
1984 }
1985 return 1;
1986 }
1987 return 0;
1988}
1989
ffde22ac
ES		 1990static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1991{
1992 struct kvm *kvm = vcpu->kvm;
1993 int lm = is_long_mode(vcpu);
1994 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1995 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1996 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1997 : kvm->arch.xen_hvm_config.blob_size_32;
1998 u32 page_num = data & ~PAGE_MASK;
1999 u64 page_addr = data & PAGE_MASK;
2000 u8 *page;
2001 int r;
2002
2003 r = -E2BIG;
2004 if (page_num >= blob_size)
2005 goto out;
2006 r = -ENOMEM;
ff5c2c03
SL		 2007 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2008 if (IS_ERR(page)) {
2009 r = PTR_ERR(page);
ffde22ac 2010 goto out;
ff5c2c03 2011 }
54bf36aa 2012 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2013 goto out_free;
2014 r = 0;
2015out_free:
2016 kfree(page);
2017out:
2018 return r;
2019}
2020
344d9588
GN		 2021static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2022{
2023 gpa_t gpa = data & ~0x3f;
2024
4a969980 2025 /* Bits 2:5 are reserved, Should be zero */
6adba527 2026 if (data & 0x3c)
344d9588
GN		 2027 return 1;
2028
2029 vcpu->arch.apf.msr_val = data;
2030
2031 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2032 kvm_clear_async_pf_completion_queue(vcpu);
2033 kvm_async_pf_hash_reset(vcpu);
2034 return 0;
2035 }
2036
8f964525
AH		 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2038 sizeof(u32)))
344d9588
GN		 2039 return 1;
2040
6adba527 2041 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2042 kvm_async_pf_wakeup_all(vcpu);
2043 return 0;
2044}
2045
12f9a48f
GC		 2046static void kvmclock_reset(struct kvm_vcpu *vcpu)
2047{
0b79459b 2048 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2049}
2050
c9aaa895
GC		 2051static void record_steal_time(struct kvm_vcpu *vcpu)
2052{
2053 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2054 return;
2055
2056 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2057 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2058 return;
2059
35f3fae1
WL		 2060 if (vcpu->arch.st.steal.version & 1)
2061 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2062
2063 vcpu->arch.st.steal.version += 1;
2064
2065 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2066 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2067
2068 smp_wmb();
2069
c54cdf14
LC		 2070 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2071 vcpu->arch.st.last_steal;
2072 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2073
2074 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2075 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2076
2077 smp_wmb();
2078
2079 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2080
2081 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2082 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2083}
2084
8fe8ab46 2085int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2086{
5753785f 2087 bool pr = false;
8fe8ab46
WA		 2088 u32 msr = msr_info->index;
2089 u64 data = msr_info->data;
5753785f 2090
15c4a640 2091 switch (msr) {
2e32b719
BP		 2092 case MSR_AMD64_NB_CFG:
2093 case MSR_IA32_UCODE_REV:
2094 case MSR_IA32_UCODE_WRITE:
2095 case MSR_VM_HSAVE_PA:
2096 case MSR_AMD64_PATCH_LOADER:
2097 case MSR_AMD64_BU_CFG2:
2098 break;
2099
15c4a640 2100 case MSR_EFER:
b69e8cae 2101 return set_efer(vcpu, data);
8f1589d9
AP		 2102 case MSR_K7_HWCR:
2103 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2104 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2105 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2106 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2107 if (data != 0) {
a737f256
CD		 2108 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2109 data);
8f1589d9
AP		 2110 return 1;
2111 }
15c4a640 2112 break;
f7c6d140
AP		 2113 case MSR_FAM10H_MMIO_CONF_BASE:
2114 if (data != 0) {
a737f256
CD		 2115 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2116 "0x%llx\n", data);
f7c6d140
AP		 2117 return 1;
2118 }
15c4a640 2119 break;
b5e2fec0
AG		 2120 case MSR_IA32_DEBUGCTLMSR:
2121 if (!data) {
2122 /* We support the non-activated case already */
2123 break;
2124 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2125 /* Values other than LBR and BTF are vendor-specific,
2126 thus reserved and should throw a #GP */
2127 return 1;
2128 }
a737f256
CD		 2129 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2130 __func__, data);
b5e2fec0 2131 break;
9ba075a6 2132 case 0x200 ... 0x2ff:
ff53604b 2133 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2134 case MSR_IA32_APICBASE:
58cb628d 2135 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2136 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2137 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2138 case MSR_IA32_TSCDEADLINE:
2139 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2140 break;
ba904635
WA		 2141 case MSR_IA32_TSC_ADJUST:
2142 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2143 if (!msr_info->host_initiated) {
d913b904 2144 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2145 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2146 }
2147 vcpu->arch.ia32_tsc_adjust_msr = data;
2148 }
2149 break;
15c4a640 2150 case MSR_IA32_MISC_ENABLE:
ad312c7c 2151 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2152 break;
64d60670
PB		 2153 case MSR_IA32_SMBASE:
2154 if (!msr_info->host_initiated)
2155 return 1;
2156 vcpu->arch.smbase = data;
2157 break;
11c6bffa 2158 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2159 case MSR_KVM_WALL_CLOCK:
2160 vcpu->kvm->arch.wall_clock = data;
2161 kvm_write_wall_clock(vcpu->kvm, data);
2162 break;
11c6bffa 2163 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2164 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2165 u64 gpa_offset;
54750f2c
MT		 2166 struct kvm_arch *ka = &vcpu->kvm->arch;
2167
12f9a48f 2168 kvmclock_reset(vcpu);
18068523 2169
54750f2c
MT		 2170 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2171 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2172
2173 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2174 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2175 &vcpu->requests);
2176
2177 ka->boot_vcpu_runs_old_kvmclock = tmp;
2178 }
2179
18068523 2180 vcpu->arch.time = data;
0061d53d 2181 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2182
2183 /* we verify if the enable bit is set... */
2184 if (!(data & 1))
2185 break;
2186
0b79459b 2187 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2188
0b79459b 2189 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2190 &vcpu->arch.pv_time, data & ~1ULL,
2191 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2192 vcpu->arch.pv_time_enabled = false;
2193 else
2194 vcpu->arch.pv_time_enabled = true;
32cad84f 2195
18068523
GOC		 2196 break;
2197 }
344d9588
GN		 2198 case MSR_KVM_ASYNC_PF_EN:
2199 if (kvm_pv_enable_async_pf(vcpu, data))
2200 return 1;
2201 break;
c9aaa895
GC		 2202 case MSR_KVM_STEAL_TIME:
2203
2204 if (unlikely(!sched_info_on()))
2205 return 1;
2206
2207 if (data & KVM_STEAL_RESERVED_MASK)
2208 return 1;
2209
2210 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2211 data & KVM_STEAL_VALID_BITS,
2212 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2213 return 1;
2214
2215 vcpu->arch.st.msr_val = data;
2216
2217 if (!(data & KVM_MSR_ENABLED))
2218 break;
2219
c9aaa895
GC		 2220 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2221
2222 break;
ae7a2a3f
MT		 2223 case MSR_KVM_PV_EOI_EN:
2224 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2225 return 1;
2226 break;
c9aaa895 2227
890ca9ae
HY		 2228 case MSR_IA32_MCG_CTL:
2229 case MSR_IA32_MCG_STATUS:
81760dcc 2230 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2231 return set_msr_mce(vcpu, msr, data);
71db6023 2232
6912ac32
WH		 2233 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2234 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2235 pr = true; /* fall through */
2236 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2237 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2238 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2239 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2240
2241 if (pr || data != 0)
a737f256
CD		 2242 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2243 "0x%x data 0x%llx\n", msr, data);
5753785f 2244 break;
84e0cefa
JS		 2245 case MSR_K7_CLK_CTL:
2246 /*
2247 * Ignore all writes to this no longer documented MSR.
2248 * Writes are only relevant for old K7 processors,
2249 * all pre-dating SVM, but a recommended workaround from
4a969980 2250 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2251 * affected processor models on the command line, hence
2252 * the need to ignore the workaround.
2253 */
2254 break;
55cd8e5a 2255 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2256 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2257 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2258 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2259 return kvm_hv_set_msr_common(vcpu, msr, data,
2260 msr_info->host_initiated);
91c9c3ed 2261 case MSR_IA32_BBL_CR_CTL3:
2262 /* Drop writes to this legacy MSR -- see rdmsr
2263 * counterpart for further detail.
2264 */
796f4687 2265 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2266 break;
2b036c6b
BO		 2267 case MSR_AMD64_OSVW_ID_LENGTH:
2268 if (!guest_cpuid_has_osvw(vcpu))
2269 return 1;
2270 vcpu->arch.osvw.length = data;
2271 break;
2272 case MSR_AMD64_OSVW_STATUS:
2273 if (!guest_cpuid_has_osvw(vcpu))
2274 return 1;
2275 vcpu->arch.osvw.status = data;
2276 break;
15c4a640 2277 default:
ffde22ac
ES		 2278 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2279 return xen_hvm_config(vcpu, data);
c6702c9d 2280 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2281 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2282 if (!ignore_msrs) {
796f4687 2283 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2284 msr, data);
ed85c068
AP		 2285 return 1;
2286 } else {
796f4687 2287 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2288 msr, data);
ed85c068
AP		 2289 break;
2290 }
15c4a640
CO		 2291 }
2292 return 0;
2293}
2294EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2295
2296
2297/*
2298 * Reads an msr value (of 'msr_index') into 'pdata'.
2299 * Returns 0 on success, non-0 otherwise.
2300 * Assumes vcpu_load() was already called.
2301 */
609e36d3 2302int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2303{
609e36d3 2304 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2305}
ff651cb6 2306EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2307
890ca9ae 2308static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2309{
2310 u64 data;
890ca9ae
HY		 2311 u64 mcg_cap = vcpu->arch.mcg_cap;
2312 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2313
2314 switch (msr) {
15c4a640
CO		 2315 case MSR_IA32_P5_MC_ADDR:
2316 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2317 data = 0;
2318 break;
15c4a640 2319 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2320 data = vcpu->arch.mcg_cap;
2321 break;
c7ac679c 2322 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2323 if (!(mcg_cap & MCG_CTL_P))
2324 return 1;
2325 data = vcpu->arch.mcg_ctl;
2326 break;
2327 case MSR_IA32_MCG_STATUS:
2328 data = vcpu->arch.mcg_status;
2329 break;
2330 default:
2331 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2332 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2333 u32 offset = msr - MSR_IA32_MC0_CTL;
2334 data = vcpu->arch.mce_banks[offset];
2335 break;
2336 }
2337 return 1;
2338 }
2339 *pdata = data;
2340 return 0;
2341}
2342
609e36d3 2343int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2344{
609e36d3 2345 switch (msr_info->index) {
890ca9ae 2346 case MSR_IA32_PLATFORM_ID:
15c4a640 2347 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2348 case MSR_IA32_DEBUGCTLMSR:
2349 case MSR_IA32_LASTBRANCHFROMIP:
2350 case MSR_IA32_LASTBRANCHTOIP:
2351 case MSR_IA32_LASTINTFROMIP:
2352 case MSR_IA32_LASTINTTOIP:
60af2ecd 2353 case MSR_K8_SYSCFG:
3afb1121
PB		 2354 case MSR_K8_TSEG_ADDR:
2355 case MSR_K8_TSEG_MASK:
60af2ecd 2356 case MSR_K7_HWCR:
61a6bd67 2357 case MSR_VM_HSAVE_PA:
1fdbd48c 2358 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2359 case MSR_AMD64_NB_CFG:
f7c6d140 2360 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2361 case MSR_AMD64_BU_CFG2:
0c2df2a1 2362 case MSR_IA32_PERF_CTL:
609e36d3 2363 msr_info->data = 0;
15c4a640 2364 break;
6912ac32
WH		 2365 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2366 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2367 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2368 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2369 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2370 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2371 msr_info->data = 0;
5753785f 2372 break;
742bc670 2373 case MSR_IA32_UCODE_REV:
609e36d3 2374 msr_info->data = 0x100000000ULL;
742bc670 2375 break;
9ba075a6 2376 case MSR_MTRRcap:
9ba075a6 2377 case 0x200 ... 0x2ff:
ff53604b 2378 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2379 case 0xcd: /* fsb frequency */
609e36d3 2380 msr_info->data = 3;
15c4a640 2381 break;
7b914098
JS		 2382 /*
2383 * MSR_EBC_FREQUENCY_ID
2384 * Conservative value valid for even the basic CPU models.
2385 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2386 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2387 * and 266MHz for model 3, or 4. Set Core Clock
2388 * Frequency to System Bus Frequency Ratio to 1 (bits
2389 * 31:24) even though these are only valid for CPU
2390 * models > 2, however guests may end up dividing or
2391 * multiplying by zero otherwise.
2392 */
2393 case MSR_EBC_FREQUENCY_ID:
609e36d3 2394 msr_info->data = 1 << 24;
7b914098 2395 break;
15c4a640 2396 case MSR_IA32_APICBASE:
609e36d3 2397 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2398 break;
0105d1a5 2399 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2400 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2401 break;
a3e06bbe 2402 case MSR_IA32_TSCDEADLINE:
609e36d3 2403 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2404 break;
ba904635 2405 case MSR_IA32_TSC_ADJUST:
609e36d3 2406 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2407 break;
15c4a640 2408 case MSR_IA32_MISC_ENABLE:
609e36d3 2409 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2410 break;
64d60670
PB		 2411 case MSR_IA32_SMBASE:
2412 if (!msr_info->host_initiated)
2413 return 1;
2414 msr_info->data = vcpu->arch.smbase;
15c4a640 2415 break;
847f0ad8
AG		 2416 case MSR_IA32_PERF_STATUS:
2417 /* TSC increment by tick */
609e36d3 2418 msr_info->data = 1000ULL;
847f0ad8 2419 /* CPU multiplier */
b0996ae4 2420 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2421 break;
15c4a640 2422 case MSR_EFER:
609e36d3 2423 msr_info->data = vcpu->arch.efer;
15c4a640 2424 break;
18068523 2425 case MSR_KVM_WALL_CLOCK:
11c6bffa 2426 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2427 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2428 break;
2429 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2430 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2431 msr_info->data = vcpu->arch.time;
18068523 2432 break;
344d9588 2433 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2434 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2435 break;
c9aaa895 2436 case MSR_KVM_STEAL_TIME:
609e36d3 2437 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2438 break;
1d92128f 2439 case MSR_KVM_PV_EOI_EN:
609e36d3 2440 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2441 break;
890ca9ae
HY		 2442 case MSR_IA32_P5_MC_ADDR:
2443 case MSR_IA32_P5_MC_TYPE:
2444 case MSR_IA32_MCG_CAP:
2445 case MSR_IA32_MCG_CTL:
2446 case MSR_IA32_MCG_STATUS:
81760dcc 2447 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2448 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2449 case MSR_K7_CLK_CTL:
2450 /*
2451 * Provide expected ramp-up count for K7. All other
2452 * are set to zero, indicating minimum divisors for
2453 * every field.
2454 *
2455 * This prevents guest kernels on AMD host with CPU
2456 * type 6, model 8 and higher from exploding due to
2457 * the rdmsr failing.
2458 */
609e36d3 2459 msr_info->data = 0x20000000;
84e0cefa 2460 break;
55cd8e5a 2461 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2462 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2463 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2464 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2465 return kvm_hv_get_msr_common(vcpu,
2466 msr_info->index, &msr_info->data);
55cd8e5a 2467 break;
91c9c3ed 2468 case MSR_IA32_BBL_CR_CTL3:
2469 /* This legacy MSR exists but isn't fully documented in current
2470 * silicon. It is however accessed by winxp in very narrow
2471 * scenarios where it sets bit #19, itself documented as
2472 * a "reserved" bit. Best effort attempt to source coherent
2473 * read data here should the balance of the register be
2474 * interpreted by the guest:
2475 *
2476 * L2 cache control register 3: 64GB range, 256KB size,
2477 * enabled, latency 0x1, configured
2478 */
609e36d3 2479 msr_info->data = 0xbe702111;
91c9c3ed 2480 break;
2b036c6b
BO		 2481 case MSR_AMD64_OSVW_ID_LENGTH:
2482 if (!guest_cpuid_has_osvw(vcpu))
2483 return 1;
609e36d3 2484 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2485 break;
2486 case MSR_AMD64_OSVW_STATUS:
2487 if (!guest_cpuid_has_osvw(vcpu))
2488 return 1;
609e36d3 2489 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2490 break;
15c4a640 2491 default:
c6702c9d 2492 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2493 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2494 if (!ignore_msrs) {
609e36d3 2495 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2496 return 1;
2497 } else {
609e36d3
PB		 2498 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2499 msr_info->data = 0;
ed85c068
AP		 2500 }
2501 break;
15c4a640 2502 }
15c4a640
CO		 2503 return 0;
2504}
2505EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2506
313a3dc7
CO		 2507/*
2508 * Read or write a bunch of msrs. All parameters are kernel addresses.
2509 *
2510 * @return number of msrs set successfully.
2511 */
2512static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2513 struct kvm_msr_entry *entries,
2514 int (*do_msr)(struct kvm_vcpu *vcpu,
2515 unsigned index, u64 *data))
2516{
f656ce01 2517 int i, idx;
313a3dc7 2518
f656ce01 2519 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2520 for (i = 0; i < msrs->nmsrs; ++i)
2521 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2522 break;
f656ce01 2523 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2524
313a3dc7
CO		 2525 return i;
2526}
2527
2528/*
2529 * Read or write a bunch of msrs. Parameters are user addresses.
2530 *
2531 * @return number of msrs set successfully.
2532 */
2533static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2534 int (*do_msr)(struct kvm_vcpu *vcpu,
2535 unsigned index, u64 *data),
2536 int writeback)
2537{
2538 struct kvm_msrs msrs;
2539 struct kvm_msr_entry *entries;
2540 int r, n;
2541 unsigned size;
2542
2543 r = -EFAULT;
2544 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2545 goto out;
2546
2547 r = -E2BIG;
2548 if (msrs.nmsrs >= MAX_IO_MSRS)
2549 goto out;
2550
313a3dc7 2551 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2552 entries = memdup_user(user_msrs->entries, size);
2553 if (IS_ERR(entries)) {
2554 r = PTR_ERR(entries);
313a3dc7 2555 goto out;
ff5c2c03 2556 }
313a3dc7
CO		 2557
2558 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2559 if (r < 0)
2560 goto out_free;
2561
2562 r = -EFAULT;
2563 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2564 goto out_free;
2565
2566 r = n;
2567
2568out_free:
7a73c028 2569 kfree(entries);
313a3dc7
CO		 2570out:
2571 return r;
2572}
2573
784aa3d7 2574int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2575{
2576 int r;
2577
2578 switch (ext) {
2579 case KVM_CAP_IRQCHIP:
2580 case KVM_CAP_HLT:
2581 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2582 case KVM_CAP_SET_TSS_ADDR:
07716717 2583 case KVM_CAP_EXT_CPUID:
9c15bb1d 2584 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2585 case KVM_CAP_CLOCKSOURCE:
7837699f 2586 case KVM_CAP_PIT:
a28e4f5a 2587 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2588 case KVM_CAP_MP_STATE:
ed848624 2589 case KVM_CAP_SYNC_MMU:
a355c85c 2590 case KVM_CAP_USER_NMI:
52d939a0 2591 case KVM_CAP_REINJECT_CONTROL:
4925663a 2592 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2593 case KVM_CAP_IOEVENTFD:
f848a5a8 2594 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2595 case KVM_CAP_PIT2:
e9f42757 2596 case KVM_CAP_PIT_STATE2:
b927a3ce 2597 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2598 case KVM_CAP_XEN_HVM:
afbcf7ab 2599 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2600 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2601 case KVM_CAP_HYPERV:
10388a07 2602 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2603 case KVM_CAP_HYPERV_SPIN:
5c919412 2604 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2605 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2606 case KVM_CAP_DEBUGREGS:
d2be1651 2607 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2608 case KVM_CAP_XSAVE:
344d9588 2609 case KVM_CAP_ASYNC_PF:
92a1f12d 2610 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2611 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2612 case KVM_CAP_READONLY_MEM:
5f66b620 2613 case KVM_CAP_HYPERV_TIME:
100943c5 2614 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2615 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2616 case KVM_CAP_ENABLE_CAP_VM:
2617 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2618 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2619 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2620#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2621 case KVM_CAP_ASSIGN_DEV_IRQ:
2622 case KVM_CAP_PCI_2_3:
2623#endif
018d00d2
ZX		 2624 r = 1;
2625 break;
6d396b55
PB		 2626 case KVM_CAP_X86_SMM:
2627 /* SMBASE is usually relocated above 1M on modern chipsets,
2628 * and SMM handlers might indeed rely on 4G segment limits,
2629 * so do not report SMM to be available if real mode is
2630 * emulated via vm86 mode. Still, do not go to great lengths
2631 * to avoid userspace's usage of the feature, because it is a
2632 * fringe case that is not enabled except via specific settings
2633 * of the module parameters.
2634 */
2635 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2636 break;
542472b5
LV		 2637 case KVM_CAP_COALESCED_MMIO:
2638 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2639 break;
774ead3a
AK		 2640 case KVM_CAP_VAPIC:
2641 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2642 break;
f725230a 2643 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2644 r = KVM_SOFT_MAX_VCPUS;
2645 break;
2646 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2647 r = KVM_MAX_VCPUS;
2648 break;
a988b910 2649 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2650 r = KVM_USER_MEM_SLOTS;
a988b910 2651 break;
a68a6a72
MT		 2652 case KVM_CAP_PV_MMU: /* obsolete */
2653 r = 0;
2f333bcb 2654 break;
4cee4b72 2655#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2656 case KVM_CAP_IOMMU:
a1b60c1c 2657 r = iommu_present(&pci_bus_type);
62c476c7 2658 break;
4cee4b72 2659#endif
890ca9ae
HY		 2660 case KVM_CAP_MCE:
2661 r = KVM_MAX_MCE_BANKS;
2662 break;
2d5b5a66 2663 case KVM_CAP_XCRS:
d366bf7e 2664 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2665 break;
92a1f12d
JR		 2666 case KVM_CAP_TSC_CONTROL:
2667 r = kvm_has_tsc_control;
2668 break;
37131313
RK		 2669 case KVM_CAP_X2APIC_API:
2670 r = KVM_X2APIC_API_VALID_FLAGS;
2671 break;
018d00d2
ZX		 2672 default:
2673 r = 0;
2674 break;
2675 }
2676 return r;
2677
2678}
2679
043405e1
CO		 2680long kvm_arch_dev_ioctl(struct file *filp,
2681 unsigned int ioctl, unsigned long arg)
2682{
2683 void __user *argp = (void __user *)arg;
2684 long r;
2685
2686 switch (ioctl) {
2687 case KVM_GET_MSR_INDEX_LIST: {
2688 struct kvm_msr_list __user *user_msr_list = argp;
2689 struct kvm_msr_list msr_list;
2690 unsigned n;
2691
2692 r = -EFAULT;
2693 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2694 goto out;
2695 n = msr_list.nmsrs;
62ef68bb 2696 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2697 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2698 goto out;
2699 r = -E2BIG;
e125e7b6 2700 if (n < msr_list.nmsrs)
043405e1
CO		 2701 goto out;
2702 r = -EFAULT;
2703 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2704 num_msrs_to_save * sizeof(u32)))
2705 goto out;
e125e7b6 2706 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2707 &emulated_msrs,
62ef68bb 2708 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2709 goto out;
2710 r = 0;
2711 break;
2712 }
9c15bb1d
BP		 2713 case KVM_GET_SUPPORTED_CPUID:
2714 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2715 struct kvm_cpuid2 __user *cpuid_arg = argp;
2716 struct kvm_cpuid2 cpuid;
2717
2718 r = -EFAULT;
2719 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2720 goto out;
9c15bb1d
BP		 2721
2722 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2723 ioctl);
674eea0f
AK		 2724 if (r)
2725 goto out;
2726
2727 r = -EFAULT;
2728 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2729 goto out;
2730 r = 0;
2731 break;
2732 }
890ca9ae 2733 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2734 r = -EFAULT;
c45dcc71
AR		 2735 if (copy_to_user(argp, &kvm_mce_cap_supported,
2736 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2737 goto out;
2738 r = 0;
2739 break;
2740 }
043405e1
CO		 2741 default:
2742 r = -EINVAL;
2743 }
2744out:
2745 return r;
2746}
2747
f5f48ee1
SY		 2748static void wbinvd_ipi(void *garbage)
2749{
2750 wbinvd();
2751}
2752
2753static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2754{
e0f0bbc5 2755 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2756}
2757
2860c4b1
PB		 2758static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2759{
2760 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2761}
2762
313a3dc7
CO		 2763void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2764{
f5f48ee1
SY		 2765 /* Address WBINVD may be executed by guest */
2766 if (need_emulate_wbinvd(vcpu)) {
2767 if (kvm_x86_ops->has_wbinvd_exit())
2768 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2769 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2770 smp_call_function_single(vcpu->cpu,
2771 wbinvd_ipi, NULL, 1);
2772 }
2773
313a3dc7 2774 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2775
0dd6a6ed
ZA		 2776 /* Apply any externally detected TSC adjustments (due to suspend) */
2777 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2778 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2779 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2780 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2781 }
8f6055cb 2782
48434c20 2783 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2784 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2785 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2786 if (tsc_delta < 0)
2787 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2788
c285545f 2789 if (check_tsc_unstable()) {
07c1419a 2790 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2791 vcpu->arch.last_guest_tsc);
a545ab6a 2792 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2793 vcpu->arch.tsc_catchup = 1;
c285545f 2794 }
e12c8f36
WL		 2795 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2796 kvm_x86_ops->set_hv_timer(vcpu,
2797 kvm_get_lapic_tscdeadline_msr(vcpu)))
2798 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2799 /*
2800 * On a host with synchronized TSC, there is no need to update
2801 * kvmclock on vcpu->cpu migration
2802 */
2803 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2804 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2805 if (vcpu->cpu != cpu)
2806 kvm_migrate_timers(vcpu);
e48672fa 2807 vcpu->cpu = cpu;
6b7d7e76 2808 }
c9aaa895 2809
c9aaa895 2810 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2811}
2812
2813void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2814{
02daab21 2815 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2816 kvm_put_guest_fpu(vcpu);
4ea1636b 2817 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2818}
2819
313a3dc7
CO		 2820static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2821 struct kvm_lapic_state *s)
2822{
d62caabb
AS		 2823 if (vcpu->arch.apicv_active)
2824 kvm_x86_ops->sync_pir_to_irr(vcpu);
2825
a92e2543 2826 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2827}
2828
2829static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2830 struct kvm_lapic_state *s)
2831{
a92e2543
RK		 2832 int r;
2833
2834 r = kvm_apic_set_state(vcpu, s);
2835 if (r)
2836 return r;
cb142eb7 2837 update_cr8_intercept(vcpu);
313a3dc7
CO		 2838
2839 return 0;
2840}
2841
127a457a
MG		 2842static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2843{
2844 return (!lapic_in_kernel(vcpu) ||
2845 kvm_apic_accept_pic_intr(vcpu));
2846}
2847
782d422b
MG		 2848/*
2849 * if userspace requested an interrupt window, check that the
2850 * interrupt window is open.
2851 *
2852 * No need to exit to userspace if we already have an interrupt queued.
2853 */
2854static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2855{
2856 return kvm_arch_interrupt_allowed(vcpu) &&
2857 !kvm_cpu_has_interrupt(vcpu) &&
2858 !kvm_event_needs_reinjection(vcpu) &&
2859 kvm_cpu_accept_dm_intr(vcpu);
2860}
2861
f77bc6a4
ZX		 2862static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2863 struct kvm_interrupt *irq)
2864{
02cdb50f 2865 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2866 return -EINVAL;
1c1a9ce9
SR		 2867
2868 if (!irqchip_in_kernel(vcpu->kvm)) {
2869 kvm_queue_interrupt(vcpu, irq->irq, false);
2870 kvm_make_request(KVM_REQ_EVENT, vcpu);
2871 return 0;
2872 }
2873
2874 /*
2875 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2876 * fail for in-kernel 8259.
2877 */
2878 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2879 return -ENXIO;
f77bc6a4 2880
1c1a9ce9
SR		 2881 if (vcpu->arch.pending_external_vector != -1)
2882 return -EEXIST;
f77bc6a4 2883
1c1a9ce9 2884 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2885 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2886 return 0;
2887}
2888
c4abb7c9
JK		 2889static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2890{
c4abb7c9 2891 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2892
2893 return 0;
2894}
2895
f077825a
PB		 2896static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2897{
64d60670
PB		 2898 kvm_make_request(KVM_REQ_SMI, vcpu);
2899
f077825a
PB		 2900 return 0;
2901}
2902
b209749f
AK		 2903static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2904 struct kvm_tpr_access_ctl *tac)
2905{
2906 if (tac->flags)
2907 return -EINVAL;
2908 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2909 return 0;
2910}
2911
890ca9ae
HY		 2912static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2913 u64 mcg_cap)
2914{
2915 int r;
2916 unsigned bank_num = mcg_cap & 0xff, bank;
2917
2918 r = -EINVAL;
a9e38c3e 2919 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2920 goto out;
c45dcc71 2921 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2922 goto out;
2923 r = 0;
2924 vcpu->arch.mcg_cap = mcg_cap;
2925 /* Init IA32_MCG_CTL to all 1s */
2926 if (mcg_cap & MCG_CTL_P)
2927 vcpu->arch.mcg_ctl = ~(u64)0;
2928 /* Init IA32_MCi_CTL to all 1s */
2929 for (bank = 0; bank < bank_num; bank++)
2930 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2931
2932 if (kvm_x86_ops->setup_mce)
2933 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2934out:
2935 return r;
2936}
2937
2938static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2939 struct kvm_x86_mce *mce)
2940{
2941 u64 mcg_cap = vcpu->arch.mcg_cap;
2942 unsigned bank_num = mcg_cap & 0xff;
2943 u64 *banks = vcpu->arch.mce_banks;
2944
2945 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2946 return -EINVAL;
2947 /*
2948 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2949 * reporting is disabled
2950 */
2951 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2952 vcpu->arch.mcg_ctl != ~(u64)0)
2953 return 0;
2954 banks += 4 * mce->bank;
2955 /*
2956 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2957 * reporting is disabled for the bank
2958 */
2959 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2960 return 0;
2961 if (mce->status & MCI_STATUS_UC) {
2962 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2963 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2964 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2965 return 0;
2966 }
2967 if (banks[1] & MCI_STATUS_VAL)
2968 mce->status |= MCI_STATUS_OVER;
2969 banks[2] = mce->addr;
2970 banks[3] = mce->misc;
2971 vcpu->arch.mcg_status = mce->mcg_status;
2972 banks[1] = mce->status;
2973 kvm_queue_exception(vcpu, MC_VECTOR);
2974 } else if (!(banks[1] & MCI_STATUS_VAL)
2975 || !(banks[1] & MCI_STATUS_UC)) {
2976 if (banks[1] & MCI_STATUS_VAL)
2977 mce->status |= MCI_STATUS_OVER;
2978 banks[2] = mce->addr;
2979 banks[3] = mce->misc;
2980 banks[1] = mce->status;
2981 } else
2982 banks[1] |= MCI_STATUS_OVER;
2983 return 0;
2984}
2985
3cfc3092
JK		 2986static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2987 struct kvm_vcpu_events *events)
2988{
7460fb4a 2989 process_nmi(vcpu);
03b82a30
JK		 2990 events->exception.injected =
2991 vcpu->arch.exception.pending &&
2992 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2993 events->exception.nr = vcpu->arch.exception.nr;
2994 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2995 events->exception.pad = 0;
3cfc3092
JK		 2996 events->exception.error_code = vcpu->arch.exception.error_code;
2997
03b82a30
JK		 2998 events->interrupt.injected =
2999 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3000 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3001 events->interrupt.soft = 0;
37ccdcbe 3002 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3003
3004 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3005 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3006 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3007 events->nmi.pad = 0;
3cfc3092 3008
66450a21 3009 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3010
f077825a
PB		 3011 events->smi.smm = is_smm(vcpu);
3012 events->smi.pending = vcpu->arch.smi_pending;
3013 events->smi.smm_inside_nmi =
3014 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3015 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3016
dab4b911 3017 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3018 | KVM_VCPUEVENT_VALID_SHADOW
3019 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3020 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3021}
3022
3023static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3024 struct kvm_vcpu_events *events)
3025{
dab4b911 3026 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3027 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3028 | KVM_VCPUEVENT_VALID_SHADOW
3029 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3030 return -EINVAL;
3031
78e546c8
PB		 3032 if (events->exception.injected &&
3033 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3034 return -EINVAL;
3035
7460fb4a 3036 process_nmi(vcpu);
3cfc3092
JK		 3037 vcpu->arch.exception.pending = events->exception.injected;
3038 vcpu->arch.exception.nr = events->exception.nr;
3039 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3040 vcpu->arch.exception.error_code = events->exception.error_code;
3041
3042 vcpu->arch.interrupt.pending = events->interrupt.injected;
3043 vcpu->arch.interrupt.nr = events->interrupt.nr;
3044 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3045 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3046 kvm_x86_ops->set_interrupt_shadow(vcpu,
3047 events->interrupt.shadow);
3cfc3092
JK		 3048
3049 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3050 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3051 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3052 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3053
66450a21 3054 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3055 lapic_in_kernel(vcpu))
66450a21 3056 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3057
f077825a
PB		 3058 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3059 if (events->smi.smm)
3060 vcpu->arch.hflags |= HF_SMM_MASK;
3061 else
3062 vcpu->arch.hflags &= ~HF_SMM_MASK;
3063 vcpu->arch.smi_pending = events->smi.pending;
3064 if (events->smi.smm_inside_nmi)
3065 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3066 else
3067 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3068 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3069 if (events->smi.latched_init)
3070 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3071 else
3072 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3073 }
3074 }
3075
3842d135
AK		 3076 kvm_make_request(KVM_REQ_EVENT, vcpu);
3077
3cfc3092
JK		 3078 return 0;
3079}
3080
a1efbe77
JK		 3081static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3082 struct kvm_debugregs *dbgregs)
3083{
73aaf249
JK		 3084 unsigned long val;
3085
a1efbe77 3086 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3087 kvm_get_dr(vcpu, 6, &val);
73aaf249 3088 dbgregs->dr6 = val;
a1efbe77
JK		 3089 dbgregs->dr7 = vcpu->arch.dr7;
3090 dbgregs->flags = 0;
97e69aa6 3091 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3092}
3093
3094static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3095 struct kvm_debugregs *dbgregs)
3096{
3097 if (dbgregs->flags)
3098 return -EINVAL;
3099
d14bdb55
PB		 3100 if (dbgregs->dr6 & ~0xffffffffull)
3101 return -EINVAL;
3102 if (dbgregs->dr7 & ~0xffffffffull)
3103 return -EINVAL;
3104
a1efbe77 3105 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3106 kvm_update_dr0123(vcpu);
a1efbe77 3107 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3108 kvm_update_dr6(vcpu);
a1efbe77 3109 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3110 kvm_update_dr7(vcpu);
a1efbe77 3111
a1efbe77
JK		 3112 return 0;
3113}
3114
df1daba7
PB		 3115#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3116
3117static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3118{
c47ada30 3119 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3120 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3121 u64 valid;
3122
3123 /*
3124 * Copy legacy XSAVE area, to avoid complications with CPUID
3125 * leaves 0 and 1 in the loop below.
3126 */
3127 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3128
3129 /* Set XSTATE_BV */
3130 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3131
3132 /*
3133 * Copy each region from the possibly compacted offset to the
3134 * non-compacted offset.
3135 */
d91cab78 3136 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3137 while (valid) {
3138 u64 feature = valid & -valid;
3139 int index = fls64(feature) - 1;
3140 void *src = get_xsave_addr(xsave, feature);
3141
3142 if (src) {
3143 u32 size, offset, ecx, edx;
3144 cpuid_count(XSTATE_CPUID, index,
3145 &size, &offset, &ecx, &edx);
3146 memcpy(dest + offset, src, size);
3147 }
3148
3149 valid -= feature;
3150 }
3151}
3152
3153static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3154{
c47ada30 3155 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3156 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3157 u64 valid;
3158
3159 /*
3160 * Copy legacy XSAVE area, to avoid complications with CPUID
3161 * leaves 0 and 1 in the loop below.
3162 */
3163 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3164
3165 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3166 xsave->header.xfeatures = xstate_bv;
782511b0 3167 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3168 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3169
3170 /*
3171 * Copy each region from the non-compacted offset to the
3172 * possibly compacted offset.
3173 */
d91cab78 3174 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3175 while (valid) {
3176 u64 feature = valid & -valid;
3177 int index = fls64(feature) - 1;
3178 void *dest = get_xsave_addr(xsave, feature);
3179
3180 if (dest) {
3181 u32 size, offset, ecx, edx;
3182 cpuid_count(XSTATE_CPUID, index,
3183 &size, &offset, &ecx, &edx);
3184 memcpy(dest, src + offset, size);
ee4100da 3185 }
df1daba7
PB		 3186
3187 valid -= feature;
3188 }
3189}
3190
2d5b5a66
SY		 3191static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3192 struct kvm_xsave *guest_xsave)
3193{
d366bf7e 3194 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3195 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3196 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3197 } else {
2d5b5a66 3198 memcpy(guest_xsave->region,
7366ed77 3199 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3200 sizeof(struct fxregs_state));
2d5b5a66 3201 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3202 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3203 }
3204}
3205
3206static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3207 struct kvm_xsave *guest_xsave)
3208{
3209 u64 xstate_bv =
3210 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3211
d366bf7e 3212 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3213 /*
3214 * Here we allow setting states that are not present in
3215 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3216 * with old userspace.
3217 */
4ff41732 3218 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3219 return -EINVAL;
df1daba7 3220 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3221 } else {
d91cab78 3222 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3223 return -EINVAL;
7366ed77 3224 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3225 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3226 }
3227 return 0;
3228}
3229
3230static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3231 struct kvm_xcrs *guest_xcrs)
3232{
d366bf7e 3233 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3234 guest_xcrs->nr_xcrs = 0;
3235 return;
3236 }
3237
3238 guest_xcrs->nr_xcrs = 1;
3239 guest_xcrs->flags = 0;
3240 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3241 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3242}
3243
3244static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3245 struct kvm_xcrs *guest_xcrs)
3246{
3247 int i, r = 0;
3248
d366bf7e 3249 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3250 return -EINVAL;
3251
3252 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3253 return -EINVAL;
3254
3255 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3256 /* Only support XCR0 currently */
c67a04cb 3257 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3258 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3259 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3260 break;
3261 }
3262 if (r)
3263 r = -EINVAL;
3264 return r;
3265}
3266
1c0b28c2
EM		 3267/*
3268 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3269 * stopped by the hypervisor. This function will be called from the host only.
3270 * EINVAL is returned when the host attempts to set the flag for a guest that
3271 * does not support pv clocks.
3272 */
3273static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3274{
0b79459b 3275 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3276 return -EINVAL;
51d59c6b 3277 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3278 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3279 return 0;
3280}
3281
5c919412
AS		 3282static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3283 struct kvm_enable_cap *cap)
3284{
3285 if (cap->flags)
3286 return -EINVAL;
3287
3288 switch (cap->cap) {
3289 case KVM_CAP_HYPERV_SYNIC:
3290 return kvm_hv_activate_synic(vcpu);
3291 default:
3292 return -EINVAL;
3293 }
3294}
3295
313a3dc7
CO		 3296long kvm_arch_vcpu_ioctl(struct file *filp,
3297 unsigned int ioctl, unsigned long arg)
3298{
3299 struct kvm_vcpu *vcpu = filp->private_data;
3300 void __user *argp = (void __user *)arg;
3301 int r;
d1ac91d8
AK		 3302 union {
3303 struct kvm_lapic_state *lapic;
3304 struct kvm_xsave *xsave;
3305 struct kvm_xcrs *xcrs;
3306 void *buffer;
3307 } u;
3308
3309 u.buffer = NULL;
313a3dc7
CO		 3310 switch (ioctl) {
3311 case KVM_GET_LAPIC: {
2204ae3c 3312 r = -EINVAL;
bce87cce 3313 if (!lapic_in_kernel(vcpu))
2204ae3c 3314 goto out;
d1ac91d8 3315 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3316
b772ff36 3317 r = -ENOMEM;
d1ac91d8 3318 if (!u.lapic)
b772ff36 3319 goto out;
d1ac91d8 3320 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3321 if (r)
3322 goto out;
3323 r = -EFAULT;
d1ac91d8 3324 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3325 goto out;
3326 r = 0;
3327 break;
3328 }
3329 case KVM_SET_LAPIC: {
2204ae3c 3330 r = -EINVAL;
bce87cce 3331 if (!lapic_in_kernel(vcpu))
2204ae3c 3332 goto out;
ff5c2c03 3333 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3334 if (IS_ERR(u.lapic))
3335 return PTR_ERR(u.lapic);
ff5c2c03 3336
d1ac91d8 3337 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3338 break;
3339 }
f77bc6a4
ZX		 3340 case KVM_INTERRUPT: {
3341 struct kvm_interrupt irq;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&irq, argp, sizeof irq))
3345 goto out;
3346 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3347 break;
3348 }
c4abb7c9
JK		 3349 case KVM_NMI: {
3350 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3351 break;
3352 }
f077825a
PB		 3353 case KVM_SMI: {
3354 r = kvm_vcpu_ioctl_smi(vcpu);
3355 break;
3356 }
313a3dc7
CO		 3357 case KVM_SET_CPUID: {
3358 struct kvm_cpuid __user *cpuid_arg = argp;
3359 struct kvm_cpuid cpuid;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3363 goto out;
3364 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3365 break;
3366 }
07716717
DK		 3367 case KVM_SET_CPUID2: {
3368 struct kvm_cpuid2 __user *cpuid_arg = argp;
3369 struct kvm_cpuid2 cpuid;
3370
3371 r = -EFAULT;
3372 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3373 goto out;
3374 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3375 cpuid_arg->entries);
07716717
DK		 3376 break;
3377 }
3378 case KVM_GET_CPUID2: {
3379 struct kvm_cpuid2 __user *cpuid_arg = argp;
3380 struct kvm_cpuid2 cpuid;
3381
3382 r = -EFAULT;
3383 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3384 goto out;
3385 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3386 cpuid_arg->entries);
07716717
DK		 3387 if (r)
3388 goto out;
3389 r = -EFAULT;
3390 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3391 goto out;
3392 r = 0;
3393 break;
3394 }
313a3dc7 3395 case KVM_GET_MSRS:
609e36d3 3396 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3397 break;
3398 case KVM_SET_MSRS:
3399 r = msr_io(vcpu, argp, do_set_msr, 0);
3400 break;
b209749f
AK		 3401 case KVM_TPR_ACCESS_REPORTING: {
3402 struct kvm_tpr_access_ctl tac;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&tac, argp, sizeof tac))
3406 goto out;
3407 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3408 if (r)
3409 goto out;
3410 r = -EFAULT;
3411 if (copy_to_user(argp, &tac, sizeof tac))
3412 goto out;
3413 r = 0;
3414 break;
3415 };
b93463aa
AK		 3416 case KVM_SET_VAPIC_ADDR: {
3417 struct kvm_vapic_addr va;
3418
3419 r = -EINVAL;
35754c98 3420 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3421 goto out;
3422 r = -EFAULT;
3423 if (copy_from_user(&va, argp, sizeof va))
3424 goto out;
fda4e2e8 3425 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3426 break;
3427 }
890ca9ae
HY		 3428 case KVM_X86_SETUP_MCE: {
3429 u64 mcg_cap;
3430
3431 r = -EFAULT;
3432 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3433 goto out;
3434 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3435 break;
3436 }
3437 case KVM_X86_SET_MCE: {
3438 struct kvm_x86_mce mce;
3439
3440 r = -EFAULT;
3441 if (copy_from_user(&mce, argp, sizeof mce))
3442 goto out;
3443 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3444 break;
3445 }
3cfc3092
JK		 3446 case KVM_GET_VCPU_EVENTS: {
3447 struct kvm_vcpu_events events;
3448
3449 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3450
3451 r = -EFAULT;
3452 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3453 break;
3454 r = 0;
3455 break;
3456 }
3457 case KVM_SET_VCPU_EVENTS: {
3458 struct kvm_vcpu_events events;
3459
3460 r = -EFAULT;
3461 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3462 break;
3463
3464 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3465 break;
3466 }
a1efbe77
JK		 3467 case KVM_GET_DEBUGREGS: {
3468 struct kvm_debugregs dbgregs;
3469
3470 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3471
3472 r = -EFAULT;
3473 if (copy_to_user(argp, &dbgregs,
3474 sizeof(struct kvm_debugregs)))
3475 break;
3476 r = 0;
3477 break;
3478 }
3479 case KVM_SET_DEBUGREGS: {
3480 struct kvm_debugregs dbgregs;
3481
3482 r = -EFAULT;
3483 if (copy_from_user(&dbgregs, argp,
3484 sizeof(struct kvm_debugregs)))
3485 break;
3486
3487 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3488 break;
3489 }
2d5b5a66 3490 case KVM_GET_XSAVE: {
d1ac91d8 3491 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3492 r = -ENOMEM;
d1ac91d8 3493 if (!u.xsave)
2d5b5a66
SY		 3494 break;
3495
d1ac91d8 3496 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3497
3498 r = -EFAULT;
d1ac91d8 3499 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3500 break;
3501 r = 0;
3502 break;
3503 }
3504 case KVM_SET_XSAVE: {
ff5c2c03 3505 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3506 if (IS_ERR(u.xsave))
3507 return PTR_ERR(u.xsave);
2d5b5a66 3508
d1ac91d8 3509 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3510 break;
3511 }
3512 case KVM_GET_XCRS: {
d1ac91d8 3513 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3514 r = -ENOMEM;
d1ac91d8 3515 if (!u.xcrs)
2d5b5a66
SY		 3516 break;
3517
d1ac91d8 3518 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3519
3520 r = -EFAULT;
d1ac91d8 3521 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3522 sizeof(struct kvm_xcrs)))
3523 break;
3524 r = 0;
3525 break;
3526 }
3527 case KVM_SET_XCRS: {
ff5c2c03 3528 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3529 if (IS_ERR(u.xcrs))
3530 return PTR_ERR(u.xcrs);
2d5b5a66 3531
d1ac91d8 3532 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3533 break;
3534 }
92a1f12d
JR		 3535 case KVM_SET_TSC_KHZ: {
3536 u32 user_tsc_khz;
3537
3538 r = -EINVAL;
92a1f12d
JR		 3539 user_tsc_khz = (u32)arg;
3540
3541 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3542 goto out;
3543
cc578287
ZA		 3544 if (user_tsc_khz == 0)
3545 user_tsc_khz = tsc_khz;
3546
381d585c
HZ		 3547 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3548 r = 0;
92a1f12d 3549
92a1f12d
JR		 3550 goto out;
3551 }
3552 case KVM_GET_TSC_KHZ: {
cc578287 3553 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3554 goto out;
3555 }
1c0b28c2
EM		 3556 case KVM_KVMCLOCK_CTRL: {
3557 r = kvm_set_guest_paused(vcpu);
3558 goto out;
3559 }
5c919412
AS		 3560 case KVM_ENABLE_CAP: {
3561 struct kvm_enable_cap cap;
3562
3563 r = -EFAULT;
3564 if (copy_from_user(&cap, argp, sizeof(cap)))
3565 goto out;
3566 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3567 break;
3568 }
313a3dc7
CO		 3569 default:
3570 r = -EINVAL;
3571 }
3572out:
d1ac91d8 3573 kfree(u.buffer);
313a3dc7
CO		 3574 return r;
3575}
3576
5b1c1493
CO		 3577int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3578{
3579 return VM_FAULT_SIGBUS;
3580}
3581
1fe779f8
CO		 3582static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3583{
3584 int ret;
3585
3586 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3587 return -EINVAL;
1fe779f8
CO		 3588 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3589 return ret;
3590}
3591
b927a3ce
SY		 3592static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3593 u64 ident_addr)
3594{
3595 kvm->arch.ept_identity_map_addr = ident_addr;
3596 return 0;
3597}
3598
1fe779f8
CO		 3599static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3600 u32 kvm_nr_mmu_pages)
3601{
3602 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3603 return -EINVAL;
3604
79fac95e 3605 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3606
3607 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3608 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3609
79fac95e 3610 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3611 return 0;
3612}
3613
3614static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3615{
39de71ec 3616 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3617}
3618
1fe779f8
CO		 3619static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3620{
3621 int r;
3622
3623 r = 0;
3624 switch (chip->chip_id) {
3625 case KVM_IRQCHIP_PIC_MASTER:
3626 memcpy(&chip->chip.pic,
3627 &pic_irqchip(kvm)->pics[0],
3628 sizeof(struct kvm_pic_state));
3629 break;
3630 case KVM_IRQCHIP_PIC_SLAVE:
3631 memcpy(&chip->chip.pic,
3632 &pic_irqchip(kvm)->pics[1],
3633 sizeof(struct kvm_pic_state));
3634 break;
3635 case KVM_IRQCHIP_IOAPIC:
eba0226b 3636 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3637 break;
3638 default:
3639 r = -EINVAL;
3640 break;
3641 }
3642 return r;
3643}
3644
3645static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3646{
3647 int r;
3648
3649 r = 0;
3650 switch (chip->chip_id) {
3651 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3652 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3653 memcpy(&pic_irqchip(kvm)->pics[0],
3654 &chip->chip.pic,
3655 sizeof(struct kvm_pic_state));
f4f51050 3656 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3657 break;
3658 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3659 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3660 memcpy(&pic_irqchip(kvm)->pics[1],
3661 &chip->chip.pic,
3662 sizeof(struct kvm_pic_state));
f4f51050 3663 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3664 break;
3665 case KVM_IRQCHIP_IOAPIC:
eba0226b 3666 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3667 break;
3668 default:
3669 r = -EINVAL;
3670 break;
3671 }
3672 kvm_pic_update_irq(pic_irqchip(kvm));
3673 return r;
3674}
3675
e0f63cb9
SY		 3676static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3677{
34f3941c
RK		 3678 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3679
3680 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3681
3682 mutex_lock(&kps->lock);
3683 memcpy(ps, &kps->channels, sizeof(*ps));
3684 mutex_unlock(&kps->lock);
2da29bcc 3685 return 0;
e0f63cb9
SY		 3686}
3687
3688static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3689{
0185604c 3690 int i;
09edea72
RK		 3691 struct kvm_pit *pit = kvm->arch.vpit;
3692
3693 mutex_lock(&pit->pit_state.lock);
34f3941c 3694 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3695 for (i = 0; i < 3; i++)
09edea72
RK		 3696 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3697 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3698 return 0;
e9f42757
BK		 3699}
3700
3701static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3702{
e9f42757
BK		 3703 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3704 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3705 sizeof(ps->channels));
3706 ps->flags = kvm->arch.vpit->pit_state.flags;
3707 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3708 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3709 return 0;
e9f42757
BK		 3710}
3711
3712static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3713{
2da29bcc 3714 int start = 0;
0185604c 3715 int i;
e9f42757 3716 u32 prev_legacy, cur_legacy;
09edea72
RK		 3717 struct kvm_pit *pit = kvm->arch.vpit;
3718
3719 mutex_lock(&pit->pit_state.lock);
3720 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3721 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3722 if (!prev_legacy && cur_legacy)
3723 start = 1;
09edea72
RK		 3724 memcpy(&pit->pit_state.channels, &ps->channels,
3725 sizeof(pit->pit_state.channels));
3726 pit->pit_state.flags = ps->flags;
0185604c 3727 for (i = 0; i < 3; i++)
09edea72 3728 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3729 start && i == 0);
09edea72 3730 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3731 return 0;
e0f63cb9
SY		 3732}
3733
52d939a0
MT		 3734static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3735 struct kvm_reinject_control *control)
3736{
71474e2f
RK		 3737 struct kvm_pit *pit = kvm->arch.vpit;
3738
3739 if (!pit)
52d939a0 3740 return -ENXIO;
b39c90b6 3741
71474e2f
RK		 3742 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3743 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3744 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3745 */
3746 mutex_lock(&pit->pit_state.lock);
3747 kvm_pit_set_reinject(pit, control->pit_reinject);
3748 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3749
52d939a0
MT		 3750 return 0;
3751}
3752
95d4c16c 3753/**
60c34612
TY		 3754 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3755 * @kvm: kvm instance
3756 * @log: slot id and address to which we copy the log
95d4c16c 3757 *
e108ff2f
PB		 3758 * Steps 1-4 below provide general overview of dirty page logging. See
3759 * kvm_get_dirty_log_protect() function description for additional details.
3760 *
3761 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3762 * always flush the TLB (step 4) even if previous step failed and the dirty
3763 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3764 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3765 * writes will be marked dirty for next log read.
95d4c16c 3766 *
60c34612
TY		 3767 * 1. Take a snapshot of the bit and clear it if needed.
3768 * 2. Write protect the corresponding page.
e108ff2f
PB		 3769 * 3. Copy the snapshot to the userspace.
3770 * 4. Flush TLB's if needed.
5bb064dc 3771 */
60c34612 3772int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3773{
60c34612 3774 bool is_dirty = false;
e108ff2f 3775 int r;
5bb064dc 3776
79fac95e 3777 mutex_lock(&kvm->slots_lock);
5bb064dc 3778
88178fd4
KH		 3779 /*
3780 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3781 */
3782 if (kvm_x86_ops->flush_log_dirty)
3783 kvm_x86_ops->flush_log_dirty(kvm);
3784
e108ff2f 3785 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3786
3787 /*
3788 * All the TLBs can be flushed out of mmu lock, see the comments in
3789 * kvm_mmu_slot_remove_write_access().
3790 */
e108ff2f 3791 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3792 if (is_dirty)
3793 kvm_flush_remote_tlbs(kvm);
3794
79fac95e 3795 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3796 return r;
3797}
3798
aa2fbe6d
YZ		 3799int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3800 bool line_status)
23d43cf9
CD		 3801{
3802 if (!irqchip_in_kernel(kvm))
3803 return -ENXIO;
3804
3805 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3806 irq_event->irq, irq_event->level,
3807 line_status);
23d43cf9
CD		 3808 return 0;
3809}
3810
90de4a18
NA		 3811static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3812 struct kvm_enable_cap *cap)
3813{
3814 int r;
3815
3816 if (cap->flags)
3817 return -EINVAL;
3818
3819 switch (cap->cap) {
3820 case KVM_CAP_DISABLE_QUIRKS:
3821 kvm->arch.disabled_quirks = cap->args[0];
3822 r = 0;
3823 break;
49df6397
SR		 3824 case KVM_CAP_SPLIT_IRQCHIP: {
3825 mutex_lock(&kvm->lock);
b053b2ae
SR		 3826 r = -EINVAL;
3827 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3828 goto split_irqchip_unlock;
49df6397
SR		 3829 r = -EEXIST;
3830 if (irqchip_in_kernel(kvm))
3831 goto split_irqchip_unlock;
557abc40 3832 if (kvm->created_vcpus)
49df6397
SR		 3833 goto split_irqchip_unlock;
3834 r = kvm_setup_empty_irq_routing(kvm);
3835 if (r)
3836 goto split_irqchip_unlock;
3837 /* Pairs with irqchip_in_kernel. */
3838 smp_wmb();
3839 kvm->arch.irqchip_split = true;
b053b2ae 3840 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3841 r = 0;
3842split_irqchip_unlock:
3843 mutex_unlock(&kvm->lock);
3844 break;
3845 }
37131313
RK		 3846 case KVM_CAP_X2APIC_API:
3847 r = -EINVAL;
3848 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3849 break;
3850
3851 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3852 kvm->arch.x2apic_format = true;
c519265f
RK		 3853 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3854 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3855
3856 r = 0;
3857 break;
90de4a18
NA		 3858 default:
3859 r = -EINVAL;
3860 break;
3861 }
3862 return r;
3863}
3864
1fe779f8
CO		 3865long kvm_arch_vm_ioctl(struct file *filp,
3866 unsigned int ioctl, unsigned long arg)
3867{
3868 struct kvm *kvm = filp->private_data;
3869 void __user *argp = (void __user *)arg;
367e1319 3870 int r = -ENOTTY;
f0d66275
DH		 3871 /*
3872 * This union makes it completely explicit to gcc-3.x
3873 * that these two variables' stack usage should be
3874 * combined, not added together.
3875 */
3876 union {
3877 struct kvm_pit_state ps;
e9f42757 3878 struct kvm_pit_state2 ps2;
c5ff41ce 3879 struct kvm_pit_config pit_config;
f0d66275 3880 } u;
1fe779f8
CO		 3881
3882 switch (ioctl) {
3883 case KVM_SET_TSS_ADDR:
3884 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3885 break;
b927a3ce
SY		 3886 case KVM_SET_IDENTITY_MAP_ADDR: {
3887 u64 ident_addr;
3888
3889 r = -EFAULT;
3890 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3891 goto out;
3892 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3893 break;
3894 }
1fe779f8
CO		 3895 case KVM_SET_NR_MMU_PAGES:
3896 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3897 break;
3898 case KVM_GET_NR_MMU_PAGES:
3899 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3900 break;
3ddea128
MT		 3901 case KVM_CREATE_IRQCHIP: {
3902 struct kvm_pic *vpic;
3903
3904 mutex_lock(&kvm->lock);
3905 r = -EEXIST;
3906 if (kvm->arch.vpic)
3907 goto create_irqchip_unlock;
3e515705 3908 r = -EINVAL;
557abc40 3909 if (kvm->created_vcpus)
3e515705 3910 goto create_irqchip_unlock;
1fe779f8 3911 r = -ENOMEM;
3ddea128
MT		 3912 vpic = kvm_create_pic(kvm);
3913 if (vpic) {
1fe779f8
CO		 3914 r = kvm_ioapic_init(kvm);
3915 if (r) {
175504cd 3916 mutex_lock(&kvm->slots_lock);
71ba994c 3917 kvm_destroy_pic(vpic);
175504cd 3918 mutex_unlock(&kvm->slots_lock);
3ddea128 3919 goto create_irqchip_unlock;
1fe779f8
CO		 3920 }
3921 } else
3ddea128 3922 goto create_irqchip_unlock;
399ec807
AK		 3923 r = kvm_setup_default_irq_routing(kvm);
3924 if (r) {
175504cd 3925 mutex_lock(&kvm->slots_lock);
3ddea128 3926 mutex_lock(&kvm->irq_lock);
72bb2fcd 3927 kvm_ioapic_destroy(kvm);
71ba994c 3928 kvm_destroy_pic(vpic);
3ddea128 3929 mutex_unlock(&kvm->irq_lock);
175504cd 3930 mutex_unlock(&kvm->slots_lock);
71ba994c 3931 goto create_irqchip_unlock;
399ec807 3932 }
71ba994c
PB		 3933 /* Write kvm->irq_routing before kvm->arch.vpic. */
3934 smp_wmb();
3935 kvm->arch.vpic = vpic;
3ddea128
MT		 3936 create_irqchip_unlock:
3937 mutex_unlock(&kvm->lock);
1fe779f8 3938 break;
3ddea128 3939 }
7837699f 3940 case KVM_CREATE_PIT:
c5ff41ce
JK		 3941 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3942 goto create_pit;
3943 case KVM_CREATE_PIT2:
3944 r = -EFAULT;
3945 if (copy_from_user(&u.pit_config, argp,
3946 sizeof(struct kvm_pit_config)))
3947 goto out;
3948 create_pit:
250715a6 3949 mutex_lock(&kvm->lock);
269e05e4
AK		 3950 r = -EEXIST;
3951 if (kvm->arch.vpit)
3952 goto create_pit_unlock;
7837699f 3953 r = -ENOMEM;
c5ff41ce 3954 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3955 if (kvm->arch.vpit)
3956 r = 0;
269e05e4 3957 create_pit_unlock:
250715a6 3958 mutex_unlock(&kvm->lock);
7837699f 3959 break;
1fe779f8
CO		 3960 case KVM_GET_IRQCHIP: {
3961 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3962 struct kvm_irqchip *chip;
1fe779f8 3963
ff5c2c03
SL		 3964 chip = memdup_user(argp, sizeof(*chip));
3965 if (IS_ERR(chip)) {
3966 r = PTR_ERR(chip);
1fe779f8 3967 goto out;
ff5c2c03
SL		 3968 }
3969
1fe779f8 3970 r = -ENXIO;
49df6397 3971 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3972 goto get_irqchip_out;
3973 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3974 if (r)
f0d66275 3975 goto get_irqchip_out;
1fe779f8 3976 r = -EFAULT;
f0d66275
DH		 3977 if (copy_to_user(argp, chip, sizeof *chip))
3978 goto get_irqchip_out;
1fe779f8 3979 r = 0;
f0d66275
DH		 3980 get_irqchip_out:
3981 kfree(chip);
1fe779f8
CO		 3982 break;
3983 }
3984 case KVM_SET_IRQCHIP: {
3985 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3986 struct kvm_irqchip *chip;
1fe779f8 3987
ff5c2c03
SL		 3988 chip = memdup_user(argp, sizeof(*chip));
3989 if (IS_ERR(chip)) {
3990 r = PTR_ERR(chip);
1fe779f8 3991 goto out;
ff5c2c03
SL		 3992 }
3993
1fe779f8 3994 r = -ENXIO;
49df6397 3995 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3996 goto set_irqchip_out;
3997 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3998 if (r)
f0d66275 3999 goto set_irqchip_out;
1fe779f8 4000 r = 0;
f0d66275
DH		 4001 set_irqchip_out:
4002 kfree(chip);
1fe779f8
CO		 4003 break;
4004 }
e0f63cb9 4005 case KVM_GET_PIT: {
e0f63cb9 4006 r = -EFAULT;
f0d66275 4007 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4008 goto out;
4009 r = -ENXIO;
4010 if (!kvm->arch.vpit)
4011 goto out;
f0d66275 4012 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4013 if (r)
4014 goto out;
4015 r = -EFAULT;
f0d66275 4016 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4017 goto out;
4018 r = 0;
4019 break;
4020 }
4021 case KVM_SET_PIT: {
e0f63cb9 4022 r = -EFAULT;
f0d66275 4023 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4024 goto out;
4025 r = -ENXIO;
4026 if (!kvm->arch.vpit)
4027 goto out;
f0d66275 4028 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4029 break;
4030 }
e9f42757
BK		 4031 case KVM_GET_PIT2: {
4032 r = -ENXIO;
4033 if (!kvm->arch.vpit)
4034 goto out;
4035 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4036 if (r)
4037 goto out;
4038 r = -EFAULT;
4039 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4040 goto out;
4041 r = 0;
4042 break;
4043 }
4044 case KVM_SET_PIT2: {
4045 r = -EFAULT;
4046 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4047 goto out;
4048 r = -ENXIO;
4049 if (!kvm->arch.vpit)
4050 goto out;
4051 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4052 break;
4053 }
52d939a0
MT		 4054 case KVM_REINJECT_CONTROL: {
4055 struct kvm_reinject_control control;
4056 r = -EFAULT;
4057 if (copy_from_user(&control, argp, sizeof(control)))
4058 goto out;
4059 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4060 break;
4061 }
d71ba788
PB		 4062 case KVM_SET_BOOT_CPU_ID:
4063 r = 0;
4064 mutex_lock(&kvm->lock);
557abc40 4065 if (kvm->created_vcpus)
d71ba788
PB		 4066 r = -EBUSY;
4067 else
4068 kvm->arch.bsp_vcpu_id = arg;
4069 mutex_unlock(&kvm->lock);
4070 break;
ffde22ac
ES		 4071 case KVM_XEN_HVM_CONFIG: {
4072 r = -EFAULT;
4073 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4074 sizeof(struct kvm_xen_hvm_config)))
4075 goto out;
4076 r = -EINVAL;
4077 if (kvm->arch.xen_hvm_config.flags)
4078 goto out;
4079 r = 0;
4080 break;
4081 }
afbcf7ab 4082 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4083 struct kvm_clock_data user_ns;
4084 u64 now_ns;
afbcf7ab
GC		 4085
4086 r = -EFAULT;
4087 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4088 goto out;
4089
4090 r = -EINVAL;
4091 if (user_ns.flags)
4092 goto out;
4093
4094 r = 0;
395c6b0a 4095 local_irq_disable();
108b249c
PB		 4096 now_ns = __get_kvmclock_ns(kvm);
4097 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4098 local_irq_enable();
2e762ff7 4099 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4100 break;
4101 }
4102 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4103 struct kvm_clock_data user_ns;
4104 u64 now_ns;
4105
108b249c
PB		 4106 now_ns = get_kvmclock_ns(kvm);
4107 user_ns.clock = now_ns;
afbcf7ab 4108 user_ns.flags = 0;
97e69aa6 4109 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4110
4111 r = -EFAULT;
4112 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4113 goto out;
4114 r = 0;
4115 break;
4116 }
90de4a18
NA		 4117 case KVM_ENABLE_CAP: {
4118 struct kvm_enable_cap cap;
afbcf7ab 4119
90de4a18
NA		 4120 r = -EFAULT;
4121 if (copy_from_user(&cap, argp, sizeof(cap)))
4122 goto out;
4123 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4124 break;
4125 }
1fe779f8 4126 default:
c274e03a 4127 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4128 }
4129out:
4130 return r;
4131}
4132
a16b043c 4133static void kvm_init_msr_list(void)
043405e1
CO		 4134{
4135 u32 dummy[2];
4136 unsigned i, j;
4137
62ef68bb 4138 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4139 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4140 continue;
93c4adc7
PB		 4141
4142 /*
4143 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4144 * to the guests in some cases.
93c4adc7
PB		 4145 */
4146 switch (msrs_to_save[i]) {
4147 case MSR_IA32_BNDCFGS:
4148 if (!kvm_x86_ops->mpx_supported())
4149 continue;
4150 break;
9dbe6cf9
PB		 4151 case MSR_TSC_AUX:
4152 if (!kvm_x86_ops->rdtscp_supported())
4153 continue;
4154 break;
93c4adc7
PB		 4155 default:
4156 break;
4157 }
4158
043405e1
CO		 4159 if (j < i)
4160 msrs_to_save[j] = msrs_to_save[i];
4161 j++;
4162 }
4163 num_msrs_to_save = j;
62ef68bb
PB		 4164
4165 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4166 switch (emulated_msrs[i]) {
6d396b55
PB		 4167 case MSR_IA32_SMBASE:
4168 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4169 continue;
4170 break;
62ef68bb
PB		 4171 default:
4172 break;
4173 }
4174
4175 if (j < i)
4176 emulated_msrs[j] = emulated_msrs[i];
4177 j++;
4178 }
4179 num_emulated_msrs = j;
043405e1
CO		 4180}
4181
bda9020e
MT		 4182static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4183 const void *v)
bbd9b64e 4184{
70252a10
AK		 4185 int handled = 0;
4186 int n;
4187
4188 do {
4189 n = min(len, 8);
bce87cce 4190 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4191 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4192 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4193 break;
4194 handled += n;
4195 addr += n;
4196 len -= n;
4197 v += n;
4198 } while (len);
bbd9b64e 4199
70252a10 4200 return handled;
bbd9b64e
CO		 4201}
4202
bda9020e 4203static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4204{
70252a10
AK		 4205 int handled = 0;
4206 int n;
4207
4208 do {
4209 n = min(len, 8);
bce87cce 4210 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4211 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4212 addr, n, v))
4213 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4214 break;
4215 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4216 handled += n;
4217 addr += n;
4218 len -= n;
4219 v += n;
4220 } while (len);
bbd9b64e 4221
70252a10 4222 return handled;
bbd9b64e
CO		 4223}
4224
2dafc6c2
GN		 4225static void kvm_set_segment(struct kvm_vcpu *vcpu,
4226 struct kvm_segment *var, int seg)
4227{
4228 kvm_x86_ops->set_segment(vcpu, var, seg);
4229}
4230
4231void kvm_get_segment(struct kvm_vcpu *vcpu,
4232 struct kvm_segment *var, int seg)
4233{
4234 kvm_x86_ops->get_segment(vcpu, var, seg);
4235}
4236
54987b7a
PB		 4237gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4238 struct x86_exception *exception)
02f59dc9
JR		 4239{
4240 gpa_t t_gpa;
02f59dc9
JR		 4241
4242 BUG_ON(!mmu_is_nested(vcpu));
4243
4244 /* NPT walks are always user-walks */
4245 access |= PFERR_USER_MASK;
54987b7a 4246 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4247
4248 return t_gpa;
4249}
4250
ab9ae313
AK		 4251gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4252 struct x86_exception *exception)
1871c602
GN		 4253{
4254 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4255 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4256}
4257
ab9ae313
AK		 4258 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4259 struct x86_exception *exception)
1871c602
GN		 4260{
4261 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4262 access |= PFERR_FETCH_MASK;
ab9ae313 4263 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4264}
4265
ab9ae313
AK		 4266gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4267 struct x86_exception *exception)
1871c602
GN		 4268{
4269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4270 access |= PFERR_WRITE_MASK;
ab9ae313 4271 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4272}
4273
4274/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4275gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4276 struct x86_exception *exception)
1871c602 4277{
ab9ae313 4278 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4279}
4280
4281static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4282 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4283 struct x86_exception *exception)
bbd9b64e
CO		 4284{
4285 void *data = val;
10589a46 4286 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4287
4288 while (bytes) {
14dfe855 4289 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4290 exception);
bbd9b64e 4291 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4292 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4293 int ret;
4294
bcc55cba 4295 if (gpa == UNMAPPED_GVA)
ab9ae313 4296 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4297 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4298 offset, toread);
10589a46 4299 if (ret < 0) {
c3cd7ffa 4300 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4301 goto out;
4302 }
bbd9b64e 4303
77c2002e
IE		 4304 bytes -= toread;
4305 data += toread;
4306 addr += toread;
bbd9b64e 4307 }
10589a46 4308out:
10589a46 4309 return r;
bbd9b64e 4310}
77c2002e 4311
1871c602 4312/* used for instruction fetching */
0f65dd70
AK		 4313static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4314 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4315 struct x86_exception *exception)
1871c602 4316{
0f65dd70 4317 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4318 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4319 unsigned offset;
4320 int ret;
0f65dd70 4321
44583cba
PB		 4322 /* Inline kvm_read_guest_virt_helper for speed. */
4323 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4324 exception);
4325 if (unlikely(gpa == UNMAPPED_GVA))
4326 return X86EMUL_PROPAGATE_FAULT;
4327
4328 offset = addr & (PAGE_SIZE-1);
4329 if (WARN_ON(offset + bytes > PAGE_SIZE))
4330 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4331 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4332 offset, bytes);
44583cba
PB		 4333 if (unlikely(ret < 0))
4334 return X86EMUL_IO_NEEDED;
4335
4336 return X86EMUL_CONTINUE;
1871c602
GN		 4337}
4338
064aea77 4339int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4340 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4341 struct x86_exception *exception)
1871c602 4342{
0f65dd70 4343 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4345
1871c602 4346 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4347 exception);
1871c602 4348}
064aea77 4349EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4350
0f65dd70
AK		 4351static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4352 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4353 struct x86_exception *exception)
1871c602 4354{
0f65dd70 4355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4356 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4357}
4358
7a036a6f
RK		 4359static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4360 unsigned long addr, void *val, unsigned int bytes)
4361{
4362 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4363 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4364
4365 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4366}
4367
6a4d7550 4368int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4369 gva_t addr, void *val,
2dafc6c2 4370 unsigned int bytes,
bcc55cba 4371 struct x86_exception *exception)
77c2002e 4372{
0f65dd70 4373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4374 void *data = val;
4375 int r = X86EMUL_CONTINUE;
4376
4377 while (bytes) {
14dfe855
JR		 4378 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4379 PFERR_WRITE_MASK,
ab9ae313 4380 exception);
77c2002e
IE		 4381 unsigned offset = addr & (PAGE_SIZE-1);
4382 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4383 int ret;
4384
bcc55cba 4385 if (gpa == UNMAPPED_GVA)
ab9ae313 4386 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4387 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4388 if (ret < 0) {
c3cd7ffa 4389 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4390 goto out;
4391 }
4392
4393 bytes -= towrite;
4394 data += towrite;
4395 addr += towrite;
4396 }
4397out:
4398 return r;
4399}
6a4d7550 4400EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4401
af7cc7d1
XG		 4402static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4403 gpa_t *gpa, struct x86_exception *exception,
4404 bool write)
4405{
97d64b78
AK		 4406 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4407 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4408
be94f6b7
HH		 4409 /*
4410 * currently PKRU is only applied to ept enabled guest so
4411 * there is no pkey in EPT page table for L1 guest or EPT
4412 * shadow page table for L2 guest.
4413 */
97d64b78 4414 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4415 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4416 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4417 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4418 (gva & (PAGE_SIZE - 1));
4f022648 4419 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4420 return 1;
4421 }
4422
af7cc7d1
XG		 4423 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4424
4425 if (*gpa == UNMAPPED_GVA)
4426 return -1;
4427
4428 /* For APIC access vmexit */
4429 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4430 return 1;
4431
4f022648
XG		 4432 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4433 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4434 return 1;
4f022648 4435 }
bebb106a 4436
af7cc7d1
XG		 4437 return 0;
4438}
4439
3200f405 4440int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4441 const void *val, int bytes)
bbd9b64e
CO		 4442{
4443 int ret;
4444
54bf36aa 4445 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4446 if (ret < 0)
bbd9b64e 4447 return 0;
0eb05bf2 4448 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4449 return 1;
4450}
4451
77d197b2
XG		 4452struct read_write_emulator_ops {
4453 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4454 int bytes);
4455 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4456 void *val, int bytes);
4457 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4458 int bytes, void *val);
4459 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4460 void *val, int bytes);
4461 bool write;
4462};
4463
4464static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4465{
4466 if (vcpu->mmio_read_completed) {
77d197b2 4467 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4468 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4469 vcpu->mmio_read_completed = 0;
4470 return 1;
4471 }
4472
4473 return 0;
4474}
4475
4476static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4477 void *val, int bytes)
4478{
54bf36aa 4479 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4480}
4481
4482static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4483 void *val, int bytes)
4484{
4485 return emulator_write_phys(vcpu, gpa, val, bytes);
4486}
4487
4488static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4489{
4490 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4491 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4492}
4493
4494static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4495 void *val, int bytes)
4496{
4497 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4498 return X86EMUL_IO_NEEDED;
4499}
4500
4501static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4502 void *val, int bytes)
4503{
f78146b0
AK		 4504 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4505
87da7e66 4506 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4507 return X86EMUL_CONTINUE;
4508}
4509
0fbe9b0b 4510static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4511 .read_write_prepare = read_prepare,
4512 .read_write_emulate = read_emulate,
4513 .read_write_mmio = vcpu_mmio_read,
4514 .read_write_exit_mmio = read_exit_mmio,
4515};
4516
0fbe9b0b 4517static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4518 .read_write_emulate = write_emulate,
4519 .read_write_mmio = write_mmio,
4520 .read_write_exit_mmio = write_exit_mmio,
4521 .write = true,
4522};
4523
22388a3c
XG		 4524static int emulator_read_write_onepage(unsigned long addr, void *val,
4525 unsigned int bytes,
4526 struct x86_exception *exception,
4527 struct kvm_vcpu *vcpu,
0fbe9b0b 4528 const struct read_write_emulator_ops *ops)
bbd9b64e 4529{
af7cc7d1
XG		 4530 gpa_t gpa;
4531 int handled, ret;
22388a3c 4532 bool write = ops->write;
f78146b0 4533 struct kvm_mmio_fragment *frag;
10589a46 4534
22388a3c 4535 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4536
af7cc7d1 4537 if (ret < 0)
bbd9b64e 4538 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4539
4540 /* For APIC access vmexit */
af7cc7d1 4541 if (ret)
bbd9b64e
CO		 4542 goto mmio;
4543
22388a3c 4544 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4545 return X86EMUL_CONTINUE;
4546
4547mmio:
4548 /*
4549 * Is this MMIO handled locally?
4550 */
22388a3c 4551 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4552 if (handled == bytes)
bbd9b64e 4553 return X86EMUL_CONTINUE;
bbd9b64e 4554
70252a10
AK		 4555 gpa += handled;
4556 bytes -= handled;
4557 val += handled;
4558
87da7e66
XG		 4559 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4560 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4561 frag->gpa = gpa;
4562 frag->data = val;
4563 frag->len = bytes;
f78146b0 4564 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4565}
4566
52eb5a6d
XL		 4567static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4568 unsigned long addr,
22388a3c
XG		 4569 void *val, unsigned int bytes,
4570 struct x86_exception *exception,
0fbe9b0b 4571 const struct read_write_emulator_ops *ops)
bbd9b64e 4572{
0f65dd70 4573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4574 gpa_t gpa;
4575 int rc;
4576
4577 if (ops->read_write_prepare &&
4578 ops->read_write_prepare(vcpu, val, bytes))
4579 return X86EMUL_CONTINUE;
4580
4581 vcpu->mmio_nr_fragments = 0;
0f65dd70 4582
bbd9b64e
CO		 4583 /* Crossing a page boundary? */
4584 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4585 int now;
bbd9b64e
CO		 4586
4587 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4588 rc = emulator_read_write_onepage(addr, val, now, exception,
4589 vcpu, ops);
4590
bbd9b64e
CO		 4591 if (rc != X86EMUL_CONTINUE)
4592 return rc;
4593 addr += now;
bac15531
NA		 4594 if (ctxt->mode != X86EMUL_MODE_PROT64)
4595 addr = (u32)addr;
bbd9b64e
CO		 4596 val += now;
4597 bytes -= now;
4598 }
22388a3c 4599
f78146b0
AK		 4600 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4601 vcpu, ops);
4602 if (rc != X86EMUL_CONTINUE)
4603 return rc;
4604
4605 if (!vcpu->mmio_nr_fragments)
4606 return rc;
4607
4608 gpa = vcpu->mmio_fragments[0].gpa;
4609
4610 vcpu->mmio_needed = 1;
4611 vcpu->mmio_cur_fragment = 0;
4612
87da7e66 4613 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4614 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4615 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4616 vcpu->run->mmio.phys_addr = gpa;
4617
4618 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4619}
4620
4621static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4622 unsigned long addr,
4623 void *val,
4624 unsigned int bytes,
4625 struct x86_exception *exception)
4626{
4627 return emulator_read_write(ctxt, addr, val, bytes,
4628 exception, &read_emultor);
4629}
4630
52eb5a6d 4631static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4632 unsigned long addr,
4633 const void *val,
4634 unsigned int bytes,
4635 struct x86_exception *exception)
4636{
4637 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4638 exception, &write_emultor);
bbd9b64e 4639}
bbd9b64e 4640
daea3e73
AK		 4641#define CMPXCHG_TYPE(t, ptr, old, new) \
4642 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4643
4644#ifdef CONFIG_X86_64
4645# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4646#else
4647# define CMPXCHG64(ptr, old, new) \
9749a6c0 4648 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4649#endif
4650
0f65dd70
AK		 4651static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4652 unsigned long addr,
bbd9b64e
CO		 4653 const void *old,
4654 const void *new,
4655 unsigned int bytes,
0f65dd70 4656 struct x86_exception *exception)
bbd9b64e 4657{
0f65dd70 4658 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4659 gpa_t gpa;
4660 struct page *page;
4661 char *kaddr;
4662 bool exchanged;
2bacc55c 4663
daea3e73
AK		 4664 /* guests cmpxchg8b have to be emulated atomically */
4665 if (bytes > 8 || (bytes & (bytes - 1)))
4666 goto emul_write;
10589a46 4667
daea3e73 4668 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4669
daea3e73
AK		 4670 if (gpa == UNMAPPED_GVA ||
4671 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4672 goto emul_write;
2bacc55c 4673
daea3e73
AK		 4674 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4675 goto emul_write;
72dc67a6 4676
54bf36aa 4677 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4678 if (is_error_page(page))
c19b8bd6 4679 goto emul_write;
72dc67a6 4680
8fd75e12 4681 kaddr = kmap_atomic(page);
daea3e73
AK		 4682 kaddr += offset_in_page(gpa);
4683 switch (bytes) {
4684 case 1:
4685 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4686 break;
4687 case 2:
4688 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4689 break;
4690 case 4:
4691 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4692 break;
4693 case 8:
4694 exchanged = CMPXCHG64(kaddr, old, new);
4695 break;
4696 default:
4697 BUG();
2bacc55c 4698 }
8fd75e12 4699 kunmap_atomic(kaddr);
daea3e73
AK		 4700 kvm_release_page_dirty(page);
4701
4702 if (!exchanged)
4703 return X86EMUL_CMPXCHG_FAILED;
4704
54bf36aa 4705 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4706 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4707
4708 return X86EMUL_CONTINUE;
4a5f48f6 4709
3200f405 4710emul_write:
daea3e73 4711 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4712
0f65dd70 4713 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4714}
4715
cf8f70bf
GN		 4716static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4717{
4718 /* TODO: String I/O for in kernel device */
4719 int r;
4720
4721 if (vcpu->arch.pio.in)
e32edf4f 4722 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4723 vcpu->arch.pio.size, pd);
4724 else
e32edf4f 4725 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4726 vcpu->arch.pio.port, vcpu->arch.pio.size,
4727 pd);
4728 return r;
4729}
4730
6f6fbe98
XG		 4731static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4732 unsigned short port, void *val,
4733 unsigned int count, bool in)
cf8f70bf 4734{
cf8f70bf 4735 vcpu->arch.pio.port = port;
6f6fbe98 4736 vcpu->arch.pio.in = in;
7972995b 4737 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4738 vcpu->arch.pio.size = size;
4739
4740 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4741 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4742 return 1;
4743 }
4744
4745 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4746 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4747 vcpu->run->io.size = size;
4748 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4749 vcpu->run->io.count = count;
4750 vcpu->run->io.port = port;
4751
4752 return 0;
4753}
4754
6f6fbe98
XG		 4755static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4756 int size, unsigned short port, void *val,
4757 unsigned int count)
cf8f70bf 4758{
ca1d4a9e 4759 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4760 int ret;
ca1d4a9e 4761
6f6fbe98
XG		 4762 if (vcpu->arch.pio.count)
4763 goto data_avail;
cf8f70bf 4764
6f6fbe98
XG		 4765 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4766 if (ret) {
4767data_avail:
4768 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4769 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4770 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4771 return 1;
4772 }
4773
cf8f70bf
GN		 4774 return 0;
4775}
4776
6f6fbe98
XG		 4777static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4778 int size, unsigned short port,
4779 const void *val, unsigned int count)
4780{
4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782
4783 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4784 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4785 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4786}
4787
bbd9b64e
CO		 4788static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4789{
4790 return kvm_x86_ops->get_segment_base(vcpu, seg);
4791}
4792
3cb16fe7 4793static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4794{
3cb16fe7 4795 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4796}
4797
5cb56059 4798int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4799{
4800 if (!need_emulate_wbinvd(vcpu))
4801 return X86EMUL_CONTINUE;
4802
4803 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4804 int cpu = get_cpu();
4805
4806 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4807 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4808 wbinvd_ipi, NULL, 1);
2eec7343 4809 put_cpu();
f5f48ee1 4810 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4811 } else
4812 wbinvd();
f5f48ee1
SY		 4813 return X86EMUL_CONTINUE;
4814}
5cb56059
JS		 4815
4816int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4817{
4818 kvm_x86_ops->skip_emulated_instruction(vcpu);
4819 return kvm_emulate_wbinvd_noskip(vcpu);
4820}
f5f48ee1
SY		 4821EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4822
5cb56059
JS		 4823
4824
bcaf5cc5
AK		 4825static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4826{
5cb56059 4827 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4828}
4829
52eb5a6d
XL		 4830static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4831 unsigned long *dest)
bbd9b64e 4832{
16f8a6f9 4833 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4834}
4835
52eb5a6d
XL		 4836static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4837 unsigned long value)
bbd9b64e 4838{
338dbc97 4839
717746e3 4840 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4841}
4842
52a46617 4843static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4844{
52a46617 4845 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4846}
4847
717746e3 4848static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4849{
717746e3 4850 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4851 unsigned long value;
4852
4853 switch (cr) {
4854 case 0:
4855 value = kvm_read_cr0(vcpu);
4856 break;
4857 case 2:
4858 value = vcpu->arch.cr2;
4859 break;
4860 case 3:
9f8fe504 4861 value = kvm_read_cr3(vcpu);
52a46617
GN		 4862 break;
4863 case 4:
4864 value = kvm_read_cr4(vcpu);
4865 break;
4866 case 8:
4867 value = kvm_get_cr8(vcpu);
4868 break;
4869 default:
a737f256 4870 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4871 return 0;
4872 }
4873
4874 return value;
4875}
4876
717746e3 4877static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4878{
717746e3 4879 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4880 int res = 0;
4881
52a46617
GN		 4882 switch (cr) {
4883 case 0:
49a9b07e 4884 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4885 break;
4886 case 2:
4887 vcpu->arch.cr2 = val;
4888 break;
4889 case 3:
2390218b 4890 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4891 break;
4892 case 4:
a83b29c6 4893 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4894 break;
4895 case 8:
eea1cff9 4896 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4897 break;
4898 default:
a737f256 4899 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4900 res = -1;
52a46617 4901 }
0f12244f
GN		 4902
4903 return res;
52a46617
GN		 4904}
4905
717746e3 4906static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4907{
717746e3 4908 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4909}
4910
4bff1e86 4911static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4912{
4bff1e86 4913 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4914}
4915
4bff1e86 4916static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4917{
4bff1e86 4918 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4919}
4920
1ac9d0cf
AK		 4921static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4922{
4923 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4924}
4925
4926static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4927{
4928 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4929}
4930
4bff1e86
AK		 4931static unsigned long emulator_get_cached_segment_base(
4932 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4933{
4bff1e86 4934 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4935}
4936
1aa36616
AK		 4937static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4938 struct desc_struct *desc, u32 *base3,
4939 int seg)
2dafc6c2
GN		 4940{
4941 struct kvm_segment var;
4942
4bff1e86 4943 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4944 *selector = var.selector;
2dafc6c2 4945
378a8b09
GN		 4946 if (var.unusable) {
4947 memset(desc, 0, sizeof(*desc));
2dafc6c2 4948 return false;
378a8b09 4949 }
2dafc6c2
GN		 4950
4951 if (var.g)
4952 var.limit >>= 12;
4953 set_desc_limit(desc, var.limit);
4954 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4955#ifdef CONFIG_X86_64
4956 if (base3)
4957 *base3 = var.base >> 32;
4958#endif
2dafc6c2
GN		 4959 desc->type = var.type;
4960 desc->s = var.s;
4961 desc->dpl = var.dpl;
4962 desc->p = var.present;
4963 desc->avl = var.avl;
4964 desc->l = var.l;
4965 desc->d = var.db;
4966 desc->g = var.g;
4967
4968 return true;
4969}
4970
1aa36616
AK		 4971static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4972 struct desc_struct *desc, u32 base3,
4973 int seg)
2dafc6c2 4974{
4bff1e86 4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4976 struct kvm_segment var;
4977
1aa36616 4978 var.selector = selector;
2dafc6c2 4979 var.base = get_desc_base(desc);
5601d05b
GN		 4980#ifdef CONFIG_X86_64
4981 var.base |= ((u64)base3) << 32;
4982#endif
2dafc6c2
GN		 4983 var.limit = get_desc_limit(desc);
4984 if (desc->g)
4985 var.limit = (var.limit << 12) | 0xfff;
4986 var.type = desc->type;
2dafc6c2
GN		 4987 var.dpl = desc->dpl;
4988 var.db = desc->d;
4989 var.s = desc->s;
4990 var.l = desc->l;
4991 var.g = desc->g;
4992 var.avl = desc->avl;
4993 var.present = desc->p;
4994 var.unusable = !var.present;
4995 var.padding = 0;
4996
4997 kvm_set_segment(vcpu, &var, seg);
4998 return;
4999}
5000
717746e3
AK		 5001static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5002 u32 msr_index, u64 *pdata)
5003{
609e36d3
PB		 5004 struct msr_data msr;
5005 int r;
5006
5007 msr.index = msr_index;
5008 msr.host_initiated = false;
5009 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5010 if (r)
5011 return r;
5012
5013 *pdata = msr.data;
5014 return 0;
717746e3
AK		 5015}
5016
5017static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5018 u32 msr_index, u64 data)
5019{
8fe8ab46
WA		 5020 struct msr_data msr;
5021
5022 msr.data = data;
5023 msr.index = msr_index;
5024 msr.host_initiated = false;
5025 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5026}
5027
64d60670
PB		 5028static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5029{
5030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5031
5032 return vcpu->arch.smbase;
5033}
5034
5035static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5036{
5037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5038
5039 vcpu->arch.smbase = smbase;
5040}
5041
67f4d428
NA		 5042static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5043 u32 pmc)
5044{
c6702c9d 5045 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5046}
5047
222d21aa
AK		 5048static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5049 u32 pmc, u64 *pdata)
5050{
c6702c9d 5051 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5052}
5053
6c3287f7
AK		 5054static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5055{
5056 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5057}
5058
5037f6f3
AK		 5059static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5060{
5061 preempt_disable();
5197b808 5062 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5063 /*
5064 * CR0.TS may reference the host fpu state, not the guest fpu state,
5065 * so it may be clear at this point.
5066 */
5067 clts();
5068}
5069
5070static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5071{
5072 preempt_enable();
5073}
5074
2953538e 5075static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5076 struct x86_instruction_info *info,
c4f035c6
AK		 5077 enum x86_intercept_stage stage)
5078{
2953538e 5079 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5080}
5081
0017f93a 5082static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5083 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5084{
0017f93a 5085 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5086}
5087
dd856efa
AK		 5088static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5089{
5090 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5091}
5092
5093static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5094{
5095 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5096}
5097
801806d9
NA		 5098static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5099{
5100 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5101}
5102
0225fb50 5103static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5104 .read_gpr = emulator_read_gpr,
5105 .write_gpr = emulator_write_gpr,
1871c602 5106 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5107 .write_std = kvm_write_guest_virt_system,
7a036a6f 5108 .read_phys = kvm_read_guest_phys_system,
1871c602 5109 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5110 .read_emulated = emulator_read_emulated,
5111 .write_emulated = emulator_write_emulated,
5112 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5113 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5114 .pio_in_emulated = emulator_pio_in_emulated,
5115 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5116 .get_segment = emulator_get_segment,
5117 .set_segment = emulator_set_segment,
5951c442 5118 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5119 .get_gdt = emulator_get_gdt,
160ce1f1 5120 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5121 .set_gdt = emulator_set_gdt,
5122 .set_idt = emulator_set_idt,
52a46617
GN		 5123 .get_cr = emulator_get_cr,
5124 .set_cr = emulator_set_cr,
9c537244 5125 .cpl = emulator_get_cpl,
35aa5375
GN		 5126 .get_dr = emulator_get_dr,
5127 .set_dr = emulator_set_dr,
64d60670
PB		 5128 .get_smbase = emulator_get_smbase,
5129 .set_smbase = emulator_set_smbase,
717746e3
AK		 5130 .set_msr = emulator_set_msr,
5131 .get_msr = emulator_get_msr,
67f4d428 5132 .check_pmc = emulator_check_pmc,
222d21aa 5133 .read_pmc = emulator_read_pmc,
6c3287f7 5134 .halt = emulator_halt,
bcaf5cc5 5135 .wbinvd = emulator_wbinvd,
d6aa1000 5136 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5137 .get_fpu = emulator_get_fpu,
5138 .put_fpu = emulator_put_fpu,
c4f035c6 5139 .intercept = emulator_intercept,
bdb42f5a 5140 .get_cpuid = emulator_get_cpuid,
801806d9 5141 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5142};
5143
95cb2295
GN		 5144static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5145{
37ccdcbe 5146 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5147 /*
5148 * an sti; sti; sequence only disable interrupts for the first
5149 * instruction. So, if the last instruction, be it emulated or
5150 * not, left the system with the INT_STI flag enabled, it
5151 * means that the last instruction is an sti. We should not
5152 * leave the flag on in this case. The same goes for mov ss
5153 */
37ccdcbe
PB		 5154 if (int_shadow & mask)
5155 mask = 0;
6addfc42 5156 if (unlikely(int_shadow || mask)) {
95cb2295 5157 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5158 if (!mask)
5159 kvm_make_request(KVM_REQ_EVENT, vcpu);
5160 }
95cb2295
GN		 5161}
5162
ef54bcfe 5163static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5164{
5165 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5166 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5167 return kvm_propagate_fault(vcpu, &ctxt->exception);
5168
5169 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5170 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5171 ctxt->exception.error_code);
54b8486f 5172 else
da9cb575 5173 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5174 return false;
54b8486f
GN		 5175}
5176
8ec4722d
MG		 5177static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5178{
adf52235 5179 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5180 int cs_db, cs_l;
5181
8ec4722d
MG		 5182 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5183
adf52235
TY		 5184 ctxt->eflags = kvm_get_rflags(vcpu);
5185 ctxt->eip = kvm_rip_read(vcpu);
5186 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5187 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5188 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5189 cs_db ? X86EMUL_MODE_PROT32 :
5190 X86EMUL_MODE_PROT16;
a584539b 5191 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5192 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5193 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5194 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5195
dd856efa 5196 init_decode_cache(ctxt);
7ae441ea 5197 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5198}
5199
71f9833b 5200int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5201{
9d74191a 5202 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5203 int ret;
5204
5205 init_emulate_ctxt(vcpu);
5206
9dac77fa
AK		 5207 ctxt->op_bytes = 2;
5208 ctxt->ad_bytes = 2;
5209 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5210 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5211
5212 if (ret != X86EMUL_CONTINUE)
5213 return EMULATE_FAIL;
5214
9dac77fa 5215 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5216 kvm_rip_write(vcpu, ctxt->eip);
5217 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5218
5219 if (irq == NMI_VECTOR)
7460fb4a 5220 vcpu->arch.nmi_pending = 0;
63995653
MG		 5221 else
5222 vcpu->arch.interrupt.pending = false;
5223
5224 return EMULATE_DONE;
5225}
5226EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5227
6d77dbfc
GN		 5228static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5229{
fc3a9157
JR		 5230 int r = EMULATE_DONE;
5231
6d77dbfc
GN		 5232 ++vcpu->stat.insn_emulation_fail;
5233 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5234 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5235 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5236 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5237 vcpu->run->internal.ndata = 0;
5238 r = EMULATE_FAIL;
5239 }
6d77dbfc 5240 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5241
5242 return r;
6d77dbfc
GN		 5243}
5244
93c05d3e 5245static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5246 bool write_fault_to_shadow_pgtable,
5247 int emulation_type)
a6f177ef 5248{
95b3cf69 5249 gpa_t gpa = cr2;
ba049e93 5250 kvm_pfn_t pfn;
a6f177ef 5251
991eebf9
GN		 5252 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5253 return false;
5254
95b3cf69
XG		 5255 if (!vcpu->arch.mmu.direct_map) {
5256 /*
5257 * Write permission should be allowed since only
5258 * write access need to be emulated.
5259 */
5260 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5261
95b3cf69
XG		 5262 /*
5263 * If the mapping is invalid in guest, let cpu retry
5264 * it to generate fault.
5265 */
5266 if (gpa == UNMAPPED_GVA)
5267 return true;
5268 }
a6f177ef 5269
8e3d9d06
XG		 5270 /*
5271 * Do not retry the unhandleable instruction if it faults on the
5272 * readonly host memory, otherwise it will goto a infinite loop:
5273 * retry instruction -> write #PF -> emulation fail -> retry
5274 * instruction -> ...
5275 */
5276 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5277
5278 /*
5279 * If the instruction failed on the error pfn, it can not be fixed,
5280 * report the error to userspace.
5281 */
5282 if (is_error_noslot_pfn(pfn))
5283 return false;
5284
5285 kvm_release_pfn_clean(pfn);
5286
5287 /* The instructions are well-emulated on direct mmu. */
5288 if (vcpu->arch.mmu.direct_map) {
5289 unsigned int indirect_shadow_pages;
5290
5291 spin_lock(&vcpu->kvm->mmu_lock);
5292 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5293 spin_unlock(&vcpu->kvm->mmu_lock);
5294
5295 if (indirect_shadow_pages)
5296 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5297
a6f177ef 5298 return true;
8e3d9d06 5299 }
a6f177ef 5300
95b3cf69
XG		 5301 /*
5302 * if emulation was due to access to shadowed page table
5303 * and it failed try to unshadow page and re-enter the
5304 * guest to let CPU execute the instruction.
5305 */
5306 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5307
5308 /*
5309 * If the access faults on its page table, it can not
5310 * be fixed by unprotecting shadow page and it should
5311 * be reported to userspace.
5312 */
5313 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5314}
5315
1cb3f3ae
XG		 5316static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5317 unsigned long cr2, int emulation_type)
5318{
5319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5320 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5321
5322 last_retry_eip = vcpu->arch.last_retry_eip;
5323 last_retry_addr = vcpu->arch.last_retry_addr;
5324
5325 /*
5326 * If the emulation is caused by #PF and it is non-page_table
5327 * writing instruction, it means the VM-EXIT is caused by shadow
5328 * page protected, we can zap the shadow page and retry this
5329 * instruction directly.
5330 *
5331 * Note: if the guest uses a non-page-table modifying instruction
5332 * on the PDE that points to the instruction, then we will unmap
5333 * the instruction and go to an infinite loop. So, we cache the
5334 * last retried eip and the last fault address, if we meet the eip
5335 * and the address again, we can break out of the potential infinite
5336 * loop.
5337 */
5338 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5339
5340 if (!(emulation_type & EMULTYPE_RETRY))
5341 return false;
5342
5343 if (x86_page_table_writing_insn(ctxt))
5344 return false;
5345
5346 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5347 return false;
5348
5349 vcpu->arch.last_retry_eip = ctxt->eip;
5350 vcpu->arch.last_retry_addr = cr2;
5351
5352 if (!vcpu->arch.mmu.direct_map)
5353 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5354
22368028 5355 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5356
5357 return true;
5358}
5359
716d51ab
GN		 5360static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5361static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5362
64d60670 5363static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5364{
64d60670 5365 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5366 /* This is a good place to trace that we are exiting SMM. */
5367 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5368
c43203ca
PB		 5369 /* Process a latched INIT or SMI, if any. */
5370 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5371 }
699023e2
PB		 5372
5373 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5374}
5375
5376static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5377{
5378 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5379
a584539b 5380 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5381
5382 if (changed & HF_SMM_MASK)
5383 kvm_smm_changed(vcpu);
a584539b
PB		 5384}
5385
4a1e10d5
PB		 5386static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5387 unsigned long *db)
5388{
5389 u32 dr6 = 0;
5390 int i;
5391 u32 enable, rwlen;
5392
5393 enable = dr7;
5394 rwlen = dr7 >> 16;
5395 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5396 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5397 dr6 |= (1 << i);
5398 return dr6;
5399}
5400
6addfc42 5401static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5402{
5403 struct kvm_run *kvm_run = vcpu->run;
5404
5405 /*
6addfc42
PB		 5406 * rflags is the old, "raw" value of the flags. The new value has
5407 * not been saved yet.
663f4c61
PB		 5408 *
5409 * This is correct even for TF set by the guest, because "the
5410 * processor will not generate this exception after the instruction
5411 * that sets the TF flag".
5412 */
663f4c61
PB		 5413 if (unlikely(rflags & X86_EFLAGS_TF)) {
5414 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5415 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5416 DR6_RTM;
663f4c61
PB		 5417 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5418 kvm_run->debug.arch.exception = DB_VECTOR;
5419 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5420 *r = EMULATE_USER_EXIT;
5421 } else {
5422 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5423 /*
5424 * "Certain debug exceptions may clear bit 0-3. The
5425 * remaining contents of the DR6 register are never
5426 * cleared by the processor".
5427 */
5428 vcpu->arch.dr6 &= ~15;
6f43ed01 5429 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5430 kvm_queue_exception(vcpu, DB_VECTOR);
5431 }
5432 }
5433}
5434
4a1e10d5
PB		 5435static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5436{
4a1e10d5
PB		 5437 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5438 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5439 struct kvm_run *kvm_run = vcpu->run;
5440 unsigned long eip = kvm_get_linear_rip(vcpu);
5441 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5442 vcpu->arch.guest_debug_dr7,
5443 vcpu->arch.eff_db);
5444
5445 if (dr6 != 0) {
6f43ed01 5446 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5447 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5448 kvm_run->debug.arch.exception = DB_VECTOR;
5449 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5450 *r = EMULATE_USER_EXIT;
5451 return true;
5452 }
5453 }
5454
4161a569
NA		 5455 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5456 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5457 unsigned long eip = kvm_get_linear_rip(vcpu);
5458 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5459 vcpu->arch.dr7,
5460 vcpu->arch.db);
5461
5462 if (dr6 != 0) {
5463 vcpu->arch.dr6 &= ~15;
6f43ed01 5464 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5465 kvm_queue_exception(vcpu, DB_VECTOR);
5466 *r = EMULATE_DONE;
5467 return true;
5468 }
5469 }
5470
5471 return false;
5472}
5473
51d8b661
AP		 5474int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5475 unsigned long cr2,
dc25e89e
AP		 5476 int emulation_type,
5477 void *insn,
5478 int insn_len)
bbd9b64e 5479{
95cb2295 5480 int r;
9d74191a 5481 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5482 bool writeback = true;
93c05d3e 5483 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5484
93c05d3e
XG		 5485 /*
5486 * Clear write_fault_to_shadow_pgtable here to ensure it is
5487 * never reused.
5488 */
5489 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5490 kvm_clear_exception_queue(vcpu);
8d7d8102 5491
571008da 5492 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5493 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5494
5495 /*
5496 * We will reenter on the same instruction since
5497 * we do not set complete_userspace_io. This does not
5498 * handle watchpoints yet, those would be handled in
5499 * the emulate_ops.
5500 */
5501 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5502 return r;
5503
9d74191a
TY		 5504 ctxt->interruptibility = 0;
5505 ctxt->have_exception = false;
e0ad0b47 5506 ctxt->exception.vector = -1;
9d74191a 5507 ctxt->perm_ok = false;
bbd9b64e 5508
b51e974f 5509 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5510
9d74191a 5511 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5512
e46479f8 5513 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5514 ++vcpu->stat.insn_emulation;
1d2887e2 5515 if (r != EMULATION_OK) {
4005996e
AK		 5516 if (emulation_type & EMULTYPE_TRAP_UD)
5517 return EMULATE_FAIL;
991eebf9
GN		 5518 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5519 emulation_type))
bbd9b64e 5520 return EMULATE_DONE;
6d77dbfc
GN		 5521 if (emulation_type & EMULTYPE_SKIP)
5522 return EMULATE_FAIL;
5523 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5524 }
5525 }
5526
ba8afb6b 5527 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5528 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5529 if (ctxt->eflags & X86_EFLAGS_RF)
5530 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5531 return EMULATE_DONE;
5532 }
5533
1cb3f3ae
XG		 5534 if (retry_instruction(ctxt, cr2, emulation_type))
5535 return EMULATE_DONE;
5536
7ae441ea 5537 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5538 changes registers values during IO operation */
7ae441ea
GN		 5539 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5540 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5541 emulator_invalidate_register_cache(ctxt);
7ae441ea 5542 }
4d2179e1 5543
5cd21917 5544restart:
9d74191a 5545 r = x86_emulate_insn(ctxt);
bbd9b64e 5546
775fde86
JR		 5547 if (r == EMULATION_INTERCEPTED)
5548 return EMULATE_DONE;
5549
d2ddd1c4 5550 if (r == EMULATION_FAILED) {
991eebf9
GN		 5551 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5552 emulation_type))
c3cd7ffa
GN		 5553 return EMULATE_DONE;
5554
6d77dbfc 5555 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5556 }
5557
9d74191a 5558 if (ctxt->have_exception) {
d2ddd1c4 5559 r = EMULATE_DONE;
ef54bcfe
PB		 5560 if (inject_emulated_exception(vcpu))
5561 return r;
d2ddd1c4 5562 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5563 if (!vcpu->arch.pio.in) {
5564 /* FIXME: return into emulator if single-stepping. */
3457e419 5565 vcpu->arch.pio.count = 0;
0912c977 5566 } else {
7ae441ea 5567 writeback = false;
716d51ab
GN		 5568 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5569 }
ac0a48c3 5570 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5571 } else if (vcpu->mmio_needed) {
5572 if (!vcpu->mmio_is_write)
5573 writeback = false;
ac0a48c3 5574 r = EMULATE_USER_EXIT;
716d51ab 5575 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5576 } else if (r == EMULATION_RESTART)
5cd21917 5577 goto restart;
d2ddd1c4
GN		 5578 else
5579 r = EMULATE_DONE;
f850e2e6 5580
7ae441ea 5581 if (writeback) {
6addfc42 5582 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5583 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5584 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5585 if (vcpu->arch.hflags != ctxt->emul_flags)
5586 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5587 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5588 if (r == EMULATE_DONE)
6addfc42 5589 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5590 if (!ctxt->have_exception ||
5591 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5592 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5593
5594 /*
5595 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5596 * do nothing, and it will be requested again as soon as
5597 * the shadow expires. But we still need to check here,
5598 * because POPF has no interrupt shadow.
5599 */
5600 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5601 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5602 } else
5603 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5604
5605 return r;
de7d789a 5606}
51d8b661 5607EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5608
cf8f70bf 5609int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5610{
cf8f70bf 5611 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5612 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5613 size, port, &val, 1);
cf8f70bf 5614 /* do not return to emulator after return from userspace */
7972995b 5615 vcpu->arch.pio.count = 0;
de7d789a
CO		 5616 return ret;
5617}
cf8f70bf 5618EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5619
251a5fd6 5620static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5621{
0a3aee0d 5622 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5623 return 0;
8cfdc000
ZA		 5624}
5625
5626static void tsc_khz_changed(void *data)
c8076604 5627{
8cfdc000
ZA		 5628 struct cpufreq_freqs *freq = data;
5629 unsigned long khz = 0;
5630
5631 if (data)
5632 khz = freq->new;
5633 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5634 khz = cpufreq_quick_get(raw_smp_processor_id());
5635 if (!khz)
5636 khz = tsc_khz;
0a3aee0d 5637 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5638}
5639
c8076604
GH		 5640static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5641 void *data)
5642{
5643 struct cpufreq_freqs *freq = data;
5644 struct kvm *kvm;
5645 struct kvm_vcpu *vcpu;
5646 int i, send_ipi = 0;
5647
8cfdc000
ZA		 5648 /*
5649 * We allow guests to temporarily run on slowing clocks,
5650 * provided we notify them after, or to run on accelerating
5651 * clocks, provided we notify them before. Thus time never
5652 * goes backwards.
5653 *
5654 * However, we have a problem. We can't atomically update
5655 * the frequency of a given CPU from this function; it is
5656 * merely a notifier, which can be called from any CPU.
5657 * Changing the TSC frequency at arbitrary points in time
5658 * requires a recomputation of local variables related to
5659 * the TSC for each VCPU. We must flag these local variables
5660 * to be updated and be sure the update takes place with the
5661 * new frequency before any guests proceed.
5662 *
5663 * Unfortunately, the combination of hotplug CPU and frequency
5664 * change creates an intractable locking scenario; the order
5665 * of when these callouts happen is undefined with respect to
5666 * CPU hotplug, and they can race with each other. As such,
5667 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5668 * undefined; you can actually have a CPU frequency change take
5669 * place in between the computation of X and the setting of the
5670 * variable. To protect against this problem, all updates of
5671 * the per_cpu tsc_khz variable are done in an interrupt
5672 * protected IPI, and all callers wishing to update the value
5673 * must wait for a synchronous IPI to complete (which is trivial
5674 * if the caller is on the CPU already). This establishes the
5675 * necessary total order on variable updates.
5676 *
5677 * Note that because a guest time update may take place
5678 * anytime after the setting of the VCPU's request bit, the
5679 * correct TSC value must be set before the request. However,
5680 * to ensure the update actually makes it to any guest which
5681 * starts running in hardware virtualization between the set
5682 * and the acquisition of the spinlock, we must also ping the
5683 * CPU after setting the request bit.
5684 *
5685 */
5686
c8076604
GH		 5687 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5688 return 0;
5689 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5690 return 0;
8cfdc000
ZA		 5691
5692 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5693
2f303b74 5694 spin_lock(&kvm_lock);
c8076604 5695 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5696 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5697 if (vcpu->cpu != freq->cpu)
5698 continue;
c285545f 5699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5700 if (vcpu->cpu != smp_processor_id())
8cfdc000 5701 send_ipi = 1;
c8076604
GH		 5702 }
5703 }
2f303b74 5704 spin_unlock(&kvm_lock);
c8076604
GH		 5705
5706 if (freq->old < freq->new && send_ipi) {
5707 /*
5708 * We upscale the frequency. Must make the guest
5709 * doesn't see old kvmclock values while running with
5710 * the new frequency, otherwise we risk the guest sees
5711 * time go backwards.
5712 *
5713 * In case we update the frequency for another cpu
5714 * (which might be in guest context) send an interrupt
5715 * to kick the cpu out of guest context. Next time
5716 * guest context is entered kvmclock will be updated,
5717 * so the guest will not see stale values.
5718 */
8cfdc000 5719 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5720 }
5721 return 0;
5722}
5723
5724static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5725 .notifier_call = kvmclock_cpufreq_notifier
5726};
5727
251a5fd6 5728static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5729{
251a5fd6
SAS		 5730 tsc_khz_changed(NULL);
5731 return 0;
8cfdc000
ZA		 5732}
5733
b820cc0c
ZA		 5734static void kvm_timer_init(void)
5735{
c285545f 5736 max_tsc_khz = tsc_khz;
460dd42e 5737
b820cc0c 5738 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5739#ifdef CONFIG_CPU_FREQ
5740 struct cpufreq_policy policy;
758f588d
BP		 5741 int cpu;
5742
c285545f 5743 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5744 cpu = get_cpu();
5745 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5746 if (policy.cpuinfo.max_freq)
5747 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5748 put_cpu();
c285545f 5749#endif
b820cc0c
ZA		 5750 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5751 CPUFREQ_TRANSITION_NOTIFIER);
5752 }
c285545f 5753 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5754
251a5fd6
SAS		 5755 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5756 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5757}
5758
ff9d07a0
ZY		 5759static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5760
f5132b01 5761int kvm_is_in_guest(void)
ff9d07a0 5762{
086c9855 5763 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5764}
5765
5766static int kvm_is_user_mode(void)
5767{
5768 int user_mode = 3;
dcf46b94 5769
086c9855
AS		 5770 if (__this_cpu_read(current_vcpu))
5771 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5772
ff9d07a0
ZY		 5773 return user_mode != 0;
5774}
5775
5776static unsigned long kvm_get_guest_ip(void)
5777{
5778 unsigned long ip = 0;
dcf46b94 5779
086c9855
AS		 5780 if (__this_cpu_read(current_vcpu))
5781 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5782
ff9d07a0
ZY		 5783 return ip;
5784}
5785
5786static struct perf_guest_info_callbacks kvm_guest_cbs = {
5787 .is_in_guest = kvm_is_in_guest,
5788 .is_user_mode = kvm_is_user_mode,
5789 .get_guest_ip = kvm_get_guest_ip,
5790};
5791
5792void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5793{
086c9855 5794 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5795}
5796EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5797
5798void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5799{
086c9855 5800 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5801}
5802EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5803
ce88decf
XG		 5804static void kvm_set_mmio_spte_mask(void)
5805{
5806 u64 mask;
5807 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5808
5809 /*
5810 * Set the reserved bits and the present bit of an paging-structure
5811 * entry to generate page fault with PFER.RSV = 1.
5812 */
885032b9 5813 /* Mask the reserved physical address bits. */
d1431483 5814 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5815
5816 /* Bit 62 is always reserved for 32bit host. */
5817 mask |= 0x3ull << 62;
5818
5819 /* Set the present bit. */
ce88decf
XG		 5820 mask |= 1ull;
5821
5822#ifdef CONFIG_X86_64
5823 /*
5824 * If reserved bit is not supported, clear the present bit to disable
5825 * mmio page fault.
5826 */
5827 if (maxphyaddr == 52)
5828 mask &= ~1ull;
5829#endif
5830
5831 kvm_mmu_set_mmio_spte_mask(mask);
5832}
5833
16e8d74d
MT		 5834#ifdef CONFIG_X86_64
5835static void pvclock_gtod_update_fn(struct work_struct *work)
5836{
d828199e
MT		 5837 struct kvm *kvm;
5838
5839 struct kvm_vcpu *vcpu;
5840 int i;
5841
2f303b74 5842 spin_lock(&kvm_lock);
d828199e
MT		 5843 list_for_each_entry(kvm, &vm_list, vm_list)
5844 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5845 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5846 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5847 spin_unlock(&kvm_lock);
16e8d74d
MT		 5848}
5849
5850static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5851
5852/*
5853 * Notification about pvclock gtod data update.
5854 */
5855static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5856 void *priv)
5857{
5858 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5859 struct timekeeper *tk = priv;
5860
5861 update_pvclock_gtod(tk);
5862
5863 /* disable master clock if host does not trust, or does not
5864 * use, TSC clocksource
5865 */
5866 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5867 atomic_read(&kvm_guest_has_master_clock) != 0)
5868 queue_work(system_long_wq, &pvclock_gtod_work);
5869
5870 return 0;
5871}
5872
5873static struct notifier_block pvclock_gtod_notifier = {
5874 .notifier_call = pvclock_gtod_notify,
5875};
5876#endif
5877
f8c16bba 5878int kvm_arch_init(void *opaque)
043405e1 5879{
b820cc0c 5880 int r;
6b61edf7 5881 struct kvm_x86_ops *ops = opaque;
f8c16bba 5882
f8c16bba
ZX		 5883 if (kvm_x86_ops) {
5884 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5885 r = -EEXIST;
5886 goto out;
f8c16bba
ZX		 5887 }
5888
5889 if (!ops->cpu_has_kvm_support()) {
5890 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5891 r = -EOPNOTSUPP;
5892 goto out;
f8c16bba
ZX		 5893 }
5894 if (ops->disabled_by_bios()) {
5895 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5896 r = -EOPNOTSUPP;
5897 goto out;
f8c16bba
ZX		 5898 }
5899
013f6a5d
MT		 5900 r = -ENOMEM;
5901 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5902 if (!shared_msrs) {
5903 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5904 goto out;
5905 }
5906
97db56ce
AK		 5907 r = kvm_mmu_module_init();
5908 if (r)
013f6a5d 5909 goto out_free_percpu;
97db56ce 5910
ce88decf 5911 kvm_set_mmio_spte_mask();
97db56ce 5912
f8c16bba 5913 kvm_x86_ops = ops;
920c8377 5914
7b52345e 5915 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5916 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5917 PT_PRESENT_MASK);
b820cc0c 5918 kvm_timer_init();
c8076604 5919
ff9d07a0
ZY		 5920 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5921
d366bf7e 5922 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5923 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5924
c5cc421b 5925 kvm_lapic_init();
16e8d74d
MT		 5926#ifdef CONFIG_X86_64
5927 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5928#endif
5929
f8c16bba 5930 return 0;
56c6d28a 5931
013f6a5d
MT		 5932out_free_percpu:
5933 free_percpu(shared_msrs);
56c6d28a 5934out:
56c6d28a 5935 return r;
043405e1 5936}
8776e519 5937
f8c16bba
ZX		 5938void kvm_arch_exit(void)
5939{
ff9d07a0
ZY		 5940 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5941
888d256e
JK		 5942 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5943 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5944 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 5945 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 5946#ifdef CONFIG_X86_64
5947 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5948#endif
f8c16bba 5949 kvm_x86_ops = NULL;
56c6d28a 5950 kvm_mmu_module_exit();
013f6a5d 5951 free_percpu(shared_msrs);
56c6d28a 5952}
f8c16bba 5953
5cb56059 5954int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5955{
5956 ++vcpu->stat.halt_exits;
35754c98 5957 if (lapic_in_kernel(vcpu)) {
a4535290 5958 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5959 return 1;
5960 } else {
5961 vcpu->run->exit_reason = KVM_EXIT_HLT;
5962 return 0;
5963 }
5964}
5cb56059
JS		 5965EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5966
5967int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5968{
5969 kvm_x86_ops->skip_emulated_instruction(vcpu);
5970 return kvm_vcpu_halt(vcpu);
5971}
8776e519
HB		 5972EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5973
6aef266c
SV		 5974/*
5975 * kvm_pv_kick_cpu_op: Kick a vcpu.
5976 *
5977 * @apicid - apicid of vcpu to be kicked.
5978 */
5979static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5980{
24d2166b 5981 struct kvm_lapic_irq lapic_irq;
6aef266c 5982
24d2166b
R		 5983 lapic_irq.shorthand = 0;
5984 lapic_irq.dest_mode = 0;
5985 lapic_irq.dest_id = apicid;
93bbf0b8 5986 lapic_irq.msi_redir_hint = false;
6aef266c 5987
24d2166b 5988 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5989 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5990}
5991
d62caabb
AS		 5992void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5993{
5994 vcpu->arch.apicv_active = false;
5995 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5996}
5997
8776e519
HB		 5998int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5999{
6000 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6001 int op_64_bit, r = 1;
8776e519 6002
5cb56059
JS		 6003 kvm_x86_ops->skip_emulated_instruction(vcpu);
6004
55cd8e5a
GN		 6005 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6006 return kvm_hv_hypercall(vcpu);
6007
5fdbf976
MT		 6008 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6009 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6010 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6011 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6012 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6013
229456fc 6014 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6015
a449c7aa
NA		 6016 op_64_bit = is_64_bit_mode(vcpu);
6017 if (!op_64_bit) {
8776e519
HB		 6018 nr &= 0xFFFFFFFF;
6019 a0 &= 0xFFFFFFFF;
6020 a1 &= 0xFFFFFFFF;
6021 a2 &= 0xFFFFFFFF;
6022 a3 &= 0xFFFFFFFF;
6023 }
6024
07708c4a
JK		 6025 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6026 ret = -KVM_EPERM;
6027 goto out;
6028 }
6029
8776e519 6030 switch (nr) {
b93463aa
AK		 6031 case KVM_HC_VAPIC_POLL_IRQ:
6032 ret = 0;
6033 break;
6aef266c
SV		 6034 case KVM_HC_KICK_CPU:
6035 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6036 ret = 0;
6037 break;
8776e519
HB		 6038 default:
6039 ret = -KVM_ENOSYS;
6040 break;
6041 }
07708c4a 6042out:
a449c7aa
NA		 6043 if (!op_64_bit)
6044 ret = (u32)ret;
5fdbf976 6045 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6046 ++vcpu->stat.hypercalls;
2f333bcb 6047 return r;
8776e519
HB		 6048}
6049EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6050
b6785def 6051static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6052{
d6aa1000 6053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6054 char instruction[3];
5fdbf976 6055 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6056
8776e519 6057 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6058
9d74191a 6059 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6060}
6061
851ba692 6062static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6063{
782d422b
MG		 6064 return vcpu->run->request_interrupt_window &&
6065 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6066}
6067
851ba692 6068static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6069{
851ba692
AK		 6070 struct kvm_run *kvm_run = vcpu->run;
6071
91586a3b 6072 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6073 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6074 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6075 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6076 kvm_run->ready_for_interrupt_injection =
6077 pic_in_kernel(vcpu->kvm) ||
782d422b 6078 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6079}
6080
95ba8273
GN		 6081static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6082{
6083 int max_irr, tpr;
6084
6085 if (!kvm_x86_ops->update_cr8_intercept)
6086 return;
6087
bce87cce 6088 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6089 return;
6090
d62caabb
AS		 6091 if (vcpu->arch.apicv_active)
6092 return;
6093
8db3baa2
GN		 6094 if (!vcpu->arch.apic->vapic_addr)
6095 max_irr = kvm_lapic_find_highest_irr(vcpu);
6096 else
6097 max_irr = -1;
95ba8273
GN		 6098
6099 if (max_irr != -1)
6100 max_irr >>= 4;
6101
6102 tpr = kvm_lapic_get_cr8(vcpu);
6103
6104 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6105}
6106
b6b8a145 6107static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6108{
b6b8a145
JK		 6109 int r;
6110
95ba8273 6111 /* try to reinject previous events if any */
b59bb7bd 6112 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6113 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6114 vcpu->arch.exception.has_error_code,
6115 vcpu->arch.exception.error_code);
d6e8c854
NA		 6116
6117 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6118 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6119 X86_EFLAGS_RF);
6120
6bdf0662
NA		 6121 if (vcpu->arch.exception.nr == DB_VECTOR &&
6122 (vcpu->arch.dr7 & DR7_GD)) {
6123 vcpu->arch.dr7 &= ~DR7_GD;
6124 kvm_update_dr7(vcpu);
6125 }
6126
b59bb7bd
GN		 6127 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6128 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6129 vcpu->arch.exception.error_code,
6130 vcpu->arch.exception.reinject);
b6b8a145 6131 return 0;
b59bb7bd
GN		 6132 }
6133
95ba8273
GN		 6134 if (vcpu->arch.nmi_injected) {
6135 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6136 return 0;
95ba8273
GN		 6137 }
6138
6139 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6140 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6141 return 0;
6142 }
6143
6144 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6145 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6146 if (r != 0)
6147 return r;
95ba8273
GN		 6148 }
6149
6150 /* try to inject new event if pending */
c43203ca
PB		 6151 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6152 vcpu->arch.smi_pending = false;
ee2cd4b7 6153 enter_smm(vcpu);
c43203ca 6154 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6155 --vcpu->arch.nmi_pending;
6156 vcpu->arch.nmi_injected = true;
6157 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6158 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6159 /*
6160 * Because interrupts can be injected asynchronously, we are
6161 * calling check_nested_events again here to avoid a race condition.
6162 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6163 * proposal and current concerns. Perhaps we should be setting
6164 * KVM_REQ_EVENT only on certain events and not unconditionally?
6165 */
6166 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6167 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6168 if (r != 0)
6169 return r;
6170 }
95ba8273 6171 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6172 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6173 false);
6174 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6175 }
6176 }
ee2cd4b7 6177
b6b8a145 6178 return 0;
95ba8273
GN		 6179}
6180
7460fb4a
AK		 6181static void process_nmi(struct kvm_vcpu *vcpu)
6182{
6183 unsigned limit = 2;
6184
6185 /*
6186 * x86 is limited to one NMI running, and one NMI pending after it.
6187 * If an NMI is already in progress, limit further NMIs to just one.
6188 * Otherwise, allow two (and we'll inject the first one immediately).
6189 */
6190 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6191 limit = 1;
6192
6193 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6194 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6195 kvm_make_request(KVM_REQ_EVENT, vcpu);
6196}
6197
660a5d51
PB		 6198#define put_smstate(type, buf, offset, val) \
6199 *(type *)((buf) + (offset) - 0x7e00) = val
6200
ee2cd4b7 6201static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6202{
6203 u32 flags = 0;
6204 flags |= seg->g << 23;
6205 flags |= seg->db << 22;
6206 flags |= seg->l << 21;
6207 flags |= seg->avl << 20;
6208 flags |= seg->present << 15;
6209 flags |= seg->dpl << 13;
6210 flags |= seg->s << 12;
6211 flags |= seg->type << 8;
6212 return flags;
6213}
6214
ee2cd4b7 6215static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6216{
6217 struct kvm_segment seg;
6218 int offset;
6219
6220 kvm_get_segment(vcpu, &seg, n);
6221 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6222
6223 if (n < 3)
6224 offset = 0x7f84 + n * 12;
6225 else
6226 offset = 0x7f2c + (n - 3) * 12;
6227
6228 put_smstate(u32, buf, offset + 8, seg.base);
6229 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6230 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6231}
6232
efbb288a 6233#ifdef CONFIG_X86_64
ee2cd4b7 6234static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6235{
6236 struct kvm_segment seg;
6237 int offset;
6238 u16 flags;
6239
6240 kvm_get_segment(vcpu, &seg, n);
6241 offset = 0x7e00 + n * 16;
6242
ee2cd4b7 6243 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6244 put_smstate(u16, buf, offset, seg.selector);
6245 put_smstate(u16, buf, offset + 2, flags);
6246 put_smstate(u32, buf, offset + 4, seg.limit);
6247 put_smstate(u64, buf, offset + 8, seg.base);
6248}
efbb288a 6249#endif
660a5d51 6250
ee2cd4b7 6251static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6252{
6253 struct desc_ptr dt;
6254 struct kvm_segment seg;
6255 unsigned long val;
6256 int i;
6257
6258 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6259 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6260 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6261 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6262
6263 for (i = 0; i < 8; i++)
6264 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6265
6266 kvm_get_dr(vcpu, 6, &val);
6267 put_smstate(u32, buf, 0x7fcc, (u32)val);
6268 kvm_get_dr(vcpu, 7, &val);
6269 put_smstate(u32, buf, 0x7fc8, (u32)val);
6270
6271 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6272 put_smstate(u32, buf, 0x7fc4, seg.selector);
6273 put_smstate(u32, buf, 0x7f64, seg.base);
6274 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6275 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6276
6277 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6278 put_smstate(u32, buf, 0x7fc0, seg.selector);
6279 put_smstate(u32, buf, 0x7f80, seg.base);
6280 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6281 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6282
6283 kvm_x86_ops->get_gdt(vcpu, &dt);
6284 put_smstate(u32, buf, 0x7f74, dt.address);
6285 put_smstate(u32, buf, 0x7f70, dt.size);
6286
6287 kvm_x86_ops->get_idt(vcpu, &dt);
6288 put_smstate(u32, buf, 0x7f58, dt.address);
6289 put_smstate(u32, buf, 0x7f54, dt.size);
6290
6291 for (i = 0; i < 6; i++)
ee2cd4b7 6292 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6293
6294 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6295
6296 /* revision id */
6297 put_smstate(u32, buf, 0x7efc, 0x00020000);
6298 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6299}
6300
ee2cd4b7 6301static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6302{
6303#ifdef CONFIG_X86_64
6304 struct desc_ptr dt;
6305 struct kvm_segment seg;
6306 unsigned long val;
6307 int i;
6308
6309 for (i = 0; i < 16; i++)
6310 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6311
6312 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6313 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6314
6315 kvm_get_dr(vcpu, 6, &val);
6316 put_smstate(u64, buf, 0x7f68, val);
6317 kvm_get_dr(vcpu, 7, &val);
6318 put_smstate(u64, buf, 0x7f60, val);
6319
6320 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6321 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6322 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6323
6324 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6325
6326 /* revision id */
6327 put_smstate(u32, buf, 0x7efc, 0x00020064);
6328
6329 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6330
6331 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6332 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6333 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6334 put_smstate(u32, buf, 0x7e94, seg.limit);
6335 put_smstate(u64, buf, 0x7e98, seg.base);
6336
6337 kvm_x86_ops->get_idt(vcpu, &dt);
6338 put_smstate(u32, buf, 0x7e84, dt.size);
6339 put_smstate(u64, buf, 0x7e88, dt.address);
6340
6341 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6342 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6343 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6344 put_smstate(u32, buf, 0x7e74, seg.limit);
6345 put_smstate(u64, buf, 0x7e78, seg.base);
6346
6347 kvm_x86_ops->get_gdt(vcpu, &dt);
6348 put_smstate(u32, buf, 0x7e64, dt.size);
6349 put_smstate(u64, buf, 0x7e68, dt.address);
6350
6351 for (i = 0; i < 6; i++)
ee2cd4b7 6352 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6353#else
6354 WARN_ON_ONCE(1);
6355#endif
6356}
6357
ee2cd4b7 6358static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6359{
660a5d51 6360 struct kvm_segment cs, ds;
18c3626e 6361 struct desc_ptr dt;
660a5d51
PB		 6362 char buf[512];
6363 u32 cr0;
6364
660a5d51
PB		 6365 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6366 vcpu->arch.hflags |= HF_SMM_MASK;
6367 memset(buf, 0, 512);
6368 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6369 enter_smm_save_state_64(vcpu, buf);
660a5d51 6370 else
ee2cd4b7 6371 enter_smm_save_state_32(vcpu, buf);
660a5d51 6372
54bf36aa 6373 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6374
6375 if (kvm_x86_ops->get_nmi_mask(vcpu))
6376 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6377 else
6378 kvm_x86_ops->set_nmi_mask(vcpu, true);
6379
6380 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6381 kvm_rip_write(vcpu, 0x8000);
6382
6383 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6384 kvm_x86_ops->set_cr0(vcpu, cr0);
6385 vcpu->arch.cr0 = cr0;
6386
6387 kvm_x86_ops->set_cr4(vcpu, 0);
6388
18c3626e
PB		 6389 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6390 dt.address = dt.size = 0;
6391 kvm_x86_ops->set_idt(vcpu, &dt);
6392
660a5d51
PB		 6393 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6394
6395 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6396 cs.base = vcpu->arch.smbase;
6397
6398 ds.selector = 0;
6399 ds.base = 0;
6400
6401 cs.limit = ds.limit = 0xffffffff;
6402 cs.type = ds.type = 0x3;
6403 cs.dpl = ds.dpl = 0;
6404 cs.db = ds.db = 0;
6405 cs.s = ds.s = 1;
6406 cs.l = ds.l = 0;
6407 cs.g = ds.g = 1;
6408 cs.avl = ds.avl = 0;
6409 cs.present = ds.present = 1;
6410 cs.unusable = ds.unusable = 0;
6411 cs.padding = ds.padding = 0;
6412
6413 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6414 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6415 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6416 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6417 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6418 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6419
6420 if (guest_cpuid_has_longmode(vcpu))
6421 kvm_x86_ops->set_efer(vcpu, 0);
6422
6423 kvm_update_cpuid(vcpu);
6424 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6425}
6426
ee2cd4b7 6427static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6428{
6429 vcpu->arch.smi_pending = true;
6430 kvm_make_request(KVM_REQ_EVENT, vcpu);
6431}
6432
2860c4b1
PB		 6433void kvm_make_scan_ioapic_request(struct kvm *kvm)
6434{
6435 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6436}
6437
3d81bc7e 6438static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6439{
5c919412
AS		 6440 u64 eoi_exit_bitmap[4];
6441
3d81bc7e
YZ		 6442 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6443 return;
c7c9c56c 6444
6308630b 6445 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6446
b053b2ae 6447 if (irqchip_split(vcpu->kvm))
6308630b 6448 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6449 else {
d62caabb
AS		 6450 if (vcpu->arch.apicv_active)
6451 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6452 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6453 }
5c919412
AS		 6454 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6455 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6456 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6457}
6458
a70656b6
RK		 6459static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6460{
6461 ++vcpu->stat.tlb_flush;
6462 kvm_x86_ops->tlb_flush(vcpu);
6463}
6464
4256f43f
TC		 6465void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6466{
c24ae0dc
TC		 6467 struct page *page = NULL;
6468
35754c98 6469 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6470 return;
6471
4256f43f
TC		 6472 if (!kvm_x86_ops->set_apic_access_page_addr)
6473 return;
6474
c24ae0dc 6475 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6476 if (is_error_page(page))
6477 return;
c24ae0dc
TC		 6478 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6479
6480 /*
6481 * Do not pin apic access page in memory, the MMU notifier
6482 * will call us again if it is migrated or swapped out.
6483 */
6484 put_page(page);
4256f43f
TC		 6485}
6486EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6487
fe71557a
TC		 6488void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6489 unsigned long address)
6490{
c24ae0dc
TC		 6491 /*
6492 * The physical address of apic access page is stored in the VMCS.
6493 * Update it when it becomes invalid.
6494 */
6495 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6496 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6497}
6498
9357d939 6499/*
362c698f 6500 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6501 * exiting to the userspace. Otherwise, the value will be returned to the
6502 * userspace.
6503 */
851ba692 6504static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6505{
6506 int r;
62a193ed
MG		 6507 bool req_int_win =
6508 dm_request_for_irq_injection(vcpu) &&
6509 kvm_cpu_accept_dm_intr(vcpu);
6510
730dca42 6511 bool req_immediate_exit = false;
b6c7a5dc 6512
3e007509 6513 if (vcpu->requests) {
a8eeb04a 6514 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6515 kvm_mmu_unload(vcpu);
a8eeb04a 6516 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6517 __kvm_migrate_timers(vcpu);
d828199e
MT		 6518 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6519 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6520 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6521 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6522 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6523 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6524 if (unlikely(r))
6525 goto out;
6526 }
a8eeb04a 6527 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6528 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6529 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6530 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6531 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6532 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6533 r = 0;
6534 goto out;
6535 }
a8eeb04a 6536 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6537 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6538 r = 0;
6539 goto out;
6540 }
a8eeb04a 6541 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6542 vcpu->fpu_active = 0;
6543 kvm_x86_ops->fpu_deactivate(vcpu);
6544 }
af585b92
GN		 6545 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6546 /* Page is swapped out. Do synthetic halt */
6547 vcpu->arch.apf.halted = true;
6548 r = 1;
6549 goto out;
6550 }
c9aaa895
GC		 6551 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6552 record_steal_time(vcpu);
64d60670
PB		 6553 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6554 process_smi(vcpu);
7460fb4a
AK		 6555 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6556 process_nmi(vcpu);
f5132b01 6557 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6558 kvm_pmu_handle_event(vcpu);
f5132b01 6559 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6560 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6561 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6562 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6563 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6564 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6565 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6566 vcpu->run->eoi.vector =
6567 vcpu->arch.pending_ioapic_eoi;
6568 r = 0;
6569 goto out;
6570 }
6571 }
3d81bc7e
YZ		 6572 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6573 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6574 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6575 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6576 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6577 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6578 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6579 r = 0;
6580 goto out;
6581 }
e516cebb
AS		 6582 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6583 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6584 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6585 r = 0;
6586 goto out;
6587 }
db397571
AS		 6588 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6589 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6590 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6591 r = 0;
6592 goto out;
6593 }
f3b138c5
AS		 6594
6595 /*
6596 * KVM_REQ_HV_STIMER has to be processed after
6597 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6598 * depend on the guest clock being up-to-date
6599 */
1f4b34f8
AS		 6600 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6601 kvm_hv_process_stimers(vcpu);
2f52d58c 6602 }
b93463aa 6603
bf9f6ac8
FW		 6604 /*
6605 * KVM_REQ_EVENT is not set when posted interrupts are set by
6606 * VT-d hardware, so we have to update RVI unconditionally.
6607 */
6608 if (kvm_lapic_enabled(vcpu)) {
6609 /*
6610 * Update architecture specific hints for APIC
6611 * virtual interrupt delivery.
6612 */
d62caabb 6613 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6614 kvm_x86_ops->hwapic_irr_update(vcpu,
6615 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6616 }
b93463aa 6617
b463a6f7 6618 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6619 kvm_apic_accept_events(vcpu);
6620 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6621 r = 1;
6622 goto out;
6623 }
6624
b6b8a145
JK		 6625 if (inject_pending_event(vcpu, req_int_win) != 0)
6626 req_immediate_exit = true;
321c5658 6627 else {
c43203ca
PB		 6628 /* Enable NMI/IRQ window open exits if needed.
6629 *
6630 * SMIs have two cases: 1) they can be nested, and
6631 * then there is nothing to do here because RSM will
6632 * cause a vmexit anyway; 2) or the SMI can be pending
6633 * because inject_pending_event has completed the
6634 * injection of an IRQ or NMI from the previous vmexit,
6635 * and then we request an immediate exit to inject the SMI.
6636 */
6637 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6638 req_immediate_exit = true;
321c5658
YS		 6639 if (vcpu->arch.nmi_pending)
6640 kvm_x86_ops->enable_nmi_window(vcpu);
6641 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6642 kvm_x86_ops->enable_irq_window(vcpu);
6643 }
b463a6f7
AK		 6644
6645 if (kvm_lapic_enabled(vcpu)) {
6646 update_cr8_intercept(vcpu);
6647 kvm_lapic_sync_to_vapic(vcpu);
6648 }
6649 }
6650
d8368af8
AK		 6651 r = kvm_mmu_reload(vcpu);
6652 if (unlikely(r)) {
d905c069 6653 goto cancel_injection;
d8368af8
AK		 6654 }
6655
b6c7a5dc
HB		 6656 preempt_disable();
6657
6658 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6659 if (vcpu->fpu_active)
6660 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6661 vcpu->mode = IN_GUEST_MODE;
6662
01b71917
MT		 6663 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6664
0f127d12
LT		 6665 /*
6666 * We should set ->mode before check ->requests,
6667 * Please see the comment in kvm_make_all_cpus_request.
6668 * This also orders the write to mode from any reads
6669 * to the page tables done while the VCPU is running.
6670 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6671 */
01b71917 6672 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6673
d94e1dc9 6674 local_irq_disable();
32f88400 6675
6b7e2d09 6676 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6677 || need_resched() || signal_pending(current)) {
6b7e2d09 6678 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6679 smp_wmb();
6c142801
AK		 6680 local_irq_enable();
6681 preempt_enable();
01b71917 6682 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6683 r = 1;
d905c069 6684 goto cancel_injection;
6c142801
AK		 6685 }
6686
fc5b7f3b
DM		 6687 kvm_load_guest_xcr0(vcpu);
6688
c43203ca
PB		 6689 if (req_immediate_exit) {
6690 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6691 smp_send_reschedule(vcpu->cpu);
c43203ca 6692 }
d6185f20 6693
8b89fe1f
PB		 6694 trace_kvm_entry(vcpu->vcpu_id);
6695 wait_lapic_expire(vcpu);
6edaa530 6696 guest_enter_irqoff();
b6c7a5dc 6697
42dbaa5a 6698 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6699 set_debugreg(0, 7);
6700 set_debugreg(vcpu->arch.eff_db[0], 0);
6701 set_debugreg(vcpu->arch.eff_db[1], 1);
6702 set_debugreg(vcpu->arch.eff_db[2], 2);
6703 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6704 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6705 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6706 }
b6c7a5dc 6707
851ba692 6708 kvm_x86_ops->run(vcpu);
b6c7a5dc 6709
c77fb5fe
PB		 6710 /*
6711 * Do this here before restoring debug registers on the host. And
6712 * since we do this before handling the vmexit, a DR access vmexit
6713 * can (a) read the correct value of the debug registers, (b) set
6714 * KVM_DEBUGREG_WONT_EXIT again.
6715 */
6716 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6717 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6718 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6719 kvm_update_dr0123(vcpu);
6720 kvm_update_dr6(vcpu);
6721 kvm_update_dr7(vcpu);
6722 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6723 }
6724
24f1e32c
FW		 6725 /*
6726 * If the guest has used debug registers, at least dr7
6727 * will be disabled while returning to the host.
6728 * If we don't have active breakpoints in the host, we don't
6729 * care about the messed up debug address registers. But if
6730 * we have some of them active, restore the old state.
6731 */
59d8eb53 6732 if (hw_breakpoint_active())
24f1e32c 6733 hw_breakpoint_restore();
42dbaa5a 6734
4ba76538 6735 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6736
6b7e2d09 6737 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6738 smp_wmb();
a547c6db 6739
fc5b7f3b
DM		 6740 kvm_put_guest_xcr0(vcpu);
6741
a547c6db 6742 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6743
6744 ++vcpu->stat.exits;
6745
f2485b3e 6746 guest_exit_irqoff();
b6c7a5dc 6747
f2485b3e 6748 local_irq_enable();
b6c7a5dc
HB		 6749 preempt_enable();
6750
f656ce01 6751 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6752
b6c7a5dc
HB		 6753 /*
6754 * Profile KVM exit RIPs:
6755 */
6756 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6757 unsigned long rip = kvm_rip_read(vcpu);
6758 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6759 }
6760
cc578287
ZA		 6761 if (unlikely(vcpu->arch.tsc_always_catchup))
6762 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6763
5cfb1d5a
MT		 6764 if (vcpu->arch.apic_attention)
6765 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6766
851ba692 6767 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6768 return r;
6769
6770cancel_injection:
6771 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6772 if (unlikely(vcpu->arch.apic_attention))
6773 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6774out:
6775 return r;
6776}
b6c7a5dc 6777
362c698f
PB		 6778static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6779{
bf9f6ac8
FW		 6780 if (!kvm_arch_vcpu_runnable(vcpu) &&
6781 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6782 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6783 kvm_vcpu_block(vcpu);
6784 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6785
6786 if (kvm_x86_ops->post_block)
6787 kvm_x86_ops->post_block(vcpu);
6788
9c8fd1ba
PB		 6789 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6790 return 1;
6791 }
362c698f
PB		 6792
6793 kvm_apic_accept_events(vcpu);
6794 switch(vcpu->arch.mp_state) {
6795 case KVM_MP_STATE_HALTED:
6796 vcpu->arch.pv.pv_unhalted = false;
6797 vcpu->arch.mp_state =
6798 KVM_MP_STATE_RUNNABLE;
6799 case KVM_MP_STATE_RUNNABLE:
6800 vcpu->arch.apf.halted = false;
6801 break;
6802 case KVM_MP_STATE_INIT_RECEIVED:
6803 break;
6804 default:
6805 return -EINTR;
6806 break;
6807 }
6808 return 1;
6809}
09cec754 6810
5d9bc648
PB		 6811static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6812{
6813 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6814 !vcpu->arch.apf.halted);
6815}
6816
362c698f 6817static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6818{
6819 int r;
f656ce01 6820 struct kvm *kvm = vcpu->kvm;
d7690175 6821
f656ce01 6822 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6823
362c698f 6824 for (;;) {
58f800d5 6825 if (kvm_vcpu_running(vcpu)) {
851ba692 6826 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6827 } else {
362c698f 6828 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6829 }
6830
09cec754
GN		 6831 if (r <= 0)
6832 break;
6833
6834 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6835 if (kvm_cpu_has_pending_timer(vcpu))
6836 kvm_inject_pending_timer_irqs(vcpu);
6837
782d422b
MG		 6838 if (dm_request_for_irq_injection(vcpu) &&
6839 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6840 r = 0;
6841 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6842 ++vcpu->stat.request_irq_exits;
362c698f 6843 break;
09cec754 6844 }
af585b92
GN		 6845
6846 kvm_check_async_pf_completion(vcpu);
6847
09cec754
GN		 6848 if (signal_pending(current)) {
6849 r = -EINTR;
851ba692 6850 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6851 ++vcpu->stat.signal_exits;
362c698f 6852 break;
09cec754
GN		 6853 }
6854 if (need_resched()) {
f656ce01 6855 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6856 cond_resched();
f656ce01 6857 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6858 }
b6c7a5dc
HB		 6859 }
6860
f656ce01 6861 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6862
6863 return r;
6864}
6865
716d51ab
GN		 6866static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6867{
6868 int r;
6869 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6870 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6871 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6872 if (r != EMULATE_DONE)
6873 return 0;
6874 return 1;
6875}
6876
6877static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6878{
6879 BUG_ON(!vcpu->arch.pio.count);
6880
6881 return complete_emulated_io(vcpu);
6882}
6883
f78146b0
AK		 6884/*
6885 * Implements the following, as a state machine:
6886 *
6887 * read:
6888 * for each fragment
87da7e66
XG		 6889 * for each mmio piece in the fragment
6890 * write gpa, len
6891 * exit
6892 * copy data
f78146b0
AK		 6893 * execute insn
6894 *
6895 * write:
6896 * for each fragment
87da7e66
XG		 6897 * for each mmio piece in the fragment
6898 * write gpa, len
6899 * copy data
6900 * exit
f78146b0 6901 */
716d51ab 6902static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6903{
6904 struct kvm_run *run = vcpu->run;
f78146b0 6905 struct kvm_mmio_fragment *frag;
87da7e66 6906 unsigned len;
5287f194 6907
716d51ab 6908 BUG_ON(!vcpu->mmio_needed);
5287f194 6909
716d51ab 6910 /* Complete previous fragment */
87da7e66
XG		 6911 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6912 len = min(8u, frag->len);
716d51ab 6913 if (!vcpu->mmio_is_write)
87da7e66
XG		 6914 memcpy(frag->data, run->mmio.data, len);
6915
6916 if (frag->len <= 8) {
6917 /* Switch to the next fragment. */
6918 frag++;
6919 vcpu->mmio_cur_fragment++;
6920 } else {
6921 /* Go forward to the next mmio piece. */
6922 frag->data += len;
6923 frag->gpa += len;
6924 frag->len -= len;
6925 }
6926
a08d3b3b 6927 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6928 vcpu->mmio_needed = 0;
0912c977
PB		 6929
6930 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6931 if (vcpu->mmio_is_write)
716d51ab
GN		 6932 return 1;
6933 vcpu->mmio_read_completed = 1;
6934 return complete_emulated_io(vcpu);
6935 }
87da7e66 6936
716d51ab
GN		 6937 run->exit_reason = KVM_EXIT_MMIO;
6938 run->mmio.phys_addr = frag->gpa;
6939 if (vcpu->mmio_is_write)
87da7e66
XG		 6940 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6941 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6942 run->mmio.is_write = vcpu->mmio_is_write;
6943 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6944 return 0;
5287f194
AK		 6945}
6946
716d51ab 6947
b6c7a5dc
HB		 6948int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6949{
c5bedc68 6950 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6951 int r;
6952 sigset_t sigsaved;
6953
c4d72e2d 6954 fpu__activate_curr(fpu);
e5c30142 6955
ac9f6dc0
AK		 6956 if (vcpu->sigset_active)
6957 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6958
a4535290 6959 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6960 kvm_vcpu_block(vcpu);
66450a21 6961 kvm_apic_accept_events(vcpu);
d7690175 6962 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6963 r = -EAGAIN;
6964 goto out;
b6c7a5dc
HB		 6965 }
6966
b6c7a5dc 6967 /* re-sync apic's tpr */
35754c98 6968 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6969 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6970 r = -EINVAL;
6971 goto out;
6972 }
6973 }
b6c7a5dc 6974
716d51ab
GN		 6975 if (unlikely(vcpu->arch.complete_userspace_io)) {
6976 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6977 vcpu->arch.complete_userspace_io = NULL;
6978 r = cui(vcpu);
6979 if (r <= 0)
6980 goto out;
6981 } else
6982 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6983
362c698f 6984 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6985
6986out:
f1d86e46 6987 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6988 if (vcpu->sigset_active)
6989 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6990
b6c7a5dc
HB		 6991 return r;
6992}
6993
6994int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6995{
7ae441ea
GN		 6996 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6997 /*
6998 * We are here if userspace calls get_regs() in the middle of
6999 * instruction emulation. Registers state needs to be copied
4a969980 7000 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7001 * that usually, but some bad designed PV devices (vmware
7002 * backdoor interface) need this to work
7003 */
dd856efa 7004 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7005 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7006 }
5fdbf976
MT		 7007 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7008 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7009 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7010 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7011 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7012 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7013 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7014 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7015#ifdef CONFIG_X86_64
5fdbf976
MT		 7016 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7017 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7018 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7019 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7020 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7021 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7022 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7023 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7024#endif
7025
5fdbf976 7026 regs->rip = kvm_rip_read(vcpu);
91586a3b 7027 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7028
b6c7a5dc
HB		 7029 return 0;
7030}
7031
7032int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7033{
7ae441ea
GN		 7034 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7035 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7036
5fdbf976
MT		 7037 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7038 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7039 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7040 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7041 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7042 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7043 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7044 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7045#ifdef CONFIG_X86_64
5fdbf976
MT		 7046 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7047 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7048 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7049 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7050 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7051 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7052 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7053 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7054#endif
7055
5fdbf976 7056 kvm_rip_write(vcpu, regs->rip);
91586a3b 7057 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7058
b4f14abd
JK		 7059 vcpu->arch.exception.pending = false;
7060
3842d135
AK		 7061 kvm_make_request(KVM_REQ_EVENT, vcpu);
7062
b6c7a5dc
HB		 7063 return 0;
7064}
7065
b6c7a5dc
HB		 7066void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7067{
7068 struct kvm_segment cs;
7069
3e6e0aab 7070 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7071 *db = cs.db;
7072 *l = cs.l;
7073}
7074EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7075
7076int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7077 struct kvm_sregs *sregs)
7078{
89a27f4d 7079 struct desc_ptr dt;
b6c7a5dc 7080
3e6e0aab
GT		 7081 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7082 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7083 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7084 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7085 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7086 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7087
3e6e0aab
GT		 7088 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7089 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7090
7091 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7092 sregs->idt.limit = dt.size;
7093 sregs->idt.base = dt.address;
b6c7a5dc 7094 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7095 sregs->gdt.limit = dt.size;
7096 sregs->gdt.base = dt.address;
b6c7a5dc 7097
4d4ec087 7098 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7099 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7100 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7101 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7102 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7103 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7104 sregs->apic_base = kvm_get_apic_base(vcpu);
7105
923c61bb 7106 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7107
36752c9b 7108 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7109 set_bit(vcpu->arch.interrupt.nr,
7110 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7111
b6c7a5dc
HB		 7112 return 0;
7113}
7114
62d9f0db
MT		 7115int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7116 struct kvm_mp_state *mp_state)
7117{
66450a21 7118 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7119 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7120 vcpu->arch.pv.pv_unhalted)
7121 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7122 else
7123 mp_state->mp_state = vcpu->arch.mp_state;
7124
62d9f0db
MT		 7125 return 0;
7126}
7127
7128int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7129 struct kvm_mp_state *mp_state)
7130{
bce87cce 7131 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7132 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7133 return -EINVAL;
7134
7135 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7136 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7137 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7138 } else
7139 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7140 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7141 return 0;
7142}
7143
7f3d35fd
KW		 7144int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7145 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7146{
9d74191a 7147 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7148 int ret;
e01c2426 7149
8ec4722d 7150 init_emulate_ctxt(vcpu);
c697518a 7151
7f3d35fd 7152 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7153 has_error_code, error_code);
c697518a 7154
c697518a 7155 if (ret)
19d04437 7156 return EMULATE_FAIL;
37817f29 7157
9d74191a
TY		 7158 kvm_rip_write(vcpu, ctxt->eip);
7159 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7160 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7161 return EMULATE_DONE;
37817f29
IE		 7162}
7163EXPORT_SYMBOL_GPL(kvm_task_switch);
7164
b6c7a5dc
HB		 7165int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7166 struct kvm_sregs *sregs)
7167{
58cb628d 7168 struct msr_data apic_base_msr;
b6c7a5dc 7169 int mmu_reset_needed = 0;
63f42e02 7170 int pending_vec, max_bits, idx;
89a27f4d 7171 struct desc_ptr dt;
b6c7a5dc 7172
6d1068b3
PM		 7173 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7174 return -EINVAL;
7175
89a27f4d
GN		 7176 dt.size = sregs->idt.limit;
7177 dt.address = sregs->idt.base;
b6c7a5dc 7178 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7179 dt.size = sregs->gdt.limit;
7180 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7181 kvm_x86_ops->set_gdt(vcpu, &dt);
7182
ad312c7c 7183 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7184 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7185 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7186 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7187
2d3ad1f4 7188 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7189
f6801dff 7190 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7191 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7192 apic_base_msr.data = sregs->apic_base;
7193 apic_base_msr.host_initiated = true;
7194 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7195
4d4ec087 7196 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7197 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7198 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7199
fc78f519 7200 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7201 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7202 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7203 kvm_update_cpuid(vcpu);
63f42e02
XG		 7204
7205 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7206 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7207 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7208 mmu_reset_needed = 1;
7209 }
63f42e02 7210 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7211
7212 if (mmu_reset_needed)
7213 kvm_mmu_reset_context(vcpu);
7214
a50abc3b 7215 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7216 pending_vec = find_first_bit(
7217 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7218 if (pending_vec < max_bits) {
66fd3f7f 7219 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7220 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7221 }
7222
3e6e0aab
GT		 7223 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7224 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7225 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7226 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7227 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7228 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7229
3e6e0aab
GT		 7230 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7231 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7232
5f0269f5
ME		 7233 update_cr8_intercept(vcpu);
7234
9c3e4aab 7235 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7236 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7237 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7238 !is_protmode(vcpu))
9c3e4aab
MT		 7239 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7240
3842d135
AK		 7241 kvm_make_request(KVM_REQ_EVENT, vcpu);
7242
b6c7a5dc
HB		 7243 return 0;
7244}
7245
d0bfb940
JK		 7246int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7247 struct kvm_guest_debug *dbg)
b6c7a5dc 7248{
355be0b9 7249 unsigned long rflags;
ae675ef0 7250 int i, r;
b6c7a5dc 7251
4f926bf2
JK		 7252 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7253 r = -EBUSY;
7254 if (vcpu->arch.exception.pending)
2122ff5e 7255 goto out;
4f926bf2
JK		 7256 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7257 kvm_queue_exception(vcpu, DB_VECTOR);
7258 else
7259 kvm_queue_exception(vcpu, BP_VECTOR);
7260 }
7261
91586a3b
JK		 7262 /*
7263 * Read rflags as long as potentially injected trace flags are still
7264 * filtered out.
7265 */
7266 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7267
7268 vcpu->guest_debug = dbg->control;
7269 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7270 vcpu->guest_debug = 0;
7271
7272 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7273 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7274 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7275 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7276 } else {
7277 for (i = 0; i < KVM_NR_DB_REGS; i++)
7278 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7279 }
c8639010 7280 kvm_update_dr7(vcpu);
ae675ef0 7281
f92653ee
JK		 7282 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7283 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7284 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7285
91586a3b
JK		 7286 /*
7287 * Trigger an rflags update that will inject or remove the trace
7288 * flags.
7289 */
7290 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7291
a96036b8 7292 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7293
4f926bf2 7294 r = 0;
d0bfb940 7295
2122ff5e 7296out:
b6c7a5dc
HB		 7297
7298 return r;
7299}
7300
8b006791
ZX		 7301/*
7302 * Translate a guest virtual address to a guest physical address.
7303 */
7304int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7305 struct kvm_translation *tr)
7306{
7307 unsigned long vaddr = tr->linear_address;
7308 gpa_t gpa;
f656ce01 7309 int idx;
8b006791 7310
f656ce01 7311 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7312 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7313 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7314 tr->physical_address = gpa;
7315 tr->valid = gpa != UNMAPPED_GVA;
7316 tr->writeable = 1;
7317 tr->usermode = 0;
8b006791
ZX		 7318
7319 return 0;
7320}
7321
d0752060
HB		 7322int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7323{
c47ada30 7324 struct fxregs_state *fxsave =
7366ed77 7325 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7326
d0752060
HB		 7327 memcpy(fpu->fpr, fxsave->st_space, 128);
7328 fpu->fcw = fxsave->cwd;
7329 fpu->fsw = fxsave->swd;
7330 fpu->ftwx = fxsave->twd;
7331 fpu->last_opcode = fxsave->fop;
7332 fpu->last_ip = fxsave->rip;
7333 fpu->last_dp = fxsave->rdp;
7334 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7335
d0752060
HB		 7336 return 0;
7337}
7338
7339int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7340{
c47ada30 7341 struct fxregs_state *fxsave =
7366ed77 7342 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7343
d0752060
HB		 7344 memcpy(fxsave->st_space, fpu->fpr, 128);
7345 fxsave->cwd = fpu->fcw;
7346 fxsave->swd = fpu->fsw;
7347 fxsave->twd = fpu->ftwx;
7348 fxsave->fop = fpu->last_opcode;
7349 fxsave->rip = fpu->last_ip;
7350 fxsave->rdp = fpu->last_dp;
7351 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7352
d0752060
HB		 7353 return 0;
7354}
7355
0ee6a517 7356static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7357{
bf935b0b 7358 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7359 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7360 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7361 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7362
2acf923e
DC		 7363 /*
7364 * Ensure guest xcr0 is valid for loading
7365 */
d91cab78 7366 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7367
ad312c7c 7368 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7369}
d0752060
HB		 7370
7371void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7372{
2608d7a1 7373 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7374 return;
7375
2acf923e
DC		 7376 /*
7377 * Restore all possible states in the guest,
7378 * and assume host would use all available bits.
7379 * Guest xcr0 would be loaded later.
7380 */
d0752060 7381 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7382 __kernel_fpu_begin();
003e2e8b 7383 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7384 trace_kvm_fpu(1);
d0752060 7385}
d0752060
HB		 7386
7387void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7388{
653f52c3
RR		 7389 if (!vcpu->guest_fpu_loaded) {
7390 vcpu->fpu_counter = 0;
d0752060 7391 return;
653f52c3 7392 }
d0752060
HB		 7393
7394 vcpu->guest_fpu_loaded = 0;
4f836347 7395 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7396 __kernel_fpu_end();
f096ed85 7397 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7398 /*
7399 * If using eager FPU mode, or if the guest is a frequent user
7400 * of the FPU, just leave the FPU active for next time.
7401 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7402 * the FPU in bursts will revert to loading it on demand.
7403 */
5a5fbdc0 7404 if (!use_eager_fpu()) {
653f52c3
RR		 7405 if (++vcpu->fpu_counter < 5)
7406 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7407 }
0c04851c 7408 trace_kvm_fpu(0);
d0752060 7409}
e9b11c17
ZX		 7410
7411void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7412{
12f9a48f 7413 kvmclock_reset(vcpu);
7f1ea208 7414
f5f48ee1 7415 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7416 kvm_x86_ops->vcpu_free(vcpu);
7417}
7418
7419struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7420 unsigned int id)
7421{
c447e76b
LL		 7422 struct kvm_vcpu *vcpu;
7423
6755bae8
ZA		 7424 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7425 printk_once(KERN_WARNING
7426 "kvm: SMP vm created on host with unstable TSC; "
7427 "guest TSC will not be reliable\n");
c447e76b
LL		 7428
7429 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7430
c447e76b 7431 return vcpu;
26e5215f 7432}
e9b11c17 7433
26e5215f
AK		 7434int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7435{
7436 int r;
e9b11c17 7437
19efffa2 7438 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7439 r = vcpu_load(vcpu);
7440 if (r)
7441 return r;
d28bc9dd 7442 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7443 kvm_mmu_setup(vcpu);
e9b11c17 7444 vcpu_put(vcpu);
26e5215f 7445 return r;
e9b11c17
ZX		 7446}
7447
31928aa5 7448void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7449{
8fe8ab46 7450 struct msr_data msr;
332967a3 7451 struct kvm *kvm = vcpu->kvm;
42897d86 7452
31928aa5
DD		 7453 if (vcpu_load(vcpu))
7454 return;
8fe8ab46
WA		 7455 msr.data = 0x0;
7456 msr.index = MSR_IA32_TSC;
7457 msr.host_initiated = true;
7458 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7459 vcpu_put(vcpu);
7460
630994b3
MT		 7461 if (!kvmclock_periodic_sync)
7462 return;
7463
332967a3
AJ		 7464 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7465 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7466}
7467
d40ccc62 7468void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7469{
9fc77441 7470 int r;
344d9588
GN		 7471 vcpu->arch.apf.msr_val = 0;
7472
9fc77441
MT		 7473 r = vcpu_load(vcpu);
7474 BUG_ON(r);
e9b11c17
ZX		 7475 kvm_mmu_unload(vcpu);
7476 vcpu_put(vcpu);
7477
7478 kvm_x86_ops->vcpu_free(vcpu);
7479}
7480
d28bc9dd 7481void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7482{
e69fab5d
PB		 7483 vcpu->arch.hflags = 0;
7484
c43203ca 7485 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7486 atomic_set(&vcpu->arch.nmi_queued, 0);
7487 vcpu->arch.nmi_pending = 0;
448fa4a9 7488 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7489 kvm_clear_interrupt_queue(vcpu);
7490 kvm_clear_exception_queue(vcpu);
448fa4a9 7491
42dbaa5a 7492 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7493 kvm_update_dr0123(vcpu);
6f43ed01 7494 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7495 kvm_update_dr6(vcpu);
42dbaa5a 7496 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7497 kvm_update_dr7(vcpu);
42dbaa5a 7498
1119022c
NA		 7499 vcpu->arch.cr2 = 0;
7500
3842d135 7501 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7502 vcpu->arch.apf.msr_val = 0;
c9aaa895 7503 vcpu->arch.st.msr_val = 0;
3842d135 7504
12f9a48f
GC		 7505 kvmclock_reset(vcpu);
7506
af585b92
GN		 7507 kvm_clear_async_pf_completion_queue(vcpu);
7508 kvm_async_pf_hash_reset(vcpu);
7509 vcpu->arch.apf.halted = false;
3842d135 7510
64d60670 7511 if (!init_event) {
d28bc9dd 7512 kvm_pmu_reset(vcpu);
64d60670
PB		 7513 vcpu->arch.smbase = 0x30000;
7514 }
f5132b01 7515
66f7b72e
JS		 7516 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7517 vcpu->arch.regs_avail = ~0;
7518 vcpu->arch.regs_dirty = ~0;
7519
d28bc9dd 7520 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7521}
7522
2b4a273b 7523void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7524{
7525 struct kvm_segment cs;
7526
7527 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7528 cs.selector = vector << 8;
7529 cs.base = vector << 12;
7530 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7531 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7532}
7533
13a34e06 7534int kvm_arch_hardware_enable(void)
e9b11c17 7535{
ca84d1a2
ZA		 7536 struct kvm *kvm;
7537 struct kvm_vcpu *vcpu;
7538 int i;
0dd6a6ed
ZA		 7539 int ret;
7540 u64 local_tsc;
7541 u64 max_tsc = 0;
7542 bool stable, backwards_tsc = false;
18863bdd
AK		 7543
7544 kvm_shared_msr_cpu_online();
13a34e06 7545 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7546 if (ret != 0)
7547 return ret;
7548
4ea1636b 7549 local_tsc = rdtsc();
0dd6a6ed
ZA		 7550 stable = !check_tsc_unstable();
7551 list_for_each_entry(kvm, &vm_list, vm_list) {
7552 kvm_for_each_vcpu(i, vcpu, kvm) {
7553 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7554 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7555 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7556 backwards_tsc = true;
7557 if (vcpu->arch.last_host_tsc > max_tsc)
7558 max_tsc = vcpu->arch.last_host_tsc;
7559 }
7560 }
7561 }
7562
7563 /*
7564 * Sometimes, even reliable TSCs go backwards. This happens on
7565 * platforms that reset TSC during suspend or hibernate actions, but
7566 * maintain synchronization. We must compensate. Fortunately, we can
7567 * detect that condition here, which happens early in CPU bringup,
7568 * before any KVM threads can be running. Unfortunately, we can't
7569 * bring the TSCs fully up to date with real time, as we aren't yet far
7570 * enough into CPU bringup that we know how much real time has actually
108b249c 7571 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7572 * variables that haven't been updated yet.
7573 *
7574 * So we simply find the maximum observed TSC above, then record the
7575 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7576 * the adjustment will be applied. Note that we accumulate
7577 * adjustments, in case multiple suspend cycles happen before some VCPU
7578 * gets a chance to run again. In the event that no KVM threads get a
7579 * chance to run, we will miss the entire elapsed period, as we'll have
7580 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7581 * loose cycle time. This isn't too big a deal, since the loss will be
7582 * uniform across all VCPUs (not to mention the scenario is extremely
7583 * unlikely). It is possible that a second hibernate recovery happens
7584 * much faster than a first, causing the observed TSC here to be
7585 * smaller; this would require additional padding adjustment, which is
7586 * why we set last_host_tsc to the local tsc observed here.
7587 *
7588 * N.B. - this code below runs only on platforms with reliable TSC,
7589 * as that is the only way backwards_tsc is set above. Also note
7590 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7591 * have the same delta_cyc adjustment applied if backwards_tsc
7592 * is detected. Note further, this adjustment is only done once,
7593 * as we reset last_host_tsc on all VCPUs to stop this from being
7594 * called multiple times (one for each physical CPU bringup).
7595 *
4a969980 7596 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7597 * will be compensated by the logic in vcpu_load, which sets the TSC to
7598 * catchup mode. This will catchup all VCPUs to real time, but cannot
7599 * guarantee that they stay in perfect synchronization.
7600 */
7601 if (backwards_tsc) {
7602 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7603 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7604 list_for_each_entry(kvm, &vm_list, vm_list) {
7605 kvm_for_each_vcpu(i, vcpu, kvm) {
7606 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7607 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7608 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7609 }
7610
7611 /*
7612 * We have to disable TSC offset matching.. if you were
7613 * booting a VM while issuing an S4 host suspend....
7614 * you may have some problem. Solving this issue is
7615 * left as an exercise to the reader.
7616 */
7617 kvm->arch.last_tsc_nsec = 0;
7618 kvm->arch.last_tsc_write = 0;
7619 }
7620
7621 }
7622 return 0;
e9b11c17
ZX		 7623}
7624
13a34e06 7625void kvm_arch_hardware_disable(void)
e9b11c17 7626{
13a34e06
RK		 7627 kvm_x86_ops->hardware_disable();
7628 drop_user_return_notifiers();
e9b11c17
ZX		 7629}
7630
7631int kvm_arch_hardware_setup(void)
7632{
9e9c3fe4
NA		 7633 int r;
7634
7635 r = kvm_x86_ops->hardware_setup();
7636 if (r != 0)
7637 return r;
7638
35181e86
HZ		 7639 if (kvm_has_tsc_control) {
7640 /*
7641 * Make sure the user can only configure tsc_khz values that
7642 * fit into a signed integer.
7643 * A min value is not calculated needed because it will always
7644 * be 1 on all machines.
7645 */
7646 u64 max = min(0x7fffffffULL,
7647 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7648 kvm_max_guest_tsc_khz = max;
7649
ad721883 7650 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7651 }
ad721883 7652
9e9c3fe4
NA		 7653 kvm_init_msr_list();
7654 return 0;
e9b11c17
ZX		 7655}
7656
7657void kvm_arch_hardware_unsetup(void)
7658{
7659 kvm_x86_ops->hardware_unsetup();
7660}
7661
7662void kvm_arch_check_processor_compat(void *rtn)
7663{
7664 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7665}
7666
7667bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7668{
7669 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7670}
7671EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7672
7673bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7674{
7675 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7676}
7677
54e9818f 7678struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7679EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7680
e9b11c17
ZX		 7681int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7682{
7683 struct page *page;
7684 struct kvm *kvm;
7685 int r;
7686
7687 BUG_ON(vcpu->kvm == NULL);
7688 kvm = vcpu->kvm;
7689
d62caabb 7690 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7691 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7692 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7693 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7694 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7695 else
a4535290 7696 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7697
7698 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7699 if (!page) {
7700 r = -ENOMEM;
7701 goto fail;
7702 }
ad312c7c 7703 vcpu->arch.pio_data = page_address(page);
e9b11c17 7704
cc578287 7705 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7706
e9b11c17
ZX		 7707 r = kvm_mmu_create(vcpu);
7708 if (r < 0)
7709 goto fail_free_pio_data;
7710
7711 if (irqchip_in_kernel(kvm)) {
7712 r = kvm_create_lapic(vcpu);
7713 if (r < 0)
7714 goto fail_mmu_destroy;
54e9818f
GN		 7715 } else
7716 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7717
890ca9ae
HY		 7718 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7719 GFP_KERNEL);
7720 if (!vcpu->arch.mce_banks) {
7721 r = -ENOMEM;
443c39bc 7722 goto fail_free_lapic;
890ca9ae
HY		 7723 }
7724 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7725
f1797359
WY		 7726 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7727 r = -ENOMEM;
f5f48ee1 7728 goto fail_free_mce_banks;
f1797359 7729 }
f5f48ee1 7730
0ee6a517 7731 fx_init(vcpu);
66f7b72e 7732
ba904635 7733 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7734 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7735
7736 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7737 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7738
5a4f55cd
EK		 7739 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7740
74545705
RK		 7741 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7742
af585b92 7743 kvm_async_pf_hash_reset(vcpu);
f5132b01 7744 kvm_pmu_init(vcpu);
af585b92 7745
1c1a9ce9
SR		 7746 vcpu->arch.pending_external_vector = -1;
7747
5c919412
AS		 7748 kvm_hv_vcpu_init(vcpu);
7749
e9b11c17 7750 return 0;
0ee6a517 7751
f5f48ee1
SY		 7752fail_free_mce_banks:
7753 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7754fail_free_lapic:
7755 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7756fail_mmu_destroy:
7757 kvm_mmu_destroy(vcpu);
7758fail_free_pio_data:
ad312c7c 7759 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7760fail:
7761 return r;
7762}
7763
7764void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7765{
f656ce01
MT		 7766 int idx;
7767
1f4b34f8 7768 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7769 kvm_pmu_destroy(vcpu);
36cb93fd 7770 kfree(vcpu->arch.mce_banks);
e9b11c17 7771 kvm_free_lapic(vcpu);
f656ce01 7772 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7773 kvm_mmu_destroy(vcpu);
f656ce01 7774 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7775 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7776 if (!lapic_in_kernel(vcpu))
54e9818f 7777 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7778}
d19a9cd2 7779
e790d9ef
RK		 7780void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7781{
ae97a3b8 7782 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7783}
7784
e08b9637 7785int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7786{
e08b9637
CO		 7787 if (type)
7788 return -EINVAL;
7789
6ef768fa 7790 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7791 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7792 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7793 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7794 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7795
5550af4d
SY		 7796 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7797 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7798 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7799 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7800 &kvm->arch.irq_sources_bitmap);
5550af4d 7801
038f8c11 7802 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7803 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7804 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7805
108b249c 7806 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 7807 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7808
7e44e449 7809 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7810 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7811
0eb05bf2 7812 kvm_page_track_init(kvm);
13d268ca 7813 kvm_mmu_init_vm(kvm);
0eb05bf2 7814
03543133
SS		 7815 if (kvm_x86_ops->vm_init)
7816 return kvm_x86_ops->vm_init(kvm);
7817
d89f5eff 7818 return 0;
d19a9cd2
ZX		 7819}
7820
7821static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7822{
9fc77441
MT		 7823 int r;
7824 r = vcpu_load(vcpu);
7825 BUG_ON(r);
d19a9cd2
ZX		 7826 kvm_mmu_unload(vcpu);
7827 vcpu_put(vcpu);
7828}
7829
7830static void kvm_free_vcpus(struct kvm *kvm)
7831{
7832 unsigned int i;
988a2cae 7833 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7834
7835 /*
7836 * Unpin any mmu pages first.
7837 */
af585b92
GN		 7838 kvm_for_each_vcpu(i, vcpu, kvm) {
7839 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7840 kvm_unload_vcpu_mmu(vcpu);
af585b92 7841 }
988a2cae
GN		 7842 kvm_for_each_vcpu(i, vcpu, kvm)
7843 kvm_arch_vcpu_free(vcpu);
7844
7845 mutex_lock(&kvm->lock);
7846 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7847 kvm->vcpus[i] = NULL;
d19a9cd2 7848
988a2cae
GN		 7849 atomic_set(&kvm->online_vcpus, 0);
7850 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7851}
7852
ad8ba2cd
SY		 7853void kvm_arch_sync_events(struct kvm *kvm)
7854{
332967a3 7855 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7856 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7857 kvm_free_all_assigned_devices(kvm);
aea924f6 7858 kvm_free_pit(kvm);
ad8ba2cd
SY		 7859}
7860
1d8007bd 7861int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7862{
7863 int i, r;
25188b99 7864 unsigned long hva;
f0d648bd
PB		 7865 struct kvm_memslots *slots = kvm_memslots(kvm);
7866 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7867
7868 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7869 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7870 return -EINVAL;
9da0e4d5 7871
f0d648bd
PB		 7872 slot = id_to_memslot(slots, id);
7873 if (size) {
b21629da 7874 if (slot->npages)
f0d648bd
PB		 7875 return -EEXIST;
7876
7877 /*
7878 * MAP_SHARED to prevent internal slot pages from being moved
7879 * by fork()/COW.
7880 */
7881 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7882 MAP_SHARED | MAP_ANONYMOUS, 0);
7883 if (IS_ERR((void *)hva))
7884 return PTR_ERR((void *)hva);
7885 } else {
7886 if (!slot->npages)
7887 return 0;
7888
7889 hva = 0;
7890 }
7891
7892 old = *slot;
9da0e4d5 7893 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7894 struct kvm_userspace_memory_region m;
9da0e4d5 7895
1d8007bd
PB		 7896 m.slot = id | (i << 16);
7897 m.flags = 0;
7898 m.guest_phys_addr = gpa;
f0d648bd 7899 m.userspace_addr = hva;
1d8007bd 7900 m.memory_size = size;
9da0e4d5
PB		 7901 r = __kvm_set_memory_region(kvm, &m);
7902 if (r < 0)
7903 return r;
7904 }
7905
f0d648bd
PB		 7906 if (!size) {
7907 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7908 WARN_ON(r < 0);
7909 }
7910
9da0e4d5
PB		 7911 return 0;
7912}
7913EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7914
1d8007bd 7915int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7916{
7917 int r;
7918
7919 mutex_lock(&kvm->slots_lock);
1d8007bd 7920 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7921 mutex_unlock(&kvm->slots_lock);
7922
7923 return r;
7924}
7925EXPORT_SYMBOL_GPL(x86_set_memory_region);
7926
d19a9cd2
ZX		 7927void kvm_arch_destroy_vm(struct kvm *kvm)
7928{
27469d29
AH		 7929 if (current->mm == kvm->mm) {
7930 /*
7931 * Free memory regions allocated on behalf of userspace,
7932 * unless the the memory map has changed due to process exit
7933 * or fd copying.
7934 */
1d8007bd
PB		 7935 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7936 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7937 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7938 }
03543133
SS		 7939 if (kvm_x86_ops->vm_destroy)
7940 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7941 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7942 kfree(kvm->arch.vpic);
7943 kfree(kvm->arch.vioapic);
d19a9cd2 7944 kvm_free_vcpus(kvm);
af1bae54 7945 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7946 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7947}
0de10343 7948
5587027c 7949void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7950 struct kvm_memory_slot *dont)
7951{
7952 int i;
7953
d89cc617
TY		 7954 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7955 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7956 kvfree(free->arch.rmap[i]);
d89cc617 7957 free->arch.rmap[i] = NULL;
77d11309 7958 }
d89cc617
TY		 7959 if (i == 0)
7960 continue;
7961
7962 if (!dont || free->arch.lpage_info[i - 1] !=
7963 dont->arch.lpage_info[i - 1]) {
548ef284 7964 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7965 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7966 }
7967 }
21ebbeda
XG		 7968
7969 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7970}
7971
5587027c
AK		 7972int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7973 unsigned long npages)
db3fe4eb
TY		 7974{
7975 int i;
7976
d89cc617 7977 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7978 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7979 unsigned long ugfn;
7980 int lpages;
d89cc617 7981 int level = i + 1;
db3fe4eb
TY		 7982
7983 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7984 slot->base_gfn, level) + 1;
7985
d89cc617
TY		 7986 slot->arch.rmap[i] =
7987 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7988 if (!slot->arch.rmap[i])
77d11309 7989 goto out_free;
d89cc617
TY		 7990 if (i == 0)
7991 continue;
77d11309 7992
92f94f1e
XG		 7993 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7994 if (!linfo)
db3fe4eb
TY		 7995 goto out_free;
7996
92f94f1e
XG		 7997 slot->arch.lpage_info[i - 1] = linfo;
7998
db3fe4eb 7999 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8000 linfo[0].disallow_lpage = 1;
db3fe4eb 8001 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8002 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8003 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8004 /*
8005 * If the gfn and userspace address are not aligned wrt each
8006 * other, or if explicitly asked to, disable large page
8007 * support for this slot
8008 */
8009 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8010 !kvm_largepages_enabled()) {
8011 unsigned long j;
8012
8013 for (j = 0; j < lpages; ++j)
92f94f1e 8014 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8015 }
8016 }
8017
21ebbeda
XG		 8018 if (kvm_page_track_create_memslot(slot, npages))
8019 goto out_free;
8020
db3fe4eb
TY		 8021 return 0;
8022
8023out_free:
d89cc617 8024 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8025 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8026 slot->arch.rmap[i] = NULL;
8027 if (i == 0)
8028 continue;
8029
548ef284 8030 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8031 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8032 }
8033 return -ENOMEM;
8034}
8035
15f46015 8036void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8037{
e6dff7d1
TY		 8038 /*
8039 * memslots->generation has been incremented.
8040 * mmio generation may have reached its maximum value.
8041 */
54bf36aa 8042 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8043}
8044
f7784b8e
MT		 8045int kvm_arch_prepare_memory_region(struct kvm *kvm,
8046 struct kvm_memory_slot *memslot,
09170a49 8047 const struct kvm_userspace_memory_region *mem,
7b6195a9 8048 enum kvm_mr_change change)
0de10343 8049{
f7784b8e
MT		 8050 return 0;
8051}
8052
88178fd4
KH		 8053static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8054 struct kvm_memory_slot *new)
8055{
8056 /* Still write protect RO slot */
8057 if (new->flags & KVM_MEM_READONLY) {
8058 kvm_mmu_slot_remove_write_access(kvm, new);
8059 return;
8060 }
8061
8062 /*
8063 * Call kvm_x86_ops dirty logging hooks when they are valid.
8064 *
8065 * kvm_x86_ops->slot_disable_log_dirty is called when:
8066 *
8067 * - KVM_MR_CREATE with dirty logging is disabled
8068 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8069 *
8070 * The reason is, in case of PML, we need to set D-bit for any slots
8071 * with dirty logging disabled in order to eliminate unnecessary GPA
8072 * logging in PML buffer (and potential PML buffer full VMEXT). This
8073 * guarantees leaving PML enabled during guest's lifetime won't have
8074 * any additonal overhead from PML when guest is running with dirty
8075 * logging disabled for memory slots.
8076 *
8077 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8078 * to dirty logging mode.
8079 *
8080 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8081 *
8082 * In case of write protect:
8083 *
8084 * Write protect all pages for dirty logging.
8085 *
8086 * All the sptes including the large sptes which point to this
8087 * slot are set to readonly. We can not create any new large
8088 * spte on this slot until the end of the logging.
8089 *
8090 * See the comments in fast_page_fault().
8091 */
8092 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8093 if (kvm_x86_ops->slot_enable_log_dirty)
8094 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8095 else
8096 kvm_mmu_slot_remove_write_access(kvm, new);
8097 } else {
8098 if (kvm_x86_ops->slot_disable_log_dirty)
8099 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8100 }
8101}
8102
f7784b8e 8103void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8104 const struct kvm_userspace_memory_region *mem,
8482644a 8105 const struct kvm_memory_slot *old,
f36f3f28 8106 const struct kvm_memory_slot *new,
8482644a 8107 enum kvm_mr_change change)
f7784b8e 8108{
8482644a 8109 int nr_mmu_pages = 0;
f7784b8e 8110
48c0e4e9
XG		 8111 if (!kvm->arch.n_requested_mmu_pages)
8112 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8113
48c0e4e9 8114 if (nr_mmu_pages)
0de10343 8115 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8116
3ea3b7fa
WL		 8117 /*
8118 * Dirty logging tracks sptes in 4k granularity, meaning that large
8119 * sptes have to be split. If live migration is successful, the guest
8120 * in the source machine will be destroyed and large sptes will be
8121 * created in the destination. However, if the guest continues to run
8122 * in the source machine (for example if live migration fails), small
8123 * sptes will remain around and cause bad performance.
8124 *
8125 * Scan sptes if dirty logging has been stopped, dropping those
8126 * which can be collapsed into a single large-page spte. Later
8127 * page faults will create the large-page sptes.
8128 */
8129 if ((change != KVM_MR_DELETE) &&
8130 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8131 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8132 kvm_mmu_zap_collapsible_sptes(kvm, new);
8133
c972f3b1 8134 /*
88178fd4 8135 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8136 *
88178fd4
KH		 8137 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8138 * been zapped so no dirty logging staff is needed for old slot. For
8139 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8140 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8141 *
8142 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8143 */
88178fd4 8144 if (change != KVM_MR_DELETE)
f36f3f28 8145 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8146}
1d737c8a 8147
2df72e9b 8148void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8149{
6ca18b69 8150 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8151}
8152
2df72e9b
MT		 8153void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8154 struct kvm_memory_slot *slot)
8155{
6ca18b69 8156 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8157}
8158
5d9bc648
PB		 8159static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8160{
8161 if (!list_empty_careful(&vcpu->async_pf.done))
8162 return true;
8163
8164 if (kvm_apic_has_events(vcpu))
8165 return true;
8166
8167 if (vcpu->arch.pv.pv_unhalted)
8168 return true;
8169
8170 if (atomic_read(&vcpu->arch.nmi_queued))
8171 return true;
8172
73917739
PB		 8173 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8174 return true;
8175
5d9bc648
PB		 8176 if (kvm_arch_interrupt_allowed(vcpu) &&
8177 kvm_cpu_has_interrupt(vcpu))
8178 return true;
8179
1f4b34f8
AS		 8180 if (kvm_hv_has_stimer_pending(vcpu))
8181 return true;
8182
5d9bc648
PB		 8183 return false;
8184}
8185
1d737c8a
ZX		 8186int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8187{
b6b8a145
JK		 8188 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8189 kvm_x86_ops->check_nested_events(vcpu, false);
8190
5d9bc648 8191 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8192}
5736199a 8193
b6d33834 8194int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8195{
b6d33834 8196 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8197}
78646121
GN		 8198
8199int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8200{
8201 return kvm_x86_ops->interrupt_allowed(vcpu);
8202}
229456fc 8203
82b32774 8204unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8205{
82b32774
NA		 8206 if (is_64_bit_mode(vcpu))
8207 return kvm_rip_read(vcpu);
8208 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8209 kvm_rip_read(vcpu));
8210}
8211EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8212
82b32774
NA		 8213bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8214{
8215 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8216}
8217EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8218
94fe45da
JK		 8219unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8220{
8221 unsigned long rflags;
8222
8223 rflags = kvm_x86_ops->get_rflags(vcpu);
8224 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8225 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8226 return rflags;
8227}
8228EXPORT_SYMBOL_GPL(kvm_get_rflags);
8229
6addfc42 8230static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8231{
8232 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8233 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8234 rflags |= X86_EFLAGS_TF;
94fe45da 8235 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8236}
8237
8238void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8239{
8240 __kvm_set_rflags(vcpu, rflags);
3842d135 8241 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8242}
8243EXPORT_SYMBOL_GPL(kvm_set_rflags);
8244
56028d08
GN		 8245void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8246{
8247 int r;
8248
fb67e14f 8249 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8250 work->wakeup_all)
56028d08
GN		 8251 return;
8252
8253 r = kvm_mmu_reload(vcpu);
8254 if (unlikely(r))
8255 return;
8256
fb67e14f
XG		 8257 if (!vcpu->arch.mmu.direct_map &&
8258 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8259 return;
8260
56028d08
GN		 8261 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8262}
8263
af585b92
GN		 8264static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8265{
8266 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8267}
8268
8269static inline u32 kvm_async_pf_next_probe(u32 key)
8270{
8271 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8272}
8273
8274static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8275{
8276 u32 key = kvm_async_pf_hash_fn(gfn);
8277
8278 while (vcpu->arch.apf.gfns[key] != ~0)
8279 key = kvm_async_pf_next_probe(key);
8280
8281 vcpu->arch.apf.gfns[key] = gfn;
8282}
8283
8284static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8285{
8286 int i;
8287 u32 key = kvm_async_pf_hash_fn(gfn);
8288
8289 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8290 (vcpu->arch.apf.gfns[key] != gfn &&
8291 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8292 key = kvm_async_pf_next_probe(key);
8293
8294 return key;
8295}
8296
8297bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8298{
8299 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8300}
8301
8302static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8303{
8304 u32 i, j, k;
8305
8306 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8307 while (true) {
8308 vcpu->arch.apf.gfns[i] = ~0;
8309 do {
8310 j = kvm_async_pf_next_probe(j);
8311 if (vcpu->arch.apf.gfns[j] == ~0)
8312 return;
8313 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8314 /*
8315 * k lies cyclically in ]i,j]
8316 * | i.k.j |
8317 * |....j i.k.| or |.k..j i...|
8318 */
8319 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8320 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8321 i = j;
8322 }
8323}
8324
7c90705b
GN		 8325static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8326{
8327
8328 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8329 sizeof(val));
8330}
8331
af585b92
GN		 8332void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8333 struct kvm_async_pf *work)
8334{
6389ee94
AK		 8335 struct x86_exception fault;
8336
7c90705b 8337 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8338 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8339
8340 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8341 (vcpu->arch.apf.send_user_only &&
8342 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8343 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8344 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8345 fault.vector = PF_VECTOR;
8346 fault.error_code_valid = true;
8347 fault.error_code = 0;
8348 fault.nested_page_fault = false;
8349 fault.address = work->arch.token;
8350 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8351 }
af585b92
GN		 8352}
8353
8354void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8355 struct kvm_async_pf *work)
8356{
6389ee94
AK		 8357 struct x86_exception fault;
8358
7c90705b 8359 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8360 if (work->wakeup_all)
7c90705b
GN		 8361 work->arch.token = ~0; /* broadcast wakeup */
8362 else
8363 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8364
8365 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8366 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8367 fault.vector = PF_VECTOR;
8368 fault.error_code_valid = true;
8369 fault.error_code = 0;
8370 fault.nested_page_fault = false;
8371 fault.address = work->arch.token;
8372 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8373 }
e6d53e3b 8374 vcpu->arch.apf.halted = false;
a4fa1635 8375 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8376}
8377
8378bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8379{
8380 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8381 return true;
8382 else
8383 return !kvm_event_needs_reinjection(vcpu) &&
8384 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8385}
8386
5544eb9b
PB		 8387void kvm_arch_start_assignment(struct kvm *kvm)
8388{
8389 atomic_inc(&kvm->arch.assigned_device_count);
8390}
8391EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8392
8393void kvm_arch_end_assignment(struct kvm *kvm)
8394{
8395 atomic_dec(&kvm->arch.assigned_device_count);
8396}
8397EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8398
8399bool kvm_arch_has_assigned_device(struct kvm *kvm)
8400{
8401 return atomic_read(&kvm->arch.assigned_device_count);
8402}
8403EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8404
e0f0bbc5
AW		 8405void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8406{
8407 atomic_inc(&kvm->arch.noncoherent_dma_count);
8408}
8409EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8410
8411void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8412{
8413 atomic_dec(&kvm->arch.noncoherent_dma_count);
8414}
8415EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8416
8417bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8418{
8419 return atomic_read(&kvm->arch.noncoherent_dma_count);
8420}
8421EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8422
14717e20
AW		 8423bool kvm_arch_has_irq_bypass(void)
8424{
8425 return kvm_x86_ops->update_pi_irte != NULL;
8426}
8427
87276880
FW		 8428int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8429 struct irq_bypass_producer *prod)
8430{
8431 struct kvm_kernel_irqfd *irqfd =
8432 container_of(cons, struct kvm_kernel_irqfd, consumer);
8433
14717e20 8434 irqfd->producer = prod;
87276880 8435
14717e20
AW		 8436 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8437 prod->irq, irqfd->gsi, 1);
87276880
FW		 8438}
8439
8440void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8441 struct irq_bypass_producer *prod)
8442{
8443 int ret;
8444 struct kvm_kernel_irqfd *irqfd =
8445 container_of(cons, struct kvm_kernel_irqfd, consumer);
8446
87276880
FW		 8447 WARN_ON(irqfd->producer != prod);
8448 irqfd->producer = NULL;
8449
8450 /*
8451 * When producer of consumer is unregistered, we change back to
8452 * remapped mode, so we can re-use the current implementation
bb3541f1 8453 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8454 * int this case doesn't want to receive the interrupts.
8455 */
8456 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8457 if (ret)
8458 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8459 " fails: %d\n", irqfd->consumer.token, ret);
8460}
8461
8462int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8463 uint32_t guest_irq, bool set)
8464{
8465 if (!kvm_x86_ops->update_pi_irte)
8466 return -EINVAL;
8467
8468 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8469}
8470
52004014
FW		 8471bool kvm_vector_hashing_enabled(void)
8472{
8473 return vector_hashing;
8474}
8475EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8476
229456fc 8477EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8478EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8479EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8480EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8481EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8482EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8483EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8484EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8485EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8486EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8487EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8488EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8489EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8490EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8491EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8492EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8493EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8494EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8495EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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