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KVM: x86: count actual tlb flushes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
13a34e06 249static void drop_user_return_notifiers(void)
3548bab5 250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
ef54bcfe 411static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 417
418 return fault->nested_page_fault;
d4f8cf66
JR		 419}
420
3419ffc8
SY		 421void kvm_inject_nmi(struct kvm_vcpu *vcpu)
422{
7460fb4a
AK		 423 atomic_inc(&vcpu->arch.nmi_queued);
424 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 425}
426EXPORT_SYMBOL_GPL(kvm_inject_nmi);
427
298101da
AK		 428void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
429{
ce7ddec4 430 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 431}
432EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
433
ce7ddec4
JR		 434void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
435{
436 kvm_multiple_exception(vcpu, nr, true, error_code, true);
437}
438EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
439
0a79b009
AK		 440/*
441 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
442 * a #GP and return false.
443 */
444bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 445{
0a79b009
AK		 446 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
447 return true;
448 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
449 return false;
298101da 450}
0a79b009 451EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 452
ec92fe44
JR		 453/*
454 * This function will be used to read from the physical memory of the currently
455 * running guest. The difference to kvm_read_guest_page is that this function
456 * can read from guest physical or from the guest's guest physical memory.
457 */
458int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
459 gfn_t ngfn, void *data, int offset, int len,
460 u32 access)
461{
54987b7a 462 struct x86_exception exception;
ec92fe44
JR		 463 gfn_t real_gfn;
464 gpa_t ngpa;
465
466 ngpa = gfn_to_gpa(ngfn);
54987b7a 467 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 468 if (real_gfn == UNMAPPED_GVA)
469 return -EFAULT;
470
471 real_gfn = gpa_to_gfn(real_gfn);
472
473 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
474}
475EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
476
3d06b8bf
JR		 477int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
478 void *data, int offset, int len, u32 access)
479{
480 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
481 data, offset, len, access);
482}
483
a03490ed
CO		 484/*
485 * Load the pae pdptrs. Return true is they are all valid.
486 */
ff03a073 487int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 488{
489 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
490 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
491 int i;
492 int ret;
ff03a073 493 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 494
ff03a073
JR		 495 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
496 offset * sizeof(u64), sizeof(pdpte),
497 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 498 if (ret < 0) {
499 ret = 0;
500 goto out;
501 }
502 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 503 if (is_present_gpte(pdpte[i]) &&
20c466b5 504 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 505 ret = 0;
506 goto out;
507 }
508 }
509 ret = 1;
510
ff03a073 511 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 512 __set_bit(VCPU_EXREG_PDPTR,
513 (unsigned long *)&vcpu->arch.regs_avail);
514 __set_bit(VCPU_EXREG_PDPTR,
515 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 516out:
a03490ed
CO		 517
518 return ret;
519}
cc4b6871 520EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 521
d835dfec
AK		 522static bool pdptrs_changed(struct kvm_vcpu *vcpu)
523{
ff03a073 524 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 525 bool changed = true;
3d06b8bf
JR		 526 int offset;
527 gfn_t gfn;
d835dfec
AK		 528 int r;
529
530 if (is_long_mode(vcpu) || !is_pae(vcpu))
531 return false;
532
6de4f3ad
AK		 533 if (!test_bit(VCPU_EXREG_PDPTR,
534 (unsigned long *)&vcpu->arch.regs_avail))
535 return true;
536
9f8fe504
AK		 537 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
538 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 539 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
540 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 541 if (r < 0)
542 goto out;
ff03a073 543 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 544out:
d835dfec
AK		 545
546 return changed;
547}
548
49a9b07e 549int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 550{
aad82703
SY		 551 unsigned long old_cr0 = kvm_read_cr0(vcpu);
552 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
553 X86_CR0_CD | X86_CR0_NW;
554
f9a48e6a
AK		 555 cr0 |= X86_CR0_ET;
556
ab344828 557#ifdef CONFIG_X86_64
0f12244f
GN		 558 if (cr0 & 0xffffffff00000000UL)
559 return 1;
ab344828
GN		 560#endif
561
562 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
565 return 1;
a03490ed 566
0f12244f
GN		 567 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
568 return 1;
a03490ed
CO		 569
570 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
571#ifdef CONFIG_X86_64
f6801dff 572 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 573 int cs_db, cs_l;
574
0f12244f
GN		 575 if (!is_pae(vcpu))
576 return 1;
a03490ed 577 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 578 if (cs_l)
579 return 1;
a03490ed
CO		 580 } else
581#endif
ff03a073 582 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 583 kvm_read_cr3(vcpu)))
0f12244f 584 return 1;
a03490ed
CO		 585 }
586
ad756a16
MJ		 587 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
588 return 1;
589
a03490ed 590 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 591
d170c419 592 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 593 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 594 kvm_async_pf_hash_reset(vcpu);
595 }
e5f3f027 596
aad82703
SY		 597 if ((cr0 ^ old_cr0) & update_bits)
598 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 599 return 0;
600}
2d3ad1f4 601EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 602
2d3ad1f4 603void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 604{
49a9b07e 605 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 608
42bdf991
MT		 609static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
610{
611 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
612 !vcpu->guest_xcr0_loaded) {
613 /* kvm_set_xcr() also depends on this */
614 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
615 vcpu->guest_xcr0_loaded = 1;
616 }
617}
618
619static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
620{
621 if (vcpu->guest_xcr0_loaded) {
622 if (vcpu->arch.xcr0 != host_xcr0)
623 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
624 vcpu->guest_xcr0_loaded = 0;
625 }
626}
627
2acf923e
DC		 628int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
629{
56c103ec
LJ		 630 u64 xcr0 = xcr;
631 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 632 u64 valid_bits;
2acf923e
DC		 633
634 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
635 if (index != XCR_XFEATURE_ENABLED_MASK)
636 return 1;
2acf923e
DC		 637 if (!(xcr0 & XSTATE_FP))
638 return 1;
639 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
640 return 1;
46c34cb0
PB		 641
642 /*
643 * Do not allow the guest to set bits that we do not support
644 * saving. However, xcr0 bit 0 is always set, even if the
645 * emulated CPU does not support XSAVE (see fx_init).
646 */
647 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
648 if (xcr0 & ~valid_bits)
2acf923e 649 return 1;
46c34cb0 650
390bd528
LJ		 651 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
652 return 1;
653
42bdf991 654 kvm_put_guest_xcr0(vcpu);
2acf923e 655 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 656
657 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
658 kvm_update_cpuid(vcpu);
2acf923e
DC		 659 return 0;
660}
661
662int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
663{
764bcbc5
Z		 664 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
665 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 666 kvm_inject_gp(vcpu, 0);
667 return 1;
668 }
669 return 0;
670}
671EXPORT_SYMBOL_GPL(kvm_set_xcr);
672
a83b29c6 673int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 674{
fc78f519 675 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 676 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
677 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 678 if (cr4 & CR4_RESERVED_BITS)
679 return 1;
a03490ed 680
2acf923e
DC		 681 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
682 return 1;
683
c68b734f
YW		 684 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
685 return 1;
686
97ec8c06
FW		 687 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
688 return 1;
689
afcbf13f 690 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 691 return 1;
692
a03490ed 693 if (is_long_mode(vcpu)) {
0f12244f
GN		 694 if (!(cr4 & X86_CR4_PAE))
695 return 1;
a2edf57f
AK		 696 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
697 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 698 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
699 kvm_read_cr3(vcpu)))
0f12244f
GN		 700 return 1;
701
ad756a16
MJ		 702 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
703 if (!guest_cpuid_has_pcid(vcpu))
704 return 1;
705
706 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
707 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
708 return 1;
709 }
710
5e1746d6 711 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 712 return 1;
a03490ed 713
ad756a16
MJ		 714 if (((cr4 ^ old_cr4) & pdptr_bits) ||
715 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 716 kvm_mmu_reset_context(vcpu);
0f12244f 717
97ec8c06
FW		 718 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
719 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
720
2acf923e 721 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 722 kvm_update_cpuid(vcpu);
2acf923e 723
0f12244f
GN		 724 return 0;
725}
2d3ad1f4 726EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 727
2390218b 728int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 729{
9f8fe504 730 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 731 kvm_mmu_sync_roots(vcpu);
d835dfec 732 kvm_mmu_flush_tlb(vcpu);
0f12244f 733 return 0;
d835dfec
AK		 734 }
735
a03490ed 736 if (is_long_mode(vcpu)) {
d9f89b88
JK		 737 if (cr3 & CR3_L_MODE_RESERVED_BITS)
738 return 1;
739 } else if (is_pae(vcpu) && is_paging(vcpu) &&
740 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 741 return 1;
a03490ed 742
0f12244f 743 vcpu->arch.cr3 = cr3;
aff48baa 744 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 745 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 746 return 0;
747}
2d3ad1f4 748EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 749
eea1cff9 750int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 751{
0f12244f
GN		 752 if (cr8 & CR8_RESERVED_BITS)
753 return 1;
a03490ed
CO		 754 if (irqchip_in_kernel(vcpu->kvm))
755 kvm_lapic_set_tpr(vcpu, cr8);
756 else
ad312c7c 757 vcpu->arch.cr8 = cr8;
0f12244f
GN		 758 return 0;
759}
2d3ad1f4 760EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 761
2d3ad1f4 762unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 763{
764 if (irqchip_in_kernel(vcpu->kvm))
765 return kvm_lapic_get_cr8(vcpu);
766 else
ad312c7c 767 return vcpu->arch.cr8;
a03490ed 768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 770
73aaf249
JK		 771static void kvm_update_dr6(struct kvm_vcpu *vcpu)
772{
773 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
774 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
775}
776
c8639010
JK		 777static void kvm_update_dr7(struct kvm_vcpu *vcpu)
778{
779 unsigned long dr7;
780
781 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
782 dr7 = vcpu->arch.guest_debug_dr7;
783 else
784 dr7 = vcpu->arch.dr7;
785 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 786 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
787 if (dr7 & DR7_BP_EN_MASK)
788 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 789}
790
6f43ed01
NA		 791static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
792{
793 u64 fixed = DR6_FIXED_1;
794
795 if (!guest_cpuid_has_rtm(vcpu))
796 fixed |= DR6_RTM;
797 return fixed;
798}
799
338dbc97 800static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 801{
802 switch (dr) {
803 case 0 ... 3:
804 vcpu->arch.db[dr] = val;
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 vcpu->arch.eff_db[dr] = val;
807 break;
808 case 4:
338dbc97
GN		 809 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
810 return 1; /* #UD */
020df079
GN		 811 /* fall through */
812 case 6:
338dbc97
GN		 813 if (val & 0xffffffff00000000ULL)
814 return -1; /* #GP */
6f43ed01 815 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 816 kvm_update_dr6(vcpu);
020df079
GN		 817 break;
818 case 5:
338dbc97
GN		 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
820 return 1; /* #UD */
020df079
GN		 821 /* fall through */
822 default: /* 7 */
338dbc97
GN		 823 if (val & 0xffffffff00000000ULL)
824 return -1; /* #GP */
020df079 825 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 826 kvm_update_dr7(vcpu);
020df079
GN		 827 break;
828 }
829
830 return 0;
831}
338dbc97
GN		 832
833int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
834{
835 int res;
836
837 res = __kvm_set_dr(vcpu, dr, val);
838 if (res > 0)
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 else if (res < 0)
841 kvm_inject_gp(vcpu, 0);
842
843 return res;
844}
020df079
GN		 845EXPORT_SYMBOL_GPL(kvm_set_dr);
846
338dbc97 847static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 *val = vcpu->arch.db[dr];
852 break;
853 case 4:
338dbc97 854 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 855 return 1;
020df079
GN		 856 /* fall through */
857 case 6:
73aaf249
JK		 858 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
859 *val = vcpu->arch.dr6;
860 else
861 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
338dbc97 864 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 865 return 1;
020df079
GN		 866 /* fall through */
867 default: /* 7 */
868 *val = vcpu->arch.dr7;
869 break;
870 }
871
872 return 0;
873}
338dbc97
GN		 874
875int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
876{
877 if (_kvm_get_dr(vcpu, dr, val)) {
878 kvm_queue_exception(vcpu, UD_VECTOR);
879 return 1;
880 }
881 return 0;
882}
020df079
GN		 883EXPORT_SYMBOL_GPL(kvm_get_dr);
884
022cd0e8
AK		 885bool kvm_rdpmc(struct kvm_vcpu *vcpu)
886{
887 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
888 u64 data;
889 int err;
890
891 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
892 if (err)
893 return err;
894 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
895 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
896 return err;
897}
898EXPORT_SYMBOL_GPL(kvm_rdpmc);
899
043405e1
CO		 900/*
901 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
902 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
903 *
904 * This list is modified at module load time to reflect the
e3267cbb
GC		 905 * capabilities of the host cpu. This capabilities test skips MSRs that are
906 * kvm-specific. Those are put in the beginning of the list.
043405e1 907 */
e3267cbb 908
e984097b 909#define KVM_SAVE_MSRS_BEGIN 12
043405e1 910static u32 msrs_to_save[] = {
e3267cbb 911 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 912 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 913 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 914 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 915 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 916 MSR_KVM_PV_EOI_EN,
043405e1 917 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 918 MSR_STAR,
043405e1
CO		 919#ifdef CONFIG_X86_64
920 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
921#endif
b3897a49 922 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 923 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 924};
925
926static unsigned num_msrs_to_save;
927
f1d24831 928static const u32 emulated_msrs[] = {
ba904635 929 MSR_IA32_TSC_ADJUST,
a3e06bbe 930 MSR_IA32_TSCDEADLINE,
043405e1 931 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 932 MSR_IA32_MCG_STATUS,
933 MSR_IA32_MCG_CTL,
043405e1
CO		 934};
935
384bb783 936bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 937{
b69e8cae 938 if (efer & efer_reserved_bits)
384bb783 939 return false;
15c4a640 940
1b2fd70c
AG		 941 if (efer & EFER_FFXSR) {
942 struct kvm_cpuid_entry2 *feat;
943
944 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 945 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 946 return false;
1b2fd70c
AG		 947 }
948
d8017474
AG		 949 if (efer & EFER_SVME) {
950 struct kvm_cpuid_entry2 *feat;
951
952 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 953 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 954 return false;
d8017474
AG		 955 }
956
384bb783
JK		 957 return true;
958}
959EXPORT_SYMBOL_GPL(kvm_valid_efer);
960
961static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
962{
963 u64 old_efer = vcpu->arch.efer;
964
965 if (!kvm_valid_efer(vcpu, efer))
966 return 1;
967
968 if (is_paging(vcpu)
969 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
970 return 1;
971
15c4a640 972 efer &= ~EFER_LMA;
f6801dff 973 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 974
a3d204e2
SY		 975 kvm_x86_ops->set_efer(vcpu, efer);
976
aad82703
SY		 977 /* Update reserved bits */
978 if ((efer ^ old_efer) & EFER_NX)
979 kvm_mmu_reset_context(vcpu);
980
b69e8cae 981 return 0;
15c4a640
CO		 982}
983
f2b4b7dd
JR		 984void kvm_enable_efer_bits(u64 mask)
985{
986 efer_reserved_bits &= ~mask;
987}
988EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
989
990
15c4a640
CO		 991/*
992 * Writes msr value into into the appropriate "register".
993 * Returns 0 on success, non-0 otherwise.
994 * Assumes vcpu_load() was already called.
995 */
8fe8ab46 996int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 997{
8fe8ab46 998 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 999}
1000
313a3dc7
CO		 1001/*
1002 * Adapt set_msr() to msr_io()'s calling convention
1003 */
1004static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1005{
8fe8ab46
WA		 1006 struct msr_data msr;
1007
1008 msr.data = *data;
1009 msr.index = index;
1010 msr.host_initiated = true;
1011 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1012}
1013
16e8d74d
MT		 1014#ifdef CONFIG_X86_64
1015struct pvclock_gtod_data {
1016 seqcount_t seq;
1017
1018 struct { /* extract of a clocksource struct */
1019 int vclock_mode;
1020 cycle_t cycle_last;
1021 cycle_t mask;
1022 u32 mult;
1023 u32 shift;
1024 } clock;
1025
cbcf2dd3
TG		 1026 u64 boot_ns;
1027 u64 nsec_base;
16e8d74d
MT		 1028};
1029
1030static struct pvclock_gtod_data pvclock_gtod_data;
1031
1032static void update_pvclock_gtod(struct timekeeper *tk)
1033{
1034 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1035 u64 boot_ns;
1036
d28ede83 1037 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1038
1039 write_seqcount_begin(&vdata->seq);
1040
1041 /* copy pvclock gtod data */
d28ede83
TG		 1042 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1043 vdata->clock.cycle_last = tk->tkr.cycle_last;
1044 vdata->clock.mask = tk->tkr.mask;
1045 vdata->clock.mult = tk->tkr.mult;
1046 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1047
cbcf2dd3 1048 vdata->boot_ns = boot_ns;
d28ede83 1049 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1050
1051 write_seqcount_end(&vdata->seq);
1052}
1053#endif
1054
1055
18068523
GOC		 1056static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1057{
9ed3c444
AK		 1058 int version;
1059 int r;
50d0a0f9 1060 struct pvclock_wall_clock wc;
923de3cf 1061 struct timespec boot;
18068523
GOC		 1062
1063 if (!wall_clock)
1064 return;
1065
9ed3c444
AK		 1066 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1067 if (r)
1068 return;
1069
1070 if (version & 1)
1071 ++version; /* first time write, random junk */
1072
1073 ++version;
18068523 1074
18068523
GOC		 1075 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1076
50d0a0f9
GH		 1077 /*
1078 * The guest calculates current wall clock time by adding
34c238a1 1079 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1080 * wall clock specified here. guest system time equals host
1081 * system time for us, thus we must fill in host boot time here.
1082 */
923de3cf 1083 getboottime(&boot);
50d0a0f9 1084
4b648665
BR		 1085 if (kvm->arch.kvmclock_offset) {
1086 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1087 boot = timespec_sub(boot, ts);
1088 }
50d0a0f9
GH		 1089 wc.sec = boot.tv_sec;
1090 wc.nsec = boot.tv_nsec;
1091 wc.version = version;
18068523
GOC		 1092
1093 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1094
1095 version++;
1096 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1097}
1098
50d0a0f9
GH		 1099static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1100{
1101 uint32_t quotient, remainder;
1102
1103 /* Don't try to replace with do_div(), this one calculates
1104 * "(dividend << 32) / divisor" */
1105 __asm__ ( "divl %4"
1106 : "=a" (quotient), "=d" (remainder)
1107 : "0" (0), "1" (dividend), "r" (divisor) );
1108 return quotient;
1109}
1110
5f4e3f88
ZA		 1111static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1112 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1113{
5f4e3f88 1114 uint64_t scaled64;
50d0a0f9
GH		 1115 int32_t shift = 0;
1116 uint64_t tps64;
1117 uint32_t tps32;
1118
5f4e3f88
ZA		 1119 tps64 = base_khz * 1000LL;
1120 scaled64 = scaled_khz * 1000LL;
50933623 1121 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1122 tps64 >>= 1;
1123 shift--;
1124 }
1125
1126 tps32 = (uint32_t)tps64;
50933623
JK		 1127 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1128 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1129 scaled64 >>= 1;
1130 else
1131 tps32 <<= 1;
50d0a0f9
GH		 1132 shift++;
1133 }
1134
5f4e3f88
ZA		 1135 *pshift = shift;
1136 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1137
5f4e3f88
ZA		 1138 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1139 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1140}
1141
759379dd
ZA		 1142static inline u64 get_kernel_ns(void)
1143{
bb0b5812 1144 return ktime_get_boot_ns();
50d0a0f9
GH		 1145}
1146
d828199e 1147#ifdef CONFIG_X86_64
16e8d74d 1148static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1149#endif
16e8d74d 1150
c8076604 1151static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1152unsigned long max_tsc_khz;
c8076604 1153
cc578287 1154static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1155{
cc578287
ZA		 1156 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1158}
1159
cc578287 1160static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1161{
cc578287
ZA		 1162 u64 v = (u64)khz * (1000000 + ppm);
1163 do_div(v, 1000000);
1164 return v;
1e993611
JR		 1165}
1166
cc578287 1167static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1168{
cc578287
ZA		 1169 u32 thresh_lo, thresh_hi;
1170 int use_scaling = 0;
217fc9cf 1171
03ba32ca
MT		 1172 /* tsc_khz can be zero if TSC calibration fails */
1173 if (this_tsc_khz == 0)
1174 return;
1175
c285545f
ZA		 1176 /* Compute a scale to convert nanoseconds in TSC cycles */
1177 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1178 &vcpu->arch.virtual_tsc_shift,
1179 &vcpu->arch.virtual_tsc_mult);
1180 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1181
1182 /*
1183 * Compute the variation in TSC rate which is acceptable
1184 * within the range of tolerance and decide if the
1185 * rate being applied is within that bounds of the hardware
1186 * rate. If so, no scaling or compensation need be done.
1187 */
1188 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1192 use_scaling = 1;
1193 }
1194 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1195}
1196
1197static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1198{
e26101b1 1199 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1200 vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
e26101b1 1202 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1203 return tsc;
1204}
1205
b48aa97e
MT		 1206void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1207{
1208#ifdef CONFIG_X86_64
1209 bool vcpus_matched;
1210 bool do_request = false;
1211 struct kvm_arch *ka = &vcpu->kvm->arch;
1212 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1213
1214 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215 atomic_read(&vcpu->kvm->online_vcpus));
1216
1217 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218 if (!ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (!vcpus_matched && ka->use_master_clock)
1222 do_request = 1;
1223
1224 if (do_request)
1225 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1226
1227 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228 atomic_read(&vcpu->kvm->online_vcpus),
1229 ka->use_master_clock, gtod->clock.vclock_mode);
1230#endif
1231}
1232
ba904635
WA		 1233static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1234{
1235 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1237}
1238
8fe8ab46 1239void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1240{
1241 struct kvm *kvm = vcpu->kvm;
f38e098f 1242 u64 offset, ns, elapsed;
99e3e30a 1243 unsigned long flags;
02626b6a 1244 s64 usdiff;
b48aa97e 1245 bool matched;
0d3da0d2 1246 bool already_matched;
8fe8ab46 1247 u64 data = msr->data;
99e3e30a 1248
038f8c11 1249 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1250 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1251 ns = get_kernel_ns();
f38e098f 1252 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1253
03ba32ca 1254 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1255 int faulted = 0;
1256
03ba32ca
MT		 1257 /* n.b - signed multiplication and division required */
1258 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1259#ifdef CONFIG_X86_64
03ba32ca 1260 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1261#else
03ba32ca 1262 /* do_div() only does unsigned */
8915aa27
MT		 1263 asm("1: idivl %[divisor]\n"
1264 "2: xor %%edx, %%edx\n"
1265 " movl $0, %[faulted]\n"
1266 "3:\n"
1267 ".section .fixup,\"ax\"\n"
1268 "4: movl $1, %[faulted]\n"
1269 " jmp 3b\n"
1270 ".previous\n"
1271
1272 _ASM_EXTABLE(1b, 4b)
1273
1274 : "=A"(usdiff), [faulted] "=r" (faulted)
1275 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1276
5d3cb0f6 1277#endif
03ba32ca
MT		 1278 do_div(elapsed, 1000);
1279 usdiff -= elapsed;
1280 if (usdiff < 0)
1281 usdiff = -usdiff;
8915aa27
MT		 1282
1283 /* idivl overflow => difference is larger than USEC_PER_SEC */
1284 if (faulted)
1285 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1286 } else
1287 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1288
1289 /*
5d3cb0f6
ZA		 1290 * Special case: TSC write with a small delta (1 second) of virtual
1291 * cycle time against real time is interpreted as an attempt to
1292 * synchronize the CPU.
1293 *
1294 * For a reliable TSC, we can match TSC offsets, and for an unstable
1295 * TSC, we add elapsed time in this computation. We could let the
1296 * compensation code attempt to catch up if we fall behind, but
1297 * it's better to try to match offsets from the beginning.
1298 */
02626b6a 1299 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1300 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1301 if (!check_tsc_unstable()) {
e26101b1 1302 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1303 pr_debug("kvm: matched tsc offset for %llu\n", data);
1304 } else {
857e4099 1305 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1306 data += delta;
1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1309 }
b48aa97e 1310 matched = true;
0d3da0d2 1311 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1312 } else {
1313 /*
1314 * We split periods of matched TSC writes into generations.
1315 * For each generation, we track the original measured
1316 * nanosecond time, offset, and write, so if TSCs are in
1317 * sync, we can match exact offset, and if not, we can match
4a969980 1318 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1319 *
1320 * These values are tracked in kvm->arch.cur_xxx variables.
1321 */
1322 kvm->arch.cur_tsc_generation++;
1323 kvm->arch.cur_tsc_nsec = ns;
1324 kvm->arch.cur_tsc_write = data;
1325 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1326 matched = false;
0d3da0d2 1327 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1328 kvm->arch.cur_tsc_generation, data);
f38e098f 1329 }
e26101b1
ZA		 1330
1331 /*
1332 * We also track th most recent recorded KHZ, write and time to
1333 * allow the matching interval to be extended at each write.
1334 */
f38e098f
ZA		 1335 kvm->arch.last_tsc_nsec = ns;
1336 kvm->arch.last_tsc_write = data;
5d3cb0f6 1337 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1338
b183aa58 1339 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1340
1341 /* Keep track of which generation this VCPU has synchronized to */
1342 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1343 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1344 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1345
ba904635
WA		 1346 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1347 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1348 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1349 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1350
1351 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1352 if (!matched) {
b48aa97e 1353 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1354 } else if (!already_matched) {
1355 kvm->arch.nr_vcpus_matched_tsc++;
1356 }
b48aa97e
MT		 1357
1358 kvm_track_tsc_matching(vcpu);
1359 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1360}
e26101b1 1361
99e3e30a
ZA		 1362EXPORT_SYMBOL_GPL(kvm_write_tsc);
1363
d828199e
MT		 1364#ifdef CONFIG_X86_64
1365
1366static cycle_t read_tsc(void)
1367{
1368 cycle_t ret;
1369 u64 last;
1370
1371 /*
1372 * Empirically, a fence (of type that depends on the CPU)
1373 * before rdtsc is enough to ensure that rdtsc is ordered
1374 * with respect to loads. The various CPU manuals are unclear
1375 * as to whether rdtsc can be reordered with later loads,
1376 * but no one has ever seen it happen.
1377 */
1378 rdtsc_barrier();
1379 ret = (cycle_t)vget_cycles();
1380
1381 last = pvclock_gtod_data.clock.cycle_last;
1382
1383 if (likely(ret >= last))
1384 return ret;
1385
1386 /*
1387 * GCC likes to generate cmov here, but this branch is extremely
1388 * predictable (it's just a funciton of time and the likely is
1389 * very likely) and there's a data dependence, so force GCC
1390 * to generate a branch instead. I don't barrier() because
1391 * we don't actually need a barrier, and if this function
1392 * ever gets inlined it will generate worse code.
1393 */
1394 asm volatile ("");
1395 return last;
1396}
1397
1398static inline u64 vgettsc(cycle_t *cycle_now)
1399{
1400 long v;
1401 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1402
1403 *cycle_now = read_tsc();
1404
1405 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1406 return v * gtod->clock.mult;
1407}
1408
cbcf2dd3 1409static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1410{
cbcf2dd3 1411 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1412 unsigned long seq;
d828199e 1413 int mode;
cbcf2dd3 1414 u64 ns;
d828199e 1415
d828199e
MT		 1416 do {
1417 seq = read_seqcount_begin(&gtod->seq);
1418 mode = gtod->clock.vclock_mode;
cbcf2dd3 1419 ns = gtod->nsec_base;
d828199e
MT		 1420 ns += vgettsc(cycle_now);
1421 ns >>= gtod->clock.shift;
cbcf2dd3 1422 ns += gtod->boot_ns;
d828199e 1423 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1424 *t = ns;
d828199e
MT		 1425
1426 return mode;
1427}
1428
1429/* returns true if host is using tsc clocksource */
1430static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1431{
d828199e
MT		 1432 /* checked again under seqlock below */
1433 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1434 return false;
1435
cbcf2dd3 1436 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1437}
1438#endif
1439
1440/*
1441 *
b48aa97e
MT		 1442 * Assuming a stable TSC across physical CPUS, and a stable TSC
1443 * across virtual CPUs, the following condition is possible.
1444 * Each numbered line represents an event visible to both
d828199e
MT		 1445 * CPUs at the next numbered event.
1446 *
1447 * "timespecX" represents host monotonic time. "tscX" represents
1448 * RDTSC value.
1449 *
1450 * VCPU0 on CPU0 | VCPU1 on CPU1
1451 *
1452 * 1. read timespec0,tsc0
1453 * 2. | timespec1 = timespec0 + N
1454 * | tsc1 = tsc0 + M
1455 * 3. transition to guest | transition to guest
1456 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1457 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1458 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1459 *
1460 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1461 *
1462 * - ret0 < ret1
1463 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1464 * ...
1465 * - 0 < N - M => M < N
1466 *
1467 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1468 * always the case (the difference between two distinct xtime instances
1469 * might be smaller then the difference between corresponding TSC reads,
1470 * when updating guest vcpus pvclock areas).
1471 *
1472 * To avoid that problem, do not allow visibility of distinct
1473 * system_timestamp/tsc_timestamp values simultaneously: use a master
1474 * copy of host monotonic time values. Update that master copy
1475 * in lockstep.
1476 *
b48aa97e 1477 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1478 *
1479 */
1480
1481static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1482{
1483#ifdef CONFIG_X86_64
1484 struct kvm_arch *ka = &kvm->arch;
1485 int vclock_mode;
b48aa97e
MT		 1486 bool host_tsc_clocksource, vcpus_matched;
1487
1488 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1489 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1490
1491 /*
1492 * If the host uses TSC clock, then passthrough TSC as stable
1493 * to the guest.
1494 */
b48aa97e 1495 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1496 &ka->master_kernel_ns,
1497 &ka->master_cycle_now);
1498
16a96021
MT		 1499 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1500 && !backwards_tsc_observed;
b48aa97e 1501
d828199e
MT		 1502 if (ka->use_master_clock)
1503 atomic_set(&kvm_guest_has_master_clock, 1);
1504
1505 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1506 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1507 vcpus_matched);
d828199e
MT		 1508#endif
1509}
1510
2e762ff7
MT		 1511static void kvm_gen_update_masterclock(struct kvm *kvm)
1512{
1513#ifdef CONFIG_X86_64
1514 int i;
1515 struct kvm_vcpu *vcpu;
1516 struct kvm_arch *ka = &kvm->arch;
1517
1518 spin_lock(&ka->pvclock_gtod_sync_lock);
1519 kvm_make_mclock_inprogress_request(kvm);
1520 /* no guest entries from this point */
1521 pvclock_update_vm_gtod_copy(kvm);
1522
1523 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1525
1526 /* guest entries allowed */
1527 kvm_for_each_vcpu(i, vcpu, kvm)
1528 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1529
1530 spin_unlock(&ka->pvclock_gtod_sync_lock);
1531#endif
1532}
1533
34c238a1 1534static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1535{
d828199e 1536 unsigned long flags, this_tsc_khz;
18068523 1537 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1538 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1539 s64 kernel_ns;
d828199e 1540 u64 tsc_timestamp, host_tsc;
0b79459b 1541 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1542 u8 pvclock_flags;
d828199e
MT		 1543 bool use_master_clock;
1544
1545 kernel_ns = 0;
1546 host_tsc = 0;
18068523 1547
d828199e
MT		 1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
1552 spin_lock(&ka->pvclock_gtod_sync_lock);
1553 use_master_clock = ka->use_master_clock;
1554 if (use_master_clock) {
1555 host_tsc = ka->master_cycle_now;
1556 kernel_ns = ka->master_kernel_ns;
1557 }
1558 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1559
1560 /* Keep irq disabled to prevent changes to the clock */
1561 local_irq_save(flags);
1562 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1563 if (unlikely(this_tsc_khz == 0)) {
1564 local_irq_restore(flags);
1565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1566 return 1;
1567 }
d828199e
MT		 1568 if (!use_master_clock) {
1569 host_tsc = native_read_tsc();
1570 kernel_ns = get_kernel_ns();
1571 }
1572
1573 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1574
c285545f
ZA		 1575 /*
1576 * We may have to catch up the TSC to match elapsed wall clock
1577 * time for two reasons, even if kvmclock is used.
1578 * 1) CPU could have been running below the maximum TSC rate
1579 * 2) Broken TSC compensation resets the base at each VCPU
1580 * entry to avoid unknown leaps of TSC even when running
1581 * again on the same CPU. This may cause apparent elapsed
1582 * time to disappear, and the guest to stand still or run
1583 * very slowly.
1584 */
1585 if (vcpu->tsc_catchup) {
1586 u64 tsc = compute_guest_tsc(v, kernel_ns);
1587 if (tsc > tsc_timestamp) {
f1e2b260 1588 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1589 tsc_timestamp = tsc;
1590 }
50d0a0f9
GH		 1591 }
1592
18068523
GOC		 1593 local_irq_restore(flags);
1594
0b79459b 1595 if (!vcpu->pv_time_enabled)
c285545f 1596 return 0;
18068523 1597
e48672fa 1598 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1599 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600 &vcpu->hv_clock.tsc_shift,
1601 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1602 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1603 }
1604
1605 /* With all the info we got, fill in the values */
1d5f066e 1606 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1607 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1608 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1609
18068523
GOC		 1610 /*
1611 * The interface expects us to write an even number signaling that the
1612 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1613 * state, we just increase by 2 at the end.
18068523 1614 */
50d0a0f9 1615 vcpu->hv_clock.version += 2;
18068523 1616
0b79459b
AH		 1617 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618 &guest_hv_clock, sizeof(guest_hv_clock))))
1619 return 0;
78c0337a
MT		 1620
1621 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1622 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1623
1624 if (vcpu->pvclock_set_guest_stopped_request) {
1625 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626 vcpu->pvclock_set_guest_stopped_request = false;
1627 }
1628
d828199e
MT		 1629 /* If the host uses TSC clocksource, then it is stable */
1630 if (use_master_clock)
1631 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632
78c0337a
MT		 1633 vcpu->hv_clock.flags = pvclock_flags;
1634
0b79459b
AH		 1635 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636 &vcpu->hv_clock,
1637 sizeof(vcpu->hv_clock));
8cfdc000 1638 return 0;
c8076604
GH		 1639}
1640
0061d53d
MT		 1641/*
1642 * kvmclock updates which are isolated to a given vcpu, such as
1643 * vcpu->cpu migration, should not allow system_timestamp from
1644 * the rest of the vcpus to remain static. Otherwise ntp frequency
1645 * correction applies to one vcpu's system_timestamp but not
1646 * the others.
1647 *
1648 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1649 * We need to rate-limit these requests though, as they can
1650 * considerably slow guests that have a large number of vcpus.
1651 * The time for a remote vcpu to update its kvmclock is bound
1652 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1653 */
1654
7e44e449
AJ		 1655#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1656
1657static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1658{
1659 int i;
7e44e449
AJ		 1660 struct delayed_work *dwork = to_delayed_work(work);
1661 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1662 kvmclock_update_work);
1663 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1664 struct kvm_vcpu *vcpu;
1665
1666 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1667 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1668 kvm_vcpu_kick(vcpu);
1669 }
1670}
1671
7e44e449
AJ		 1672static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1673{
1674 struct kvm *kvm = v->kvm;
1675
105b21bb 1676 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1677 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1678 KVMCLOCK_UPDATE_DELAY);
1679}
1680
332967a3
AJ		 1681#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1682
1683static void kvmclock_sync_fn(struct work_struct *work)
1684{
1685 struct delayed_work *dwork = to_delayed_work(work);
1686 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687 kvmclock_sync_work);
1688 struct kvm *kvm = container_of(ka, struct kvm, arch);
1689
1690 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1691 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1692 KVMCLOCK_SYNC_PERIOD);
1693}
1694
9ba075a6
AK		 1695static bool msr_mtrr_valid(unsigned msr)
1696{
1697 switch (msr) {
1698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1699 case MSR_MTRRfix64K_00000:
1700 case MSR_MTRRfix16K_80000:
1701 case MSR_MTRRfix16K_A0000:
1702 case MSR_MTRRfix4K_C0000:
1703 case MSR_MTRRfix4K_C8000:
1704 case MSR_MTRRfix4K_D0000:
1705 case MSR_MTRRfix4K_D8000:
1706 case MSR_MTRRfix4K_E0000:
1707 case MSR_MTRRfix4K_E8000:
1708 case MSR_MTRRfix4K_F0000:
1709 case MSR_MTRRfix4K_F8000:
1710 case MSR_MTRRdefType:
1711 case MSR_IA32_CR_PAT:
1712 return true;
1713 case 0x2f8:
1714 return true;
1715 }
1716 return false;
1717}
1718
d6289b93
MT		 1719static bool valid_pat_type(unsigned t)
1720{
1721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1722}
1723
1724static bool valid_mtrr_type(unsigned t)
1725{
1726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1727}
1728
1729static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1730{
1731 int i;
fd275235 1732 u64 mask;
d6289b93
MT		 1733
1734 if (!msr_mtrr_valid(msr))
1735 return false;
1736
1737 if (msr == MSR_IA32_CR_PAT) {
1738 for (i = 0; i < 8; i++)
1739 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1740 return false;
1741 return true;
1742 } else if (msr == MSR_MTRRdefType) {
1743 if (data & ~0xcff)
1744 return false;
1745 return valid_mtrr_type(data & 0xff);
1746 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1747 for (i = 0; i < 8 ; i++)
1748 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1749 return false;
1750 return true;
1751 }
1752
1753 /* variable MTRRs */
adfb5d27
WL		 1754 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1755
fd275235 1756 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1757 if ((msr & 1) == 0) {
adfb5d27 1758 /* MTRR base */
d7a2a246
WL		 1759 if (!valid_mtrr_type(data & 0xff))
1760 return false;
1761 mask |= 0xf00;
1762 } else
1763 /* MTRR mask */
1764 mask |= 0x7ff;
1765 if (data & mask) {
1766 kvm_inject_gp(vcpu, 0);
1767 return false;
1768 }
1769
adfb5d27 1770 return true;
d6289b93
MT		 1771}
1772
9ba075a6
AK		 1773static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1774{
0bed3b56
SY		 1775 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1776
d6289b93 1777 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1778 return 1;
1779
0bed3b56
SY		 1780 if (msr == MSR_MTRRdefType) {
1781 vcpu->arch.mtrr_state.def_type = data;
1782 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1783 } else if (msr == MSR_MTRRfix64K_00000)
1784 p[0] = data;
1785 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1786 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1787 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1788 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1789 else if (msr == MSR_IA32_CR_PAT)
1790 vcpu->arch.pat = data;
1791 else { /* Variable MTRRs */
1792 int idx, is_mtrr_mask;
1793 u64 *pt;
1794
1795 idx = (msr - 0x200) / 2;
1796 is_mtrr_mask = msr - 0x200 - 2 * idx;
1797 if (!is_mtrr_mask)
1798 pt =
1799 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1800 else
1801 pt =
1802 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1803 *pt = data;
1804 }
1805
1806 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1807 return 0;
1808}
15c4a640 1809
890ca9ae 1810static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1811{
890ca9ae
HY		 1812 u64 mcg_cap = vcpu->arch.mcg_cap;
1813 unsigned bank_num = mcg_cap & 0xff;
1814
15c4a640 1815 switch (msr) {
15c4a640 1816 case MSR_IA32_MCG_STATUS:
890ca9ae 1817 vcpu->arch.mcg_status = data;
15c4a640 1818 break;
c7ac679c 1819 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1820 if (!(mcg_cap & MCG_CTL_P))
1821 return 1;
1822 if (data != 0 && data != ~(u64)0)
1823 return -1;
1824 vcpu->arch.mcg_ctl = data;
1825 break;
1826 default:
1827 if (msr >= MSR_IA32_MC0_CTL &&
1828 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1829 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1830 /* only 0 or all 1s can be written to IA32_MCi_CTL
1831 * some Linux kernels though clear bit 10 in bank 4 to
1832 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1833 * this to avoid an uncatched #GP in the guest
1834 */
890ca9ae 1835 if ((offset & 0x3) == 0 &&
114be429 1836 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1837 return -1;
1838 vcpu->arch.mce_banks[offset] = data;
1839 break;
1840 }
1841 return 1;
1842 }
1843 return 0;
1844}
1845
ffde22ac
ES		 1846static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1847{
1848 struct kvm *kvm = vcpu->kvm;
1849 int lm = is_long_mode(vcpu);
1850 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1851 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1852 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1853 : kvm->arch.xen_hvm_config.blob_size_32;
1854 u32 page_num = data & ~PAGE_MASK;
1855 u64 page_addr = data & PAGE_MASK;
1856 u8 *page;
1857 int r;
1858
1859 r = -E2BIG;
1860 if (page_num >= blob_size)
1861 goto out;
1862 r = -ENOMEM;
ff5c2c03
SL		 1863 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1864 if (IS_ERR(page)) {
1865 r = PTR_ERR(page);
ffde22ac 1866 goto out;
ff5c2c03 1867 }
ffde22ac
ES		 1868 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1869 goto out_free;
1870 r = 0;
1871out_free:
1872 kfree(page);
1873out:
1874 return r;
1875}
1876
55cd8e5a
GN		 1877static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1878{
1879 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1880}
1881
1882static bool kvm_hv_msr_partition_wide(u32 msr)
1883{
1884 bool r = false;
1885 switch (msr) {
1886 case HV_X64_MSR_GUEST_OS_ID:
1887 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1888 case HV_X64_MSR_REFERENCE_TSC:
1889 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1890 r = true;
1891 break;
1892 }
1893
1894 return r;
1895}
1896
1897static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1898{
1899 struct kvm *kvm = vcpu->kvm;
1900
1901 switch (msr) {
1902 case HV_X64_MSR_GUEST_OS_ID:
1903 kvm->arch.hv_guest_os_id = data;
1904 /* setting guest os id to zero disables hypercall page */
1905 if (!kvm->arch.hv_guest_os_id)
1906 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1907 break;
1908 case HV_X64_MSR_HYPERCALL: {
1909 u64 gfn;
1910 unsigned long addr;
1911 u8 instructions[4];
1912
1913 /* if guest os id is not set hypercall should remain disabled */
1914 if (!kvm->arch.hv_guest_os_id)
1915 break;
1916 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1917 kvm->arch.hv_hypercall = data;
1918 break;
1919 }
1920 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1921 addr = gfn_to_hva(kvm, gfn);
1922 if (kvm_is_error_hva(addr))
1923 return 1;
1924 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1925 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1926 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1927 return 1;
1928 kvm->arch.hv_hypercall = data;
b94b64c9 1929 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1930 break;
1931 }
e984097b
VR		 1932 case HV_X64_MSR_REFERENCE_TSC: {
1933 u64 gfn;
1934 HV_REFERENCE_TSC_PAGE tsc_ref;
1935 memset(&tsc_ref, 0, sizeof(tsc_ref));
1936 kvm->arch.hv_tsc_page = data;
1937 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1938 break;
1939 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1940 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1941 &tsc_ref, sizeof(tsc_ref)))
1942 return 1;
1943 mark_page_dirty(kvm, gfn);
1944 break;
1945 }
55cd8e5a 1946 default:
a737f256
CD		 1947 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1949 return 1;
1950 }
1951 return 0;
1952}
1953
1954static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1955{
10388a07
GN		 1956 switch (msr) {
1957 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1958 u64 gfn;
10388a07 1959 unsigned long addr;
55cd8e5a 1960
10388a07
GN		 1961 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1962 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1963 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1964 return 1;
10388a07
GN		 1965 break;
1966 }
b3af1e88
VR		 1967 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1968 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1969 if (kvm_is_error_hva(addr))
1970 return 1;
8b0cedff 1971 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1972 return 1;
1973 vcpu->arch.hv_vapic = data;
b3af1e88 1974 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1975 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1976 return 1;
10388a07
GN		 1977 break;
1978 }
1979 case HV_X64_MSR_EOI:
1980 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1981 case HV_X64_MSR_ICR:
1982 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1983 case HV_X64_MSR_TPR:
1984 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1985 default:
a737f256
CD		 1986 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1987 "data 0x%llx\n", msr, data);
10388a07
GN		 1988 return 1;
1989 }
1990
1991 return 0;
55cd8e5a
GN		 1992}
1993
344d9588
GN		 1994static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1995{
1996 gpa_t gpa = data & ~0x3f;
1997
4a969980 1998 /* Bits 2:5 are reserved, Should be zero */
6adba527 1999 if (data & 0x3c)
344d9588
GN		 2000 return 1;
2001
2002 vcpu->arch.apf.msr_val = data;
2003
2004 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2005 kvm_clear_async_pf_completion_queue(vcpu);
2006 kvm_async_pf_hash_reset(vcpu);
2007 return 0;
2008 }
2009
8f964525
AH		 2010 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2011 sizeof(u32)))
344d9588
GN		 2012 return 1;
2013
6adba527 2014 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2015 kvm_async_pf_wakeup_all(vcpu);
2016 return 0;
2017}
2018
12f9a48f
GC		 2019static void kvmclock_reset(struct kvm_vcpu *vcpu)
2020{
0b79459b 2021 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2022}
2023
c9aaa895
GC		 2024static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2025{
2026 u64 delta;
2027
2028 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2029 return;
2030
2031 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2032 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2033 vcpu->arch.st.accum_steal = delta;
2034}
2035
2036static void record_steal_time(struct kvm_vcpu *vcpu)
2037{
2038 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2039 return;
2040
2041 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2042 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2043 return;
2044
2045 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2046 vcpu->arch.st.steal.version += 2;
2047 vcpu->arch.st.accum_steal = 0;
2048
2049 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2050 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2051}
2052
8fe8ab46 2053int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2054{
5753785f 2055 bool pr = false;
8fe8ab46
WA		 2056 u32 msr = msr_info->index;
2057 u64 data = msr_info->data;
5753785f 2058
15c4a640 2059 switch (msr) {
2e32b719
BP		 2060 case MSR_AMD64_NB_CFG:
2061 case MSR_IA32_UCODE_REV:
2062 case MSR_IA32_UCODE_WRITE:
2063 case MSR_VM_HSAVE_PA:
2064 case MSR_AMD64_PATCH_LOADER:
2065 case MSR_AMD64_BU_CFG2:
2066 break;
2067
15c4a640 2068 case MSR_EFER:
b69e8cae 2069 return set_efer(vcpu, data);
8f1589d9
AP		 2070 case MSR_K7_HWCR:
2071 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2072 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2073 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2074 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2075 if (data != 0) {
a737f256
CD		 2076 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2077 data);
8f1589d9
AP		 2078 return 1;
2079 }
15c4a640 2080 break;
f7c6d140
AP		 2081 case MSR_FAM10H_MMIO_CONF_BASE:
2082 if (data != 0) {
a737f256
CD		 2083 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2084 "0x%llx\n", data);
f7c6d140
AP		 2085 return 1;
2086 }
15c4a640 2087 break;
b5e2fec0
AG		 2088 case MSR_IA32_DEBUGCTLMSR:
2089 if (!data) {
2090 /* We support the non-activated case already */
2091 break;
2092 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2093 /* Values other than LBR and BTF are vendor-specific,
2094 thus reserved and should throw a #GP */
2095 return 1;
2096 }
a737f256
CD		 2097 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2098 __func__, data);
b5e2fec0 2099 break;
9ba075a6
AK		 2100 case 0x200 ... 0x2ff:
2101 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2102 case MSR_IA32_APICBASE:
58cb628d 2103 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2104 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2105 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2106 case MSR_IA32_TSCDEADLINE:
2107 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2108 break;
ba904635
WA		 2109 case MSR_IA32_TSC_ADJUST:
2110 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2111 if (!msr_info->host_initiated) {
2112 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2113 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2114 }
2115 vcpu->arch.ia32_tsc_adjust_msr = data;
2116 }
2117 break;
15c4a640 2118 case MSR_IA32_MISC_ENABLE:
ad312c7c 2119 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2120 break;
11c6bffa 2121 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2122 case MSR_KVM_WALL_CLOCK:
2123 vcpu->kvm->arch.wall_clock = data;
2124 kvm_write_wall_clock(vcpu->kvm, data);
2125 break;
11c6bffa 2126 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2127 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2128 u64 gpa_offset;
12f9a48f 2129 kvmclock_reset(vcpu);
18068523
GOC		 2130
2131 vcpu->arch.time = data;
0061d53d 2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2133
2134 /* we verify if the enable bit is set... */
2135 if (!(data & 1))
2136 break;
2137
0b79459b 2138 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2139
0b79459b 2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2141 &vcpu->arch.pv_time, data & ~1ULL,
2142 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2143 vcpu->arch.pv_time_enabled = false;
2144 else
2145 vcpu->arch.pv_time_enabled = true;
32cad84f 2146
18068523
GOC		 2147 break;
2148 }
344d9588
GN		 2149 case MSR_KVM_ASYNC_PF_EN:
2150 if (kvm_pv_enable_async_pf(vcpu, data))
2151 return 1;
2152 break;
c9aaa895
GC		 2153 case MSR_KVM_STEAL_TIME:
2154
2155 if (unlikely(!sched_info_on()))
2156 return 1;
2157
2158 if (data & KVM_STEAL_RESERVED_MASK)
2159 return 1;
2160
2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2162 data & KVM_STEAL_VALID_BITS,
2163 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2164 return 1;
2165
2166 vcpu->arch.st.msr_val = data;
2167
2168 if (!(data & KVM_MSR_ENABLED))
2169 break;
2170
2171 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2172
2173 preempt_disable();
2174 accumulate_steal_time(vcpu);
2175 preempt_enable();
2176
2177 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2178
2179 break;
ae7a2a3f
MT		 2180 case MSR_KVM_PV_EOI_EN:
2181 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2182 return 1;
2183 break;
c9aaa895 2184
890ca9ae
HY		 2185 case MSR_IA32_MCG_CTL:
2186 case MSR_IA32_MCG_STATUS:
2187 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2188 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2189
2190 /* Performance counters are not protected by a CPUID bit,
2191 * so we should check all of them in the generic path for the sake of
2192 * cross vendor migration.
2193 * Writing a zero into the event select MSRs disables them,
2194 * which we perfectly emulate ;-). Any other value should be at least
2195 * reported, some guests depend on them.
2196 */
71db6023
AP		 2197 case MSR_K7_EVNTSEL0:
2198 case MSR_K7_EVNTSEL1:
2199 case MSR_K7_EVNTSEL2:
2200 case MSR_K7_EVNTSEL3:
2201 if (data != 0)
a737f256
CD		 2202 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2203 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2204 break;
2205 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2206 * so we ignore writes to make it happy.
2207 */
71db6023
AP		 2208 case MSR_K7_PERFCTR0:
2209 case MSR_K7_PERFCTR1:
2210 case MSR_K7_PERFCTR2:
2211 case MSR_K7_PERFCTR3:
a737f256
CD		 2212 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2213 "0x%x data 0x%llx\n", msr, data);
71db6023 2214 break;
5753785f
GN		 2215 case MSR_P6_PERFCTR0:
2216 case MSR_P6_PERFCTR1:
2217 pr = true;
2218 case MSR_P6_EVNTSEL0:
2219 case MSR_P6_EVNTSEL1:
2220 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2221 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2222
2223 if (pr || data != 0)
a737f256
CD		 2224 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2225 "0x%x data 0x%llx\n", msr, data);
5753785f 2226 break;
84e0cefa
JS		 2227 case MSR_K7_CLK_CTL:
2228 /*
2229 * Ignore all writes to this no longer documented MSR.
2230 * Writes are only relevant for old K7 processors,
2231 * all pre-dating SVM, but a recommended workaround from
4a969980 2232 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2233 * affected processor models on the command line, hence
2234 * the need to ignore the workaround.
2235 */
2236 break;
55cd8e5a
GN		 2237 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2238 if (kvm_hv_msr_partition_wide(msr)) {
2239 int r;
2240 mutex_lock(&vcpu->kvm->lock);
2241 r = set_msr_hyperv_pw(vcpu, msr, data);
2242 mutex_unlock(&vcpu->kvm->lock);
2243 return r;
2244 } else
2245 return set_msr_hyperv(vcpu, msr, data);
2246 break;
91c9c3ed 2247 case MSR_IA32_BBL_CR_CTL3:
2248 /* Drop writes to this legacy MSR -- see rdmsr
2249 * counterpart for further detail.
2250 */
a737f256 2251 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2252 break;
2b036c6b
BO		 2253 case MSR_AMD64_OSVW_ID_LENGTH:
2254 if (!guest_cpuid_has_osvw(vcpu))
2255 return 1;
2256 vcpu->arch.osvw.length = data;
2257 break;
2258 case MSR_AMD64_OSVW_STATUS:
2259 if (!guest_cpuid_has_osvw(vcpu))
2260 return 1;
2261 vcpu->arch.osvw.status = data;
2262 break;
15c4a640 2263 default:
ffde22ac
ES		 2264 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2265 return xen_hvm_config(vcpu, data);
f5132b01 2266 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2267 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2268 if (!ignore_msrs) {
a737f256
CD		 2269 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2270 msr, data);
ed85c068
AP		 2271 return 1;
2272 } else {
a737f256
CD		 2273 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2274 msr, data);
ed85c068
AP		 2275 break;
2276 }
15c4a640
CO		 2277 }
2278 return 0;
2279}
2280EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2281
2282
2283/*
2284 * Reads an msr value (of 'msr_index') into 'pdata'.
2285 * Returns 0 on success, non-0 otherwise.
2286 * Assumes vcpu_load() was already called.
2287 */
2288int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2289{
2290 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2291}
2292
9ba075a6
AK		 2293static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2294{
0bed3b56
SY		 2295 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2296
9ba075a6
AK		 2297 if (!msr_mtrr_valid(msr))
2298 return 1;
2299
0bed3b56
SY		 2300 if (msr == MSR_MTRRdefType)
2301 *pdata = vcpu->arch.mtrr_state.def_type +
2302 (vcpu->arch.mtrr_state.enabled << 10);
2303 else if (msr == MSR_MTRRfix64K_00000)
2304 *pdata = p[0];
2305 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2306 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2307 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2308 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2309 else if (msr == MSR_IA32_CR_PAT)
2310 *pdata = vcpu->arch.pat;
2311 else { /* Variable MTRRs */
2312 int idx, is_mtrr_mask;
2313 u64 *pt;
2314
2315 idx = (msr - 0x200) / 2;
2316 is_mtrr_mask = msr - 0x200 - 2 * idx;
2317 if (!is_mtrr_mask)
2318 pt =
2319 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2320 else
2321 pt =
2322 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2323 *pdata = *pt;
2324 }
2325
9ba075a6
AK		 2326 return 0;
2327}
2328
890ca9ae 2329static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2330{
2331 u64 data;
890ca9ae
HY		 2332 u64 mcg_cap = vcpu->arch.mcg_cap;
2333 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2334
2335 switch (msr) {
15c4a640
CO		 2336 case MSR_IA32_P5_MC_ADDR:
2337 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2338 data = 0;
2339 break;
15c4a640 2340 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2341 data = vcpu->arch.mcg_cap;
2342 break;
c7ac679c 2343 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2344 if (!(mcg_cap & MCG_CTL_P))
2345 return 1;
2346 data = vcpu->arch.mcg_ctl;
2347 break;
2348 case MSR_IA32_MCG_STATUS:
2349 data = vcpu->arch.mcg_status;
2350 break;
2351 default:
2352 if (msr >= MSR_IA32_MC0_CTL &&
2353 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2354 u32 offset = msr - MSR_IA32_MC0_CTL;
2355 data = vcpu->arch.mce_banks[offset];
2356 break;
2357 }
2358 return 1;
2359 }
2360 *pdata = data;
2361 return 0;
2362}
2363
55cd8e5a
GN		 2364static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2365{
2366 u64 data = 0;
2367 struct kvm *kvm = vcpu->kvm;
2368
2369 switch (msr) {
2370 case HV_X64_MSR_GUEST_OS_ID:
2371 data = kvm->arch.hv_guest_os_id;
2372 break;
2373 case HV_X64_MSR_HYPERCALL:
2374 data = kvm->arch.hv_hypercall;
2375 break;
e984097b
VR		 2376 case HV_X64_MSR_TIME_REF_COUNT: {
2377 data =
2378 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2379 break;
2380 }
2381 case HV_X64_MSR_REFERENCE_TSC:
2382 data = kvm->arch.hv_tsc_page;
2383 break;
55cd8e5a 2384 default:
a737f256 2385 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2386 return 1;
2387 }
2388
2389 *pdata = data;
2390 return 0;
2391}
2392
2393static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2394{
2395 u64 data = 0;
2396
2397 switch (msr) {
2398 case HV_X64_MSR_VP_INDEX: {
2399 int r;
2400 struct kvm_vcpu *v;
684851a1
TY		 2401 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2402 if (v == vcpu) {
55cd8e5a 2403 data = r;
684851a1
TY		 2404 break;
2405 }
2406 }
55cd8e5a
GN		 2407 break;
2408 }
10388a07
GN		 2409 case HV_X64_MSR_EOI:
2410 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2411 case HV_X64_MSR_ICR:
2412 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2413 case HV_X64_MSR_TPR:
2414 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2415 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2416 data = vcpu->arch.hv_vapic;
2417 break;
55cd8e5a 2418 default:
a737f256 2419 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2420 return 1;
2421 }
2422 *pdata = data;
2423 return 0;
2424}
2425
890ca9ae
HY		 2426int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2427{
2428 u64 data;
2429
2430 switch (msr) {
890ca9ae 2431 case MSR_IA32_PLATFORM_ID:
15c4a640 2432 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2433 case MSR_IA32_DEBUGCTLMSR:
2434 case MSR_IA32_LASTBRANCHFROMIP:
2435 case MSR_IA32_LASTBRANCHTOIP:
2436 case MSR_IA32_LASTINTFROMIP:
2437 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2438 case MSR_K8_SYSCFG:
2439 case MSR_K7_HWCR:
61a6bd67 2440 case MSR_VM_HSAVE_PA:
9e699624 2441 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2442 case MSR_K7_EVNTSEL1:
2443 case MSR_K7_EVNTSEL2:
2444 case MSR_K7_EVNTSEL3:
1f3ee616 2445 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2446 case MSR_K7_PERFCTR1:
2447 case MSR_K7_PERFCTR2:
2448 case MSR_K7_PERFCTR3:
1fdbd48c 2449 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2450 case MSR_AMD64_NB_CFG:
f7c6d140 2451 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2452 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2453 data = 0;
2454 break;
5753785f
GN		 2455 case MSR_P6_PERFCTR0:
2456 case MSR_P6_PERFCTR1:
2457 case MSR_P6_EVNTSEL0:
2458 case MSR_P6_EVNTSEL1:
2459 if (kvm_pmu_msr(vcpu, msr))
2460 return kvm_pmu_get_msr(vcpu, msr, pdata);
2461 data = 0;
2462 break;
742bc670
MT		 2463 case MSR_IA32_UCODE_REV:
2464 data = 0x100000000ULL;
2465 break;
9ba075a6
AK		 2466 case MSR_MTRRcap:
2467 data = 0x500 | KVM_NR_VAR_MTRR;
2468 break;
2469 case 0x200 ... 0x2ff:
2470 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2471 case 0xcd: /* fsb frequency */
2472 data = 3;
2473 break;
7b914098
JS		 2474 /*
2475 * MSR_EBC_FREQUENCY_ID
2476 * Conservative value valid for even the basic CPU models.
2477 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2478 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2479 * and 266MHz for model 3, or 4. Set Core Clock
2480 * Frequency to System Bus Frequency Ratio to 1 (bits
2481 * 31:24) even though these are only valid for CPU
2482 * models > 2, however guests may end up dividing or
2483 * multiplying by zero otherwise.
2484 */
2485 case MSR_EBC_FREQUENCY_ID:
2486 data = 1 << 24;
2487 break;
15c4a640
CO		 2488 case MSR_IA32_APICBASE:
2489 data = kvm_get_apic_base(vcpu);
2490 break;
0105d1a5
GN		 2491 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2492 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2493 break;
a3e06bbe
LJ		 2494 case MSR_IA32_TSCDEADLINE:
2495 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2496 break;
ba904635
WA		 2497 case MSR_IA32_TSC_ADJUST:
2498 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2499 break;
15c4a640 2500 case MSR_IA32_MISC_ENABLE:
ad312c7c 2501 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2502 break;
847f0ad8
AG		 2503 case MSR_IA32_PERF_STATUS:
2504 /* TSC increment by tick */
2505 data = 1000ULL;
2506 /* CPU multiplier */
2507 data |= (((uint64_t)4ULL) << 40);
2508 break;
15c4a640 2509 case MSR_EFER:
f6801dff 2510 data = vcpu->arch.efer;
15c4a640 2511 break;
18068523 2512 case MSR_KVM_WALL_CLOCK:
11c6bffa 2513 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2514 data = vcpu->kvm->arch.wall_clock;
2515 break;
2516 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2517 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2518 data = vcpu->arch.time;
2519 break;
344d9588
GN		 2520 case MSR_KVM_ASYNC_PF_EN:
2521 data = vcpu->arch.apf.msr_val;
2522 break;
c9aaa895
GC		 2523 case MSR_KVM_STEAL_TIME:
2524 data = vcpu->arch.st.msr_val;
2525 break;
1d92128f
MT		 2526 case MSR_KVM_PV_EOI_EN:
2527 data = vcpu->arch.pv_eoi.msr_val;
2528 break;
890ca9ae
HY		 2529 case MSR_IA32_P5_MC_ADDR:
2530 case MSR_IA32_P5_MC_TYPE:
2531 case MSR_IA32_MCG_CAP:
2532 case MSR_IA32_MCG_CTL:
2533 case MSR_IA32_MCG_STATUS:
2534 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2535 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2536 case MSR_K7_CLK_CTL:
2537 /*
2538 * Provide expected ramp-up count for K7. All other
2539 * are set to zero, indicating minimum divisors for
2540 * every field.
2541 *
2542 * This prevents guest kernels on AMD host with CPU
2543 * type 6, model 8 and higher from exploding due to
2544 * the rdmsr failing.
2545 */
2546 data = 0x20000000;
2547 break;
55cd8e5a
GN		 2548 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2549 if (kvm_hv_msr_partition_wide(msr)) {
2550 int r;
2551 mutex_lock(&vcpu->kvm->lock);
2552 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2553 mutex_unlock(&vcpu->kvm->lock);
2554 return r;
2555 } else
2556 return get_msr_hyperv(vcpu, msr, pdata);
2557 break;
91c9c3ed 2558 case MSR_IA32_BBL_CR_CTL3:
2559 /* This legacy MSR exists but isn't fully documented in current
2560 * silicon. It is however accessed by winxp in very narrow
2561 * scenarios where it sets bit #19, itself documented as
2562 * a "reserved" bit. Best effort attempt to source coherent
2563 * read data here should the balance of the register be
2564 * interpreted by the guest:
2565 *
2566 * L2 cache control register 3: 64GB range, 256KB size,
2567 * enabled, latency 0x1, configured
2568 */
2569 data = 0xbe702111;
2570 break;
2b036c6b
BO		 2571 case MSR_AMD64_OSVW_ID_LENGTH:
2572 if (!guest_cpuid_has_osvw(vcpu))
2573 return 1;
2574 data = vcpu->arch.osvw.length;
2575 break;
2576 case MSR_AMD64_OSVW_STATUS:
2577 if (!guest_cpuid_has_osvw(vcpu))
2578 return 1;
2579 data = vcpu->arch.osvw.status;
2580 break;
15c4a640 2581 default:
f5132b01
GN		 2582 if (kvm_pmu_msr(vcpu, msr))
2583 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2584 if (!ignore_msrs) {
a737f256 2585 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2586 return 1;
2587 } else {
a737f256 2588 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2589 data = 0;
2590 }
2591 break;
15c4a640
CO		 2592 }
2593 *pdata = data;
2594 return 0;
2595}
2596EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2597
313a3dc7
CO		 2598/*
2599 * Read or write a bunch of msrs. All parameters are kernel addresses.
2600 *
2601 * @return number of msrs set successfully.
2602 */
2603static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2604 struct kvm_msr_entry *entries,
2605 int (*do_msr)(struct kvm_vcpu *vcpu,
2606 unsigned index, u64 *data))
2607{
f656ce01 2608 int i, idx;
313a3dc7 2609
f656ce01 2610 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2611 for (i = 0; i < msrs->nmsrs; ++i)
2612 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2613 break;
f656ce01 2614 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2615
313a3dc7
CO		 2616 return i;
2617}
2618
2619/*
2620 * Read or write a bunch of msrs. Parameters are user addresses.
2621 *
2622 * @return number of msrs set successfully.
2623 */
2624static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2625 int (*do_msr)(struct kvm_vcpu *vcpu,
2626 unsigned index, u64 *data),
2627 int writeback)
2628{
2629 struct kvm_msrs msrs;
2630 struct kvm_msr_entry *entries;
2631 int r, n;
2632 unsigned size;
2633
2634 r = -EFAULT;
2635 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2636 goto out;
2637
2638 r = -E2BIG;
2639 if (msrs.nmsrs >= MAX_IO_MSRS)
2640 goto out;
2641
313a3dc7 2642 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2643 entries = memdup_user(user_msrs->entries, size);
2644 if (IS_ERR(entries)) {
2645 r = PTR_ERR(entries);
313a3dc7 2646 goto out;
ff5c2c03 2647 }
313a3dc7
CO		 2648
2649 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2650 if (r < 0)
2651 goto out_free;
2652
2653 r = -EFAULT;
2654 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2655 goto out_free;
2656
2657 r = n;
2658
2659out_free:
7a73c028 2660 kfree(entries);
313a3dc7
CO		 2661out:
2662 return r;
2663}
2664
784aa3d7 2665int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2666{
2667 int r;
2668
2669 switch (ext) {
2670 case KVM_CAP_IRQCHIP:
2671 case KVM_CAP_HLT:
2672 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2673 case KVM_CAP_SET_TSS_ADDR:
07716717 2674 case KVM_CAP_EXT_CPUID:
9c15bb1d 2675 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2676 case KVM_CAP_CLOCKSOURCE:
7837699f 2677 case KVM_CAP_PIT:
a28e4f5a 2678 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2679 case KVM_CAP_MP_STATE:
ed848624 2680 case KVM_CAP_SYNC_MMU:
a355c85c 2681 case KVM_CAP_USER_NMI:
52d939a0 2682 case KVM_CAP_REINJECT_CONTROL:
4925663a 2683 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2684 case KVM_CAP_IRQFD:
d34e6b17 2685 case KVM_CAP_IOEVENTFD:
f848a5a8 2686 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2687 case KVM_CAP_PIT2:
e9f42757 2688 case KVM_CAP_PIT_STATE2:
b927a3ce 2689 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2690 case KVM_CAP_XEN_HVM:
afbcf7ab 2691 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2692 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2693 case KVM_CAP_HYPERV:
10388a07 2694 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2695 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2696 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2697 case KVM_CAP_DEBUGREGS:
d2be1651 2698 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2699 case KVM_CAP_XSAVE:
344d9588 2700 case KVM_CAP_ASYNC_PF:
92a1f12d 2701 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2702 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2703 case KVM_CAP_READONLY_MEM:
5f66b620 2704 case KVM_CAP_HYPERV_TIME:
100943c5 2705 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2706#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2707 case KVM_CAP_ASSIGN_DEV_IRQ:
2708 case KVM_CAP_PCI_2_3:
2709#endif
018d00d2
ZX		 2710 r = 1;
2711 break;
542472b5
LV		 2712 case KVM_CAP_COALESCED_MMIO:
2713 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2714 break;
774ead3a
AK		 2715 case KVM_CAP_VAPIC:
2716 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2717 break;
f725230a 2718 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2719 r = KVM_SOFT_MAX_VCPUS;
2720 break;
2721 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2722 r = KVM_MAX_VCPUS;
2723 break;
a988b910 2724 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2725 r = KVM_USER_MEM_SLOTS;
a988b910 2726 break;
a68a6a72
MT		 2727 case KVM_CAP_PV_MMU: /* obsolete */
2728 r = 0;
2f333bcb 2729 break;
4cee4b72 2730#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2731 case KVM_CAP_IOMMU:
a1b60c1c 2732 r = iommu_present(&pci_bus_type);
62c476c7 2733 break;
4cee4b72 2734#endif
890ca9ae
HY		 2735 case KVM_CAP_MCE:
2736 r = KVM_MAX_MCE_BANKS;
2737 break;
2d5b5a66
SY		 2738 case KVM_CAP_XCRS:
2739 r = cpu_has_xsave;
2740 break;
92a1f12d
JR		 2741 case KVM_CAP_TSC_CONTROL:
2742 r = kvm_has_tsc_control;
2743 break;
4d25a066
JK		 2744 case KVM_CAP_TSC_DEADLINE_TIMER:
2745 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2746 break;
018d00d2
ZX		 2747 default:
2748 r = 0;
2749 break;
2750 }
2751 return r;
2752
2753}
2754
043405e1
CO		 2755long kvm_arch_dev_ioctl(struct file *filp,
2756 unsigned int ioctl, unsigned long arg)
2757{
2758 void __user *argp = (void __user *)arg;
2759 long r;
2760
2761 switch (ioctl) {
2762 case KVM_GET_MSR_INDEX_LIST: {
2763 struct kvm_msr_list __user *user_msr_list = argp;
2764 struct kvm_msr_list msr_list;
2765 unsigned n;
2766
2767 r = -EFAULT;
2768 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2769 goto out;
2770 n = msr_list.nmsrs;
2771 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2772 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2773 goto out;
2774 r = -E2BIG;
e125e7b6 2775 if (n < msr_list.nmsrs)
043405e1
CO		 2776 goto out;
2777 r = -EFAULT;
2778 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2779 num_msrs_to_save * sizeof(u32)))
2780 goto out;
e125e7b6 2781 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2782 &emulated_msrs,
2783 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2784 goto out;
2785 r = 0;
2786 break;
2787 }
9c15bb1d
BP		 2788 case KVM_GET_SUPPORTED_CPUID:
2789 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2790 struct kvm_cpuid2 __user *cpuid_arg = argp;
2791 struct kvm_cpuid2 cpuid;
2792
2793 r = -EFAULT;
2794 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2795 goto out;
9c15bb1d
BP		 2796
2797 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2798 ioctl);
674eea0f
AK		 2799 if (r)
2800 goto out;
2801
2802 r = -EFAULT;
2803 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2804 goto out;
2805 r = 0;
2806 break;
2807 }
890ca9ae
HY		 2808 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2809 u64 mce_cap;
2810
2811 mce_cap = KVM_MCE_CAP_SUPPORTED;
2812 r = -EFAULT;
2813 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2814 goto out;
2815 r = 0;
2816 break;
2817 }
043405e1
CO		 2818 default:
2819 r = -EINVAL;
2820 }
2821out:
2822 return r;
2823}
2824
f5f48ee1
SY		 2825static void wbinvd_ipi(void *garbage)
2826{
2827 wbinvd();
2828}
2829
2830static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2831{
e0f0bbc5 2832 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2833}
2834
313a3dc7
CO		 2835void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2836{
f5f48ee1
SY		 2837 /* Address WBINVD may be executed by guest */
2838 if (need_emulate_wbinvd(vcpu)) {
2839 if (kvm_x86_ops->has_wbinvd_exit())
2840 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2841 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2842 smp_call_function_single(vcpu->cpu,
2843 wbinvd_ipi, NULL, 1);
2844 }
2845
313a3dc7 2846 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2847
0dd6a6ed
ZA		 2848 /* Apply any externally detected TSC adjustments (due to suspend) */
2849 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2850 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2851 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2852 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2853 }
8f6055cb 2854
48434c20 2855 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2856 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2857 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2858 if (tsc_delta < 0)
2859 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2860 if (check_tsc_unstable()) {
b183aa58
ZA		 2861 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2862 vcpu->arch.last_guest_tsc);
2863 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2864 vcpu->arch.tsc_catchup = 1;
c285545f 2865 }
d98d07ca
MT		 2866 /*
2867 * On a host with synchronized TSC, there is no need to update
2868 * kvmclock on vcpu->cpu migration
2869 */
2870 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2871 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2872 if (vcpu->cpu != cpu)
2873 kvm_migrate_timers(vcpu);
e48672fa 2874 vcpu->cpu = cpu;
6b7d7e76 2875 }
c9aaa895
GC		 2876
2877 accumulate_steal_time(vcpu);
2878 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2879}
2880
2881void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2882{
02daab21 2883 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2884 kvm_put_guest_fpu(vcpu);
6f526ec5 2885 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2886}
2887
313a3dc7
CO		 2888static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2889 struct kvm_lapic_state *s)
2890{
5a71785d 2891 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2892 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2893
2894 return 0;
2895}
2896
2897static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2898 struct kvm_lapic_state *s)
2899{
64eb0620 2900 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2901 update_cr8_intercept(vcpu);
313a3dc7
CO		 2902
2903 return 0;
2904}
2905
f77bc6a4
ZX		 2906static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2907 struct kvm_interrupt *irq)
2908{
02cdb50f 2909 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2910 return -EINVAL;
2911 if (irqchip_in_kernel(vcpu->kvm))
2912 return -ENXIO;
f77bc6a4 2913
66fd3f7f 2914 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2915 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2916
f77bc6a4
ZX		 2917 return 0;
2918}
2919
c4abb7c9
JK		 2920static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2921{
c4abb7c9 2922 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2923
2924 return 0;
2925}
2926
b209749f
AK		 2927static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2928 struct kvm_tpr_access_ctl *tac)
2929{
2930 if (tac->flags)
2931 return -EINVAL;
2932 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2933 return 0;
2934}
2935
890ca9ae
HY		 2936static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2937 u64 mcg_cap)
2938{
2939 int r;
2940 unsigned bank_num = mcg_cap & 0xff, bank;
2941
2942 r = -EINVAL;
a9e38c3e 2943 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2944 goto out;
2945 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2946 goto out;
2947 r = 0;
2948 vcpu->arch.mcg_cap = mcg_cap;
2949 /* Init IA32_MCG_CTL to all 1s */
2950 if (mcg_cap & MCG_CTL_P)
2951 vcpu->arch.mcg_ctl = ~(u64)0;
2952 /* Init IA32_MCi_CTL to all 1s */
2953 for (bank = 0; bank < bank_num; bank++)
2954 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2955out:
2956 return r;
2957}
2958
2959static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2960 struct kvm_x86_mce *mce)
2961{
2962 u64 mcg_cap = vcpu->arch.mcg_cap;
2963 unsigned bank_num = mcg_cap & 0xff;
2964 u64 *banks = vcpu->arch.mce_banks;
2965
2966 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2967 return -EINVAL;
2968 /*
2969 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2970 * reporting is disabled
2971 */
2972 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2973 vcpu->arch.mcg_ctl != ~(u64)0)
2974 return 0;
2975 banks += 4 * mce->bank;
2976 /*
2977 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2978 * reporting is disabled for the bank
2979 */
2980 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2981 return 0;
2982 if (mce->status & MCI_STATUS_UC) {
2983 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2984 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2985 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2986 return 0;
2987 }
2988 if (banks[1] & MCI_STATUS_VAL)
2989 mce->status |= MCI_STATUS_OVER;
2990 banks[2] = mce->addr;
2991 banks[3] = mce->misc;
2992 vcpu->arch.mcg_status = mce->mcg_status;
2993 banks[1] = mce->status;
2994 kvm_queue_exception(vcpu, MC_VECTOR);
2995 } else if (!(banks[1] & MCI_STATUS_VAL)
2996 || !(banks[1] & MCI_STATUS_UC)) {
2997 if (banks[1] & MCI_STATUS_VAL)
2998 mce->status |= MCI_STATUS_OVER;
2999 banks[2] = mce->addr;
3000 banks[3] = mce->misc;
3001 banks[1] = mce->status;
3002 } else
3003 banks[1] |= MCI_STATUS_OVER;
3004 return 0;
3005}
3006
3cfc3092
JK		 3007static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3008 struct kvm_vcpu_events *events)
3009{
7460fb4a 3010 process_nmi(vcpu);
03b82a30
JK		 3011 events->exception.injected =
3012 vcpu->arch.exception.pending &&
3013 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3014 events->exception.nr = vcpu->arch.exception.nr;
3015 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3016 events->exception.pad = 0;
3cfc3092
JK		 3017 events->exception.error_code = vcpu->arch.exception.error_code;
3018
03b82a30
JK		 3019 events->interrupt.injected =
3020 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3021 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3022 events->interrupt.soft = 0;
37ccdcbe 3023 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3024
3025 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3026 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3027 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3028 events->nmi.pad = 0;
3cfc3092 3029
66450a21 3030 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3031
dab4b911 3032 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3033 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3034 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3035}
3036
3037static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3038 struct kvm_vcpu_events *events)
3039{
dab4b911 3040 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3041 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3042 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3043 return -EINVAL;
3044
7460fb4a 3045 process_nmi(vcpu);
3cfc3092
JK		 3046 vcpu->arch.exception.pending = events->exception.injected;
3047 vcpu->arch.exception.nr = events->exception.nr;
3048 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3049 vcpu->arch.exception.error_code = events->exception.error_code;
3050
3051 vcpu->arch.interrupt.pending = events->interrupt.injected;
3052 vcpu->arch.interrupt.nr = events->interrupt.nr;
3053 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3054 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3055 kvm_x86_ops->set_interrupt_shadow(vcpu,
3056 events->interrupt.shadow);
3cfc3092
JK		 3057
3058 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3059 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3060 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3061 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3062
66450a21
JK		 3063 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3064 kvm_vcpu_has_lapic(vcpu))
3065 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3066
3842d135
AK		 3067 kvm_make_request(KVM_REQ_EVENT, vcpu);
3068
3cfc3092
JK		 3069 return 0;
3070}
3071
a1efbe77
JK		 3072static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3073 struct kvm_debugregs *dbgregs)
3074{
73aaf249
JK		 3075 unsigned long val;
3076
a1efbe77 3077 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3078 _kvm_get_dr(vcpu, 6, &val);
3079 dbgregs->dr6 = val;
a1efbe77
JK		 3080 dbgregs->dr7 = vcpu->arch.dr7;
3081 dbgregs->flags = 0;
97e69aa6 3082 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3083}
3084
3085static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3086 struct kvm_debugregs *dbgregs)
3087{
3088 if (dbgregs->flags)
3089 return -EINVAL;
3090
a1efbe77
JK		 3091 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3092 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3093 kvm_update_dr6(vcpu);
a1efbe77 3094 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3095 kvm_update_dr7(vcpu);
a1efbe77 3096
a1efbe77
JK		 3097 return 0;
3098}
3099
2d5b5a66
SY		 3100static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3101 struct kvm_xsave *guest_xsave)
3102{
4344ee98 3103 if (cpu_has_xsave) {
2d5b5a66
SY		 3104 memcpy(guest_xsave->region,
3105 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3106 vcpu->arch.guest_xstate_size);
3107 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3108 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3109 } else {
2d5b5a66
SY		 3110 memcpy(guest_xsave->region,
3111 &vcpu->arch.guest_fpu.state->fxsave,
3112 sizeof(struct i387_fxsave_struct));
3113 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3114 XSTATE_FPSSE;
3115 }
3116}
3117
3118static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3119 struct kvm_xsave *guest_xsave)
3120{
3121 u64 xstate_bv =
3122 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3123
d7876f1b
PB		 3124 if (cpu_has_xsave) {
3125 /*
3126 * Here we allow setting states that are not present in
3127 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3128 * with old userspace.
3129 */
4ff41732 3130 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3131 return -EINVAL;
2d5b5a66 3132 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3133 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3134 } else {
2d5b5a66
SY		 3135 if (xstate_bv & ~XSTATE_FPSSE)
3136 return -EINVAL;
3137 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3138 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3139 }
3140 return 0;
3141}
3142
3143static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3144 struct kvm_xcrs *guest_xcrs)
3145{
3146 if (!cpu_has_xsave) {
3147 guest_xcrs->nr_xcrs = 0;
3148 return;
3149 }
3150
3151 guest_xcrs->nr_xcrs = 1;
3152 guest_xcrs->flags = 0;
3153 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3154 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3155}
3156
3157static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3158 struct kvm_xcrs *guest_xcrs)
3159{
3160 int i, r = 0;
3161
3162 if (!cpu_has_xsave)
3163 return -EINVAL;
3164
3165 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3166 return -EINVAL;
3167
3168 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3169 /* Only support XCR0 currently */
c67a04cb 3170 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3171 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3172 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3173 break;
3174 }
3175 if (r)
3176 r = -EINVAL;
3177 return r;
3178}
3179
1c0b28c2
EM		 3180/*
3181 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3182 * stopped by the hypervisor. This function will be called from the host only.
3183 * EINVAL is returned when the host attempts to set the flag for a guest that
3184 * does not support pv clocks.
3185 */
3186static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3187{
0b79459b 3188 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3189 return -EINVAL;
51d59c6b 3190 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3191 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3192 return 0;
3193}
3194
313a3dc7
CO		 3195long kvm_arch_vcpu_ioctl(struct file *filp,
3196 unsigned int ioctl, unsigned long arg)
3197{
3198 struct kvm_vcpu *vcpu = filp->private_data;
3199 void __user *argp = (void __user *)arg;
3200 int r;
d1ac91d8
AK		 3201 union {
3202 struct kvm_lapic_state *lapic;
3203 struct kvm_xsave *xsave;
3204 struct kvm_xcrs *xcrs;
3205 void *buffer;
3206 } u;
3207
3208 u.buffer = NULL;
313a3dc7
CO		 3209 switch (ioctl) {
3210 case KVM_GET_LAPIC: {
2204ae3c
MT		 3211 r = -EINVAL;
3212 if (!vcpu->arch.apic)
3213 goto out;
d1ac91d8 3214 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3215
b772ff36 3216 r = -ENOMEM;
d1ac91d8 3217 if (!u.lapic)
b772ff36 3218 goto out;
d1ac91d8 3219 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3220 if (r)
3221 goto out;
3222 r = -EFAULT;
d1ac91d8 3223 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3224 goto out;
3225 r = 0;
3226 break;
3227 }
3228 case KVM_SET_LAPIC: {
2204ae3c
MT		 3229 r = -EINVAL;
3230 if (!vcpu->arch.apic)
3231 goto out;
ff5c2c03 3232 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3233 if (IS_ERR(u.lapic))
3234 return PTR_ERR(u.lapic);
ff5c2c03 3235
d1ac91d8 3236 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3237 break;
3238 }
f77bc6a4
ZX		 3239 case KVM_INTERRUPT: {
3240 struct kvm_interrupt irq;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&irq, argp, sizeof irq))
3244 goto out;
3245 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3246 break;
3247 }
c4abb7c9
JK		 3248 case KVM_NMI: {
3249 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3250 break;
3251 }
313a3dc7
CO		 3252 case KVM_SET_CPUID: {
3253 struct kvm_cpuid __user *cpuid_arg = argp;
3254 struct kvm_cpuid cpuid;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3258 goto out;
3259 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3260 break;
3261 }
07716717
DK		 3262 case KVM_SET_CPUID2: {
3263 struct kvm_cpuid2 __user *cpuid_arg = argp;
3264 struct kvm_cpuid2 cpuid;
3265
3266 r = -EFAULT;
3267 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3268 goto out;
3269 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3270 cpuid_arg->entries);
07716717
DK		 3271 break;
3272 }
3273 case KVM_GET_CPUID2: {
3274 struct kvm_cpuid2 __user *cpuid_arg = argp;
3275 struct kvm_cpuid2 cpuid;
3276
3277 r = -EFAULT;
3278 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3279 goto out;
3280 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3281 cpuid_arg->entries);
07716717
DK		 3282 if (r)
3283 goto out;
3284 r = -EFAULT;
3285 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3286 goto out;
3287 r = 0;
3288 break;
3289 }
313a3dc7
CO		 3290 case KVM_GET_MSRS:
3291 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3292 break;
3293 case KVM_SET_MSRS:
3294 r = msr_io(vcpu, argp, do_set_msr, 0);
3295 break;
b209749f
AK		 3296 case KVM_TPR_ACCESS_REPORTING: {
3297 struct kvm_tpr_access_ctl tac;
3298
3299 r = -EFAULT;
3300 if (copy_from_user(&tac, argp, sizeof tac))
3301 goto out;
3302 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3303 if (r)
3304 goto out;
3305 r = -EFAULT;
3306 if (copy_to_user(argp, &tac, sizeof tac))
3307 goto out;
3308 r = 0;
3309 break;
3310 };
b93463aa
AK		 3311 case KVM_SET_VAPIC_ADDR: {
3312 struct kvm_vapic_addr va;
3313
3314 r = -EINVAL;
3315 if (!irqchip_in_kernel(vcpu->kvm))
3316 goto out;
3317 r = -EFAULT;
3318 if (copy_from_user(&va, argp, sizeof va))
3319 goto out;
fda4e2e8 3320 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3321 break;
3322 }
890ca9ae
HY		 3323 case KVM_X86_SETUP_MCE: {
3324 u64 mcg_cap;
3325
3326 r = -EFAULT;
3327 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3328 goto out;
3329 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3330 break;
3331 }
3332 case KVM_X86_SET_MCE: {
3333 struct kvm_x86_mce mce;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&mce, argp, sizeof mce))
3337 goto out;
3338 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3339 break;
3340 }
3cfc3092
JK		 3341 case KVM_GET_VCPU_EVENTS: {
3342 struct kvm_vcpu_events events;
3343
3344 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3345
3346 r = -EFAULT;
3347 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3348 break;
3349 r = 0;
3350 break;
3351 }
3352 case KVM_SET_VCPU_EVENTS: {
3353 struct kvm_vcpu_events events;
3354
3355 r = -EFAULT;
3356 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3357 break;
3358
3359 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3360 break;
3361 }
a1efbe77
JK		 3362 case KVM_GET_DEBUGREGS: {
3363 struct kvm_debugregs dbgregs;
3364
3365 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3366
3367 r = -EFAULT;
3368 if (copy_to_user(argp, &dbgregs,
3369 sizeof(struct kvm_debugregs)))
3370 break;
3371 r = 0;
3372 break;
3373 }
3374 case KVM_SET_DEBUGREGS: {
3375 struct kvm_debugregs dbgregs;
3376
3377 r = -EFAULT;
3378 if (copy_from_user(&dbgregs, argp,
3379 sizeof(struct kvm_debugregs)))
3380 break;
3381
3382 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3383 break;
3384 }
2d5b5a66 3385 case KVM_GET_XSAVE: {
d1ac91d8 3386 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3387 r = -ENOMEM;
d1ac91d8 3388 if (!u.xsave)
2d5b5a66
SY		 3389 break;
3390
d1ac91d8 3391 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3392
3393 r = -EFAULT;
d1ac91d8 3394 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3395 break;
3396 r = 0;
3397 break;
3398 }
3399 case KVM_SET_XSAVE: {
ff5c2c03 3400 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3401 if (IS_ERR(u.xsave))
3402 return PTR_ERR(u.xsave);
2d5b5a66 3403
d1ac91d8 3404 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3405 break;
3406 }
3407 case KVM_GET_XCRS: {
d1ac91d8 3408 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3409 r = -ENOMEM;
d1ac91d8 3410 if (!u.xcrs)
2d5b5a66
SY		 3411 break;
3412
d1ac91d8 3413 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3414
3415 r = -EFAULT;
d1ac91d8 3416 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3417 sizeof(struct kvm_xcrs)))
3418 break;
3419 r = 0;
3420 break;
3421 }
3422 case KVM_SET_XCRS: {
ff5c2c03 3423 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3424 if (IS_ERR(u.xcrs))
3425 return PTR_ERR(u.xcrs);
2d5b5a66 3426
d1ac91d8 3427 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3428 break;
3429 }
92a1f12d
JR		 3430 case KVM_SET_TSC_KHZ: {
3431 u32 user_tsc_khz;
3432
3433 r = -EINVAL;
92a1f12d
JR		 3434 user_tsc_khz = (u32)arg;
3435
3436 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3437 goto out;
3438
cc578287
ZA		 3439 if (user_tsc_khz == 0)
3440 user_tsc_khz = tsc_khz;
3441
3442 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3443
3444 r = 0;
3445 goto out;
3446 }
3447 case KVM_GET_TSC_KHZ: {
cc578287 3448 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3449 goto out;
3450 }
1c0b28c2
EM		 3451 case KVM_KVMCLOCK_CTRL: {
3452 r = kvm_set_guest_paused(vcpu);
3453 goto out;
3454 }
313a3dc7
CO		 3455 default:
3456 r = -EINVAL;
3457 }
3458out:
d1ac91d8 3459 kfree(u.buffer);
313a3dc7
CO		 3460 return r;
3461}
3462
5b1c1493
CO		 3463int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3464{
3465 return VM_FAULT_SIGBUS;
3466}
3467
1fe779f8
CO		 3468static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3469{
3470 int ret;
3471
3472 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3473 return -EINVAL;
1fe779f8
CO		 3474 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3475 return ret;
3476}
3477
b927a3ce
SY		 3478static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3479 u64 ident_addr)
3480{
3481 kvm->arch.ept_identity_map_addr = ident_addr;
3482 return 0;
3483}
3484
1fe779f8
CO		 3485static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3486 u32 kvm_nr_mmu_pages)
3487{
3488 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3489 return -EINVAL;
3490
79fac95e 3491 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3492
3493 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3494 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3495
79fac95e 3496 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3497 return 0;
3498}
3499
3500static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3501{
39de71ec 3502 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3503}
3504
1fe779f8
CO		 3505static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3506{
3507 int r;
3508
3509 r = 0;
3510 switch (chip->chip_id) {
3511 case KVM_IRQCHIP_PIC_MASTER:
3512 memcpy(&chip->chip.pic,
3513 &pic_irqchip(kvm)->pics[0],
3514 sizeof(struct kvm_pic_state));
3515 break;
3516 case KVM_IRQCHIP_PIC_SLAVE:
3517 memcpy(&chip->chip.pic,
3518 &pic_irqchip(kvm)->pics[1],
3519 sizeof(struct kvm_pic_state));
3520 break;
3521 case KVM_IRQCHIP_IOAPIC:
eba0226b 3522 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3523 break;
3524 default:
3525 r = -EINVAL;
3526 break;
3527 }
3528 return r;
3529}
3530
3531static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3532{
3533 int r;
3534
3535 r = 0;
3536 switch (chip->chip_id) {
3537 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3538 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3539 memcpy(&pic_irqchip(kvm)->pics[0],
3540 &chip->chip.pic,
3541 sizeof(struct kvm_pic_state));
f4f51050 3542 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3543 break;
3544 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3545 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3546 memcpy(&pic_irqchip(kvm)->pics[1],
3547 &chip->chip.pic,
3548 sizeof(struct kvm_pic_state));
f4f51050 3549 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3550 break;
3551 case KVM_IRQCHIP_IOAPIC:
eba0226b 3552 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3553 break;
3554 default:
3555 r = -EINVAL;
3556 break;
3557 }
3558 kvm_pic_update_irq(pic_irqchip(kvm));
3559 return r;
3560}
3561
e0f63cb9
SY		 3562static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3563{
3564 int r = 0;
3565
894a9c55 3566 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3567 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3569 return r;
3570}
3571
3572static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3573{
3574 int r = 0;
3575
894a9c55 3576 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3577 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3578 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3579 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3580 return r;
3581}
3582
3583static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3584{
3585 int r = 0;
3586
3587 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3588 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3589 sizeof(ps->channels));
3590 ps->flags = kvm->arch.vpit->pit_state.flags;
3591 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3592 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3593 return r;
3594}
3595
3596static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3597{
3598 int r = 0, start = 0;
3599 u32 prev_legacy, cur_legacy;
3600 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3601 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3602 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3603 if (!prev_legacy && cur_legacy)
3604 start = 1;
3605 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3606 sizeof(kvm->arch.vpit->pit_state.channels));
3607 kvm->arch.vpit->pit_state.flags = ps->flags;
3608 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3609 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3610 return r;
3611}
3612
52d939a0
MT		 3613static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3614 struct kvm_reinject_control *control)
3615{
3616 if (!kvm->arch.vpit)
3617 return -ENXIO;
894a9c55 3618 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3619 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3620 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3621 return 0;
3622}
3623
95d4c16c 3624/**
60c34612
TY		 3625 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3626 * @kvm: kvm instance
3627 * @log: slot id and address to which we copy the log
95d4c16c 3628 *
60c34612
TY		 3629 * We need to keep it in mind that VCPU threads can write to the bitmap
3630 * concurrently. So, to avoid losing data, we keep the following order for
3631 * each bit:
95d4c16c 3632 *
60c34612
TY		 3633 * 1. Take a snapshot of the bit and clear it if needed.
3634 * 2. Write protect the corresponding page.
3635 * 3. Flush TLB's if needed.
3636 * 4. Copy the snapshot to the userspace.
95d4c16c 3637 *
60c34612
TY		 3638 * Between 2 and 3, the guest may write to the page using the remaining TLB
3639 * entry. This is not a problem because the page will be reported dirty at
3640 * step 4 using the snapshot taken before and step 3 ensures that successive
3641 * writes will be logged for the next call.
5bb064dc 3642 */
60c34612 3643int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3644{
7850ac54 3645 int r;
5bb064dc 3646 struct kvm_memory_slot *memslot;
60c34612
TY		 3647 unsigned long n, i;
3648 unsigned long *dirty_bitmap;
3649 unsigned long *dirty_bitmap_buffer;
3650 bool is_dirty = false;
5bb064dc 3651
79fac95e 3652 mutex_lock(&kvm->slots_lock);
5bb064dc 3653
b050b015 3654 r = -EINVAL;
bbacc0c1 3655 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3656 goto out;
3657
28a37544 3658 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3659
3660 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3661 r = -ENOENT;
60c34612 3662 if (!dirty_bitmap)
b050b015
MT		 3663 goto out;
3664
87bf6e7d 3665 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3666
60c34612
TY		 3667 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3668 memset(dirty_bitmap_buffer, 0, n);
b050b015 3669
60c34612 3670 spin_lock(&kvm->mmu_lock);
b050b015 3671
60c34612
TY		 3672 for (i = 0; i < n / sizeof(long); i++) {
3673 unsigned long mask;
3674 gfn_t offset;
cdfca7b3 3675
60c34612
TY		 3676 if (!dirty_bitmap[i])
3677 continue;
b050b015 3678
60c34612 3679 is_dirty = true;
914ebccd 3680
60c34612
TY		 3681 mask = xchg(&dirty_bitmap[i], 0);
3682 dirty_bitmap_buffer[i] = mask;
edde99ce 3683
60c34612
TY		 3684 offset = i * BITS_PER_LONG;
3685 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3686 }
60c34612
TY		 3687
3688 spin_unlock(&kvm->mmu_lock);
3689
198c74f4
XG		 3690 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3691 lockdep_assert_held(&kvm->slots_lock);
3692
3693 /*
3694 * All the TLBs can be flushed out of mmu lock, see the comments in
3695 * kvm_mmu_slot_remove_write_access().
3696 */
3697 if (is_dirty)
3698 kvm_flush_remote_tlbs(kvm);
3699
60c34612
TY		 3700 r = -EFAULT;
3701 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3702 goto out;
b050b015 3703
5bb064dc
ZX		 3704 r = 0;
3705out:
79fac95e 3706 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3707 return r;
3708}
3709
aa2fbe6d
YZ		 3710int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3711 bool line_status)
23d43cf9
CD		 3712{
3713 if (!irqchip_in_kernel(kvm))
3714 return -ENXIO;
3715
3716 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3717 irq_event->irq, irq_event->level,
3718 line_status);
23d43cf9
CD		 3719 return 0;
3720}
3721
1fe779f8
CO		 3722long kvm_arch_vm_ioctl(struct file *filp,
3723 unsigned int ioctl, unsigned long arg)
3724{
3725 struct kvm *kvm = filp->private_data;
3726 void __user *argp = (void __user *)arg;
367e1319 3727 int r = -ENOTTY;
f0d66275
DH		 3728 /*
3729 * This union makes it completely explicit to gcc-3.x
3730 * that these two variables' stack usage should be
3731 * combined, not added together.
3732 */
3733 union {
3734 struct kvm_pit_state ps;
e9f42757 3735 struct kvm_pit_state2 ps2;
c5ff41ce 3736 struct kvm_pit_config pit_config;
f0d66275 3737 } u;
1fe779f8
CO		 3738
3739 switch (ioctl) {
3740 case KVM_SET_TSS_ADDR:
3741 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3742 break;
b927a3ce
SY		 3743 case KVM_SET_IDENTITY_MAP_ADDR: {
3744 u64 ident_addr;
3745
3746 r = -EFAULT;
3747 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3748 goto out;
3749 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3750 break;
3751 }
1fe779f8
CO		 3752 case KVM_SET_NR_MMU_PAGES:
3753 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3754 break;
3755 case KVM_GET_NR_MMU_PAGES:
3756 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3757 break;
3ddea128
MT		 3758 case KVM_CREATE_IRQCHIP: {
3759 struct kvm_pic *vpic;
3760
3761 mutex_lock(&kvm->lock);
3762 r = -EEXIST;
3763 if (kvm->arch.vpic)
3764 goto create_irqchip_unlock;
3e515705
AK		 3765 r = -EINVAL;
3766 if (atomic_read(&kvm->online_vcpus))
3767 goto create_irqchip_unlock;
1fe779f8 3768 r = -ENOMEM;
3ddea128
MT		 3769 vpic = kvm_create_pic(kvm);
3770 if (vpic) {
1fe779f8
CO		 3771 r = kvm_ioapic_init(kvm);
3772 if (r) {
175504cd 3773 mutex_lock(&kvm->slots_lock);
72bb2fcd 3774 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3775 &vpic->dev_master);
3776 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3777 &vpic->dev_slave);
3778 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3779 &vpic->dev_eclr);
175504cd 3780 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3781 kfree(vpic);
3782 goto create_irqchip_unlock;
1fe779f8
CO		 3783 }
3784 } else
3ddea128
MT		 3785 goto create_irqchip_unlock;
3786 smp_wmb();
3787 kvm->arch.vpic = vpic;
3788 smp_wmb();
399ec807
AK		 3789 r = kvm_setup_default_irq_routing(kvm);
3790 if (r) {
175504cd 3791 mutex_lock(&kvm->slots_lock);
3ddea128 3792 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3793 kvm_ioapic_destroy(kvm);
3794 kvm_destroy_pic(kvm);
3ddea128 3795 mutex_unlock(&kvm->irq_lock);
175504cd 3796 mutex_unlock(&kvm->slots_lock);
399ec807 3797 }
3ddea128
MT		 3798 create_irqchip_unlock:
3799 mutex_unlock(&kvm->lock);
1fe779f8 3800 break;
3ddea128 3801 }
7837699f 3802 case KVM_CREATE_PIT:
c5ff41ce
JK		 3803 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3804 goto create_pit;
3805 case KVM_CREATE_PIT2:
3806 r = -EFAULT;
3807 if (copy_from_user(&u.pit_config, argp,
3808 sizeof(struct kvm_pit_config)))
3809 goto out;
3810 create_pit:
79fac95e 3811 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3812 r = -EEXIST;
3813 if (kvm->arch.vpit)
3814 goto create_pit_unlock;
7837699f 3815 r = -ENOMEM;
c5ff41ce 3816 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3817 if (kvm->arch.vpit)
3818 r = 0;
269e05e4 3819 create_pit_unlock:
79fac95e 3820 mutex_unlock(&kvm->slots_lock);
7837699f 3821 break;
1fe779f8
CO		 3822 case KVM_GET_IRQCHIP: {
3823 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3824 struct kvm_irqchip *chip;
1fe779f8 3825
ff5c2c03
SL		 3826 chip = memdup_user(argp, sizeof(*chip));
3827 if (IS_ERR(chip)) {
3828 r = PTR_ERR(chip);
1fe779f8 3829 goto out;
ff5c2c03
SL		 3830 }
3831
1fe779f8
CO		 3832 r = -ENXIO;
3833 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3834 goto get_irqchip_out;
3835 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3836 if (r)
f0d66275 3837 goto get_irqchip_out;
1fe779f8 3838 r = -EFAULT;
f0d66275
DH		 3839 if (copy_to_user(argp, chip, sizeof *chip))
3840 goto get_irqchip_out;
1fe779f8 3841 r = 0;
f0d66275
DH		 3842 get_irqchip_out:
3843 kfree(chip);
1fe779f8
CO		 3844 break;
3845 }
3846 case KVM_SET_IRQCHIP: {
3847 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3848 struct kvm_irqchip *chip;
1fe779f8 3849
ff5c2c03
SL		 3850 chip = memdup_user(argp, sizeof(*chip));
3851 if (IS_ERR(chip)) {
3852 r = PTR_ERR(chip);
1fe779f8 3853 goto out;
ff5c2c03
SL		 3854 }
3855
1fe779f8
CO		 3856 r = -ENXIO;
3857 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3858 goto set_irqchip_out;
3859 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3860 if (r)
f0d66275 3861 goto set_irqchip_out;
1fe779f8 3862 r = 0;
f0d66275
DH		 3863 set_irqchip_out:
3864 kfree(chip);
1fe779f8
CO		 3865 break;
3866 }
e0f63cb9 3867 case KVM_GET_PIT: {
e0f63cb9 3868 r = -EFAULT;
f0d66275 3869 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3870 goto out;
3871 r = -ENXIO;
3872 if (!kvm->arch.vpit)
3873 goto out;
f0d66275 3874 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3875 if (r)
3876 goto out;
3877 r = -EFAULT;
f0d66275 3878 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3879 goto out;
3880 r = 0;
3881 break;
3882 }
3883 case KVM_SET_PIT: {
e0f63cb9 3884 r = -EFAULT;
f0d66275 3885 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3886 goto out;
3887 r = -ENXIO;
3888 if (!kvm->arch.vpit)
3889 goto out;
f0d66275 3890 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3891 break;
3892 }
e9f42757
BK		 3893 case KVM_GET_PIT2: {
3894 r = -ENXIO;
3895 if (!kvm->arch.vpit)
3896 goto out;
3897 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3898 if (r)
3899 goto out;
3900 r = -EFAULT;
3901 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3902 goto out;
3903 r = 0;
3904 break;
3905 }
3906 case KVM_SET_PIT2: {
3907 r = -EFAULT;
3908 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3909 goto out;
3910 r = -ENXIO;
3911 if (!kvm->arch.vpit)
3912 goto out;
3913 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3914 break;
3915 }
52d939a0
MT		 3916 case KVM_REINJECT_CONTROL: {
3917 struct kvm_reinject_control control;
3918 r = -EFAULT;
3919 if (copy_from_user(&control, argp, sizeof(control)))
3920 goto out;
3921 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3922 break;
3923 }
ffde22ac
ES		 3924 case KVM_XEN_HVM_CONFIG: {
3925 r = -EFAULT;
3926 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3927 sizeof(struct kvm_xen_hvm_config)))
3928 goto out;
3929 r = -EINVAL;
3930 if (kvm->arch.xen_hvm_config.flags)
3931 goto out;
3932 r = 0;
3933 break;
3934 }
afbcf7ab 3935 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3936 struct kvm_clock_data user_ns;
3937 u64 now_ns;
3938 s64 delta;
3939
3940 r = -EFAULT;
3941 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3942 goto out;
3943
3944 r = -EINVAL;
3945 if (user_ns.flags)
3946 goto out;
3947
3948 r = 0;
395c6b0a 3949 local_irq_disable();
759379dd 3950 now_ns = get_kernel_ns();
afbcf7ab 3951 delta = user_ns.clock - now_ns;
395c6b0a 3952 local_irq_enable();
afbcf7ab 3953 kvm->arch.kvmclock_offset = delta;
2e762ff7 3954 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3955 break;
3956 }
3957 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3958 struct kvm_clock_data user_ns;
3959 u64 now_ns;
3960
395c6b0a 3961 local_irq_disable();
759379dd 3962 now_ns = get_kernel_ns();
afbcf7ab 3963 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3964 local_irq_enable();
afbcf7ab 3965 user_ns.flags = 0;
97e69aa6 3966 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3967
3968 r = -EFAULT;
3969 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3970 goto out;
3971 r = 0;
3972 break;
3973 }
3974
1fe779f8
CO		 3975 default:
3976 ;
3977 }
3978out:
3979 return r;
3980}
3981
a16b043c 3982static void kvm_init_msr_list(void)
043405e1
CO		 3983{
3984 u32 dummy[2];
3985 unsigned i, j;
3986
e3267cbb
GC		 3987 /* skip the first msrs in the list. KVM-specific */
3988 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3989 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3990 continue;
93c4adc7
PB		 3991
3992 /*
3993 * Even MSRs that are valid in the host may not be exposed
3994 * to the guests in some cases. We could work around this
3995 * in VMX with the generic MSR save/load machinery, but it
3996 * is not really worthwhile since it will really only
3997 * happen with nested virtualization.
3998 */
3999 switch (msrs_to_save[i]) {
4000 case MSR_IA32_BNDCFGS:
4001 if (!kvm_x86_ops->mpx_supported())
4002 continue;
4003 break;
4004 default:
4005 break;
4006 }
4007
043405e1
CO		 4008 if (j < i)
4009 msrs_to_save[j] = msrs_to_save[i];
4010 j++;
4011 }
4012 num_msrs_to_save = j;
4013}
4014
bda9020e
MT		 4015static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4016 const void *v)
bbd9b64e 4017{
70252a10
AK		 4018 int handled = 0;
4019 int n;
4020
4021 do {
4022 n = min(len, 8);
4023 if (!(vcpu->arch.apic &&
4024 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4025 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4026 break;
4027 handled += n;
4028 addr += n;
4029 len -= n;
4030 v += n;
4031 } while (len);
bbd9b64e 4032
70252a10 4033 return handled;
bbd9b64e
CO		 4034}
4035
bda9020e 4036static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4037{
70252a10
AK		 4038 int handled = 0;
4039 int n;
4040
4041 do {
4042 n = min(len, 8);
4043 if (!(vcpu->arch.apic &&
4044 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4045 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4046 break;
4047 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4048 handled += n;
4049 addr += n;
4050 len -= n;
4051 v += n;
4052 } while (len);
bbd9b64e 4053
70252a10 4054 return handled;
bbd9b64e
CO		 4055}
4056
2dafc6c2
GN		 4057static void kvm_set_segment(struct kvm_vcpu *vcpu,
4058 struct kvm_segment *var, int seg)
4059{
4060 kvm_x86_ops->set_segment(vcpu, var, seg);
4061}
4062
4063void kvm_get_segment(struct kvm_vcpu *vcpu,
4064 struct kvm_segment *var, int seg)
4065{
4066 kvm_x86_ops->get_segment(vcpu, var, seg);
4067}
4068
54987b7a
PB		 4069gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4070 struct x86_exception *exception)
02f59dc9
JR		 4071{
4072 gpa_t t_gpa;
02f59dc9
JR		 4073
4074 BUG_ON(!mmu_is_nested(vcpu));
4075
4076 /* NPT walks are always user-walks */
4077 access |= PFERR_USER_MASK;
54987b7a 4078 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4079
4080 return t_gpa;
4081}
4082
ab9ae313
AK		 4083gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4084 struct x86_exception *exception)
1871c602
GN		 4085{
4086 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4087 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4088}
4089
ab9ae313
AK		 4090 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4091 struct x86_exception *exception)
1871c602
GN		 4092{
4093 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4094 access |= PFERR_FETCH_MASK;
ab9ae313 4095 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4096}
4097
ab9ae313
AK		 4098gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4099 struct x86_exception *exception)
1871c602
GN		 4100{
4101 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4102 access |= PFERR_WRITE_MASK;
ab9ae313 4103 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4104}
4105
4106/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4107gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4108 struct x86_exception *exception)
1871c602 4109{
ab9ae313 4110 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4111}
4112
4113static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4114 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4115 struct x86_exception *exception)
bbd9b64e
CO		 4116{
4117 void *data = val;
10589a46 4118 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4119
4120 while (bytes) {
14dfe855 4121 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4122 exception);
bbd9b64e 4123 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4124 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4125 int ret;
4126
bcc55cba 4127 if (gpa == UNMAPPED_GVA)
ab9ae313 4128 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4129 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4130 offset, toread);
10589a46 4131 if (ret < 0) {
c3cd7ffa 4132 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4133 goto out;
4134 }
bbd9b64e 4135
77c2002e
IE		 4136 bytes -= toread;
4137 data += toread;
4138 addr += toread;
bbd9b64e 4139 }
10589a46 4140out:
10589a46 4141 return r;
bbd9b64e 4142}
77c2002e 4143
1871c602 4144/* used for instruction fetching */
0f65dd70
AK		 4145static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4146 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4147 struct x86_exception *exception)
1871c602 4148{
0f65dd70 4149 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4150 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4151 unsigned offset;
4152 int ret;
0f65dd70 4153
44583cba
PB		 4154 /* Inline kvm_read_guest_virt_helper for speed. */
4155 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4156 exception);
4157 if (unlikely(gpa == UNMAPPED_GVA))
4158 return X86EMUL_PROPAGATE_FAULT;
4159
4160 offset = addr & (PAGE_SIZE-1);
4161 if (WARN_ON(offset + bytes > PAGE_SIZE))
4162 bytes = (unsigned)PAGE_SIZE - offset;
4163 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4164 offset, bytes);
4165 if (unlikely(ret < 0))
4166 return X86EMUL_IO_NEEDED;
4167
4168 return X86EMUL_CONTINUE;
1871c602
GN		 4169}
4170
064aea77 4171int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4172 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4173 struct x86_exception *exception)
1871c602 4174{
0f65dd70 4175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4176 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4177
1871c602 4178 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4179 exception);
1871c602 4180}
064aea77 4181EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4182
0f65dd70
AK		 4183static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4184 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4185 struct x86_exception *exception)
1871c602 4186{
0f65dd70 4187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4188 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4189}
4190
6a4d7550 4191int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4192 gva_t addr, void *val,
2dafc6c2 4193 unsigned int bytes,
bcc55cba 4194 struct x86_exception *exception)
77c2002e 4195{
0f65dd70 4196 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4197 void *data = val;
4198 int r = X86EMUL_CONTINUE;
4199
4200 while (bytes) {
14dfe855
JR		 4201 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4202 PFERR_WRITE_MASK,
ab9ae313 4203 exception);
77c2002e
IE		 4204 unsigned offset = addr & (PAGE_SIZE-1);
4205 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4206 int ret;
4207
bcc55cba 4208 if (gpa == UNMAPPED_GVA)
ab9ae313 4209 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4210 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4211 if (ret < 0) {
c3cd7ffa 4212 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4213 goto out;
4214 }
4215
4216 bytes -= towrite;
4217 data += towrite;
4218 addr += towrite;
4219 }
4220out:
4221 return r;
4222}
6a4d7550 4223EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4224
af7cc7d1
XG		 4225static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4226 gpa_t *gpa, struct x86_exception *exception,
4227 bool write)
4228{
97d64b78
AK		 4229 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4230 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4231
97d64b78 4232 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4233 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4234 vcpu->arch.access, access)) {
bebb106a
XG		 4235 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4236 (gva & (PAGE_SIZE - 1));
4f022648 4237 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4238 return 1;
4239 }
4240
af7cc7d1
XG		 4241 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4242
4243 if (*gpa == UNMAPPED_GVA)
4244 return -1;
4245
4246 /* For APIC access vmexit */
4247 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4248 return 1;
4249
4f022648
XG		 4250 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4251 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4252 return 1;
4f022648 4253 }
bebb106a 4254
af7cc7d1
XG		 4255 return 0;
4256}
4257
3200f405 4258int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4259 const void *val, int bytes)
bbd9b64e
CO		 4260{
4261 int ret;
4262
4263 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4264 if (ret < 0)
bbd9b64e 4265 return 0;
f57f2ef5 4266 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4267 return 1;
4268}
4269
77d197b2
XG		 4270struct read_write_emulator_ops {
4271 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4272 int bytes);
4273 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4274 void *val, int bytes);
4275 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4276 int bytes, void *val);
4277 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4278 void *val, int bytes);
4279 bool write;
4280};
4281
4282static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4283{
4284 if (vcpu->mmio_read_completed) {
77d197b2 4285 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4286 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4287 vcpu->mmio_read_completed = 0;
4288 return 1;
4289 }
4290
4291 return 0;
4292}
4293
4294static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4295 void *val, int bytes)
4296{
4297 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4298}
4299
4300static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4301 void *val, int bytes)
4302{
4303 return emulator_write_phys(vcpu, gpa, val, bytes);
4304}
4305
4306static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4307{
4308 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4309 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4310}
4311
4312static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4313 void *val, int bytes)
4314{
4315 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4316 return X86EMUL_IO_NEEDED;
4317}
4318
4319static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4320 void *val, int bytes)
4321{
f78146b0
AK		 4322 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4323
87da7e66 4324 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4325 return X86EMUL_CONTINUE;
4326}
4327
0fbe9b0b 4328static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4329 .read_write_prepare = read_prepare,
4330 .read_write_emulate = read_emulate,
4331 .read_write_mmio = vcpu_mmio_read,
4332 .read_write_exit_mmio = read_exit_mmio,
4333};
4334
0fbe9b0b 4335static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4336 .read_write_emulate = write_emulate,
4337 .read_write_mmio = write_mmio,
4338 .read_write_exit_mmio = write_exit_mmio,
4339 .write = true,
4340};
4341
22388a3c
XG		 4342static int emulator_read_write_onepage(unsigned long addr, void *val,
4343 unsigned int bytes,
4344 struct x86_exception *exception,
4345 struct kvm_vcpu *vcpu,
0fbe9b0b 4346 const struct read_write_emulator_ops *ops)
bbd9b64e 4347{
af7cc7d1
XG		 4348 gpa_t gpa;
4349 int handled, ret;
22388a3c 4350 bool write = ops->write;
f78146b0 4351 struct kvm_mmio_fragment *frag;
10589a46 4352
22388a3c 4353 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4354
af7cc7d1 4355 if (ret < 0)
bbd9b64e 4356 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4357
4358 /* For APIC access vmexit */
af7cc7d1 4359 if (ret)
bbd9b64e
CO		 4360 goto mmio;
4361
22388a3c 4362 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4363 return X86EMUL_CONTINUE;
4364
4365mmio:
4366 /*
4367 * Is this MMIO handled locally?
4368 */
22388a3c 4369 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4370 if (handled == bytes)
bbd9b64e 4371 return X86EMUL_CONTINUE;
bbd9b64e 4372
70252a10
AK		 4373 gpa += handled;
4374 bytes -= handled;
4375 val += handled;
4376
87da7e66
XG		 4377 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4378 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4379 frag->gpa = gpa;
4380 frag->data = val;
4381 frag->len = bytes;
f78146b0 4382 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4383}
4384
22388a3c
XG		 4385int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4386 void *val, unsigned int bytes,
4387 struct x86_exception *exception,
0fbe9b0b 4388 const struct read_write_emulator_ops *ops)
bbd9b64e 4389{
0f65dd70 4390 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4391 gpa_t gpa;
4392 int rc;
4393
4394 if (ops->read_write_prepare &&
4395 ops->read_write_prepare(vcpu, val, bytes))
4396 return X86EMUL_CONTINUE;
4397
4398 vcpu->mmio_nr_fragments = 0;
0f65dd70 4399
bbd9b64e
CO		 4400 /* Crossing a page boundary? */
4401 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4402 int now;
bbd9b64e
CO		 4403
4404 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4405 rc = emulator_read_write_onepage(addr, val, now, exception,
4406 vcpu, ops);
4407
bbd9b64e
CO		 4408 if (rc != X86EMUL_CONTINUE)
4409 return rc;
4410 addr += now;
4411 val += now;
4412 bytes -= now;
4413 }
22388a3c 4414
f78146b0
AK		 4415 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4416 vcpu, ops);
4417 if (rc != X86EMUL_CONTINUE)
4418 return rc;
4419
4420 if (!vcpu->mmio_nr_fragments)
4421 return rc;
4422
4423 gpa = vcpu->mmio_fragments[0].gpa;
4424
4425 vcpu->mmio_needed = 1;
4426 vcpu->mmio_cur_fragment = 0;
4427
87da7e66 4428 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4429 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4430 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4431 vcpu->run->mmio.phys_addr = gpa;
4432
4433 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4434}
4435
4436static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4437 unsigned long addr,
4438 void *val,
4439 unsigned int bytes,
4440 struct x86_exception *exception)
4441{
4442 return emulator_read_write(ctxt, addr, val, bytes,
4443 exception, &read_emultor);
4444}
4445
4446int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4447 unsigned long addr,
4448 const void *val,
4449 unsigned int bytes,
4450 struct x86_exception *exception)
4451{
4452 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4453 exception, &write_emultor);
bbd9b64e 4454}
bbd9b64e 4455
daea3e73
AK		 4456#define CMPXCHG_TYPE(t, ptr, old, new) \
4457 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4458
4459#ifdef CONFIG_X86_64
4460# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4461#else
4462# define CMPXCHG64(ptr, old, new) \
9749a6c0 4463 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4464#endif
4465
0f65dd70
AK		 4466static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4467 unsigned long addr,
bbd9b64e
CO		 4468 const void *old,
4469 const void *new,
4470 unsigned int bytes,
0f65dd70 4471 struct x86_exception *exception)
bbd9b64e 4472{
0f65dd70 4473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4474 gpa_t gpa;
4475 struct page *page;
4476 char *kaddr;
4477 bool exchanged;
2bacc55c 4478
daea3e73
AK		 4479 /* guests cmpxchg8b have to be emulated atomically */
4480 if (bytes > 8 || (bytes & (bytes - 1)))
4481 goto emul_write;
10589a46 4482
daea3e73 4483 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4484
daea3e73
AK		 4485 if (gpa == UNMAPPED_GVA ||
4486 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4487 goto emul_write;
2bacc55c 4488
daea3e73
AK		 4489 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4490 goto emul_write;
72dc67a6 4491
daea3e73 4492 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4493 if (is_error_page(page))
c19b8bd6 4494 goto emul_write;
72dc67a6 4495
8fd75e12 4496 kaddr = kmap_atomic(page);
daea3e73
AK		 4497 kaddr += offset_in_page(gpa);
4498 switch (bytes) {
4499 case 1:
4500 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4501 break;
4502 case 2:
4503 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4504 break;
4505 case 4:
4506 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4507 break;
4508 case 8:
4509 exchanged = CMPXCHG64(kaddr, old, new);
4510 break;
4511 default:
4512 BUG();
2bacc55c 4513 }
8fd75e12 4514 kunmap_atomic(kaddr);
daea3e73
AK		 4515 kvm_release_page_dirty(page);
4516
4517 if (!exchanged)
4518 return X86EMUL_CMPXCHG_FAILED;
4519
d3714010 4520 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4521 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4522
4523 return X86EMUL_CONTINUE;
4a5f48f6 4524
3200f405 4525emul_write:
daea3e73 4526 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4527
0f65dd70 4528 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4529}
4530
cf8f70bf
GN		 4531static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4532{
4533 /* TODO: String I/O for in kernel device */
4534 int r;
4535
4536 if (vcpu->arch.pio.in)
4537 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4538 vcpu->arch.pio.size, pd);
4539 else
4540 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4541 vcpu->arch.pio.port, vcpu->arch.pio.size,
4542 pd);
4543 return r;
4544}
4545
6f6fbe98
XG		 4546static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4547 unsigned short port, void *val,
4548 unsigned int count, bool in)
cf8f70bf 4549{
cf8f70bf 4550 vcpu->arch.pio.port = port;
6f6fbe98 4551 vcpu->arch.pio.in = in;
7972995b 4552 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4553 vcpu->arch.pio.size = size;
4554
4555 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4556 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4557 return 1;
4558 }
4559
4560 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4561 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4562 vcpu->run->io.size = size;
4563 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4564 vcpu->run->io.count = count;
4565 vcpu->run->io.port = port;
4566
4567 return 0;
4568}
4569
6f6fbe98
XG		 4570static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4571 int size, unsigned short port, void *val,
4572 unsigned int count)
cf8f70bf 4573{
ca1d4a9e 4574 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4575 int ret;
ca1d4a9e 4576
6f6fbe98
XG		 4577 if (vcpu->arch.pio.count)
4578 goto data_avail;
cf8f70bf 4579
6f6fbe98
XG		 4580 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4581 if (ret) {
4582data_avail:
4583 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4584 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4585 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4586 return 1;
4587 }
4588
cf8f70bf
GN		 4589 return 0;
4590}
4591
6f6fbe98
XG		 4592static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4593 int size, unsigned short port,
4594 const void *val, unsigned int count)
4595{
4596 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4597
4598 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4599 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4600 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4601}
4602
bbd9b64e
CO		 4603static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4604{
4605 return kvm_x86_ops->get_segment_base(vcpu, seg);
4606}
4607
3cb16fe7 4608static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4609{
3cb16fe7 4610 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4611}
4612
f5f48ee1
SY		 4613int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4614{
4615 if (!need_emulate_wbinvd(vcpu))
4616 return X86EMUL_CONTINUE;
4617
4618 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4619 int cpu = get_cpu();
4620
4621 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4622 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4623 wbinvd_ipi, NULL, 1);
2eec7343 4624 put_cpu();
f5f48ee1 4625 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4626 } else
4627 wbinvd();
f5f48ee1
SY		 4628 return X86EMUL_CONTINUE;
4629}
4630EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4631
bcaf5cc5
AK		 4632static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4633{
4634 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4635}
4636
717746e3 4637int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4638{
717746e3 4639 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4640}
4641
717746e3 4642int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4643{
338dbc97 4644
717746e3 4645 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4646}
4647
52a46617 4648static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4649{
52a46617 4650 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4651}
4652
717746e3 4653static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4654{
717746e3 4655 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4656 unsigned long value;
4657
4658 switch (cr) {
4659 case 0:
4660 value = kvm_read_cr0(vcpu);
4661 break;
4662 case 2:
4663 value = vcpu->arch.cr2;
4664 break;
4665 case 3:
9f8fe504 4666 value = kvm_read_cr3(vcpu);
52a46617
GN		 4667 break;
4668 case 4:
4669 value = kvm_read_cr4(vcpu);
4670 break;
4671 case 8:
4672 value = kvm_get_cr8(vcpu);
4673 break;
4674 default:
a737f256 4675 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4676 return 0;
4677 }
4678
4679 return value;
4680}
4681
717746e3 4682static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4683{
717746e3 4684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4685 int res = 0;
4686
52a46617
GN		 4687 switch (cr) {
4688 case 0:
49a9b07e 4689 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4690 break;
4691 case 2:
4692 vcpu->arch.cr2 = val;
4693 break;
4694 case 3:
2390218b 4695 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4696 break;
4697 case 4:
a83b29c6 4698 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4699 break;
4700 case 8:
eea1cff9 4701 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4702 break;
4703 default:
a737f256 4704 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4705 res = -1;
52a46617 4706 }
0f12244f
GN		 4707
4708 return res;
52a46617
GN		 4709}
4710
717746e3 4711static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4712{
717746e3 4713 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4714}
4715
4bff1e86 4716static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4717{
4bff1e86 4718 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4719}
4720
4bff1e86 4721static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4722{
4bff1e86 4723 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4724}
4725
1ac9d0cf
AK		 4726static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4727{
4728 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4729}
4730
4731static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4732{
4733 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4734}
4735
4bff1e86
AK		 4736static unsigned long emulator_get_cached_segment_base(
4737 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4738{
4bff1e86 4739 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4740}
4741
1aa36616
AK		 4742static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4743 struct desc_struct *desc, u32 *base3,
4744 int seg)
2dafc6c2
GN		 4745{
4746 struct kvm_segment var;
4747
4bff1e86 4748 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4749 *selector = var.selector;
2dafc6c2 4750
378a8b09
GN		 4751 if (var.unusable) {
4752 memset(desc, 0, sizeof(*desc));
2dafc6c2 4753 return false;
378a8b09 4754 }
2dafc6c2
GN		 4755
4756 if (var.g)
4757 var.limit >>= 12;
4758 set_desc_limit(desc, var.limit);
4759 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4760#ifdef CONFIG_X86_64
4761 if (base3)
4762 *base3 = var.base >> 32;
4763#endif
2dafc6c2
GN		 4764 desc->type = var.type;
4765 desc->s = var.s;
4766 desc->dpl = var.dpl;
4767 desc->p = var.present;
4768 desc->avl = var.avl;
4769 desc->l = var.l;
4770 desc->d = var.db;
4771 desc->g = var.g;
4772
4773 return true;
4774}
4775
1aa36616
AK		 4776static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4777 struct desc_struct *desc, u32 base3,
4778 int seg)
2dafc6c2 4779{
4bff1e86 4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4781 struct kvm_segment var;
4782
1aa36616 4783 var.selector = selector;
2dafc6c2 4784 var.base = get_desc_base(desc);
5601d05b
GN		 4785#ifdef CONFIG_X86_64
4786 var.base |= ((u64)base3) << 32;
4787#endif
2dafc6c2
GN		 4788 var.limit = get_desc_limit(desc);
4789 if (desc->g)
4790 var.limit = (var.limit << 12) | 0xfff;
4791 var.type = desc->type;
2dafc6c2
GN		 4792 var.dpl = desc->dpl;
4793 var.db = desc->d;
4794 var.s = desc->s;
4795 var.l = desc->l;
4796 var.g = desc->g;
4797 var.avl = desc->avl;
4798 var.present = desc->p;
4799 var.unusable = !var.present;
4800 var.padding = 0;
4801
4802 kvm_set_segment(vcpu, &var, seg);
4803 return;
4804}
4805
717746e3
AK		 4806static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4807 u32 msr_index, u64 *pdata)
4808{
4809 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4810}
4811
4812static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4813 u32 msr_index, u64 data)
4814{
8fe8ab46
WA		 4815 struct msr_data msr;
4816
4817 msr.data = data;
4818 msr.index = msr_index;
4819 msr.host_initiated = false;
4820 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4821}
4822
67f4d428
NA		 4823static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4824 u32 pmc)
4825{
4826 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4827}
4828
222d21aa
AK		 4829static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4830 u32 pmc, u64 *pdata)
4831{
4832 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4833}
4834
6c3287f7
AK		 4835static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4836{
4837 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4838}
4839
5037f6f3
AK		 4840static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4841{
4842 preempt_disable();
5197b808 4843 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4844 /*
4845 * CR0.TS may reference the host fpu state, not the guest fpu state,
4846 * so it may be clear at this point.
4847 */
4848 clts();
4849}
4850
4851static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4852{
4853 preempt_enable();
4854}
4855
2953538e 4856static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4857 struct x86_instruction_info *info,
c4f035c6
AK		 4858 enum x86_intercept_stage stage)
4859{
2953538e 4860 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4861}
4862
0017f93a 4863static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4864 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4865{
0017f93a 4866 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4867}
4868
dd856efa
AK		 4869static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4870{
4871 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4872}
4873
4874static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4875{
4876 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4877}
4878
0225fb50 4879static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4880 .read_gpr = emulator_read_gpr,
4881 .write_gpr = emulator_write_gpr,
1871c602 4882 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4883 .write_std = kvm_write_guest_virt_system,
1871c602 4884 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4885 .read_emulated = emulator_read_emulated,
4886 .write_emulated = emulator_write_emulated,
4887 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4888 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4889 .pio_in_emulated = emulator_pio_in_emulated,
4890 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4891 .get_segment = emulator_get_segment,
4892 .set_segment = emulator_set_segment,
5951c442 4893 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4894 .get_gdt = emulator_get_gdt,
160ce1f1 4895 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4896 .set_gdt = emulator_set_gdt,
4897 .set_idt = emulator_set_idt,
52a46617
GN		 4898 .get_cr = emulator_get_cr,
4899 .set_cr = emulator_set_cr,
9c537244 4900 .cpl = emulator_get_cpl,
35aa5375
GN		 4901 .get_dr = emulator_get_dr,
4902 .set_dr = emulator_set_dr,
717746e3
AK		 4903 .set_msr = emulator_set_msr,
4904 .get_msr = emulator_get_msr,
67f4d428 4905 .check_pmc = emulator_check_pmc,
222d21aa 4906 .read_pmc = emulator_read_pmc,
6c3287f7 4907 .halt = emulator_halt,
bcaf5cc5 4908 .wbinvd = emulator_wbinvd,
d6aa1000 4909 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4910 .get_fpu = emulator_get_fpu,
4911 .put_fpu = emulator_put_fpu,
c4f035c6 4912 .intercept = emulator_intercept,
bdb42f5a 4913 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4914};
4915
95cb2295
GN		 4916static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4917{
37ccdcbe 4918 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4919 /*
4920 * an sti; sti; sequence only disable interrupts for the first
4921 * instruction. So, if the last instruction, be it emulated or
4922 * not, left the system with the INT_STI flag enabled, it
4923 * means that the last instruction is an sti. We should not
4924 * leave the flag on in this case. The same goes for mov ss
4925 */
37ccdcbe
PB		 4926 if (int_shadow & mask)
4927 mask = 0;
6addfc42 4928 if (unlikely(int_shadow || mask)) {
95cb2295 4929 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4930 if (!mask)
4931 kvm_make_request(KVM_REQ_EVENT, vcpu);
4932 }
95cb2295
GN		 4933}
4934
ef54bcfe 4935static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4936{
4937 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4938 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4939 return kvm_propagate_fault(vcpu, &ctxt->exception);
4940
4941 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4942 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4943 ctxt->exception.error_code);
54b8486f 4944 else
da9cb575 4945 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4946 return false;
54b8486f
GN		 4947}
4948
8ec4722d
MG		 4949static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4950{
adf52235 4951 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4952 int cs_db, cs_l;
4953
8ec4722d
MG		 4954 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4955
adf52235
TY		 4956 ctxt->eflags = kvm_get_rflags(vcpu);
4957 ctxt->eip = kvm_rip_read(vcpu);
4958 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4959 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4960 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4961 cs_db ? X86EMUL_MODE_PROT32 :
4962 X86EMUL_MODE_PROT16;
4963 ctxt->guest_mode = is_guest_mode(vcpu);
4964
dd856efa 4965 init_decode_cache(ctxt);
7ae441ea 4966 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4967}
4968
71f9833b 4969int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4970{
9d74191a 4971 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4972 int ret;
4973
4974 init_emulate_ctxt(vcpu);
4975
9dac77fa
AK		 4976 ctxt->op_bytes = 2;
4977 ctxt->ad_bytes = 2;
4978 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4979 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4980
4981 if (ret != X86EMUL_CONTINUE)
4982 return EMULATE_FAIL;
4983
9dac77fa 4984 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4985 kvm_rip_write(vcpu, ctxt->eip);
4986 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4987
4988 if (irq == NMI_VECTOR)
7460fb4a 4989 vcpu->arch.nmi_pending = 0;
63995653
MG		 4990 else
4991 vcpu->arch.interrupt.pending = false;
4992
4993 return EMULATE_DONE;
4994}
4995EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4996
6d77dbfc
GN		 4997static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4998{
fc3a9157
JR		 4999 int r = EMULATE_DONE;
5000
6d77dbfc
GN		 5001 ++vcpu->stat.insn_emulation_fail;
5002 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5003 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5004 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5005 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5006 vcpu->run->internal.ndata = 0;
5007 r = EMULATE_FAIL;
5008 }
6d77dbfc 5009 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5010
5011 return r;
6d77dbfc
GN		 5012}
5013
93c05d3e 5014static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5015 bool write_fault_to_shadow_pgtable,
5016 int emulation_type)
a6f177ef 5017{
95b3cf69 5018 gpa_t gpa = cr2;
8e3d9d06 5019 pfn_t pfn;
a6f177ef 5020
991eebf9
GN		 5021 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5022 return false;
5023
95b3cf69
XG		 5024 if (!vcpu->arch.mmu.direct_map) {
5025 /*
5026 * Write permission should be allowed since only
5027 * write access need to be emulated.
5028 */
5029 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5030
95b3cf69
XG		 5031 /*
5032 * If the mapping is invalid in guest, let cpu retry
5033 * it to generate fault.
5034 */
5035 if (gpa == UNMAPPED_GVA)
5036 return true;
5037 }
a6f177ef 5038
8e3d9d06
XG		 5039 /*
5040 * Do not retry the unhandleable instruction if it faults on the
5041 * readonly host memory, otherwise it will goto a infinite loop:
5042 * retry instruction -> write #PF -> emulation fail -> retry
5043 * instruction -> ...
5044 */
5045 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5046
5047 /*
5048 * If the instruction failed on the error pfn, it can not be fixed,
5049 * report the error to userspace.
5050 */
5051 if (is_error_noslot_pfn(pfn))
5052 return false;
5053
5054 kvm_release_pfn_clean(pfn);
5055
5056 /* The instructions are well-emulated on direct mmu. */
5057 if (vcpu->arch.mmu.direct_map) {
5058 unsigned int indirect_shadow_pages;
5059
5060 spin_lock(&vcpu->kvm->mmu_lock);
5061 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5062 spin_unlock(&vcpu->kvm->mmu_lock);
5063
5064 if (indirect_shadow_pages)
5065 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5066
a6f177ef 5067 return true;
8e3d9d06 5068 }
a6f177ef 5069
95b3cf69
XG		 5070 /*
5071 * if emulation was due to access to shadowed page table
5072 * and it failed try to unshadow page and re-enter the
5073 * guest to let CPU execute the instruction.
5074 */
5075 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5076
5077 /*
5078 * If the access faults on its page table, it can not
5079 * be fixed by unprotecting shadow page and it should
5080 * be reported to userspace.
5081 */
5082 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5083}
5084
1cb3f3ae
XG		 5085static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5086 unsigned long cr2, int emulation_type)
5087{
5088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5089 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5090
5091 last_retry_eip = vcpu->arch.last_retry_eip;
5092 last_retry_addr = vcpu->arch.last_retry_addr;
5093
5094 /*
5095 * If the emulation is caused by #PF and it is non-page_table
5096 * writing instruction, it means the VM-EXIT is caused by shadow
5097 * page protected, we can zap the shadow page and retry this
5098 * instruction directly.
5099 *
5100 * Note: if the guest uses a non-page-table modifying instruction
5101 * on the PDE that points to the instruction, then we will unmap
5102 * the instruction and go to an infinite loop. So, we cache the
5103 * last retried eip and the last fault address, if we meet the eip
5104 * and the address again, we can break out of the potential infinite
5105 * loop.
5106 */
5107 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5108
5109 if (!(emulation_type & EMULTYPE_RETRY))
5110 return false;
5111
5112 if (x86_page_table_writing_insn(ctxt))
5113 return false;
5114
5115 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5116 return false;
5117
5118 vcpu->arch.last_retry_eip = ctxt->eip;
5119 vcpu->arch.last_retry_addr = cr2;
5120
5121 if (!vcpu->arch.mmu.direct_map)
5122 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5123
22368028 5124 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5125
5126 return true;
5127}
5128
716d51ab
GN		 5129static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5130static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5131
4a1e10d5
PB		 5132static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5133 unsigned long *db)
5134{
5135 u32 dr6 = 0;
5136 int i;
5137 u32 enable, rwlen;
5138
5139 enable = dr7;
5140 rwlen = dr7 >> 16;
5141 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5142 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5143 dr6 |= (1 << i);
5144 return dr6;
5145}
5146
6addfc42 5147static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5148{
5149 struct kvm_run *kvm_run = vcpu->run;
5150
5151 /*
6addfc42
PB		 5152 * rflags is the old, "raw" value of the flags. The new value has
5153 * not been saved yet.
663f4c61
PB		 5154 *
5155 * This is correct even for TF set by the guest, because "the
5156 * processor will not generate this exception after the instruction
5157 * that sets the TF flag".
5158 */
663f4c61
PB		 5159 if (unlikely(rflags & X86_EFLAGS_TF)) {
5160 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5161 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5162 DR6_RTM;
663f4c61
PB		 5163 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5164 kvm_run->debug.arch.exception = DB_VECTOR;
5165 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5166 *r = EMULATE_USER_EXIT;
5167 } else {
5168 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5169 /*
5170 * "Certain debug exceptions may clear bit 0-3. The
5171 * remaining contents of the DR6 register are never
5172 * cleared by the processor".
5173 */
5174 vcpu->arch.dr6 &= ~15;
6f43ed01 5175 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5176 kvm_queue_exception(vcpu, DB_VECTOR);
5177 }
5178 }
5179}
5180
4a1e10d5
PB		 5181static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5182{
5183 struct kvm_run *kvm_run = vcpu->run;
5184 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5185 u32 dr6 = 0;
5186
5187 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5188 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5189 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5190 vcpu->arch.guest_debug_dr7,
5191 vcpu->arch.eff_db);
5192
5193 if (dr6 != 0) {
6f43ed01 5194 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5195 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5196 get_segment_base(vcpu, VCPU_SREG_CS);
5197
5198 kvm_run->debug.arch.exception = DB_VECTOR;
5199 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5200 *r = EMULATE_USER_EXIT;
5201 return true;
5202 }
5203 }
5204
4161a569
NA		 5205 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5206 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5207 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5208 vcpu->arch.dr7,
5209 vcpu->arch.db);
5210
5211 if (dr6 != 0) {
5212 vcpu->arch.dr6 &= ~15;
6f43ed01 5213 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5214 kvm_queue_exception(vcpu, DB_VECTOR);
5215 *r = EMULATE_DONE;
5216 return true;
5217 }
5218 }
5219
5220 return false;
5221}
5222
51d8b661
AP		 5223int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5224 unsigned long cr2,
dc25e89e
AP		 5225 int emulation_type,
5226 void *insn,
5227 int insn_len)
bbd9b64e 5228{
95cb2295 5229 int r;
9d74191a 5230 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5231 bool writeback = true;
93c05d3e 5232 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5233
93c05d3e
XG		 5234 /*
5235 * Clear write_fault_to_shadow_pgtable here to ensure it is
5236 * never reused.
5237 */
5238 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5239 kvm_clear_exception_queue(vcpu);
8d7d8102 5240
571008da 5241 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5242 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5243
5244 /*
5245 * We will reenter on the same instruction since
5246 * we do not set complete_userspace_io. This does not
5247 * handle watchpoints yet, those would be handled in
5248 * the emulate_ops.
5249 */
5250 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5251 return r;
5252
9d74191a
TY		 5253 ctxt->interruptibility = 0;
5254 ctxt->have_exception = false;
e0ad0b47 5255 ctxt->exception.vector = -1;
9d74191a 5256 ctxt->perm_ok = false;
bbd9b64e 5257
b51e974f 5258 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5259
9d74191a 5260 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5261
e46479f8 5262 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5263 ++vcpu->stat.insn_emulation;
1d2887e2 5264 if (r != EMULATION_OK) {
4005996e
AK		 5265 if (emulation_type & EMULTYPE_TRAP_UD)
5266 return EMULATE_FAIL;
991eebf9
GN		 5267 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5268 emulation_type))
bbd9b64e 5269 return EMULATE_DONE;
6d77dbfc
GN		 5270 if (emulation_type & EMULTYPE_SKIP)
5271 return EMULATE_FAIL;
5272 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5273 }
5274 }
5275
ba8afb6b 5276 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5277 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5278 if (ctxt->eflags & X86_EFLAGS_RF)
5279 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5280 return EMULATE_DONE;
5281 }
5282
1cb3f3ae
XG		 5283 if (retry_instruction(ctxt, cr2, emulation_type))
5284 return EMULATE_DONE;
5285
7ae441ea 5286 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5287 changes registers values during IO operation */
7ae441ea
GN		 5288 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5289 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5290 emulator_invalidate_register_cache(ctxt);
7ae441ea 5291 }
4d2179e1 5292
5cd21917 5293restart:
9d74191a 5294 r = x86_emulate_insn(ctxt);
bbd9b64e 5295
775fde86
JR		 5296 if (r == EMULATION_INTERCEPTED)
5297 return EMULATE_DONE;
5298
d2ddd1c4 5299 if (r == EMULATION_FAILED) {
991eebf9
GN		 5300 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5301 emulation_type))
c3cd7ffa
GN		 5302 return EMULATE_DONE;
5303
6d77dbfc 5304 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5305 }
5306
9d74191a 5307 if (ctxt->have_exception) {
d2ddd1c4 5308 r = EMULATE_DONE;
ef54bcfe
PB		 5309 if (inject_emulated_exception(vcpu))
5310 return r;
d2ddd1c4 5311 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5312 if (!vcpu->arch.pio.in) {
5313 /* FIXME: return into emulator if single-stepping. */
3457e419 5314 vcpu->arch.pio.count = 0;
0912c977 5315 } else {
7ae441ea 5316 writeback = false;
716d51ab
GN		 5317 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5318 }
ac0a48c3 5319 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5320 } else if (vcpu->mmio_needed) {
5321 if (!vcpu->mmio_is_write)
5322 writeback = false;
ac0a48c3 5323 r = EMULATE_USER_EXIT;
716d51ab 5324 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5325 } else if (r == EMULATION_RESTART)
5cd21917 5326 goto restart;
d2ddd1c4
GN		 5327 else
5328 r = EMULATE_DONE;
f850e2e6 5329
7ae441ea 5330 if (writeback) {
6addfc42 5331 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5332 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5333 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5334 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5335 if (r == EMULATE_DONE)
6addfc42
PB		 5336 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5337 __kvm_set_rflags(vcpu, ctxt->eflags);
5338
5339 /*
5340 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5341 * do nothing, and it will be requested again as soon as
5342 * the shadow expires. But we still need to check here,
5343 * because POPF has no interrupt shadow.
5344 */
5345 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5346 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5347 } else
5348 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5349
5350 return r;
de7d789a 5351}
51d8b661 5352EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5353
cf8f70bf 5354int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5355{
cf8f70bf 5356 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5357 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5358 size, port, &val, 1);
cf8f70bf 5359 /* do not return to emulator after return from userspace */
7972995b 5360 vcpu->arch.pio.count = 0;
de7d789a
CO		 5361 return ret;
5362}
cf8f70bf 5363EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5364
8cfdc000
ZA		 5365static void tsc_bad(void *info)
5366{
0a3aee0d 5367 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5368}
5369
5370static void tsc_khz_changed(void *data)
c8076604 5371{
8cfdc000
ZA		 5372 struct cpufreq_freqs *freq = data;
5373 unsigned long khz = 0;
5374
5375 if (data)
5376 khz = freq->new;
5377 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5378 khz = cpufreq_quick_get(raw_smp_processor_id());
5379 if (!khz)
5380 khz = tsc_khz;
0a3aee0d 5381 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5382}
5383
c8076604
GH		 5384static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5385 void *data)
5386{
5387 struct cpufreq_freqs *freq = data;
5388 struct kvm *kvm;
5389 struct kvm_vcpu *vcpu;
5390 int i, send_ipi = 0;
5391
8cfdc000
ZA		 5392 /*
5393 * We allow guests to temporarily run on slowing clocks,
5394 * provided we notify them after, or to run on accelerating
5395 * clocks, provided we notify them before. Thus time never
5396 * goes backwards.
5397 *
5398 * However, we have a problem. We can't atomically update
5399 * the frequency of a given CPU from this function; it is
5400 * merely a notifier, which can be called from any CPU.
5401 * Changing the TSC frequency at arbitrary points in time
5402 * requires a recomputation of local variables related to
5403 * the TSC for each VCPU. We must flag these local variables
5404 * to be updated and be sure the update takes place with the
5405 * new frequency before any guests proceed.
5406 *
5407 * Unfortunately, the combination of hotplug CPU and frequency
5408 * change creates an intractable locking scenario; the order
5409 * of when these callouts happen is undefined with respect to
5410 * CPU hotplug, and they can race with each other. As such,
5411 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5412 * undefined; you can actually have a CPU frequency change take
5413 * place in between the computation of X and the setting of the
5414 * variable. To protect against this problem, all updates of
5415 * the per_cpu tsc_khz variable are done in an interrupt
5416 * protected IPI, and all callers wishing to update the value
5417 * must wait for a synchronous IPI to complete (which is trivial
5418 * if the caller is on the CPU already). This establishes the
5419 * necessary total order on variable updates.
5420 *
5421 * Note that because a guest time update may take place
5422 * anytime after the setting of the VCPU's request bit, the
5423 * correct TSC value must be set before the request. However,
5424 * to ensure the update actually makes it to any guest which
5425 * starts running in hardware virtualization between the set
5426 * and the acquisition of the spinlock, we must also ping the
5427 * CPU after setting the request bit.
5428 *
5429 */
5430
c8076604
GH		 5431 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5432 return 0;
5433 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5434 return 0;
8cfdc000
ZA		 5435
5436 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5437
2f303b74 5438 spin_lock(&kvm_lock);
c8076604 5439 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5440 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5441 if (vcpu->cpu != freq->cpu)
5442 continue;
c285545f 5443 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5444 if (vcpu->cpu != smp_processor_id())
8cfdc000 5445 send_ipi = 1;
c8076604
GH		 5446 }
5447 }
2f303b74 5448 spin_unlock(&kvm_lock);
c8076604
GH		 5449
5450 if (freq->old < freq->new && send_ipi) {
5451 /*
5452 * We upscale the frequency. Must make the guest
5453 * doesn't see old kvmclock values while running with
5454 * the new frequency, otherwise we risk the guest sees
5455 * time go backwards.
5456 *
5457 * In case we update the frequency for another cpu
5458 * (which might be in guest context) send an interrupt
5459 * to kick the cpu out of guest context. Next time
5460 * guest context is entered kvmclock will be updated,
5461 * so the guest will not see stale values.
5462 */
8cfdc000 5463 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5464 }
5465 return 0;
5466}
5467
5468static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5469 .notifier_call = kvmclock_cpufreq_notifier
5470};
5471
5472static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5473 unsigned long action, void *hcpu)
5474{
5475 unsigned int cpu = (unsigned long)hcpu;
5476
5477 switch (action) {
5478 case CPU_ONLINE:
5479 case CPU_DOWN_FAILED:
5480 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5481 break;
5482 case CPU_DOWN_PREPARE:
5483 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5484 break;
5485 }
5486 return NOTIFY_OK;
5487}
5488
5489static struct notifier_block kvmclock_cpu_notifier_block = {
5490 .notifier_call = kvmclock_cpu_notifier,
5491 .priority = -INT_MAX
c8076604
GH		 5492};
5493
b820cc0c
ZA		 5494static void kvm_timer_init(void)
5495{
5496 int cpu;
5497
c285545f 5498 max_tsc_khz = tsc_khz;
460dd42e
SB		 5499
5500 cpu_notifier_register_begin();
b820cc0c 5501 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5502#ifdef CONFIG_CPU_FREQ
5503 struct cpufreq_policy policy;
5504 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5505 cpu = get_cpu();
5506 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5507 if (policy.cpuinfo.max_freq)
5508 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5509 put_cpu();
c285545f 5510#endif
b820cc0c
ZA		 5511 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5512 CPUFREQ_TRANSITION_NOTIFIER);
5513 }
c285545f 5514 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5515 for_each_online_cpu(cpu)
5516 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5517
5518 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5519 cpu_notifier_register_done();
5520
b820cc0c
ZA		 5521}
5522
ff9d07a0
ZY		 5523static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5524
f5132b01 5525int kvm_is_in_guest(void)
ff9d07a0 5526{
086c9855 5527 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5528}
5529
5530static int kvm_is_user_mode(void)
5531{
5532 int user_mode = 3;
dcf46b94 5533
086c9855
AS		 5534 if (__this_cpu_read(current_vcpu))
5535 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5536
ff9d07a0
ZY		 5537 return user_mode != 0;
5538}
5539
5540static unsigned long kvm_get_guest_ip(void)
5541{
5542 unsigned long ip = 0;
dcf46b94 5543
086c9855
AS		 5544 if (__this_cpu_read(current_vcpu))
5545 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5546
ff9d07a0
ZY		 5547 return ip;
5548}
5549
5550static struct perf_guest_info_callbacks kvm_guest_cbs = {
5551 .is_in_guest = kvm_is_in_guest,
5552 .is_user_mode = kvm_is_user_mode,
5553 .get_guest_ip = kvm_get_guest_ip,
5554};
5555
5556void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5557{
086c9855 5558 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5559}
5560EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5561
5562void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5563{
086c9855 5564 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5565}
5566EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5567
ce88decf
XG		 5568static void kvm_set_mmio_spte_mask(void)
5569{
5570 u64 mask;
5571 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5572
5573 /*
5574 * Set the reserved bits and the present bit of an paging-structure
5575 * entry to generate page fault with PFER.RSV = 1.
5576 */
885032b9 5577 /* Mask the reserved physical address bits. */
d1431483 5578 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5579
5580 /* Bit 62 is always reserved for 32bit host. */
5581 mask |= 0x3ull << 62;
5582
5583 /* Set the present bit. */
ce88decf
XG		 5584 mask |= 1ull;
5585
5586#ifdef CONFIG_X86_64
5587 /*
5588 * If reserved bit is not supported, clear the present bit to disable
5589 * mmio page fault.
5590 */
5591 if (maxphyaddr == 52)
5592 mask &= ~1ull;
5593#endif
5594
5595 kvm_mmu_set_mmio_spte_mask(mask);
5596}
5597
16e8d74d
MT		 5598#ifdef CONFIG_X86_64
5599static void pvclock_gtod_update_fn(struct work_struct *work)
5600{
d828199e
MT		 5601 struct kvm *kvm;
5602
5603 struct kvm_vcpu *vcpu;
5604 int i;
5605
2f303b74 5606 spin_lock(&kvm_lock);
d828199e
MT		 5607 list_for_each_entry(kvm, &vm_list, vm_list)
5608 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5609 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5610 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5611 spin_unlock(&kvm_lock);
16e8d74d
MT		 5612}
5613
5614static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5615
5616/*
5617 * Notification about pvclock gtod data update.
5618 */
5619static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5620 void *priv)
5621{
5622 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5623 struct timekeeper *tk = priv;
5624
5625 update_pvclock_gtod(tk);
5626
5627 /* disable master clock if host does not trust, or does not
5628 * use, TSC clocksource
5629 */
5630 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5631 atomic_read(&kvm_guest_has_master_clock) != 0)
5632 queue_work(system_long_wq, &pvclock_gtod_work);
5633
5634 return 0;
5635}
5636
5637static struct notifier_block pvclock_gtod_notifier = {
5638 .notifier_call = pvclock_gtod_notify,
5639};
5640#endif
5641
f8c16bba 5642int kvm_arch_init(void *opaque)
043405e1 5643{
b820cc0c 5644 int r;
6b61edf7 5645 struct kvm_x86_ops *ops = opaque;
f8c16bba 5646
f8c16bba
ZX		 5647 if (kvm_x86_ops) {
5648 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5649 r = -EEXIST;
5650 goto out;
f8c16bba
ZX		 5651 }
5652
5653 if (!ops->cpu_has_kvm_support()) {
5654 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5655 r = -EOPNOTSUPP;
5656 goto out;
f8c16bba
ZX		 5657 }
5658 if (ops->disabled_by_bios()) {
5659 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5660 r = -EOPNOTSUPP;
5661 goto out;
f8c16bba
ZX		 5662 }
5663
013f6a5d
MT		 5664 r = -ENOMEM;
5665 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5666 if (!shared_msrs) {
5667 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5668 goto out;
5669 }
5670
97db56ce
AK		 5671 r = kvm_mmu_module_init();
5672 if (r)
013f6a5d 5673 goto out_free_percpu;
97db56ce 5674
ce88decf 5675 kvm_set_mmio_spte_mask();
97db56ce 5676
f8c16bba 5677 kvm_x86_ops = ops;
920c8377
PB		 5678 kvm_init_msr_list();
5679
7b52345e 5680 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5681 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5682
b820cc0c 5683 kvm_timer_init();
c8076604 5684
ff9d07a0
ZY		 5685 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5686
2acf923e
DC		 5687 if (cpu_has_xsave)
5688 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5689
c5cc421b 5690 kvm_lapic_init();
16e8d74d
MT		 5691#ifdef CONFIG_X86_64
5692 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5693#endif
5694
f8c16bba 5695 return 0;
56c6d28a 5696
013f6a5d
MT		 5697out_free_percpu:
5698 free_percpu(shared_msrs);
56c6d28a 5699out:
56c6d28a 5700 return r;
043405e1 5701}
8776e519 5702
f8c16bba
ZX		 5703void kvm_arch_exit(void)
5704{
ff9d07a0
ZY		 5705 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5706
888d256e
JK		 5707 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5708 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5709 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5710 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5711#ifdef CONFIG_X86_64
5712 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5713#endif
f8c16bba 5714 kvm_x86_ops = NULL;
56c6d28a 5715 kvm_mmu_module_exit();
013f6a5d 5716 free_percpu(shared_msrs);
56c6d28a 5717}
f8c16bba 5718
8776e519
HB		 5719int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5720{
5721 ++vcpu->stat.halt_exits;
5722 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5723 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5724 return 1;
5725 } else {
5726 vcpu->run->exit_reason = KVM_EXIT_HLT;
5727 return 0;
5728 }
5729}
5730EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5731
55cd8e5a
GN		 5732int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5733{
5734 u64 param, ingpa, outgpa, ret;
5735 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5736 bool fast, longmode;
55cd8e5a
GN		 5737
5738 /*
5739 * hypercall generates UD from non zero cpl and real mode
5740 * per HYPER-V spec
5741 */
3eeb3288 5742 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5743 kvm_queue_exception(vcpu, UD_VECTOR);
5744 return 0;
5745 }
5746
a449c7aa 5747 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5748
5749 if (!longmode) {
ccd46936
GN		 5750 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5751 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5752 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5753 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5754 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5755 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5756 }
5757#ifdef CONFIG_X86_64
5758 else {
5759 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5760 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5761 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5762 }
5763#endif
5764
5765 code = param & 0xffff;
5766 fast = (param >> 16) & 0x1;
5767 rep_cnt = (param >> 32) & 0xfff;
5768 rep_idx = (param >> 48) & 0xfff;
5769
5770 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5771
c25bc163
GN		 5772 switch (code) {
5773 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5774 kvm_vcpu_on_spin(vcpu);
5775 break;
5776 default:
5777 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5778 break;
5779 }
55cd8e5a
GN		 5780
5781 ret = res | (((u64)rep_done & 0xfff) << 32);
5782 if (longmode) {
5783 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5784 } else {
5785 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5786 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5787 }
5788
5789 return 1;
5790}
5791
6aef266c
SV		 5792/*
5793 * kvm_pv_kick_cpu_op: Kick a vcpu.
5794 *
5795 * @apicid - apicid of vcpu to be kicked.
5796 */
5797static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5798{
24d2166b 5799 struct kvm_lapic_irq lapic_irq;
6aef266c 5800
24d2166b
R		 5801 lapic_irq.shorthand = 0;
5802 lapic_irq.dest_mode = 0;
5803 lapic_irq.dest_id = apicid;
6aef266c 5804
24d2166b
R		 5805 lapic_irq.delivery_mode = APIC_DM_REMRD;
5806 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5807}
5808
8776e519
HB		 5809int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5810{
5811 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5812 int op_64_bit, r = 1;
8776e519 5813
55cd8e5a
GN		 5814 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5815 return kvm_hv_hypercall(vcpu);
5816
5fdbf976
MT		 5817 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5818 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5819 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5820 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5821 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5822
229456fc 5823 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5824
a449c7aa
NA		 5825 op_64_bit = is_64_bit_mode(vcpu);
5826 if (!op_64_bit) {
8776e519
HB		 5827 nr &= 0xFFFFFFFF;
5828 a0 &= 0xFFFFFFFF;
5829 a1 &= 0xFFFFFFFF;
5830 a2 &= 0xFFFFFFFF;
5831 a3 &= 0xFFFFFFFF;
5832 }
5833
07708c4a
JK		 5834 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5835 ret = -KVM_EPERM;
5836 goto out;
5837 }
5838
8776e519 5839 switch (nr) {
b93463aa
AK		 5840 case KVM_HC_VAPIC_POLL_IRQ:
5841 ret = 0;
5842 break;
6aef266c
SV		 5843 case KVM_HC_KICK_CPU:
5844 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5845 ret = 0;
5846 break;
8776e519
HB		 5847 default:
5848 ret = -KVM_ENOSYS;
5849 break;
5850 }
07708c4a 5851out:
a449c7aa
NA		 5852 if (!op_64_bit)
5853 ret = (u32)ret;
5fdbf976 5854 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5855 ++vcpu->stat.hypercalls;
2f333bcb 5856 return r;
8776e519
HB		 5857}
5858EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5859
b6785def 5860static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5861{
d6aa1000 5862 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5863 char instruction[3];
5fdbf976 5864 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5865
8776e519 5866 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5867
9d74191a 5868 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5869}
5870
b6c7a5dc
HB		 5871/*
5872 * Check if userspace requested an interrupt window, and that the
5873 * interrupt window is open.
5874 *
5875 * No need to exit to userspace if we already have an interrupt queued.
5876 */
851ba692 5877static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5878{
8061823a 5879 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5880 vcpu->run->request_interrupt_window &&
5df56646 5881 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5882}
5883
851ba692 5884static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5885{
851ba692
AK		 5886 struct kvm_run *kvm_run = vcpu->run;
5887
91586a3b 5888 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5889 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5890 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5891 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5892 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5893 else
b6c7a5dc 5894 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5895 kvm_arch_interrupt_allowed(vcpu) &&
5896 !kvm_cpu_has_interrupt(vcpu) &&
5897 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5898}
5899
95ba8273
GN		 5900static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5901{
5902 int max_irr, tpr;
5903
5904 if (!kvm_x86_ops->update_cr8_intercept)
5905 return;
5906
88c808fd
AK		 5907 if (!vcpu->arch.apic)
5908 return;
5909
8db3baa2
GN		 5910 if (!vcpu->arch.apic->vapic_addr)
5911 max_irr = kvm_lapic_find_highest_irr(vcpu);
5912 else
5913 max_irr = -1;
95ba8273
GN		 5914
5915 if (max_irr != -1)
5916 max_irr >>= 4;
5917
5918 tpr = kvm_lapic_get_cr8(vcpu);
5919
5920 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5921}
5922
b6b8a145 5923static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5924{
b6b8a145
JK		 5925 int r;
5926
95ba8273 5927 /* try to reinject previous events if any */
b59bb7bd 5928 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5929 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5930 vcpu->arch.exception.has_error_code,
5931 vcpu->arch.exception.error_code);
d6e8c854
NA		 5932
5933 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5934 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5935 X86_EFLAGS_RF);
5936
b59bb7bd
GN		 5937 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5938 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5939 vcpu->arch.exception.error_code,
5940 vcpu->arch.exception.reinject);
b6b8a145 5941 return 0;
b59bb7bd
GN		 5942 }
5943
95ba8273
GN		 5944 if (vcpu->arch.nmi_injected) {
5945 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5946 return 0;
95ba8273
GN		 5947 }
5948
5949 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5950 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5951 return 0;
5952 }
5953
5954 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5955 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5956 if (r != 0)
5957 return r;
95ba8273
GN		 5958 }
5959
5960 /* try to inject new event if pending */
5961 if (vcpu->arch.nmi_pending) {
5962 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5963 --vcpu->arch.nmi_pending;
95ba8273
GN		 5964 vcpu->arch.nmi_injected = true;
5965 kvm_x86_ops->set_nmi(vcpu);
5966 }
c7c9c56c 5967 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5968 /*
5969 * Because interrupts can be injected asynchronously, we are
5970 * calling check_nested_events again here to avoid a race condition.
5971 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5972 * proposal and current concerns. Perhaps we should be setting
5973 * KVM_REQ_EVENT only on certain events and not unconditionally?
5974 */
5975 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5976 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5977 if (r != 0)
5978 return r;
5979 }
95ba8273 5980 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5981 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5982 false);
5983 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5984 }
5985 }
b6b8a145 5986 return 0;
95ba8273
GN		 5987}
5988
7460fb4a
AK		 5989static void process_nmi(struct kvm_vcpu *vcpu)
5990{
5991 unsigned limit = 2;
5992
5993 /*
5994 * x86 is limited to one NMI running, and one NMI pending after it.
5995 * If an NMI is already in progress, limit further NMIs to just one.
5996 * Otherwise, allow two (and we'll inject the first one immediately).
5997 */
5998 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5999 limit = 1;
6000
6001 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6002 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6003 kvm_make_request(KVM_REQ_EVENT, vcpu);
6004}
6005
3d81bc7e 6006static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6007{
6008 u64 eoi_exit_bitmap[4];
cf9e65b7 6009 u32 tmr[8];
c7c9c56c 6010
3d81bc7e
YZ		 6011 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6012 return;
c7c9c56c
YZ		 6013
6014 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6015 memset(tmr, 0, 32);
c7c9c56c 6016
cf9e65b7 6017 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6018 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6019 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6020}
6021
a70656b6
RK		 6022static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6023{
6024 ++vcpu->stat.tlb_flush;
6025 kvm_x86_ops->tlb_flush(vcpu);
6026}
6027
9357d939
TY		 6028/*
6029 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6030 * exiting to the userspace. Otherwise, the value will be returned to the
6031 * userspace.
6032 */
851ba692 6033static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6034{
6035 int r;
6a8b1d13 6036 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6037 vcpu->run->request_interrupt_window;
730dca42 6038 bool req_immediate_exit = false;
b6c7a5dc 6039
3e007509 6040 if (vcpu->requests) {
a8eeb04a 6041 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6042 kvm_mmu_unload(vcpu);
a8eeb04a 6043 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6044 __kvm_migrate_timers(vcpu);
d828199e
MT		 6045 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6046 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6047 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6048 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6049 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6050 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6051 if (unlikely(r))
6052 goto out;
6053 }
a8eeb04a 6054 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6055 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6056 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6057 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6058 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6059 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6060 r = 0;
6061 goto out;
6062 }
a8eeb04a 6063 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6064 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6065 r = 0;
6066 goto out;
6067 }
a8eeb04a 6068 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6069 vcpu->fpu_active = 0;
6070 kvm_x86_ops->fpu_deactivate(vcpu);
6071 }
af585b92
GN		 6072 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6073 /* Page is swapped out. Do synthetic halt */
6074 vcpu->arch.apf.halted = true;
6075 r = 1;
6076 goto out;
6077 }
c9aaa895
GC		 6078 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6079 record_steal_time(vcpu);
7460fb4a
AK		 6080 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6081 process_nmi(vcpu);
f5132b01
GN		 6082 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6083 kvm_handle_pmu_event(vcpu);
6084 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6085 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6086 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6087 vcpu_scan_ioapic(vcpu);
2f52d58c 6088 }
b93463aa 6089
b463a6f7 6090 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6091 kvm_apic_accept_events(vcpu);
6092 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6093 r = 1;
6094 goto out;
6095 }
6096
b6b8a145
JK		 6097 if (inject_pending_event(vcpu, req_int_win) != 0)
6098 req_immediate_exit = true;
b463a6f7 6099 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6100 else if (vcpu->arch.nmi_pending)
c9a7953f 6101 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6102 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6103 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6104
6105 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6106 /*
6107 * Update architecture specific hints for APIC
6108 * virtual interrupt delivery.
6109 */
6110 if (kvm_x86_ops->hwapic_irr_update)
6111 kvm_x86_ops->hwapic_irr_update(vcpu,
6112 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6113 update_cr8_intercept(vcpu);
6114 kvm_lapic_sync_to_vapic(vcpu);
6115 }
6116 }
6117
d8368af8
AK		 6118 r = kvm_mmu_reload(vcpu);
6119 if (unlikely(r)) {
d905c069 6120 goto cancel_injection;
d8368af8
AK		 6121 }
6122
b6c7a5dc
HB		 6123 preempt_disable();
6124
6125 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6126 if (vcpu->fpu_active)
6127 kvm_load_guest_fpu(vcpu);
2acf923e 6128 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6129
6b7e2d09
XG		 6130 vcpu->mode = IN_GUEST_MODE;
6131
01b71917
MT		 6132 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6133
6b7e2d09
XG		 6134 /* We should set ->mode before check ->requests,
6135 * see the comment in make_all_cpus_request.
6136 */
01b71917 6137 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6138
d94e1dc9 6139 local_irq_disable();
32f88400 6140
6b7e2d09 6141 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6142 || need_resched() || signal_pending(current)) {
6b7e2d09 6143 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6144 smp_wmb();
6c142801
AK		 6145 local_irq_enable();
6146 preempt_enable();
01b71917 6147 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6148 r = 1;
d905c069 6149 goto cancel_injection;
6c142801
AK		 6150 }
6151
d6185f20
NHE		 6152 if (req_immediate_exit)
6153 smp_send_reschedule(vcpu->cpu);
6154
b6c7a5dc
HB		 6155 kvm_guest_enter();
6156
42dbaa5a 6157 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6158 set_debugreg(0, 7);
6159 set_debugreg(vcpu->arch.eff_db[0], 0);
6160 set_debugreg(vcpu->arch.eff_db[1], 1);
6161 set_debugreg(vcpu->arch.eff_db[2], 2);
6162 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6163 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6164 }
b6c7a5dc 6165
229456fc 6166 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6167 kvm_x86_ops->run(vcpu);
b6c7a5dc 6168
c77fb5fe
PB		 6169 /*
6170 * Do this here before restoring debug registers on the host. And
6171 * since we do this before handling the vmexit, a DR access vmexit
6172 * can (a) read the correct value of the debug registers, (b) set
6173 * KVM_DEBUGREG_WONT_EXIT again.
6174 */
6175 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6176 int i;
6177
6178 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6179 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6180 for (i = 0; i < KVM_NR_DB_REGS; i++)
6181 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6182 }
6183
24f1e32c
FW		 6184 /*
6185 * If the guest has used debug registers, at least dr7
6186 * will be disabled while returning to the host.
6187 * If we don't have active breakpoints in the host, we don't
6188 * care about the messed up debug address registers. But if
6189 * we have some of them active, restore the old state.
6190 */
59d8eb53 6191 if (hw_breakpoint_active())
24f1e32c 6192 hw_breakpoint_restore();
42dbaa5a 6193
886b470c
MT		 6194 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6195 native_read_tsc());
1d5f066e 6196
6b7e2d09 6197 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6198 smp_wmb();
a547c6db
YZ		 6199
6200 /* Interrupt is enabled by handle_external_intr() */
6201 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6202
6203 ++vcpu->stat.exits;
6204
6205 /*
6206 * We must have an instruction between local_irq_enable() and
6207 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6208 * the interrupt shadow. The stat.exits increment will do nicely.
6209 * But we need to prevent reordering, hence this barrier():
6210 */
6211 barrier();
6212
6213 kvm_guest_exit();
6214
6215 preempt_enable();
6216
f656ce01 6217 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6218
b6c7a5dc
HB		 6219 /*
6220 * Profile KVM exit RIPs:
6221 */
6222 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6223 unsigned long rip = kvm_rip_read(vcpu);
6224 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6225 }
6226
cc578287
ZA		 6227 if (unlikely(vcpu->arch.tsc_always_catchup))
6228 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6229
5cfb1d5a
MT		 6230 if (vcpu->arch.apic_attention)
6231 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6232
851ba692 6233 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6234 return r;
6235
6236cancel_injection:
6237 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6238 if (unlikely(vcpu->arch.apic_attention))
6239 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6240out:
6241 return r;
6242}
b6c7a5dc 6243
09cec754 6244
851ba692 6245static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6246{
6247 int r;
f656ce01 6248 struct kvm *kvm = vcpu->kvm;
d7690175 6249
f656ce01 6250 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6251
6252 r = 1;
6253 while (r > 0) {
af585b92
GN		 6254 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6255 !vcpu->arch.apf.halted)
851ba692 6256 r = vcpu_enter_guest(vcpu);
d7690175 6257 else {
f656ce01 6258 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6259 kvm_vcpu_block(vcpu);
f656ce01 6260 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6261 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6262 kvm_apic_accept_events(vcpu);
09cec754
GN		 6263 switch(vcpu->arch.mp_state) {
6264 case KVM_MP_STATE_HALTED:
6aef266c 6265 vcpu->arch.pv.pv_unhalted = false;
d7690175 6266 vcpu->arch.mp_state =
09cec754
GN		 6267 KVM_MP_STATE_RUNNABLE;
6268 case KVM_MP_STATE_RUNNABLE:
af585b92 6269 vcpu->arch.apf.halted = false;
09cec754 6270 break;
66450a21
JK		 6271 case KVM_MP_STATE_INIT_RECEIVED:
6272 break;
09cec754
GN		 6273 default:
6274 r = -EINTR;
6275 break;
6276 }
6277 }
d7690175
MT		 6278 }
6279
09cec754
GN		 6280 if (r <= 0)
6281 break;
6282
6283 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6284 if (kvm_cpu_has_pending_timer(vcpu))
6285 kvm_inject_pending_timer_irqs(vcpu);
6286
851ba692 6287 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6288 r = -EINTR;
851ba692 6289 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6290 ++vcpu->stat.request_irq_exits;
6291 }
af585b92
GN		 6292
6293 kvm_check_async_pf_completion(vcpu);
6294
09cec754
GN		 6295 if (signal_pending(current)) {
6296 r = -EINTR;
851ba692 6297 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6298 ++vcpu->stat.signal_exits;
6299 }
6300 if (need_resched()) {
f656ce01 6301 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6302 cond_resched();
f656ce01 6303 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6304 }
b6c7a5dc
HB		 6305 }
6306
f656ce01 6307 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6308
6309 return r;
6310}
6311
716d51ab
GN		 6312static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6313{
6314 int r;
6315 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6316 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6317 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6318 if (r != EMULATE_DONE)
6319 return 0;
6320 return 1;
6321}
6322
6323static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6324{
6325 BUG_ON(!vcpu->arch.pio.count);
6326
6327 return complete_emulated_io(vcpu);
6328}
6329
f78146b0
AK		 6330/*
6331 * Implements the following, as a state machine:
6332 *
6333 * read:
6334 * for each fragment
87da7e66
XG		 6335 * for each mmio piece in the fragment
6336 * write gpa, len
6337 * exit
6338 * copy data
f78146b0
AK		 6339 * execute insn
6340 *
6341 * write:
6342 * for each fragment
87da7e66
XG		 6343 * for each mmio piece in the fragment
6344 * write gpa, len
6345 * copy data
6346 * exit
f78146b0 6347 */
716d51ab 6348static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6349{
6350 struct kvm_run *run = vcpu->run;
f78146b0 6351 struct kvm_mmio_fragment *frag;
87da7e66 6352 unsigned len;
5287f194 6353
716d51ab 6354 BUG_ON(!vcpu->mmio_needed);
5287f194 6355
716d51ab 6356 /* Complete previous fragment */
87da7e66
XG		 6357 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6358 len = min(8u, frag->len);
716d51ab 6359 if (!vcpu->mmio_is_write)
87da7e66
XG		 6360 memcpy(frag->data, run->mmio.data, len);
6361
6362 if (frag->len <= 8) {
6363 /* Switch to the next fragment. */
6364 frag++;
6365 vcpu->mmio_cur_fragment++;
6366 } else {
6367 /* Go forward to the next mmio piece. */
6368 frag->data += len;
6369 frag->gpa += len;
6370 frag->len -= len;
6371 }
6372
a08d3b3b 6373 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6374 vcpu->mmio_needed = 0;
0912c977
PB		 6375
6376 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6377 if (vcpu->mmio_is_write)
716d51ab
GN		 6378 return 1;
6379 vcpu->mmio_read_completed = 1;
6380 return complete_emulated_io(vcpu);
6381 }
87da7e66 6382
716d51ab
GN		 6383 run->exit_reason = KVM_EXIT_MMIO;
6384 run->mmio.phys_addr = frag->gpa;
6385 if (vcpu->mmio_is_write)
87da7e66
XG		 6386 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6387 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6388 run->mmio.is_write = vcpu->mmio_is_write;
6389 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6390 return 0;
5287f194
AK		 6391}
6392
716d51ab 6393
b6c7a5dc
HB		 6394int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6395{
6396 int r;
6397 sigset_t sigsaved;
6398
e5c30142
AK		 6399 if (!tsk_used_math(current) && init_fpu(current))
6400 return -ENOMEM;
6401
ac9f6dc0
AK		 6402 if (vcpu->sigset_active)
6403 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6404
a4535290 6405 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6406 kvm_vcpu_block(vcpu);
66450a21 6407 kvm_apic_accept_events(vcpu);
d7690175 6408 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6409 r = -EAGAIN;
6410 goto out;
b6c7a5dc
HB		 6411 }
6412
b6c7a5dc 6413 /* re-sync apic's tpr */
eea1cff9
AP		 6414 if (!irqchip_in_kernel(vcpu->kvm)) {
6415 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6416 r = -EINVAL;
6417 goto out;
6418 }
6419 }
b6c7a5dc 6420
716d51ab
GN		 6421 if (unlikely(vcpu->arch.complete_userspace_io)) {
6422 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6423 vcpu->arch.complete_userspace_io = NULL;
6424 r = cui(vcpu);
6425 if (r <= 0)
6426 goto out;
6427 } else
6428 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6429
851ba692 6430 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6431
6432out:
f1d86e46 6433 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6434 if (vcpu->sigset_active)
6435 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6436
b6c7a5dc
HB		 6437 return r;
6438}
6439
6440int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6441{
7ae441ea
GN		 6442 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6443 /*
6444 * We are here if userspace calls get_regs() in the middle of
6445 * instruction emulation. Registers state needs to be copied
4a969980 6446 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6447 * that usually, but some bad designed PV devices (vmware
6448 * backdoor interface) need this to work
6449 */
dd856efa 6450 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6451 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6452 }
5fdbf976
MT		 6453 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6454 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6455 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6456 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6457 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6458 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6459 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6460 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6461#ifdef CONFIG_X86_64
5fdbf976
MT		 6462 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6463 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6464 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6465 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6466 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6467 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6468 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6469 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6470#endif
6471
5fdbf976 6472 regs->rip = kvm_rip_read(vcpu);
91586a3b 6473 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6474
b6c7a5dc
HB		 6475 return 0;
6476}
6477
6478int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6479{
7ae441ea
GN		 6480 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6481 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6482
5fdbf976
MT		 6483 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6484 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6485 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6486 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6487 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6488 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6489 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6490 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6491#ifdef CONFIG_X86_64
5fdbf976
MT		 6492 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6493 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6494 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6495 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6496 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6497 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6498 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6499 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6500#endif
6501
5fdbf976 6502 kvm_rip_write(vcpu, regs->rip);
91586a3b 6503 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6504
b4f14abd
JK		 6505 vcpu->arch.exception.pending = false;
6506
3842d135
AK		 6507 kvm_make_request(KVM_REQ_EVENT, vcpu);
6508
b6c7a5dc
HB		 6509 return 0;
6510}
6511
b6c7a5dc
HB		 6512void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6513{
6514 struct kvm_segment cs;
6515
3e6e0aab 6516 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6517 *db = cs.db;
6518 *l = cs.l;
6519}
6520EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6521
6522int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6523 struct kvm_sregs *sregs)
6524{
89a27f4d 6525 struct desc_ptr dt;
b6c7a5dc 6526
3e6e0aab
GT		 6527 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6528 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6529 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6530 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6531 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6532 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6533
3e6e0aab
GT		 6534 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6535 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6536
6537 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6538 sregs->idt.limit = dt.size;
6539 sregs->idt.base = dt.address;
b6c7a5dc 6540 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6541 sregs->gdt.limit = dt.size;
6542 sregs->gdt.base = dt.address;
b6c7a5dc 6543
4d4ec087 6544 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6545 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6546 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6547 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6548 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6549 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6550 sregs->apic_base = kvm_get_apic_base(vcpu);
6551
923c61bb 6552 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6553
36752c9b 6554 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6555 set_bit(vcpu->arch.interrupt.nr,
6556 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6557
b6c7a5dc
HB		 6558 return 0;
6559}
6560
62d9f0db
MT		 6561int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6562 struct kvm_mp_state *mp_state)
6563{
66450a21 6564 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6565 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6566 vcpu->arch.pv.pv_unhalted)
6567 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6568 else
6569 mp_state->mp_state = vcpu->arch.mp_state;
6570
62d9f0db
MT		 6571 return 0;
6572}
6573
6574int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6575 struct kvm_mp_state *mp_state)
6576{
66450a21
JK		 6577 if (!kvm_vcpu_has_lapic(vcpu) &&
6578 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6579 return -EINVAL;
6580
6581 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6582 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6583 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6584 } else
6585 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6586 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6587 return 0;
6588}
6589
7f3d35fd
KW		 6590int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6591 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6592{
9d74191a 6593 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6594 int ret;
e01c2426 6595
8ec4722d 6596 init_emulate_ctxt(vcpu);
c697518a 6597
7f3d35fd 6598 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6599 has_error_code, error_code);
c697518a 6600
c697518a 6601 if (ret)
19d04437 6602 return EMULATE_FAIL;
37817f29 6603
9d74191a
TY		 6604 kvm_rip_write(vcpu, ctxt->eip);
6605 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6606 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6607 return EMULATE_DONE;
37817f29
IE		 6608}
6609EXPORT_SYMBOL_GPL(kvm_task_switch);
6610
b6c7a5dc
HB		 6611int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6612 struct kvm_sregs *sregs)
6613{
58cb628d 6614 struct msr_data apic_base_msr;
b6c7a5dc 6615 int mmu_reset_needed = 0;
63f42e02 6616 int pending_vec, max_bits, idx;
89a27f4d 6617 struct desc_ptr dt;
b6c7a5dc 6618
6d1068b3
PM		 6619 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6620 return -EINVAL;
6621
89a27f4d
GN		 6622 dt.size = sregs->idt.limit;
6623 dt.address = sregs->idt.base;
b6c7a5dc 6624 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6625 dt.size = sregs->gdt.limit;
6626 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6627 kvm_x86_ops->set_gdt(vcpu, &dt);
6628
ad312c7c 6629 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6630 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6631 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6632 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6633
2d3ad1f4 6634 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6635
f6801dff 6636 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6637 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6638 apic_base_msr.data = sregs->apic_base;
6639 apic_base_msr.host_initiated = true;
6640 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6641
4d4ec087 6642 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6643 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6644 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6645
fc78f519 6646 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6647 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6648 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6649 kvm_update_cpuid(vcpu);
63f42e02
XG		 6650
6651 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6652 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6653 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6654 mmu_reset_needed = 1;
6655 }
63f42e02 6656 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6657
6658 if (mmu_reset_needed)
6659 kvm_mmu_reset_context(vcpu);
6660
a50abc3b 6661 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6662 pending_vec = find_first_bit(
6663 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6664 if (pending_vec < max_bits) {
66fd3f7f 6665 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6666 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6667 }
6668
3e6e0aab
GT		 6669 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6670 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6671 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6672 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6673 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6674 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6675
3e6e0aab
GT		 6676 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6677 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6678
5f0269f5
ME		 6679 update_cr8_intercept(vcpu);
6680
9c3e4aab 6681 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6682 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6683 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6684 !is_protmode(vcpu))
9c3e4aab
MT		 6685 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6686
3842d135
AK		 6687 kvm_make_request(KVM_REQ_EVENT, vcpu);
6688
b6c7a5dc
HB		 6689 return 0;
6690}
6691
d0bfb940
JK		 6692int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6693 struct kvm_guest_debug *dbg)
b6c7a5dc 6694{
355be0b9 6695 unsigned long rflags;
ae675ef0 6696 int i, r;
b6c7a5dc 6697
4f926bf2
JK		 6698 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6699 r = -EBUSY;
6700 if (vcpu->arch.exception.pending)
2122ff5e 6701 goto out;
4f926bf2
JK		 6702 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6703 kvm_queue_exception(vcpu, DB_VECTOR);
6704 else
6705 kvm_queue_exception(vcpu, BP_VECTOR);
6706 }
6707
91586a3b
JK		 6708 /*
6709 * Read rflags as long as potentially injected trace flags are still
6710 * filtered out.
6711 */
6712 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6713
6714 vcpu->guest_debug = dbg->control;
6715 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6716 vcpu->guest_debug = 0;
6717
6718 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6719 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6720 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6721 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6722 } else {
6723 for (i = 0; i < KVM_NR_DB_REGS; i++)
6724 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6725 }
c8639010 6726 kvm_update_dr7(vcpu);
ae675ef0 6727
f92653ee
JK		 6728 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6729 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6730 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6731
91586a3b
JK		 6732 /*
6733 * Trigger an rflags update that will inject or remove the trace
6734 * flags.
6735 */
6736 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6737
c8639010 6738 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6739
4f926bf2 6740 r = 0;
d0bfb940 6741
2122ff5e 6742out:
b6c7a5dc
HB		 6743
6744 return r;
6745}
6746
8b006791
ZX		 6747/*
6748 * Translate a guest virtual address to a guest physical address.
6749 */
6750int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6751 struct kvm_translation *tr)
6752{
6753 unsigned long vaddr = tr->linear_address;
6754 gpa_t gpa;
f656ce01 6755 int idx;
8b006791 6756
f656ce01 6757 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6758 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6759 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6760 tr->physical_address = gpa;
6761 tr->valid = gpa != UNMAPPED_GVA;
6762 tr->writeable = 1;
6763 tr->usermode = 0;
8b006791
ZX		 6764
6765 return 0;
6766}
6767
d0752060
HB		 6768int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6769{
98918833
SY		 6770 struct i387_fxsave_struct *fxsave =
6771 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6772
d0752060
HB		 6773 memcpy(fpu->fpr, fxsave->st_space, 128);
6774 fpu->fcw = fxsave->cwd;
6775 fpu->fsw = fxsave->swd;
6776 fpu->ftwx = fxsave->twd;
6777 fpu->last_opcode = fxsave->fop;
6778 fpu->last_ip = fxsave->rip;
6779 fpu->last_dp = fxsave->rdp;
6780 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6781
d0752060
HB		 6782 return 0;
6783}
6784
6785int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6786{
98918833
SY		 6787 struct i387_fxsave_struct *fxsave =
6788 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6789
d0752060
HB		 6790 memcpy(fxsave->st_space, fpu->fpr, 128);
6791 fxsave->cwd = fpu->fcw;
6792 fxsave->swd = fpu->fsw;
6793 fxsave->twd = fpu->ftwx;
6794 fxsave->fop = fpu->last_opcode;
6795 fxsave->rip = fpu->last_ip;
6796 fxsave->rdp = fpu->last_dp;
6797 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6798
d0752060
HB		 6799 return 0;
6800}
6801
10ab25cd 6802int fx_init(struct kvm_vcpu *vcpu)
d0752060 6803{
10ab25cd
JK		 6804 int err;
6805
6806 err = fpu_alloc(&vcpu->arch.guest_fpu);
6807 if (err)
6808 return err;
6809
98918833 6810 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6811
2acf923e
DC		 6812 /*
6813 * Ensure guest xcr0 is valid for loading
6814 */
6815 vcpu->arch.xcr0 = XSTATE_FP;
6816
ad312c7c 6817 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6818
6819 return 0;
d0752060
HB		 6820}
6821EXPORT_SYMBOL_GPL(fx_init);
6822
98918833
SY		 6823static void fx_free(struct kvm_vcpu *vcpu)
6824{
6825 fpu_free(&vcpu->arch.guest_fpu);
6826}
6827
d0752060
HB		 6828void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6829{
2608d7a1 6830 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6831 return;
6832
2acf923e
DC		 6833 /*
6834 * Restore all possible states in the guest,
6835 * and assume host would use all available bits.
6836 * Guest xcr0 would be loaded later.
6837 */
6838 kvm_put_guest_xcr0(vcpu);
d0752060 6839 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6840 __kernel_fpu_begin();
98918833 6841 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6842 trace_kvm_fpu(1);
d0752060 6843}
d0752060
HB		 6844
6845void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6846{
2acf923e
DC		 6847 kvm_put_guest_xcr0(vcpu);
6848
d0752060
HB		 6849 if (!vcpu->guest_fpu_loaded)
6850 return;
6851
6852 vcpu->guest_fpu_loaded = 0;
98918833 6853 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6854 __kernel_fpu_end();
f096ed85 6855 ++vcpu->stat.fpu_reload;
a8eeb04a 6856 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6857 trace_kvm_fpu(0);
d0752060 6858}
e9b11c17
ZX		 6859
6860void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6861{
12f9a48f 6862 kvmclock_reset(vcpu);
7f1ea208 6863
f5f48ee1 6864 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6865 fx_free(vcpu);
e9b11c17
ZX		 6866 kvm_x86_ops->vcpu_free(vcpu);
6867}
6868
6869struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6870 unsigned int id)
6871{
6755bae8
ZA		 6872 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6873 printk_once(KERN_WARNING
6874 "kvm: SMP vm created on host with unstable TSC; "
6875 "guest TSC will not be reliable\n");
26e5215f
AK		 6876 return kvm_x86_ops->vcpu_create(kvm, id);
6877}
e9b11c17 6878
26e5215f
AK		 6879int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6880{
6881 int r;
e9b11c17 6882
0bed3b56 6883 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6884 r = vcpu_load(vcpu);
6885 if (r)
6886 return r;
57f252f2 6887 kvm_vcpu_reset(vcpu);
8a3c1a33 6888 kvm_mmu_setup(vcpu);
e9b11c17 6889 vcpu_put(vcpu);
e9b11c17 6890
26e5215f 6891 return r;
e9b11c17
ZX		 6892}
6893
42897d86
MT		 6894int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6895{
6896 int r;
8fe8ab46 6897 struct msr_data msr;
332967a3 6898 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6899
6900 r = vcpu_load(vcpu);
6901 if (r)
6902 return r;
8fe8ab46
WA		 6903 msr.data = 0x0;
6904 msr.index = MSR_IA32_TSC;
6905 msr.host_initiated = true;
6906 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6907 vcpu_put(vcpu);
6908
332967a3
AJ		 6909 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6910 KVMCLOCK_SYNC_PERIOD);
6911
42897d86
MT		 6912 return r;
6913}
6914
d40ccc62 6915void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6916{
9fc77441 6917 int r;
344d9588
GN		 6918 vcpu->arch.apf.msr_val = 0;
6919
9fc77441
MT		 6920 r = vcpu_load(vcpu);
6921 BUG_ON(r);
e9b11c17
ZX		 6922 kvm_mmu_unload(vcpu);
6923 vcpu_put(vcpu);
6924
98918833 6925 fx_free(vcpu);
e9b11c17
ZX		 6926 kvm_x86_ops->vcpu_free(vcpu);
6927}
6928
66450a21 6929void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6930{
7460fb4a
AK		 6931 atomic_set(&vcpu->arch.nmi_queued, 0);
6932 vcpu->arch.nmi_pending = 0;
448fa4a9 6933 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6934 kvm_clear_interrupt_queue(vcpu);
6935 kvm_clear_exception_queue(vcpu);
448fa4a9 6936
42dbaa5a 6937 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6938 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6939 kvm_update_dr6(vcpu);
42dbaa5a 6940 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6941 kvm_update_dr7(vcpu);
42dbaa5a 6942
3842d135 6943 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6944 vcpu->arch.apf.msr_val = 0;
c9aaa895 6945 vcpu->arch.st.msr_val = 0;
3842d135 6946
12f9a48f
GC		 6947 kvmclock_reset(vcpu);
6948
af585b92
GN		 6949 kvm_clear_async_pf_completion_queue(vcpu);
6950 kvm_async_pf_hash_reset(vcpu);
6951 vcpu->arch.apf.halted = false;
3842d135 6952
f5132b01
GN		 6953 kvm_pmu_reset(vcpu);
6954
66f7b72e
JS		 6955 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6956 vcpu->arch.regs_avail = ~0;
6957 vcpu->arch.regs_dirty = ~0;
6958
57f252f2 6959 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6960}
6961
66450a21
JK		 6962void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6963{
6964 struct kvm_segment cs;
6965
6966 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6967 cs.selector = vector << 8;
6968 cs.base = vector << 12;
6969 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6970 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6971}
6972
13a34e06 6973int kvm_arch_hardware_enable(void)
e9b11c17 6974{
ca84d1a2
ZA		 6975 struct kvm *kvm;
6976 struct kvm_vcpu *vcpu;
6977 int i;
0dd6a6ed
ZA		 6978 int ret;
6979 u64 local_tsc;
6980 u64 max_tsc = 0;
6981 bool stable, backwards_tsc = false;
18863bdd
AK		 6982
6983 kvm_shared_msr_cpu_online();
13a34e06 6984 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 6985 if (ret != 0)
6986 return ret;
6987
6988 local_tsc = native_read_tsc();
6989 stable = !check_tsc_unstable();
6990 list_for_each_entry(kvm, &vm_list, vm_list) {
6991 kvm_for_each_vcpu(i, vcpu, kvm) {
6992 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 6993 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 6994 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6995 backwards_tsc = true;
6996 if (vcpu->arch.last_host_tsc > max_tsc)
6997 max_tsc = vcpu->arch.last_host_tsc;
6998 }
6999 }
7000 }
7001
7002 /*
7003 * Sometimes, even reliable TSCs go backwards. This happens on
7004 * platforms that reset TSC during suspend or hibernate actions, but
7005 * maintain synchronization. We must compensate. Fortunately, we can
7006 * detect that condition here, which happens early in CPU bringup,
7007 * before any KVM threads can be running. Unfortunately, we can't
7008 * bring the TSCs fully up to date with real time, as we aren't yet far
7009 * enough into CPU bringup that we know how much real time has actually
7010 * elapsed; our helper function, get_kernel_ns() will be using boot
7011 * variables that haven't been updated yet.
7012 *
7013 * So we simply find the maximum observed TSC above, then record the
7014 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7015 * the adjustment will be applied. Note that we accumulate
7016 * adjustments, in case multiple suspend cycles happen before some VCPU
7017 * gets a chance to run again. In the event that no KVM threads get a
7018 * chance to run, we will miss the entire elapsed period, as we'll have
7019 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7020 * loose cycle time. This isn't too big a deal, since the loss will be
7021 * uniform across all VCPUs (not to mention the scenario is extremely
7022 * unlikely). It is possible that a second hibernate recovery happens
7023 * much faster than a first, causing the observed TSC here to be
7024 * smaller; this would require additional padding adjustment, which is
7025 * why we set last_host_tsc to the local tsc observed here.
7026 *
7027 * N.B. - this code below runs only on platforms with reliable TSC,
7028 * as that is the only way backwards_tsc is set above. Also note
7029 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7030 * have the same delta_cyc adjustment applied if backwards_tsc
7031 * is detected. Note further, this adjustment is only done once,
7032 * as we reset last_host_tsc on all VCPUs to stop this from being
7033 * called multiple times (one for each physical CPU bringup).
7034 *
4a969980 7035 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7036 * will be compensated by the logic in vcpu_load, which sets the TSC to
7037 * catchup mode. This will catchup all VCPUs to real time, but cannot
7038 * guarantee that they stay in perfect synchronization.
7039 */
7040 if (backwards_tsc) {
7041 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7042 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7043 list_for_each_entry(kvm, &vm_list, vm_list) {
7044 kvm_for_each_vcpu(i, vcpu, kvm) {
7045 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7046 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7047 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7048 }
7049
7050 /*
7051 * We have to disable TSC offset matching.. if you were
7052 * booting a VM while issuing an S4 host suspend....
7053 * you may have some problem. Solving this issue is
7054 * left as an exercise to the reader.
7055 */
7056 kvm->arch.last_tsc_nsec = 0;
7057 kvm->arch.last_tsc_write = 0;
7058 }
7059
7060 }
7061 return 0;
e9b11c17
ZX		 7062}
7063
13a34e06 7064void kvm_arch_hardware_disable(void)
e9b11c17 7065{
13a34e06
RK		 7066 kvm_x86_ops->hardware_disable();
7067 drop_user_return_notifiers();
e9b11c17
ZX		 7068}
7069
7070int kvm_arch_hardware_setup(void)
7071{
7072 return kvm_x86_ops->hardware_setup();
7073}
7074
7075void kvm_arch_hardware_unsetup(void)
7076{
7077 kvm_x86_ops->hardware_unsetup();
7078}
7079
7080void kvm_arch_check_processor_compat(void *rtn)
7081{
7082 kvm_x86_ops->check_processor_compatibility(rtn);
7083}
7084
3e515705
AK		 7085bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7086{
7087 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7088}
7089
54e9818f
GN		 7090struct static_key kvm_no_apic_vcpu __read_mostly;
7091
e9b11c17
ZX		 7092int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7093{
7094 struct page *page;
7095 struct kvm *kvm;
7096 int r;
7097
7098 BUG_ON(vcpu->kvm == NULL);
7099 kvm = vcpu->kvm;
7100
6aef266c 7101 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7102 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7103 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7104 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7105 else
a4535290 7106 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7107
7108 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7109 if (!page) {
7110 r = -ENOMEM;
7111 goto fail;
7112 }
ad312c7c 7113 vcpu->arch.pio_data = page_address(page);
e9b11c17 7114
cc578287 7115 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7116
e9b11c17
ZX		 7117 r = kvm_mmu_create(vcpu);
7118 if (r < 0)
7119 goto fail_free_pio_data;
7120
7121 if (irqchip_in_kernel(kvm)) {
7122 r = kvm_create_lapic(vcpu);
7123 if (r < 0)
7124 goto fail_mmu_destroy;
54e9818f
GN		 7125 } else
7126 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7127
890ca9ae
HY		 7128 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7129 GFP_KERNEL);
7130 if (!vcpu->arch.mce_banks) {
7131 r = -ENOMEM;
443c39bc 7132 goto fail_free_lapic;
890ca9ae
HY		 7133 }
7134 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7135
f1797359
WY		 7136 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7137 r = -ENOMEM;
f5f48ee1 7138 goto fail_free_mce_banks;
f1797359 7139 }
f5f48ee1 7140
66f7b72e
JS		 7141 r = fx_init(vcpu);
7142 if (r)
7143 goto fail_free_wbinvd_dirty_mask;
7144
ba904635 7145 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7146 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7147
7148 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7149 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7150
af585b92 7151 kvm_async_pf_hash_reset(vcpu);
f5132b01 7152 kvm_pmu_init(vcpu);
af585b92 7153
e9b11c17 7154 return 0;
66f7b72e
JS		 7155fail_free_wbinvd_dirty_mask:
7156 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7157fail_free_mce_banks:
7158 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7159fail_free_lapic:
7160 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7161fail_mmu_destroy:
7162 kvm_mmu_destroy(vcpu);
7163fail_free_pio_data:
ad312c7c 7164 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7165fail:
7166 return r;
7167}
7168
7169void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7170{
f656ce01
MT		 7171 int idx;
7172
f5132b01 7173 kvm_pmu_destroy(vcpu);
36cb93fd 7174 kfree(vcpu->arch.mce_banks);
e9b11c17 7175 kvm_free_lapic(vcpu);
f656ce01 7176 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7177 kvm_mmu_destroy(vcpu);
f656ce01 7178 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7179 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7180 if (!irqchip_in_kernel(vcpu->kvm))
7181 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7182}
d19a9cd2 7183
e790d9ef
RK		 7184void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7185{
ae97a3b8 7186 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7187}
7188
e08b9637 7189int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7190{
e08b9637
CO		 7191 if (type)
7192 return -EINVAL;
7193
f05e70ac 7194 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7195 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7196 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7197 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7198
5550af4d
SY		 7199 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7200 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7201 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7202 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7203 &kvm->arch.irq_sources_bitmap);
5550af4d 7204
038f8c11 7205 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7206 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7207 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7208
7209 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7210
7e44e449 7211 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7212 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7213
d89f5eff 7214 return 0;
d19a9cd2
ZX		 7215}
7216
7217static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7218{
9fc77441
MT		 7219 int r;
7220 r = vcpu_load(vcpu);
7221 BUG_ON(r);
d19a9cd2
ZX		 7222 kvm_mmu_unload(vcpu);
7223 vcpu_put(vcpu);
7224}
7225
7226static void kvm_free_vcpus(struct kvm *kvm)
7227{
7228 unsigned int i;
988a2cae 7229 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7230
7231 /*
7232 * Unpin any mmu pages first.
7233 */
af585b92
GN		 7234 kvm_for_each_vcpu(i, vcpu, kvm) {
7235 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7236 kvm_unload_vcpu_mmu(vcpu);
af585b92 7237 }
988a2cae
GN		 7238 kvm_for_each_vcpu(i, vcpu, kvm)
7239 kvm_arch_vcpu_free(vcpu);
7240
7241 mutex_lock(&kvm->lock);
7242 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7243 kvm->vcpus[i] = NULL;
d19a9cd2 7244
988a2cae
GN		 7245 atomic_set(&kvm->online_vcpus, 0);
7246 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7247}
7248
ad8ba2cd
SY		 7249void kvm_arch_sync_events(struct kvm *kvm)
7250{
332967a3 7251 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7252 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7253 kvm_free_all_assigned_devices(kvm);
aea924f6 7254 kvm_free_pit(kvm);
ad8ba2cd
SY		 7255}
7256
d19a9cd2
ZX		 7257void kvm_arch_destroy_vm(struct kvm *kvm)
7258{
27469d29
AH		 7259 if (current->mm == kvm->mm) {
7260 /*
7261 * Free memory regions allocated on behalf of userspace,
7262 * unless the the memory map has changed due to process exit
7263 * or fd copying.
7264 */
7265 struct kvm_userspace_memory_region mem;
7266 memset(&mem, 0, sizeof(mem));
7267 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7268 kvm_set_memory_region(kvm, &mem);
7269
7270 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7271 kvm_set_memory_region(kvm, &mem);
7272
7273 mem.slot = TSS_PRIVATE_MEMSLOT;
7274 kvm_set_memory_region(kvm, &mem);
7275 }
6eb55818 7276 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7277 kfree(kvm->arch.vpic);
7278 kfree(kvm->arch.vioapic);
d19a9cd2 7279 kvm_free_vcpus(kvm);
3d45830c
AK		 7280 if (kvm->arch.apic_access_page)
7281 put_page(kvm->arch.apic_access_page);
1e08ec4a 7282 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7283}
0de10343 7284
5587027c 7285void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7286 struct kvm_memory_slot *dont)
7287{
7288 int i;
7289
d89cc617
TY		 7290 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7291 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7292 kvm_kvfree(free->arch.rmap[i]);
7293 free->arch.rmap[i] = NULL;
77d11309 7294 }
d89cc617
TY		 7295 if (i == 0)
7296 continue;
7297
7298 if (!dont || free->arch.lpage_info[i - 1] !=
7299 dont->arch.lpage_info[i - 1]) {
7300 kvm_kvfree(free->arch.lpage_info[i - 1]);
7301 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7302 }
7303 }
7304}
7305
5587027c
AK		 7306int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7307 unsigned long npages)
db3fe4eb
TY		 7308{
7309 int i;
7310
d89cc617 7311 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7312 unsigned long ugfn;
7313 int lpages;
d89cc617 7314 int level = i + 1;
db3fe4eb
TY		 7315
7316 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7317 slot->base_gfn, level) + 1;
7318
d89cc617
TY		 7319 slot->arch.rmap[i] =
7320 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7321 if (!slot->arch.rmap[i])
77d11309 7322 goto out_free;
d89cc617
TY		 7323 if (i == 0)
7324 continue;
77d11309 7325
d89cc617
TY		 7326 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7327 sizeof(*slot->arch.lpage_info[i - 1]));
7328 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7329 goto out_free;
7330
7331 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7332 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7333 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7334 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7335 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7336 /*
7337 * If the gfn and userspace address are not aligned wrt each
7338 * other, or if explicitly asked to, disable large page
7339 * support for this slot
7340 */
7341 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7342 !kvm_largepages_enabled()) {
7343 unsigned long j;
7344
7345 for (j = 0; j < lpages; ++j)
d89cc617 7346 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7347 }
7348 }
7349
7350 return 0;
7351
7352out_free:
d89cc617
TY		 7353 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7354 kvm_kvfree(slot->arch.rmap[i]);
7355 slot->arch.rmap[i] = NULL;
7356 if (i == 0)
7357 continue;
7358
7359 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7360 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7361 }
7362 return -ENOMEM;
7363}
7364
e59dbe09
TY		 7365void kvm_arch_memslots_updated(struct kvm *kvm)
7366{
e6dff7d1
TY		 7367 /*
7368 * memslots->generation has been incremented.
7369 * mmio generation may have reached its maximum value.
7370 */
7371 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7372}
7373
f7784b8e
MT		 7374int kvm_arch_prepare_memory_region(struct kvm *kvm,
7375 struct kvm_memory_slot *memslot,
f7784b8e 7376 struct kvm_userspace_memory_region *mem,
7b6195a9 7377 enum kvm_mr_change change)
0de10343 7378{
7a905b14
TY		 7379 /*
7380 * Only private memory slots need to be mapped here since
7381 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7382 */
7b6195a9 7383 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7384 unsigned long userspace_addr;
604b38ac 7385
7a905b14
TY		 7386 /*
7387 * MAP_SHARED to prevent internal slot pages from being moved
7388 * by fork()/COW.
7389 */
7b6195a9 7390 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7391 PROT_READ | PROT_WRITE,
7392 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7393
7a905b14
TY		 7394 if (IS_ERR((void *)userspace_addr))
7395 return PTR_ERR((void *)userspace_addr);
604b38ac 7396
7a905b14 7397 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7398 }
7399
f7784b8e
MT		 7400 return 0;
7401}
7402
7403void kvm_arch_commit_memory_region(struct kvm *kvm,
7404 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7405 const struct kvm_memory_slot *old,
7406 enum kvm_mr_change change)
f7784b8e
MT		 7407{
7408
8482644a 7409 int nr_mmu_pages = 0;
f7784b8e 7410
8482644a 7411 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7412 int ret;
7413
8482644a
TY		 7414 ret = vm_munmap(old->userspace_addr,
7415 old->npages * PAGE_SIZE);
f7784b8e
MT		 7416 if (ret < 0)
7417 printk(KERN_WARNING
7418 "kvm_vm_ioctl_set_memory_region: "
7419 "failed to munmap memory\n");
7420 }
7421
48c0e4e9
XG		 7422 if (!kvm->arch.n_requested_mmu_pages)
7423 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7424
48c0e4e9 7425 if (nr_mmu_pages)
0de10343 7426 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7427 /*
7428 * Write protect all pages for dirty logging.
c126d94f
XG		 7429 *
7430 * All the sptes including the large sptes which point to this
7431 * slot are set to readonly. We can not create any new large
7432 * spte on this slot until the end of the logging.
7433 *
7434 * See the comments in fast_page_fault().
c972f3b1 7435 */
8482644a 7436 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7437 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7438}
1d737c8a 7439
2df72e9b 7440void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7441{
6ca18b69 7442 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7443}
7444
2df72e9b
MT		 7445void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7446 struct kvm_memory_slot *slot)
7447{
6ca18b69 7448 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7449}
7450
1d737c8a
ZX		 7451int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7452{
b6b8a145
JK		 7453 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7454 kvm_x86_ops->check_nested_events(vcpu, false);
7455
af585b92
GN		 7456 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7457 !vcpu->arch.apf.halted)
7458 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7459 || kvm_apic_has_events(vcpu)
6aef266c 7460 || vcpu->arch.pv.pv_unhalted
7460fb4a 7461 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7462 (kvm_arch_interrupt_allowed(vcpu) &&
7463 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7464}
5736199a 7465
b6d33834 7466int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7467{
b6d33834 7468 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7469}
78646121
GN		 7470
7471int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7472{
7473 return kvm_x86_ops->interrupt_allowed(vcpu);
7474}
229456fc 7475
f92653ee
JK		 7476bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7477{
7478 unsigned long current_rip = kvm_rip_read(vcpu) +
7479 get_segment_base(vcpu, VCPU_SREG_CS);
7480
7481 return current_rip == linear_rip;
7482}
7483EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7484
94fe45da
JK		 7485unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7486{
7487 unsigned long rflags;
7488
7489 rflags = kvm_x86_ops->get_rflags(vcpu);
7490 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7491 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7492 return rflags;
7493}
7494EXPORT_SYMBOL_GPL(kvm_get_rflags);
7495
6addfc42 7496static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7497{
7498 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7499 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7500 rflags |= X86_EFLAGS_TF;
94fe45da 7501 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7502}
7503
7504void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7505{
7506 __kvm_set_rflags(vcpu, rflags);
3842d135 7507 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7508}
7509EXPORT_SYMBOL_GPL(kvm_set_rflags);
7510
56028d08
GN		 7511void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7512{
7513 int r;
7514
fb67e14f 7515 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7516 work->wakeup_all)
56028d08
GN		 7517 return;
7518
7519 r = kvm_mmu_reload(vcpu);
7520 if (unlikely(r))
7521 return;
7522
fb67e14f
XG		 7523 if (!vcpu->arch.mmu.direct_map &&
7524 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7525 return;
7526
56028d08
GN		 7527 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7528}
7529
af585b92
GN		 7530static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7531{
7532 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7533}
7534
7535static inline u32 kvm_async_pf_next_probe(u32 key)
7536{
7537 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7538}
7539
7540static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7541{
7542 u32 key = kvm_async_pf_hash_fn(gfn);
7543
7544 while (vcpu->arch.apf.gfns[key] != ~0)
7545 key = kvm_async_pf_next_probe(key);
7546
7547 vcpu->arch.apf.gfns[key] = gfn;
7548}
7549
7550static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7551{
7552 int i;
7553 u32 key = kvm_async_pf_hash_fn(gfn);
7554
7555 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7556 (vcpu->arch.apf.gfns[key] != gfn &&
7557 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7558 key = kvm_async_pf_next_probe(key);
7559
7560 return key;
7561}
7562
7563bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7564{
7565 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7566}
7567
7568static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7569{
7570 u32 i, j, k;
7571
7572 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7573 while (true) {
7574 vcpu->arch.apf.gfns[i] = ~0;
7575 do {
7576 j = kvm_async_pf_next_probe(j);
7577 if (vcpu->arch.apf.gfns[j] == ~0)
7578 return;
7579 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7580 /*
7581 * k lies cyclically in ]i,j]
7582 * | i.k.j |
7583 * |....j i.k.| or |.k..j i...|
7584 */
7585 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7586 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7587 i = j;
7588 }
7589}
7590
7c90705b
GN		 7591static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7592{
7593
7594 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7595 sizeof(val));
7596}
7597
af585b92
GN		 7598void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7599 struct kvm_async_pf *work)
7600{
6389ee94
AK		 7601 struct x86_exception fault;
7602
7c90705b 7603 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7604 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7605
7606 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7607 (vcpu->arch.apf.send_user_only &&
7608 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7609 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7610 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7611 fault.vector = PF_VECTOR;
7612 fault.error_code_valid = true;
7613 fault.error_code = 0;
7614 fault.nested_page_fault = false;
7615 fault.address = work->arch.token;
7616 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7617 }
af585b92
GN		 7618}
7619
7620void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7621 struct kvm_async_pf *work)
7622{
6389ee94
AK		 7623 struct x86_exception fault;
7624
7c90705b 7625 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7626 if (work->wakeup_all)
7c90705b
GN		 7627 work->arch.token = ~0; /* broadcast wakeup */
7628 else
7629 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7630
7631 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7632 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7633 fault.vector = PF_VECTOR;
7634 fault.error_code_valid = true;
7635 fault.error_code = 0;
7636 fault.nested_page_fault = false;
7637 fault.address = work->arch.token;
7638 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7639 }
e6d53e3b 7640 vcpu->arch.apf.halted = false;
a4fa1635 7641 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7642}
7643
7644bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7645{
7646 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7647 return true;
7648 else
7649 return !kvm_event_needs_reinjection(vcpu) &&
7650 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7651}
7652
e0f0bbc5
AW		 7653void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7654{
7655 atomic_inc(&kvm->arch.noncoherent_dma_count);
7656}
7657EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7658
7659void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7660{
7661 atomic_dec(&kvm->arch.noncoherent_dma_count);
7662}
7663EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7664
7665bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7666{
7667 return atomic_read(&kvm->arch.noncoherent_dma_count);
7668}
7669EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7670
229456fc
MT		 7671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7672EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7675EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7676EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7677EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7678EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7679EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
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