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KVM: x86: avoid write-tearing of TDP
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 165 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 166 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 167 { "request_irq", VCPU_STAT(request_irq_exits) },
168 { "irq_exits", VCPU_STAT(irq_exits) },
169 { "host_state_reload", VCPU_STAT(host_state_reload) },
170 { "efer_reload", VCPU_STAT(efer_reload) },
171 { "fpu_reload", VCPU_STAT(fpu_reload) },
172 { "insn_emulation", VCPU_STAT(insn_emulation) },
173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 174 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 175 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
177 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
180 { "mmu_flooded", VM_STAT(mmu_flooded) },
181 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 183 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 185 { "largepages", VM_STAT(lpages) },
417bc304
HB		 186 { NULL }
187};
188
2acf923e
DC		 189u64 __read_mostly host_xcr0;
190
b6785def 191static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 192
af585b92
GN		 193static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
194{
195 int i;
196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
197 vcpu->arch.apf.gfns[i] = ~0;
198}
199
18863bdd
AK		 200static void kvm_on_user_return(struct user_return_notifier *urn)
201{
202 unsigned slot;
18863bdd
AK		 203 struct kvm_shared_msrs *locals
204 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 205 struct kvm_shared_msr_values *values;
18863bdd
AK		 206
207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 208 values = &locals->values[slot];
209 if (values->host != values->curr) {
210 wrmsrl(shared_msrs_global.msrs[slot], values->host);
211 values->curr = values->host;
18863bdd
AK		 212 }
213 }
214 locals->registered = false;
215 user_return_notifier_unregister(urn);
216}
217
2bf78fa7 218static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 219{
18863bdd 220 u64 value;
013f6a5d
MT		 221 unsigned int cpu = smp_processor_id();
222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 223
2bf78fa7
SY		 224 /* only read, and nobody should modify it at this time,
225 * so don't need lock */
226 if (slot >= shared_msrs_global.nr) {
227 printk(KERN_ERR "kvm: invalid MSR slot!");
228 return;
229 }
230 rdmsrl_safe(msr, &value);
231 smsr->values[slot].host = value;
232 smsr->values[slot].curr = value;
233}
234
235void kvm_define_shared_msr(unsigned slot, u32 msr)
236{
0123be42 237 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 238 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 239 if (slot >= shared_msrs_global.nr)
240 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 241}
242EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
243
244static void kvm_shared_msr_cpu_online(void)
245{
246 unsigned i;
18863bdd
AK		 247
248 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 249 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 250}
251
8b3c3104 252int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 253{
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 256 int err;
18863bdd 257
2bf78fa7 258 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 259 return 0;
2bf78fa7 260 smsr->values[slot].curr = value;
8b3c3104
AH		 261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
262 if (err)
263 return 1;
264
18863bdd
AK		 265 if (!smsr->registered) {
266 smsr->urn.on_user_return = kvm_on_user_return;
267 user_return_notifier_register(&smsr->urn);
268 smsr->registered = true;
269 }
8b3c3104 270 return 0;
18863bdd
AK		 271}
272EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
273
13a34e06 274static void drop_user_return_notifiers(void)
3548bab5 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 278
279 if (smsr->registered)
280 kvm_on_user_return(&smsr->urn);
281}
282
6866b83e
CO		 283u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
284{
8a5a87d9 285 return vcpu->arch.apic_base;
6866b83e
CO		 286}
287EXPORT_SYMBOL_GPL(kvm_get_apic_base);
288
58cb628d
JK		 289int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
290{
291 u64 old_state = vcpu->arch.apic_base &
292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
293 u64 new_state = msr_info->data &
294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
297
298 if (!msr_info->host_initiated &&
299 ((msr_info->data & reserved_bits) != 0 ||
300 new_state == X2APIC_ENABLE ||
301 (new_state == MSR_IA32_APICBASE_ENABLE &&
302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
304 old_state == 0)))
305 return 1;
306
307 kvm_lapic_set_base(vcpu, msr_info->data);
308 return 0;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_set_apic_base);
311
2605fc21 312asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 313{
314 /* Fault while not rebooting. We want the trace. */
315 BUG();
316}
317EXPORT_SYMBOL_GPL(kvm_spurious_fault);
318
3fd28fce
ED		 319#define EXCPT_BENIGN 0
320#define EXCPT_CONTRIBUTORY 1
321#define EXCPT_PF 2
322
323static int exception_class(int vector)
324{
325 switch (vector) {
326 case PF_VECTOR:
327 return EXCPT_PF;
328 case DE_VECTOR:
329 case TS_VECTOR:
330 case NP_VECTOR:
331 case SS_VECTOR:
332 case GP_VECTOR:
333 return EXCPT_CONTRIBUTORY;
334 default:
335 break;
336 }
337 return EXCPT_BENIGN;
338}
339
d6e8c854
NA		 340#define EXCPT_FAULT 0
341#define EXCPT_TRAP 1
342#define EXCPT_ABORT 2
343#define EXCPT_INTERRUPT 3
344
345static int exception_type(int vector)
346{
347 unsigned int mask;
348
349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
350 return EXCPT_INTERRUPT;
351
352 mask = 1 << vector;
353
354 /* #DB is trap, as instruction watchpoints are handled elsewhere */
355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
356 return EXCPT_TRAP;
357
358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
359 return EXCPT_ABORT;
360
361 /* Reserved exceptions will result in fault */
362 return EXCPT_FAULT;
363}
364
3fd28fce 365static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 366 unsigned nr, bool has_error, u32 error_code,
367 bool reinject)
3fd28fce
ED		 368{
369 u32 prev_nr;
370 int class1, class2;
371
3842d135
AK		 372 kvm_make_request(KVM_REQ_EVENT, vcpu);
373
3fd28fce
ED		 374 if (!vcpu->arch.exception.pending) {
375 queue:
3ffb2468
NA		 376 if (has_error && !is_protmode(vcpu))
377 has_error = false;
3fd28fce
ED		 378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = has_error;
380 vcpu->arch.exception.nr = nr;
381 vcpu->arch.exception.error_code = error_code;
3f0fd292 382 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 383 return;
384 }
385
386 /* to check exception */
387 prev_nr = vcpu->arch.exception.nr;
388 if (prev_nr == DF_VECTOR) {
389 /* triple fault -> shutdown */
a8eeb04a 390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 391 return;
392 }
393 class1 = exception_class(prev_nr);
394 class2 = exception_class(nr);
395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
397 /* generate double fault per SDM Table 5-5 */
398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = true;
400 vcpu->arch.exception.nr = DF_VECTOR;
401 vcpu->arch.exception.error_code = 0;
402 } else
403 /* replace previous exception with a new one in a hope
404 that instruction re-execution will regenerate lost
405 exception */
406 goto queue;
407}
408
298101da
AK		 409void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
410{
ce7ddec4 411 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 412}
413EXPORT_SYMBOL_GPL(kvm_queue_exception);
414
ce7ddec4
JR		 415void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
416{
417 kvm_multiple_exception(vcpu, nr, false, 0, true);
418}
419EXPORT_SYMBOL_GPL(kvm_requeue_exception);
420
db8fcefa 421void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 422{
db8fcefa
AP		 423 if (err)
424 kvm_inject_gp(vcpu, 0);
425 else
426 kvm_x86_ops->skip_emulated_instruction(vcpu);
427}
428EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 429
6389ee94 430void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 431{
432 ++vcpu->stat.pf_guest;
6389ee94
AK		 433 vcpu->arch.cr2 = fault->address;
434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 435}
27d6c865 436EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 437
ef54bcfe 438static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 439{
6389ee94
AK		 440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 442 else
6389ee94 443 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 444
445 return fault->nested_page_fault;
d4f8cf66
JR		 446}
447
3419ffc8
SY		 448void kvm_inject_nmi(struct kvm_vcpu *vcpu)
449{
7460fb4a
AK		 450 atomic_inc(&vcpu->arch.nmi_queued);
451 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 452}
453EXPORT_SYMBOL_GPL(kvm_inject_nmi);
454
298101da
AK		 455void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
456{
ce7ddec4 457 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 458}
459EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
460
ce7ddec4
JR		 461void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
462{
463 kvm_multiple_exception(vcpu, nr, true, error_code, true);
464}
465EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
466
0a79b009
AK		 467/*
468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
469 * a #GP and return false.
470 */
471bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 472{
0a79b009
AK		 473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
474 return true;
475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
476 return false;
298101da 477}
0a79b009 478EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 479
16f8a6f9
NA		 480bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
481{
482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
483 return true;
484
485 kvm_queue_exception(vcpu, UD_VECTOR);
486 return false;
487}
488EXPORT_SYMBOL_GPL(kvm_require_dr);
489
ec92fe44
JR		 490/*
491 * This function will be used to read from the physical memory of the currently
54bf36aa 492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 493 * can read from guest physical or from the guest's guest physical memory.
494 */
495int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
496 gfn_t ngfn, void *data, int offset, int len,
497 u32 access)
498{
54987b7a 499 struct x86_exception exception;
ec92fe44
JR		 500 gfn_t real_gfn;
501 gpa_t ngpa;
502
503 ngpa = gfn_to_gpa(ngfn);
54987b7a 504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 505 if (real_gfn == UNMAPPED_GVA)
506 return -EFAULT;
507
508 real_gfn = gpa_to_gfn(real_gfn);
509
54bf36aa 510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 511}
512EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
513
69b0049a 514static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 515 void *data, int offset, int len, u32 access)
516{
517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
518 data, offset, len, access);
519}
520
a03490ed
CO		 521/*
522 * Load the pae pdptrs. Return true is they are all valid.
523 */
ff03a073 524int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 525{
526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
528 int i;
529 int ret;
ff03a073 530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 531
ff03a073
JR		 532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
533 offset * sizeof(u64), sizeof(pdpte),
534 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 535 if (ret < 0) {
536 ret = 0;
537 goto out;
538 }
539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 540 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 541 (pdpte[i] &
542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 543 ret = 0;
544 goto out;
545 }
546 }
547 ret = 1;
548
ff03a073 549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 550 __set_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail);
552 __set_bit(VCPU_EXREG_PDPTR,
553 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 554out:
a03490ed
CO		 555
556 return ret;
557}
cc4b6871 558EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 559
d835dfec
AK		 560static bool pdptrs_changed(struct kvm_vcpu *vcpu)
561{
ff03a073 562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 563 bool changed = true;
3d06b8bf
JR		 564 int offset;
565 gfn_t gfn;
d835dfec
AK		 566 int r;
567
568 if (is_long_mode(vcpu) || !is_pae(vcpu))
569 return false;
570
6de4f3ad
AK		 571 if (!test_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail))
573 return true;
574
9f8fe504
AK		 575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
578 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 579 if (r < 0)
580 goto out;
ff03a073 581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 582out:
d835dfec
AK		 583
584 return changed;
585}
586
49a9b07e 587int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 588{
aad82703 589 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 591
f9a48e6a
AK		 592 cr0 |= X86_CR0_ET;
593
ab344828 594#ifdef CONFIG_X86_64
0f12244f
GN		 595 if (cr0 & 0xffffffff00000000UL)
596 return 1;
ab344828
GN		 597#endif
598
599 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 600
0f12244f
GN		 601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
602 return 1;
a03490ed 603
0f12244f
GN		 604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
605 return 1;
a03490ed
CO		 606
607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
608#ifdef CONFIG_X86_64
f6801dff 609 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 610 int cs_db, cs_l;
611
0f12244f
GN		 612 if (!is_pae(vcpu))
613 return 1;
a03490ed 614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 615 if (cs_l)
616 return 1;
a03490ed
CO		 617 } else
618#endif
ff03a073 619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 620 kvm_read_cr3(vcpu)))
0f12244f 621 return 1;
a03490ed
CO		 622 }
623
ad756a16
MJ		 624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
625 return 1;
626
a03490ed 627 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 628
d170c419 629 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 630 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 631 kvm_async_pf_hash_reset(vcpu);
632 }
e5f3f027 633
aad82703
SY		 634 if ((cr0 ^ old_cr0) & update_bits)
635 kvm_mmu_reset_context(vcpu);
b18d5431 636
879ae188
LE		 637 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
638 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
641
0f12244f
GN		 642 return 0;
643}
2d3ad1f4 644EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 645
2d3ad1f4 646void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 647{
49a9b07e 648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 649}
2d3ad1f4 650EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 651
42bdf991
MT		 652static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
653{
654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
655 !vcpu->guest_xcr0_loaded) {
656 /* kvm_set_xcr() also depends on this */
657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
658 vcpu->guest_xcr0_loaded = 1;
659 }
660}
661
662static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
663{
664 if (vcpu->guest_xcr0_loaded) {
665 if (vcpu->arch.xcr0 != host_xcr0)
666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
667 vcpu->guest_xcr0_loaded = 0;
668 }
669}
670
69b0049a 671static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 672{
56c103ec
LJ		 673 u64 xcr0 = xcr;
674 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 675 u64 valid_bits;
2acf923e
DC		 676
677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
678 if (index != XCR_XFEATURE_ENABLED_MASK)
679 return 1;
d91cab78 680 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 681 return 1;
d91cab78 682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 683 return 1;
46c34cb0
PB		 684
685 /*
686 * Do not allow the guest to set bits that we do not support
687 * saving. However, xcr0 bit 0 is always set, even if the
688 * emulated CPU does not support XSAVE (see fx_init).
689 */
d91cab78 690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 691 if (xcr0 & ~valid_bits)
2acf923e 692 return 1;
46c34cb0 693
d91cab78
DH		 694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
695 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 696 return 1;
697
d91cab78
DH		 698 if (xcr0 & XFEATURE_MASK_AVX512) {
699 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 700 return 1;
d91cab78 701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 702 return 1;
703 }
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
b9baba86
HH		 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
744 return 1;
745
a03490ed 746 if (is_long_mode(vcpu)) {
0f12244f
GN		 747 if (!(cr4 & X86_CR4_PAE))
748 return 1;
a2edf57f
AK		 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
752 kvm_read_cr3(vcpu)))
0f12244f
GN		 753 return 1;
754
ad756a16
MJ		 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
757 return 1;
758
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
761 return 1;
762 }
763
5e1746d6 764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 765 return 1;
a03490ed 766
ad756a16
MJ		 767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 769 kvm_mmu_reset_context(vcpu);
0f12244f 770
b9baba86 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 772 kvm_update_cpuid(vcpu);
2acf923e 773
0f12244f
GN		 774 return 0;
775}
2d3ad1f4 776EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 777
2390218b 778int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 779{
ac146235 780#ifdef CONFIG_X86_64
9d88fca7 781 cr3 &= ~CR3_PCID_INVD;
ac146235 782#endif
9d88fca7 783
9f8fe504 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 785 kvm_mmu_sync_roots(vcpu);
77c3913b 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 787 return 0;
d835dfec
AK		 788 }
789
a03490ed 790 if (is_long_mode(vcpu)) {
d9f89b88
JK		 791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 return 1;
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 795 return 1;
a03490ed 796
0f12244f 797 vcpu->arch.cr3 = cr3;
aff48baa 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 799 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 803
eea1cff9 804int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 805{
0f12244f
GN		 806 if (cr8 & CR8_RESERVED_BITS)
807 return 1;
35754c98 808 if (lapic_in_kernel(vcpu))
a03490ed
CO		 809 kvm_lapic_set_tpr(vcpu, cr8);
810 else
ad312c7c 811 vcpu->arch.cr8 = cr8;
0f12244f
GN		 812 return 0;
813}
2d3ad1f4 814EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 815
2d3ad1f4 816unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 817{
35754c98 818 if (lapic_in_kernel(vcpu))
a03490ed
CO		 819 return kvm_lapic_get_cr8(vcpu);
820 else
ad312c7c 821 return vcpu->arch.cr8;
a03490ed 822}
2d3ad1f4 823EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 824
ae561ede
NA		 825static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
826{
827 int i;
828
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
833 }
834}
835
73aaf249
JK		 836static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837{
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
840}
841
c8639010
JK		 842static void kvm_update_dr7(struct kvm_vcpu *vcpu)
843{
844 unsigned long dr7;
845
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
848 else
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 854}
855
6f43ed01
NA		 856static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857{
858 u64 fixed = DR6_FIXED_1;
859
860 if (!guest_cpuid_has_rtm(vcpu))
861 fixed |= DR6_RTM;
862 return fixed;
863}
864
338dbc97 865static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 866{
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
872 break;
873 case 4:
020df079
GN		 874 /* fall through */
875 case 6:
338dbc97
GN		 876 if (val & 0xffffffff00000000ULL)
877 return -1; /* #GP */
6f43ed01 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 879 kvm_update_dr6(vcpu);
020df079
GN		 880 break;
881 case 5:
020df079
GN		 882 /* fall through */
883 default: /* 7 */
338dbc97
GN		 884 if (val & 0xffffffff00000000ULL)
885 return -1; /* #GP */
020df079 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 887 kvm_update_dr7(vcpu);
020df079
GN		 888 break;
889 }
890
891 return 0;
892}
338dbc97
GN		 893
894int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895{
16f8a6f9 896 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 897 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 898 return 1;
899 }
900 return 0;
338dbc97 901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_set_dr);
903
16f8a6f9 904int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 905{
906 switch (dr) {
907 case 0 ... 3:
908 *val = vcpu->arch.db[dr];
909 break;
910 case 4:
020df079
GN		 911 /* fall through */
912 case 6:
73aaf249
JK		 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
915 else
916 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 917 break;
918 case 5:
020df079
GN		 919 /* fall through */
920 default: /* 7 */
921 *val = vcpu->arch.dr7;
922 break;
923 }
338dbc97
GN		 924 return 0;
925}
020df079
GN		 926EXPORT_SYMBOL_GPL(kvm_get_dr);
927
022cd0e8
AK		 928bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929{
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
931 u64 data;
932 int err;
933
c6702c9d 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 935 if (err)
936 return err;
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
939 return err;
940}
941EXPORT_SYMBOL_GPL(kvm_rdpmc);
942
043405e1
CO		 943/*
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 *
947 * This list is modified at module load time to reflect the
e3267cbb 948 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
043405e1 951 */
e3267cbb 952
043405e1
CO		 953static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 955 MSR_STAR,
043405e1
CO		 956#ifdef CONFIG_X86_64
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958#endif
b3897a49 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 961};
962
963static unsigned num_msrs_to_save;
964
62ef68bb
PB		 965static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 972 HV_X64_MSR_RESET,
11c4b1ca 973 HV_X64_MSR_VP_INDEX,
9eec50b8 974 HV_X64_MSR_VP_RUNTIME,
5c919412 975 HV_X64_MSR_SCONTROL,
1f4b34f8 976 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
978 MSR_KVM_PV_EOI_EN,
979
ba904635 980 MSR_IA32_TSC_ADJUST,
a3e06bbe 981 MSR_IA32_TSCDEADLINE,
043405e1 982 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 983 MSR_IA32_MCG_STATUS,
984 MSR_IA32_MCG_CTL,
64d60670 985 MSR_IA32_SMBASE,
043405e1
CO		 986};
987
62ef68bb
PB		 988static unsigned num_emulated_msrs;
989
384bb783 990bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 991{
b69e8cae 992 if (efer & efer_reserved_bits)
384bb783 993 return false;
15c4a640 994
1b2fd70c
AG		 995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1000 return false;
1b2fd70c
AG		 1001 }
1002
d8017474
AG		 1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1008 return false;
d8017474
AG		 1009 }
1010
384bb783
JK		 1011 return true;
1012}
1013EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014
1015static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016{
1017 u64 old_efer = vcpu->arch.efer;
1018
1019 if (!kvm_valid_efer(vcpu, efer))
1020 return 1;
1021
1022 if (is_paging(vcpu)
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1024 return 1;
1025
15c4a640 1026 efer &= ~EFER_LMA;
f6801dff 1027 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1028
a3d204e2
SY		 1029 kvm_x86_ops->set_efer(vcpu, efer);
1030
aad82703
SY		 1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1034
b69e8cae 1035 return 0;
15c4a640
CO		 1036}
1037
f2b4b7dd
JR		 1038void kvm_enable_efer_bits(u64 mask)
1039{
1040 efer_reserved_bits &= ~mask;
1041}
1042EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1043
15c4a640
CO		 1044/*
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1048 */
8fe8ab46 1049int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1050{
854e8bb1
NA		 1051 switch (msr->index) {
1052 case MSR_FS_BASE:
1053 case MSR_GS_BASE:
1054 case MSR_KERNEL_GS_BASE:
1055 case MSR_CSTAR:
1056 case MSR_LSTAR:
1057 if (is_noncanonical_address(msr->data))
1058 return 1;
1059 break;
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1062 /*
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1067 *
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1073 */
1074 msr->data = get_canonical(msr->data);
1075 }
8fe8ab46 1076 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1077}
854e8bb1 1078EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1079
313a3dc7
CO		 1080/*
1081 * Adapt set_msr() to msr_io()'s calling convention
1082 */
609e36d3
PB		 1083static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084{
1085 struct msr_data msr;
1086 int r;
1087
1088 msr.index = index;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1091 if (r)
1092 return r;
1093
1094 *data = msr.data;
1095 return 0;
1096}
1097
313a3dc7
CO		 1098static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099{
8fe8ab46
WA		 1100 struct msr_data msr;
1101
1102 msr.data = *data;
1103 msr.index = index;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1106}
1107
16e8d74d
MT		 1108#ifdef CONFIG_X86_64
1109struct pvclock_gtod_data {
1110 seqcount_t seq;
1111
1112 struct { /* extract of a clocksource struct */
1113 int vclock_mode;
1114 cycle_t cycle_last;
1115 cycle_t mask;
1116 u32 mult;
1117 u32 shift;
1118 } clock;
1119
cbcf2dd3
TG		 1120 u64 boot_ns;
1121 u64 nsec_base;
16e8d74d
MT		 1122};
1123
1124static struct pvclock_gtod_data pvclock_gtod_data;
1125
1126static void update_pvclock_gtod(struct timekeeper *tk)
1127{
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1129 u64 boot_ns;
1130
876e7881 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1132
1133 write_seqcount_begin(&vdata->seq);
1134
1135 /* copy pvclock gtod data */
876e7881
PZ		 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1141
cbcf2dd3 1142 vdata->boot_ns = boot_ns;
876e7881 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1144
1145 write_seqcount_end(&vdata->seq);
1146}
1147#endif
1148
bab5bb39
NK		 1149void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1150{
1151 /*
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1155 */
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1157}
16e8d74d 1158
18068523
GOC		 1159static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1160{
9ed3c444
AK		 1161 int version;
1162 int r;
50d0a0f9 1163 struct pvclock_wall_clock wc;
923de3cf 1164 struct timespec boot;
18068523
GOC		 1165
1166 if (!wall_clock)
1167 return;
1168
9ed3c444
AK		 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1170 if (r)
1171 return;
1172
1173 if (version & 1)
1174 ++version; /* first time write, random junk */
1175
1176 ++version;
18068523 1177
1dab1345
NK		 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1179 return;
18068523 1180
50d0a0f9
GH		 1181 /*
1182 * The guest calculates current wall clock time by adding
34c238a1 1183 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1186 */
923de3cf 1187 getboottime(&boot);
50d0a0f9 1188
4b648665
BR		 1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1192 }
50d0a0f9
GH		 1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
18068523
GOC		 1196
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1198
1199 version++;
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1201}
1202
50d0a0f9
GH		 1203static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204{
b51012de
PB		 1205 do_shl32_div32(dividend, divisor);
1206 return dividend;
50d0a0f9
GH		 1207}
1208
3ae13faa 1209static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
3ae13faa
PB		 1217 tps64 = base_hz;
1218 scaled64 = scaled_hz;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
3ae13faa
PB		 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
4941b8cb 1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1302 if (user_tsc_khz == 0) {
ad721883
HZ		 1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1324 use_scaling = 1;
1325 }
4941b8cb 1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1565 * predictable (it's just a function of time and the likely is
d828199e
MT		 1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
78db6a50 1719 unsigned long flags, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
78db6a50
PB		 1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
78db6a50
PB		 1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1789 }
1790
1791 /* With all the info we got, fill in the values */
1d5f066e 1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1794 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1795
09a0c3f1
OH		 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return 0;
1799
5dca0d91
RK		 1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
18068523 1813 */
5dca0d91
RK		 1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
1820
1821 smp_wmb();
78c0337a
MT		 1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
d828199e
MT		 1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834
78c0337a
MT		 1835 vcpu->hv_clock.flags = pvclock_flags;
1836
ce1a5e60
DM		 1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838
0b79459b
AH		 1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1842
1843 smp_wmb();
1844
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 &vcpu->hv_clock,
1848 sizeof(vcpu->hv_clock.version));
8cfdc000 1849 return 0;
c8076604
GH		 1850}
1851
0061d53d
MT		 1852/*
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1857 * the others.
1858 *
1859 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1864 */
1865
7e44e449
AJ		 1866#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867
1868static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1869{
1870 int i;
7e44e449
AJ		 1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1875 struct kvm_vcpu *vcpu;
1876
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1879 kvm_vcpu_kick(vcpu);
1880 }
1881}
1882
7e44e449
AJ		 1883static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884{
1885 struct kvm *kvm = v->kvm;
1886
105b21bb 1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1890}
1891
332967a3
AJ		 1892#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893
1894static void kvmclock_sync_fn(struct work_struct *work)
1895{
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900
630994b3
MT		 1901 if (!kvmclock_periodic_sync)
1902 return;
1903
332967a3
AJ		 1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1907}
1908
890ca9ae 1909static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1910{
890ca9ae
HY		 1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1913
15c4a640 1914 switch (msr) {
15c4a640 1915 case MSR_IA32_MCG_STATUS:
890ca9ae 1916 vcpu->arch.mcg_status = data;
15c4a640 1917 break;
c7ac679c 1918 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1919 if (!(mcg_cap & MCG_CTL_P))
1920 return 1;
1921 if (data != 0 && data != ~(u64)0)
1922 return -1;
1923 vcpu->arch.mcg_ctl = data;
1924 break;
1925 default:
1926 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1928 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1933 */
890ca9ae 1934 if ((offset & 0x3) == 0 &&
114be429 1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1936 return -1;
1937 vcpu->arch.mce_banks[offset] = data;
1938 break;
1939 }
1940 return 1;
1941 }
1942 return 0;
1943}
1944
ffde22ac
ES		 1945static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946{
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1955 u8 *page;
1956 int r;
1957
1958 r = -E2BIG;
1959 if (page_num >= blob_size)
1960 goto out;
1961 r = -ENOMEM;
ff5c2c03
SL		 1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1963 if (IS_ERR(page)) {
1964 r = PTR_ERR(page);
ffde22ac 1965 goto out;
ff5c2c03 1966 }
54bf36aa 1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1968 goto out_free;
1969 r = 0;
1970out_free:
1971 kfree(page);
1972out:
1973 return r;
1974}
1975
344d9588
GN		 1976static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977{
1978 gpa_t gpa = data & ~0x3f;
1979
4a969980 1980 /* Bits 2:5 are reserved, Should be zero */
6adba527 1981 if (data & 0x3c)
344d9588
GN		 1982 return 1;
1983
1984 vcpu->arch.apf.msr_val = data;
1985
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1989 return 0;
1990 }
1991
8f964525
AH		 1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1993 sizeof(u32)))
344d9588
GN		 1994 return 1;
1995
6adba527 1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1997 kvm_async_pf_wakeup_all(vcpu);
1998 return 0;
1999}
2000
12f9a48f
GC		 2001static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002{
0b79459b 2003 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2004}
2005
c9aaa895
GC		 2006static void record_steal_time(struct kvm_vcpu *vcpu)
2007{
2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2009 return;
2010
2011 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2012 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2013 return;
2014
35f3fae1
WL		 2015 if (vcpu->arch.st.steal.version & 1)
2016 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2017
2018 vcpu->arch.st.steal.version += 1;
2019
2020 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2021 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2022
2023 smp_wmb();
2024
c54cdf14
LC		 2025 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2026 vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2028
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2031
2032 smp_wmb();
2033
2034 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2035
2036 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2038}
2039
8fe8ab46 2040int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2041{
5753785f 2042 bool pr = false;
8fe8ab46
WA		 2043 u32 msr = msr_info->index;
2044 u64 data = msr_info->data;
5753785f 2045
15c4a640 2046 switch (msr) {
2e32b719
BP		 2047 case MSR_AMD64_NB_CFG:
2048 case MSR_IA32_UCODE_REV:
2049 case MSR_IA32_UCODE_WRITE:
2050 case MSR_VM_HSAVE_PA:
2051 case MSR_AMD64_PATCH_LOADER:
2052 case MSR_AMD64_BU_CFG2:
2053 break;
2054
15c4a640 2055 case MSR_EFER:
b69e8cae 2056 return set_efer(vcpu, data);
8f1589d9
AP		 2057 case MSR_K7_HWCR:
2058 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2059 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2060 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2061 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2062 if (data != 0) {
a737f256
CD		 2063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2064 data);
8f1589d9
AP		 2065 return 1;
2066 }
15c4a640 2067 break;
f7c6d140
AP		 2068 case MSR_FAM10H_MMIO_CONF_BASE:
2069 if (data != 0) {
a737f256
CD		 2070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2071 "0x%llx\n", data);
f7c6d140
AP		 2072 return 1;
2073 }
15c4a640 2074 break;
b5e2fec0
AG		 2075 case MSR_IA32_DEBUGCTLMSR:
2076 if (!data) {
2077 /* We support the non-activated case already */
2078 break;
2079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2080 /* Values other than LBR and BTF are vendor-specific,
2081 thus reserved and should throw a #GP */
2082 return 1;
2083 }
a737f256
CD		 2084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2085 __func__, data);
b5e2fec0 2086 break;
9ba075a6 2087 case 0x200 ... 0x2ff:
ff53604b 2088 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2089 case MSR_IA32_APICBASE:
58cb628d 2090 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2092 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2093 case MSR_IA32_TSCDEADLINE:
2094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2095 break;
ba904635
WA		 2096 case MSR_IA32_TSC_ADJUST:
2097 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2098 if (!msr_info->host_initiated) {
d913b904 2099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2100 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2101 }
2102 vcpu->arch.ia32_tsc_adjust_msr = data;
2103 }
2104 break;
15c4a640 2105 case MSR_IA32_MISC_ENABLE:
ad312c7c 2106 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2107 break;
64d60670
PB		 2108 case MSR_IA32_SMBASE:
2109 if (!msr_info->host_initiated)
2110 return 1;
2111 vcpu->arch.smbase = data;
2112 break;
11c6bffa 2113 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2114 case MSR_KVM_WALL_CLOCK:
2115 vcpu->kvm->arch.wall_clock = data;
2116 kvm_write_wall_clock(vcpu->kvm, data);
2117 break;
11c6bffa 2118 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2119 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2120 u64 gpa_offset;
54750f2c
MT		 2121 struct kvm_arch *ka = &vcpu->kvm->arch;
2122
12f9a48f 2123 kvmclock_reset(vcpu);
18068523 2124
54750f2c
MT		 2125 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2126 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2127
2128 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2129 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2130 &vcpu->requests);
2131
2132 ka->boot_vcpu_runs_old_kvmclock = tmp;
2133 }
2134
18068523 2135 vcpu->arch.time = data;
0061d53d 2136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2137
2138 /* we verify if the enable bit is set... */
2139 if (!(data & 1))
2140 break;
2141
0b79459b 2142 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2143
0b79459b 2144 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2145 &vcpu->arch.pv_time, data & ~1ULL,
2146 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2147 vcpu->arch.pv_time_enabled = false;
2148 else
2149 vcpu->arch.pv_time_enabled = true;
32cad84f 2150
18068523
GOC		 2151 break;
2152 }
344d9588
GN		 2153 case MSR_KVM_ASYNC_PF_EN:
2154 if (kvm_pv_enable_async_pf(vcpu, data))
2155 return 1;
2156 break;
c9aaa895
GC		 2157 case MSR_KVM_STEAL_TIME:
2158
2159 if (unlikely(!sched_info_on()))
2160 return 1;
2161
2162 if (data & KVM_STEAL_RESERVED_MASK)
2163 return 1;
2164
2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2166 data & KVM_STEAL_VALID_BITS,
2167 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2168 return 1;
2169
2170 vcpu->arch.st.msr_val = data;
2171
2172 if (!(data & KVM_MSR_ENABLED))
2173 break;
2174
c9aaa895
GC		 2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2176
2177 break;
ae7a2a3f
MT		 2178 case MSR_KVM_PV_EOI_EN:
2179 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2180 return 1;
2181 break;
c9aaa895 2182
890ca9ae
HY		 2183 case MSR_IA32_MCG_CTL:
2184 case MSR_IA32_MCG_STATUS:
81760dcc 2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2186 return set_msr_mce(vcpu, msr, data);
71db6023 2187
6912ac32
WH		 2188 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2189 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2190 pr = true; /* fall through */
2191 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2192 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2193 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2194 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2195
2196 if (pr || data != 0)
a737f256
CD		 2197 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2198 "0x%x data 0x%llx\n", msr, data);
5753785f 2199 break;
84e0cefa
JS		 2200 case MSR_K7_CLK_CTL:
2201 /*
2202 * Ignore all writes to this no longer documented MSR.
2203 * Writes are only relevant for old K7 processors,
2204 * all pre-dating SVM, but a recommended workaround from
4a969980 2205 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2206 * affected processor models on the command line, hence
2207 * the need to ignore the workaround.
2208 */
2209 break;
55cd8e5a 2210 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2211 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2212 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2213 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2214 return kvm_hv_set_msr_common(vcpu, msr, data,
2215 msr_info->host_initiated);
91c9c3ed 2216 case MSR_IA32_BBL_CR_CTL3:
2217 /* Drop writes to this legacy MSR -- see rdmsr
2218 * counterpart for further detail.
2219 */
a737f256 2220 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2221 break;
2b036c6b
BO		 2222 case MSR_AMD64_OSVW_ID_LENGTH:
2223 if (!guest_cpuid_has_osvw(vcpu))
2224 return 1;
2225 vcpu->arch.osvw.length = data;
2226 break;
2227 case MSR_AMD64_OSVW_STATUS:
2228 if (!guest_cpuid_has_osvw(vcpu))
2229 return 1;
2230 vcpu->arch.osvw.status = data;
2231 break;
15c4a640 2232 default:
ffde22ac
ES		 2233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2234 return xen_hvm_config(vcpu, data);
c6702c9d 2235 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2236 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2237 if (!ignore_msrs) {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 return 1;
2241 } else {
a737f256
CD		 2242 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2243 msr, data);
ed85c068
AP		 2244 break;
2245 }
15c4a640
CO		 2246 }
2247 return 0;
2248}
2249EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2250
2251
2252/*
2253 * Reads an msr value (of 'msr_index') into 'pdata'.
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
609e36d3 2257int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2258{
609e36d3 2259 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2260}
ff651cb6 2261EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2262
890ca9ae 2263static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2264{
2265 u64 data;
890ca9ae
HY		 2266 u64 mcg_cap = vcpu->arch.mcg_cap;
2267 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2268
2269 switch (msr) {
15c4a640
CO		 2270 case MSR_IA32_P5_MC_ADDR:
2271 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2272 data = 0;
2273 break;
15c4a640 2274 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2275 data = vcpu->arch.mcg_cap;
2276 break;
c7ac679c 2277 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2278 if (!(mcg_cap & MCG_CTL_P))
2279 return 1;
2280 data = vcpu->arch.mcg_ctl;
2281 break;
2282 case MSR_IA32_MCG_STATUS:
2283 data = vcpu->arch.mcg_status;
2284 break;
2285 default:
2286 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2287 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2288 u32 offset = msr - MSR_IA32_MC0_CTL;
2289 data = vcpu->arch.mce_banks[offset];
2290 break;
2291 }
2292 return 1;
2293 }
2294 *pdata = data;
2295 return 0;
2296}
2297
609e36d3 2298int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2299{
609e36d3 2300 switch (msr_info->index) {
890ca9ae 2301 case MSR_IA32_PLATFORM_ID:
15c4a640 2302 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2303 case MSR_IA32_DEBUGCTLMSR:
2304 case MSR_IA32_LASTBRANCHFROMIP:
2305 case MSR_IA32_LASTBRANCHTOIP:
2306 case MSR_IA32_LASTINTFROMIP:
2307 case MSR_IA32_LASTINTTOIP:
60af2ecd 2308 case MSR_K8_SYSCFG:
3afb1121
PB		 2309 case MSR_K8_TSEG_ADDR:
2310 case MSR_K8_TSEG_MASK:
60af2ecd 2311 case MSR_K7_HWCR:
61a6bd67 2312 case MSR_VM_HSAVE_PA:
1fdbd48c 2313 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2314 case MSR_AMD64_NB_CFG:
f7c6d140 2315 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2316 case MSR_AMD64_BU_CFG2:
609e36d3 2317 msr_info->data = 0;
15c4a640 2318 break;
6912ac32
WH		 2319 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2320 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2321 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2322 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2323 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2324 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2325 msr_info->data = 0;
5753785f 2326 break;
742bc670 2327 case MSR_IA32_UCODE_REV:
609e36d3 2328 msr_info->data = 0x100000000ULL;
742bc670 2329 break;
9ba075a6 2330 case MSR_MTRRcap:
9ba075a6 2331 case 0x200 ... 0x2ff:
ff53604b 2332 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2333 case 0xcd: /* fsb frequency */
609e36d3 2334 msr_info->data = 3;
15c4a640 2335 break;
7b914098
JS		 2336 /*
2337 * MSR_EBC_FREQUENCY_ID
2338 * Conservative value valid for even the basic CPU models.
2339 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2340 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2341 * and 266MHz for model 3, or 4. Set Core Clock
2342 * Frequency to System Bus Frequency Ratio to 1 (bits
2343 * 31:24) even though these are only valid for CPU
2344 * models > 2, however guests may end up dividing or
2345 * multiplying by zero otherwise.
2346 */
2347 case MSR_EBC_FREQUENCY_ID:
609e36d3 2348 msr_info->data = 1 << 24;
7b914098 2349 break;
15c4a640 2350 case MSR_IA32_APICBASE:
609e36d3 2351 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2352 break;
0105d1a5 2353 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2354 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2355 break;
a3e06bbe 2356 case MSR_IA32_TSCDEADLINE:
609e36d3 2357 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2358 break;
ba904635 2359 case MSR_IA32_TSC_ADJUST:
609e36d3 2360 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2361 break;
15c4a640 2362 case MSR_IA32_MISC_ENABLE:
609e36d3 2363 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2364 break;
64d60670
PB		 2365 case MSR_IA32_SMBASE:
2366 if (!msr_info->host_initiated)
2367 return 1;
2368 msr_info->data = vcpu->arch.smbase;
15c4a640 2369 break;
847f0ad8
AG		 2370 case MSR_IA32_PERF_STATUS:
2371 /* TSC increment by tick */
609e36d3 2372 msr_info->data = 1000ULL;
847f0ad8 2373 /* CPU multiplier */
b0996ae4 2374 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2375 break;
15c4a640 2376 case MSR_EFER:
609e36d3 2377 msr_info->data = vcpu->arch.efer;
15c4a640 2378 break;
18068523 2379 case MSR_KVM_WALL_CLOCK:
11c6bffa 2380 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2381 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2382 break;
2383 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2384 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2385 msr_info->data = vcpu->arch.time;
18068523 2386 break;
344d9588 2387 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2388 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2389 break;
c9aaa895 2390 case MSR_KVM_STEAL_TIME:
609e36d3 2391 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2392 break;
1d92128f 2393 case MSR_KVM_PV_EOI_EN:
609e36d3 2394 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2395 break;
890ca9ae
HY		 2396 case MSR_IA32_P5_MC_ADDR:
2397 case MSR_IA32_P5_MC_TYPE:
2398 case MSR_IA32_MCG_CAP:
2399 case MSR_IA32_MCG_CTL:
2400 case MSR_IA32_MCG_STATUS:
81760dcc 2401 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2402 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2403 case MSR_K7_CLK_CTL:
2404 /*
2405 * Provide expected ramp-up count for K7. All other
2406 * are set to zero, indicating minimum divisors for
2407 * every field.
2408 *
2409 * This prevents guest kernels on AMD host with CPU
2410 * type 6, model 8 and higher from exploding due to
2411 * the rdmsr failing.
2412 */
609e36d3 2413 msr_info->data = 0x20000000;
84e0cefa 2414 break;
55cd8e5a 2415 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2416 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2417 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2418 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2419 return kvm_hv_get_msr_common(vcpu,
2420 msr_info->index, &msr_info->data);
55cd8e5a 2421 break;
91c9c3ed 2422 case MSR_IA32_BBL_CR_CTL3:
2423 /* This legacy MSR exists but isn't fully documented in current
2424 * silicon. It is however accessed by winxp in very narrow
2425 * scenarios where it sets bit #19, itself documented as
2426 * a "reserved" bit. Best effort attempt to source coherent
2427 * read data here should the balance of the register be
2428 * interpreted by the guest:
2429 *
2430 * L2 cache control register 3: 64GB range, 256KB size,
2431 * enabled, latency 0x1, configured
2432 */
609e36d3 2433 msr_info->data = 0xbe702111;
91c9c3ed 2434 break;
2b036c6b
BO		 2435 case MSR_AMD64_OSVW_ID_LENGTH:
2436 if (!guest_cpuid_has_osvw(vcpu))
2437 return 1;
609e36d3 2438 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2439 break;
2440 case MSR_AMD64_OSVW_STATUS:
2441 if (!guest_cpuid_has_osvw(vcpu))
2442 return 1;
609e36d3 2443 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2444 break;
15c4a640 2445 default:
c6702c9d 2446 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2447 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2448 if (!ignore_msrs) {
609e36d3 2449 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2450 return 1;
2451 } else {
609e36d3
PB		 2452 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2453 msr_info->data = 0;
ed85c068
AP		 2454 }
2455 break;
15c4a640 2456 }
15c4a640
CO		 2457 return 0;
2458}
2459EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2460
313a3dc7
CO		 2461/*
2462 * Read or write a bunch of msrs. All parameters are kernel addresses.
2463 *
2464 * @return number of msrs set successfully.
2465 */
2466static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2467 struct kvm_msr_entry *entries,
2468 int (*do_msr)(struct kvm_vcpu *vcpu,
2469 unsigned index, u64 *data))
2470{
f656ce01 2471 int i, idx;
313a3dc7 2472
f656ce01 2473 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2474 for (i = 0; i < msrs->nmsrs; ++i)
2475 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2476 break;
f656ce01 2477 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2478
313a3dc7
CO		 2479 return i;
2480}
2481
2482/*
2483 * Read or write a bunch of msrs. Parameters are user addresses.
2484 *
2485 * @return number of msrs set successfully.
2486 */
2487static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2488 int (*do_msr)(struct kvm_vcpu *vcpu,
2489 unsigned index, u64 *data),
2490 int writeback)
2491{
2492 struct kvm_msrs msrs;
2493 struct kvm_msr_entry *entries;
2494 int r, n;
2495 unsigned size;
2496
2497 r = -EFAULT;
2498 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2499 goto out;
2500
2501 r = -E2BIG;
2502 if (msrs.nmsrs >= MAX_IO_MSRS)
2503 goto out;
2504
313a3dc7 2505 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2506 entries = memdup_user(user_msrs->entries, size);
2507 if (IS_ERR(entries)) {
2508 r = PTR_ERR(entries);
313a3dc7 2509 goto out;
ff5c2c03 2510 }
313a3dc7
CO		 2511
2512 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2513 if (r < 0)
2514 goto out_free;
2515
2516 r = -EFAULT;
2517 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2518 goto out_free;
2519
2520 r = n;
2521
2522out_free:
7a73c028 2523 kfree(entries);
313a3dc7
CO		 2524out:
2525 return r;
2526}
2527
784aa3d7 2528int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2529{
2530 int r;
2531
2532 switch (ext) {
2533 case KVM_CAP_IRQCHIP:
2534 case KVM_CAP_HLT:
2535 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2536 case KVM_CAP_SET_TSS_ADDR:
07716717 2537 case KVM_CAP_EXT_CPUID:
9c15bb1d 2538 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2539 case KVM_CAP_CLOCKSOURCE:
7837699f 2540 case KVM_CAP_PIT:
a28e4f5a 2541 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2542 case KVM_CAP_MP_STATE:
ed848624 2543 case KVM_CAP_SYNC_MMU:
a355c85c 2544 case KVM_CAP_USER_NMI:
52d939a0 2545 case KVM_CAP_REINJECT_CONTROL:
4925663a 2546 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2547 case KVM_CAP_IOEVENTFD:
f848a5a8 2548 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2549 case KVM_CAP_PIT2:
e9f42757 2550 case KVM_CAP_PIT_STATE2:
b927a3ce 2551 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2552 case KVM_CAP_XEN_HVM:
afbcf7ab 2553 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2554 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2555 case KVM_CAP_HYPERV:
10388a07 2556 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2557 case KVM_CAP_HYPERV_SPIN:
5c919412 2558 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2559 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2560 case KVM_CAP_DEBUGREGS:
d2be1651 2561 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2562 case KVM_CAP_XSAVE:
344d9588 2563 case KVM_CAP_ASYNC_PF:
92a1f12d 2564 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2565 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2566 case KVM_CAP_READONLY_MEM:
5f66b620 2567 case KVM_CAP_HYPERV_TIME:
100943c5 2568 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2569 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2570 case KVM_CAP_ENABLE_CAP_VM:
2571 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2572 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2573 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2574#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2575 case KVM_CAP_ASSIGN_DEV_IRQ:
2576 case KVM_CAP_PCI_2_3:
2577#endif
018d00d2
ZX		 2578 r = 1;
2579 break;
6d396b55
PB		 2580 case KVM_CAP_X86_SMM:
2581 /* SMBASE is usually relocated above 1M on modern chipsets,
2582 * and SMM handlers might indeed rely on 4G segment limits,
2583 * so do not report SMM to be available if real mode is
2584 * emulated via vm86 mode. Still, do not go to great lengths
2585 * to avoid userspace's usage of the feature, because it is a
2586 * fringe case that is not enabled except via specific settings
2587 * of the module parameters.
2588 */
2589 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2590 break;
542472b5
LV		 2591 case KVM_CAP_COALESCED_MMIO:
2592 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2593 break;
774ead3a
AK		 2594 case KVM_CAP_VAPIC:
2595 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2596 break;
f725230a 2597 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2598 r = KVM_SOFT_MAX_VCPUS;
2599 break;
2600 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2601 r = KVM_MAX_VCPUS;
2602 break;
a988b910 2603 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2604 r = KVM_USER_MEM_SLOTS;
a988b910 2605 break;
a68a6a72
MT		 2606 case KVM_CAP_PV_MMU: /* obsolete */
2607 r = 0;
2f333bcb 2608 break;
4cee4b72 2609#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2610 case KVM_CAP_IOMMU:
a1b60c1c 2611 r = iommu_present(&pci_bus_type);
62c476c7 2612 break;
4cee4b72 2613#endif
890ca9ae
HY		 2614 case KVM_CAP_MCE:
2615 r = KVM_MAX_MCE_BANKS;
2616 break;
2d5b5a66 2617 case KVM_CAP_XCRS:
d366bf7e 2618 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2619 break;
92a1f12d
JR		 2620 case KVM_CAP_TSC_CONTROL:
2621 r = kvm_has_tsc_control;
2622 break;
018d00d2
ZX		 2623 default:
2624 r = 0;
2625 break;
2626 }
2627 return r;
2628
2629}
2630
043405e1
CO		 2631long kvm_arch_dev_ioctl(struct file *filp,
2632 unsigned int ioctl, unsigned long arg)
2633{
2634 void __user *argp = (void __user *)arg;
2635 long r;
2636
2637 switch (ioctl) {
2638 case KVM_GET_MSR_INDEX_LIST: {
2639 struct kvm_msr_list __user *user_msr_list = argp;
2640 struct kvm_msr_list msr_list;
2641 unsigned n;
2642
2643 r = -EFAULT;
2644 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2645 goto out;
2646 n = msr_list.nmsrs;
62ef68bb 2647 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2648 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2649 goto out;
2650 r = -E2BIG;
e125e7b6 2651 if (n < msr_list.nmsrs)
043405e1
CO		 2652 goto out;
2653 r = -EFAULT;
2654 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2655 num_msrs_to_save * sizeof(u32)))
2656 goto out;
e125e7b6 2657 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2658 &emulated_msrs,
62ef68bb 2659 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2660 goto out;
2661 r = 0;
2662 break;
2663 }
9c15bb1d
BP		 2664 case KVM_GET_SUPPORTED_CPUID:
2665 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2666 struct kvm_cpuid2 __user *cpuid_arg = argp;
2667 struct kvm_cpuid2 cpuid;
2668
2669 r = -EFAULT;
2670 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2671 goto out;
9c15bb1d
BP		 2672
2673 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2674 ioctl);
674eea0f
AK		 2675 if (r)
2676 goto out;
2677
2678 r = -EFAULT;
2679 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2680 goto out;
2681 r = 0;
2682 break;
2683 }
890ca9ae
HY		 2684 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2685 u64 mce_cap;
2686
2687 mce_cap = KVM_MCE_CAP_SUPPORTED;
2688 r = -EFAULT;
2689 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
043405e1
CO		 2694 default:
2695 r = -EINVAL;
2696 }
2697out:
2698 return r;
2699}
2700
f5f48ee1
SY		 2701static void wbinvd_ipi(void *garbage)
2702{
2703 wbinvd();
2704}
2705
2706static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2707{
e0f0bbc5 2708 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2709}
2710
2860c4b1
PB		 2711static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2712{
2713 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2714}
2715
313a3dc7
CO		 2716void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2717{
f5f48ee1
SY		 2718 /* Address WBINVD may be executed by guest */
2719 if (need_emulate_wbinvd(vcpu)) {
2720 if (kvm_x86_ops->has_wbinvd_exit())
2721 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2722 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2723 smp_call_function_single(vcpu->cpu,
2724 wbinvd_ipi, NULL, 1);
2725 }
2726
313a3dc7 2727 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2728
0dd6a6ed
ZA		 2729 /* Apply any externally detected TSC adjustments (due to suspend) */
2730 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2731 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2732 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2733 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2734 }
8f6055cb 2735
48434c20 2736 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2737 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2738 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2739 if (tsc_delta < 0)
2740 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2741 if (check_tsc_unstable()) {
07c1419a 2742 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2743 vcpu->arch.last_guest_tsc);
2744 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2745 vcpu->arch.tsc_catchup = 1;
c285545f 2746 }
d98d07ca
MT		 2747 /*
2748 * On a host with synchronized TSC, there is no need to update
2749 * kvmclock on vcpu->cpu migration
2750 */
2751 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2752 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2753 if (vcpu->cpu != cpu)
2754 kvm_migrate_timers(vcpu);
e48672fa 2755 vcpu->cpu = cpu;
6b7d7e76 2756 }
c9aaa895 2757
c9aaa895 2758 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2759}
2760
2761void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2762{
02daab21 2763 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2764 kvm_put_guest_fpu(vcpu);
4ea1636b 2765 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2766}
2767
313a3dc7
CO		 2768static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2769 struct kvm_lapic_state *s)
2770{
d62caabb
AS		 2771 if (vcpu->arch.apicv_active)
2772 kvm_x86_ops->sync_pir_to_irr(vcpu);
2773
ad312c7c 2774 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2775
2776 return 0;
2777}
2778
2779static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2780 struct kvm_lapic_state *s)
2781{
64eb0620 2782 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2783 update_cr8_intercept(vcpu);
313a3dc7
CO		 2784
2785 return 0;
2786}
2787
127a457a
MG		 2788static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2789{
2790 return (!lapic_in_kernel(vcpu) ||
2791 kvm_apic_accept_pic_intr(vcpu));
2792}
2793
782d422b
MG		 2794/*
2795 * if userspace requested an interrupt window, check that the
2796 * interrupt window is open.
2797 *
2798 * No need to exit to userspace if we already have an interrupt queued.
2799 */
2800static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2801{
2802 return kvm_arch_interrupt_allowed(vcpu) &&
2803 !kvm_cpu_has_interrupt(vcpu) &&
2804 !kvm_event_needs_reinjection(vcpu) &&
2805 kvm_cpu_accept_dm_intr(vcpu);
2806}
2807
f77bc6a4
ZX		 2808static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2809 struct kvm_interrupt *irq)
2810{
02cdb50f 2811 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2812 return -EINVAL;
1c1a9ce9
SR		 2813
2814 if (!irqchip_in_kernel(vcpu->kvm)) {
2815 kvm_queue_interrupt(vcpu, irq->irq, false);
2816 kvm_make_request(KVM_REQ_EVENT, vcpu);
2817 return 0;
2818 }
2819
2820 /*
2821 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2822 * fail for in-kernel 8259.
2823 */
2824 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2825 return -ENXIO;
f77bc6a4 2826
1c1a9ce9
SR		 2827 if (vcpu->arch.pending_external_vector != -1)
2828 return -EEXIST;
f77bc6a4 2829
1c1a9ce9 2830 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2831 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2832 return 0;
2833}
2834
c4abb7c9
JK		 2835static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2836{
c4abb7c9 2837 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2838
2839 return 0;
2840}
2841
f077825a
PB		 2842static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2843{
64d60670
PB		 2844 kvm_make_request(KVM_REQ_SMI, vcpu);
2845
f077825a
PB		 2846 return 0;
2847}
2848
b209749f
AK		 2849static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2850 struct kvm_tpr_access_ctl *tac)
2851{
2852 if (tac->flags)
2853 return -EINVAL;
2854 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2855 return 0;
2856}
2857
890ca9ae
HY		 2858static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2859 u64 mcg_cap)
2860{
2861 int r;
2862 unsigned bank_num = mcg_cap & 0xff, bank;
2863
2864 r = -EINVAL;
a9e38c3e 2865 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2866 goto out;
2867 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2868 goto out;
2869 r = 0;
2870 vcpu->arch.mcg_cap = mcg_cap;
2871 /* Init IA32_MCG_CTL to all 1s */
2872 if (mcg_cap & MCG_CTL_P)
2873 vcpu->arch.mcg_ctl = ~(u64)0;
2874 /* Init IA32_MCi_CTL to all 1s */
2875 for (bank = 0; bank < bank_num; bank++)
2876 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2877out:
2878 return r;
2879}
2880
2881static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2882 struct kvm_x86_mce *mce)
2883{
2884 u64 mcg_cap = vcpu->arch.mcg_cap;
2885 unsigned bank_num = mcg_cap & 0xff;
2886 u64 *banks = vcpu->arch.mce_banks;
2887
2888 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2889 return -EINVAL;
2890 /*
2891 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2892 * reporting is disabled
2893 */
2894 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2895 vcpu->arch.mcg_ctl != ~(u64)0)
2896 return 0;
2897 banks += 4 * mce->bank;
2898 /*
2899 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2900 * reporting is disabled for the bank
2901 */
2902 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2903 return 0;
2904 if (mce->status & MCI_STATUS_UC) {
2905 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2906 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2908 return 0;
2909 }
2910 if (banks[1] & MCI_STATUS_VAL)
2911 mce->status |= MCI_STATUS_OVER;
2912 banks[2] = mce->addr;
2913 banks[3] = mce->misc;
2914 vcpu->arch.mcg_status = mce->mcg_status;
2915 banks[1] = mce->status;
2916 kvm_queue_exception(vcpu, MC_VECTOR);
2917 } else if (!(banks[1] & MCI_STATUS_VAL)
2918 || !(banks[1] & MCI_STATUS_UC)) {
2919 if (banks[1] & MCI_STATUS_VAL)
2920 mce->status |= MCI_STATUS_OVER;
2921 banks[2] = mce->addr;
2922 banks[3] = mce->misc;
2923 banks[1] = mce->status;
2924 } else
2925 banks[1] |= MCI_STATUS_OVER;
2926 return 0;
2927}
2928
3cfc3092
JK		 2929static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2930 struct kvm_vcpu_events *events)
2931{
7460fb4a 2932 process_nmi(vcpu);
03b82a30
JK		 2933 events->exception.injected =
2934 vcpu->arch.exception.pending &&
2935 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2936 events->exception.nr = vcpu->arch.exception.nr;
2937 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2938 events->exception.pad = 0;
3cfc3092
JK		 2939 events->exception.error_code = vcpu->arch.exception.error_code;
2940
03b82a30
JK		 2941 events->interrupt.injected =
2942 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2943 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2944 events->interrupt.soft = 0;
37ccdcbe 2945 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2946
2947 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2948 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2949 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2950 events->nmi.pad = 0;
3cfc3092 2951
66450a21 2952 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2953
f077825a
PB		 2954 events->smi.smm = is_smm(vcpu);
2955 events->smi.pending = vcpu->arch.smi_pending;
2956 events->smi.smm_inside_nmi =
2957 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2958 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2959
dab4b911 2960 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2961 | KVM_VCPUEVENT_VALID_SHADOW
2962 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2963 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2964}
2965
2966static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2967 struct kvm_vcpu_events *events)
2968{
dab4b911 2969 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2970 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2971 | KVM_VCPUEVENT_VALID_SHADOW
2972 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2973 return -EINVAL;
2974
7460fb4a 2975 process_nmi(vcpu);
3cfc3092
JK		 2976 vcpu->arch.exception.pending = events->exception.injected;
2977 vcpu->arch.exception.nr = events->exception.nr;
2978 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2979 vcpu->arch.exception.error_code = events->exception.error_code;
2980
2981 vcpu->arch.interrupt.pending = events->interrupt.injected;
2982 vcpu->arch.interrupt.nr = events->interrupt.nr;
2983 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2984 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2985 kvm_x86_ops->set_interrupt_shadow(vcpu,
2986 events->interrupt.shadow);
3cfc3092
JK		 2987
2988 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2989 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2990 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2991 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2992
66450a21 2993 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2994 lapic_in_kernel(vcpu))
66450a21 2995 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2996
f077825a
PB		 2997 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2998 if (events->smi.smm)
2999 vcpu->arch.hflags |= HF_SMM_MASK;
3000 else
3001 vcpu->arch.hflags &= ~HF_SMM_MASK;
3002 vcpu->arch.smi_pending = events->smi.pending;
3003 if (events->smi.smm_inside_nmi)
3004 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3005 else
3006 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3007 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3008 if (events->smi.latched_init)
3009 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3010 else
3011 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3012 }
3013 }
3014
3842d135
AK		 3015 kvm_make_request(KVM_REQ_EVENT, vcpu);
3016
3cfc3092
JK		 3017 return 0;
3018}
3019
a1efbe77
JK		 3020static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3021 struct kvm_debugregs *dbgregs)
3022{
73aaf249
JK		 3023 unsigned long val;
3024
a1efbe77 3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3026 kvm_get_dr(vcpu, 6, &val);
73aaf249 3027 dbgregs->dr6 = val;
a1efbe77
JK		 3028 dbgregs->dr7 = vcpu->arch.dr7;
3029 dbgregs->flags = 0;
97e69aa6 3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3031}
3032
3033static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3034 struct kvm_debugregs *dbgregs)
3035{
3036 if (dbgregs->flags)
3037 return -EINVAL;
3038
a1efbe77 3039 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3040 kvm_update_dr0123(vcpu);
a1efbe77 3041 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3042 kvm_update_dr6(vcpu);
a1efbe77 3043 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3044 kvm_update_dr7(vcpu);
a1efbe77 3045
a1efbe77
JK		 3046 return 0;
3047}
3048
df1daba7
PB		 3049#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3050
3051static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3052{
c47ada30 3053 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3054 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3055 u64 valid;
3056
3057 /*
3058 * Copy legacy XSAVE area, to avoid complications with CPUID
3059 * leaves 0 and 1 in the loop below.
3060 */
3061 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3062
3063 /* Set XSTATE_BV */
3064 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3065
3066 /*
3067 * Copy each region from the possibly compacted offset to the
3068 * non-compacted offset.
3069 */
d91cab78 3070 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3071 while (valid) {
3072 u64 feature = valid & -valid;
3073 int index = fls64(feature) - 1;
3074 void *src = get_xsave_addr(xsave, feature);
3075
3076 if (src) {
3077 u32 size, offset, ecx, edx;
3078 cpuid_count(XSTATE_CPUID, index,
3079 &size, &offset, &ecx, &edx);
3080 memcpy(dest + offset, src, size);
3081 }
3082
3083 valid -= feature;
3084 }
3085}
3086
3087static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3088{
c47ada30 3089 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3090 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3091 u64 valid;
3092
3093 /*
3094 * Copy legacy XSAVE area, to avoid complications with CPUID
3095 * leaves 0 and 1 in the loop below.
3096 */
3097 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3098
3099 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3100 xsave->header.xfeatures = xstate_bv;
782511b0 3101 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3102 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3103
3104 /*
3105 * Copy each region from the non-compacted offset to the
3106 * possibly compacted offset.
3107 */
d91cab78 3108 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3109 while (valid) {
3110 u64 feature = valid & -valid;
3111 int index = fls64(feature) - 1;
3112 void *dest = get_xsave_addr(xsave, feature);
3113
3114 if (dest) {
3115 u32 size, offset, ecx, edx;
3116 cpuid_count(XSTATE_CPUID, index,
3117 &size, &offset, &ecx, &edx);
3118 memcpy(dest, src + offset, size);
ee4100da 3119 }
df1daba7
PB		 3120
3121 valid -= feature;
3122 }
3123}
3124
2d5b5a66
SY		 3125static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3126 struct kvm_xsave *guest_xsave)
3127{
d366bf7e 3128 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3129 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3130 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3131 } else {
2d5b5a66 3132 memcpy(guest_xsave->region,
7366ed77 3133 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3134 sizeof(struct fxregs_state));
2d5b5a66 3135 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3136 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3137 }
3138}
3139
3140static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3141 struct kvm_xsave *guest_xsave)
3142{
3143 u64 xstate_bv =
3144 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3145
d366bf7e 3146 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3147 /*
3148 * Here we allow setting states that are not present in
3149 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3150 * with old userspace.
3151 */
4ff41732 3152 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3153 return -EINVAL;
df1daba7 3154 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3155 } else {
d91cab78 3156 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3157 return -EINVAL;
7366ed77 3158 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3159 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3160 }
3161 return 0;
3162}
3163
3164static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3165 struct kvm_xcrs *guest_xcrs)
3166{
d366bf7e 3167 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3168 guest_xcrs->nr_xcrs = 0;
3169 return;
3170 }
3171
3172 guest_xcrs->nr_xcrs = 1;
3173 guest_xcrs->flags = 0;
3174 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3175 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3176}
3177
3178static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3179 struct kvm_xcrs *guest_xcrs)
3180{
3181 int i, r = 0;
3182
d366bf7e 3183 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3184 return -EINVAL;
3185
3186 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3187 return -EINVAL;
3188
3189 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3190 /* Only support XCR0 currently */
c67a04cb 3191 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3192 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3193 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3194 break;
3195 }
3196 if (r)
3197 r = -EINVAL;
3198 return r;
3199}
3200
1c0b28c2
EM		 3201/*
3202 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3203 * stopped by the hypervisor. This function will be called from the host only.
3204 * EINVAL is returned when the host attempts to set the flag for a guest that
3205 * does not support pv clocks.
3206 */
3207static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3208{
0b79459b 3209 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3210 return -EINVAL;
51d59c6b 3211 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3212 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3213 return 0;
3214}
3215
5c919412
AS		 3216static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3217 struct kvm_enable_cap *cap)
3218{
3219 if (cap->flags)
3220 return -EINVAL;
3221
3222 switch (cap->cap) {
3223 case KVM_CAP_HYPERV_SYNIC:
3224 return kvm_hv_activate_synic(vcpu);
3225 default:
3226 return -EINVAL;
3227 }
3228}
3229
313a3dc7
CO		 3230long kvm_arch_vcpu_ioctl(struct file *filp,
3231 unsigned int ioctl, unsigned long arg)
3232{
3233 struct kvm_vcpu *vcpu = filp->private_data;
3234 void __user *argp = (void __user *)arg;
3235 int r;
d1ac91d8
AK		 3236 union {
3237 struct kvm_lapic_state *lapic;
3238 struct kvm_xsave *xsave;
3239 struct kvm_xcrs *xcrs;
3240 void *buffer;
3241 } u;
3242
3243 u.buffer = NULL;
313a3dc7
CO		 3244 switch (ioctl) {
3245 case KVM_GET_LAPIC: {
2204ae3c 3246 r = -EINVAL;
bce87cce 3247 if (!lapic_in_kernel(vcpu))
2204ae3c 3248 goto out;
d1ac91d8 3249 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3250
b772ff36 3251 r = -ENOMEM;
d1ac91d8 3252 if (!u.lapic)
b772ff36 3253 goto out;
d1ac91d8 3254 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3255 if (r)
3256 goto out;
3257 r = -EFAULT;
d1ac91d8 3258 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3259 goto out;
3260 r = 0;
3261 break;
3262 }
3263 case KVM_SET_LAPIC: {
2204ae3c 3264 r = -EINVAL;
bce87cce 3265 if (!lapic_in_kernel(vcpu))
2204ae3c 3266 goto out;
ff5c2c03 3267 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3268 if (IS_ERR(u.lapic))
3269 return PTR_ERR(u.lapic);
ff5c2c03 3270
d1ac91d8 3271 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3272 break;
3273 }
f77bc6a4
ZX		 3274 case KVM_INTERRUPT: {
3275 struct kvm_interrupt irq;
3276
3277 r = -EFAULT;
3278 if (copy_from_user(&irq, argp, sizeof irq))
3279 goto out;
3280 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3281 break;
3282 }
c4abb7c9
JK		 3283 case KVM_NMI: {
3284 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3285 break;
3286 }
f077825a
PB		 3287 case KVM_SMI: {
3288 r = kvm_vcpu_ioctl_smi(vcpu);
3289 break;
3290 }
313a3dc7
CO		 3291 case KVM_SET_CPUID: {
3292 struct kvm_cpuid __user *cpuid_arg = argp;
3293 struct kvm_cpuid cpuid;
3294
3295 r = -EFAULT;
3296 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3297 goto out;
3298 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3299 break;
3300 }
07716717
DK		 3301 case KVM_SET_CPUID2: {
3302 struct kvm_cpuid2 __user *cpuid_arg = argp;
3303 struct kvm_cpuid2 cpuid;
3304
3305 r = -EFAULT;
3306 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3307 goto out;
3308 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3309 cpuid_arg->entries);
07716717
DK		 3310 break;
3311 }
3312 case KVM_GET_CPUID2: {
3313 struct kvm_cpuid2 __user *cpuid_arg = argp;
3314 struct kvm_cpuid2 cpuid;
3315
3316 r = -EFAULT;
3317 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3318 goto out;
3319 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3320 cpuid_arg->entries);
07716717
DK		 3321 if (r)
3322 goto out;
3323 r = -EFAULT;
3324 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3325 goto out;
3326 r = 0;
3327 break;
3328 }
313a3dc7 3329 case KVM_GET_MSRS:
609e36d3 3330 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3331 break;
3332 case KVM_SET_MSRS:
3333 r = msr_io(vcpu, argp, do_set_msr, 0);
3334 break;
b209749f
AK		 3335 case KVM_TPR_ACCESS_REPORTING: {
3336 struct kvm_tpr_access_ctl tac;
3337
3338 r = -EFAULT;
3339 if (copy_from_user(&tac, argp, sizeof tac))
3340 goto out;
3341 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3342 if (r)
3343 goto out;
3344 r = -EFAULT;
3345 if (copy_to_user(argp, &tac, sizeof tac))
3346 goto out;
3347 r = 0;
3348 break;
3349 };
b93463aa
AK		 3350 case KVM_SET_VAPIC_ADDR: {
3351 struct kvm_vapic_addr va;
3352
3353 r = -EINVAL;
35754c98 3354 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3355 goto out;
3356 r = -EFAULT;
3357 if (copy_from_user(&va, argp, sizeof va))
3358 goto out;
fda4e2e8 3359 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3360 break;
3361 }
890ca9ae
HY		 3362 case KVM_X86_SETUP_MCE: {
3363 u64 mcg_cap;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3367 goto out;
3368 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3369 break;
3370 }
3371 case KVM_X86_SET_MCE: {
3372 struct kvm_x86_mce mce;
3373
3374 r = -EFAULT;
3375 if (copy_from_user(&mce, argp, sizeof mce))
3376 goto out;
3377 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3378 break;
3379 }
3cfc3092
JK		 3380 case KVM_GET_VCPU_EVENTS: {
3381 struct kvm_vcpu_events events;
3382
3383 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3384
3385 r = -EFAULT;
3386 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3387 break;
3388 r = 0;
3389 break;
3390 }
3391 case KVM_SET_VCPU_EVENTS: {
3392 struct kvm_vcpu_events events;
3393
3394 r = -EFAULT;
3395 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3396 break;
3397
3398 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3399 break;
3400 }
a1efbe77
JK		 3401 case KVM_GET_DEBUGREGS: {
3402 struct kvm_debugregs dbgregs;
3403
3404 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3405
3406 r = -EFAULT;
3407 if (copy_to_user(argp, &dbgregs,
3408 sizeof(struct kvm_debugregs)))
3409 break;
3410 r = 0;
3411 break;
3412 }
3413 case KVM_SET_DEBUGREGS: {
3414 struct kvm_debugregs dbgregs;
3415
3416 r = -EFAULT;
3417 if (copy_from_user(&dbgregs, argp,
3418 sizeof(struct kvm_debugregs)))
3419 break;
3420
3421 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3422 break;
3423 }
2d5b5a66 3424 case KVM_GET_XSAVE: {
d1ac91d8 3425 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3426 r = -ENOMEM;
d1ac91d8 3427 if (!u.xsave)
2d5b5a66
SY		 3428 break;
3429
d1ac91d8 3430 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3431
3432 r = -EFAULT;
d1ac91d8 3433 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3434 break;
3435 r = 0;
3436 break;
3437 }
3438 case KVM_SET_XSAVE: {
ff5c2c03 3439 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3440 if (IS_ERR(u.xsave))
3441 return PTR_ERR(u.xsave);
2d5b5a66 3442
d1ac91d8 3443 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3444 break;
3445 }
3446 case KVM_GET_XCRS: {
d1ac91d8 3447 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3448 r = -ENOMEM;
d1ac91d8 3449 if (!u.xcrs)
2d5b5a66
SY		 3450 break;
3451
d1ac91d8 3452 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3453
3454 r = -EFAULT;
d1ac91d8 3455 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3456 sizeof(struct kvm_xcrs)))
3457 break;
3458 r = 0;
3459 break;
3460 }
3461 case KVM_SET_XCRS: {
ff5c2c03 3462 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3463 if (IS_ERR(u.xcrs))
3464 return PTR_ERR(u.xcrs);
2d5b5a66 3465
d1ac91d8 3466 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3467 break;
3468 }
92a1f12d
JR		 3469 case KVM_SET_TSC_KHZ: {
3470 u32 user_tsc_khz;
3471
3472 r = -EINVAL;
92a1f12d
JR		 3473 user_tsc_khz = (u32)arg;
3474
3475 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3476 goto out;
3477
cc578287
ZA		 3478 if (user_tsc_khz == 0)
3479 user_tsc_khz = tsc_khz;
3480
381d585c
HZ		 3481 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3482 r = 0;
92a1f12d 3483
92a1f12d
JR		 3484 goto out;
3485 }
3486 case KVM_GET_TSC_KHZ: {
cc578287 3487 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3488 goto out;
3489 }
1c0b28c2
EM		 3490 case KVM_KVMCLOCK_CTRL: {
3491 r = kvm_set_guest_paused(vcpu);
3492 goto out;
3493 }
5c919412
AS		 3494 case KVM_ENABLE_CAP: {
3495 struct kvm_enable_cap cap;
3496
3497 r = -EFAULT;
3498 if (copy_from_user(&cap, argp, sizeof(cap)))
3499 goto out;
3500 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3501 break;
3502 }
313a3dc7
CO		 3503 default:
3504 r = -EINVAL;
3505 }
3506out:
d1ac91d8 3507 kfree(u.buffer);
313a3dc7
CO		 3508 return r;
3509}
3510
5b1c1493
CO		 3511int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3512{
3513 return VM_FAULT_SIGBUS;
3514}
3515
1fe779f8
CO		 3516static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3517{
3518 int ret;
3519
3520 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3521 return -EINVAL;
1fe779f8
CO		 3522 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3523 return ret;
3524}
3525
b927a3ce
SY		 3526static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3527 u64 ident_addr)
3528{
3529 kvm->arch.ept_identity_map_addr = ident_addr;
3530 return 0;
3531}
3532
1fe779f8
CO		 3533static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3534 u32 kvm_nr_mmu_pages)
3535{
3536 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3537 return -EINVAL;
3538
79fac95e 3539 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3540
3541 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3542 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3543
79fac95e 3544 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3545 return 0;
3546}
3547
3548static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3549{
39de71ec 3550 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3551}
3552
1fe779f8
CO		 3553static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3554{
3555 int r;
3556
3557 r = 0;
3558 switch (chip->chip_id) {
3559 case KVM_IRQCHIP_PIC_MASTER:
3560 memcpy(&chip->chip.pic,
3561 &pic_irqchip(kvm)->pics[0],
3562 sizeof(struct kvm_pic_state));
3563 break;
3564 case KVM_IRQCHIP_PIC_SLAVE:
3565 memcpy(&chip->chip.pic,
3566 &pic_irqchip(kvm)->pics[1],
3567 sizeof(struct kvm_pic_state));
3568 break;
3569 case KVM_IRQCHIP_IOAPIC:
eba0226b 3570 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3571 break;
3572 default:
3573 r = -EINVAL;
3574 break;
3575 }
3576 return r;
3577}
3578
3579static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3580{
3581 int r;
3582
3583 r = 0;
3584 switch (chip->chip_id) {
3585 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3586 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3587 memcpy(&pic_irqchip(kvm)->pics[0],
3588 &chip->chip.pic,
3589 sizeof(struct kvm_pic_state));
f4f51050 3590 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3591 break;
3592 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3593 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3594 memcpy(&pic_irqchip(kvm)->pics[1],
3595 &chip->chip.pic,
3596 sizeof(struct kvm_pic_state));
f4f51050 3597 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3598 break;
3599 case KVM_IRQCHIP_IOAPIC:
eba0226b 3600 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3601 break;
3602 default:
3603 r = -EINVAL;
3604 break;
3605 }
3606 kvm_pic_update_irq(pic_irqchip(kvm));
3607 return r;
3608}
3609
e0f63cb9
SY		 3610static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3611{
34f3941c
RK		 3612 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3613
3614 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3615
3616 mutex_lock(&kps->lock);
3617 memcpy(ps, &kps->channels, sizeof(*ps));
3618 mutex_unlock(&kps->lock);
2da29bcc 3619 return 0;
e0f63cb9
SY		 3620}
3621
3622static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3623{
0185604c 3624 int i;
09edea72
RK		 3625 struct kvm_pit *pit = kvm->arch.vpit;
3626
3627 mutex_lock(&pit->pit_state.lock);
34f3941c 3628 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3629 for (i = 0; i < 3; i++)
09edea72
RK		 3630 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3631 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3632 return 0;
e9f42757
BK		 3633}
3634
3635static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3636{
e9f42757
BK		 3637 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3638 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3639 sizeof(ps->channels));
3640 ps->flags = kvm->arch.vpit->pit_state.flags;
3641 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3642 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3643 return 0;
e9f42757
BK		 3644}
3645
3646static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3647{
2da29bcc 3648 int start = 0;
0185604c 3649 int i;
e9f42757 3650 u32 prev_legacy, cur_legacy;
09edea72
RK		 3651 struct kvm_pit *pit = kvm->arch.vpit;
3652
3653 mutex_lock(&pit->pit_state.lock);
3654 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3655 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3656 if (!prev_legacy && cur_legacy)
3657 start = 1;
09edea72
RK		 3658 memcpy(&pit->pit_state.channels, &ps->channels,
3659 sizeof(pit->pit_state.channels));
3660 pit->pit_state.flags = ps->flags;
0185604c 3661 for (i = 0; i < 3; i++)
09edea72 3662 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3663 start && i == 0);
09edea72 3664 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3665 return 0;
e0f63cb9
SY		 3666}
3667
52d939a0
MT		 3668static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3669 struct kvm_reinject_control *control)
3670{
71474e2f
RK		 3671 struct kvm_pit *pit = kvm->arch.vpit;
3672
3673 if (!pit)
52d939a0 3674 return -ENXIO;
b39c90b6 3675
71474e2f
RK		 3676 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3677 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3678 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3679 */
3680 mutex_lock(&pit->pit_state.lock);
3681 kvm_pit_set_reinject(pit, control->pit_reinject);
3682 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3683
52d939a0
MT		 3684 return 0;
3685}
3686
95d4c16c 3687/**
60c34612
TY		 3688 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3689 * @kvm: kvm instance
3690 * @log: slot id and address to which we copy the log
95d4c16c 3691 *
e108ff2f
PB		 3692 * Steps 1-4 below provide general overview of dirty page logging. See
3693 * kvm_get_dirty_log_protect() function description for additional details.
3694 *
3695 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3696 * always flush the TLB (step 4) even if previous step failed and the dirty
3697 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3698 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3699 * writes will be marked dirty for next log read.
95d4c16c 3700 *
60c34612
TY		 3701 * 1. Take a snapshot of the bit and clear it if needed.
3702 * 2. Write protect the corresponding page.
e108ff2f
PB		 3703 * 3. Copy the snapshot to the userspace.
3704 * 4. Flush TLB's if needed.
5bb064dc 3705 */
60c34612 3706int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3707{
60c34612 3708 bool is_dirty = false;
e108ff2f 3709 int r;
5bb064dc 3710
79fac95e 3711 mutex_lock(&kvm->slots_lock);
5bb064dc 3712
88178fd4
KH		 3713 /*
3714 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3715 */
3716 if (kvm_x86_ops->flush_log_dirty)
3717 kvm_x86_ops->flush_log_dirty(kvm);
3718
e108ff2f 3719 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3720
3721 /*
3722 * All the TLBs can be flushed out of mmu lock, see the comments in
3723 * kvm_mmu_slot_remove_write_access().
3724 */
e108ff2f 3725 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3726 if (is_dirty)
3727 kvm_flush_remote_tlbs(kvm);
3728
79fac95e 3729 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3730 return r;
3731}
3732
aa2fbe6d
YZ		 3733int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3734 bool line_status)
23d43cf9
CD		 3735{
3736 if (!irqchip_in_kernel(kvm))
3737 return -ENXIO;
3738
3739 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3740 irq_event->irq, irq_event->level,
3741 line_status);
23d43cf9
CD		 3742 return 0;
3743}
3744
90de4a18
NA		 3745static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3746 struct kvm_enable_cap *cap)
3747{
3748 int r;
3749
3750 if (cap->flags)
3751 return -EINVAL;
3752
3753 switch (cap->cap) {
3754 case KVM_CAP_DISABLE_QUIRKS:
3755 kvm->arch.disabled_quirks = cap->args[0];
3756 r = 0;
3757 break;
49df6397
SR		 3758 case KVM_CAP_SPLIT_IRQCHIP: {
3759 mutex_lock(&kvm->lock);
b053b2ae
SR		 3760 r = -EINVAL;
3761 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3762 goto split_irqchip_unlock;
49df6397
SR		 3763 r = -EEXIST;
3764 if (irqchip_in_kernel(kvm))
3765 goto split_irqchip_unlock;
3766 if (atomic_read(&kvm->online_vcpus))
3767 goto split_irqchip_unlock;
3768 r = kvm_setup_empty_irq_routing(kvm);
3769 if (r)
3770 goto split_irqchip_unlock;
3771 /* Pairs with irqchip_in_kernel. */
3772 smp_wmb();
3773 kvm->arch.irqchip_split = true;
b053b2ae 3774 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3775 r = 0;
3776split_irqchip_unlock:
3777 mutex_unlock(&kvm->lock);
3778 break;
3779 }
90de4a18
NA		 3780 default:
3781 r = -EINVAL;
3782 break;
3783 }
3784 return r;
3785}
3786
1fe779f8
CO		 3787long kvm_arch_vm_ioctl(struct file *filp,
3788 unsigned int ioctl, unsigned long arg)
3789{
3790 struct kvm *kvm = filp->private_data;
3791 void __user *argp = (void __user *)arg;
367e1319 3792 int r = -ENOTTY;
f0d66275
DH		 3793 /*
3794 * This union makes it completely explicit to gcc-3.x
3795 * that these two variables' stack usage should be
3796 * combined, not added together.
3797 */
3798 union {
3799 struct kvm_pit_state ps;
e9f42757 3800 struct kvm_pit_state2 ps2;
c5ff41ce 3801 struct kvm_pit_config pit_config;
f0d66275 3802 } u;
1fe779f8
CO		 3803
3804 switch (ioctl) {
3805 case KVM_SET_TSS_ADDR:
3806 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3807 break;
b927a3ce
SY		 3808 case KVM_SET_IDENTITY_MAP_ADDR: {
3809 u64 ident_addr;
3810
3811 r = -EFAULT;
3812 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3813 goto out;
3814 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3815 break;
3816 }
1fe779f8
CO		 3817 case KVM_SET_NR_MMU_PAGES:
3818 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3819 break;
3820 case KVM_GET_NR_MMU_PAGES:
3821 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3822 break;
3ddea128
MT		 3823 case KVM_CREATE_IRQCHIP: {
3824 struct kvm_pic *vpic;
3825
3826 mutex_lock(&kvm->lock);
3827 r = -EEXIST;
3828 if (kvm->arch.vpic)
3829 goto create_irqchip_unlock;
3e515705
AK		 3830 r = -EINVAL;
3831 if (atomic_read(&kvm->online_vcpus))
3832 goto create_irqchip_unlock;
1fe779f8 3833 r = -ENOMEM;
3ddea128
MT		 3834 vpic = kvm_create_pic(kvm);
3835 if (vpic) {
1fe779f8
CO		 3836 r = kvm_ioapic_init(kvm);
3837 if (r) {
175504cd 3838 mutex_lock(&kvm->slots_lock);
71ba994c 3839 kvm_destroy_pic(vpic);
175504cd 3840 mutex_unlock(&kvm->slots_lock);
3ddea128 3841 goto create_irqchip_unlock;
1fe779f8
CO		 3842 }
3843 } else
3ddea128 3844 goto create_irqchip_unlock;
399ec807
AK		 3845 r = kvm_setup_default_irq_routing(kvm);
3846 if (r) {
175504cd 3847 mutex_lock(&kvm->slots_lock);
3ddea128 3848 mutex_lock(&kvm->irq_lock);
72bb2fcd 3849 kvm_ioapic_destroy(kvm);
71ba994c 3850 kvm_destroy_pic(vpic);
3ddea128 3851 mutex_unlock(&kvm->irq_lock);
175504cd 3852 mutex_unlock(&kvm->slots_lock);
71ba994c 3853 goto create_irqchip_unlock;
399ec807 3854 }
71ba994c
PB		 3855 /* Write kvm->irq_routing before kvm->arch.vpic. */
3856 smp_wmb();
3857 kvm->arch.vpic = vpic;
3ddea128
MT		 3858 create_irqchip_unlock:
3859 mutex_unlock(&kvm->lock);
1fe779f8 3860 break;
3ddea128 3861 }
7837699f 3862 case KVM_CREATE_PIT:
c5ff41ce
JK		 3863 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3864 goto create_pit;
3865 case KVM_CREATE_PIT2:
3866 r = -EFAULT;
3867 if (copy_from_user(&u.pit_config, argp,
3868 sizeof(struct kvm_pit_config)))
3869 goto out;
3870 create_pit:
79fac95e 3871 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3872 r = -EEXIST;
3873 if (kvm->arch.vpit)
3874 goto create_pit_unlock;
7837699f 3875 r = -ENOMEM;
c5ff41ce 3876 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3877 if (kvm->arch.vpit)
3878 r = 0;
269e05e4 3879 create_pit_unlock:
79fac95e 3880 mutex_unlock(&kvm->slots_lock);
7837699f 3881 break;
1fe779f8
CO		 3882 case KVM_GET_IRQCHIP: {
3883 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3884 struct kvm_irqchip *chip;
1fe779f8 3885
ff5c2c03
SL		 3886 chip = memdup_user(argp, sizeof(*chip));
3887 if (IS_ERR(chip)) {
3888 r = PTR_ERR(chip);
1fe779f8 3889 goto out;
ff5c2c03
SL		 3890 }
3891
1fe779f8 3892 r = -ENXIO;
49df6397 3893 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3894 goto get_irqchip_out;
3895 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3896 if (r)
f0d66275 3897 goto get_irqchip_out;
1fe779f8 3898 r = -EFAULT;
f0d66275
DH		 3899 if (copy_to_user(argp, chip, sizeof *chip))
3900 goto get_irqchip_out;
1fe779f8 3901 r = 0;
f0d66275
DH		 3902 get_irqchip_out:
3903 kfree(chip);
1fe779f8
CO		 3904 break;
3905 }
3906 case KVM_SET_IRQCHIP: {
3907 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3908 struct kvm_irqchip *chip;
1fe779f8 3909
ff5c2c03
SL		 3910 chip = memdup_user(argp, sizeof(*chip));
3911 if (IS_ERR(chip)) {
3912 r = PTR_ERR(chip);
1fe779f8 3913 goto out;
ff5c2c03
SL		 3914 }
3915
1fe779f8 3916 r = -ENXIO;
49df6397 3917 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3918 goto set_irqchip_out;
3919 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3920 if (r)
f0d66275 3921 goto set_irqchip_out;
1fe779f8 3922 r = 0;
f0d66275
DH		 3923 set_irqchip_out:
3924 kfree(chip);
1fe779f8
CO		 3925 break;
3926 }
e0f63cb9 3927 case KVM_GET_PIT: {
e0f63cb9 3928 r = -EFAULT;
f0d66275 3929 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3930 goto out;
3931 r = -ENXIO;
3932 if (!kvm->arch.vpit)
3933 goto out;
f0d66275 3934 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3935 if (r)
3936 goto out;
3937 r = -EFAULT;
f0d66275 3938 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3939 goto out;
3940 r = 0;
3941 break;
3942 }
3943 case KVM_SET_PIT: {
e0f63cb9 3944 r = -EFAULT;
f0d66275 3945 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3946 goto out;
3947 r = -ENXIO;
3948 if (!kvm->arch.vpit)
3949 goto out;
f0d66275 3950 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3951 break;
3952 }
e9f42757
BK		 3953 case KVM_GET_PIT2: {
3954 r = -ENXIO;
3955 if (!kvm->arch.vpit)
3956 goto out;
3957 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3958 if (r)
3959 goto out;
3960 r = -EFAULT;
3961 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3962 goto out;
3963 r = 0;
3964 break;
3965 }
3966 case KVM_SET_PIT2: {
3967 r = -EFAULT;
3968 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3969 goto out;
3970 r = -ENXIO;
3971 if (!kvm->arch.vpit)
3972 goto out;
3973 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3974 break;
3975 }
52d939a0
MT		 3976 case KVM_REINJECT_CONTROL: {
3977 struct kvm_reinject_control control;
3978 r = -EFAULT;
3979 if (copy_from_user(&control, argp, sizeof(control)))
3980 goto out;
3981 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3982 break;
3983 }
d71ba788
PB		 3984 case KVM_SET_BOOT_CPU_ID:
3985 r = 0;
3986 mutex_lock(&kvm->lock);
3987 if (atomic_read(&kvm->online_vcpus) != 0)
3988 r = -EBUSY;
3989 else
3990 kvm->arch.bsp_vcpu_id = arg;
3991 mutex_unlock(&kvm->lock);
3992 break;
ffde22ac
ES		 3993 case KVM_XEN_HVM_CONFIG: {
3994 r = -EFAULT;
3995 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3996 sizeof(struct kvm_xen_hvm_config)))
3997 goto out;
3998 r = -EINVAL;
3999 if (kvm->arch.xen_hvm_config.flags)
4000 goto out;
4001 r = 0;
4002 break;
4003 }
afbcf7ab 4004 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4005 struct kvm_clock_data user_ns;
4006 u64 now_ns;
4007 s64 delta;
4008
4009 r = -EFAULT;
4010 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4011 goto out;
4012
4013 r = -EINVAL;
4014 if (user_ns.flags)
4015 goto out;
4016
4017 r = 0;
395c6b0a 4018 local_irq_disable();
759379dd 4019 now_ns = get_kernel_ns();
afbcf7ab 4020 delta = user_ns.clock - now_ns;
395c6b0a 4021 local_irq_enable();
afbcf7ab 4022 kvm->arch.kvmclock_offset = delta;
2e762ff7 4023 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4024 break;
4025 }
4026 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4027 struct kvm_clock_data user_ns;
4028 u64 now_ns;
4029
395c6b0a 4030 local_irq_disable();
759379dd 4031 now_ns = get_kernel_ns();
afbcf7ab 4032 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4033 local_irq_enable();
afbcf7ab 4034 user_ns.flags = 0;
97e69aa6 4035 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4036
4037 r = -EFAULT;
4038 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4039 goto out;
4040 r = 0;
4041 break;
4042 }
90de4a18
NA		 4043 case KVM_ENABLE_CAP: {
4044 struct kvm_enable_cap cap;
afbcf7ab 4045
90de4a18
NA		 4046 r = -EFAULT;
4047 if (copy_from_user(&cap, argp, sizeof(cap)))
4048 goto out;
4049 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4050 break;
4051 }
1fe779f8 4052 default:
c274e03a 4053 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4054 }
4055out:
4056 return r;
4057}
4058
a16b043c 4059static void kvm_init_msr_list(void)
043405e1
CO		 4060{
4061 u32 dummy[2];
4062 unsigned i, j;
4063
62ef68bb 4064 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4065 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4066 continue;
93c4adc7
PB		 4067
4068 /*
4069 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4070 * to the guests in some cases.
93c4adc7
PB		 4071 */
4072 switch (msrs_to_save[i]) {
4073 case MSR_IA32_BNDCFGS:
4074 if (!kvm_x86_ops->mpx_supported())
4075 continue;
4076 break;
9dbe6cf9
PB		 4077 case MSR_TSC_AUX:
4078 if (!kvm_x86_ops->rdtscp_supported())
4079 continue;
4080 break;
93c4adc7
PB		 4081 default:
4082 break;
4083 }
4084
043405e1
CO		 4085 if (j < i)
4086 msrs_to_save[j] = msrs_to_save[i];
4087 j++;
4088 }
4089 num_msrs_to_save = j;
62ef68bb
PB		 4090
4091 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4092 switch (emulated_msrs[i]) {
6d396b55
PB		 4093 case MSR_IA32_SMBASE:
4094 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4095 continue;
4096 break;
62ef68bb
PB		 4097 default:
4098 break;
4099 }
4100
4101 if (j < i)
4102 emulated_msrs[j] = emulated_msrs[i];
4103 j++;
4104 }
4105 num_emulated_msrs = j;
043405e1
CO		 4106}
4107
bda9020e
MT		 4108static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4109 const void *v)
bbd9b64e 4110{
70252a10
AK		 4111 int handled = 0;
4112 int n;
4113
4114 do {
4115 n = min(len, 8);
bce87cce 4116 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4117 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4118 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4119 break;
4120 handled += n;
4121 addr += n;
4122 len -= n;
4123 v += n;
4124 } while (len);
bbd9b64e 4125
70252a10 4126 return handled;
bbd9b64e
CO		 4127}
4128
bda9020e 4129static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4130{
70252a10
AK		 4131 int handled = 0;
4132 int n;
4133
4134 do {
4135 n = min(len, 8);
bce87cce 4136 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4137 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4138 addr, n, v))
4139 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4140 break;
4141 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4142 handled += n;
4143 addr += n;
4144 len -= n;
4145 v += n;
4146 } while (len);
bbd9b64e 4147
70252a10 4148 return handled;
bbd9b64e
CO		 4149}
4150
2dafc6c2
GN		 4151static void kvm_set_segment(struct kvm_vcpu *vcpu,
4152 struct kvm_segment *var, int seg)
4153{
4154 kvm_x86_ops->set_segment(vcpu, var, seg);
4155}
4156
4157void kvm_get_segment(struct kvm_vcpu *vcpu,
4158 struct kvm_segment *var, int seg)
4159{
4160 kvm_x86_ops->get_segment(vcpu, var, seg);
4161}
4162
54987b7a
PB		 4163gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4164 struct x86_exception *exception)
02f59dc9
JR		 4165{
4166 gpa_t t_gpa;
02f59dc9
JR		 4167
4168 BUG_ON(!mmu_is_nested(vcpu));
4169
4170 /* NPT walks are always user-walks */
4171 access |= PFERR_USER_MASK;
54987b7a 4172 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4173
4174 return t_gpa;
4175}
4176
ab9ae313
AK		 4177gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4178 struct x86_exception *exception)
1871c602
GN		 4179{
4180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4181 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4182}
4183
ab9ae313
AK		 4184 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4185 struct x86_exception *exception)
1871c602
GN		 4186{
4187 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4188 access |= PFERR_FETCH_MASK;
ab9ae313 4189 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4190}
4191
ab9ae313
AK		 4192gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4193 struct x86_exception *exception)
1871c602
GN		 4194{
4195 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4196 access |= PFERR_WRITE_MASK;
ab9ae313 4197 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4198}
4199
4200/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4201gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4202 struct x86_exception *exception)
1871c602 4203{
ab9ae313 4204 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4205}
4206
4207static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4208 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4209 struct x86_exception *exception)
bbd9b64e
CO		 4210{
4211 void *data = val;
10589a46 4212 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4213
4214 while (bytes) {
14dfe855 4215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4216 exception);
bbd9b64e 4217 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4218 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4219 int ret;
4220
bcc55cba 4221 if (gpa == UNMAPPED_GVA)
ab9ae313 4222 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4223 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4224 offset, toread);
10589a46 4225 if (ret < 0) {
c3cd7ffa 4226 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4227 goto out;
4228 }
bbd9b64e 4229
77c2002e
IE		 4230 bytes -= toread;
4231 data += toread;
4232 addr += toread;
bbd9b64e 4233 }
10589a46 4234out:
10589a46 4235 return r;
bbd9b64e 4236}
77c2002e 4237
1871c602 4238/* used for instruction fetching */
0f65dd70
AK		 4239static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4240 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4241 struct x86_exception *exception)
1871c602 4242{
0f65dd70 4243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4244 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4245 unsigned offset;
4246 int ret;
0f65dd70 4247
44583cba
PB		 4248 /* Inline kvm_read_guest_virt_helper for speed. */
4249 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4250 exception);
4251 if (unlikely(gpa == UNMAPPED_GVA))
4252 return X86EMUL_PROPAGATE_FAULT;
4253
4254 offset = addr & (PAGE_SIZE-1);
4255 if (WARN_ON(offset + bytes > PAGE_SIZE))
4256 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4257 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4258 offset, bytes);
44583cba
PB		 4259 if (unlikely(ret < 0))
4260 return X86EMUL_IO_NEEDED;
4261
4262 return X86EMUL_CONTINUE;
1871c602
GN		 4263}
4264
064aea77 4265int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4266 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4267 struct x86_exception *exception)
1871c602 4268{
0f65dd70 4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4271
1871c602 4272 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4273 exception);
1871c602 4274}
064aea77 4275EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4276
0f65dd70
AK		 4277static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4278 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4279 struct x86_exception *exception)
1871c602 4280{
0f65dd70 4281 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4282 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4283}
4284
7a036a6f
RK		 4285static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4286 unsigned long addr, void *val, unsigned int bytes)
4287{
4288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4289 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4290
4291 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4292}
4293
6a4d7550 4294int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4295 gva_t addr, void *val,
2dafc6c2 4296 unsigned int bytes,
bcc55cba 4297 struct x86_exception *exception)
77c2002e 4298{
0f65dd70 4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4300 void *data = val;
4301 int r = X86EMUL_CONTINUE;
4302
4303 while (bytes) {
14dfe855
JR		 4304 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4305 PFERR_WRITE_MASK,
ab9ae313 4306 exception);
77c2002e
IE		 4307 unsigned offset = addr & (PAGE_SIZE-1);
4308 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4309 int ret;
4310
bcc55cba 4311 if (gpa == UNMAPPED_GVA)
ab9ae313 4312 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4313 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4314 if (ret < 0) {
c3cd7ffa 4315 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4316 goto out;
4317 }
4318
4319 bytes -= towrite;
4320 data += towrite;
4321 addr += towrite;
4322 }
4323out:
4324 return r;
4325}
6a4d7550 4326EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4327
af7cc7d1
XG		 4328static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4329 gpa_t *gpa, struct x86_exception *exception,
4330 bool write)
4331{
97d64b78
AK		 4332 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4333 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4334
be94f6b7
HH		 4335 /*
4336 * currently PKRU is only applied to ept enabled guest so
4337 * there is no pkey in EPT page table for L1 guest or EPT
4338 * shadow page table for L2 guest.
4339 */
97d64b78 4340 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4341 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4342 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4343 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4344 (gva & (PAGE_SIZE - 1));
4f022648 4345 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4346 return 1;
4347 }
4348
af7cc7d1
XG		 4349 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4350
4351 if (*gpa == UNMAPPED_GVA)
4352 return -1;
4353
4354 /* For APIC access vmexit */
4355 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4356 return 1;
4357
4f022648
XG		 4358 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4359 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4360 return 1;
4f022648 4361 }
bebb106a 4362
af7cc7d1
XG		 4363 return 0;
4364}
4365
3200f405 4366int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4367 const void *val, int bytes)
bbd9b64e
CO		 4368{
4369 int ret;
4370
54bf36aa 4371 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4372 if (ret < 0)
bbd9b64e 4373 return 0;
0eb05bf2 4374 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4375 return 1;
4376}
4377
77d197b2
XG		 4378struct read_write_emulator_ops {
4379 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4380 int bytes);
4381 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4382 void *val, int bytes);
4383 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 int bytes, void *val);
4385 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4386 void *val, int bytes);
4387 bool write;
4388};
4389
4390static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4391{
4392 if (vcpu->mmio_read_completed) {
77d197b2 4393 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4394 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4395 vcpu->mmio_read_completed = 0;
4396 return 1;
4397 }
4398
4399 return 0;
4400}
4401
4402static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes)
4404{
54bf36aa 4405 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4406}
4407
4408static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4409 void *val, int bytes)
4410{
4411 return emulator_write_phys(vcpu, gpa, val, bytes);
4412}
4413
4414static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4415{
4416 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4417 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4418}
4419
4420static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4422{
4423 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4424 return X86EMUL_IO_NEEDED;
4425}
4426
4427static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4428 void *val, int bytes)
4429{
f78146b0
AK		 4430 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4431
87da7e66 4432 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4433 return X86EMUL_CONTINUE;
4434}
4435
0fbe9b0b 4436static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4437 .read_write_prepare = read_prepare,
4438 .read_write_emulate = read_emulate,
4439 .read_write_mmio = vcpu_mmio_read,
4440 .read_write_exit_mmio = read_exit_mmio,
4441};
4442
0fbe9b0b 4443static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4444 .read_write_emulate = write_emulate,
4445 .read_write_mmio = write_mmio,
4446 .read_write_exit_mmio = write_exit_mmio,
4447 .write = true,
4448};
4449
22388a3c
XG		 4450static int emulator_read_write_onepage(unsigned long addr, void *val,
4451 unsigned int bytes,
4452 struct x86_exception *exception,
4453 struct kvm_vcpu *vcpu,
0fbe9b0b 4454 const struct read_write_emulator_ops *ops)
bbd9b64e 4455{
af7cc7d1
XG		 4456 gpa_t gpa;
4457 int handled, ret;
22388a3c 4458 bool write = ops->write;
f78146b0 4459 struct kvm_mmio_fragment *frag;
10589a46 4460
22388a3c 4461 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4462
af7cc7d1 4463 if (ret < 0)
bbd9b64e 4464 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4465
4466 /* For APIC access vmexit */
af7cc7d1 4467 if (ret)
bbd9b64e
CO		 4468 goto mmio;
4469
22388a3c 4470 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4471 return X86EMUL_CONTINUE;
4472
4473mmio:
4474 /*
4475 * Is this MMIO handled locally?
4476 */
22388a3c 4477 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4478 if (handled == bytes)
bbd9b64e 4479 return X86EMUL_CONTINUE;
bbd9b64e 4480
70252a10
AK		 4481 gpa += handled;
4482 bytes -= handled;
4483 val += handled;
4484
87da7e66
XG		 4485 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4486 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4487 frag->gpa = gpa;
4488 frag->data = val;
4489 frag->len = bytes;
f78146b0 4490 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4491}
4492
52eb5a6d
XL		 4493static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4494 unsigned long addr,
22388a3c
XG		 4495 void *val, unsigned int bytes,
4496 struct x86_exception *exception,
0fbe9b0b 4497 const struct read_write_emulator_ops *ops)
bbd9b64e 4498{
0f65dd70 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4500 gpa_t gpa;
4501 int rc;
4502
4503 if (ops->read_write_prepare &&
4504 ops->read_write_prepare(vcpu, val, bytes))
4505 return X86EMUL_CONTINUE;
4506
4507 vcpu->mmio_nr_fragments = 0;
0f65dd70 4508
bbd9b64e
CO		 4509 /* Crossing a page boundary? */
4510 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4511 int now;
bbd9b64e
CO		 4512
4513 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4514 rc = emulator_read_write_onepage(addr, val, now, exception,
4515 vcpu, ops);
4516
bbd9b64e
CO		 4517 if (rc != X86EMUL_CONTINUE)
4518 return rc;
4519 addr += now;
bac15531
NA		 4520 if (ctxt->mode != X86EMUL_MODE_PROT64)
4521 addr = (u32)addr;
bbd9b64e
CO		 4522 val += now;
4523 bytes -= now;
4524 }
22388a3c 4525
f78146b0
AK		 4526 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4527 vcpu, ops);
4528 if (rc != X86EMUL_CONTINUE)
4529 return rc;
4530
4531 if (!vcpu->mmio_nr_fragments)
4532 return rc;
4533
4534 gpa = vcpu->mmio_fragments[0].gpa;
4535
4536 vcpu->mmio_needed = 1;
4537 vcpu->mmio_cur_fragment = 0;
4538
87da7e66 4539 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4540 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4541 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4542 vcpu->run->mmio.phys_addr = gpa;
4543
4544 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4545}
4546
4547static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4548 unsigned long addr,
4549 void *val,
4550 unsigned int bytes,
4551 struct x86_exception *exception)
4552{
4553 return emulator_read_write(ctxt, addr, val, bytes,
4554 exception, &read_emultor);
4555}
4556
52eb5a6d 4557static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4558 unsigned long addr,
4559 const void *val,
4560 unsigned int bytes,
4561 struct x86_exception *exception)
4562{
4563 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4564 exception, &write_emultor);
bbd9b64e 4565}
bbd9b64e 4566
daea3e73
AK		 4567#define CMPXCHG_TYPE(t, ptr, old, new) \
4568 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4569
4570#ifdef CONFIG_X86_64
4571# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4572#else
4573# define CMPXCHG64(ptr, old, new) \
9749a6c0 4574 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4575#endif
4576
0f65dd70
AK		 4577static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4578 unsigned long addr,
bbd9b64e
CO		 4579 const void *old,
4580 const void *new,
4581 unsigned int bytes,
0f65dd70 4582 struct x86_exception *exception)
bbd9b64e 4583{
0f65dd70 4584 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4585 gpa_t gpa;
4586 struct page *page;
4587 char *kaddr;
4588 bool exchanged;
2bacc55c 4589
daea3e73
AK		 4590 /* guests cmpxchg8b have to be emulated atomically */
4591 if (bytes > 8 || (bytes & (bytes - 1)))
4592 goto emul_write;
10589a46 4593
daea3e73 4594 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4595
daea3e73
AK		 4596 if (gpa == UNMAPPED_GVA ||
4597 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4598 goto emul_write;
2bacc55c 4599
daea3e73
AK		 4600 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4601 goto emul_write;
72dc67a6 4602
54bf36aa 4603 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4604 if (is_error_page(page))
c19b8bd6 4605 goto emul_write;
72dc67a6 4606
8fd75e12 4607 kaddr = kmap_atomic(page);
daea3e73
AK		 4608 kaddr += offset_in_page(gpa);
4609 switch (bytes) {
4610 case 1:
4611 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4612 break;
4613 case 2:
4614 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4615 break;
4616 case 4:
4617 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4618 break;
4619 case 8:
4620 exchanged = CMPXCHG64(kaddr, old, new);
4621 break;
4622 default:
4623 BUG();
2bacc55c 4624 }
8fd75e12 4625 kunmap_atomic(kaddr);
daea3e73
AK		 4626 kvm_release_page_dirty(page);
4627
4628 if (!exchanged)
4629 return X86EMUL_CMPXCHG_FAILED;
4630
54bf36aa 4631 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4632 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4633
4634 return X86EMUL_CONTINUE;
4a5f48f6 4635
3200f405 4636emul_write:
daea3e73 4637 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4638
0f65dd70 4639 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4640}
4641
cf8f70bf
GN		 4642static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4643{
4644 /* TODO: String I/O for in kernel device */
4645 int r;
4646
4647 if (vcpu->arch.pio.in)
e32edf4f 4648 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4649 vcpu->arch.pio.size, pd);
4650 else
e32edf4f 4651 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4652 vcpu->arch.pio.port, vcpu->arch.pio.size,
4653 pd);
4654 return r;
4655}
4656
6f6fbe98
XG		 4657static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4658 unsigned short port, void *val,
4659 unsigned int count, bool in)
cf8f70bf 4660{
cf8f70bf 4661 vcpu->arch.pio.port = port;
6f6fbe98 4662 vcpu->arch.pio.in = in;
7972995b 4663 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4664 vcpu->arch.pio.size = size;
4665
4666 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4667 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4668 return 1;
4669 }
4670
4671 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4672 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4673 vcpu->run->io.size = size;
4674 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4675 vcpu->run->io.count = count;
4676 vcpu->run->io.port = port;
4677
4678 return 0;
4679}
4680
6f6fbe98
XG		 4681static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4682 int size, unsigned short port, void *val,
4683 unsigned int count)
cf8f70bf 4684{
ca1d4a9e 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4686 int ret;
ca1d4a9e 4687
6f6fbe98
XG		 4688 if (vcpu->arch.pio.count)
4689 goto data_avail;
cf8f70bf 4690
6f6fbe98
XG		 4691 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4692 if (ret) {
4693data_avail:
4694 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4695 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4696 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4697 return 1;
4698 }
4699
cf8f70bf
GN		 4700 return 0;
4701}
4702
6f6fbe98
XG		 4703static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4704 int size, unsigned short port,
4705 const void *val, unsigned int count)
4706{
4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4708
4709 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4710 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4711 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4712}
4713
bbd9b64e
CO		 4714static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4715{
4716 return kvm_x86_ops->get_segment_base(vcpu, seg);
4717}
4718
3cb16fe7 4719static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4720{
3cb16fe7 4721 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4722}
4723
5cb56059 4724int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4725{
4726 if (!need_emulate_wbinvd(vcpu))
4727 return X86EMUL_CONTINUE;
4728
4729 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4730 int cpu = get_cpu();
4731
4732 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4733 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4734 wbinvd_ipi, NULL, 1);
2eec7343 4735 put_cpu();
f5f48ee1 4736 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4737 } else
4738 wbinvd();
f5f48ee1
SY		 4739 return X86EMUL_CONTINUE;
4740}
5cb56059
JS		 4741
4742int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4743{
4744 kvm_x86_ops->skip_emulated_instruction(vcpu);
4745 return kvm_emulate_wbinvd_noskip(vcpu);
4746}
f5f48ee1
SY		 4747EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4748
5cb56059
JS		 4749
4750
bcaf5cc5
AK		 4751static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4752{
5cb56059 4753 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4754}
4755
52eb5a6d
XL		 4756static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4757 unsigned long *dest)
bbd9b64e 4758{
16f8a6f9 4759 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4760}
4761
52eb5a6d
XL		 4762static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4763 unsigned long value)
bbd9b64e 4764{
338dbc97 4765
717746e3 4766 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4767}
4768
52a46617 4769static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4770{
52a46617 4771 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4772}
4773
717746e3 4774static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4775{
717746e3 4776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4777 unsigned long value;
4778
4779 switch (cr) {
4780 case 0:
4781 value = kvm_read_cr0(vcpu);
4782 break;
4783 case 2:
4784 value = vcpu->arch.cr2;
4785 break;
4786 case 3:
9f8fe504 4787 value = kvm_read_cr3(vcpu);
52a46617
GN		 4788 break;
4789 case 4:
4790 value = kvm_read_cr4(vcpu);
4791 break;
4792 case 8:
4793 value = kvm_get_cr8(vcpu);
4794 break;
4795 default:
a737f256 4796 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4797 return 0;
4798 }
4799
4800 return value;
4801}
4802
717746e3 4803static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4804{
717746e3 4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4806 int res = 0;
4807
52a46617
GN		 4808 switch (cr) {
4809 case 0:
49a9b07e 4810 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4811 break;
4812 case 2:
4813 vcpu->arch.cr2 = val;
4814 break;
4815 case 3:
2390218b 4816 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4817 break;
4818 case 4:
a83b29c6 4819 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4820 break;
4821 case 8:
eea1cff9 4822 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4823 break;
4824 default:
a737f256 4825 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4826 res = -1;
52a46617 4827 }
0f12244f
GN		 4828
4829 return res;
52a46617
GN		 4830}
4831
717746e3 4832static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4833{
717746e3 4834 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4835}
4836
4bff1e86 4837static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4838{
4bff1e86 4839 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4840}
4841
4bff1e86 4842static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4843{
4bff1e86 4844 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4845}
4846
1ac9d0cf
AK		 4847static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4848{
4849 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4850}
4851
4852static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4853{
4854 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4855}
4856
4bff1e86
AK		 4857static unsigned long emulator_get_cached_segment_base(
4858 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4859{
4bff1e86 4860 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4861}
4862
1aa36616
AK		 4863static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4864 struct desc_struct *desc, u32 *base3,
4865 int seg)
2dafc6c2
GN		 4866{
4867 struct kvm_segment var;
4868
4bff1e86 4869 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4870 *selector = var.selector;
2dafc6c2 4871
378a8b09
GN		 4872 if (var.unusable) {
4873 memset(desc, 0, sizeof(*desc));
2dafc6c2 4874 return false;
378a8b09 4875 }
2dafc6c2
GN		 4876
4877 if (var.g)
4878 var.limit >>= 12;
4879 set_desc_limit(desc, var.limit);
4880 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4881#ifdef CONFIG_X86_64
4882 if (base3)
4883 *base3 = var.base >> 32;
4884#endif
2dafc6c2
GN		 4885 desc->type = var.type;
4886 desc->s = var.s;
4887 desc->dpl = var.dpl;
4888 desc->p = var.present;
4889 desc->avl = var.avl;
4890 desc->l = var.l;
4891 desc->d = var.db;
4892 desc->g = var.g;
4893
4894 return true;
4895}
4896
1aa36616
AK		 4897static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4898 struct desc_struct *desc, u32 base3,
4899 int seg)
2dafc6c2 4900{
4bff1e86 4901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4902 struct kvm_segment var;
4903
1aa36616 4904 var.selector = selector;
2dafc6c2 4905 var.base = get_desc_base(desc);
5601d05b
GN		 4906#ifdef CONFIG_X86_64
4907 var.base |= ((u64)base3) << 32;
4908#endif
2dafc6c2
GN		 4909 var.limit = get_desc_limit(desc);
4910 if (desc->g)
4911 var.limit = (var.limit << 12) | 0xfff;
4912 var.type = desc->type;
2dafc6c2
GN		 4913 var.dpl = desc->dpl;
4914 var.db = desc->d;
4915 var.s = desc->s;
4916 var.l = desc->l;
4917 var.g = desc->g;
4918 var.avl = desc->avl;
4919 var.present = desc->p;
4920 var.unusable = !var.present;
4921 var.padding = 0;
4922
4923 kvm_set_segment(vcpu, &var, seg);
4924 return;
4925}
4926
717746e3
AK		 4927static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4928 u32 msr_index, u64 *pdata)
4929{
609e36d3
PB		 4930 struct msr_data msr;
4931 int r;
4932
4933 msr.index = msr_index;
4934 msr.host_initiated = false;
4935 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4936 if (r)
4937 return r;
4938
4939 *pdata = msr.data;
4940 return 0;
717746e3
AK		 4941}
4942
4943static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4944 u32 msr_index, u64 data)
4945{
8fe8ab46
WA		 4946 struct msr_data msr;
4947
4948 msr.data = data;
4949 msr.index = msr_index;
4950 msr.host_initiated = false;
4951 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4952}
4953
64d60670
PB		 4954static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4955{
4956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4957
4958 return vcpu->arch.smbase;
4959}
4960
4961static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4962{
4963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4964
4965 vcpu->arch.smbase = smbase;
4966}
4967
67f4d428
NA		 4968static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4969 u32 pmc)
4970{
c6702c9d 4971 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4972}
4973
222d21aa
AK		 4974static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4975 u32 pmc, u64 *pdata)
4976{
c6702c9d 4977 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4978}
4979
6c3287f7
AK		 4980static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4981{
4982 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4983}
4984
5037f6f3
AK		 4985static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4986{
4987 preempt_disable();
5197b808 4988 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4989 /*
4990 * CR0.TS may reference the host fpu state, not the guest fpu state,
4991 * so it may be clear at this point.
4992 */
4993 clts();
4994}
4995
4996static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4997{
4998 preempt_enable();
4999}
5000
2953538e 5001static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5002 struct x86_instruction_info *info,
c4f035c6
AK		 5003 enum x86_intercept_stage stage)
5004{
2953538e 5005 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5006}
5007
0017f93a 5008static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5009 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5010{
0017f93a 5011 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5012}
5013
dd856efa
AK		 5014static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5015{
5016 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5017}
5018
5019static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5020{
5021 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5022}
5023
801806d9
NA		 5024static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5025{
5026 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5027}
5028
0225fb50 5029static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5030 .read_gpr = emulator_read_gpr,
5031 .write_gpr = emulator_write_gpr,
1871c602 5032 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5033 .write_std = kvm_write_guest_virt_system,
7a036a6f 5034 .read_phys = kvm_read_guest_phys_system,
1871c602 5035 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5036 .read_emulated = emulator_read_emulated,
5037 .write_emulated = emulator_write_emulated,
5038 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5039 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5040 .pio_in_emulated = emulator_pio_in_emulated,
5041 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5042 .get_segment = emulator_get_segment,
5043 .set_segment = emulator_set_segment,
5951c442 5044 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5045 .get_gdt = emulator_get_gdt,
160ce1f1 5046 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5047 .set_gdt = emulator_set_gdt,
5048 .set_idt = emulator_set_idt,
52a46617
GN		 5049 .get_cr = emulator_get_cr,
5050 .set_cr = emulator_set_cr,
9c537244 5051 .cpl = emulator_get_cpl,
35aa5375
GN		 5052 .get_dr = emulator_get_dr,
5053 .set_dr = emulator_set_dr,
64d60670
PB		 5054 .get_smbase = emulator_get_smbase,
5055 .set_smbase = emulator_set_smbase,
717746e3
AK		 5056 .set_msr = emulator_set_msr,
5057 .get_msr = emulator_get_msr,
67f4d428 5058 .check_pmc = emulator_check_pmc,
222d21aa 5059 .read_pmc = emulator_read_pmc,
6c3287f7 5060 .halt = emulator_halt,
bcaf5cc5 5061 .wbinvd = emulator_wbinvd,
d6aa1000 5062 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5063 .get_fpu = emulator_get_fpu,
5064 .put_fpu = emulator_put_fpu,
c4f035c6 5065 .intercept = emulator_intercept,
bdb42f5a 5066 .get_cpuid = emulator_get_cpuid,
801806d9 5067 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5068};
5069
95cb2295
GN		 5070static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5071{
37ccdcbe 5072 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5073 /*
5074 * an sti; sti; sequence only disable interrupts for the first
5075 * instruction. So, if the last instruction, be it emulated or
5076 * not, left the system with the INT_STI flag enabled, it
5077 * means that the last instruction is an sti. We should not
5078 * leave the flag on in this case. The same goes for mov ss
5079 */
37ccdcbe
PB		 5080 if (int_shadow & mask)
5081 mask = 0;
6addfc42 5082 if (unlikely(int_shadow || mask)) {
95cb2295 5083 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5084 if (!mask)
5085 kvm_make_request(KVM_REQ_EVENT, vcpu);
5086 }
95cb2295
GN		 5087}
5088
ef54bcfe 5089static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5090{
5091 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5092 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5093 return kvm_propagate_fault(vcpu, &ctxt->exception);
5094
5095 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5096 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5097 ctxt->exception.error_code);
54b8486f 5098 else
da9cb575 5099 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5100 return false;
54b8486f
GN		 5101}
5102
8ec4722d
MG		 5103static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5104{
adf52235 5105 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5106 int cs_db, cs_l;
5107
8ec4722d
MG		 5108 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5109
adf52235
TY		 5110 ctxt->eflags = kvm_get_rflags(vcpu);
5111 ctxt->eip = kvm_rip_read(vcpu);
5112 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5113 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5114 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5115 cs_db ? X86EMUL_MODE_PROT32 :
5116 X86EMUL_MODE_PROT16;
a584539b 5117 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5118 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5119 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5120 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5121
dd856efa 5122 init_decode_cache(ctxt);
7ae441ea 5123 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5124}
5125
71f9833b 5126int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5127{
9d74191a 5128 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5129 int ret;
5130
5131 init_emulate_ctxt(vcpu);
5132
9dac77fa
AK		 5133 ctxt->op_bytes = 2;
5134 ctxt->ad_bytes = 2;
5135 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5136 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5137
5138 if (ret != X86EMUL_CONTINUE)
5139 return EMULATE_FAIL;
5140
9dac77fa 5141 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5142 kvm_rip_write(vcpu, ctxt->eip);
5143 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5144
5145 if (irq == NMI_VECTOR)
7460fb4a 5146 vcpu->arch.nmi_pending = 0;
63995653
MG		 5147 else
5148 vcpu->arch.interrupt.pending = false;
5149
5150 return EMULATE_DONE;
5151}
5152EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5153
6d77dbfc
GN		 5154static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5155{
fc3a9157
JR		 5156 int r = EMULATE_DONE;
5157
6d77dbfc
GN		 5158 ++vcpu->stat.insn_emulation_fail;
5159 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5160 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5161 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5162 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5163 vcpu->run->internal.ndata = 0;
5164 r = EMULATE_FAIL;
5165 }
6d77dbfc 5166 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5167
5168 return r;
6d77dbfc
GN		 5169}
5170
93c05d3e 5171static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5172 bool write_fault_to_shadow_pgtable,
5173 int emulation_type)
a6f177ef 5174{
95b3cf69 5175 gpa_t gpa = cr2;
ba049e93 5176 kvm_pfn_t pfn;
a6f177ef 5177
991eebf9
GN		 5178 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5179 return false;
5180
95b3cf69
XG		 5181 if (!vcpu->arch.mmu.direct_map) {
5182 /*
5183 * Write permission should be allowed since only
5184 * write access need to be emulated.
5185 */
5186 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5187
95b3cf69
XG		 5188 /*
5189 * If the mapping is invalid in guest, let cpu retry
5190 * it to generate fault.
5191 */
5192 if (gpa == UNMAPPED_GVA)
5193 return true;
5194 }
a6f177ef 5195
8e3d9d06
XG		 5196 /*
5197 * Do not retry the unhandleable instruction if it faults on the
5198 * readonly host memory, otherwise it will goto a infinite loop:
5199 * retry instruction -> write #PF -> emulation fail -> retry
5200 * instruction -> ...
5201 */
5202 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5203
5204 /*
5205 * If the instruction failed on the error pfn, it can not be fixed,
5206 * report the error to userspace.
5207 */
5208 if (is_error_noslot_pfn(pfn))
5209 return false;
5210
5211 kvm_release_pfn_clean(pfn);
5212
5213 /* The instructions are well-emulated on direct mmu. */
5214 if (vcpu->arch.mmu.direct_map) {
5215 unsigned int indirect_shadow_pages;
5216
5217 spin_lock(&vcpu->kvm->mmu_lock);
5218 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5219 spin_unlock(&vcpu->kvm->mmu_lock);
5220
5221 if (indirect_shadow_pages)
5222 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5223
a6f177ef 5224 return true;
8e3d9d06 5225 }
a6f177ef 5226
95b3cf69
XG		 5227 /*
5228 * if emulation was due to access to shadowed page table
5229 * and it failed try to unshadow page and re-enter the
5230 * guest to let CPU execute the instruction.
5231 */
5232 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5233
5234 /*
5235 * If the access faults on its page table, it can not
5236 * be fixed by unprotecting shadow page and it should
5237 * be reported to userspace.
5238 */
5239 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5240}
5241
1cb3f3ae
XG		 5242static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5243 unsigned long cr2, int emulation_type)
5244{
5245 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5246 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5247
5248 last_retry_eip = vcpu->arch.last_retry_eip;
5249 last_retry_addr = vcpu->arch.last_retry_addr;
5250
5251 /*
5252 * If the emulation is caused by #PF and it is non-page_table
5253 * writing instruction, it means the VM-EXIT is caused by shadow
5254 * page protected, we can zap the shadow page and retry this
5255 * instruction directly.
5256 *
5257 * Note: if the guest uses a non-page-table modifying instruction
5258 * on the PDE that points to the instruction, then we will unmap
5259 * the instruction and go to an infinite loop. So, we cache the
5260 * last retried eip and the last fault address, if we meet the eip
5261 * and the address again, we can break out of the potential infinite
5262 * loop.
5263 */
5264 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5265
5266 if (!(emulation_type & EMULTYPE_RETRY))
5267 return false;
5268
5269 if (x86_page_table_writing_insn(ctxt))
5270 return false;
5271
5272 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5273 return false;
5274
5275 vcpu->arch.last_retry_eip = ctxt->eip;
5276 vcpu->arch.last_retry_addr = cr2;
5277
5278 if (!vcpu->arch.mmu.direct_map)
5279 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5280
22368028 5281 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5282
5283 return true;
5284}
5285
716d51ab
GN		 5286static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5287static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5288
64d60670 5289static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5290{
64d60670 5291 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5292 /* This is a good place to trace that we are exiting SMM. */
5293 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5294
64d60670
PB		 5295 if (unlikely(vcpu->arch.smi_pending)) {
5296 kvm_make_request(KVM_REQ_SMI, vcpu);
5297 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5298 } else {
5299 /* Process a latched INIT, if any. */
5300 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5301 }
5302 }
699023e2
PB		 5303
5304 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5305}
5306
5307static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5308{
5309 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5310
a584539b 5311 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5312
5313 if (changed & HF_SMM_MASK)
5314 kvm_smm_changed(vcpu);
a584539b
PB		 5315}
5316
4a1e10d5
PB		 5317static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5318 unsigned long *db)
5319{
5320 u32 dr6 = 0;
5321 int i;
5322 u32 enable, rwlen;
5323
5324 enable = dr7;
5325 rwlen = dr7 >> 16;
5326 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5327 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5328 dr6 |= (1 << i);
5329 return dr6;
5330}
5331
6addfc42 5332static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5333{
5334 struct kvm_run *kvm_run = vcpu->run;
5335
5336 /*
6addfc42
PB		 5337 * rflags is the old, "raw" value of the flags. The new value has
5338 * not been saved yet.
663f4c61
PB		 5339 *
5340 * This is correct even for TF set by the guest, because "the
5341 * processor will not generate this exception after the instruction
5342 * that sets the TF flag".
5343 */
663f4c61
PB		 5344 if (unlikely(rflags & X86_EFLAGS_TF)) {
5345 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5346 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5347 DR6_RTM;
663f4c61
PB		 5348 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5349 kvm_run->debug.arch.exception = DB_VECTOR;
5350 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5351 *r = EMULATE_USER_EXIT;
5352 } else {
5353 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5354 /*
5355 * "Certain debug exceptions may clear bit 0-3. The
5356 * remaining contents of the DR6 register are never
5357 * cleared by the processor".
5358 */
5359 vcpu->arch.dr6 &= ~15;
6f43ed01 5360 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5361 kvm_queue_exception(vcpu, DB_VECTOR);
5362 }
5363 }
5364}
5365
4a1e10d5
PB		 5366static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5367{
4a1e10d5
PB		 5368 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5369 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5370 struct kvm_run *kvm_run = vcpu->run;
5371 unsigned long eip = kvm_get_linear_rip(vcpu);
5372 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5373 vcpu->arch.guest_debug_dr7,
5374 vcpu->arch.eff_db);
5375
5376 if (dr6 != 0) {
6f43ed01 5377 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5378 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5379 kvm_run->debug.arch.exception = DB_VECTOR;
5380 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5381 *r = EMULATE_USER_EXIT;
5382 return true;
5383 }
5384 }
5385
4161a569
NA		 5386 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5387 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5388 unsigned long eip = kvm_get_linear_rip(vcpu);
5389 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5390 vcpu->arch.dr7,
5391 vcpu->arch.db);
5392
5393 if (dr6 != 0) {
5394 vcpu->arch.dr6 &= ~15;
6f43ed01 5395 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5396 kvm_queue_exception(vcpu, DB_VECTOR);
5397 *r = EMULATE_DONE;
5398 return true;
5399 }
5400 }
5401
5402 return false;
5403}
5404
51d8b661
AP		 5405int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5406 unsigned long cr2,
dc25e89e
AP		 5407 int emulation_type,
5408 void *insn,
5409 int insn_len)
bbd9b64e 5410{
95cb2295 5411 int r;
9d74191a 5412 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5413 bool writeback = true;
93c05d3e 5414 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5415
93c05d3e
XG		 5416 /*
5417 * Clear write_fault_to_shadow_pgtable here to ensure it is
5418 * never reused.
5419 */
5420 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5421 kvm_clear_exception_queue(vcpu);
8d7d8102 5422
571008da 5423 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5424 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5425
5426 /*
5427 * We will reenter on the same instruction since
5428 * we do not set complete_userspace_io. This does not
5429 * handle watchpoints yet, those would be handled in
5430 * the emulate_ops.
5431 */
5432 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5433 return r;
5434
9d74191a
TY		 5435 ctxt->interruptibility = 0;
5436 ctxt->have_exception = false;
e0ad0b47 5437 ctxt->exception.vector = -1;
9d74191a 5438 ctxt->perm_ok = false;
bbd9b64e 5439
b51e974f 5440 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5441
9d74191a 5442 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5443
e46479f8 5444 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5445 ++vcpu->stat.insn_emulation;
1d2887e2 5446 if (r != EMULATION_OK) {
4005996e
AK		 5447 if (emulation_type & EMULTYPE_TRAP_UD)
5448 return EMULATE_FAIL;
991eebf9
GN		 5449 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5450 emulation_type))
bbd9b64e 5451 return EMULATE_DONE;
6d77dbfc
GN		 5452 if (emulation_type & EMULTYPE_SKIP)
5453 return EMULATE_FAIL;
5454 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5455 }
5456 }
5457
ba8afb6b 5458 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5459 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5460 if (ctxt->eflags & X86_EFLAGS_RF)
5461 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5462 return EMULATE_DONE;
5463 }
5464
1cb3f3ae
XG		 5465 if (retry_instruction(ctxt, cr2, emulation_type))
5466 return EMULATE_DONE;
5467
7ae441ea 5468 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5469 changes registers values during IO operation */
7ae441ea
GN		 5470 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5471 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5472 emulator_invalidate_register_cache(ctxt);
7ae441ea 5473 }
4d2179e1 5474
5cd21917 5475restart:
9d74191a 5476 r = x86_emulate_insn(ctxt);
bbd9b64e 5477
775fde86
JR		 5478 if (r == EMULATION_INTERCEPTED)
5479 return EMULATE_DONE;
5480
d2ddd1c4 5481 if (r == EMULATION_FAILED) {
991eebf9
GN		 5482 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5483 emulation_type))
c3cd7ffa
GN		 5484 return EMULATE_DONE;
5485
6d77dbfc 5486 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5487 }
5488
9d74191a 5489 if (ctxt->have_exception) {
d2ddd1c4 5490 r = EMULATE_DONE;
ef54bcfe
PB		 5491 if (inject_emulated_exception(vcpu))
5492 return r;
d2ddd1c4 5493 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5494 if (!vcpu->arch.pio.in) {
5495 /* FIXME: return into emulator if single-stepping. */
3457e419 5496 vcpu->arch.pio.count = 0;
0912c977 5497 } else {
7ae441ea 5498 writeback = false;
716d51ab
GN		 5499 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5500 }
ac0a48c3 5501 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5502 } else if (vcpu->mmio_needed) {
5503 if (!vcpu->mmio_is_write)
5504 writeback = false;
ac0a48c3 5505 r = EMULATE_USER_EXIT;
716d51ab 5506 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5507 } else if (r == EMULATION_RESTART)
5cd21917 5508 goto restart;
d2ddd1c4
GN		 5509 else
5510 r = EMULATE_DONE;
f850e2e6 5511
7ae441ea 5512 if (writeback) {
6addfc42 5513 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5514 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5515 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5516 if (vcpu->arch.hflags != ctxt->emul_flags)
5517 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5518 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5519 if (r == EMULATE_DONE)
6addfc42 5520 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5521 if (!ctxt->have_exception ||
5522 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5523 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5524
5525 /*
5526 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5527 * do nothing, and it will be requested again as soon as
5528 * the shadow expires. But we still need to check here,
5529 * because POPF has no interrupt shadow.
5530 */
5531 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5532 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5533 } else
5534 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5535
5536 return r;
de7d789a 5537}
51d8b661 5538EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5539
cf8f70bf 5540int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5541{
cf8f70bf 5542 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5543 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5544 size, port, &val, 1);
cf8f70bf 5545 /* do not return to emulator after return from userspace */
7972995b 5546 vcpu->arch.pio.count = 0;
de7d789a
CO		 5547 return ret;
5548}
cf8f70bf 5549EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5550
8cfdc000
ZA		 5551static void tsc_bad(void *info)
5552{
0a3aee0d 5553 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5554}
5555
5556static void tsc_khz_changed(void *data)
c8076604 5557{
8cfdc000
ZA		 5558 struct cpufreq_freqs *freq = data;
5559 unsigned long khz = 0;
5560
5561 if (data)
5562 khz = freq->new;
5563 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5564 khz = cpufreq_quick_get(raw_smp_processor_id());
5565 if (!khz)
5566 khz = tsc_khz;
0a3aee0d 5567 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5568}
5569
c8076604
GH		 5570static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5571 void *data)
5572{
5573 struct cpufreq_freqs *freq = data;
5574 struct kvm *kvm;
5575 struct kvm_vcpu *vcpu;
5576 int i, send_ipi = 0;
5577
8cfdc000
ZA		 5578 /*
5579 * We allow guests to temporarily run on slowing clocks,
5580 * provided we notify them after, or to run on accelerating
5581 * clocks, provided we notify them before. Thus time never
5582 * goes backwards.
5583 *
5584 * However, we have a problem. We can't atomically update
5585 * the frequency of a given CPU from this function; it is
5586 * merely a notifier, which can be called from any CPU.
5587 * Changing the TSC frequency at arbitrary points in time
5588 * requires a recomputation of local variables related to
5589 * the TSC for each VCPU. We must flag these local variables
5590 * to be updated and be sure the update takes place with the
5591 * new frequency before any guests proceed.
5592 *
5593 * Unfortunately, the combination of hotplug CPU and frequency
5594 * change creates an intractable locking scenario; the order
5595 * of when these callouts happen is undefined with respect to
5596 * CPU hotplug, and they can race with each other. As such,
5597 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5598 * undefined; you can actually have a CPU frequency change take
5599 * place in between the computation of X and the setting of the
5600 * variable. To protect against this problem, all updates of
5601 * the per_cpu tsc_khz variable are done in an interrupt
5602 * protected IPI, and all callers wishing to update the value
5603 * must wait for a synchronous IPI to complete (which is trivial
5604 * if the caller is on the CPU already). This establishes the
5605 * necessary total order on variable updates.
5606 *
5607 * Note that because a guest time update may take place
5608 * anytime after the setting of the VCPU's request bit, the
5609 * correct TSC value must be set before the request. However,
5610 * to ensure the update actually makes it to any guest which
5611 * starts running in hardware virtualization between the set
5612 * and the acquisition of the spinlock, we must also ping the
5613 * CPU after setting the request bit.
5614 *
5615 */
5616
c8076604
GH		 5617 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5618 return 0;
5619 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5620 return 0;
8cfdc000
ZA		 5621
5622 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5623
2f303b74 5624 spin_lock(&kvm_lock);
c8076604 5625 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5626 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5627 if (vcpu->cpu != freq->cpu)
5628 continue;
c285545f 5629 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5630 if (vcpu->cpu != smp_processor_id())
8cfdc000 5631 send_ipi = 1;
c8076604
GH		 5632 }
5633 }
2f303b74 5634 spin_unlock(&kvm_lock);
c8076604
GH		 5635
5636 if (freq->old < freq->new && send_ipi) {
5637 /*
5638 * We upscale the frequency. Must make the guest
5639 * doesn't see old kvmclock values while running with
5640 * the new frequency, otherwise we risk the guest sees
5641 * time go backwards.
5642 *
5643 * In case we update the frequency for another cpu
5644 * (which might be in guest context) send an interrupt
5645 * to kick the cpu out of guest context. Next time
5646 * guest context is entered kvmclock will be updated,
5647 * so the guest will not see stale values.
5648 */
8cfdc000 5649 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5650 }
5651 return 0;
5652}
5653
5654static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5655 .notifier_call = kvmclock_cpufreq_notifier
5656};
5657
5658static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5659 unsigned long action, void *hcpu)
5660{
5661 unsigned int cpu = (unsigned long)hcpu;
5662
5663 switch (action) {
5664 case CPU_ONLINE:
5665 case CPU_DOWN_FAILED:
5666 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5667 break;
5668 case CPU_DOWN_PREPARE:
5669 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5670 break;
5671 }
5672 return NOTIFY_OK;
5673}
5674
5675static struct notifier_block kvmclock_cpu_notifier_block = {
5676 .notifier_call = kvmclock_cpu_notifier,
5677 .priority = -INT_MAX
c8076604
GH		 5678};
5679
b820cc0c
ZA		 5680static void kvm_timer_init(void)
5681{
5682 int cpu;
5683
c285545f 5684 max_tsc_khz = tsc_khz;
460dd42e
SB		 5685
5686 cpu_notifier_register_begin();
b820cc0c 5687 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5688#ifdef CONFIG_CPU_FREQ
5689 struct cpufreq_policy policy;
5690 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5691 cpu = get_cpu();
5692 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5693 if (policy.cpuinfo.max_freq)
5694 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5695 put_cpu();
c285545f 5696#endif
b820cc0c
ZA		 5697 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5698 CPUFREQ_TRANSITION_NOTIFIER);
5699 }
c285545f 5700 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5701 for_each_online_cpu(cpu)
5702 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5703
5704 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5705 cpu_notifier_register_done();
5706
b820cc0c
ZA		 5707}
5708
ff9d07a0
ZY		 5709static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5710
f5132b01 5711int kvm_is_in_guest(void)
ff9d07a0 5712{
086c9855 5713 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5714}
5715
5716static int kvm_is_user_mode(void)
5717{
5718 int user_mode = 3;
dcf46b94 5719
086c9855
AS		 5720 if (__this_cpu_read(current_vcpu))
5721 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5722
ff9d07a0
ZY		 5723 return user_mode != 0;
5724}
5725
5726static unsigned long kvm_get_guest_ip(void)
5727{
5728 unsigned long ip = 0;
dcf46b94 5729
086c9855
AS		 5730 if (__this_cpu_read(current_vcpu))
5731 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5732
ff9d07a0
ZY		 5733 return ip;
5734}
5735
5736static struct perf_guest_info_callbacks kvm_guest_cbs = {
5737 .is_in_guest = kvm_is_in_guest,
5738 .is_user_mode = kvm_is_user_mode,
5739 .get_guest_ip = kvm_get_guest_ip,
5740};
5741
5742void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5743{
086c9855 5744 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5745}
5746EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5747
5748void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5749{
086c9855 5750 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5751}
5752EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5753
ce88decf
XG		 5754static void kvm_set_mmio_spte_mask(void)
5755{
5756 u64 mask;
5757 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5758
5759 /*
5760 * Set the reserved bits and the present bit of an paging-structure
5761 * entry to generate page fault with PFER.RSV = 1.
5762 */
885032b9 5763 /* Mask the reserved physical address bits. */
d1431483 5764 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5765
5766 /* Bit 62 is always reserved for 32bit host. */
5767 mask |= 0x3ull << 62;
5768
5769 /* Set the present bit. */
ce88decf
XG		 5770 mask |= 1ull;
5771
5772#ifdef CONFIG_X86_64
5773 /*
5774 * If reserved bit is not supported, clear the present bit to disable
5775 * mmio page fault.
5776 */
5777 if (maxphyaddr == 52)
5778 mask &= ~1ull;
5779#endif
5780
5781 kvm_mmu_set_mmio_spte_mask(mask);
5782}
5783
16e8d74d
MT		 5784#ifdef CONFIG_X86_64
5785static void pvclock_gtod_update_fn(struct work_struct *work)
5786{
d828199e
MT		 5787 struct kvm *kvm;
5788
5789 struct kvm_vcpu *vcpu;
5790 int i;
5791
2f303b74 5792 spin_lock(&kvm_lock);
d828199e
MT		 5793 list_for_each_entry(kvm, &vm_list, vm_list)
5794 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5795 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5796 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5797 spin_unlock(&kvm_lock);
16e8d74d
MT		 5798}
5799
5800static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5801
5802/*
5803 * Notification about pvclock gtod data update.
5804 */
5805static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5806 void *priv)
5807{
5808 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5809 struct timekeeper *tk = priv;
5810
5811 update_pvclock_gtod(tk);
5812
5813 /* disable master clock if host does not trust, or does not
5814 * use, TSC clocksource
5815 */
5816 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5817 atomic_read(&kvm_guest_has_master_clock) != 0)
5818 queue_work(system_long_wq, &pvclock_gtod_work);
5819
5820 return 0;
5821}
5822
5823static struct notifier_block pvclock_gtod_notifier = {
5824 .notifier_call = pvclock_gtod_notify,
5825};
5826#endif
5827
f8c16bba 5828int kvm_arch_init(void *opaque)
043405e1 5829{
b820cc0c 5830 int r;
6b61edf7 5831 struct kvm_x86_ops *ops = opaque;
f8c16bba 5832
f8c16bba
ZX		 5833 if (kvm_x86_ops) {
5834 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5835 r = -EEXIST;
5836 goto out;
f8c16bba
ZX		 5837 }
5838
5839 if (!ops->cpu_has_kvm_support()) {
5840 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5841 r = -EOPNOTSUPP;
5842 goto out;
f8c16bba
ZX		 5843 }
5844 if (ops->disabled_by_bios()) {
5845 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5846 r = -EOPNOTSUPP;
5847 goto out;
f8c16bba
ZX		 5848 }
5849
013f6a5d
MT		 5850 r = -ENOMEM;
5851 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5852 if (!shared_msrs) {
5853 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5854 goto out;
5855 }
5856
97db56ce
AK		 5857 r = kvm_mmu_module_init();
5858 if (r)
013f6a5d 5859 goto out_free_percpu;
97db56ce 5860
ce88decf 5861 kvm_set_mmio_spte_mask();
97db56ce 5862
f8c16bba 5863 kvm_x86_ops = ops;
920c8377 5864
7b52345e 5865 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5866 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5867
b820cc0c 5868 kvm_timer_init();
c8076604 5869
ff9d07a0
ZY		 5870 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5871
d366bf7e 5872 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5873 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5874
c5cc421b 5875 kvm_lapic_init();
16e8d74d
MT		 5876#ifdef CONFIG_X86_64
5877 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5878#endif
5879
f8c16bba 5880 return 0;
56c6d28a 5881
013f6a5d
MT		 5882out_free_percpu:
5883 free_percpu(shared_msrs);
56c6d28a 5884out:
56c6d28a 5885 return r;
043405e1 5886}
8776e519 5887
f8c16bba
ZX		 5888void kvm_arch_exit(void)
5889{
ff9d07a0
ZY		 5890 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5891
888d256e
JK		 5892 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5893 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5894 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5895 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5896#ifdef CONFIG_X86_64
5897 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5898#endif
f8c16bba 5899 kvm_x86_ops = NULL;
56c6d28a 5900 kvm_mmu_module_exit();
013f6a5d 5901 free_percpu(shared_msrs);
56c6d28a 5902}
f8c16bba 5903
5cb56059 5904int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5905{
5906 ++vcpu->stat.halt_exits;
35754c98 5907 if (lapic_in_kernel(vcpu)) {
a4535290 5908 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5909 return 1;
5910 } else {
5911 vcpu->run->exit_reason = KVM_EXIT_HLT;
5912 return 0;
5913 }
5914}
5cb56059
JS		 5915EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5916
5917int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5918{
5919 kvm_x86_ops->skip_emulated_instruction(vcpu);
5920 return kvm_vcpu_halt(vcpu);
5921}
8776e519
HB		 5922EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5923
6aef266c
SV		 5924/*
5925 * kvm_pv_kick_cpu_op: Kick a vcpu.
5926 *
5927 * @apicid - apicid of vcpu to be kicked.
5928 */
5929static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5930{
24d2166b 5931 struct kvm_lapic_irq lapic_irq;
6aef266c 5932
24d2166b
R		 5933 lapic_irq.shorthand = 0;
5934 lapic_irq.dest_mode = 0;
5935 lapic_irq.dest_id = apicid;
93bbf0b8 5936 lapic_irq.msi_redir_hint = false;
6aef266c 5937
24d2166b 5938 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5939 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5940}
5941
d62caabb
AS		 5942void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5943{
5944 vcpu->arch.apicv_active = false;
5945 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5946}
5947
8776e519
HB		 5948int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5949{
5950 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5951 int op_64_bit, r = 1;
8776e519 5952
5cb56059
JS		 5953 kvm_x86_ops->skip_emulated_instruction(vcpu);
5954
55cd8e5a
GN		 5955 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5956 return kvm_hv_hypercall(vcpu);
5957
5fdbf976
MT		 5958 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5959 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5960 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5961 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5962 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5963
229456fc 5964 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5965
a449c7aa
NA		 5966 op_64_bit = is_64_bit_mode(vcpu);
5967 if (!op_64_bit) {
8776e519
HB		 5968 nr &= 0xFFFFFFFF;
5969 a0 &= 0xFFFFFFFF;
5970 a1 &= 0xFFFFFFFF;
5971 a2 &= 0xFFFFFFFF;
5972 a3 &= 0xFFFFFFFF;
5973 }
5974
07708c4a
JK		 5975 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5976 ret = -KVM_EPERM;
5977 goto out;
5978 }
5979
8776e519 5980 switch (nr) {
b93463aa
AK		 5981 case KVM_HC_VAPIC_POLL_IRQ:
5982 ret = 0;
5983 break;
6aef266c
SV		 5984 case KVM_HC_KICK_CPU:
5985 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5986 ret = 0;
5987 break;
8776e519
HB		 5988 default:
5989 ret = -KVM_ENOSYS;
5990 break;
5991 }
07708c4a 5992out:
a449c7aa
NA		 5993 if (!op_64_bit)
5994 ret = (u32)ret;
5fdbf976 5995 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5996 ++vcpu->stat.hypercalls;
2f333bcb 5997 return r;
8776e519
HB		 5998}
5999EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6000
b6785def 6001static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6002{
d6aa1000 6003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6004 char instruction[3];
5fdbf976 6005 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6006
8776e519 6007 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6008
9d74191a 6009 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6010}
6011
851ba692 6012static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6013{
782d422b
MG		 6014 return vcpu->run->request_interrupt_window &&
6015 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6016}
6017
851ba692 6018static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6019{
851ba692
AK		 6020 struct kvm_run *kvm_run = vcpu->run;
6021
91586a3b 6022 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6023 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6024 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6025 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6026 kvm_run->ready_for_interrupt_injection =
6027 pic_in_kernel(vcpu->kvm) ||
782d422b 6028 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6029}
6030
95ba8273
GN		 6031static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6032{
6033 int max_irr, tpr;
6034
6035 if (!kvm_x86_ops->update_cr8_intercept)
6036 return;
6037
bce87cce 6038 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6039 return;
6040
d62caabb
AS		 6041 if (vcpu->arch.apicv_active)
6042 return;
6043
8db3baa2
GN		 6044 if (!vcpu->arch.apic->vapic_addr)
6045 max_irr = kvm_lapic_find_highest_irr(vcpu);
6046 else
6047 max_irr = -1;
95ba8273
GN		 6048
6049 if (max_irr != -1)
6050 max_irr >>= 4;
6051
6052 tpr = kvm_lapic_get_cr8(vcpu);
6053
6054 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6055}
6056
b6b8a145 6057static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6058{
b6b8a145
JK		 6059 int r;
6060
95ba8273 6061 /* try to reinject previous events if any */
b59bb7bd 6062 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6063 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6064 vcpu->arch.exception.has_error_code,
6065 vcpu->arch.exception.error_code);
d6e8c854
NA		 6066
6067 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6068 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6069 X86_EFLAGS_RF);
6070
6bdf0662
NA		 6071 if (vcpu->arch.exception.nr == DB_VECTOR &&
6072 (vcpu->arch.dr7 & DR7_GD)) {
6073 vcpu->arch.dr7 &= ~DR7_GD;
6074 kvm_update_dr7(vcpu);
6075 }
6076
b59bb7bd
GN		 6077 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6078 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6079 vcpu->arch.exception.error_code,
6080 vcpu->arch.exception.reinject);
b6b8a145 6081 return 0;
b59bb7bd
GN		 6082 }
6083
95ba8273
GN		 6084 if (vcpu->arch.nmi_injected) {
6085 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6086 return 0;
95ba8273
GN		 6087 }
6088
6089 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6090 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6091 return 0;
6092 }
6093
6094 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6095 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6096 if (r != 0)
6097 return r;
95ba8273
GN		 6098 }
6099
6100 /* try to inject new event if pending */
321c5658
YS		 6101 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6102 --vcpu->arch.nmi_pending;
6103 vcpu->arch.nmi_injected = true;
6104 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6105 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6106 /*
6107 * Because interrupts can be injected asynchronously, we are
6108 * calling check_nested_events again here to avoid a race condition.
6109 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6110 * proposal and current concerns. Perhaps we should be setting
6111 * KVM_REQ_EVENT only on certain events and not unconditionally?
6112 */
6113 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6114 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6115 if (r != 0)
6116 return r;
6117 }
95ba8273 6118 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6119 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6120 false);
6121 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6122 }
6123 }
b6b8a145 6124 return 0;
95ba8273
GN		 6125}
6126
7460fb4a
AK		 6127static void process_nmi(struct kvm_vcpu *vcpu)
6128{
6129 unsigned limit = 2;
6130
6131 /*
6132 * x86 is limited to one NMI running, and one NMI pending after it.
6133 * If an NMI is already in progress, limit further NMIs to just one.
6134 * Otherwise, allow two (and we'll inject the first one immediately).
6135 */
6136 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6137 limit = 1;
6138
6139 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6140 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6141 kvm_make_request(KVM_REQ_EVENT, vcpu);
6142}
6143
660a5d51
PB		 6144#define put_smstate(type, buf, offset, val) \
6145 *(type *)((buf) + (offset) - 0x7e00) = val
6146
6147static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6148{
6149 u32 flags = 0;
6150 flags |= seg->g << 23;
6151 flags |= seg->db << 22;
6152 flags |= seg->l << 21;
6153 flags |= seg->avl << 20;
6154 flags |= seg->present << 15;
6155 flags |= seg->dpl << 13;
6156 flags |= seg->s << 12;
6157 flags |= seg->type << 8;
6158 return flags;
6159}
6160
6161static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6162{
6163 struct kvm_segment seg;
6164 int offset;
6165
6166 kvm_get_segment(vcpu, &seg, n);
6167 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6168
6169 if (n < 3)
6170 offset = 0x7f84 + n * 12;
6171 else
6172 offset = 0x7f2c + (n - 3) * 12;
6173
6174 put_smstate(u32, buf, offset + 8, seg.base);
6175 put_smstate(u32, buf, offset + 4, seg.limit);
6176 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6177}
6178
efbb288a 6179#ifdef CONFIG_X86_64
660a5d51
PB		 6180static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6181{
6182 struct kvm_segment seg;
6183 int offset;
6184 u16 flags;
6185
6186 kvm_get_segment(vcpu, &seg, n);
6187 offset = 0x7e00 + n * 16;
6188
6189 flags = process_smi_get_segment_flags(&seg) >> 8;
6190 put_smstate(u16, buf, offset, seg.selector);
6191 put_smstate(u16, buf, offset + 2, flags);
6192 put_smstate(u32, buf, offset + 4, seg.limit);
6193 put_smstate(u64, buf, offset + 8, seg.base);
6194}
efbb288a 6195#endif
660a5d51
PB		 6196
6197static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6198{
6199 struct desc_ptr dt;
6200 struct kvm_segment seg;
6201 unsigned long val;
6202 int i;
6203
6204 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6205 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6206 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6207 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6208
6209 for (i = 0; i < 8; i++)
6210 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6211
6212 kvm_get_dr(vcpu, 6, &val);
6213 put_smstate(u32, buf, 0x7fcc, (u32)val);
6214 kvm_get_dr(vcpu, 7, &val);
6215 put_smstate(u32, buf, 0x7fc8, (u32)val);
6216
6217 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6218 put_smstate(u32, buf, 0x7fc4, seg.selector);
6219 put_smstate(u32, buf, 0x7f64, seg.base);
6220 put_smstate(u32, buf, 0x7f60, seg.limit);
6221 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6222
6223 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6224 put_smstate(u32, buf, 0x7fc0, seg.selector);
6225 put_smstate(u32, buf, 0x7f80, seg.base);
6226 put_smstate(u32, buf, 0x7f7c, seg.limit);
6227 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6228
6229 kvm_x86_ops->get_gdt(vcpu, &dt);
6230 put_smstate(u32, buf, 0x7f74, dt.address);
6231 put_smstate(u32, buf, 0x7f70, dt.size);
6232
6233 kvm_x86_ops->get_idt(vcpu, &dt);
6234 put_smstate(u32, buf, 0x7f58, dt.address);
6235 put_smstate(u32, buf, 0x7f54, dt.size);
6236
6237 for (i = 0; i < 6; i++)
6238 process_smi_save_seg_32(vcpu, buf, i);
6239
6240 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6241
6242 /* revision id */
6243 put_smstate(u32, buf, 0x7efc, 0x00020000);
6244 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6245}
6246
6247static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6248{
6249#ifdef CONFIG_X86_64
6250 struct desc_ptr dt;
6251 struct kvm_segment seg;
6252 unsigned long val;
6253 int i;
6254
6255 for (i = 0; i < 16; i++)
6256 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6257
6258 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6259 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6260
6261 kvm_get_dr(vcpu, 6, &val);
6262 put_smstate(u64, buf, 0x7f68, val);
6263 kvm_get_dr(vcpu, 7, &val);
6264 put_smstate(u64, buf, 0x7f60, val);
6265
6266 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6267 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6268 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6269
6270 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6271
6272 /* revision id */
6273 put_smstate(u32, buf, 0x7efc, 0x00020064);
6274
6275 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6276
6277 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6278 put_smstate(u16, buf, 0x7e90, seg.selector);
6279 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6280 put_smstate(u32, buf, 0x7e94, seg.limit);
6281 put_smstate(u64, buf, 0x7e98, seg.base);
6282
6283 kvm_x86_ops->get_idt(vcpu, &dt);
6284 put_smstate(u32, buf, 0x7e84, dt.size);
6285 put_smstate(u64, buf, 0x7e88, dt.address);
6286
6287 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6288 put_smstate(u16, buf, 0x7e70, seg.selector);
6289 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6290 put_smstate(u32, buf, 0x7e74, seg.limit);
6291 put_smstate(u64, buf, 0x7e78, seg.base);
6292
6293 kvm_x86_ops->get_gdt(vcpu, &dt);
6294 put_smstate(u32, buf, 0x7e64, dt.size);
6295 put_smstate(u64, buf, 0x7e68, dt.address);
6296
6297 for (i = 0; i < 6; i++)
6298 process_smi_save_seg_64(vcpu, buf, i);
6299#else
6300 WARN_ON_ONCE(1);
6301#endif
6302}
6303
64d60670
PB		 6304static void process_smi(struct kvm_vcpu *vcpu)
6305{
660a5d51 6306 struct kvm_segment cs, ds;
18c3626e 6307 struct desc_ptr dt;
660a5d51
PB		 6308 char buf[512];
6309 u32 cr0;
6310
64d60670
PB		 6311 if (is_smm(vcpu)) {
6312 vcpu->arch.smi_pending = true;
6313 return;
6314 }
6315
660a5d51
PB		 6316 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6317 vcpu->arch.hflags |= HF_SMM_MASK;
6318 memset(buf, 0, 512);
6319 if (guest_cpuid_has_longmode(vcpu))
6320 process_smi_save_state_64(vcpu, buf);
6321 else
6322 process_smi_save_state_32(vcpu, buf);
6323
54bf36aa 6324 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6325
6326 if (kvm_x86_ops->get_nmi_mask(vcpu))
6327 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6328 else
6329 kvm_x86_ops->set_nmi_mask(vcpu, true);
6330
6331 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6332 kvm_rip_write(vcpu, 0x8000);
6333
6334 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6335 kvm_x86_ops->set_cr0(vcpu, cr0);
6336 vcpu->arch.cr0 = cr0;
6337
6338 kvm_x86_ops->set_cr4(vcpu, 0);
6339
18c3626e
PB		 6340 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6341 dt.address = dt.size = 0;
6342 kvm_x86_ops->set_idt(vcpu, &dt);
6343
660a5d51
PB		 6344 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6345
6346 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6347 cs.base = vcpu->arch.smbase;
6348
6349 ds.selector = 0;
6350 ds.base = 0;
6351
6352 cs.limit = ds.limit = 0xffffffff;
6353 cs.type = ds.type = 0x3;
6354 cs.dpl = ds.dpl = 0;
6355 cs.db = ds.db = 0;
6356 cs.s = ds.s = 1;
6357 cs.l = ds.l = 0;
6358 cs.g = ds.g = 1;
6359 cs.avl = ds.avl = 0;
6360 cs.present = ds.present = 1;
6361 cs.unusable = ds.unusable = 0;
6362 cs.padding = ds.padding = 0;
6363
6364 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6369 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6370
6371 if (guest_cpuid_has_longmode(vcpu))
6372 kvm_x86_ops->set_efer(vcpu, 0);
6373
6374 kvm_update_cpuid(vcpu);
6375 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6376}
6377
2860c4b1
PB		 6378void kvm_make_scan_ioapic_request(struct kvm *kvm)
6379{
6380 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6381}
6382
3d81bc7e 6383static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6384{
5c919412
AS		 6385 u64 eoi_exit_bitmap[4];
6386
3d81bc7e
YZ		 6387 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6388 return;
c7c9c56c 6389
6308630b 6390 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6391
b053b2ae 6392 if (irqchip_split(vcpu->kvm))
6308630b 6393 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6394 else {
d62caabb
AS		 6395 if (vcpu->arch.apicv_active)
6396 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6397 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6398 }
5c919412
AS		 6399 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6400 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6401 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6402}
6403
a70656b6
RK		 6404static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6405{
6406 ++vcpu->stat.tlb_flush;
6407 kvm_x86_ops->tlb_flush(vcpu);
6408}
6409
4256f43f
TC		 6410void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6411{
c24ae0dc
TC		 6412 struct page *page = NULL;
6413
35754c98 6414 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6415 return;
6416
4256f43f
TC		 6417 if (!kvm_x86_ops->set_apic_access_page_addr)
6418 return;
6419
c24ae0dc 6420 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6421 if (is_error_page(page))
6422 return;
c24ae0dc
TC		 6423 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6424
6425 /*
6426 * Do not pin apic access page in memory, the MMU notifier
6427 * will call us again if it is migrated or swapped out.
6428 */
6429 put_page(page);
4256f43f
TC		 6430}
6431EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6432
fe71557a
TC		 6433void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6434 unsigned long address)
6435{
c24ae0dc
TC		 6436 /*
6437 * The physical address of apic access page is stored in the VMCS.
6438 * Update it when it becomes invalid.
6439 */
6440 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6441 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6442}
6443
9357d939 6444/*
362c698f 6445 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6446 * exiting to the userspace. Otherwise, the value will be returned to the
6447 * userspace.
6448 */
851ba692 6449static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6450{
6451 int r;
62a193ed
MG		 6452 bool req_int_win =
6453 dm_request_for_irq_injection(vcpu) &&
6454 kvm_cpu_accept_dm_intr(vcpu);
6455
730dca42 6456 bool req_immediate_exit = false;
b6c7a5dc 6457
3e007509 6458 if (vcpu->requests) {
a8eeb04a 6459 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6460 kvm_mmu_unload(vcpu);
a8eeb04a 6461 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6462 __kvm_migrate_timers(vcpu);
d828199e
MT		 6463 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6464 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6465 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6466 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6467 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6468 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6469 if (unlikely(r))
6470 goto out;
6471 }
a8eeb04a 6472 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6473 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6474 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6475 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6476 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6477 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6478 r = 0;
6479 goto out;
6480 }
a8eeb04a 6481 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6482 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6483 r = 0;
6484 goto out;
6485 }
a8eeb04a 6486 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6487 vcpu->fpu_active = 0;
6488 kvm_x86_ops->fpu_deactivate(vcpu);
6489 }
af585b92
GN		 6490 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6491 /* Page is swapped out. Do synthetic halt */
6492 vcpu->arch.apf.halted = true;
6493 r = 1;
6494 goto out;
6495 }
c9aaa895
GC		 6496 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6497 record_steal_time(vcpu);
64d60670
PB		 6498 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6499 process_smi(vcpu);
7460fb4a
AK		 6500 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6501 process_nmi(vcpu);
f5132b01 6502 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6503 kvm_pmu_handle_event(vcpu);
f5132b01 6504 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6505 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6506 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6507 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6508 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6509 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6510 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6511 vcpu->run->eoi.vector =
6512 vcpu->arch.pending_ioapic_eoi;
6513 r = 0;
6514 goto out;
6515 }
6516 }
3d81bc7e
YZ		 6517 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6518 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6519 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6520 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6521 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6522 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6523 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6524 r = 0;
6525 goto out;
6526 }
e516cebb
AS		 6527 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6528 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6529 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6530 r = 0;
6531 goto out;
6532 }
db397571
AS		 6533 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6534 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6535 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6536 r = 0;
6537 goto out;
6538 }
f3b138c5
AS		 6539
6540 /*
6541 * KVM_REQ_HV_STIMER has to be processed after
6542 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6543 * depend on the guest clock being up-to-date
6544 */
1f4b34f8
AS		 6545 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6546 kvm_hv_process_stimers(vcpu);
2f52d58c 6547 }
b93463aa 6548
bf9f6ac8
FW		 6549 /*
6550 * KVM_REQ_EVENT is not set when posted interrupts are set by
6551 * VT-d hardware, so we have to update RVI unconditionally.
6552 */
6553 if (kvm_lapic_enabled(vcpu)) {
6554 /*
6555 * Update architecture specific hints for APIC
6556 * virtual interrupt delivery.
6557 */
d62caabb 6558 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6559 kvm_x86_ops->hwapic_irr_update(vcpu,
6560 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6561 }
b93463aa 6562
b463a6f7 6563 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6564 kvm_apic_accept_events(vcpu);
6565 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6566 r = 1;
6567 goto out;
6568 }
6569
b6b8a145
JK		 6570 if (inject_pending_event(vcpu, req_int_win) != 0)
6571 req_immediate_exit = true;
b463a6f7 6572 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6573 else {
6574 if (vcpu->arch.nmi_pending)
6575 kvm_x86_ops->enable_nmi_window(vcpu);
6576 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6577 kvm_x86_ops->enable_irq_window(vcpu);
6578 }
b463a6f7
AK		 6579
6580 if (kvm_lapic_enabled(vcpu)) {
6581 update_cr8_intercept(vcpu);
6582 kvm_lapic_sync_to_vapic(vcpu);
6583 }
6584 }
6585
d8368af8
AK		 6586 r = kvm_mmu_reload(vcpu);
6587 if (unlikely(r)) {
d905c069 6588 goto cancel_injection;
d8368af8
AK		 6589 }
6590
b6c7a5dc
HB		 6591 preempt_disable();
6592
6593 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6594 if (vcpu->fpu_active)
6595 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6596 vcpu->mode = IN_GUEST_MODE;
6597
01b71917
MT		 6598 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6599
0f127d12
LT		 6600 /*
6601 * We should set ->mode before check ->requests,
6602 * Please see the comment in kvm_make_all_cpus_request.
6603 * This also orders the write to mode from any reads
6604 * to the page tables done while the VCPU is running.
6605 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6606 */
01b71917 6607 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6608
d94e1dc9 6609 local_irq_disable();
32f88400 6610
6b7e2d09 6611 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6612 || need_resched() || signal_pending(current)) {
6b7e2d09 6613 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6614 smp_wmb();
6c142801
AK		 6615 local_irq_enable();
6616 preempt_enable();
01b71917 6617 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6618 r = 1;
d905c069 6619 goto cancel_injection;
6c142801
AK		 6620 }
6621
fc5b7f3b
DM		 6622 kvm_load_guest_xcr0(vcpu);
6623
d6185f20
NHE		 6624 if (req_immediate_exit)
6625 smp_send_reschedule(vcpu->cpu);
6626
8b89fe1f
PB		 6627 trace_kvm_entry(vcpu->vcpu_id);
6628 wait_lapic_expire(vcpu);
ccf73aaf 6629 __kvm_guest_enter();
b6c7a5dc 6630
42dbaa5a 6631 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6632 set_debugreg(0, 7);
6633 set_debugreg(vcpu->arch.eff_db[0], 0);
6634 set_debugreg(vcpu->arch.eff_db[1], 1);
6635 set_debugreg(vcpu->arch.eff_db[2], 2);
6636 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6637 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6638 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6639 }
b6c7a5dc 6640
851ba692 6641 kvm_x86_ops->run(vcpu);
b6c7a5dc 6642
c77fb5fe
PB		 6643 /*
6644 * Do this here before restoring debug registers on the host. And
6645 * since we do this before handling the vmexit, a DR access vmexit
6646 * can (a) read the correct value of the debug registers, (b) set
6647 * KVM_DEBUGREG_WONT_EXIT again.
6648 */
6649 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6650 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6651 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6652 kvm_update_dr0123(vcpu);
6653 kvm_update_dr6(vcpu);
6654 kvm_update_dr7(vcpu);
6655 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6656 }
6657
24f1e32c
FW		 6658 /*
6659 * If the guest has used debug registers, at least dr7
6660 * will be disabled while returning to the host.
6661 * If we don't have active breakpoints in the host, we don't
6662 * care about the messed up debug address registers. But if
6663 * we have some of them active, restore the old state.
6664 */
59d8eb53 6665 if (hw_breakpoint_active())
24f1e32c 6666 hw_breakpoint_restore();
42dbaa5a 6667
4ba76538 6668 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6669
6b7e2d09 6670 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6671 smp_wmb();
a547c6db 6672
fc5b7f3b
DM		 6673 kvm_put_guest_xcr0(vcpu);
6674
a547c6db
YZ		 6675 /* Interrupt is enabled by handle_external_intr() */
6676 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6677
6678 ++vcpu->stat.exits;
6679
6680 /*
6681 * We must have an instruction between local_irq_enable() and
6682 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6683 * the interrupt shadow. The stat.exits increment will do nicely.
6684 * But we need to prevent reordering, hence this barrier():
6685 */
6686 barrier();
6687
6688 kvm_guest_exit();
6689
6690 preempt_enable();
6691
f656ce01 6692 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6693
b6c7a5dc
HB		 6694 /*
6695 * Profile KVM exit RIPs:
6696 */
6697 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6698 unsigned long rip = kvm_rip_read(vcpu);
6699 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6700 }
6701
cc578287
ZA		 6702 if (unlikely(vcpu->arch.tsc_always_catchup))
6703 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6704
5cfb1d5a
MT		 6705 if (vcpu->arch.apic_attention)
6706 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6707
851ba692 6708 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6709 return r;
6710
6711cancel_injection:
6712 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6713 if (unlikely(vcpu->arch.apic_attention))
6714 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6715out:
6716 return r;
6717}
b6c7a5dc 6718
362c698f
PB		 6719static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6720{
bf9f6ac8
FW		 6721 if (!kvm_arch_vcpu_runnable(vcpu) &&
6722 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6723 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6724 kvm_vcpu_block(vcpu);
6725 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6726
6727 if (kvm_x86_ops->post_block)
6728 kvm_x86_ops->post_block(vcpu);
6729
9c8fd1ba
PB		 6730 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6731 return 1;
6732 }
362c698f
PB		 6733
6734 kvm_apic_accept_events(vcpu);
6735 switch(vcpu->arch.mp_state) {
6736 case KVM_MP_STATE_HALTED:
6737 vcpu->arch.pv.pv_unhalted = false;
6738 vcpu->arch.mp_state =
6739 KVM_MP_STATE_RUNNABLE;
6740 case KVM_MP_STATE_RUNNABLE:
6741 vcpu->arch.apf.halted = false;
6742 break;
6743 case KVM_MP_STATE_INIT_RECEIVED:
6744 break;
6745 default:
6746 return -EINTR;
6747 break;
6748 }
6749 return 1;
6750}
09cec754 6751
5d9bc648
PB		 6752static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6753{
6754 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6755 !vcpu->arch.apf.halted);
6756}
6757
362c698f 6758static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6759{
6760 int r;
f656ce01 6761 struct kvm *kvm = vcpu->kvm;
d7690175 6762
f656ce01 6763 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6764
362c698f 6765 for (;;) {
58f800d5 6766 if (kvm_vcpu_running(vcpu)) {
851ba692 6767 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6768 } else {
362c698f 6769 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6770 }
6771
09cec754
GN		 6772 if (r <= 0)
6773 break;
6774
6775 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6776 if (kvm_cpu_has_pending_timer(vcpu))
6777 kvm_inject_pending_timer_irqs(vcpu);
6778
782d422b
MG		 6779 if (dm_request_for_irq_injection(vcpu) &&
6780 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6781 r = 0;
6782 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6783 ++vcpu->stat.request_irq_exits;
362c698f 6784 break;
09cec754 6785 }
af585b92
GN		 6786
6787 kvm_check_async_pf_completion(vcpu);
6788
09cec754
GN		 6789 if (signal_pending(current)) {
6790 r = -EINTR;
851ba692 6791 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6792 ++vcpu->stat.signal_exits;
362c698f 6793 break;
09cec754
GN		 6794 }
6795 if (need_resched()) {
f656ce01 6796 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6797 cond_resched();
f656ce01 6798 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6799 }
b6c7a5dc
HB		 6800 }
6801
f656ce01 6802 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6803
6804 return r;
6805}
6806
716d51ab
GN		 6807static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6808{
6809 int r;
6810 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6811 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6812 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6813 if (r != EMULATE_DONE)
6814 return 0;
6815 return 1;
6816}
6817
6818static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6819{
6820 BUG_ON(!vcpu->arch.pio.count);
6821
6822 return complete_emulated_io(vcpu);
6823}
6824
f78146b0
AK		 6825/*
6826 * Implements the following, as a state machine:
6827 *
6828 * read:
6829 * for each fragment
87da7e66
XG		 6830 * for each mmio piece in the fragment
6831 * write gpa, len
6832 * exit
6833 * copy data
f78146b0
AK		 6834 * execute insn
6835 *
6836 * write:
6837 * for each fragment
87da7e66
XG		 6838 * for each mmio piece in the fragment
6839 * write gpa, len
6840 * copy data
6841 * exit
f78146b0 6842 */
716d51ab 6843static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6844{
6845 struct kvm_run *run = vcpu->run;
f78146b0 6846 struct kvm_mmio_fragment *frag;
87da7e66 6847 unsigned len;
5287f194 6848
716d51ab 6849 BUG_ON(!vcpu->mmio_needed);
5287f194 6850
716d51ab 6851 /* Complete previous fragment */
87da7e66
XG		 6852 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6853 len = min(8u, frag->len);
716d51ab 6854 if (!vcpu->mmio_is_write)
87da7e66
XG		 6855 memcpy(frag->data, run->mmio.data, len);
6856
6857 if (frag->len <= 8) {
6858 /* Switch to the next fragment. */
6859 frag++;
6860 vcpu->mmio_cur_fragment++;
6861 } else {
6862 /* Go forward to the next mmio piece. */
6863 frag->data += len;
6864 frag->gpa += len;
6865 frag->len -= len;
6866 }
6867
a08d3b3b 6868 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6869 vcpu->mmio_needed = 0;
0912c977
PB		 6870
6871 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6872 if (vcpu->mmio_is_write)
716d51ab
GN		 6873 return 1;
6874 vcpu->mmio_read_completed = 1;
6875 return complete_emulated_io(vcpu);
6876 }
87da7e66 6877
716d51ab
GN		 6878 run->exit_reason = KVM_EXIT_MMIO;
6879 run->mmio.phys_addr = frag->gpa;
6880 if (vcpu->mmio_is_write)
87da7e66
XG		 6881 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6882 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6883 run->mmio.is_write = vcpu->mmio_is_write;
6884 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6885 return 0;
5287f194
AK		 6886}
6887
716d51ab 6888
b6c7a5dc
HB		 6889int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6890{
c5bedc68 6891 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6892 int r;
6893 sigset_t sigsaved;
6894
c4d72e2d 6895 fpu__activate_curr(fpu);
e5c30142 6896
ac9f6dc0
AK		 6897 if (vcpu->sigset_active)
6898 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6899
a4535290 6900 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6901 kvm_vcpu_block(vcpu);
66450a21 6902 kvm_apic_accept_events(vcpu);
d7690175 6903 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6904 r = -EAGAIN;
6905 goto out;
b6c7a5dc
HB		 6906 }
6907
b6c7a5dc 6908 /* re-sync apic's tpr */
35754c98 6909 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6910 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6911 r = -EINVAL;
6912 goto out;
6913 }
6914 }
b6c7a5dc 6915
716d51ab
GN		 6916 if (unlikely(vcpu->arch.complete_userspace_io)) {
6917 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6918 vcpu->arch.complete_userspace_io = NULL;
6919 r = cui(vcpu);
6920 if (r <= 0)
6921 goto out;
6922 } else
6923 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6924
362c698f 6925 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6926
6927out:
f1d86e46 6928 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6929 if (vcpu->sigset_active)
6930 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6931
b6c7a5dc
HB		 6932 return r;
6933}
6934
6935int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6936{
7ae441ea
GN		 6937 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6938 /*
6939 * We are here if userspace calls get_regs() in the middle of
6940 * instruction emulation. Registers state needs to be copied
4a969980 6941 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6942 * that usually, but some bad designed PV devices (vmware
6943 * backdoor interface) need this to work
6944 */
dd856efa 6945 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6946 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6947 }
5fdbf976
MT		 6948 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6949 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6950 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6951 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6952 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6953 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6954 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6955 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6956#ifdef CONFIG_X86_64
5fdbf976
MT		 6957 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6958 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6959 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6960 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6961 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6962 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6963 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6964 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6965#endif
6966
5fdbf976 6967 regs->rip = kvm_rip_read(vcpu);
91586a3b 6968 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6969
b6c7a5dc
HB		 6970 return 0;
6971}
6972
6973int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6974{
7ae441ea
GN		 6975 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6976 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6977
5fdbf976
MT		 6978 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6979 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6980 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6981 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6982 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6983 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6984 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6985 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6986#ifdef CONFIG_X86_64
5fdbf976
MT		 6987 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6988 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6989 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6990 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6991 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6992 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6993 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6994 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6995#endif
6996
5fdbf976 6997 kvm_rip_write(vcpu, regs->rip);
91586a3b 6998 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6999
b4f14abd
JK		 7000 vcpu->arch.exception.pending = false;
7001
3842d135
AK		 7002 kvm_make_request(KVM_REQ_EVENT, vcpu);
7003
b6c7a5dc
HB		 7004 return 0;
7005}
7006
b6c7a5dc
HB		 7007void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7008{
7009 struct kvm_segment cs;
7010
3e6e0aab 7011 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7012 *db = cs.db;
7013 *l = cs.l;
7014}
7015EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7016
7017int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7018 struct kvm_sregs *sregs)
7019{
89a27f4d 7020 struct desc_ptr dt;
b6c7a5dc 7021
3e6e0aab
GT		 7022 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7023 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7024 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7025 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7026 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7027 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7028
3e6e0aab
GT		 7029 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7030 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7031
7032 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7033 sregs->idt.limit = dt.size;
7034 sregs->idt.base = dt.address;
b6c7a5dc 7035 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7036 sregs->gdt.limit = dt.size;
7037 sregs->gdt.base = dt.address;
b6c7a5dc 7038
4d4ec087 7039 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7040 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7041 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7042 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7043 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7044 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7045 sregs->apic_base = kvm_get_apic_base(vcpu);
7046
923c61bb 7047 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7048
36752c9b 7049 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7050 set_bit(vcpu->arch.interrupt.nr,
7051 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7052
b6c7a5dc
HB		 7053 return 0;
7054}
7055
62d9f0db
MT		 7056int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7057 struct kvm_mp_state *mp_state)
7058{
66450a21 7059 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7060 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7061 vcpu->arch.pv.pv_unhalted)
7062 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7063 else
7064 mp_state->mp_state = vcpu->arch.mp_state;
7065
62d9f0db
MT		 7066 return 0;
7067}
7068
7069int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7070 struct kvm_mp_state *mp_state)
7071{
bce87cce 7072 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7073 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7074 return -EINVAL;
7075
7076 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7077 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7078 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7079 } else
7080 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7081 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7082 return 0;
7083}
7084
7f3d35fd
KW		 7085int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7086 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7087{
9d74191a 7088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7089 int ret;
e01c2426 7090
8ec4722d 7091 init_emulate_ctxt(vcpu);
c697518a 7092
7f3d35fd 7093 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7094 has_error_code, error_code);
c697518a 7095
c697518a 7096 if (ret)
19d04437 7097 return EMULATE_FAIL;
37817f29 7098
9d74191a
TY		 7099 kvm_rip_write(vcpu, ctxt->eip);
7100 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7101 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7102 return EMULATE_DONE;
37817f29
IE		 7103}
7104EXPORT_SYMBOL_GPL(kvm_task_switch);
7105
b6c7a5dc
HB		 7106int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7107 struct kvm_sregs *sregs)
7108{
58cb628d 7109 struct msr_data apic_base_msr;
b6c7a5dc 7110 int mmu_reset_needed = 0;
63f42e02 7111 int pending_vec, max_bits, idx;
89a27f4d 7112 struct desc_ptr dt;
b6c7a5dc 7113
6d1068b3
PM		 7114 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7115 return -EINVAL;
7116
89a27f4d
GN		 7117 dt.size = sregs->idt.limit;
7118 dt.address = sregs->idt.base;
b6c7a5dc 7119 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7120 dt.size = sregs->gdt.limit;
7121 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7122 kvm_x86_ops->set_gdt(vcpu, &dt);
7123
ad312c7c 7124 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7125 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7126 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7127 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7128
2d3ad1f4 7129 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7130
f6801dff 7131 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7132 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7133 apic_base_msr.data = sregs->apic_base;
7134 apic_base_msr.host_initiated = true;
7135 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7136
4d4ec087 7137 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7138 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7139 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7140
fc78f519 7141 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7142 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7143 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7144 kvm_update_cpuid(vcpu);
63f42e02
XG		 7145
7146 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7147 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7148 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7149 mmu_reset_needed = 1;
7150 }
63f42e02 7151 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7152
7153 if (mmu_reset_needed)
7154 kvm_mmu_reset_context(vcpu);
7155
a50abc3b 7156 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7157 pending_vec = find_first_bit(
7158 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7159 if (pending_vec < max_bits) {
66fd3f7f 7160 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7161 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7162 }
7163
3e6e0aab
GT		 7164 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7165 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7166 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7167 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7168 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7169 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7170
3e6e0aab
GT		 7171 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7172 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7173
5f0269f5
ME		 7174 update_cr8_intercept(vcpu);
7175
9c3e4aab 7176 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7177 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7178 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7179 !is_protmode(vcpu))
9c3e4aab
MT		 7180 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7181
3842d135
AK		 7182 kvm_make_request(KVM_REQ_EVENT, vcpu);
7183
b6c7a5dc
HB		 7184 return 0;
7185}
7186
d0bfb940
JK		 7187int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7188 struct kvm_guest_debug *dbg)
b6c7a5dc 7189{
355be0b9 7190 unsigned long rflags;
ae675ef0 7191 int i, r;
b6c7a5dc 7192
4f926bf2
JK		 7193 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7194 r = -EBUSY;
7195 if (vcpu->arch.exception.pending)
2122ff5e 7196 goto out;
4f926bf2
JK		 7197 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7198 kvm_queue_exception(vcpu, DB_VECTOR);
7199 else
7200 kvm_queue_exception(vcpu, BP_VECTOR);
7201 }
7202
91586a3b
JK		 7203 /*
7204 * Read rflags as long as potentially injected trace flags are still
7205 * filtered out.
7206 */
7207 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7208
7209 vcpu->guest_debug = dbg->control;
7210 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7211 vcpu->guest_debug = 0;
7212
7213 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7214 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7215 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7216 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7217 } else {
7218 for (i = 0; i < KVM_NR_DB_REGS; i++)
7219 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7220 }
c8639010 7221 kvm_update_dr7(vcpu);
ae675ef0 7222
f92653ee
JK		 7223 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7224 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7225 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7226
91586a3b
JK		 7227 /*
7228 * Trigger an rflags update that will inject or remove the trace
7229 * flags.
7230 */
7231 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7232
a96036b8 7233 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7234
4f926bf2 7235 r = 0;
d0bfb940 7236
2122ff5e 7237out:
b6c7a5dc
HB		 7238
7239 return r;
7240}
7241
8b006791
ZX		 7242/*
7243 * Translate a guest virtual address to a guest physical address.
7244 */
7245int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7246 struct kvm_translation *tr)
7247{
7248 unsigned long vaddr = tr->linear_address;
7249 gpa_t gpa;
f656ce01 7250 int idx;
8b006791 7251
f656ce01 7252 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7253 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7254 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7255 tr->physical_address = gpa;
7256 tr->valid = gpa != UNMAPPED_GVA;
7257 tr->writeable = 1;
7258 tr->usermode = 0;
8b006791
ZX		 7259
7260 return 0;
7261}
7262
d0752060
HB		 7263int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7264{
c47ada30 7265 struct fxregs_state *fxsave =
7366ed77 7266 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7267
d0752060
HB		 7268 memcpy(fpu->fpr, fxsave->st_space, 128);
7269 fpu->fcw = fxsave->cwd;
7270 fpu->fsw = fxsave->swd;
7271 fpu->ftwx = fxsave->twd;
7272 fpu->last_opcode = fxsave->fop;
7273 fpu->last_ip = fxsave->rip;
7274 fpu->last_dp = fxsave->rdp;
7275 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7276
d0752060
HB		 7277 return 0;
7278}
7279
7280int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7281{
c47ada30 7282 struct fxregs_state *fxsave =
7366ed77 7283 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7284
d0752060
HB		 7285 memcpy(fxsave->st_space, fpu->fpr, 128);
7286 fxsave->cwd = fpu->fcw;
7287 fxsave->swd = fpu->fsw;
7288 fxsave->twd = fpu->ftwx;
7289 fxsave->fop = fpu->last_opcode;
7290 fxsave->rip = fpu->last_ip;
7291 fxsave->rdp = fpu->last_dp;
7292 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7293
d0752060
HB		 7294 return 0;
7295}
7296
0ee6a517 7297static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7298{
bf935b0b 7299 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7300 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7301 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7302 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7303
2acf923e
DC		 7304 /*
7305 * Ensure guest xcr0 is valid for loading
7306 */
d91cab78 7307 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7308
ad312c7c 7309 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7310}
d0752060
HB		 7311
7312void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7313{
2608d7a1 7314 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7315 return;
7316
2acf923e
DC		 7317 /*
7318 * Restore all possible states in the guest,
7319 * and assume host would use all available bits.
7320 * Guest xcr0 would be loaded later.
7321 */
d0752060 7322 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7323 __kernel_fpu_begin();
003e2e8b 7324 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7325 trace_kvm_fpu(1);
d0752060 7326}
d0752060
HB		 7327
7328void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7329{
653f52c3
RR		 7330 if (!vcpu->guest_fpu_loaded) {
7331 vcpu->fpu_counter = 0;
d0752060 7332 return;
653f52c3 7333 }
d0752060
HB		 7334
7335 vcpu->guest_fpu_loaded = 0;
4f836347 7336 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7337 __kernel_fpu_end();
f096ed85 7338 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7339 /*
7340 * If using eager FPU mode, or if the guest is a frequent user
7341 * of the FPU, just leave the FPU active for next time.
7342 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7343 * the FPU in bursts will revert to loading it on demand.
7344 */
5a5fbdc0 7345 if (!use_eager_fpu()) {
653f52c3
RR		 7346 if (++vcpu->fpu_counter < 5)
7347 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7348 }
0c04851c 7349 trace_kvm_fpu(0);
d0752060 7350}
e9b11c17
ZX		 7351
7352void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7353{
12f9a48f 7354 kvmclock_reset(vcpu);
7f1ea208 7355
f5f48ee1 7356 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7357 kvm_x86_ops->vcpu_free(vcpu);
7358}
7359
7360struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7361 unsigned int id)
7362{
c447e76b
LL		 7363 struct kvm_vcpu *vcpu;
7364
6755bae8
ZA		 7365 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7366 printk_once(KERN_WARNING
7367 "kvm: SMP vm created on host with unstable TSC; "
7368 "guest TSC will not be reliable\n");
c447e76b
LL		 7369
7370 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7371
c447e76b 7372 return vcpu;
26e5215f 7373}
e9b11c17 7374
26e5215f
AK		 7375int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7376{
7377 int r;
e9b11c17 7378
19efffa2 7379 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7380 r = vcpu_load(vcpu);
7381 if (r)
7382 return r;
d28bc9dd 7383 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7384 kvm_mmu_setup(vcpu);
e9b11c17 7385 vcpu_put(vcpu);
26e5215f 7386 return r;
e9b11c17
ZX		 7387}
7388
31928aa5 7389void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7390{
8fe8ab46 7391 struct msr_data msr;
332967a3 7392 struct kvm *kvm = vcpu->kvm;
42897d86 7393
31928aa5
DD		 7394 if (vcpu_load(vcpu))
7395 return;
8fe8ab46
WA		 7396 msr.data = 0x0;
7397 msr.index = MSR_IA32_TSC;
7398 msr.host_initiated = true;
7399 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7400 vcpu_put(vcpu);
7401
630994b3
MT		 7402 if (!kvmclock_periodic_sync)
7403 return;
7404
332967a3
AJ		 7405 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7406 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7407}
7408
d40ccc62 7409void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7410{
9fc77441 7411 int r;
344d9588
GN		 7412 vcpu->arch.apf.msr_val = 0;
7413
9fc77441
MT		 7414 r = vcpu_load(vcpu);
7415 BUG_ON(r);
e9b11c17
ZX		 7416 kvm_mmu_unload(vcpu);
7417 vcpu_put(vcpu);
7418
7419 kvm_x86_ops->vcpu_free(vcpu);
7420}
7421
d28bc9dd 7422void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7423{
e69fab5d
PB		 7424 vcpu->arch.hflags = 0;
7425
7460fb4a
AK		 7426 atomic_set(&vcpu->arch.nmi_queued, 0);
7427 vcpu->arch.nmi_pending = 0;
448fa4a9 7428 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7429 kvm_clear_interrupt_queue(vcpu);
7430 kvm_clear_exception_queue(vcpu);
448fa4a9 7431
42dbaa5a 7432 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7433 kvm_update_dr0123(vcpu);
6f43ed01 7434 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7435 kvm_update_dr6(vcpu);
42dbaa5a 7436 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7437 kvm_update_dr7(vcpu);
42dbaa5a 7438
1119022c
NA		 7439 vcpu->arch.cr2 = 0;
7440
3842d135 7441 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7442 vcpu->arch.apf.msr_val = 0;
c9aaa895 7443 vcpu->arch.st.msr_val = 0;
3842d135 7444
12f9a48f
GC		 7445 kvmclock_reset(vcpu);
7446
af585b92
GN		 7447 kvm_clear_async_pf_completion_queue(vcpu);
7448 kvm_async_pf_hash_reset(vcpu);
7449 vcpu->arch.apf.halted = false;
3842d135 7450
64d60670 7451 if (!init_event) {
d28bc9dd 7452 kvm_pmu_reset(vcpu);
64d60670
PB		 7453 vcpu->arch.smbase = 0x30000;
7454 }
f5132b01 7455
66f7b72e
JS		 7456 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7457 vcpu->arch.regs_avail = ~0;
7458 vcpu->arch.regs_dirty = ~0;
7459
d28bc9dd 7460 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7461}
7462
2b4a273b 7463void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7464{
7465 struct kvm_segment cs;
7466
7467 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7468 cs.selector = vector << 8;
7469 cs.base = vector << 12;
7470 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7471 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7472}
7473
13a34e06 7474int kvm_arch_hardware_enable(void)
e9b11c17 7475{
ca84d1a2
ZA		 7476 struct kvm *kvm;
7477 struct kvm_vcpu *vcpu;
7478 int i;
0dd6a6ed
ZA		 7479 int ret;
7480 u64 local_tsc;
7481 u64 max_tsc = 0;
7482 bool stable, backwards_tsc = false;
18863bdd
AK		 7483
7484 kvm_shared_msr_cpu_online();
13a34e06 7485 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7486 if (ret != 0)
7487 return ret;
7488
4ea1636b 7489 local_tsc = rdtsc();
0dd6a6ed
ZA		 7490 stable = !check_tsc_unstable();
7491 list_for_each_entry(kvm, &vm_list, vm_list) {
7492 kvm_for_each_vcpu(i, vcpu, kvm) {
7493 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7494 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7495 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7496 backwards_tsc = true;
7497 if (vcpu->arch.last_host_tsc > max_tsc)
7498 max_tsc = vcpu->arch.last_host_tsc;
7499 }
7500 }
7501 }
7502
7503 /*
7504 * Sometimes, even reliable TSCs go backwards. This happens on
7505 * platforms that reset TSC during suspend or hibernate actions, but
7506 * maintain synchronization. We must compensate. Fortunately, we can
7507 * detect that condition here, which happens early in CPU bringup,
7508 * before any KVM threads can be running. Unfortunately, we can't
7509 * bring the TSCs fully up to date with real time, as we aren't yet far
7510 * enough into CPU bringup that we know how much real time has actually
7511 * elapsed; our helper function, get_kernel_ns() will be using boot
7512 * variables that haven't been updated yet.
7513 *
7514 * So we simply find the maximum observed TSC above, then record the
7515 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7516 * the adjustment will be applied. Note that we accumulate
7517 * adjustments, in case multiple suspend cycles happen before some VCPU
7518 * gets a chance to run again. In the event that no KVM threads get a
7519 * chance to run, we will miss the entire elapsed period, as we'll have
7520 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7521 * loose cycle time. This isn't too big a deal, since the loss will be
7522 * uniform across all VCPUs (not to mention the scenario is extremely
7523 * unlikely). It is possible that a second hibernate recovery happens
7524 * much faster than a first, causing the observed TSC here to be
7525 * smaller; this would require additional padding adjustment, which is
7526 * why we set last_host_tsc to the local tsc observed here.
7527 *
7528 * N.B. - this code below runs only on platforms with reliable TSC,
7529 * as that is the only way backwards_tsc is set above. Also note
7530 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7531 * have the same delta_cyc adjustment applied if backwards_tsc
7532 * is detected. Note further, this adjustment is only done once,
7533 * as we reset last_host_tsc on all VCPUs to stop this from being
7534 * called multiple times (one for each physical CPU bringup).
7535 *
4a969980 7536 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7537 * will be compensated by the logic in vcpu_load, which sets the TSC to
7538 * catchup mode. This will catchup all VCPUs to real time, but cannot
7539 * guarantee that they stay in perfect synchronization.
7540 */
7541 if (backwards_tsc) {
7542 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7543 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7544 list_for_each_entry(kvm, &vm_list, vm_list) {
7545 kvm_for_each_vcpu(i, vcpu, kvm) {
7546 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7547 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7548 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7549 }
7550
7551 /*
7552 * We have to disable TSC offset matching.. if you were
7553 * booting a VM while issuing an S4 host suspend....
7554 * you may have some problem. Solving this issue is
7555 * left as an exercise to the reader.
7556 */
7557 kvm->arch.last_tsc_nsec = 0;
7558 kvm->arch.last_tsc_write = 0;
7559 }
7560
7561 }
7562 return 0;
e9b11c17
ZX		 7563}
7564
13a34e06 7565void kvm_arch_hardware_disable(void)
e9b11c17 7566{
13a34e06
RK		 7567 kvm_x86_ops->hardware_disable();
7568 drop_user_return_notifiers();
e9b11c17
ZX		 7569}
7570
7571int kvm_arch_hardware_setup(void)
7572{
9e9c3fe4
NA		 7573 int r;
7574
7575 r = kvm_x86_ops->hardware_setup();
7576 if (r != 0)
7577 return r;
7578
35181e86
HZ		 7579 if (kvm_has_tsc_control) {
7580 /*
7581 * Make sure the user can only configure tsc_khz values that
7582 * fit into a signed integer.
7583 * A min value is not calculated needed because it will always
7584 * be 1 on all machines.
7585 */
7586 u64 max = min(0x7fffffffULL,
7587 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7588 kvm_max_guest_tsc_khz = max;
7589
ad721883 7590 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7591 }
ad721883 7592
9e9c3fe4
NA		 7593 kvm_init_msr_list();
7594 return 0;
e9b11c17
ZX		 7595}
7596
7597void kvm_arch_hardware_unsetup(void)
7598{
7599 kvm_x86_ops->hardware_unsetup();
7600}
7601
7602void kvm_arch_check_processor_compat(void *rtn)
7603{
7604 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7605}
7606
7607bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7608{
7609 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7610}
7611EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7612
7613bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7614{
7615 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7616}
7617
3e515705
AK		 7618bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7619{
35754c98 7620 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7621}
7622
54e9818f 7623struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7624EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7625
e9b11c17
ZX		 7626int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7627{
7628 struct page *page;
7629 struct kvm *kvm;
7630 int r;
7631
7632 BUG_ON(vcpu->kvm == NULL);
7633 kvm = vcpu->kvm;
7634
d62caabb 7635 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7636 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7637 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7638 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7639 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7640 else
a4535290 7641 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7642
7643 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7644 if (!page) {
7645 r = -ENOMEM;
7646 goto fail;
7647 }
ad312c7c 7648 vcpu->arch.pio_data = page_address(page);
e9b11c17 7649
cc578287 7650 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7651
e9b11c17
ZX		 7652 r = kvm_mmu_create(vcpu);
7653 if (r < 0)
7654 goto fail_free_pio_data;
7655
7656 if (irqchip_in_kernel(kvm)) {
7657 r = kvm_create_lapic(vcpu);
7658 if (r < 0)
7659 goto fail_mmu_destroy;
54e9818f
GN		 7660 } else
7661 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7662
890ca9ae
HY		 7663 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7664 GFP_KERNEL);
7665 if (!vcpu->arch.mce_banks) {
7666 r = -ENOMEM;
443c39bc 7667 goto fail_free_lapic;
890ca9ae
HY		 7668 }
7669 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7670
f1797359
WY		 7671 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7672 r = -ENOMEM;
f5f48ee1 7673 goto fail_free_mce_banks;
f1797359 7674 }
f5f48ee1 7675
0ee6a517 7676 fx_init(vcpu);
66f7b72e 7677
ba904635 7678 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7679 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7680
7681 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7682 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7683
5a4f55cd
EK		 7684 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7685
74545705
RK		 7686 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7687
af585b92 7688 kvm_async_pf_hash_reset(vcpu);
f5132b01 7689 kvm_pmu_init(vcpu);
af585b92 7690
1c1a9ce9
SR		 7691 vcpu->arch.pending_external_vector = -1;
7692
5c919412
AS		 7693 kvm_hv_vcpu_init(vcpu);
7694
e9b11c17 7695 return 0;
0ee6a517 7696
f5f48ee1
SY		 7697fail_free_mce_banks:
7698 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7699fail_free_lapic:
7700 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7701fail_mmu_destroy:
7702 kvm_mmu_destroy(vcpu);
7703fail_free_pio_data:
ad312c7c 7704 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7705fail:
7706 return r;
7707}
7708
7709void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7710{
f656ce01
MT		 7711 int idx;
7712
1f4b34f8 7713 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7714 kvm_pmu_destroy(vcpu);
36cb93fd 7715 kfree(vcpu->arch.mce_banks);
e9b11c17 7716 kvm_free_lapic(vcpu);
f656ce01 7717 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7718 kvm_mmu_destroy(vcpu);
f656ce01 7719 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7720 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7721 if (!lapic_in_kernel(vcpu))
54e9818f 7722 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7723}
d19a9cd2 7724
e790d9ef
RK		 7725void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7726{
ae97a3b8 7727 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7728}
7729
e08b9637 7730int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7731{
e08b9637
CO		 7732 if (type)
7733 return -EINVAL;
7734
6ef768fa 7735 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7736 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7737 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7738 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7739 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7740
5550af4d
SY		 7741 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7742 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7743 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7744 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7745 &kvm->arch.irq_sources_bitmap);
5550af4d 7746
038f8c11 7747 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7748 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7749 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7750
7751 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7752
7e44e449 7753 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7754 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7755
0eb05bf2 7756 kvm_page_track_init(kvm);
13d268ca 7757 kvm_mmu_init_vm(kvm);
0eb05bf2 7758
03543133
SS		 7759 if (kvm_x86_ops->vm_init)
7760 return kvm_x86_ops->vm_init(kvm);
7761
d89f5eff 7762 return 0;
d19a9cd2
ZX		 7763}
7764
7765static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7766{
9fc77441
MT		 7767 int r;
7768 r = vcpu_load(vcpu);
7769 BUG_ON(r);
d19a9cd2
ZX		 7770 kvm_mmu_unload(vcpu);
7771 vcpu_put(vcpu);
7772}
7773
7774static void kvm_free_vcpus(struct kvm *kvm)
7775{
7776 unsigned int i;
988a2cae 7777 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7778
7779 /*
7780 * Unpin any mmu pages first.
7781 */
af585b92
GN		 7782 kvm_for_each_vcpu(i, vcpu, kvm) {
7783 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7784 kvm_unload_vcpu_mmu(vcpu);
af585b92 7785 }
988a2cae
GN		 7786 kvm_for_each_vcpu(i, vcpu, kvm)
7787 kvm_arch_vcpu_free(vcpu);
7788
7789 mutex_lock(&kvm->lock);
7790 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7791 kvm->vcpus[i] = NULL;
d19a9cd2 7792
988a2cae
GN		 7793 atomic_set(&kvm->online_vcpus, 0);
7794 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7795}
7796
ad8ba2cd
SY		 7797void kvm_arch_sync_events(struct kvm *kvm)
7798{
332967a3 7799 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7800 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7801 kvm_free_all_assigned_devices(kvm);
aea924f6 7802 kvm_free_pit(kvm);
ad8ba2cd
SY		 7803}
7804
1d8007bd 7805int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7806{
7807 int i, r;
25188b99 7808 unsigned long hva;
f0d648bd
PB		 7809 struct kvm_memslots *slots = kvm_memslots(kvm);
7810 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7811
7812 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7813 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7814 return -EINVAL;
9da0e4d5 7815
f0d648bd
PB		 7816 slot = id_to_memslot(slots, id);
7817 if (size) {
7818 if (WARN_ON(slot->npages))
7819 return -EEXIST;
7820
7821 /*
7822 * MAP_SHARED to prevent internal slot pages from being moved
7823 * by fork()/COW.
7824 */
7825 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7826 MAP_SHARED | MAP_ANONYMOUS, 0);
7827 if (IS_ERR((void *)hva))
7828 return PTR_ERR((void *)hva);
7829 } else {
7830 if (!slot->npages)
7831 return 0;
7832
7833 hva = 0;
7834 }
7835
7836 old = *slot;
9da0e4d5 7837 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7838 struct kvm_userspace_memory_region m;
9da0e4d5 7839
1d8007bd
PB		 7840 m.slot = id | (i << 16);
7841 m.flags = 0;
7842 m.guest_phys_addr = gpa;
f0d648bd 7843 m.userspace_addr = hva;
1d8007bd 7844 m.memory_size = size;
9da0e4d5
PB		 7845 r = __kvm_set_memory_region(kvm, &m);
7846 if (r < 0)
7847 return r;
7848 }
7849
f0d648bd
PB		 7850 if (!size) {
7851 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7852 WARN_ON(r < 0);
7853 }
7854
9da0e4d5
PB		 7855 return 0;
7856}
7857EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7858
1d8007bd 7859int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7860{
7861 int r;
7862
7863 mutex_lock(&kvm->slots_lock);
1d8007bd 7864 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7865 mutex_unlock(&kvm->slots_lock);
7866
7867 return r;
7868}
7869EXPORT_SYMBOL_GPL(x86_set_memory_region);
7870
d19a9cd2
ZX		 7871void kvm_arch_destroy_vm(struct kvm *kvm)
7872{
27469d29
AH		 7873 if (current->mm == kvm->mm) {
7874 /*
7875 * Free memory regions allocated on behalf of userspace,
7876 * unless the the memory map has changed due to process exit
7877 * or fd copying.
7878 */
1d8007bd
PB		 7879 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7880 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7881 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7882 }
03543133
SS		 7883 if (kvm_x86_ops->vm_destroy)
7884 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7885 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7886 kfree(kvm->arch.vpic);
7887 kfree(kvm->arch.vioapic);
d19a9cd2 7888 kvm_free_vcpus(kvm);
1e08ec4a 7889 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7890 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7891}
0de10343 7892
5587027c 7893void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7894 struct kvm_memory_slot *dont)
7895{
7896 int i;
7897
d89cc617
TY		 7898 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7899 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7900 kvfree(free->arch.rmap[i]);
d89cc617 7901 free->arch.rmap[i] = NULL;
77d11309 7902 }
d89cc617
TY		 7903 if (i == 0)
7904 continue;
7905
7906 if (!dont || free->arch.lpage_info[i - 1] !=
7907 dont->arch.lpage_info[i - 1]) {
548ef284 7908 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7909 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7910 }
7911 }
21ebbeda
XG		 7912
7913 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7914}
7915
5587027c
AK		 7916int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7917 unsigned long npages)
db3fe4eb
TY		 7918{
7919 int i;
7920
d89cc617 7921 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7922 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7923 unsigned long ugfn;
7924 int lpages;
d89cc617 7925 int level = i + 1;
db3fe4eb
TY		 7926
7927 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7928 slot->base_gfn, level) + 1;
7929
d89cc617
TY		 7930 slot->arch.rmap[i] =
7931 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7932 if (!slot->arch.rmap[i])
77d11309 7933 goto out_free;
d89cc617
TY		 7934 if (i == 0)
7935 continue;
77d11309 7936
92f94f1e
XG		 7937 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7938 if (!linfo)
db3fe4eb
TY		 7939 goto out_free;
7940
92f94f1e
XG		 7941 slot->arch.lpage_info[i - 1] = linfo;
7942
db3fe4eb 7943 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7944 linfo[0].disallow_lpage = 1;
db3fe4eb 7945 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7946 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7947 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7948 /*
7949 * If the gfn and userspace address are not aligned wrt each
7950 * other, or if explicitly asked to, disable large page
7951 * support for this slot
7952 */
7953 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7954 !kvm_largepages_enabled()) {
7955 unsigned long j;
7956
7957 for (j = 0; j < lpages; ++j)
92f94f1e 7958 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7959 }
7960 }
7961
21ebbeda
XG		 7962 if (kvm_page_track_create_memslot(slot, npages))
7963 goto out_free;
7964
db3fe4eb
TY		 7965 return 0;
7966
7967out_free:
d89cc617 7968 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7969 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7970 slot->arch.rmap[i] = NULL;
7971 if (i == 0)
7972 continue;
7973
548ef284 7974 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7975 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7976 }
7977 return -ENOMEM;
7978}
7979
15f46015 7980void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7981{
e6dff7d1
TY		 7982 /*
7983 * memslots->generation has been incremented.
7984 * mmio generation may have reached its maximum value.
7985 */
54bf36aa 7986 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7987}
7988
f7784b8e
MT		 7989int kvm_arch_prepare_memory_region(struct kvm *kvm,
7990 struct kvm_memory_slot *memslot,
09170a49 7991 const struct kvm_userspace_memory_region *mem,
7b6195a9 7992 enum kvm_mr_change change)
0de10343 7993{
f7784b8e
MT		 7994 return 0;
7995}
7996
88178fd4
KH		 7997static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7998 struct kvm_memory_slot *new)
7999{
8000 /* Still write protect RO slot */
8001 if (new->flags & KVM_MEM_READONLY) {
8002 kvm_mmu_slot_remove_write_access(kvm, new);
8003 return;
8004 }
8005
8006 /*
8007 * Call kvm_x86_ops dirty logging hooks when they are valid.
8008 *
8009 * kvm_x86_ops->slot_disable_log_dirty is called when:
8010 *
8011 * - KVM_MR_CREATE with dirty logging is disabled
8012 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8013 *
8014 * The reason is, in case of PML, we need to set D-bit for any slots
8015 * with dirty logging disabled in order to eliminate unnecessary GPA
8016 * logging in PML buffer (and potential PML buffer full VMEXT). This
8017 * guarantees leaving PML enabled during guest's lifetime won't have
8018 * any additonal overhead from PML when guest is running with dirty
8019 * logging disabled for memory slots.
8020 *
8021 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8022 * to dirty logging mode.
8023 *
8024 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8025 *
8026 * In case of write protect:
8027 *
8028 * Write protect all pages for dirty logging.
8029 *
8030 * All the sptes including the large sptes which point to this
8031 * slot are set to readonly. We can not create any new large
8032 * spte on this slot until the end of the logging.
8033 *
8034 * See the comments in fast_page_fault().
8035 */
8036 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8037 if (kvm_x86_ops->slot_enable_log_dirty)
8038 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8039 else
8040 kvm_mmu_slot_remove_write_access(kvm, new);
8041 } else {
8042 if (kvm_x86_ops->slot_disable_log_dirty)
8043 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8044 }
8045}
8046
f7784b8e 8047void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8048 const struct kvm_userspace_memory_region *mem,
8482644a 8049 const struct kvm_memory_slot *old,
f36f3f28 8050 const struct kvm_memory_slot *new,
8482644a 8051 enum kvm_mr_change change)
f7784b8e 8052{
8482644a 8053 int nr_mmu_pages = 0;
f7784b8e 8054
48c0e4e9
XG		 8055 if (!kvm->arch.n_requested_mmu_pages)
8056 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8057
48c0e4e9 8058 if (nr_mmu_pages)
0de10343 8059 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8060
3ea3b7fa
WL		 8061 /*
8062 * Dirty logging tracks sptes in 4k granularity, meaning that large
8063 * sptes have to be split. If live migration is successful, the guest
8064 * in the source machine will be destroyed and large sptes will be
8065 * created in the destination. However, if the guest continues to run
8066 * in the source machine (for example if live migration fails), small
8067 * sptes will remain around and cause bad performance.
8068 *
8069 * Scan sptes if dirty logging has been stopped, dropping those
8070 * which can be collapsed into a single large-page spte. Later
8071 * page faults will create the large-page sptes.
8072 */
8073 if ((change != KVM_MR_DELETE) &&
8074 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8075 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8076 kvm_mmu_zap_collapsible_sptes(kvm, new);
8077
c972f3b1 8078 /*
88178fd4 8079 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8080 *
88178fd4
KH		 8081 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8082 * been zapped so no dirty logging staff is needed for old slot. For
8083 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8084 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8085 *
8086 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8087 */
88178fd4 8088 if (change != KVM_MR_DELETE)
f36f3f28 8089 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8090}
1d737c8a 8091
2df72e9b 8092void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8093{
6ca18b69 8094 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8095}
8096
2df72e9b
MT		 8097void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8098 struct kvm_memory_slot *slot)
8099{
6ca18b69 8100 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8101}
8102
5d9bc648
PB		 8103static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8104{
8105 if (!list_empty_careful(&vcpu->async_pf.done))
8106 return true;
8107
8108 if (kvm_apic_has_events(vcpu))
8109 return true;
8110
8111 if (vcpu->arch.pv.pv_unhalted)
8112 return true;
8113
8114 if (atomic_read(&vcpu->arch.nmi_queued))
8115 return true;
8116
73917739
PB		 8117 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8118 return true;
8119
5d9bc648
PB		 8120 if (kvm_arch_interrupt_allowed(vcpu) &&
8121 kvm_cpu_has_interrupt(vcpu))
8122 return true;
8123
1f4b34f8
AS		 8124 if (kvm_hv_has_stimer_pending(vcpu))
8125 return true;
8126
5d9bc648
PB		 8127 return false;
8128}
8129
1d737c8a
ZX		 8130int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8131{
b6b8a145
JK		 8132 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8133 kvm_x86_ops->check_nested_events(vcpu, false);
8134
5d9bc648 8135 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8136}
5736199a 8137
b6d33834 8138int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8139{
b6d33834 8140 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8141}
78646121
GN		 8142
8143int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8144{
8145 return kvm_x86_ops->interrupt_allowed(vcpu);
8146}
229456fc 8147
82b32774 8148unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8149{
82b32774
NA		 8150 if (is_64_bit_mode(vcpu))
8151 return kvm_rip_read(vcpu);
8152 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8153 kvm_rip_read(vcpu));
8154}
8155EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8156
82b32774
NA		 8157bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8158{
8159 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8160}
8161EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8162
94fe45da
JK		 8163unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8164{
8165 unsigned long rflags;
8166
8167 rflags = kvm_x86_ops->get_rflags(vcpu);
8168 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8169 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8170 return rflags;
8171}
8172EXPORT_SYMBOL_GPL(kvm_get_rflags);
8173
6addfc42 8174static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8175{
8176 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8177 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8178 rflags |= X86_EFLAGS_TF;
94fe45da 8179 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8180}
8181
8182void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8183{
8184 __kvm_set_rflags(vcpu, rflags);
3842d135 8185 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8186}
8187EXPORT_SYMBOL_GPL(kvm_set_rflags);
8188
56028d08
GN		 8189void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8190{
8191 int r;
8192
fb67e14f 8193 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8194 work->wakeup_all)
56028d08
GN		 8195 return;
8196
8197 r = kvm_mmu_reload(vcpu);
8198 if (unlikely(r))
8199 return;
8200
fb67e14f
XG		 8201 if (!vcpu->arch.mmu.direct_map &&
8202 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8203 return;
8204
56028d08
GN		 8205 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8206}
8207
af585b92
GN		 8208static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8209{
8210 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8211}
8212
8213static inline u32 kvm_async_pf_next_probe(u32 key)
8214{
8215 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8216}
8217
8218static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8219{
8220 u32 key = kvm_async_pf_hash_fn(gfn);
8221
8222 while (vcpu->arch.apf.gfns[key] != ~0)
8223 key = kvm_async_pf_next_probe(key);
8224
8225 vcpu->arch.apf.gfns[key] = gfn;
8226}
8227
8228static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8229{
8230 int i;
8231 u32 key = kvm_async_pf_hash_fn(gfn);
8232
8233 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8234 (vcpu->arch.apf.gfns[key] != gfn &&
8235 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8236 key = kvm_async_pf_next_probe(key);
8237
8238 return key;
8239}
8240
8241bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8242{
8243 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8244}
8245
8246static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8247{
8248 u32 i, j, k;
8249
8250 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8251 while (true) {
8252 vcpu->arch.apf.gfns[i] = ~0;
8253 do {
8254 j = kvm_async_pf_next_probe(j);
8255 if (vcpu->arch.apf.gfns[j] == ~0)
8256 return;
8257 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8258 /*
8259 * k lies cyclically in ]i,j]
8260 * | i.k.j |
8261 * |....j i.k.| or |.k..j i...|
8262 */
8263 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8264 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8265 i = j;
8266 }
8267}
8268
7c90705b
GN		 8269static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8270{
8271
8272 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8273 sizeof(val));
8274}
8275
af585b92
GN		 8276void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8277 struct kvm_async_pf *work)
8278{
6389ee94
AK		 8279 struct x86_exception fault;
8280
7c90705b 8281 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8282 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8283
8284 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8285 (vcpu->arch.apf.send_user_only &&
8286 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8287 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8288 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8289 fault.vector = PF_VECTOR;
8290 fault.error_code_valid = true;
8291 fault.error_code = 0;
8292 fault.nested_page_fault = false;
8293 fault.address = work->arch.token;
8294 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8295 }
af585b92
GN		 8296}
8297
8298void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8299 struct kvm_async_pf *work)
8300{
6389ee94
AK		 8301 struct x86_exception fault;
8302
7c90705b 8303 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8304 if (work->wakeup_all)
7c90705b
GN		 8305 work->arch.token = ~0; /* broadcast wakeup */
8306 else
8307 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8308
8309 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8310 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8311 fault.vector = PF_VECTOR;
8312 fault.error_code_valid = true;
8313 fault.error_code = 0;
8314 fault.nested_page_fault = false;
8315 fault.address = work->arch.token;
8316 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8317 }
e6d53e3b 8318 vcpu->arch.apf.halted = false;
a4fa1635 8319 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8320}
8321
8322bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8323{
8324 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8325 return true;
8326 else
8327 return !kvm_event_needs_reinjection(vcpu) &&
8328 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8329}
8330
5544eb9b
PB		 8331void kvm_arch_start_assignment(struct kvm *kvm)
8332{
8333 atomic_inc(&kvm->arch.assigned_device_count);
8334}
8335EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8336
8337void kvm_arch_end_assignment(struct kvm *kvm)
8338{
8339 atomic_dec(&kvm->arch.assigned_device_count);
8340}
8341EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8342
8343bool kvm_arch_has_assigned_device(struct kvm *kvm)
8344{
8345 return atomic_read(&kvm->arch.assigned_device_count);
8346}
8347EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8348
e0f0bbc5
AW		 8349void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8350{
8351 atomic_inc(&kvm->arch.noncoherent_dma_count);
8352}
8353EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8354
8355void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8356{
8357 atomic_dec(&kvm->arch.noncoherent_dma_count);
8358}
8359EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8360
8361bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8362{
8363 return atomic_read(&kvm->arch.noncoherent_dma_count);
8364}
8365EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8366
14717e20
AW		 8367bool kvm_arch_has_irq_bypass(void)
8368{
8369 return kvm_x86_ops->update_pi_irte != NULL;
8370}
8371
87276880
FW		 8372int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8373 struct irq_bypass_producer *prod)
8374{
8375 struct kvm_kernel_irqfd *irqfd =
8376 container_of(cons, struct kvm_kernel_irqfd, consumer);
8377
14717e20 8378 irqfd->producer = prod;
87276880 8379
14717e20
AW		 8380 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8381 prod->irq, irqfd->gsi, 1);
87276880
FW		 8382}
8383
8384void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8385 struct irq_bypass_producer *prod)
8386{
8387 int ret;
8388 struct kvm_kernel_irqfd *irqfd =
8389 container_of(cons, struct kvm_kernel_irqfd, consumer);
8390
87276880
FW		 8391 WARN_ON(irqfd->producer != prod);
8392 irqfd->producer = NULL;
8393
8394 /*
8395 * When producer of consumer is unregistered, we change back to
8396 * remapped mode, so we can re-use the current implementation
8397 * when the irq is masked/disabed or the consumer side (KVM
8398 * int this case doesn't want to receive the interrupts.
8399 */
8400 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8401 if (ret)
8402 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8403 " fails: %d\n", irqfd->consumer.token, ret);
8404}
8405
8406int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8407 uint32_t guest_irq, bool set)
8408{
8409 if (!kvm_x86_ops->update_pi_irte)
8410 return -EINVAL;
8411
8412 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8413}
8414
52004014
FW		 8415bool kvm_vector_hashing_enabled(void)
8416{
8417 return vector_hashing;
8418}
8419EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8420
229456fc 8421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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