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kvm: use kmalloc() instead of kzalloc() during iodev register/unregister
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 152 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 153 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 154 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 155 { "request_irq", VCPU_STAT(request_irq_exits) },
156 { "irq_exits", VCPU_STAT(irq_exits) },
157 { "host_state_reload", VCPU_STAT(host_state_reload) },
158 { "efer_reload", VCPU_STAT(efer_reload) },
159 { "fpu_reload", VCPU_STAT(fpu_reload) },
160 { "insn_emulation", VCPU_STAT(insn_emulation) },
161 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 162 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 163 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 164 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
165 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
166 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
167 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
168 { "mmu_flooded", VM_STAT(mmu_flooded) },
169 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 170 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 171 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 172 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 173 { "largepages", VM_STAT(lpages) },
417bc304
HB		 174 { NULL }
175};
176
2acf923e
DC		 177u64 __read_mostly host_xcr0;
178
b6785def 179static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 180
af585b92
GN		 181static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
182{
183 int i;
184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
185 vcpu->arch.apf.gfns[i] = ~0;
186}
187
18863bdd
AK		 188static void kvm_on_user_return(struct user_return_notifier *urn)
189{
190 unsigned slot;
18863bdd
AK		 191 struct kvm_shared_msrs *locals
192 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 193 struct kvm_shared_msr_values *values;
18863bdd
AK		 194
195 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 196 values = &locals->values[slot];
197 if (values->host != values->curr) {
198 wrmsrl(shared_msrs_global.msrs[slot], values->host);
199 values->curr = values->host;
18863bdd
AK		 200 }
201 }
202 locals->registered = false;
203 user_return_notifier_unregister(urn);
204}
205
2bf78fa7 206static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 207{
18863bdd 208 u64 value;
013f6a5d
MT		 209 unsigned int cpu = smp_processor_id();
210 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 211
2bf78fa7
SY		 212 /* only read, and nobody should modify it at this time,
213 * so don't need lock */
214 if (slot >= shared_msrs_global.nr) {
215 printk(KERN_ERR "kvm: invalid MSR slot!");
216 return;
217 }
218 rdmsrl_safe(msr, &value);
219 smsr->values[slot].host = value;
220 smsr->values[slot].curr = value;
221}
222
223void kvm_define_shared_msr(unsigned slot, u32 msr)
224{
0123be42 225 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 226 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 227 if (slot >= shared_msrs_global.nr)
228 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 229}
230EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232static void kvm_shared_msr_cpu_online(void)
233{
234 unsigned i;
18863bdd
AK		 235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 237 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 238}
239
8b3c3104 240int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 241{
013f6a5d
MT		 242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 244 int err;
18863bdd 245
2bf78fa7 246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 247 return 0;
2bf78fa7 248 smsr->values[slot].curr = value;
8b3c3104
AH		 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
18863bdd
AK		 253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
8b3c3104 258 return 0;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
13a34e06 262static void drop_user_return_notifiers(void)
3548bab5 263{
013f6a5d
MT		 264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269}
270
6866b83e
CO		 271u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272{
8a5a87d9 273 return vcpu->arch.apic_base;
6866b83e
CO		 274}
275EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
58cb628d
JK		 277int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278{
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
6866b83e
CO		 297}
298EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
2605fc21 300asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 301{
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304}
305EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
3fd28fce
ED		 307#define EXCPT_BENIGN 0
308#define EXCPT_CONTRIBUTORY 1
309#define EXCPT_PF 2
310
311static int exception_class(int vector)
312{
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326}
327
d6e8c854
NA		 328#define EXCPT_FAULT 0
329#define EXCPT_TRAP 1
330#define EXCPT_ABORT 2
331#define EXCPT_INTERRUPT 3
332
333static int exception_type(int vector)
334{
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351}
352
3fd28fce 353static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
3fd28fce
ED		 356{
357 u32 prev_nr;
358 int class1, class2;
359
3842d135
AK		 360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
3fd28fce
ED		 362 if (!vcpu->arch.exception.pending) {
363 queue:
3ffb2468
NA		 364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
3fd28fce
ED		 366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
3f0fd292 370 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
a8eeb04a 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395}
396
298101da
AK		 397void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
ce7ddec4
JR		 403void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404{
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
db8fcefa 409void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 410{
db8fcefa
AP		 411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415}
416EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 417
6389ee94 418void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 419{
420 ++vcpu->stat.pf_guest;
6389ee94
AK		 421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 423}
27d6c865 424EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 425
ef54bcfe 426static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 427{
6389ee94
AK		 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 430 else
6389ee94 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 432
433 return fault->nested_page_fault;
d4f8cf66
JR		 434}
435
3419ffc8
SY		 436void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437{
7460fb4a
AK		 438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 440}
441EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
298101da
AK		 443void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444{
ce7ddec4 445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 446}
447EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
ce7ddec4
JR		 449void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450{
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452}
453EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
0a79b009
AK		 455/*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 460{
0a79b009
AK		 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
298101da 465}
0a79b009 466EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 467
16f8a6f9
NA		 468bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469{
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475}
476EXPORT_SYMBOL_GPL(kvm_require_dr);
477
ec92fe44
JR		 478/*
479 * This function will be used to read from the physical memory of the currently
54bf36aa 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 481 * can read from guest physical or from the guest's guest physical memory.
482 */
483int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486{
54987b7a 487 struct x86_exception exception;
ec92fe44
JR		 488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
54987b7a 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
54bf36aa 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 499}
500EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
69b0049a 502static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 503 void *data, int offset, int len, u32 access)
504{
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507}
508
a03490ed
CO		 509/*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
ff03a073 512int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 513{
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
ff03a073 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 519
ff03a073
JR		 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 528 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 529 (pdpte[i] &
530 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 624
625 if ((cr0 ^ old_cr0) & X86_CR0_CD)
626 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
627
0f12244f
GN		 628 return 0;
629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 631
2d3ad1f4 632void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 633{
49a9b07e 634 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 637
42bdf991
MT		 638static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
639{
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
641 !vcpu->guest_xcr0_loaded) {
642 /* kvm_set_xcr() also depends on this */
643 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
644 vcpu->guest_xcr0_loaded = 1;
645 }
646}
647
648static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (vcpu->guest_xcr0_loaded) {
651 if (vcpu->arch.xcr0 != host_xcr0)
652 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
653 vcpu->guest_xcr0_loaded = 0;
654 }
655}
656
69b0049a 657static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 658{
56c103ec
LJ		 659 u64 xcr0 = xcr;
660 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 661 u64 valid_bits;
2acf923e
DC		 662
663 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
664 if (index != XCR_XFEATURE_ENABLED_MASK)
665 return 1;
2acf923e
DC		 666 if (!(xcr0 & XSTATE_FP))
667 return 1;
668 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
669 return 1;
46c34cb0
PB		 670
671 /*
672 * Do not allow the guest to set bits that we do not support
673 * saving. However, xcr0 bit 0 is always set, even if the
674 * emulated CPU does not support XSAVE (see fx_init).
675 */
676 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
677 if (xcr0 & ~valid_bits)
2acf923e 678 return 1;
46c34cb0 679
390bd528
LJ		 680 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
681 return 1;
682
612263b3
CP		 683 if (xcr0 & XSTATE_AVX512) {
684 if (!(xcr0 & XSTATE_YMM))
685 return 1;
686 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
687 return 1;
688 }
42bdf991 689 kvm_put_guest_xcr0(vcpu);
2acf923e 690 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 691
692 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
693 kvm_update_cpuid(vcpu);
2acf923e
DC		 694 return 0;
695}
696
697int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
698{
764bcbc5
Z		 699 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
700 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 701 kvm_inject_gp(vcpu, 0);
702 return 1;
703 }
704 return 0;
705}
706EXPORT_SYMBOL_GPL(kvm_set_xcr);
707
a83b29c6 708int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 709{
fc78f519 710 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 711 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
712 X86_CR4_SMEP | X86_CR4_SMAP;
713
0f12244f
GN		 714 if (cr4 & CR4_RESERVED_BITS)
715 return 1;
a03490ed 716
2acf923e
DC		 717 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
718 return 1;
719
c68b734f
YW		 720 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
721 return 1;
722
97ec8c06
FW		 723 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
724 return 1;
725
afcbf13f 726 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 727 return 1;
728
a03490ed 729 if (is_long_mode(vcpu)) {
0f12244f
GN		 730 if (!(cr4 & X86_CR4_PAE))
731 return 1;
a2edf57f
AK		 732 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
733 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 734 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
735 kvm_read_cr3(vcpu)))
0f12244f
GN		 736 return 1;
737
ad756a16
MJ		 738 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
739 if (!guest_cpuid_has_pcid(vcpu))
740 return 1;
741
742 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
743 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
744 return 1;
745 }
746
5e1746d6 747 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 748 return 1;
a03490ed 749
ad756a16
MJ		 750 if (((cr4 ^ old_cr4) & pdptr_bits) ||
751 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 752 kvm_mmu_reset_context(vcpu);
0f12244f 753
2acf923e 754 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 755 kvm_update_cpuid(vcpu);
2acf923e 756
0f12244f
GN		 757 return 0;
758}
2d3ad1f4 759EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 760
2390218b 761int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 762{
ac146235 763#ifdef CONFIG_X86_64
9d88fca7 764 cr3 &= ~CR3_PCID_INVD;
ac146235 765#endif
9d88fca7 766
9f8fe504 767 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 768 kvm_mmu_sync_roots(vcpu);
77c3913b 769 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 770 return 0;
d835dfec
AK		 771 }
772
a03490ed 773 if (is_long_mode(vcpu)) {
d9f89b88
JK		 774 if (cr3 & CR3_L_MODE_RESERVED_BITS)
775 return 1;
776 } else if (is_pae(vcpu) && is_paging(vcpu) &&
777 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 778 return 1;
a03490ed 779
0f12244f 780 vcpu->arch.cr3 = cr3;
aff48baa 781 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 782 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 783 return 0;
784}
2d3ad1f4 785EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 786
eea1cff9 787int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 788{
0f12244f
GN		 789 if (cr8 & CR8_RESERVED_BITS)
790 return 1;
35754c98 791 if (lapic_in_kernel(vcpu))
a03490ed
CO		 792 kvm_lapic_set_tpr(vcpu, cr8);
793 else
ad312c7c 794 vcpu->arch.cr8 = cr8;
0f12244f
GN		 795 return 0;
796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 798
2d3ad1f4 799unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 800{
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 return kvm_lapic_get_cr8(vcpu);
803 else
ad312c7c 804 return vcpu->arch.cr8;
a03490ed 805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 807
ae561ede
NA		 808static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
809{
810 int i;
811
812 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
813 for (i = 0; i < KVM_NR_DB_REGS; i++)
814 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
815 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
816 }
817}
818
73aaf249
JK		 819static void kvm_update_dr6(struct kvm_vcpu *vcpu)
820{
821 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
822 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
823}
824
c8639010
JK		 825static void kvm_update_dr7(struct kvm_vcpu *vcpu)
826{
827 unsigned long dr7;
828
829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 dr7 = vcpu->arch.guest_debug_dr7;
831 else
832 dr7 = vcpu->arch.dr7;
833 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
835 if (dr7 & DR7_BP_EN_MASK)
836 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 837}
838
6f43ed01
NA		 839static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
840{
841 u64 fixed = DR6_FIXED_1;
842
843 if (!guest_cpuid_has_rtm(vcpu))
844 fixed |= DR6_RTM;
845 return fixed;
846}
847
338dbc97 848static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 849{
850 switch (dr) {
851 case 0 ... 3:
852 vcpu->arch.db[dr] = val;
853 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
854 vcpu->arch.eff_db[dr] = val;
855 break;
856 case 4:
020df079
GN		 857 /* fall through */
858 case 6:
338dbc97
GN		 859 if (val & 0xffffffff00000000ULL)
860 return -1; /* #GP */
6f43ed01 861 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 862 kvm_update_dr6(vcpu);
020df079
GN		 863 break;
864 case 5:
020df079
GN		 865 /* fall through */
866 default: /* 7 */
338dbc97
GN		 867 if (val & 0xffffffff00000000ULL)
868 return -1; /* #GP */
020df079 869 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 870 kvm_update_dr7(vcpu);
020df079
GN		 871 break;
872 }
873
874 return 0;
875}
338dbc97
GN		 876
877int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
878{
16f8a6f9 879 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 880 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 881 return 1;
882 }
883 return 0;
338dbc97 884}
020df079
GN		 885EXPORT_SYMBOL_GPL(kvm_set_dr);
886
16f8a6f9 887int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 888{
889 switch (dr) {
890 case 0 ... 3:
891 *val = vcpu->arch.db[dr];
892 break;
893 case 4:
020df079
GN		 894 /* fall through */
895 case 6:
73aaf249
JK		 896 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
897 *val = vcpu->arch.dr6;
898 else
899 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 900 break;
901 case 5:
020df079
GN		 902 /* fall through */
903 default: /* 7 */
904 *val = vcpu->arch.dr7;
905 break;
906 }
338dbc97
GN		 907 return 0;
908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_get_dr);
910
022cd0e8
AK		 911bool kvm_rdpmc(struct kvm_vcpu *vcpu)
912{
913 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
914 u64 data;
915 int err;
916
c6702c9d 917 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 918 if (err)
919 return err;
920 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
921 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
922 return err;
923}
924EXPORT_SYMBOL_GPL(kvm_rdpmc);
925
043405e1
CO		 926/*
927 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
928 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
929 *
930 * This list is modified at module load time to reflect the
e3267cbb 931 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 932 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
933 * may depend on host virtualization features rather than host cpu features.
043405e1 934 */
e3267cbb 935
043405e1
CO		 936static u32 msrs_to_save[] = {
937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 938 MSR_STAR,
043405e1
CO		 939#ifdef CONFIG_X86_64
940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941#endif
b3897a49 942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 944};
945
946static unsigned num_msrs_to_save;
947
62ef68bb
PB		 948static u32 emulated_msrs[] = {
949 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
950 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
951 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
952 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 953 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
954 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
62ef68bb
PB		 955 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
956 MSR_KVM_PV_EOI_EN,
957
ba904635 958 MSR_IA32_TSC_ADJUST,
a3e06bbe 959 MSR_IA32_TSCDEADLINE,
043405e1 960 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 961 MSR_IA32_MCG_STATUS,
962 MSR_IA32_MCG_CTL,
64d60670 963 MSR_IA32_SMBASE,
043405e1
CO		 964};
965
62ef68bb
PB		 966static unsigned num_emulated_msrs;
967
384bb783 968bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 969{
b69e8cae 970 if (efer & efer_reserved_bits)
384bb783 971 return false;
15c4a640 972
1b2fd70c
AG		 973 if (efer & EFER_FFXSR) {
974 struct kvm_cpuid_entry2 *feat;
975
976 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 977 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 978 return false;
1b2fd70c
AG		 979 }
980
d8017474
AG		 981 if (efer & EFER_SVME) {
982 struct kvm_cpuid_entry2 *feat;
983
984 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 985 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 986 return false;
d8017474
AG		 987 }
988
384bb783
JK		 989 return true;
990}
991EXPORT_SYMBOL_GPL(kvm_valid_efer);
992
993static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
994{
995 u64 old_efer = vcpu->arch.efer;
996
997 if (!kvm_valid_efer(vcpu, efer))
998 return 1;
999
1000 if (is_paging(vcpu)
1001 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1002 return 1;
1003
15c4a640 1004 efer &= ~EFER_LMA;
f6801dff 1005 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1006
a3d204e2
SY		 1007 kvm_x86_ops->set_efer(vcpu, efer);
1008
aad82703
SY		 1009 /* Update reserved bits */
1010 if ((efer ^ old_efer) & EFER_NX)
1011 kvm_mmu_reset_context(vcpu);
1012
b69e8cae 1013 return 0;
15c4a640
CO		 1014}
1015
f2b4b7dd
JR		 1016void kvm_enable_efer_bits(u64 mask)
1017{
1018 efer_reserved_bits &= ~mask;
1019}
1020EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1021
15c4a640
CO		 1022/*
1023 * Writes msr value into into the appropriate "register".
1024 * Returns 0 on success, non-0 otherwise.
1025 * Assumes vcpu_load() was already called.
1026 */
8fe8ab46 1027int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1028{
854e8bb1
NA		 1029 switch (msr->index) {
1030 case MSR_FS_BASE:
1031 case MSR_GS_BASE:
1032 case MSR_KERNEL_GS_BASE:
1033 case MSR_CSTAR:
1034 case MSR_LSTAR:
1035 if (is_noncanonical_address(msr->data))
1036 return 1;
1037 break;
1038 case MSR_IA32_SYSENTER_EIP:
1039 case MSR_IA32_SYSENTER_ESP:
1040 /*
1041 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1042 * non-canonical address is written on Intel but not on
1043 * AMD (which ignores the top 32-bits, because it does
1044 * not implement 64-bit SYSENTER).
1045 *
1046 * 64-bit code should hence be able to write a non-canonical
1047 * value on AMD. Making the address canonical ensures that
1048 * vmentry does not fail on Intel after writing a non-canonical
1049 * value, and that something deterministic happens if the guest
1050 * invokes 64-bit SYSENTER.
1051 */
1052 msr->data = get_canonical(msr->data);
1053 }
8fe8ab46 1054 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1055}
854e8bb1 1056EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1057
313a3dc7
CO		 1058/*
1059 * Adapt set_msr() to msr_io()'s calling convention
1060 */
609e36d3
PB		 1061static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1062{
1063 struct msr_data msr;
1064 int r;
1065
1066 msr.index = index;
1067 msr.host_initiated = true;
1068 r = kvm_get_msr(vcpu, &msr);
1069 if (r)
1070 return r;
1071
1072 *data = msr.data;
1073 return 0;
1074}
1075
313a3dc7
CO		 1076static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1077{
8fe8ab46
WA		 1078 struct msr_data msr;
1079
1080 msr.data = *data;
1081 msr.index = index;
1082 msr.host_initiated = true;
1083 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1084}
1085
16e8d74d
MT		 1086#ifdef CONFIG_X86_64
1087struct pvclock_gtod_data {
1088 seqcount_t seq;
1089
1090 struct { /* extract of a clocksource struct */
1091 int vclock_mode;
1092 cycle_t cycle_last;
1093 cycle_t mask;
1094 u32 mult;
1095 u32 shift;
1096 } clock;
1097
cbcf2dd3
TG		 1098 u64 boot_ns;
1099 u64 nsec_base;
16e8d74d
MT		 1100};
1101
1102static struct pvclock_gtod_data pvclock_gtod_data;
1103
1104static void update_pvclock_gtod(struct timekeeper *tk)
1105{
1106 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1107 u64 boot_ns;
1108
876e7881 1109 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1110
1111 write_seqcount_begin(&vdata->seq);
1112
1113 /* copy pvclock gtod data */
876e7881
PZ		 1114 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1115 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1116 vdata->clock.mask = tk->tkr_mono.mask;
1117 vdata->clock.mult = tk->tkr_mono.mult;
1118 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1119
cbcf2dd3 1120 vdata->boot_ns = boot_ns;
876e7881 1121 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1122
1123 write_seqcount_end(&vdata->seq);
1124}
1125#endif
1126
bab5bb39
NK		 1127void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1128{
1129 /*
1130 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1131 * vcpu_enter_guest. This function is only called from
1132 * the physical CPU that is running vcpu.
1133 */
1134 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1135}
16e8d74d 1136
18068523
GOC		 1137static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1138{
9ed3c444
AK		 1139 int version;
1140 int r;
50d0a0f9 1141 struct pvclock_wall_clock wc;
923de3cf 1142 struct timespec boot;
18068523
GOC		 1143
1144 if (!wall_clock)
1145 return;
1146
9ed3c444
AK		 1147 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1148 if (r)
1149 return;
1150
1151 if (version & 1)
1152 ++version; /* first time write, random junk */
1153
1154 ++version;
18068523 1155
18068523
GOC		 1156 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1157
50d0a0f9
GH		 1158 /*
1159 * The guest calculates current wall clock time by adding
34c238a1 1160 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1161 * wall clock specified here. guest system time equals host
1162 * system time for us, thus we must fill in host boot time here.
1163 */
923de3cf 1164 getboottime(&boot);
50d0a0f9 1165
4b648665
BR		 1166 if (kvm->arch.kvmclock_offset) {
1167 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1168 boot = timespec_sub(boot, ts);
1169 }
50d0a0f9
GH		 1170 wc.sec = boot.tv_sec;
1171 wc.nsec = boot.tv_nsec;
1172 wc.version = version;
18068523
GOC		 1173
1174 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1175
1176 version++;
1177 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1178}
1179
50d0a0f9
GH		 1180static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1181{
1182 uint32_t quotient, remainder;
1183
1184 /* Don't try to replace with do_div(), this one calculates
1185 * "(dividend << 32) / divisor" */
1186 __asm__ ( "divl %4"
1187 : "=a" (quotient), "=d" (remainder)
1188 : "0" (0), "1" (dividend), "r" (divisor) );
1189 return quotient;
1190}
1191
5f4e3f88
ZA		 1192static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1193 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1194{
5f4e3f88 1195 uint64_t scaled64;
50d0a0f9
GH		 1196 int32_t shift = 0;
1197 uint64_t tps64;
1198 uint32_t tps32;
1199
5f4e3f88
ZA		 1200 tps64 = base_khz * 1000LL;
1201 scaled64 = scaled_khz * 1000LL;
50933623 1202 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1203 tps64 >>= 1;
1204 shift--;
1205 }
1206
1207 tps32 = (uint32_t)tps64;
50933623
JK		 1208 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1209 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1210 scaled64 >>= 1;
1211 else
1212 tps32 <<= 1;
50d0a0f9
GH		 1213 shift++;
1214 }
1215
5f4e3f88
ZA		 1216 *pshift = shift;
1217 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1218
5f4e3f88
ZA		 1219 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1220 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1221}
1222
d828199e 1223#ifdef CONFIG_X86_64
16e8d74d 1224static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1225#endif
16e8d74d 1226
c8076604 1227static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1228static unsigned long max_tsc_khz;
c8076604 1229
cc578287 1230static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1231{
cc578287
ZA		 1232 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1233 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1234}
1235
cc578287 1236static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1237{
cc578287
ZA		 1238 u64 v = (u64)khz * (1000000 + ppm);
1239 do_div(v, 1000000);
1240 return v;
1e993611
JR		 1241}
1242
cc578287 1243static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1244{
cc578287
ZA		 1245 u32 thresh_lo, thresh_hi;
1246 int use_scaling = 0;
217fc9cf 1247
03ba32ca
MT		 1248 /* tsc_khz can be zero if TSC calibration fails */
1249 if (this_tsc_khz == 0)
1250 return;
1251
c285545f
ZA		 1252 /* Compute a scale to convert nanoseconds in TSC cycles */
1253 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1254 &vcpu->arch.virtual_tsc_shift,
1255 &vcpu->arch.virtual_tsc_mult);
1256 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1257
1258 /*
1259 * Compute the variation in TSC rate which is acceptable
1260 * within the range of tolerance and decide if the
1261 * rate being applied is within that bounds of the hardware
1262 * rate. If so, no scaling or compensation need be done.
1263 */
1264 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1265 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1266 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1267 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1268 use_scaling = 1;
1269 }
1270 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1271}
1272
1273static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1274{
e26101b1 1275 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1276 vcpu->arch.virtual_tsc_mult,
1277 vcpu->arch.virtual_tsc_shift);
e26101b1 1278 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1279 return tsc;
1280}
1281
69b0049a 1282static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1283{
1284#ifdef CONFIG_X86_64
1285 bool vcpus_matched;
b48aa97e
MT		 1286 struct kvm_arch *ka = &vcpu->kvm->arch;
1287 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1288
1289 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1290 atomic_read(&vcpu->kvm->online_vcpus));
1291
7f187922
MT		 1292 /*
1293 * Once the masterclock is enabled, always perform request in
1294 * order to update it.
1295 *
1296 * In order to enable masterclock, the host clocksource must be TSC
1297 * and the vcpus need to have matched TSCs. When that happens,
1298 * perform request to enable masterclock.
1299 */
1300 if (ka->use_master_clock ||
1301 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1302 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1303
1304 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1305 atomic_read(&vcpu->kvm->online_vcpus),
1306 ka->use_master_clock, gtod->clock.vclock_mode);
1307#endif
1308}
1309
ba904635
WA		 1310static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1311{
1312 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1313 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1314}
1315
8fe8ab46 1316void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1317{
1318 struct kvm *kvm = vcpu->kvm;
f38e098f 1319 u64 offset, ns, elapsed;
99e3e30a 1320 unsigned long flags;
02626b6a 1321 s64 usdiff;
b48aa97e 1322 bool matched;
0d3da0d2 1323 bool already_matched;
8fe8ab46 1324 u64 data = msr->data;
99e3e30a 1325
038f8c11 1326 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1327 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1328 ns = get_kernel_ns();
f38e098f 1329 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1330
03ba32ca 1331 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1332 int faulted = 0;
1333
03ba32ca
MT		 1334 /* n.b - signed multiplication and division required */
1335 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1336#ifdef CONFIG_X86_64
03ba32ca 1337 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1338#else
03ba32ca 1339 /* do_div() only does unsigned */
8915aa27
MT		 1340 asm("1: idivl %[divisor]\n"
1341 "2: xor %%edx, %%edx\n"
1342 " movl $0, %[faulted]\n"
1343 "3:\n"
1344 ".section .fixup,\"ax\"\n"
1345 "4: movl $1, %[faulted]\n"
1346 " jmp 3b\n"
1347 ".previous\n"
1348
1349 _ASM_EXTABLE(1b, 4b)
1350
1351 : "=A"(usdiff), [faulted] "=r" (faulted)
1352 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1353
5d3cb0f6 1354#endif
03ba32ca
MT		 1355 do_div(elapsed, 1000);
1356 usdiff -= elapsed;
1357 if (usdiff < 0)
1358 usdiff = -usdiff;
8915aa27
MT		 1359
1360 /* idivl overflow => difference is larger than USEC_PER_SEC */
1361 if (faulted)
1362 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1363 } else
1364 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1365
1366 /*
5d3cb0f6
ZA		 1367 * Special case: TSC write with a small delta (1 second) of virtual
1368 * cycle time against real time is interpreted as an attempt to
1369 * synchronize the CPU.
1370 *
1371 * For a reliable TSC, we can match TSC offsets, and for an unstable
1372 * TSC, we add elapsed time in this computation. We could let the
1373 * compensation code attempt to catch up if we fall behind, but
1374 * it's better to try to match offsets from the beginning.
1375 */
02626b6a 1376 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1377 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1378 if (!check_tsc_unstable()) {
e26101b1 1379 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1380 pr_debug("kvm: matched tsc offset for %llu\n", data);
1381 } else {
857e4099 1382 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1383 data += delta;
1384 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1385 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1386 }
b48aa97e 1387 matched = true;
0d3da0d2 1388 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1389 } else {
1390 /*
1391 * We split periods of matched TSC writes into generations.
1392 * For each generation, we track the original measured
1393 * nanosecond time, offset, and write, so if TSCs are in
1394 * sync, we can match exact offset, and if not, we can match
4a969980 1395 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1396 *
1397 * These values are tracked in kvm->arch.cur_xxx variables.
1398 */
1399 kvm->arch.cur_tsc_generation++;
1400 kvm->arch.cur_tsc_nsec = ns;
1401 kvm->arch.cur_tsc_write = data;
1402 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1403 matched = false;
0d3da0d2 1404 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1405 kvm->arch.cur_tsc_generation, data);
f38e098f 1406 }
e26101b1
ZA		 1407
1408 /*
1409 * We also track th most recent recorded KHZ, write and time to
1410 * allow the matching interval to be extended at each write.
1411 */
f38e098f
ZA		 1412 kvm->arch.last_tsc_nsec = ns;
1413 kvm->arch.last_tsc_write = data;
5d3cb0f6 1414 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1415
b183aa58 1416 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1417
1418 /* Keep track of which generation this VCPU has synchronized to */
1419 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1420 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1421 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1422
ba904635
WA		 1423 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1424 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1425 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1426 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1427
1428 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1429 if (!matched) {
b48aa97e 1430 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1431 } else if (!already_matched) {
1432 kvm->arch.nr_vcpus_matched_tsc++;
1433 }
b48aa97e
MT		 1434
1435 kvm_track_tsc_matching(vcpu);
1436 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1437}
e26101b1 1438
99e3e30a
ZA		 1439EXPORT_SYMBOL_GPL(kvm_write_tsc);
1440
d828199e
MT		 1441#ifdef CONFIG_X86_64
1442
1443static cycle_t read_tsc(void)
1444{
03b9730b
AL		 1445 cycle_t ret = (cycle_t)rdtsc_ordered();
1446 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1447
1448 if (likely(ret >= last))
1449 return ret;
1450
1451 /*
1452 * GCC likes to generate cmov here, but this branch is extremely
1453 * predictable (it's just a funciton of time and the likely is
1454 * very likely) and there's a data dependence, so force GCC
1455 * to generate a branch instead. I don't barrier() because
1456 * we don't actually need a barrier, and if this function
1457 * ever gets inlined it will generate worse code.
1458 */
1459 asm volatile ("");
1460 return last;
1461}
1462
1463static inline u64 vgettsc(cycle_t *cycle_now)
1464{
1465 long v;
1466 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1467
1468 *cycle_now = read_tsc();
1469
1470 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1471 return v * gtod->clock.mult;
1472}
1473
cbcf2dd3 1474static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1475{
cbcf2dd3 1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1477 unsigned long seq;
d828199e 1478 int mode;
cbcf2dd3 1479 u64 ns;
d828199e 1480
d828199e
MT		 1481 do {
1482 seq = read_seqcount_begin(&gtod->seq);
1483 mode = gtod->clock.vclock_mode;
cbcf2dd3 1484 ns = gtod->nsec_base;
d828199e
MT		 1485 ns += vgettsc(cycle_now);
1486 ns >>= gtod->clock.shift;
cbcf2dd3 1487 ns += gtod->boot_ns;
d828199e 1488 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1489 *t = ns;
d828199e
MT		 1490
1491 return mode;
1492}
1493
1494/* returns true if host is using tsc clocksource */
1495static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1496{
d828199e
MT		 1497 /* checked again under seqlock below */
1498 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1499 return false;
1500
cbcf2dd3 1501 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1502}
1503#endif
1504
1505/*
1506 *
b48aa97e
MT		 1507 * Assuming a stable TSC across physical CPUS, and a stable TSC
1508 * across virtual CPUs, the following condition is possible.
1509 * Each numbered line represents an event visible to both
d828199e
MT		 1510 * CPUs at the next numbered event.
1511 *
1512 * "timespecX" represents host monotonic time. "tscX" represents
1513 * RDTSC value.
1514 *
1515 * VCPU0 on CPU0 | VCPU1 on CPU1
1516 *
1517 * 1. read timespec0,tsc0
1518 * 2. | timespec1 = timespec0 + N
1519 * | tsc1 = tsc0 + M
1520 * 3. transition to guest | transition to guest
1521 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1522 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1523 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1524 *
1525 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1526 *
1527 * - ret0 < ret1
1528 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1529 * ...
1530 * - 0 < N - M => M < N
1531 *
1532 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1533 * always the case (the difference between two distinct xtime instances
1534 * might be smaller then the difference between corresponding TSC reads,
1535 * when updating guest vcpus pvclock areas).
1536 *
1537 * To avoid that problem, do not allow visibility of distinct
1538 * system_timestamp/tsc_timestamp values simultaneously: use a master
1539 * copy of host monotonic time values. Update that master copy
1540 * in lockstep.
1541 *
b48aa97e 1542 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1543 *
1544 */
1545
1546static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1547{
1548#ifdef CONFIG_X86_64
1549 struct kvm_arch *ka = &kvm->arch;
1550 int vclock_mode;
b48aa97e
MT		 1551 bool host_tsc_clocksource, vcpus_matched;
1552
1553 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1554 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1555
1556 /*
1557 * If the host uses TSC clock, then passthrough TSC as stable
1558 * to the guest.
1559 */
b48aa97e 1560 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1561 &ka->master_kernel_ns,
1562 &ka->master_cycle_now);
1563
16a96021 1564 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1565 && !backwards_tsc_observed
1566 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1567
d828199e
MT		 1568 if (ka->use_master_clock)
1569 atomic_set(&kvm_guest_has_master_clock, 1);
1570
1571 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1572 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1573 vcpus_matched);
d828199e
MT		 1574#endif
1575}
1576
2e762ff7
MT		 1577static void kvm_gen_update_masterclock(struct kvm *kvm)
1578{
1579#ifdef CONFIG_X86_64
1580 int i;
1581 struct kvm_vcpu *vcpu;
1582 struct kvm_arch *ka = &kvm->arch;
1583
1584 spin_lock(&ka->pvclock_gtod_sync_lock);
1585 kvm_make_mclock_inprogress_request(kvm);
1586 /* no guest entries from this point */
1587 pvclock_update_vm_gtod_copy(kvm);
1588
1589 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1591
1592 /* guest entries allowed */
1593 kvm_for_each_vcpu(i, vcpu, kvm)
1594 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1595
1596 spin_unlock(&ka->pvclock_gtod_sync_lock);
1597#endif
1598}
1599
34c238a1 1600static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1601{
d828199e 1602 unsigned long flags, this_tsc_khz;
18068523 1603 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1604 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1605 s64 kernel_ns;
d828199e 1606 u64 tsc_timestamp, host_tsc;
0b79459b 1607 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1608 u8 pvclock_flags;
d828199e
MT		 1609 bool use_master_clock;
1610
1611 kernel_ns = 0;
1612 host_tsc = 0;
18068523 1613
d828199e
MT		 1614 /*
1615 * If the host uses TSC clock, then passthrough TSC as stable
1616 * to the guest.
1617 */
1618 spin_lock(&ka->pvclock_gtod_sync_lock);
1619 use_master_clock = ka->use_master_clock;
1620 if (use_master_clock) {
1621 host_tsc = ka->master_cycle_now;
1622 kernel_ns = ka->master_kernel_ns;
1623 }
1624 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1625
1626 /* Keep irq disabled to prevent changes to the clock */
1627 local_irq_save(flags);
89cbc767 1628 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1629 if (unlikely(this_tsc_khz == 0)) {
1630 local_irq_restore(flags);
1631 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1632 return 1;
1633 }
d828199e 1634 if (!use_master_clock) {
4ea1636b 1635 host_tsc = rdtsc();
d828199e
MT		 1636 kernel_ns = get_kernel_ns();
1637 }
1638
1639 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1640
c285545f
ZA		 1641 /*
1642 * We may have to catch up the TSC to match elapsed wall clock
1643 * time for two reasons, even if kvmclock is used.
1644 * 1) CPU could have been running below the maximum TSC rate
1645 * 2) Broken TSC compensation resets the base at each VCPU
1646 * entry to avoid unknown leaps of TSC even when running
1647 * again on the same CPU. This may cause apparent elapsed
1648 * time to disappear, and the guest to stand still or run
1649 * very slowly.
1650 */
1651 if (vcpu->tsc_catchup) {
1652 u64 tsc = compute_guest_tsc(v, kernel_ns);
1653 if (tsc > tsc_timestamp) {
f1e2b260 1654 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1655 tsc_timestamp = tsc;
1656 }
50d0a0f9
GH		 1657 }
1658
18068523
GOC		 1659 local_irq_restore(flags);
1660
0b79459b 1661 if (!vcpu->pv_time_enabled)
c285545f 1662 return 0;
18068523 1663
e48672fa 1664 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1665 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1666 &vcpu->hv_clock.tsc_shift,
1667 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1668 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1669 }
1670
1671 /* With all the info we got, fill in the values */
1d5f066e 1672 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1673 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1674 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1675
09a0c3f1
OH		 1676 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1677 &guest_hv_clock, sizeof(guest_hv_clock))))
1678 return 0;
1679
5dca0d91
RK		 1680 /* This VCPU is paused, but it's legal for a guest to read another
1681 * VCPU's kvmclock, so we really have to follow the specification where
1682 * it says that version is odd if data is being modified, and even after
1683 * it is consistent.
1684 *
1685 * Version field updates must be kept separate. This is because
1686 * kvm_write_guest_cached might use a "rep movs" instruction, and
1687 * writes within a string instruction are weakly ordered. So there
1688 * are three writes overall.
1689 *
1690 * As a small optimization, only write the version field in the first
1691 * and third write. The vcpu->pv_time cache is still valid, because the
1692 * version field is the first in the struct.
18068523 1693 */
5dca0d91
RK		 1694 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1695
1696 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1697 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1698 &vcpu->hv_clock,
1699 sizeof(vcpu->hv_clock.version));
1700
1701 smp_wmb();
78c0337a
MT		 1702
1703 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1704 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1705
1706 if (vcpu->pvclock_set_guest_stopped_request) {
1707 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1708 vcpu->pvclock_set_guest_stopped_request = false;
1709 }
1710
d828199e
MT		 1711 /* If the host uses TSC clocksource, then it is stable */
1712 if (use_master_clock)
1713 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1714
78c0337a
MT		 1715 vcpu->hv_clock.flags = pvclock_flags;
1716
ce1a5e60
DM		 1717 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1718
0b79459b
AH		 1719 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1720 &vcpu->hv_clock,
1721 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1722
1723 smp_wmb();
1724
1725 vcpu->hv_clock.version++;
1726 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1727 &vcpu->hv_clock,
1728 sizeof(vcpu->hv_clock.version));
8cfdc000 1729 return 0;
c8076604
GH		 1730}
1731
0061d53d
MT		 1732/*
1733 * kvmclock updates which are isolated to a given vcpu, such as
1734 * vcpu->cpu migration, should not allow system_timestamp from
1735 * the rest of the vcpus to remain static. Otherwise ntp frequency
1736 * correction applies to one vcpu's system_timestamp but not
1737 * the others.
1738 *
1739 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1740 * We need to rate-limit these requests though, as they can
1741 * considerably slow guests that have a large number of vcpus.
1742 * The time for a remote vcpu to update its kvmclock is bound
1743 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1744 */
1745
7e44e449
AJ		 1746#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1747
1748static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1749{
1750 int i;
7e44e449
AJ		 1751 struct delayed_work *dwork = to_delayed_work(work);
1752 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1753 kvmclock_update_work);
1754 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1755 struct kvm_vcpu *vcpu;
1756
1757 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1758 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1759 kvm_vcpu_kick(vcpu);
1760 }
1761}
1762
7e44e449
AJ		 1763static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1764{
1765 struct kvm *kvm = v->kvm;
1766
105b21bb 1767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1768 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1769 KVMCLOCK_UPDATE_DELAY);
1770}
1771
332967a3
AJ		 1772#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1773
1774static void kvmclock_sync_fn(struct work_struct *work)
1775{
1776 struct delayed_work *dwork = to_delayed_work(work);
1777 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1778 kvmclock_sync_work);
1779 struct kvm *kvm = container_of(ka, struct kvm, arch);
1780
630994b3
MT		 1781 if (!kvmclock_periodic_sync)
1782 return;
1783
332967a3
AJ		 1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1785 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1786 KVMCLOCK_SYNC_PERIOD);
1787}
1788
890ca9ae 1789static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1790{
890ca9ae
HY		 1791 u64 mcg_cap = vcpu->arch.mcg_cap;
1792 unsigned bank_num = mcg_cap & 0xff;
1793
15c4a640 1794 switch (msr) {
15c4a640 1795 case MSR_IA32_MCG_STATUS:
890ca9ae 1796 vcpu->arch.mcg_status = data;
15c4a640 1797 break;
c7ac679c 1798 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1799 if (!(mcg_cap & MCG_CTL_P))
1800 return 1;
1801 if (data != 0 && data != ~(u64)0)
1802 return -1;
1803 vcpu->arch.mcg_ctl = data;
1804 break;
1805 default:
1806 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1807 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1808 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1809 /* only 0 or all 1s can be written to IA32_MCi_CTL
1810 * some Linux kernels though clear bit 10 in bank 4 to
1811 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1812 * this to avoid an uncatched #GP in the guest
1813 */
890ca9ae 1814 if ((offset & 0x3) == 0 &&
114be429 1815 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1816 return -1;
1817 vcpu->arch.mce_banks[offset] = data;
1818 break;
1819 }
1820 return 1;
1821 }
1822 return 0;
1823}
1824
ffde22ac
ES		 1825static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1826{
1827 struct kvm *kvm = vcpu->kvm;
1828 int lm = is_long_mode(vcpu);
1829 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1830 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1831 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1832 : kvm->arch.xen_hvm_config.blob_size_32;
1833 u32 page_num = data & ~PAGE_MASK;
1834 u64 page_addr = data & PAGE_MASK;
1835 u8 *page;
1836 int r;
1837
1838 r = -E2BIG;
1839 if (page_num >= blob_size)
1840 goto out;
1841 r = -ENOMEM;
ff5c2c03
SL		 1842 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1843 if (IS_ERR(page)) {
1844 r = PTR_ERR(page);
ffde22ac 1845 goto out;
ff5c2c03 1846 }
54bf36aa 1847 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1848 goto out_free;
1849 r = 0;
1850out_free:
1851 kfree(page);
1852out:
1853 return r;
1854}
1855
344d9588
GN		 1856static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1857{
1858 gpa_t gpa = data & ~0x3f;
1859
4a969980 1860 /* Bits 2:5 are reserved, Should be zero */
6adba527 1861 if (data & 0x3c)
344d9588
GN		 1862 return 1;
1863
1864 vcpu->arch.apf.msr_val = data;
1865
1866 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1867 kvm_clear_async_pf_completion_queue(vcpu);
1868 kvm_async_pf_hash_reset(vcpu);
1869 return 0;
1870 }
1871
8f964525
AH		 1872 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1873 sizeof(u32)))
344d9588
GN		 1874 return 1;
1875
6adba527 1876 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1877 kvm_async_pf_wakeup_all(vcpu);
1878 return 0;
1879}
1880
12f9a48f
GC		 1881static void kvmclock_reset(struct kvm_vcpu *vcpu)
1882{
0b79459b 1883 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1884}
1885
c9aaa895
GC		 1886static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1887{
1888 u64 delta;
1889
1890 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1891 return;
1892
1893 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1894 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1895 vcpu->arch.st.accum_steal = delta;
1896}
1897
1898static void record_steal_time(struct kvm_vcpu *vcpu)
1899{
1900 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1901 return;
1902
1903 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1904 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1905 return;
1906
1907 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1908 vcpu->arch.st.steal.version += 2;
1909 vcpu->arch.st.accum_steal = 0;
1910
1911 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1912 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1913}
1914
8fe8ab46 1915int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1916{
5753785f 1917 bool pr = false;
8fe8ab46
WA		 1918 u32 msr = msr_info->index;
1919 u64 data = msr_info->data;
5753785f 1920
15c4a640 1921 switch (msr) {
2e32b719
BP		 1922 case MSR_AMD64_NB_CFG:
1923 case MSR_IA32_UCODE_REV:
1924 case MSR_IA32_UCODE_WRITE:
1925 case MSR_VM_HSAVE_PA:
1926 case MSR_AMD64_PATCH_LOADER:
1927 case MSR_AMD64_BU_CFG2:
1928 break;
1929
15c4a640 1930 case MSR_EFER:
b69e8cae 1931 return set_efer(vcpu, data);
8f1589d9
AP		 1932 case MSR_K7_HWCR:
1933 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1934 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1935 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1936 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1937 if (data != 0) {
a737f256
CD		 1938 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1939 data);
8f1589d9
AP		 1940 return 1;
1941 }
15c4a640 1942 break;
f7c6d140
AP		 1943 case MSR_FAM10H_MMIO_CONF_BASE:
1944 if (data != 0) {
a737f256
CD		 1945 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1946 "0x%llx\n", data);
f7c6d140
AP		 1947 return 1;
1948 }
15c4a640 1949 break;
b5e2fec0
AG		 1950 case MSR_IA32_DEBUGCTLMSR:
1951 if (!data) {
1952 /* We support the non-activated case already */
1953 break;
1954 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1955 /* Values other than LBR and BTF are vendor-specific,
1956 thus reserved and should throw a #GP */
1957 return 1;
1958 }
a737f256
CD		 1959 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1960 __func__, data);
b5e2fec0 1961 break;
9ba075a6 1962 case 0x200 ... 0x2ff:
ff53604b 1963 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1964 case MSR_IA32_APICBASE:
58cb628d 1965 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1966 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1967 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1968 case MSR_IA32_TSCDEADLINE:
1969 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1970 break;
ba904635
WA		 1971 case MSR_IA32_TSC_ADJUST:
1972 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1973 if (!msr_info->host_initiated) {
d913b904 1974 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 1975 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 1976 }
1977 vcpu->arch.ia32_tsc_adjust_msr = data;
1978 }
1979 break;
15c4a640 1980 case MSR_IA32_MISC_ENABLE:
ad312c7c 1981 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1982 break;
64d60670
PB		 1983 case MSR_IA32_SMBASE:
1984 if (!msr_info->host_initiated)
1985 return 1;
1986 vcpu->arch.smbase = data;
1987 break;
11c6bffa 1988 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1989 case MSR_KVM_WALL_CLOCK:
1990 vcpu->kvm->arch.wall_clock = data;
1991 kvm_write_wall_clock(vcpu->kvm, data);
1992 break;
11c6bffa 1993 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1994 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1995 u64 gpa_offset;
54750f2c
MT		 1996 struct kvm_arch *ka = &vcpu->kvm->arch;
1997
12f9a48f 1998 kvmclock_reset(vcpu);
18068523 1999
54750f2c
MT		 2000 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2001 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2002
2003 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2004 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2005 &vcpu->requests);
2006
2007 ka->boot_vcpu_runs_old_kvmclock = tmp;
2008 }
2009
18068523 2010 vcpu->arch.time = data;
0061d53d 2011 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2012
2013 /* we verify if the enable bit is set... */
2014 if (!(data & 1))
2015 break;
2016
0b79459b 2017 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2018
0b79459b 2019 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2020 &vcpu->arch.pv_time, data & ~1ULL,
2021 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2022 vcpu->arch.pv_time_enabled = false;
2023 else
2024 vcpu->arch.pv_time_enabled = true;
32cad84f 2025
18068523
GOC		 2026 break;
2027 }
344d9588
GN		 2028 case MSR_KVM_ASYNC_PF_EN:
2029 if (kvm_pv_enable_async_pf(vcpu, data))
2030 return 1;
2031 break;
c9aaa895
GC		 2032 case MSR_KVM_STEAL_TIME:
2033
2034 if (unlikely(!sched_info_on()))
2035 return 1;
2036
2037 if (data & KVM_STEAL_RESERVED_MASK)
2038 return 1;
2039
2040 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2041 data & KVM_STEAL_VALID_BITS,
2042 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2043 return 1;
2044
2045 vcpu->arch.st.msr_val = data;
2046
2047 if (!(data & KVM_MSR_ENABLED))
2048 break;
2049
2050 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2051
2052 preempt_disable();
2053 accumulate_steal_time(vcpu);
2054 preempt_enable();
2055
2056 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2057
2058 break;
ae7a2a3f
MT		 2059 case MSR_KVM_PV_EOI_EN:
2060 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2061 return 1;
2062 break;
c9aaa895 2063
890ca9ae
HY		 2064 case MSR_IA32_MCG_CTL:
2065 case MSR_IA32_MCG_STATUS:
81760dcc 2066 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2067 return set_msr_mce(vcpu, msr, data);
71db6023 2068
6912ac32
WH		 2069 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2070 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2071 pr = true; /* fall through */
2072 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2073 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2074 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2075 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2076
2077 if (pr || data != 0)
a737f256
CD		 2078 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2079 "0x%x data 0x%llx\n", msr, data);
5753785f 2080 break;
84e0cefa
JS		 2081 case MSR_K7_CLK_CTL:
2082 /*
2083 * Ignore all writes to this no longer documented MSR.
2084 * Writes are only relevant for old K7 processors,
2085 * all pre-dating SVM, but a recommended workaround from
4a969980 2086 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2087 * affected processor models on the command line, hence
2088 * the need to ignore the workaround.
2089 */
2090 break;
55cd8e5a 2091 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2092 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2093 case HV_X64_MSR_CRASH_CTL:
2094 return kvm_hv_set_msr_common(vcpu, msr, data,
2095 msr_info->host_initiated);
91c9c3ed 2096 case MSR_IA32_BBL_CR_CTL3:
2097 /* Drop writes to this legacy MSR -- see rdmsr
2098 * counterpart for further detail.
2099 */
a737f256 2100 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2101 break;
2b036c6b
BO		 2102 case MSR_AMD64_OSVW_ID_LENGTH:
2103 if (!guest_cpuid_has_osvw(vcpu))
2104 return 1;
2105 vcpu->arch.osvw.length = data;
2106 break;
2107 case MSR_AMD64_OSVW_STATUS:
2108 if (!guest_cpuid_has_osvw(vcpu))
2109 return 1;
2110 vcpu->arch.osvw.status = data;
2111 break;
15c4a640 2112 default:
ffde22ac
ES		 2113 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2114 return xen_hvm_config(vcpu, data);
c6702c9d 2115 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2116 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2117 if (!ignore_msrs) {
a737f256
CD		 2118 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2119 msr, data);
ed85c068
AP		 2120 return 1;
2121 } else {
a737f256
CD		 2122 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2123 msr, data);
ed85c068
AP		 2124 break;
2125 }
15c4a640
CO		 2126 }
2127 return 0;
2128}
2129EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2130
2131
2132/*
2133 * Reads an msr value (of 'msr_index') into 'pdata'.
2134 * Returns 0 on success, non-0 otherwise.
2135 * Assumes vcpu_load() was already called.
2136 */
609e36d3 2137int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2138{
609e36d3 2139 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2140}
ff651cb6 2141EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2142
890ca9ae 2143static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2144{
2145 u64 data;
890ca9ae
HY		 2146 u64 mcg_cap = vcpu->arch.mcg_cap;
2147 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2148
2149 switch (msr) {
15c4a640
CO		 2150 case MSR_IA32_P5_MC_ADDR:
2151 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2152 data = 0;
2153 break;
15c4a640 2154 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2155 data = vcpu->arch.mcg_cap;
2156 break;
c7ac679c 2157 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2158 if (!(mcg_cap & MCG_CTL_P))
2159 return 1;
2160 data = vcpu->arch.mcg_ctl;
2161 break;
2162 case MSR_IA32_MCG_STATUS:
2163 data = vcpu->arch.mcg_status;
2164 break;
2165 default:
2166 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2167 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2168 u32 offset = msr - MSR_IA32_MC0_CTL;
2169 data = vcpu->arch.mce_banks[offset];
2170 break;
2171 }
2172 return 1;
2173 }
2174 *pdata = data;
2175 return 0;
2176}
2177
609e36d3 2178int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2179{
609e36d3 2180 switch (msr_info->index) {
890ca9ae 2181 case MSR_IA32_PLATFORM_ID:
15c4a640 2182 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2183 case MSR_IA32_DEBUGCTLMSR:
2184 case MSR_IA32_LASTBRANCHFROMIP:
2185 case MSR_IA32_LASTBRANCHTOIP:
2186 case MSR_IA32_LASTINTFROMIP:
2187 case MSR_IA32_LASTINTTOIP:
60af2ecd 2188 case MSR_K8_SYSCFG:
3afb1121
PB		 2189 case MSR_K8_TSEG_ADDR:
2190 case MSR_K8_TSEG_MASK:
60af2ecd 2191 case MSR_K7_HWCR:
61a6bd67 2192 case MSR_VM_HSAVE_PA:
1fdbd48c 2193 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2194 case MSR_AMD64_NB_CFG:
f7c6d140 2195 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2196 case MSR_AMD64_BU_CFG2:
609e36d3 2197 msr_info->data = 0;
15c4a640 2198 break;
6912ac32
WH		 2199 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2200 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2201 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2202 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2203 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2204 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2205 msr_info->data = 0;
5753785f 2206 break;
742bc670 2207 case MSR_IA32_UCODE_REV:
609e36d3 2208 msr_info->data = 0x100000000ULL;
742bc670 2209 break;
9ba075a6 2210 case MSR_MTRRcap:
9ba075a6 2211 case 0x200 ... 0x2ff:
ff53604b 2212 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2213 case 0xcd: /* fsb frequency */
609e36d3 2214 msr_info->data = 3;
15c4a640 2215 break;
7b914098
JS		 2216 /*
2217 * MSR_EBC_FREQUENCY_ID
2218 * Conservative value valid for even the basic CPU models.
2219 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2220 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2221 * and 266MHz for model 3, or 4. Set Core Clock
2222 * Frequency to System Bus Frequency Ratio to 1 (bits
2223 * 31:24) even though these are only valid for CPU
2224 * models > 2, however guests may end up dividing or
2225 * multiplying by zero otherwise.
2226 */
2227 case MSR_EBC_FREQUENCY_ID:
609e36d3 2228 msr_info->data = 1 << 24;
7b914098 2229 break;
15c4a640 2230 case MSR_IA32_APICBASE:
609e36d3 2231 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2232 break;
0105d1a5 2233 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2234 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2235 break;
a3e06bbe 2236 case MSR_IA32_TSCDEADLINE:
609e36d3 2237 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2238 break;
ba904635 2239 case MSR_IA32_TSC_ADJUST:
609e36d3 2240 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2241 break;
15c4a640 2242 case MSR_IA32_MISC_ENABLE:
609e36d3 2243 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2244 break;
64d60670
PB		 2245 case MSR_IA32_SMBASE:
2246 if (!msr_info->host_initiated)
2247 return 1;
2248 msr_info->data = vcpu->arch.smbase;
15c4a640 2249 break;
847f0ad8
AG		 2250 case MSR_IA32_PERF_STATUS:
2251 /* TSC increment by tick */
609e36d3 2252 msr_info->data = 1000ULL;
847f0ad8 2253 /* CPU multiplier */
b0996ae4 2254 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2255 break;
15c4a640 2256 case MSR_EFER:
609e36d3 2257 msr_info->data = vcpu->arch.efer;
15c4a640 2258 break;
18068523 2259 case MSR_KVM_WALL_CLOCK:
11c6bffa 2260 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2261 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2262 break;
2263 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2264 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2265 msr_info->data = vcpu->arch.time;
18068523 2266 break;
344d9588 2267 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2268 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2269 break;
c9aaa895 2270 case MSR_KVM_STEAL_TIME:
609e36d3 2271 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2272 break;
1d92128f 2273 case MSR_KVM_PV_EOI_EN:
609e36d3 2274 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2275 break;
890ca9ae
HY		 2276 case MSR_IA32_P5_MC_ADDR:
2277 case MSR_IA32_P5_MC_TYPE:
2278 case MSR_IA32_MCG_CAP:
2279 case MSR_IA32_MCG_CTL:
2280 case MSR_IA32_MCG_STATUS:
81760dcc 2281 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2282 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2283 case MSR_K7_CLK_CTL:
2284 /*
2285 * Provide expected ramp-up count for K7. All other
2286 * are set to zero, indicating minimum divisors for
2287 * every field.
2288 *
2289 * This prevents guest kernels on AMD host with CPU
2290 * type 6, model 8 and higher from exploding due to
2291 * the rdmsr failing.
2292 */
609e36d3 2293 msr_info->data = 0x20000000;
84e0cefa 2294 break;
55cd8e5a 2295 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2296 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2297 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2298 return kvm_hv_get_msr_common(vcpu,
2299 msr_info->index, &msr_info->data);
55cd8e5a 2300 break;
91c9c3ed 2301 case MSR_IA32_BBL_CR_CTL3:
2302 /* This legacy MSR exists but isn't fully documented in current
2303 * silicon. It is however accessed by winxp in very narrow
2304 * scenarios where it sets bit #19, itself documented as
2305 * a "reserved" bit. Best effort attempt to source coherent
2306 * read data here should the balance of the register be
2307 * interpreted by the guest:
2308 *
2309 * L2 cache control register 3: 64GB range, 256KB size,
2310 * enabled, latency 0x1, configured
2311 */
609e36d3 2312 msr_info->data = 0xbe702111;
91c9c3ed 2313 break;
2b036c6b
BO		 2314 case MSR_AMD64_OSVW_ID_LENGTH:
2315 if (!guest_cpuid_has_osvw(vcpu))
2316 return 1;
609e36d3 2317 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2318 break;
2319 case MSR_AMD64_OSVW_STATUS:
2320 if (!guest_cpuid_has_osvw(vcpu))
2321 return 1;
609e36d3 2322 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2323 break;
15c4a640 2324 default:
c6702c9d 2325 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2326 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2327 if (!ignore_msrs) {
609e36d3 2328 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2329 return 1;
2330 } else {
609e36d3
PB		 2331 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2332 msr_info->data = 0;
ed85c068
AP		 2333 }
2334 break;
15c4a640 2335 }
15c4a640
CO		 2336 return 0;
2337}
2338EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2339
313a3dc7
CO		 2340/*
2341 * Read or write a bunch of msrs. All parameters are kernel addresses.
2342 *
2343 * @return number of msrs set successfully.
2344 */
2345static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2346 struct kvm_msr_entry *entries,
2347 int (*do_msr)(struct kvm_vcpu *vcpu,
2348 unsigned index, u64 *data))
2349{
f656ce01 2350 int i, idx;
313a3dc7 2351
f656ce01 2352 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2353 for (i = 0; i < msrs->nmsrs; ++i)
2354 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2355 break;
f656ce01 2356 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2357
313a3dc7
CO		 2358 return i;
2359}
2360
2361/*
2362 * Read or write a bunch of msrs. Parameters are user addresses.
2363 *
2364 * @return number of msrs set successfully.
2365 */
2366static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2367 int (*do_msr)(struct kvm_vcpu *vcpu,
2368 unsigned index, u64 *data),
2369 int writeback)
2370{
2371 struct kvm_msrs msrs;
2372 struct kvm_msr_entry *entries;
2373 int r, n;
2374 unsigned size;
2375
2376 r = -EFAULT;
2377 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2378 goto out;
2379
2380 r = -E2BIG;
2381 if (msrs.nmsrs >= MAX_IO_MSRS)
2382 goto out;
2383
313a3dc7 2384 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2385 entries = memdup_user(user_msrs->entries, size);
2386 if (IS_ERR(entries)) {
2387 r = PTR_ERR(entries);
313a3dc7 2388 goto out;
ff5c2c03 2389 }
313a3dc7
CO		 2390
2391 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2392 if (r < 0)
2393 goto out_free;
2394
2395 r = -EFAULT;
2396 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2397 goto out_free;
2398
2399 r = n;
2400
2401out_free:
7a73c028 2402 kfree(entries);
313a3dc7
CO		 2403out:
2404 return r;
2405}
2406
784aa3d7 2407int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2408{
2409 int r;
2410
2411 switch (ext) {
2412 case KVM_CAP_IRQCHIP:
2413 case KVM_CAP_HLT:
2414 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2415 case KVM_CAP_SET_TSS_ADDR:
07716717 2416 case KVM_CAP_EXT_CPUID:
9c15bb1d 2417 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2418 case KVM_CAP_CLOCKSOURCE:
7837699f 2419 case KVM_CAP_PIT:
a28e4f5a 2420 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2421 case KVM_CAP_MP_STATE:
ed848624 2422 case KVM_CAP_SYNC_MMU:
a355c85c 2423 case KVM_CAP_USER_NMI:
52d939a0 2424 case KVM_CAP_REINJECT_CONTROL:
4925663a 2425 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2426 case KVM_CAP_IOEVENTFD:
f848a5a8 2427 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2428 case KVM_CAP_PIT2:
e9f42757 2429 case KVM_CAP_PIT_STATE2:
b927a3ce 2430 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2431 case KVM_CAP_XEN_HVM:
afbcf7ab 2432 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2433 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2434 case KVM_CAP_HYPERV:
10388a07 2435 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2436 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2437 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2438 case KVM_CAP_DEBUGREGS:
d2be1651 2439 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2440 case KVM_CAP_XSAVE:
344d9588 2441 case KVM_CAP_ASYNC_PF:
92a1f12d 2442 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2443 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2444 case KVM_CAP_READONLY_MEM:
5f66b620 2445 case KVM_CAP_HYPERV_TIME:
100943c5 2446 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2447 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2448 case KVM_CAP_ENABLE_CAP_VM:
2449 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2450 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2451 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2452#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2453 case KVM_CAP_ASSIGN_DEV_IRQ:
2454 case KVM_CAP_PCI_2_3:
2455#endif
018d00d2
ZX		 2456 r = 1;
2457 break;
6d396b55
PB		 2458 case KVM_CAP_X86_SMM:
2459 /* SMBASE is usually relocated above 1M on modern chipsets,
2460 * and SMM handlers might indeed rely on 4G segment limits,
2461 * so do not report SMM to be available if real mode is
2462 * emulated via vm86 mode. Still, do not go to great lengths
2463 * to avoid userspace's usage of the feature, because it is a
2464 * fringe case that is not enabled except via specific settings
2465 * of the module parameters.
2466 */
2467 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2468 break;
542472b5
LV		 2469 case KVM_CAP_COALESCED_MMIO:
2470 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2471 break;
774ead3a
AK		 2472 case KVM_CAP_VAPIC:
2473 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2474 break;
f725230a 2475 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2476 r = KVM_SOFT_MAX_VCPUS;
2477 break;
2478 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2479 r = KVM_MAX_VCPUS;
2480 break;
a988b910 2481 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2482 r = KVM_USER_MEM_SLOTS;
a988b910 2483 break;
a68a6a72
MT		 2484 case KVM_CAP_PV_MMU: /* obsolete */
2485 r = 0;
2f333bcb 2486 break;
4cee4b72 2487#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2488 case KVM_CAP_IOMMU:
a1b60c1c 2489 r = iommu_present(&pci_bus_type);
62c476c7 2490 break;
4cee4b72 2491#endif
890ca9ae
HY		 2492 case KVM_CAP_MCE:
2493 r = KVM_MAX_MCE_BANKS;
2494 break;
2d5b5a66
SY		 2495 case KVM_CAP_XCRS:
2496 r = cpu_has_xsave;
2497 break;
92a1f12d
JR		 2498 case KVM_CAP_TSC_CONTROL:
2499 r = kvm_has_tsc_control;
2500 break;
018d00d2
ZX		 2501 default:
2502 r = 0;
2503 break;
2504 }
2505 return r;
2506
2507}
2508
043405e1
CO		 2509long kvm_arch_dev_ioctl(struct file *filp,
2510 unsigned int ioctl, unsigned long arg)
2511{
2512 void __user *argp = (void __user *)arg;
2513 long r;
2514
2515 switch (ioctl) {
2516 case KVM_GET_MSR_INDEX_LIST: {
2517 struct kvm_msr_list __user *user_msr_list = argp;
2518 struct kvm_msr_list msr_list;
2519 unsigned n;
2520
2521 r = -EFAULT;
2522 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2523 goto out;
2524 n = msr_list.nmsrs;
62ef68bb 2525 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2526 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2527 goto out;
2528 r = -E2BIG;
e125e7b6 2529 if (n < msr_list.nmsrs)
043405e1
CO		 2530 goto out;
2531 r = -EFAULT;
2532 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2533 num_msrs_to_save * sizeof(u32)))
2534 goto out;
e125e7b6 2535 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2536 &emulated_msrs,
62ef68bb 2537 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2538 goto out;
2539 r = 0;
2540 break;
2541 }
9c15bb1d
BP		 2542 case KVM_GET_SUPPORTED_CPUID:
2543 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2544 struct kvm_cpuid2 __user *cpuid_arg = argp;
2545 struct kvm_cpuid2 cpuid;
2546
2547 r = -EFAULT;
2548 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2549 goto out;
9c15bb1d
BP		 2550
2551 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2552 ioctl);
674eea0f
AK		 2553 if (r)
2554 goto out;
2555
2556 r = -EFAULT;
2557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2558 goto out;
2559 r = 0;
2560 break;
2561 }
890ca9ae
HY		 2562 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2563 u64 mce_cap;
2564
2565 mce_cap = KVM_MCE_CAP_SUPPORTED;
2566 r = -EFAULT;
2567 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2568 goto out;
2569 r = 0;
2570 break;
2571 }
043405e1
CO		 2572 default:
2573 r = -EINVAL;
2574 }
2575out:
2576 return r;
2577}
2578
f5f48ee1
SY		 2579static void wbinvd_ipi(void *garbage)
2580{
2581 wbinvd();
2582}
2583
2584static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2585{
e0f0bbc5 2586 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2587}
2588
313a3dc7
CO		 2589void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2590{
f5f48ee1
SY		 2591 /* Address WBINVD may be executed by guest */
2592 if (need_emulate_wbinvd(vcpu)) {
2593 if (kvm_x86_ops->has_wbinvd_exit())
2594 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2595 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2596 smp_call_function_single(vcpu->cpu,
2597 wbinvd_ipi, NULL, 1);
2598 }
2599
313a3dc7 2600 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2601
0dd6a6ed
ZA		 2602 /* Apply any externally detected TSC adjustments (due to suspend) */
2603 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2604 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2605 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2606 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2607 }
8f6055cb 2608
48434c20 2609 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2610 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2611 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2612 if (tsc_delta < 0)
2613 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2614 if (check_tsc_unstable()) {
b183aa58
ZA		 2615 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2616 vcpu->arch.last_guest_tsc);
2617 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2618 vcpu->arch.tsc_catchup = 1;
c285545f 2619 }
d98d07ca
MT		 2620 /*
2621 * On a host with synchronized TSC, there is no need to update
2622 * kvmclock on vcpu->cpu migration
2623 */
2624 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2625 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2626 if (vcpu->cpu != cpu)
2627 kvm_migrate_timers(vcpu);
e48672fa 2628 vcpu->cpu = cpu;
6b7d7e76 2629 }
c9aaa895
GC		 2630
2631 accumulate_steal_time(vcpu);
2632 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2633}
2634
2635void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2636{
02daab21 2637 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2638 kvm_put_guest_fpu(vcpu);
4ea1636b 2639 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2640}
2641
313a3dc7
CO		 2642static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2643 struct kvm_lapic_state *s)
2644{
5a71785d 2645 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2646 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2647
2648 return 0;
2649}
2650
2651static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2652 struct kvm_lapic_state *s)
2653{
64eb0620 2654 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2655 update_cr8_intercept(vcpu);
313a3dc7
CO		 2656
2657 return 0;
2658}
2659
f77bc6a4
ZX		 2660static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2661 struct kvm_interrupt *irq)
2662{
02cdb50f 2663 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2664 return -EINVAL;
1c1a9ce9
SR		 2665
2666 if (!irqchip_in_kernel(vcpu->kvm)) {
2667 kvm_queue_interrupt(vcpu, irq->irq, false);
2668 kvm_make_request(KVM_REQ_EVENT, vcpu);
2669 return 0;
2670 }
2671
2672 /*
2673 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2674 * fail for in-kernel 8259.
2675 */
2676 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2677 return -ENXIO;
f77bc6a4 2678
1c1a9ce9
SR		 2679 if (vcpu->arch.pending_external_vector != -1)
2680 return -EEXIST;
f77bc6a4 2681
1c1a9ce9 2682 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2683 return 0;
2684}
2685
c4abb7c9
JK		 2686static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2687{
c4abb7c9 2688 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2689
2690 return 0;
2691}
2692
f077825a
PB		 2693static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2694{
64d60670
PB		 2695 kvm_make_request(KVM_REQ_SMI, vcpu);
2696
f077825a
PB		 2697 return 0;
2698}
2699
b209749f
AK		 2700static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2701 struct kvm_tpr_access_ctl *tac)
2702{
2703 if (tac->flags)
2704 return -EINVAL;
2705 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2706 return 0;
2707}
2708
890ca9ae
HY		 2709static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2710 u64 mcg_cap)
2711{
2712 int r;
2713 unsigned bank_num = mcg_cap & 0xff, bank;
2714
2715 r = -EINVAL;
a9e38c3e 2716 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2717 goto out;
2718 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2719 goto out;
2720 r = 0;
2721 vcpu->arch.mcg_cap = mcg_cap;
2722 /* Init IA32_MCG_CTL to all 1s */
2723 if (mcg_cap & MCG_CTL_P)
2724 vcpu->arch.mcg_ctl = ~(u64)0;
2725 /* Init IA32_MCi_CTL to all 1s */
2726 for (bank = 0; bank < bank_num; bank++)
2727 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2728out:
2729 return r;
2730}
2731
2732static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2733 struct kvm_x86_mce *mce)
2734{
2735 u64 mcg_cap = vcpu->arch.mcg_cap;
2736 unsigned bank_num = mcg_cap & 0xff;
2737 u64 *banks = vcpu->arch.mce_banks;
2738
2739 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2740 return -EINVAL;
2741 /*
2742 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2743 * reporting is disabled
2744 */
2745 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2746 vcpu->arch.mcg_ctl != ~(u64)0)
2747 return 0;
2748 banks += 4 * mce->bank;
2749 /*
2750 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2751 * reporting is disabled for the bank
2752 */
2753 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2754 return 0;
2755 if (mce->status & MCI_STATUS_UC) {
2756 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2757 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2758 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2759 return 0;
2760 }
2761 if (banks[1] & MCI_STATUS_VAL)
2762 mce->status |= MCI_STATUS_OVER;
2763 banks[2] = mce->addr;
2764 banks[3] = mce->misc;
2765 vcpu->arch.mcg_status = mce->mcg_status;
2766 banks[1] = mce->status;
2767 kvm_queue_exception(vcpu, MC_VECTOR);
2768 } else if (!(banks[1] & MCI_STATUS_VAL)
2769 || !(banks[1] & MCI_STATUS_UC)) {
2770 if (banks[1] & MCI_STATUS_VAL)
2771 mce->status |= MCI_STATUS_OVER;
2772 banks[2] = mce->addr;
2773 banks[3] = mce->misc;
2774 banks[1] = mce->status;
2775 } else
2776 banks[1] |= MCI_STATUS_OVER;
2777 return 0;
2778}
2779
3cfc3092
JK		 2780static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2781 struct kvm_vcpu_events *events)
2782{
7460fb4a 2783 process_nmi(vcpu);
03b82a30
JK		 2784 events->exception.injected =
2785 vcpu->arch.exception.pending &&
2786 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2787 events->exception.nr = vcpu->arch.exception.nr;
2788 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2789 events->exception.pad = 0;
3cfc3092
JK		 2790 events->exception.error_code = vcpu->arch.exception.error_code;
2791
03b82a30
JK		 2792 events->interrupt.injected =
2793 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2794 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2795 events->interrupt.soft = 0;
37ccdcbe 2796 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2797
2798 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2799 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2800 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2801 events->nmi.pad = 0;
3cfc3092 2802
66450a21 2803 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2804
f077825a
PB		 2805 events->smi.smm = is_smm(vcpu);
2806 events->smi.pending = vcpu->arch.smi_pending;
2807 events->smi.smm_inside_nmi =
2808 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2809 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2810
dab4b911 2811 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2812 | KVM_VCPUEVENT_VALID_SHADOW
2813 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2814 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2815}
2816
2817static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2818 struct kvm_vcpu_events *events)
2819{
dab4b911 2820 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2821 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2822 | KVM_VCPUEVENT_VALID_SHADOW
2823 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2824 return -EINVAL;
2825
7460fb4a 2826 process_nmi(vcpu);
3cfc3092
JK		 2827 vcpu->arch.exception.pending = events->exception.injected;
2828 vcpu->arch.exception.nr = events->exception.nr;
2829 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2830 vcpu->arch.exception.error_code = events->exception.error_code;
2831
2832 vcpu->arch.interrupt.pending = events->interrupt.injected;
2833 vcpu->arch.interrupt.nr = events->interrupt.nr;
2834 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2835 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2836 kvm_x86_ops->set_interrupt_shadow(vcpu,
2837 events->interrupt.shadow);
3cfc3092
JK		 2838
2839 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2840 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2841 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2842 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2843
66450a21
JK		 2844 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2845 kvm_vcpu_has_lapic(vcpu))
2846 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2847
f077825a
PB		 2848 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2849 if (events->smi.smm)
2850 vcpu->arch.hflags |= HF_SMM_MASK;
2851 else
2852 vcpu->arch.hflags &= ~HF_SMM_MASK;
2853 vcpu->arch.smi_pending = events->smi.pending;
2854 if (events->smi.smm_inside_nmi)
2855 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2856 else
2857 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2858 if (kvm_vcpu_has_lapic(vcpu)) {
2859 if (events->smi.latched_init)
2860 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2861 else
2862 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2863 }
2864 }
2865
3842d135
AK		 2866 kvm_make_request(KVM_REQ_EVENT, vcpu);
2867
3cfc3092
JK		 2868 return 0;
2869}
2870
a1efbe77
JK		 2871static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2872 struct kvm_debugregs *dbgregs)
2873{
73aaf249
JK		 2874 unsigned long val;
2875
a1efbe77 2876 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2877 kvm_get_dr(vcpu, 6, &val);
73aaf249 2878 dbgregs->dr6 = val;
a1efbe77
JK		 2879 dbgregs->dr7 = vcpu->arch.dr7;
2880 dbgregs->flags = 0;
97e69aa6 2881 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2882}
2883
2884static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2885 struct kvm_debugregs *dbgregs)
2886{
2887 if (dbgregs->flags)
2888 return -EINVAL;
2889
a1efbe77 2890 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2891 kvm_update_dr0123(vcpu);
a1efbe77 2892 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2893 kvm_update_dr6(vcpu);
a1efbe77 2894 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2895 kvm_update_dr7(vcpu);
a1efbe77 2896
a1efbe77
JK		 2897 return 0;
2898}
2899
df1daba7
PB		 2900#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2901
2902static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2903{
c47ada30 2904 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2905 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2906 u64 valid;
2907
2908 /*
2909 * Copy legacy XSAVE area, to avoid complications with CPUID
2910 * leaves 0 and 1 in the loop below.
2911 */
2912 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2913
2914 /* Set XSTATE_BV */
2915 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2916
2917 /*
2918 * Copy each region from the possibly compacted offset to the
2919 * non-compacted offset.
2920 */
2921 valid = xstate_bv & ~XSTATE_FPSSE;
2922 while (valid) {
2923 u64 feature = valid & -valid;
2924 int index = fls64(feature) - 1;
2925 void *src = get_xsave_addr(xsave, feature);
2926
2927 if (src) {
2928 u32 size, offset, ecx, edx;
2929 cpuid_count(XSTATE_CPUID, index,
2930 &size, &offset, &ecx, &edx);
2931 memcpy(dest + offset, src, size);
2932 }
2933
2934 valid -= feature;
2935 }
2936}
2937
2938static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2939{
c47ada30 2940 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2941 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2942 u64 valid;
2943
2944 /*
2945 * Copy legacy XSAVE area, to avoid complications with CPUID
2946 * leaves 0 and 1 in the loop below.
2947 */
2948 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2949
2950 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2951 xsave->header.xfeatures = xstate_bv;
df1daba7 2952 if (cpu_has_xsaves)
3a54450b 2953 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2954
2955 /*
2956 * Copy each region from the non-compacted offset to the
2957 * possibly compacted offset.
2958 */
2959 valid = xstate_bv & ~XSTATE_FPSSE;
2960 while (valid) {
2961 u64 feature = valid & -valid;
2962 int index = fls64(feature) - 1;
2963 void *dest = get_xsave_addr(xsave, feature);
2964
2965 if (dest) {
2966 u32 size, offset, ecx, edx;
2967 cpuid_count(XSTATE_CPUID, index,
2968 &size, &offset, &ecx, &edx);
2969 memcpy(dest, src + offset, size);
ee4100da 2970 }
df1daba7
PB		 2971
2972 valid -= feature;
2973 }
2974}
2975
2d5b5a66
SY		 2976static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2977 struct kvm_xsave *guest_xsave)
2978{
4344ee98 2979 if (cpu_has_xsave) {
df1daba7
PB		 2980 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2981 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2982 } else {
2d5b5a66 2983 memcpy(guest_xsave->region,
7366ed77 2984 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2985 sizeof(struct fxregs_state));
2d5b5a66
SY		 2986 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2987 XSTATE_FPSSE;
2988 }
2989}
2990
2991static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2992 struct kvm_xsave *guest_xsave)
2993{
2994 u64 xstate_bv =
2995 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2996
d7876f1b
PB		 2997 if (cpu_has_xsave) {
2998 /*
2999 * Here we allow setting states that are not present in
3000 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3001 * with old userspace.
3002 */
4ff41732 3003 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3004 return -EINVAL;
df1daba7 3005 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3006 } else {
2d5b5a66
SY		 3007 if (xstate_bv & ~XSTATE_FPSSE)
3008 return -EINVAL;
7366ed77 3009 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3010 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3011 }
3012 return 0;
3013}
3014
3015static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3016 struct kvm_xcrs *guest_xcrs)
3017{
3018 if (!cpu_has_xsave) {
3019 guest_xcrs->nr_xcrs = 0;
3020 return;
3021 }
3022
3023 guest_xcrs->nr_xcrs = 1;
3024 guest_xcrs->flags = 0;
3025 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3026 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3027}
3028
3029static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031{
3032 int i, r = 0;
3033
3034 if (!cpu_has_xsave)
3035 return -EINVAL;
3036
3037 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3038 return -EINVAL;
3039
3040 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3041 /* Only support XCR0 currently */
c67a04cb 3042 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3043 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3044 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3045 break;
3046 }
3047 if (r)
3048 r = -EINVAL;
3049 return r;
3050}
3051
1c0b28c2
EM		 3052/*
3053 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3054 * stopped by the hypervisor. This function will be called from the host only.
3055 * EINVAL is returned when the host attempts to set the flag for a guest that
3056 * does not support pv clocks.
3057 */
3058static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3059{
0b79459b 3060 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3061 return -EINVAL;
51d59c6b 3062 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3064 return 0;
3065}
3066
313a3dc7
CO		 3067long kvm_arch_vcpu_ioctl(struct file *filp,
3068 unsigned int ioctl, unsigned long arg)
3069{
3070 struct kvm_vcpu *vcpu = filp->private_data;
3071 void __user *argp = (void __user *)arg;
3072 int r;
d1ac91d8
AK		 3073 union {
3074 struct kvm_lapic_state *lapic;
3075 struct kvm_xsave *xsave;
3076 struct kvm_xcrs *xcrs;
3077 void *buffer;
3078 } u;
3079
3080 u.buffer = NULL;
313a3dc7
CO		 3081 switch (ioctl) {
3082 case KVM_GET_LAPIC: {
2204ae3c
MT		 3083 r = -EINVAL;
3084 if (!vcpu->arch.apic)
3085 goto out;
d1ac91d8 3086 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3087
b772ff36 3088 r = -ENOMEM;
d1ac91d8 3089 if (!u.lapic)
b772ff36 3090 goto out;
d1ac91d8 3091 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3092 if (r)
3093 goto out;
3094 r = -EFAULT;
d1ac91d8 3095 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3096 goto out;
3097 r = 0;
3098 break;
3099 }
3100 case KVM_SET_LAPIC: {
2204ae3c
MT		 3101 r = -EINVAL;
3102 if (!vcpu->arch.apic)
3103 goto out;
ff5c2c03 3104 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3105 if (IS_ERR(u.lapic))
3106 return PTR_ERR(u.lapic);
ff5c2c03 3107
d1ac91d8 3108 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3109 break;
3110 }
f77bc6a4
ZX		 3111 case KVM_INTERRUPT: {
3112 struct kvm_interrupt irq;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&irq, argp, sizeof irq))
3116 goto out;
3117 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3118 break;
3119 }
c4abb7c9
JK		 3120 case KVM_NMI: {
3121 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3122 break;
3123 }
f077825a
PB		 3124 case KVM_SMI: {
3125 r = kvm_vcpu_ioctl_smi(vcpu);
3126 break;
3127 }
313a3dc7
CO		 3128 case KVM_SET_CPUID: {
3129 struct kvm_cpuid __user *cpuid_arg = argp;
3130 struct kvm_cpuid cpuid;
3131
3132 r = -EFAULT;
3133 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3134 goto out;
3135 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3136 break;
3137 }
07716717
DK		 3138 case KVM_SET_CPUID2: {
3139 struct kvm_cpuid2 __user *cpuid_arg = argp;
3140 struct kvm_cpuid2 cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3146 cpuid_arg->entries);
07716717
DK		 3147 break;
3148 }
3149 case KVM_GET_CPUID2: {
3150 struct kvm_cpuid2 __user *cpuid_arg = argp;
3151 struct kvm_cpuid2 cpuid;
3152
3153 r = -EFAULT;
3154 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3155 goto out;
3156 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3157 cpuid_arg->entries);
07716717
DK		 3158 if (r)
3159 goto out;
3160 r = -EFAULT;
3161 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3162 goto out;
3163 r = 0;
3164 break;
3165 }
313a3dc7 3166 case KVM_GET_MSRS:
609e36d3 3167 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3168 break;
3169 case KVM_SET_MSRS:
3170 r = msr_io(vcpu, argp, do_set_msr, 0);
3171 break;
b209749f
AK		 3172 case KVM_TPR_ACCESS_REPORTING: {
3173 struct kvm_tpr_access_ctl tac;
3174
3175 r = -EFAULT;
3176 if (copy_from_user(&tac, argp, sizeof tac))
3177 goto out;
3178 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3179 if (r)
3180 goto out;
3181 r = -EFAULT;
3182 if (copy_to_user(argp, &tac, sizeof tac))
3183 goto out;
3184 r = 0;
3185 break;
3186 };
b93463aa
AK		 3187 case KVM_SET_VAPIC_ADDR: {
3188 struct kvm_vapic_addr va;
3189
3190 r = -EINVAL;
35754c98 3191 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3192 goto out;
3193 r = -EFAULT;
3194 if (copy_from_user(&va, argp, sizeof va))
3195 goto out;
fda4e2e8 3196 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3197 break;
3198 }
890ca9ae
HY		 3199 case KVM_X86_SETUP_MCE: {
3200 u64 mcg_cap;
3201
3202 r = -EFAULT;
3203 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3204 goto out;
3205 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3206 break;
3207 }
3208 case KVM_X86_SET_MCE: {
3209 struct kvm_x86_mce mce;
3210
3211 r = -EFAULT;
3212 if (copy_from_user(&mce, argp, sizeof mce))
3213 goto out;
3214 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3215 break;
3216 }
3cfc3092
JK		 3217 case KVM_GET_VCPU_EVENTS: {
3218 struct kvm_vcpu_events events;
3219
3220 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3221
3222 r = -EFAULT;
3223 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3224 break;
3225 r = 0;
3226 break;
3227 }
3228 case KVM_SET_VCPU_EVENTS: {
3229 struct kvm_vcpu_events events;
3230
3231 r = -EFAULT;
3232 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3233 break;
3234
3235 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3236 break;
3237 }
a1efbe77
JK		 3238 case KVM_GET_DEBUGREGS: {
3239 struct kvm_debugregs dbgregs;
3240
3241 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3242
3243 r = -EFAULT;
3244 if (copy_to_user(argp, &dbgregs,
3245 sizeof(struct kvm_debugregs)))
3246 break;
3247 r = 0;
3248 break;
3249 }
3250 case KVM_SET_DEBUGREGS: {
3251 struct kvm_debugregs dbgregs;
3252
3253 r = -EFAULT;
3254 if (copy_from_user(&dbgregs, argp,
3255 sizeof(struct kvm_debugregs)))
3256 break;
3257
3258 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3259 break;
3260 }
2d5b5a66 3261 case KVM_GET_XSAVE: {
d1ac91d8 3262 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3263 r = -ENOMEM;
d1ac91d8 3264 if (!u.xsave)
2d5b5a66
SY		 3265 break;
3266
d1ac91d8 3267 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3268
3269 r = -EFAULT;
d1ac91d8 3270 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3271 break;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_SET_XSAVE: {
ff5c2c03 3276 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3277 if (IS_ERR(u.xsave))
3278 return PTR_ERR(u.xsave);
2d5b5a66 3279
d1ac91d8 3280 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3281 break;
3282 }
3283 case KVM_GET_XCRS: {
d1ac91d8 3284 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3285 r = -ENOMEM;
d1ac91d8 3286 if (!u.xcrs)
2d5b5a66
SY		 3287 break;
3288
d1ac91d8 3289 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3290
3291 r = -EFAULT;
d1ac91d8 3292 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3293 sizeof(struct kvm_xcrs)))
3294 break;
3295 r = 0;
3296 break;
3297 }
3298 case KVM_SET_XCRS: {
ff5c2c03 3299 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3300 if (IS_ERR(u.xcrs))
3301 return PTR_ERR(u.xcrs);
2d5b5a66 3302
d1ac91d8 3303 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3304 break;
3305 }
92a1f12d
JR		 3306 case KVM_SET_TSC_KHZ: {
3307 u32 user_tsc_khz;
3308
3309 r = -EINVAL;
92a1f12d
JR		 3310 user_tsc_khz = (u32)arg;
3311
3312 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3313 goto out;
3314
cc578287
ZA		 3315 if (user_tsc_khz == 0)
3316 user_tsc_khz = tsc_khz;
3317
3318 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3319
3320 r = 0;
3321 goto out;
3322 }
3323 case KVM_GET_TSC_KHZ: {
cc578287 3324 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3325 goto out;
3326 }
1c0b28c2
EM		 3327 case KVM_KVMCLOCK_CTRL: {
3328 r = kvm_set_guest_paused(vcpu);
3329 goto out;
3330 }
313a3dc7
CO		 3331 default:
3332 r = -EINVAL;
3333 }
3334out:
d1ac91d8 3335 kfree(u.buffer);
313a3dc7
CO		 3336 return r;
3337}
3338
5b1c1493
CO		 3339int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3340{
3341 return VM_FAULT_SIGBUS;
3342}
3343
1fe779f8
CO		 3344static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3345{
3346 int ret;
3347
3348 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3349 return -EINVAL;
1fe779f8
CO		 3350 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3351 return ret;
3352}
3353
b927a3ce
SY		 3354static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3355 u64 ident_addr)
3356{
3357 kvm->arch.ept_identity_map_addr = ident_addr;
3358 return 0;
3359}
3360
1fe779f8
CO		 3361static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3362 u32 kvm_nr_mmu_pages)
3363{
3364 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3365 return -EINVAL;
3366
79fac95e 3367 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3368
3369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3371
79fac95e 3372 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3373 return 0;
3374}
3375
3376static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3377{
39de71ec 3378 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3379}
3380
1fe779f8
CO		 3381static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3382{
3383 int r;
3384
3385 r = 0;
3386 switch (chip->chip_id) {
3387 case KVM_IRQCHIP_PIC_MASTER:
3388 memcpy(&chip->chip.pic,
3389 &pic_irqchip(kvm)->pics[0],
3390 sizeof(struct kvm_pic_state));
3391 break;
3392 case KVM_IRQCHIP_PIC_SLAVE:
3393 memcpy(&chip->chip.pic,
3394 &pic_irqchip(kvm)->pics[1],
3395 sizeof(struct kvm_pic_state));
3396 break;
3397 case KVM_IRQCHIP_IOAPIC:
eba0226b 3398 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3399 break;
3400 default:
3401 r = -EINVAL;
3402 break;
3403 }
3404 return r;
3405}
3406
3407static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3408{
3409 int r;
3410
3411 r = 0;
3412 switch (chip->chip_id) {
3413 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3414 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3415 memcpy(&pic_irqchip(kvm)->pics[0],
3416 &chip->chip.pic,
3417 sizeof(struct kvm_pic_state));
f4f51050 3418 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3419 break;
3420 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3421 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3422 memcpy(&pic_irqchip(kvm)->pics[1],
3423 &chip->chip.pic,
3424 sizeof(struct kvm_pic_state));
f4f51050 3425 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3426 break;
3427 case KVM_IRQCHIP_IOAPIC:
eba0226b 3428 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3429 break;
3430 default:
3431 r = -EINVAL;
3432 break;
3433 }
3434 kvm_pic_update_irq(pic_irqchip(kvm));
3435 return r;
3436}
3437
e0f63cb9
SY		 3438static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3439{
3440 int r = 0;
3441
894a9c55 3442 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3443 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3444 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3445 return r;
3446}
3447
3448static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3449{
3450 int r = 0;
3451
894a9c55 3452 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3453 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3454 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3456 return r;
3457}
3458
3459static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3460{
3461 int r = 0;
3462
3463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3464 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3465 sizeof(ps->channels));
3466 ps->flags = kvm->arch.vpit->pit_state.flags;
3467 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3468 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3469 return r;
3470}
3471
3472static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3473{
3474 int r = 0, start = 0;
3475 u32 prev_legacy, cur_legacy;
3476 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3477 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3478 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3479 if (!prev_legacy && cur_legacy)
3480 start = 1;
3481 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3482 sizeof(kvm->arch.vpit->pit_state.channels));
3483 kvm->arch.vpit->pit_state.flags = ps->flags;
3484 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3485 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3486 return r;
3487}
3488
52d939a0
MT		 3489static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3490 struct kvm_reinject_control *control)
3491{
3492 if (!kvm->arch.vpit)
3493 return -ENXIO;
894a9c55 3494 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3495 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3497 return 0;
3498}
3499
95d4c16c 3500/**
60c34612
TY		 3501 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3502 * @kvm: kvm instance
3503 * @log: slot id and address to which we copy the log
95d4c16c 3504 *
e108ff2f
PB		 3505 * Steps 1-4 below provide general overview of dirty page logging. See
3506 * kvm_get_dirty_log_protect() function description for additional details.
3507 *
3508 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3509 * always flush the TLB (step 4) even if previous step failed and the dirty
3510 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3511 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3512 * writes will be marked dirty for next log read.
95d4c16c 3513 *
60c34612
TY		 3514 * 1. Take a snapshot of the bit and clear it if needed.
3515 * 2. Write protect the corresponding page.
e108ff2f
PB		 3516 * 3. Copy the snapshot to the userspace.
3517 * 4. Flush TLB's if needed.
5bb064dc 3518 */
60c34612 3519int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3520{
60c34612 3521 bool is_dirty = false;
e108ff2f 3522 int r;
5bb064dc 3523
79fac95e 3524 mutex_lock(&kvm->slots_lock);
5bb064dc 3525
88178fd4
KH		 3526 /*
3527 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3528 */
3529 if (kvm_x86_ops->flush_log_dirty)
3530 kvm_x86_ops->flush_log_dirty(kvm);
3531
e108ff2f 3532 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3533
3534 /*
3535 * All the TLBs can be flushed out of mmu lock, see the comments in
3536 * kvm_mmu_slot_remove_write_access().
3537 */
e108ff2f 3538 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3539 if (is_dirty)
3540 kvm_flush_remote_tlbs(kvm);
3541
79fac95e 3542 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3543 return r;
3544}
3545
aa2fbe6d
YZ		 3546int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3547 bool line_status)
23d43cf9
CD		 3548{
3549 if (!irqchip_in_kernel(kvm))
3550 return -ENXIO;
3551
3552 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3553 irq_event->irq, irq_event->level,
3554 line_status);
23d43cf9
CD		 3555 return 0;
3556}
3557
90de4a18
NA		 3558static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3559 struct kvm_enable_cap *cap)
3560{
3561 int r;
3562
3563 if (cap->flags)
3564 return -EINVAL;
3565
3566 switch (cap->cap) {
3567 case KVM_CAP_DISABLE_QUIRKS:
3568 kvm->arch.disabled_quirks = cap->args[0];
3569 r = 0;
3570 break;
49df6397
SR		 3571 case KVM_CAP_SPLIT_IRQCHIP: {
3572 mutex_lock(&kvm->lock);
b053b2ae
SR		 3573 r = -EINVAL;
3574 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3575 goto split_irqchip_unlock;
49df6397
SR		 3576 r = -EEXIST;
3577 if (irqchip_in_kernel(kvm))
3578 goto split_irqchip_unlock;
3579 if (atomic_read(&kvm->online_vcpus))
3580 goto split_irqchip_unlock;
3581 r = kvm_setup_empty_irq_routing(kvm);
3582 if (r)
3583 goto split_irqchip_unlock;
3584 /* Pairs with irqchip_in_kernel. */
3585 smp_wmb();
3586 kvm->arch.irqchip_split = true;
b053b2ae 3587 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3588 r = 0;
3589split_irqchip_unlock:
3590 mutex_unlock(&kvm->lock);
3591 break;
3592 }
90de4a18
NA		 3593 default:
3594 r = -EINVAL;
3595 break;
3596 }
3597 return r;
3598}
3599
1fe779f8
CO		 3600long kvm_arch_vm_ioctl(struct file *filp,
3601 unsigned int ioctl, unsigned long arg)
3602{
3603 struct kvm *kvm = filp->private_data;
3604 void __user *argp = (void __user *)arg;
367e1319 3605 int r = -ENOTTY;
f0d66275
DH		 3606 /*
3607 * This union makes it completely explicit to gcc-3.x
3608 * that these two variables' stack usage should be
3609 * combined, not added together.
3610 */
3611 union {
3612 struct kvm_pit_state ps;
e9f42757 3613 struct kvm_pit_state2 ps2;
c5ff41ce 3614 struct kvm_pit_config pit_config;
f0d66275 3615 } u;
1fe779f8
CO		 3616
3617 switch (ioctl) {
3618 case KVM_SET_TSS_ADDR:
3619 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3620 break;
b927a3ce
SY		 3621 case KVM_SET_IDENTITY_MAP_ADDR: {
3622 u64 ident_addr;
3623
3624 r = -EFAULT;
3625 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3626 goto out;
3627 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3628 break;
3629 }
1fe779f8
CO		 3630 case KVM_SET_NR_MMU_PAGES:
3631 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3632 break;
3633 case KVM_GET_NR_MMU_PAGES:
3634 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3635 break;
3ddea128
MT		 3636 case KVM_CREATE_IRQCHIP: {
3637 struct kvm_pic *vpic;
3638
3639 mutex_lock(&kvm->lock);
3640 r = -EEXIST;
3641 if (kvm->arch.vpic)
3642 goto create_irqchip_unlock;
3e515705
AK		 3643 r = -EINVAL;
3644 if (atomic_read(&kvm->online_vcpus))
3645 goto create_irqchip_unlock;
1fe779f8 3646 r = -ENOMEM;
3ddea128
MT		 3647 vpic = kvm_create_pic(kvm);
3648 if (vpic) {
1fe779f8
CO		 3649 r = kvm_ioapic_init(kvm);
3650 if (r) {
175504cd 3651 mutex_lock(&kvm->slots_lock);
71ba994c 3652 kvm_destroy_pic(vpic);
175504cd 3653 mutex_unlock(&kvm->slots_lock);
3ddea128 3654 goto create_irqchip_unlock;
1fe779f8
CO		 3655 }
3656 } else
3ddea128 3657 goto create_irqchip_unlock;
399ec807
AK		 3658 r = kvm_setup_default_irq_routing(kvm);
3659 if (r) {
175504cd 3660 mutex_lock(&kvm->slots_lock);
3ddea128 3661 mutex_lock(&kvm->irq_lock);
72bb2fcd 3662 kvm_ioapic_destroy(kvm);
71ba994c 3663 kvm_destroy_pic(vpic);
3ddea128 3664 mutex_unlock(&kvm->irq_lock);
175504cd 3665 mutex_unlock(&kvm->slots_lock);
71ba994c 3666 goto create_irqchip_unlock;
399ec807 3667 }
71ba994c
PB		 3668 /* Write kvm->irq_routing before kvm->arch.vpic. */
3669 smp_wmb();
3670 kvm->arch.vpic = vpic;
3ddea128
MT		 3671 create_irqchip_unlock:
3672 mutex_unlock(&kvm->lock);
1fe779f8 3673 break;
3ddea128 3674 }
7837699f 3675 case KVM_CREATE_PIT:
c5ff41ce
JK		 3676 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3677 goto create_pit;
3678 case KVM_CREATE_PIT2:
3679 r = -EFAULT;
3680 if (copy_from_user(&u.pit_config, argp,
3681 sizeof(struct kvm_pit_config)))
3682 goto out;
3683 create_pit:
79fac95e 3684 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3685 r = -EEXIST;
3686 if (kvm->arch.vpit)
3687 goto create_pit_unlock;
7837699f 3688 r = -ENOMEM;
c5ff41ce 3689 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3690 if (kvm->arch.vpit)
3691 r = 0;
269e05e4 3692 create_pit_unlock:
79fac95e 3693 mutex_unlock(&kvm->slots_lock);
7837699f 3694 break;
1fe779f8
CO		 3695 case KVM_GET_IRQCHIP: {
3696 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3697 struct kvm_irqchip *chip;
1fe779f8 3698
ff5c2c03
SL		 3699 chip = memdup_user(argp, sizeof(*chip));
3700 if (IS_ERR(chip)) {
3701 r = PTR_ERR(chip);
1fe779f8 3702 goto out;
ff5c2c03
SL		 3703 }
3704
1fe779f8 3705 r = -ENXIO;
49df6397 3706 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3707 goto get_irqchip_out;
3708 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3709 if (r)
f0d66275 3710 goto get_irqchip_out;
1fe779f8 3711 r = -EFAULT;
f0d66275
DH		 3712 if (copy_to_user(argp, chip, sizeof *chip))
3713 goto get_irqchip_out;
1fe779f8 3714 r = 0;
f0d66275
DH		 3715 get_irqchip_out:
3716 kfree(chip);
1fe779f8
CO		 3717 break;
3718 }
3719 case KVM_SET_IRQCHIP: {
3720 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3721 struct kvm_irqchip *chip;
1fe779f8 3722
ff5c2c03
SL		 3723 chip = memdup_user(argp, sizeof(*chip));
3724 if (IS_ERR(chip)) {
3725 r = PTR_ERR(chip);
1fe779f8 3726 goto out;
ff5c2c03
SL		 3727 }
3728
1fe779f8 3729 r = -ENXIO;
49df6397 3730 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3731 goto set_irqchip_out;
3732 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3733 if (r)
f0d66275 3734 goto set_irqchip_out;
1fe779f8 3735 r = 0;
f0d66275
DH		 3736 set_irqchip_out:
3737 kfree(chip);
1fe779f8
CO		 3738 break;
3739 }
e0f63cb9 3740 case KVM_GET_PIT: {
e0f63cb9 3741 r = -EFAULT;
f0d66275 3742 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3743 goto out;
3744 r = -ENXIO;
3745 if (!kvm->arch.vpit)
3746 goto out;
f0d66275 3747 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3748 if (r)
3749 goto out;
3750 r = -EFAULT;
f0d66275 3751 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3752 goto out;
3753 r = 0;
3754 break;
3755 }
3756 case KVM_SET_PIT: {
e0f63cb9 3757 r = -EFAULT;
f0d66275 3758 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3759 goto out;
3760 r = -ENXIO;
3761 if (!kvm->arch.vpit)
3762 goto out;
f0d66275 3763 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3764 break;
3765 }
e9f42757
BK		 3766 case KVM_GET_PIT2: {
3767 r = -ENXIO;
3768 if (!kvm->arch.vpit)
3769 goto out;
3770 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3771 if (r)
3772 goto out;
3773 r = -EFAULT;
3774 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3775 goto out;
3776 r = 0;
3777 break;
3778 }
3779 case KVM_SET_PIT2: {
3780 r = -EFAULT;
3781 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3782 goto out;
3783 r = -ENXIO;
3784 if (!kvm->arch.vpit)
3785 goto out;
3786 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3787 break;
3788 }
52d939a0
MT		 3789 case KVM_REINJECT_CONTROL: {
3790 struct kvm_reinject_control control;
3791 r = -EFAULT;
3792 if (copy_from_user(&control, argp, sizeof(control)))
3793 goto out;
3794 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3795 break;
3796 }
d71ba788
PB		 3797 case KVM_SET_BOOT_CPU_ID:
3798 r = 0;
3799 mutex_lock(&kvm->lock);
3800 if (atomic_read(&kvm->online_vcpus) != 0)
3801 r = -EBUSY;
3802 else
3803 kvm->arch.bsp_vcpu_id = arg;
3804 mutex_unlock(&kvm->lock);
3805 break;
ffde22ac
ES		 3806 case KVM_XEN_HVM_CONFIG: {
3807 r = -EFAULT;
3808 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3809 sizeof(struct kvm_xen_hvm_config)))
3810 goto out;
3811 r = -EINVAL;
3812 if (kvm->arch.xen_hvm_config.flags)
3813 goto out;
3814 r = 0;
3815 break;
3816 }
afbcf7ab 3817 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3818 struct kvm_clock_data user_ns;
3819 u64 now_ns;
3820 s64 delta;
3821
3822 r = -EFAULT;
3823 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3824 goto out;
3825
3826 r = -EINVAL;
3827 if (user_ns.flags)
3828 goto out;
3829
3830 r = 0;
395c6b0a 3831 local_irq_disable();
759379dd 3832 now_ns = get_kernel_ns();
afbcf7ab 3833 delta = user_ns.clock - now_ns;
395c6b0a 3834 local_irq_enable();
afbcf7ab 3835 kvm->arch.kvmclock_offset = delta;
2e762ff7 3836 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3837 break;
3838 }
3839 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3840 struct kvm_clock_data user_ns;
3841 u64 now_ns;
3842
395c6b0a 3843 local_irq_disable();
759379dd 3844 now_ns = get_kernel_ns();
afbcf7ab 3845 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3846 local_irq_enable();
afbcf7ab 3847 user_ns.flags = 0;
97e69aa6 3848 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3849
3850 r = -EFAULT;
3851 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3852 goto out;
3853 r = 0;
3854 break;
3855 }
90de4a18
NA		 3856 case KVM_ENABLE_CAP: {
3857 struct kvm_enable_cap cap;
afbcf7ab 3858
90de4a18
NA		 3859 r = -EFAULT;
3860 if (copy_from_user(&cap, argp, sizeof(cap)))
3861 goto out;
3862 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3863 break;
3864 }
1fe779f8 3865 default:
c274e03a 3866 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3867 }
3868out:
3869 return r;
3870}
3871
a16b043c 3872static void kvm_init_msr_list(void)
043405e1
CO		 3873{
3874 u32 dummy[2];
3875 unsigned i, j;
3876
62ef68bb 3877 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3878 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3879 continue;
93c4adc7
PB		 3880
3881 /*
3882 * Even MSRs that are valid in the host may not be exposed
3883 * to the guests in some cases. We could work around this
3884 * in VMX with the generic MSR save/load machinery, but it
3885 * is not really worthwhile since it will really only
3886 * happen with nested virtualization.
3887 */
3888 switch (msrs_to_save[i]) {
3889 case MSR_IA32_BNDCFGS:
3890 if (!kvm_x86_ops->mpx_supported())
3891 continue;
3892 break;
3893 default:
3894 break;
3895 }
3896
043405e1
CO		 3897 if (j < i)
3898 msrs_to_save[j] = msrs_to_save[i];
3899 j++;
3900 }
3901 num_msrs_to_save = j;
62ef68bb
PB		 3902
3903 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3904 switch (emulated_msrs[i]) {
6d396b55
PB		 3905 case MSR_IA32_SMBASE:
3906 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3907 continue;
3908 break;
62ef68bb
PB		 3909 default:
3910 break;
3911 }
3912
3913 if (j < i)
3914 emulated_msrs[j] = emulated_msrs[i];
3915 j++;
3916 }
3917 num_emulated_msrs = j;
043405e1
CO		 3918}
3919
bda9020e
MT		 3920static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3921 const void *v)
bbd9b64e 3922{
70252a10
AK		 3923 int handled = 0;
3924 int n;
3925
3926 do {
3927 n = min(len, 8);
3928 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3929 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3930 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3931 break;
3932 handled += n;
3933 addr += n;
3934 len -= n;
3935 v += n;
3936 } while (len);
bbd9b64e 3937
70252a10 3938 return handled;
bbd9b64e
CO		 3939}
3940
bda9020e 3941static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3942{
70252a10
AK		 3943 int handled = 0;
3944 int n;
3945
3946 do {
3947 n = min(len, 8);
3948 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3949 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3950 addr, n, v))
3951 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3952 break;
3953 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3954 handled += n;
3955 addr += n;
3956 len -= n;
3957 v += n;
3958 } while (len);
bbd9b64e 3959
70252a10 3960 return handled;
bbd9b64e
CO		 3961}
3962
2dafc6c2
GN		 3963static void kvm_set_segment(struct kvm_vcpu *vcpu,
3964 struct kvm_segment *var, int seg)
3965{
3966 kvm_x86_ops->set_segment(vcpu, var, seg);
3967}
3968
3969void kvm_get_segment(struct kvm_vcpu *vcpu,
3970 struct kvm_segment *var, int seg)
3971{
3972 kvm_x86_ops->get_segment(vcpu, var, seg);
3973}
3974
54987b7a
PB		 3975gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3976 struct x86_exception *exception)
02f59dc9
JR		 3977{
3978 gpa_t t_gpa;
02f59dc9
JR		 3979
3980 BUG_ON(!mmu_is_nested(vcpu));
3981
3982 /* NPT walks are always user-walks */
3983 access |= PFERR_USER_MASK;
54987b7a 3984 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3985
3986 return t_gpa;
3987}
3988
ab9ae313
AK		 3989gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3990 struct x86_exception *exception)
1871c602
GN		 3991{
3992 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3993 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3994}
3995
ab9ae313
AK		 3996 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3997 struct x86_exception *exception)
1871c602
GN		 3998{
3999 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4000 access |= PFERR_FETCH_MASK;
ab9ae313 4001 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4002}
4003
ab9ae313
AK		 4004gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4005 struct x86_exception *exception)
1871c602
GN		 4006{
4007 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4008 access |= PFERR_WRITE_MASK;
ab9ae313 4009 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4010}
4011
4012/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4013gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4014 struct x86_exception *exception)
1871c602 4015{
ab9ae313 4016 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4017}
4018
4019static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4020 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4021 struct x86_exception *exception)
bbd9b64e
CO		 4022{
4023 void *data = val;
10589a46 4024 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4025
4026 while (bytes) {
14dfe855 4027 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4028 exception);
bbd9b64e 4029 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4030 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4031 int ret;
4032
bcc55cba 4033 if (gpa == UNMAPPED_GVA)
ab9ae313 4034 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4035 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4036 offset, toread);
10589a46 4037 if (ret < 0) {
c3cd7ffa 4038 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4039 goto out;
4040 }
bbd9b64e 4041
77c2002e
IE		 4042 bytes -= toread;
4043 data += toread;
4044 addr += toread;
bbd9b64e 4045 }
10589a46 4046out:
10589a46 4047 return r;
bbd9b64e 4048}
77c2002e 4049
1871c602 4050/* used for instruction fetching */
0f65dd70
AK		 4051static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4052 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4053 struct x86_exception *exception)
1871c602 4054{
0f65dd70 4055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4056 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4057 unsigned offset;
4058 int ret;
0f65dd70 4059
44583cba
PB		 4060 /* Inline kvm_read_guest_virt_helper for speed. */
4061 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4062 exception);
4063 if (unlikely(gpa == UNMAPPED_GVA))
4064 return X86EMUL_PROPAGATE_FAULT;
4065
4066 offset = addr & (PAGE_SIZE-1);
4067 if (WARN_ON(offset + bytes > PAGE_SIZE))
4068 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4069 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4070 offset, bytes);
44583cba
PB		 4071 if (unlikely(ret < 0))
4072 return X86EMUL_IO_NEEDED;
4073
4074 return X86EMUL_CONTINUE;
1871c602
GN		 4075}
4076
064aea77 4077int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4078 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4079 struct x86_exception *exception)
1871c602 4080{
0f65dd70 4081 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4082 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4083
1871c602 4084 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4085 exception);
1871c602 4086}
064aea77 4087EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4088
0f65dd70
AK		 4089static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4090 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4091 struct x86_exception *exception)
1871c602 4092{
0f65dd70 4093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4094 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4095}
4096
6a4d7550 4097int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4098 gva_t addr, void *val,
2dafc6c2 4099 unsigned int bytes,
bcc55cba 4100 struct x86_exception *exception)
77c2002e 4101{
0f65dd70 4102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4103 void *data = val;
4104 int r = X86EMUL_CONTINUE;
4105
4106 while (bytes) {
14dfe855
JR		 4107 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4108 PFERR_WRITE_MASK,
ab9ae313 4109 exception);
77c2002e
IE		 4110 unsigned offset = addr & (PAGE_SIZE-1);
4111 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4112 int ret;
4113
bcc55cba 4114 if (gpa == UNMAPPED_GVA)
ab9ae313 4115 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4116 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4117 if (ret < 0) {
c3cd7ffa 4118 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4119 goto out;
4120 }
4121
4122 bytes -= towrite;
4123 data += towrite;
4124 addr += towrite;
4125 }
4126out:
4127 return r;
4128}
6a4d7550 4129EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4130
af7cc7d1
XG		 4131static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4132 gpa_t *gpa, struct x86_exception *exception,
4133 bool write)
4134{
97d64b78
AK		 4135 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4136 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4137
97d64b78 4138 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4139 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4140 vcpu->arch.access, access)) {
bebb106a
XG		 4141 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4142 (gva & (PAGE_SIZE - 1));
4f022648 4143 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4144 return 1;
4145 }
4146
af7cc7d1
XG		 4147 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4148
4149 if (*gpa == UNMAPPED_GVA)
4150 return -1;
4151
4152 /* For APIC access vmexit */
4153 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4154 return 1;
4155
4f022648
XG		 4156 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4157 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4158 return 1;
4f022648 4159 }
bebb106a 4160
af7cc7d1
XG		 4161 return 0;
4162}
4163
3200f405 4164int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4165 const void *val, int bytes)
bbd9b64e
CO		 4166{
4167 int ret;
4168
54bf36aa 4169 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4170 if (ret < 0)
bbd9b64e 4171 return 0;
f57f2ef5 4172 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4173 return 1;
4174}
4175
77d197b2
XG		 4176struct read_write_emulator_ops {
4177 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4178 int bytes);
4179 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4180 void *val, int bytes);
4181 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4182 int bytes, void *val);
4183 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 void *val, int bytes);
4185 bool write;
4186};
4187
4188static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4189{
4190 if (vcpu->mmio_read_completed) {
77d197b2 4191 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4192 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4193 vcpu->mmio_read_completed = 0;
4194 return 1;
4195 }
4196
4197 return 0;
4198}
4199
4200static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4201 void *val, int bytes)
4202{
54bf36aa 4203 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4204}
4205
4206static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes)
4208{
4209 return emulator_write_phys(vcpu, gpa, val, bytes);
4210}
4211
4212static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4213{
4214 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4215 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4216}
4217
4218static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 void *val, int bytes)
4220{
4221 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4222 return X86EMUL_IO_NEEDED;
4223}
4224
4225static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4226 void *val, int bytes)
4227{
f78146b0
AK		 4228 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4229
87da7e66 4230 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4231 return X86EMUL_CONTINUE;
4232}
4233
0fbe9b0b 4234static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4235 .read_write_prepare = read_prepare,
4236 .read_write_emulate = read_emulate,
4237 .read_write_mmio = vcpu_mmio_read,
4238 .read_write_exit_mmio = read_exit_mmio,
4239};
4240
0fbe9b0b 4241static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4242 .read_write_emulate = write_emulate,
4243 .read_write_mmio = write_mmio,
4244 .read_write_exit_mmio = write_exit_mmio,
4245 .write = true,
4246};
4247
22388a3c
XG		 4248static int emulator_read_write_onepage(unsigned long addr, void *val,
4249 unsigned int bytes,
4250 struct x86_exception *exception,
4251 struct kvm_vcpu *vcpu,
0fbe9b0b 4252 const struct read_write_emulator_ops *ops)
bbd9b64e 4253{
af7cc7d1
XG		 4254 gpa_t gpa;
4255 int handled, ret;
22388a3c 4256 bool write = ops->write;
f78146b0 4257 struct kvm_mmio_fragment *frag;
10589a46 4258
22388a3c 4259 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4260
af7cc7d1 4261 if (ret < 0)
bbd9b64e 4262 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4263
4264 /* For APIC access vmexit */
af7cc7d1 4265 if (ret)
bbd9b64e
CO		 4266 goto mmio;
4267
22388a3c 4268 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4269 return X86EMUL_CONTINUE;
4270
4271mmio:
4272 /*
4273 * Is this MMIO handled locally?
4274 */
22388a3c 4275 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4276 if (handled == bytes)
bbd9b64e 4277 return X86EMUL_CONTINUE;
bbd9b64e 4278
70252a10
AK		 4279 gpa += handled;
4280 bytes -= handled;
4281 val += handled;
4282
87da7e66
XG		 4283 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4284 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4285 frag->gpa = gpa;
4286 frag->data = val;
4287 frag->len = bytes;
f78146b0 4288 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4289}
4290
52eb5a6d
XL		 4291static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4292 unsigned long addr,
22388a3c
XG		 4293 void *val, unsigned int bytes,
4294 struct x86_exception *exception,
0fbe9b0b 4295 const struct read_write_emulator_ops *ops)
bbd9b64e 4296{
0f65dd70 4297 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4298 gpa_t gpa;
4299 int rc;
4300
4301 if (ops->read_write_prepare &&
4302 ops->read_write_prepare(vcpu, val, bytes))
4303 return X86EMUL_CONTINUE;
4304
4305 vcpu->mmio_nr_fragments = 0;
0f65dd70 4306
bbd9b64e
CO		 4307 /* Crossing a page boundary? */
4308 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4309 int now;
bbd9b64e
CO		 4310
4311 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4312 rc = emulator_read_write_onepage(addr, val, now, exception,
4313 vcpu, ops);
4314
bbd9b64e
CO		 4315 if (rc != X86EMUL_CONTINUE)
4316 return rc;
4317 addr += now;
bac15531
NA		 4318 if (ctxt->mode != X86EMUL_MODE_PROT64)
4319 addr = (u32)addr;
bbd9b64e
CO		 4320 val += now;
4321 bytes -= now;
4322 }
22388a3c 4323
f78146b0
AK		 4324 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4325 vcpu, ops);
4326 if (rc != X86EMUL_CONTINUE)
4327 return rc;
4328
4329 if (!vcpu->mmio_nr_fragments)
4330 return rc;
4331
4332 gpa = vcpu->mmio_fragments[0].gpa;
4333
4334 vcpu->mmio_needed = 1;
4335 vcpu->mmio_cur_fragment = 0;
4336
87da7e66 4337 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4338 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4339 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4340 vcpu->run->mmio.phys_addr = gpa;
4341
4342 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4343}
4344
4345static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4346 unsigned long addr,
4347 void *val,
4348 unsigned int bytes,
4349 struct x86_exception *exception)
4350{
4351 return emulator_read_write(ctxt, addr, val, bytes,
4352 exception, &read_emultor);
4353}
4354
52eb5a6d 4355static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4356 unsigned long addr,
4357 const void *val,
4358 unsigned int bytes,
4359 struct x86_exception *exception)
4360{
4361 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4362 exception, &write_emultor);
bbd9b64e 4363}
bbd9b64e 4364
daea3e73
AK		 4365#define CMPXCHG_TYPE(t, ptr, old, new) \
4366 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4367
4368#ifdef CONFIG_X86_64
4369# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4370#else
4371# define CMPXCHG64(ptr, old, new) \
9749a6c0 4372 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4373#endif
4374
0f65dd70
AK		 4375static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4376 unsigned long addr,
bbd9b64e
CO		 4377 const void *old,
4378 const void *new,
4379 unsigned int bytes,
0f65dd70 4380 struct x86_exception *exception)
bbd9b64e 4381{
0f65dd70 4382 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4383 gpa_t gpa;
4384 struct page *page;
4385 char *kaddr;
4386 bool exchanged;
2bacc55c 4387
daea3e73
AK		 4388 /* guests cmpxchg8b have to be emulated atomically */
4389 if (bytes > 8 || (bytes & (bytes - 1)))
4390 goto emul_write;
10589a46 4391
daea3e73 4392 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4393
daea3e73
AK		 4394 if (gpa == UNMAPPED_GVA ||
4395 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4396 goto emul_write;
2bacc55c 4397
daea3e73
AK		 4398 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4399 goto emul_write;
72dc67a6 4400
54bf36aa 4401 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4402 if (is_error_page(page))
c19b8bd6 4403 goto emul_write;
72dc67a6 4404
8fd75e12 4405 kaddr = kmap_atomic(page);
daea3e73
AK		 4406 kaddr += offset_in_page(gpa);
4407 switch (bytes) {
4408 case 1:
4409 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4410 break;
4411 case 2:
4412 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4413 break;
4414 case 4:
4415 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4416 break;
4417 case 8:
4418 exchanged = CMPXCHG64(kaddr, old, new);
4419 break;
4420 default:
4421 BUG();
2bacc55c 4422 }
8fd75e12 4423 kunmap_atomic(kaddr);
daea3e73
AK		 4424 kvm_release_page_dirty(page);
4425
4426 if (!exchanged)
4427 return X86EMUL_CMPXCHG_FAILED;
4428
54bf36aa 4429 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4430 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4431
4432 return X86EMUL_CONTINUE;
4a5f48f6 4433
3200f405 4434emul_write:
daea3e73 4435 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4436
0f65dd70 4437 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4438}
4439
cf8f70bf
GN		 4440static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4441{
4442 /* TODO: String I/O for in kernel device */
4443 int r;
4444
4445 if (vcpu->arch.pio.in)
e32edf4f 4446 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4447 vcpu->arch.pio.size, pd);
4448 else
e32edf4f 4449 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4450 vcpu->arch.pio.port, vcpu->arch.pio.size,
4451 pd);
4452 return r;
4453}
4454
6f6fbe98
XG		 4455static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4456 unsigned short port, void *val,
4457 unsigned int count, bool in)
cf8f70bf 4458{
cf8f70bf 4459 vcpu->arch.pio.port = port;
6f6fbe98 4460 vcpu->arch.pio.in = in;
7972995b 4461 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4462 vcpu->arch.pio.size = size;
4463
4464 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4465 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4466 return 1;
4467 }
4468
4469 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4470 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4471 vcpu->run->io.size = size;
4472 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4473 vcpu->run->io.count = count;
4474 vcpu->run->io.port = port;
4475
4476 return 0;
4477}
4478
6f6fbe98
XG		 4479static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4480 int size, unsigned short port, void *val,
4481 unsigned int count)
cf8f70bf 4482{
ca1d4a9e 4483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4484 int ret;
ca1d4a9e 4485
6f6fbe98
XG		 4486 if (vcpu->arch.pio.count)
4487 goto data_avail;
cf8f70bf 4488
6f6fbe98
XG		 4489 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4490 if (ret) {
4491data_avail:
4492 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4493 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4494 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4495 return 1;
4496 }
4497
cf8f70bf
GN		 4498 return 0;
4499}
4500
6f6fbe98
XG		 4501static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4502 int size, unsigned short port,
4503 const void *val, unsigned int count)
4504{
4505 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4506
4507 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4508 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4509 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4510}
4511
bbd9b64e
CO		 4512static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4513{
4514 return kvm_x86_ops->get_segment_base(vcpu, seg);
4515}
4516
3cb16fe7 4517static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4518{
3cb16fe7 4519 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4520}
4521
5cb56059 4522int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4523{
4524 if (!need_emulate_wbinvd(vcpu))
4525 return X86EMUL_CONTINUE;
4526
4527 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4528 int cpu = get_cpu();
4529
4530 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4531 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4532 wbinvd_ipi, NULL, 1);
2eec7343 4533 put_cpu();
f5f48ee1 4534 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4535 } else
4536 wbinvd();
f5f48ee1
SY		 4537 return X86EMUL_CONTINUE;
4538}
5cb56059
JS		 4539
4540int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4541{
4542 kvm_x86_ops->skip_emulated_instruction(vcpu);
4543 return kvm_emulate_wbinvd_noskip(vcpu);
4544}
f5f48ee1
SY		 4545EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4546
5cb56059
JS		 4547
4548
bcaf5cc5
AK		 4549static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4550{
5cb56059 4551 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4552}
4553
52eb5a6d
XL		 4554static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4555 unsigned long *dest)
bbd9b64e 4556{
16f8a6f9 4557 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4558}
4559
52eb5a6d
XL		 4560static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4561 unsigned long value)
bbd9b64e 4562{
338dbc97 4563
717746e3 4564 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4565}
4566
52a46617 4567static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4568{
52a46617 4569 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4570}
4571
717746e3 4572static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4573{
717746e3 4574 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4575 unsigned long value;
4576
4577 switch (cr) {
4578 case 0:
4579 value = kvm_read_cr0(vcpu);
4580 break;
4581 case 2:
4582 value = vcpu->arch.cr2;
4583 break;
4584 case 3:
9f8fe504 4585 value = kvm_read_cr3(vcpu);
52a46617
GN		 4586 break;
4587 case 4:
4588 value = kvm_read_cr4(vcpu);
4589 break;
4590 case 8:
4591 value = kvm_get_cr8(vcpu);
4592 break;
4593 default:
a737f256 4594 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4595 return 0;
4596 }
4597
4598 return value;
4599}
4600
717746e3 4601static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4602{
717746e3 4603 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4604 int res = 0;
4605
52a46617
GN		 4606 switch (cr) {
4607 case 0:
49a9b07e 4608 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4609 break;
4610 case 2:
4611 vcpu->arch.cr2 = val;
4612 break;
4613 case 3:
2390218b 4614 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4615 break;
4616 case 4:
a83b29c6 4617 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4618 break;
4619 case 8:
eea1cff9 4620 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4621 break;
4622 default:
a737f256 4623 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4624 res = -1;
52a46617 4625 }
0f12244f
GN		 4626
4627 return res;
52a46617
GN		 4628}
4629
717746e3 4630static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4631{
717746e3 4632 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4633}
4634
4bff1e86 4635static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4636{
4bff1e86 4637 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4638}
4639
4bff1e86 4640static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4641{
4bff1e86 4642 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4643}
4644
1ac9d0cf
AK		 4645static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4646{
4647 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4648}
4649
4650static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4651{
4652 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4653}
4654
4bff1e86
AK		 4655static unsigned long emulator_get_cached_segment_base(
4656 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4657{
4bff1e86 4658 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4659}
4660
1aa36616
AK		 4661static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4662 struct desc_struct *desc, u32 *base3,
4663 int seg)
2dafc6c2
GN		 4664{
4665 struct kvm_segment var;
4666
4bff1e86 4667 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4668 *selector = var.selector;
2dafc6c2 4669
378a8b09
GN		 4670 if (var.unusable) {
4671 memset(desc, 0, sizeof(*desc));
2dafc6c2 4672 return false;
378a8b09 4673 }
2dafc6c2
GN		 4674
4675 if (var.g)
4676 var.limit >>= 12;
4677 set_desc_limit(desc, var.limit);
4678 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4679#ifdef CONFIG_X86_64
4680 if (base3)
4681 *base3 = var.base >> 32;
4682#endif
2dafc6c2
GN		 4683 desc->type = var.type;
4684 desc->s = var.s;
4685 desc->dpl = var.dpl;
4686 desc->p = var.present;
4687 desc->avl = var.avl;
4688 desc->l = var.l;
4689 desc->d = var.db;
4690 desc->g = var.g;
4691
4692 return true;
4693}
4694
1aa36616
AK		 4695static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4696 struct desc_struct *desc, u32 base3,
4697 int seg)
2dafc6c2 4698{
4bff1e86 4699 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4700 struct kvm_segment var;
4701
1aa36616 4702 var.selector = selector;
2dafc6c2 4703 var.base = get_desc_base(desc);
5601d05b
GN		 4704#ifdef CONFIG_X86_64
4705 var.base |= ((u64)base3) << 32;
4706#endif
2dafc6c2
GN		 4707 var.limit = get_desc_limit(desc);
4708 if (desc->g)
4709 var.limit = (var.limit << 12) | 0xfff;
4710 var.type = desc->type;
2dafc6c2
GN		 4711 var.dpl = desc->dpl;
4712 var.db = desc->d;
4713 var.s = desc->s;
4714 var.l = desc->l;
4715 var.g = desc->g;
4716 var.avl = desc->avl;
4717 var.present = desc->p;
4718 var.unusable = !var.present;
4719 var.padding = 0;
4720
4721 kvm_set_segment(vcpu, &var, seg);
4722 return;
4723}
4724
717746e3
AK		 4725static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4726 u32 msr_index, u64 *pdata)
4727{
609e36d3
PB		 4728 struct msr_data msr;
4729 int r;
4730
4731 msr.index = msr_index;
4732 msr.host_initiated = false;
4733 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4734 if (r)
4735 return r;
4736
4737 *pdata = msr.data;
4738 return 0;
717746e3
AK		 4739}
4740
4741static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4742 u32 msr_index, u64 data)
4743{
8fe8ab46
WA		 4744 struct msr_data msr;
4745
4746 msr.data = data;
4747 msr.index = msr_index;
4748 msr.host_initiated = false;
4749 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4750}
4751
64d60670
PB		 4752static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4753{
4754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4755
4756 return vcpu->arch.smbase;
4757}
4758
4759static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4760{
4761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4762
4763 vcpu->arch.smbase = smbase;
4764}
4765
67f4d428
NA		 4766static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4767 u32 pmc)
4768{
c6702c9d 4769 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4770}
4771
222d21aa
AK		 4772static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4773 u32 pmc, u64 *pdata)
4774{
c6702c9d 4775 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4776}
4777
6c3287f7
AK		 4778static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4779{
4780 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4781}
4782
5037f6f3
AK		 4783static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4784{
4785 preempt_disable();
5197b808 4786 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4787 /*
4788 * CR0.TS may reference the host fpu state, not the guest fpu state,
4789 * so it may be clear at this point.
4790 */
4791 clts();
4792}
4793
4794static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4795{
4796 preempt_enable();
4797}
4798
2953538e 4799static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4800 struct x86_instruction_info *info,
c4f035c6
AK		 4801 enum x86_intercept_stage stage)
4802{
2953538e 4803 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4804}
4805
0017f93a 4806static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4807 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4808{
0017f93a 4809 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4810}
4811
dd856efa
AK		 4812static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4813{
4814 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4815}
4816
4817static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4818{
4819 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4820}
4821
801806d9
NA		 4822static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4823{
4824 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4825}
4826
0225fb50 4827static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4828 .read_gpr = emulator_read_gpr,
4829 .write_gpr = emulator_write_gpr,
1871c602 4830 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4831 .write_std = kvm_write_guest_virt_system,
1871c602 4832 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4833 .read_emulated = emulator_read_emulated,
4834 .write_emulated = emulator_write_emulated,
4835 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4836 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4837 .pio_in_emulated = emulator_pio_in_emulated,
4838 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4839 .get_segment = emulator_get_segment,
4840 .set_segment = emulator_set_segment,
5951c442 4841 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4842 .get_gdt = emulator_get_gdt,
160ce1f1 4843 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4844 .set_gdt = emulator_set_gdt,
4845 .set_idt = emulator_set_idt,
52a46617
GN		 4846 .get_cr = emulator_get_cr,
4847 .set_cr = emulator_set_cr,
9c537244 4848 .cpl = emulator_get_cpl,
35aa5375
GN		 4849 .get_dr = emulator_get_dr,
4850 .set_dr = emulator_set_dr,
64d60670
PB		 4851 .get_smbase = emulator_get_smbase,
4852 .set_smbase = emulator_set_smbase,
717746e3
AK		 4853 .set_msr = emulator_set_msr,
4854 .get_msr = emulator_get_msr,
67f4d428 4855 .check_pmc = emulator_check_pmc,
222d21aa 4856 .read_pmc = emulator_read_pmc,
6c3287f7 4857 .halt = emulator_halt,
bcaf5cc5 4858 .wbinvd = emulator_wbinvd,
d6aa1000 4859 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4860 .get_fpu = emulator_get_fpu,
4861 .put_fpu = emulator_put_fpu,
c4f035c6 4862 .intercept = emulator_intercept,
bdb42f5a 4863 .get_cpuid = emulator_get_cpuid,
801806d9 4864 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4865};
4866
95cb2295
GN		 4867static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4868{
37ccdcbe 4869 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4870 /*
4871 * an sti; sti; sequence only disable interrupts for the first
4872 * instruction. So, if the last instruction, be it emulated or
4873 * not, left the system with the INT_STI flag enabled, it
4874 * means that the last instruction is an sti. We should not
4875 * leave the flag on in this case. The same goes for mov ss
4876 */
37ccdcbe
PB		 4877 if (int_shadow & mask)
4878 mask = 0;
6addfc42 4879 if (unlikely(int_shadow || mask)) {
95cb2295 4880 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4881 if (!mask)
4882 kvm_make_request(KVM_REQ_EVENT, vcpu);
4883 }
95cb2295
GN		 4884}
4885
ef54bcfe 4886static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4887{
4888 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4889 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4890 return kvm_propagate_fault(vcpu, &ctxt->exception);
4891
4892 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4893 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4894 ctxt->exception.error_code);
54b8486f 4895 else
da9cb575 4896 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4897 return false;
54b8486f
GN		 4898}
4899
8ec4722d
MG		 4900static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4901{
adf52235 4902 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4903 int cs_db, cs_l;
4904
8ec4722d
MG		 4905 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4906
adf52235
TY		 4907 ctxt->eflags = kvm_get_rflags(vcpu);
4908 ctxt->eip = kvm_rip_read(vcpu);
4909 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4910 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4911 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4912 cs_db ? X86EMUL_MODE_PROT32 :
4913 X86EMUL_MODE_PROT16;
a584539b 4914 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4915 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4916 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4917 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4918
dd856efa 4919 init_decode_cache(ctxt);
7ae441ea 4920 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4921}
4922
71f9833b 4923int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4924{
9d74191a 4925 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4926 int ret;
4927
4928 init_emulate_ctxt(vcpu);
4929
9dac77fa
AK		 4930 ctxt->op_bytes = 2;
4931 ctxt->ad_bytes = 2;
4932 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4933 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4934
4935 if (ret != X86EMUL_CONTINUE)
4936 return EMULATE_FAIL;
4937
9dac77fa 4938 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4939 kvm_rip_write(vcpu, ctxt->eip);
4940 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4941
4942 if (irq == NMI_VECTOR)
7460fb4a 4943 vcpu->arch.nmi_pending = 0;
63995653
MG		 4944 else
4945 vcpu->arch.interrupt.pending = false;
4946
4947 return EMULATE_DONE;
4948}
4949EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4950
6d77dbfc
GN		 4951static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4952{
fc3a9157
JR		 4953 int r = EMULATE_DONE;
4954
6d77dbfc
GN		 4955 ++vcpu->stat.insn_emulation_fail;
4956 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4957 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4958 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4959 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4960 vcpu->run->internal.ndata = 0;
4961 r = EMULATE_FAIL;
4962 }
6d77dbfc 4963 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4964
4965 return r;
6d77dbfc
GN		 4966}
4967
93c05d3e 4968static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4969 bool write_fault_to_shadow_pgtable,
4970 int emulation_type)
a6f177ef 4971{
95b3cf69 4972 gpa_t gpa = cr2;
8e3d9d06 4973 pfn_t pfn;
a6f177ef 4974
991eebf9
GN		 4975 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4976 return false;
4977
95b3cf69
XG		 4978 if (!vcpu->arch.mmu.direct_map) {
4979 /*
4980 * Write permission should be allowed since only
4981 * write access need to be emulated.
4982 */
4983 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4984
95b3cf69
XG		 4985 /*
4986 * If the mapping is invalid in guest, let cpu retry
4987 * it to generate fault.
4988 */
4989 if (gpa == UNMAPPED_GVA)
4990 return true;
4991 }
a6f177ef 4992
8e3d9d06
XG		 4993 /*
4994 * Do not retry the unhandleable instruction if it faults on the
4995 * readonly host memory, otherwise it will goto a infinite loop:
4996 * retry instruction -> write #PF -> emulation fail -> retry
4997 * instruction -> ...
4998 */
4999 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5000
5001 /*
5002 * If the instruction failed on the error pfn, it can not be fixed,
5003 * report the error to userspace.
5004 */
5005 if (is_error_noslot_pfn(pfn))
5006 return false;
5007
5008 kvm_release_pfn_clean(pfn);
5009
5010 /* The instructions are well-emulated on direct mmu. */
5011 if (vcpu->arch.mmu.direct_map) {
5012 unsigned int indirect_shadow_pages;
5013
5014 spin_lock(&vcpu->kvm->mmu_lock);
5015 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5016 spin_unlock(&vcpu->kvm->mmu_lock);
5017
5018 if (indirect_shadow_pages)
5019 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5020
a6f177ef 5021 return true;
8e3d9d06 5022 }
a6f177ef 5023
95b3cf69
XG		 5024 /*
5025 * if emulation was due to access to shadowed page table
5026 * and it failed try to unshadow page and re-enter the
5027 * guest to let CPU execute the instruction.
5028 */
5029 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5030
5031 /*
5032 * If the access faults on its page table, it can not
5033 * be fixed by unprotecting shadow page and it should
5034 * be reported to userspace.
5035 */
5036 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5037}
5038
1cb3f3ae
XG		 5039static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5040 unsigned long cr2, int emulation_type)
5041{
5042 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5043 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5044
5045 last_retry_eip = vcpu->arch.last_retry_eip;
5046 last_retry_addr = vcpu->arch.last_retry_addr;
5047
5048 /*
5049 * If the emulation is caused by #PF and it is non-page_table
5050 * writing instruction, it means the VM-EXIT is caused by shadow
5051 * page protected, we can zap the shadow page and retry this
5052 * instruction directly.
5053 *
5054 * Note: if the guest uses a non-page-table modifying instruction
5055 * on the PDE that points to the instruction, then we will unmap
5056 * the instruction and go to an infinite loop. So, we cache the
5057 * last retried eip and the last fault address, if we meet the eip
5058 * and the address again, we can break out of the potential infinite
5059 * loop.
5060 */
5061 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5062
5063 if (!(emulation_type & EMULTYPE_RETRY))
5064 return false;
5065
5066 if (x86_page_table_writing_insn(ctxt))
5067 return false;
5068
5069 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5070 return false;
5071
5072 vcpu->arch.last_retry_eip = ctxt->eip;
5073 vcpu->arch.last_retry_addr = cr2;
5074
5075 if (!vcpu->arch.mmu.direct_map)
5076 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5077
22368028 5078 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5079
5080 return true;
5081}
5082
716d51ab
GN		 5083static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5084static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5085
64d60670 5086static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5087{
64d60670 5088 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5089 /* This is a good place to trace that we are exiting SMM. */
5090 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5091
64d60670
PB		 5092 if (unlikely(vcpu->arch.smi_pending)) {
5093 kvm_make_request(KVM_REQ_SMI, vcpu);
5094 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5095 } else {
5096 /* Process a latched INIT, if any. */
5097 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5098 }
5099 }
699023e2
PB		 5100
5101 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5102}
5103
5104static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5105{
5106 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5107
a584539b 5108 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5109
5110 if (changed & HF_SMM_MASK)
5111 kvm_smm_changed(vcpu);
a584539b
PB		 5112}
5113
4a1e10d5
PB		 5114static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5115 unsigned long *db)
5116{
5117 u32 dr6 = 0;
5118 int i;
5119 u32 enable, rwlen;
5120
5121 enable = dr7;
5122 rwlen = dr7 >> 16;
5123 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5124 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5125 dr6 |= (1 << i);
5126 return dr6;
5127}
5128
6addfc42 5129static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5130{
5131 struct kvm_run *kvm_run = vcpu->run;
5132
5133 /*
6addfc42
PB		 5134 * rflags is the old, "raw" value of the flags. The new value has
5135 * not been saved yet.
663f4c61
PB		 5136 *
5137 * This is correct even for TF set by the guest, because "the
5138 * processor will not generate this exception after the instruction
5139 * that sets the TF flag".
5140 */
663f4c61
PB		 5141 if (unlikely(rflags & X86_EFLAGS_TF)) {
5142 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5143 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5144 DR6_RTM;
663f4c61
PB		 5145 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5146 kvm_run->debug.arch.exception = DB_VECTOR;
5147 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5148 *r = EMULATE_USER_EXIT;
5149 } else {
5150 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5151 /*
5152 * "Certain debug exceptions may clear bit 0-3. The
5153 * remaining contents of the DR6 register are never
5154 * cleared by the processor".
5155 */
5156 vcpu->arch.dr6 &= ~15;
6f43ed01 5157 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5158 kvm_queue_exception(vcpu, DB_VECTOR);
5159 }
5160 }
5161}
5162
4a1e10d5
PB		 5163static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5164{
4a1e10d5
PB		 5165 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5166 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5167 struct kvm_run *kvm_run = vcpu->run;
5168 unsigned long eip = kvm_get_linear_rip(vcpu);
5169 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5170 vcpu->arch.guest_debug_dr7,
5171 vcpu->arch.eff_db);
5172
5173 if (dr6 != 0) {
6f43ed01 5174 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5175 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5176 kvm_run->debug.arch.exception = DB_VECTOR;
5177 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5178 *r = EMULATE_USER_EXIT;
5179 return true;
5180 }
5181 }
5182
4161a569
NA		 5183 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5184 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5185 unsigned long eip = kvm_get_linear_rip(vcpu);
5186 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5187 vcpu->arch.dr7,
5188 vcpu->arch.db);
5189
5190 if (dr6 != 0) {
5191 vcpu->arch.dr6 &= ~15;
6f43ed01 5192 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5193 kvm_queue_exception(vcpu, DB_VECTOR);
5194 *r = EMULATE_DONE;
5195 return true;
5196 }
5197 }
5198
5199 return false;
5200}
5201
51d8b661
AP		 5202int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5203 unsigned long cr2,
dc25e89e
AP		 5204 int emulation_type,
5205 void *insn,
5206 int insn_len)
bbd9b64e 5207{
95cb2295 5208 int r;
9d74191a 5209 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5210 bool writeback = true;
93c05d3e 5211 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5212
93c05d3e
XG		 5213 /*
5214 * Clear write_fault_to_shadow_pgtable here to ensure it is
5215 * never reused.
5216 */
5217 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5218 kvm_clear_exception_queue(vcpu);
8d7d8102 5219
571008da 5220 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5221 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5222
5223 /*
5224 * We will reenter on the same instruction since
5225 * we do not set complete_userspace_io. This does not
5226 * handle watchpoints yet, those would be handled in
5227 * the emulate_ops.
5228 */
5229 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5230 return r;
5231
9d74191a
TY		 5232 ctxt->interruptibility = 0;
5233 ctxt->have_exception = false;
e0ad0b47 5234 ctxt->exception.vector = -1;
9d74191a 5235 ctxt->perm_ok = false;
bbd9b64e 5236
b51e974f 5237 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5238
9d74191a 5239 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5240
e46479f8 5241 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5242 ++vcpu->stat.insn_emulation;
1d2887e2 5243 if (r != EMULATION_OK) {
4005996e
AK		 5244 if (emulation_type & EMULTYPE_TRAP_UD)
5245 return EMULATE_FAIL;
991eebf9
GN		 5246 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5247 emulation_type))
bbd9b64e 5248 return EMULATE_DONE;
6d77dbfc
GN		 5249 if (emulation_type & EMULTYPE_SKIP)
5250 return EMULATE_FAIL;
5251 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5252 }
5253 }
5254
ba8afb6b 5255 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5256 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5257 if (ctxt->eflags & X86_EFLAGS_RF)
5258 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5259 return EMULATE_DONE;
5260 }
5261
1cb3f3ae
XG		 5262 if (retry_instruction(ctxt, cr2, emulation_type))
5263 return EMULATE_DONE;
5264
7ae441ea 5265 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5266 changes registers values during IO operation */
7ae441ea
GN		 5267 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5268 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5269 emulator_invalidate_register_cache(ctxt);
7ae441ea 5270 }
4d2179e1 5271
5cd21917 5272restart:
9d74191a 5273 r = x86_emulate_insn(ctxt);
bbd9b64e 5274
775fde86
JR		 5275 if (r == EMULATION_INTERCEPTED)
5276 return EMULATE_DONE;
5277
d2ddd1c4 5278 if (r == EMULATION_FAILED) {
991eebf9
GN		 5279 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5280 emulation_type))
c3cd7ffa
GN		 5281 return EMULATE_DONE;
5282
6d77dbfc 5283 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5284 }
5285
9d74191a 5286 if (ctxt->have_exception) {
d2ddd1c4 5287 r = EMULATE_DONE;
ef54bcfe
PB		 5288 if (inject_emulated_exception(vcpu))
5289 return r;
d2ddd1c4 5290 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5291 if (!vcpu->arch.pio.in) {
5292 /* FIXME: return into emulator if single-stepping. */
3457e419 5293 vcpu->arch.pio.count = 0;
0912c977 5294 } else {
7ae441ea 5295 writeback = false;
716d51ab
GN		 5296 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5297 }
ac0a48c3 5298 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5299 } else if (vcpu->mmio_needed) {
5300 if (!vcpu->mmio_is_write)
5301 writeback = false;
ac0a48c3 5302 r = EMULATE_USER_EXIT;
716d51ab 5303 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5304 } else if (r == EMULATION_RESTART)
5cd21917 5305 goto restart;
d2ddd1c4
GN		 5306 else
5307 r = EMULATE_DONE;
f850e2e6 5308
7ae441ea 5309 if (writeback) {
6addfc42 5310 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5311 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5312 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5313 if (vcpu->arch.hflags != ctxt->emul_flags)
5314 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5315 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5316 if (r == EMULATE_DONE)
6addfc42 5317 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5318 if (!ctxt->have_exception ||
5319 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5320 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5321
5322 /*
5323 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5324 * do nothing, and it will be requested again as soon as
5325 * the shadow expires. But we still need to check here,
5326 * because POPF has no interrupt shadow.
5327 */
5328 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5329 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5330 } else
5331 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5332
5333 return r;
de7d789a 5334}
51d8b661 5335EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5336
cf8f70bf 5337int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5338{
cf8f70bf 5339 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5340 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5341 size, port, &val, 1);
cf8f70bf 5342 /* do not return to emulator after return from userspace */
7972995b 5343 vcpu->arch.pio.count = 0;
de7d789a
CO		 5344 return ret;
5345}
cf8f70bf 5346EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5347
8cfdc000
ZA		 5348static void tsc_bad(void *info)
5349{
0a3aee0d 5350 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5351}
5352
5353static void tsc_khz_changed(void *data)
c8076604 5354{
8cfdc000
ZA		 5355 struct cpufreq_freqs *freq = data;
5356 unsigned long khz = 0;
5357
5358 if (data)
5359 khz = freq->new;
5360 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5361 khz = cpufreq_quick_get(raw_smp_processor_id());
5362 if (!khz)
5363 khz = tsc_khz;
0a3aee0d 5364 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5365}
5366
c8076604
GH		 5367static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5368 void *data)
5369{
5370 struct cpufreq_freqs *freq = data;
5371 struct kvm *kvm;
5372 struct kvm_vcpu *vcpu;
5373 int i, send_ipi = 0;
5374
8cfdc000
ZA		 5375 /*
5376 * We allow guests to temporarily run on slowing clocks,
5377 * provided we notify them after, or to run on accelerating
5378 * clocks, provided we notify them before. Thus time never
5379 * goes backwards.
5380 *
5381 * However, we have a problem. We can't atomically update
5382 * the frequency of a given CPU from this function; it is
5383 * merely a notifier, which can be called from any CPU.
5384 * Changing the TSC frequency at arbitrary points in time
5385 * requires a recomputation of local variables related to
5386 * the TSC for each VCPU. We must flag these local variables
5387 * to be updated and be sure the update takes place with the
5388 * new frequency before any guests proceed.
5389 *
5390 * Unfortunately, the combination of hotplug CPU and frequency
5391 * change creates an intractable locking scenario; the order
5392 * of when these callouts happen is undefined with respect to
5393 * CPU hotplug, and they can race with each other. As such,
5394 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5395 * undefined; you can actually have a CPU frequency change take
5396 * place in between the computation of X and the setting of the
5397 * variable. To protect against this problem, all updates of
5398 * the per_cpu tsc_khz variable are done in an interrupt
5399 * protected IPI, and all callers wishing to update the value
5400 * must wait for a synchronous IPI to complete (which is trivial
5401 * if the caller is on the CPU already). This establishes the
5402 * necessary total order on variable updates.
5403 *
5404 * Note that because a guest time update may take place
5405 * anytime after the setting of the VCPU's request bit, the
5406 * correct TSC value must be set before the request. However,
5407 * to ensure the update actually makes it to any guest which
5408 * starts running in hardware virtualization between the set
5409 * and the acquisition of the spinlock, we must also ping the
5410 * CPU after setting the request bit.
5411 *
5412 */
5413
c8076604
GH		 5414 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5415 return 0;
5416 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5417 return 0;
8cfdc000
ZA		 5418
5419 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5420
2f303b74 5421 spin_lock(&kvm_lock);
c8076604 5422 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5423 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5424 if (vcpu->cpu != freq->cpu)
5425 continue;
c285545f 5426 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5427 if (vcpu->cpu != smp_processor_id())
8cfdc000 5428 send_ipi = 1;
c8076604
GH		 5429 }
5430 }
2f303b74 5431 spin_unlock(&kvm_lock);
c8076604
GH		 5432
5433 if (freq->old < freq->new && send_ipi) {
5434 /*
5435 * We upscale the frequency. Must make the guest
5436 * doesn't see old kvmclock values while running with
5437 * the new frequency, otherwise we risk the guest sees
5438 * time go backwards.
5439 *
5440 * In case we update the frequency for another cpu
5441 * (which might be in guest context) send an interrupt
5442 * to kick the cpu out of guest context. Next time
5443 * guest context is entered kvmclock will be updated,
5444 * so the guest will not see stale values.
5445 */
8cfdc000 5446 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5447 }
5448 return 0;
5449}
5450
5451static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5452 .notifier_call = kvmclock_cpufreq_notifier
5453};
5454
5455static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5456 unsigned long action, void *hcpu)
5457{
5458 unsigned int cpu = (unsigned long)hcpu;
5459
5460 switch (action) {
5461 case CPU_ONLINE:
5462 case CPU_DOWN_FAILED:
5463 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5464 break;
5465 case CPU_DOWN_PREPARE:
5466 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5467 break;
5468 }
5469 return NOTIFY_OK;
5470}
5471
5472static struct notifier_block kvmclock_cpu_notifier_block = {
5473 .notifier_call = kvmclock_cpu_notifier,
5474 .priority = -INT_MAX
c8076604
GH		 5475};
5476
b820cc0c
ZA		 5477static void kvm_timer_init(void)
5478{
5479 int cpu;
5480
c285545f 5481 max_tsc_khz = tsc_khz;
460dd42e
SB		 5482
5483 cpu_notifier_register_begin();
b820cc0c 5484 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5485#ifdef CONFIG_CPU_FREQ
5486 struct cpufreq_policy policy;
5487 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5488 cpu = get_cpu();
5489 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5490 if (policy.cpuinfo.max_freq)
5491 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5492 put_cpu();
c285545f 5493#endif
b820cc0c
ZA		 5494 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5495 CPUFREQ_TRANSITION_NOTIFIER);
5496 }
c285545f 5497 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5498 for_each_online_cpu(cpu)
5499 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5500
5501 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5502 cpu_notifier_register_done();
5503
b820cc0c
ZA		 5504}
5505
ff9d07a0
ZY		 5506static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5507
f5132b01 5508int kvm_is_in_guest(void)
ff9d07a0 5509{
086c9855 5510 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5511}
5512
5513static int kvm_is_user_mode(void)
5514{
5515 int user_mode = 3;
dcf46b94 5516
086c9855
AS		 5517 if (__this_cpu_read(current_vcpu))
5518 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5519
ff9d07a0
ZY		 5520 return user_mode != 0;
5521}
5522
5523static unsigned long kvm_get_guest_ip(void)
5524{
5525 unsigned long ip = 0;
dcf46b94 5526
086c9855
AS		 5527 if (__this_cpu_read(current_vcpu))
5528 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5529
ff9d07a0
ZY		 5530 return ip;
5531}
5532
5533static struct perf_guest_info_callbacks kvm_guest_cbs = {
5534 .is_in_guest = kvm_is_in_guest,
5535 .is_user_mode = kvm_is_user_mode,
5536 .get_guest_ip = kvm_get_guest_ip,
5537};
5538
5539void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5540{
086c9855 5541 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5542}
5543EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5544
5545void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5546{
086c9855 5547 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5548}
5549EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5550
ce88decf
XG		 5551static void kvm_set_mmio_spte_mask(void)
5552{
5553 u64 mask;
5554 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5555
5556 /*
5557 * Set the reserved bits and the present bit of an paging-structure
5558 * entry to generate page fault with PFER.RSV = 1.
5559 */
885032b9 5560 /* Mask the reserved physical address bits. */
d1431483 5561 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5562
5563 /* Bit 62 is always reserved for 32bit host. */
5564 mask |= 0x3ull << 62;
5565
5566 /* Set the present bit. */
ce88decf
XG		 5567 mask |= 1ull;
5568
5569#ifdef CONFIG_X86_64
5570 /*
5571 * If reserved bit is not supported, clear the present bit to disable
5572 * mmio page fault.
5573 */
5574 if (maxphyaddr == 52)
5575 mask &= ~1ull;
5576#endif
5577
5578 kvm_mmu_set_mmio_spte_mask(mask);
5579}
5580
16e8d74d
MT		 5581#ifdef CONFIG_X86_64
5582static void pvclock_gtod_update_fn(struct work_struct *work)
5583{
d828199e
MT		 5584 struct kvm *kvm;
5585
5586 struct kvm_vcpu *vcpu;
5587 int i;
5588
2f303b74 5589 spin_lock(&kvm_lock);
d828199e
MT		 5590 list_for_each_entry(kvm, &vm_list, vm_list)
5591 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5592 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5593 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5594 spin_unlock(&kvm_lock);
16e8d74d
MT		 5595}
5596
5597static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5598
5599/*
5600 * Notification about pvclock gtod data update.
5601 */
5602static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5603 void *priv)
5604{
5605 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5606 struct timekeeper *tk = priv;
5607
5608 update_pvclock_gtod(tk);
5609
5610 /* disable master clock if host does not trust, or does not
5611 * use, TSC clocksource
5612 */
5613 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5614 atomic_read(&kvm_guest_has_master_clock) != 0)
5615 queue_work(system_long_wq, &pvclock_gtod_work);
5616
5617 return 0;
5618}
5619
5620static struct notifier_block pvclock_gtod_notifier = {
5621 .notifier_call = pvclock_gtod_notify,
5622};
5623#endif
5624
f8c16bba 5625int kvm_arch_init(void *opaque)
043405e1 5626{
b820cc0c 5627 int r;
6b61edf7 5628 struct kvm_x86_ops *ops = opaque;
f8c16bba 5629
f8c16bba
ZX		 5630 if (kvm_x86_ops) {
5631 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5632 r = -EEXIST;
5633 goto out;
f8c16bba
ZX		 5634 }
5635
5636 if (!ops->cpu_has_kvm_support()) {
5637 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5638 r = -EOPNOTSUPP;
5639 goto out;
f8c16bba
ZX		 5640 }
5641 if (ops->disabled_by_bios()) {
5642 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5643 r = -EOPNOTSUPP;
5644 goto out;
f8c16bba
ZX		 5645 }
5646
013f6a5d
MT		 5647 r = -ENOMEM;
5648 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5649 if (!shared_msrs) {
5650 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5651 goto out;
5652 }
5653
97db56ce
AK		 5654 r = kvm_mmu_module_init();
5655 if (r)
013f6a5d 5656 goto out_free_percpu;
97db56ce 5657
ce88decf 5658 kvm_set_mmio_spte_mask();
97db56ce 5659
f8c16bba 5660 kvm_x86_ops = ops;
920c8377 5661
7b52345e 5662 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5663 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5664
b820cc0c 5665 kvm_timer_init();
c8076604 5666
ff9d07a0
ZY		 5667 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5668
2acf923e
DC		 5669 if (cpu_has_xsave)
5670 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5671
c5cc421b 5672 kvm_lapic_init();
16e8d74d
MT		 5673#ifdef CONFIG_X86_64
5674 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5675#endif
5676
f8c16bba 5677 return 0;
56c6d28a 5678
013f6a5d
MT		 5679out_free_percpu:
5680 free_percpu(shared_msrs);
56c6d28a 5681out:
56c6d28a 5682 return r;
043405e1 5683}
8776e519 5684
f8c16bba
ZX		 5685void kvm_arch_exit(void)
5686{
ff9d07a0
ZY		 5687 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5688
888d256e
JK		 5689 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5690 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5691 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5692 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5693#ifdef CONFIG_X86_64
5694 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5695#endif
f8c16bba 5696 kvm_x86_ops = NULL;
56c6d28a 5697 kvm_mmu_module_exit();
013f6a5d 5698 free_percpu(shared_msrs);
56c6d28a 5699}
f8c16bba 5700
5cb56059 5701int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5702{
5703 ++vcpu->stat.halt_exits;
35754c98 5704 if (lapic_in_kernel(vcpu)) {
a4535290 5705 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5706 return 1;
5707 } else {
5708 vcpu->run->exit_reason = KVM_EXIT_HLT;
5709 return 0;
5710 }
5711}
5cb56059
JS		 5712EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5713
5714int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5715{
5716 kvm_x86_ops->skip_emulated_instruction(vcpu);
5717 return kvm_vcpu_halt(vcpu);
5718}
8776e519
HB		 5719EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5720
6aef266c
SV		 5721/*
5722 * kvm_pv_kick_cpu_op: Kick a vcpu.
5723 *
5724 * @apicid - apicid of vcpu to be kicked.
5725 */
5726static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5727{
24d2166b 5728 struct kvm_lapic_irq lapic_irq;
6aef266c 5729
24d2166b
R		 5730 lapic_irq.shorthand = 0;
5731 lapic_irq.dest_mode = 0;
5732 lapic_irq.dest_id = apicid;
93bbf0b8 5733 lapic_irq.msi_redir_hint = false;
6aef266c 5734
24d2166b 5735 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5736 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5737}
5738
8776e519
HB		 5739int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5740{
5741 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5742 int op_64_bit, r = 1;
8776e519 5743
5cb56059
JS		 5744 kvm_x86_ops->skip_emulated_instruction(vcpu);
5745
55cd8e5a
GN		 5746 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5747 return kvm_hv_hypercall(vcpu);
5748
5fdbf976
MT		 5749 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5750 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5751 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5752 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5753 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5754
229456fc 5755 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5756
a449c7aa
NA		 5757 op_64_bit = is_64_bit_mode(vcpu);
5758 if (!op_64_bit) {
8776e519
HB		 5759 nr &= 0xFFFFFFFF;
5760 a0 &= 0xFFFFFFFF;
5761 a1 &= 0xFFFFFFFF;
5762 a2 &= 0xFFFFFFFF;
5763 a3 &= 0xFFFFFFFF;
5764 }
5765
07708c4a
JK		 5766 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5767 ret = -KVM_EPERM;
5768 goto out;
5769 }
5770
8776e519 5771 switch (nr) {
b93463aa
AK		 5772 case KVM_HC_VAPIC_POLL_IRQ:
5773 ret = 0;
5774 break;
6aef266c
SV		 5775 case KVM_HC_KICK_CPU:
5776 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5777 ret = 0;
5778 break;
8776e519
HB		 5779 default:
5780 ret = -KVM_ENOSYS;
5781 break;
5782 }
07708c4a 5783out:
a449c7aa
NA		 5784 if (!op_64_bit)
5785 ret = (u32)ret;
5fdbf976 5786 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5787 ++vcpu->stat.hypercalls;
2f333bcb 5788 return r;
8776e519
HB		 5789}
5790EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5791
b6785def 5792static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5793{
d6aa1000 5794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5795 char instruction[3];
5fdbf976 5796 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5797
8776e519 5798 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5799
9d74191a 5800 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5801}
5802
b6c7a5dc
HB		 5803/*
5804 * Check if userspace requested an interrupt window, and that the
5805 * interrupt window is open.
5806 *
5807 * No need to exit to userspace if we already have an interrupt queued.
5808 */
851ba692 5809static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5810{
1c1a9ce9
SR		 5811 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5812 return false;
5813
5814 if (kvm_cpu_has_interrupt(vcpu))
5815 return false;
5816
5817 return (irqchip_split(vcpu->kvm)
5818 ? kvm_apic_accept_pic_intr(vcpu)
5819 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5820}
5821
851ba692 5822static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5823{
851ba692
AK		 5824 struct kvm_run *kvm_run = vcpu->run;
5825
91586a3b 5826 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5827 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5828 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5829 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5830 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5831 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5832 kvm_arch_interrupt_allowed(vcpu) &&
5833 !kvm_cpu_has_interrupt(vcpu) &&
5834 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5835 else if (!pic_in_kernel(vcpu->kvm))
5836 kvm_run->ready_for_interrupt_injection =
5837 kvm_apic_accept_pic_intr(vcpu) &&
5838 !kvm_cpu_has_interrupt(vcpu);
5839 else
5840 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5841}
5842
95ba8273
GN		 5843static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5844{
5845 int max_irr, tpr;
5846
5847 if (!kvm_x86_ops->update_cr8_intercept)
5848 return;
5849
88c808fd
AK		 5850 if (!vcpu->arch.apic)
5851 return;
5852
8db3baa2
GN		 5853 if (!vcpu->arch.apic->vapic_addr)
5854 max_irr = kvm_lapic_find_highest_irr(vcpu);
5855 else
5856 max_irr = -1;
95ba8273
GN		 5857
5858 if (max_irr != -1)
5859 max_irr >>= 4;
5860
5861 tpr = kvm_lapic_get_cr8(vcpu);
5862
5863 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5864}
5865
b6b8a145 5866static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5867{
b6b8a145
JK		 5868 int r;
5869
95ba8273 5870 /* try to reinject previous events if any */
b59bb7bd 5871 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5872 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5873 vcpu->arch.exception.has_error_code,
5874 vcpu->arch.exception.error_code);
d6e8c854
NA		 5875
5876 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5877 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5878 X86_EFLAGS_RF);
5879
6bdf0662
NA		 5880 if (vcpu->arch.exception.nr == DB_VECTOR &&
5881 (vcpu->arch.dr7 & DR7_GD)) {
5882 vcpu->arch.dr7 &= ~DR7_GD;
5883 kvm_update_dr7(vcpu);
5884 }
5885
b59bb7bd
GN		 5886 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5887 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5888 vcpu->arch.exception.error_code,
5889 vcpu->arch.exception.reinject);
b6b8a145 5890 return 0;
b59bb7bd
GN		 5891 }
5892
95ba8273
GN		 5893 if (vcpu->arch.nmi_injected) {
5894 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5895 return 0;
95ba8273
GN		 5896 }
5897
5898 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5899 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5900 return 0;
5901 }
5902
5903 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5904 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5905 if (r != 0)
5906 return r;
95ba8273
GN		 5907 }
5908
5909 /* try to inject new event if pending */
5910 if (vcpu->arch.nmi_pending) {
5911 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5912 --vcpu->arch.nmi_pending;
95ba8273
GN		 5913 vcpu->arch.nmi_injected = true;
5914 kvm_x86_ops->set_nmi(vcpu);
5915 }
c7c9c56c 5916 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5917 /*
5918 * Because interrupts can be injected asynchronously, we are
5919 * calling check_nested_events again here to avoid a race condition.
5920 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5921 * proposal and current concerns. Perhaps we should be setting
5922 * KVM_REQ_EVENT only on certain events and not unconditionally?
5923 */
5924 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5925 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5926 if (r != 0)
5927 return r;
5928 }
95ba8273 5929 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5930 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5931 false);
5932 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5933 }
5934 }
b6b8a145 5935 return 0;
95ba8273
GN		 5936}
5937
7460fb4a
AK		 5938static void process_nmi(struct kvm_vcpu *vcpu)
5939{
5940 unsigned limit = 2;
5941
5942 /*
5943 * x86 is limited to one NMI running, and one NMI pending after it.
5944 * If an NMI is already in progress, limit further NMIs to just one.
5945 * Otherwise, allow two (and we'll inject the first one immediately).
5946 */
5947 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5948 limit = 1;
5949
5950 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5951 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5952 kvm_make_request(KVM_REQ_EVENT, vcpu);
5953}
5954
660a5d51
PB		 5955#define put_smstate(type, buf, offset, val) \
5956 *(type *)((buf) + (offset) - 0x7e00) = val
5957
5958static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5959{
5960 u32 flags = 0;
5961 flags |= seg->g << 23;
5962 flags |= seg->db << 22;
5963 flags |= seg->l << 21;
5964 flags |= seg->avl << 20;
5965 flags |= seg->present << 15;
5966 flags |= seg->dpl << 13;
5967 flags |= seg->s << 12;
5968 flags |= seg->type << 8;
5969 return flags;
5970}
5971
5972static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5973{
5974 struct kvm_segment seg;
5975 int offset;
5976
5977 kvm_get_segment(vcpu, &seg, n);
5978 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5979
5980 if (n < 3)
5981 offset = 0x7f84 + n * 12;
5982 else
5983 offset = 0x7f2c + (n - 3) * 12;
5984
5985 put_smstate(u32, buf, offset + 8, seg.base);
5986 put_smstate(u32, buf, offset + 4, seg.limit);
5987 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5988}
5989
efbb288a 5990#ifdef CONFIG_X86_64
660a5d51
PB		 5991static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5992{
5993 struct kvm_segment seg;
5994 int offset;
5995 u16 flags;
5996
5997 kvm_get_segment(vcpu, &seg, n);
5998 offset = 0x7e00 + n * 16;
5999
6000 flags = process_smi_get_segment_flags(&seg) >> 8;
6001 put_smstate(u16, buf, offset, seg.selector);
6002 put_smstate(u16, buf, offset + 2, flags);
6003 put_smstate(u32, buf, offset + 4, seg.limit);
6004 put_smstate(u64, buf, offset + 8, seg.base);
6005}
efbb288a 6006#endif
660a5d51
PB		 6007
6008static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6009{
6010 struct desc_ptr dt;
6011 struct kvm_segment seg;
6012 unsigned long val;
6013 int i;
6014
6015 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6016 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6017 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6018 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6019
6020 for (i = 0; i < 8; i++)
6021 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6022
6023 kvm_get_dr(vcpu, 6, &val);
6024 put_smstate(u32, buf, 0x7fcc, (u32)val);
6025 kvm_get_dr(vcpu, 7, &val);
6026 put_smstate(u32, buf, 0x7fc8, (u32)val);
6027
6028 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6029 put_smstate(u32, buf, 0x7fc4, seg.selector);
6030 put_smstate(u32, buf, 0x7f64, seg.base);
6031 put_smstate(u32, buf, 0x7f60, seg.limit);
6032 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6033
6034 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6035 put_smstate(u32, buf, 0x7fc0, seg.selector);
6036 put_smstate(u32, buf, 0x7f80, seg.base);
6037 put_smstate(u32, buf, 0x7f7c, seg.limit);
6038 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6039
6040 kvm_x86_ops->get_gdt(vcpu, &dt);
6041 put_smstate(u32, buf, 0x7f74, dt.address);
6042 put_smstate(u32, buf, 0x7f70, dt.size);
6043
6044 kvm_x86_ops->get_idt(vcpu, &dt);
6045 put_smstate(u32, buf, 0x7f58, dt.address);
6046 put_smstate(u32, buf, 0x7f54, dt.size);
6047
6048 for (i = 0; i < 6; i++)
6049 process_smi_save_seg_32(vcpu, buf, i);
6050
6051 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6052
6053 /* revision id */
6054 put_smstate(u32, buf, 0x7efc, 0x00020000);
6055 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6056}
6057
6058static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6059{
6060#ifdef CONFIG_X86_64
6061 struct desc_ptr dt;
6062 struct kvm_segment seg;
6063 unsigned long val;
6064 int i;
6065
6066 for (i = 0; i < 16; i++)
6067 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6068
6069 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6070 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6071
6072 kvm_get_dr(vcpu, 6, &val);
6073 put_smstate(u64, buf, 0x7f68, val);
6074 kvm_get_dr(vcpu, 7, &val);
6075 put_smstate(u64, buf, 0x7f60, val);
6076
6077 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6078 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6079 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6080
6081 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6082
6083 /* revision id */
6084 put_smstate(u32, buf, 0x7efc, 0x00020064);
6085
6086 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6087
6088 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6089 put_smstate(u16, buf, 0x7e90, seg.selector);
6090 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6091 put_smstate(u32, buf, 0x7e94, seg.limit);
6092 put_smstate(u64, buf, 0x7e98, seg.base);
6093
6094 kvm_x86_ops->get_idt(vcpu, &dt);
6095 put_smstate(u32, buf, 0x7e84, dt.size);
6096 put_smstate(u64, buf, 0x7e88, dt.address);
6097
6098 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6099 put_smstate(u16, buf, 0x7e70, seg.selector);
6100 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6101 put_smstate(u32, buf, 0x7e74, seg.limit);
6102 put_smstate(u64, buf, 0x7e78, seg.base);
6103
6104 kvm_x86_ops->get_gdt(vcpu, &dt);
6105 put_smstate(u32, buf, 0x7e64, dt.size);
6106 put_smstate(u64, buf, 0x7e68, dt.address);
6107
6108 for (i = 0; i < 6; i++)
6109 process_smi_save_seg_64(vcpu, buf, i);
6110#else
6111 WARN_ON_ONCE(1);
6112#endif
6113}
6114
64d60670
PB		 6115static void process_smi(struct kvm_vcpu *vcpu)
6116{
660a5d51 6117 struct kvm_segment cs, ds;
18c3626e 6118 struct desc_ptr dt;
660a5d51
PB		 6119 char buf[512];
6120 u32 cr0;
6121
64d60670
PB		 6122 if (is_smm(vcpu)) {
6123 vcpu->arch.smi_pending = true;
6124 return;
6125 }
6126
660a5d51
PB		 6127 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6128 vcpu->arch.hflags |= HF_SMM_MASK;
6129 memset(buf, 0, 512);
6130 if (guest_cpuid_has_longmode(vcpu))
6131 process_smi_save_state_64(vcpu, buf);
6132 else
6133 process_smi_save_state_32(vcpu, buf);
6134
54bf36aa 6135 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6136
6137 if (kvm_x86_ops->get_nmi_mask(vcpu))
6138 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6139 else
6140 kvm_x86_ops->set_nmi_mask(vcpu, true);
6141
6142 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6143 kvm_rip_write(vcpu, 0x8000);
6144
6145 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6146 kvm_x86_ops->set_cr0(vcpu, cr0);
6147 vcpu->arch.cr0 = cr0;
6148
6149 kvm_x86_ops->set_cr4(vcpu, 0);
6150
18c3626e
PB		 6151 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6152 dt.address = dt.size = 0;
6153 kvm_x86_ops->set_idt(vcpu, &dt);
6154
660a5d51
PB		 6155 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6156
6157 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6158 cs.base = vcpu->arch.smbase;
6159
6160 ds.selector = 0;
6161 ds.base = 0;
6162
6163 cs.limit = ds.limit = 0xffffffff;
6164 cs.type = ds.type = 0x3;
6165 cs.dpl = ds.dpl = 0;
6166 cs.db = ds.db = 0;
6167 cs.s = ds.s = 1;
6168 cs.l = ds.l = 0;
6169 cs.g = ds.g = 1;
6170 cs.avl = ds.avl = 0;
6171 cs.present = ds.present = 1;
6172 cs.unusable = ds.unusable = 0;
6173 cs.padding = ds.padding = 0;
6174
6175 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6176 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6177 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6178 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6181
6182 if (guest_cpuid_has_longmode(vcpu))
6183 kvm_x86_ops->set_efer(vcpu, 0);
6184
6185 kvm_update_cpuid(vcpu);
6186 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6187}
6188
3d81bc7e 6189static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6190{
3d81bc7e
YZ		 6191 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6192 return;
c7c9c56c 6193
3bb345f3 6194 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6195
b053b2ae
SR		 6196 if (irqchip_split(vcpu->kvm))
6197 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6198 else
6199 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
3bb345f3 6200 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6201}
6202
a70656b6
RK		 6203static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6204{
6205 ++vcpu->stat.tlb_flush;
6206 kvm_x86_ops->tlb_flush(vcpu);
6207}
6208
4256f43f
TC		 6209void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6210{
c24ae0dc
TC		 6211 struct page *page = NULL;
6212
35754c98 6213 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6214 return;
6215
4256f43f
TC		 6216 if (!kvm_x86_ops->set_apic_access_page_addr)
6217 return;
6218
c24ae0dc 6219 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6220 if (is_error_page(page))
6221 return;
c24ae0dc
TC		 6222 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6223
6224 /*
6225 * Do not pin apic access page in memory, the MMU notifier
6226 * will call us again if it is migrated or swapped out.
6227 */
6228 put_page(page);
4256f43f
TC		 6229}
6230EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6231
fe71557a
TC		 6232void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6233 unsigned long address)
6234{
c24ae0dc
TC		 6235 /*
6236 * The physical address of apic access page is stored in the VMCS.
6237 * Update it when it becomes invalid.
6238 */
6239 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6240 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6241}
6242
9357d939 6243/*
362c698f 6244 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6245 * exiting to the userspace. Otherwise, the value will be returned to the
6246 * userspace.
6247 */
851ba692 6248static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6249{
6250 int r;
35754c98 6251 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6252 vcpu->run->request_interrupt_window;
730dca42 6253 bool req_immediate_exit = false;
b6c7a5dc 6254
3e007509 6255 if (vcpu->requests) {
a8eeb04a 6256 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6257 kvm_mmu_unload(vcpu);
a8eeb04a 6258 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6259 __kvm_migrate_timers(vcpu);
d828199e
MT		 6260 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6261 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6262 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6263 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6264 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6265 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6266 if (unlikely(r))
6267 goto out;
6268 }
a8eeb04a 6269 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6270 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6271 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6272 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6273 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6274 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6275 r = 0;
6276 goto out;
6277 }
a8eeb04a 6278 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6279 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6280 r = 0;
6281 goto out;
6282 }
a8eeb04a 6283 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6284 vcpu->fpu_active = 0;
6285 kvm_x86_ops->fpu_deactivate(vcpu);
6286 }
af585b92
GN		 6287 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6288 /* Page is swapped out. Do synthetic halt */
6289 vcpu->arch.apf.halted = true;
6290 r = 1;
6291 goto out;
6292 }
c9aaa895
GC		 6293 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6294 record_steal_time(vcpu);
64d60670
PB		 6295 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6296 process_smi(vcpu);
7460fb4a
AK		 6297 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6298 process_nmi(vcpu);
f5132b01 6299 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6300 kvm_pmu_handle_event(vcpu);
f5132b01 6301 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6302 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6303 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6304 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6305 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6306 (void *) vcpu->arch.eoi_exit_bitmap)) {
6307 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6308 vcpu->run->eoi.vector =
6309 vcpu->arch.pending_ioapic_eoi;
6310 r = 0;
6311 goto out;
6312 }
6313 }
3d81bc7e
YZ		 6314 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6315 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6316 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6317 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6318 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6319 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6320 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6321 r = 0;
6322 goto out;
6323 }
2f52d58c 6324 }
b93463aa 6325
b463a6f7 6326 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6327 kvm_apic_accept_events(vcpu);
6328 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6329 r = 1;
6330 goto out;
6331 }
6332
b6b8a145
JK		 6333 if (inject_pending_event(vcpu, req_int_win) != 0)
6334 req_immediate_exit = true;
b463a6f7 6335 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6336 else if (vcpu->arch.nmi_pending)
c9a7953f 6337 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6338 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6339 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6340
6341 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6342 /*
6343 * Update architecture specific hints for APIC
6344 * virtual interrupt delivery.
6345 */
6346 if (kvm_x86_ops->hwapic_irr_update)
6347 kvm_x86_ops->hwapic_irr_update(vcpu,
6348 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6349 update_cr8_intercept(vcpu);
6350 kvm_lapic_sync_to_vapic(vcpu);
6351 }
6352 }
6353
d8368af8
AK		 6354 r = kvm_mmu_reload(vcpu);
6355 if (unlikely(r)) {
d905c069 6356 goto cancel_injection;
d8368af8
AK		 6357 }
6358
b6c7a5dc
HB		 6359 preempt_disable();
6360
6361 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6362 if (vcpu->fpu_active)
6363 kvm_load_guest_fpu(vcpu);
2acf923e 6364 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6365
6b7e2d09
XG		 6366 vcpu->mode = IN_GUEST_MODE;
6367
01b71917
MT		 6368 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6369
6b7e2d09
XG		 6370 /* We should set ->mode before check ->requests,
6371 * see the comment in make_all_cpus_request.
6372 */
01b71917 6373 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6374
d94e1dc9 6375 local_irq_disable();
32f88400 6376
6b7e2d09 6377 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6378 || need_resched() || signal_pending(current)) {
6b7e2d09 6379 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6380 smp_wmb();
6c142801
AK		 6381 local_irq_enable();
6382 preempt_enable();
01b71917 6383 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6384 r = 1;
d905c069 6385 goto cancel_injection;
6c142801
AK		 6386 }
6387
d6185f20
NHE		 6388 if (req_immediate_exit)
6389 smp_send_reschedule(vcpu->cpu);
6390
ccf73aaf 6391 __kvm_guest_enter();
b6c7a5dc 6392
42dbaa5a 6393 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6394 set_debugreg(0, 7);
6395 set_debugreg(vcpu->arch.eff_db[0], 0);
6396 set_debugreg(vcpu->arch.eff_db[1], 1);
6397 set_debugreg(vcpu->arch.eff_db[2], 2);
6398 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6399 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6400 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6401 }
b6c7a5dc 6402
229456fc 6403 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6404 wait_lapic_expire(vcpu);
851ba692 6405 kvm_x86_ops->run(vcpu);
b6c7a5dc 6406
c77fb5fe
PB		 6407 /*
6408 * Do this here before restoring debug registers on the host. And
6409 * since we do this before handling the vmexit, a DR access vmexit
6410 * can (a) read the correct value of the debug registers, (b) set
6411 * KVM_DEBUGREG_WONT_EXIT again.
6412 */
6413 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6414 int i;
6415
6416 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6417 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6418 for (i = 0; i < KVM_NR_DB_REGS; i++)
6419 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6420 }
6421
24f1e32c
FW		 6422 /*
6423 * If the guest has used debug registers, at least dr7
6424 * will be disabled while returning to the host.
6425 * If we don't have active breakpoints in the host, we don't
6426 * care about the messed up debug address registers. But if
6427 * we have some of them active, restore the old state.
6428 */
59d8eb53 6429 if (hw_breakpoint_active())
24f1e32c 6430 hw_breakpoint_restore();
42dbaa5a 6431
886b470c 6432 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6433 rdtsc());
1d5f066e 6434
6b7e2d09 6435 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6436 smp_wmb();
a547c6db
YZ		 6437
6438 /* Interrupt is enabled by handle_external_intr() */
6439 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6440
6441 ++vcpu->stat.exits;
6442
6443 /*
6444 * We must have an instruction between local_irq_enable() and
6445 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6446 * the interrupt shadow. The stat.exits increment will do nicely.
6447 * But we need to prevent reordering, hence this barrier():
6448 */
6449 barrier();
6450
6451 kvm_guest_exit();
6452
6453 preempt_enable();
6454
f656ce01 6455 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6456
b6c7a5dc
HB		 6457 /*
6458 * Profile KVM exit RIPs:
6459 */
6460 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6461 unsigned long rip = kvm_rip_read(vcpu);
6462 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6463 }
6464
cc578287
ZA		 6465 if (unlikely(vcpu->arch.tsc_always_catchup))
6466 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6467
5cfb1d5a
MT		 6468 if (vcpu->arch.apic_attention)
6469 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6470
851ba692 6471 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6472 return r;
6473
6474cancel_injection:
6475 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6476 if (unlikely(vcpu->arch.apic_attention))
6477 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6478out:
6479 return r;
6480}
b6c7a5dc 6481
362c698f
PB		 6482static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6483{
9c8fd1ba
PB		 6484 if (!kvm_arch_vcpu_runnable(vcpu)) {
6485 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6486 kvm_vcpu_block(vcpu);
6487 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6488 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6489 return 1;
6490 }
362c698f
PB		 6491
6492 kvm_apic_accept_events(vcpu);
6493 switch(vcpu->arch.mp_state) {
6494 case KVM_MP_STATE_HALTED:
6495 vcpu->arch.pv.pv_unhalted = false;
6496 vcpu->arch.mp_state =
6497 KVM_MP_STATE_RUNNABLE;
6498 case KVM_MP_STATE_RUNNABLE:
6499 vcpu->arch.apf.halted = false;
6500 break;
6501 case KVM_MP_STATE_INIT_RECEIVED:
6502 break;
6503 default:
6504 return -EINTR;
6505 break;
6506 }
6507 return 1;
6508}
09cec754 6509
362c698f 6510static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6511{
6512 int r;
f656ce01 6513 struct kvm *kvm = vcpu->kvm;
d7690175 6514
f656ce01 6515 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6516
362c698f 6517 for (;;) {
af585b92
GN		 6518 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6519 !vcpu->arch.apf.halted)
851ba692 6520 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6521 else
6522 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6523 if (r <= 0)
6524 break;
6525
6526 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6527 if (kvm_cpu_has_pending_timer(vcpu))
6528 kvm_inject_pending_timer_irqs(vcpu);
6529
851ba692 6530 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6531 r = 0;
6532 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6533 ++vcpu->stat.request_irq_exits;
362c698f 6534 break;
09cec754 6535 }
af585b92
GN		 6536
6537 kvm_check_async_pf_completion(vcpu);
6538
09cec754
GN		 6539 if (signal_pending(current)) {
6540 r = -EINTR;
851ba692 6541 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6542 ++vcpu->stat.signal_exits;
362c698f 6543 break;
09cec754
GN		 6544 }
6545 if (need_resched()) {
f656ce01 6546 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6547 cond_resched();
f656ce01 6548 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6549 }
b6c7a5dc
HB		 6550 }
6551
f656ce01 6552 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6553
6554 return r;
6555}
6556
716d51ab
GN		 6557static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6558{
6559 int r;
6560 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6561 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6562 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6563 if (r != EMULATE_DONE)
6564 return 0;
6565 return 1;
6566}
6567
6568static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6569{
6570 BUG_ON(!vcpu->arch.pio.count);
6571
6572 return complete_emulated_io(vcpu);
6573}
6574
f78146b0
AK		 6575/*
6576 * Implements the following, as a state machine:
6577 *
6578 * read:
6579 * for each fragment
87da7e66
XG		 6580 * for each mmio piece in the fragment
6581 * write gpa, len
6582 * exit
6583 * copy data
f78146b0
AK		 6584 * execute insn
6585 *
6586 * write:
6587 * for each fragment
87da7e66
XG		 6588 * for each mmio piece in the fragment
6589 * write gpa, len
6590 * copy data
6591 * exit
f78146b0 6592 */
716d51ab 6593static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6594{
6595 struct kvm_run *run = vcpu->run;
f78146b0 6596 struct kvm_mmio_fragment *frag;
87da7e66 6597 unsigned len;
5287f194 6598
716d51ab 6599 BUG_ON(!vcpu->mmio_needed);
5287f194 6600
716d51ab 6601 /* Complete previous fragment */
87da7e66
XG		 6602 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6603 len = min(8u, frag->len);
716d51ab 6604 if (!vcpu->mmio_is_write)
87da7e66
XG		 6605 memcpy(frag->data, run->mmio.data, len);
6606
6607 if (frag->len <= 8) {
6608 /* Switch to the next fragment. */
6609 frag++;
6610 vcpu->mmio_cur_fragment++;
6611 } else {
6612 /* Go forward to the next mmio piece. */
6613 frag->data += len;
6614 frag->gpa += len;
6615 frag->len -= len;
6616 }
6617
a08d3b3b 6618 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6619 vcpu->mmio_needed = 0;
0912c977
PB		 6620
6621 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6622 if (vcpu->mmio_is_write)
716d51ab
GN		 6623 return 1;
6624 vcpu->mmio_read_completed = 1;
6625 return complete_emulated_io(vcpu);
6626 }
87da7e66 6627
716d51ab
GN		 6628 run->exit_reason = KVM_EXIT_MMIO;
6629 run->mmio.phys_addr = frag->gpa;
6630 if (vcpu->mmio_is_write)
87da7e66
XG		 6631 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6632 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6633 run->mmio.is_write = vcpu->mmio_is_write;
6634 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6635 return 0;
5287f194
AK		 6636}
6637
716d51ab 6638
b6c7a5dc
HB		 6639int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6640{
c5bedc68 6641 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6642 int r;
6643 sigset_t sigsaved;
6644
c4d72e2d 6645 fpu__activate_curr(fpu);
e5c30142 6646
ac9f6dc0
AK		 6647 if (vcpu->sigset_active)
6648 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6649
a4535290 6650 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6651 kvm_vcpu_block(vcpu);
66450a21 6652 kvm_apic_accept_events(vcpu);
d7690175 6653 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6654 r = -EAGAIN;
6655 goto out;
b6c7a5dc
HB		 6656 }
6657
b6c7a5dc 6658 /* re-sync apic's tpr */
35754c98 6659 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6660 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6661 r = -EINVAL;
6662 goto out;
6663 }
6664 }
b6c7a5dc 6665
716d51ab
GN		 6666 if (unlikely(vcpu->arch.complete_userspace_io)) {
6667 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6668 vcpu->arch.complete_userspace_io = NULL;
6669 r = cui(vcpu);
6670 if (r <= 0)
6671 goto out;
6672 } else
6673 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6674
362c698f 6675 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6676
6677out:
f1d86e46 6678 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6679 if (vcpu->sigset_active)
6680 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6681
b6c7a5dc
HB		 6682 return r;
6683}
6684
6685int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6686{
7ae441ea
GN		 6687 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6688 /*
6689 * We are here if userspace calls get_regs() in the middle of
6690 * instruction emulation. Registers state needs to be copied
4a969980 6691 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6692 * that usually, but some bad designed PV devices (vmware
6693 * backdoor interface) need this to work
6694 */
dd856efa 6695 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6696 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6697 }
5fdbf976
MT		 6698 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6699 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6700 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6701 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6702 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6703 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6704 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6705 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6706#ifdef CONFIG_X86_64
5fdbf976
MT		 6707 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6708 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6709 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6710 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6711 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6712 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6713 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6714 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6715#endif
6716
5fdbf976 6717 regs->rip = kvm_rip_read(vcpu);
91586a3b 6718 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6719
b6c7a5dc
HB		 6720 return 0;
6721}
6722
6723int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6724{
7ae441ea
GN		 6725 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6726 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6727
5fdbf976
MT		 6728 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6729 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6730 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6731 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6732 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6733 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6734 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6735 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6736#ifdef CONFIG_X86_64
5fdbf976
MT		 6737 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6738 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6739 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6740 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6741 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6742 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6743 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6744 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6745#endif
6746
5fdbf976 6747 kvm_rip_write(vcpu, regs->rip);
91586a3b 6748 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6749
b4f14abd
JK		 6750 vcpu->arch.exception.pending = false;
6751
3842d135
AK		 6752 kvm_make_request(KVM_REQ_EVENT, vcpu);
6753
b6c7a5dc
HB		 6754 return 0;
6755}
6756
b6c7a5dc
HB		 6757void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6758{
6759 struct kvm_segment cs;
6760
3e6e0aab 6761 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6762 *db = cs.db;
6763 *l = cs.l;
6764}
6765EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6766
6767int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6768 struct kvm_sregs *sregs)
6769{
89a27f4d 6770 struct desc_ptr dt;
b6c7a5dc 6771
3e6e0aab
GT		 6772 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6773 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6774 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6775 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6776 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6777 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6778
3e6e0aab
GT		 6779 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6780 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6781
6782 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6783 sregs->idt.limit = dt.size;
6784 sregs->idt.base = dt.address;
b6c7a5dc 6785 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6786 sregs->gdt.limit = dt.size;
6787 sregs->gdt.base = dt.address;
b6c7a5dc 6788
4d4ec087 6789 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6790 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6791 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6792 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6793 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6794 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6795 sregs->apic_base = kvm_get_apic_base(vcpu);
6796
923c61bb 6797 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6798
36752c9b 6799 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6800 set_bit(vcpu->arch.interrupt.nr,
6801 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6802
b6c7a5dc
HB		 6803 return 0;
6804}
6805
62d9f0db
MT		 6806int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6807 struct kvm_mp_state *mp_state)
6808{
66450a21 6809 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6810 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6811 vcpu->arch.pv.pv_unhalted)
6812 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6813 else
6814 mp_state->mp_state = vcpu->arch.mp_state;
6815
62d9f0db
MT		 6816 return 0;
6817}
6818
6819int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6820 struct kvm_mp_state *mp_state)
6821{
66450a21
JK		 6822 if (!kvm_vcpu_has_lapic(vcpu) &&
6823 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6824 return -EINVAL;
6825
6826 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6827 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6828 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6829 } else
6830 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6831 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6832 return 0;
6833}
6834
7f3d35fd
KW		 6835int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6836 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6837{
9d74191a 6838 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6839 int ret;
e01c2426 6840
8ec4722d 6841 init_emulate_ctxt(vcpu);
c697518a 6842
7f3d35fd 6843 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6844 has_error_code, error_code);
c697518a 6845
c697518a 6846 if (ret)
19d04437 6847 return EMULATE_FAIL;
37817f29 6848
9d74191a
TY		 6849 kvm_rip_write(vcpu, ctxt->eip);
6850 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6851 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6852 return EMULATE_DONE;
37817f29
IE		 6853}
6854EXPORT_SYMBOL_GPL(kvm_task_switch);
6855
b6c7a5dc
HB		 6856int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6857 struct kvm_sregs *sregs)
6858{
58cb628d 6859 struct msr_data apic_base_msr;
b6c7a5dc 6860 int mmu_reset_needed = 0;
63f42e02 6861 int pending_vec, max_bits, idx;
89a27f4d 6862 struct desc_ptr dt;
b6c7a5dc 6863
6d1068b3
PM		 6864 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6865 return -EINVAL;
6866
89a27f4d
GN		 6867 dt.size = sregs->idt.limit;
6868 dt.address = sregs->idt.base;
b6c7a5dc 6869 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6870 dt.size = sregs->gdt.limit;
6871 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6872 kvm_x86_ops->set_gdt(vcpu, &dt);
6873
ad312c7c 6874 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6875 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6876 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6877 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6878
2d3ad1f4 6879 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6880
f6801dff 6881 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6882 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6883 apic_base_msr.data = sregs->apic_base;
6884 apic_base_msr.host_initiated = true;
6885 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6886
4d4ec087 6887 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6888 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6889 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6890
fc78f519 6891 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6892 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6893 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6894 kvm_update_cpuid(vcpu);
63f42e02
XG		 6895
6896 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6897 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6898 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6899 mmu_reset_needed = 1;
6900 }
63f42e02 6901 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6902
6903 if (mmu_reset_needed)
6904 kvm_mmu_reset_context(vcpu);
6905
a50abc3b 6906 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6907 pending_vec = find_first_bit(
6908 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6909 if (pending_vec < max_bits) {
66fd3f7f 6910 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6911 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6912 }
6913
3e6e0aab
GT		 6914 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6915 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6916 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6917 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6918 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6919 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6920
3e6e0aab
GT		 6921 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6922 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6923
5f0269f5
ME		 6924 update_cr8_intercept(vcpu);
6925
9c3e4aab 6926 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6927 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6928 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6929 !is_protmode(vcpu))
9c3e4aab
MT		 6930 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6931
3842d135
AK		 6932 kvm_make_request(KVM_REQ_EVENT, vcpu);
6933
b6c7a5dc
HB		 6934 return 0;
6935}
6936
d0bfb940
JK		 6937int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6938 struct kvm_guest_debug *dbg)
b6c7a5dc 6939{
355be0b9 6940 unsigned long rflags;
ae675ef0 6941 int i, r;
b6c7a5dc 6942
4f926bf2
JK		 6943 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6944 r = -EBUSY;
6945 if (vcpu->arch.exception.pending)
2122ff5e 6946 goto out;
4f926bf2
JK		 6947 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6948 kvm_queue_exception(vcpu, DB_VECTOR);
6949 else
6950 kvm_queue_exception(vcpu, BP_VECTOR);
6951 }
6952
91586a3b
JK		 6953 /*
6954 * Read rflags as long as potentially injected trace flags are still
6955 * filtered out.
6956 */
6957 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6958
6959 vcpu->guest_debug = dbg->control;
6960 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6961 vcpu->guest_debug = 0;
6962
6963 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6964 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6965 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6966 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6967 } else {
6968 for (i = 0; i < KVM_NR_DB_REGS; i++)
6969 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6970 }
c8639010 6971 kvm_update_dr7(vcpu);
ae675ef0 6972
f92653ee
JK		 6973 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6974 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6975 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6976
91586a3b
JK		 6977 /*
6978 * Trigger an rflags update that will inject or remove the trace
6979 * flags.
6980 */
6981 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6982
c8639010 6983 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6984
4f926bf2 6985 r = 0;
d0bfb940 6986
2122ff5e 6987out:
b6c7a5dc
HB		 6988
6989 return r;
6990}
6991
8b006791
ZX		 6992/*
6993 * Translate a guest virtual address to a guest physical address.
6994 */
6995int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6996 struct kvm_translation *tr)
6997{
6998 unsigned long vaddr = tr->linear_address;
6999 gpa_t gpa;
f656ce01 7000 int idx;
8b006791 7001
f656ce01 7002 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7003 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7004 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7005 tr->physical_address = gpa;
7006 tr->valid = gpa != UNMAPPED_GVA;
7007 tr->writeable = 1;
7008 tr->usermode = 0;
8b006791
ZX		 7009
7010 return 0;
7011}
7012
d0752060
HB		 7013int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7014{
c47ada30 7015 struct fxregs_state *fxsave =
7366ed77 7016 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7017
d0752060
HB		 7018 memcpy(fpu->fpr, fxsave->st_space, 128);
7019 fpu->fcw = fxsave->cwd;
7020 fpu->fsw = fxsave->swd;
7021 fpu->ftwx = fxsave->twd;
7022 fpu->last_opcode = fxsave->fop;
7023 fpu->last_ip = fxsave->rip;
7024 fpu->last_dp = fxsave->rdp;
7025 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7026
d0752060
HB		 7027 return 0;
7028}
7029
7030int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7031{
c47ada30 7032 struct fxregs_state *fxsave =
7366ed77 7033 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7034
d0752060
HB		 7035 memcpy(fxsave->st_space, fpu->fpr, 128);
7036 fxsave->cwd = fpu->fcw;
7037 fxsave->swd = fpu->fsw;
7038 fxsave->twd = fpu->ftwx;
7039 fxsave->fop = fpu->last_opcode;
7040 fxsave->rip = fpu->last_ip;
7041 fxsave->rdp = fpu->last_dp;
7042 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7043
d0752060
HB		 7044 return 0;
7045}
7046
0ee6a517 7047static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7048{
bf935b0b 7049 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7050 if (cpu_has_xsaves)
7366ed77 7051 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7052 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7053
2acf923e
DC		 7054 /*
7055 * Ensure guest xcr0 is valid for loading
7056 */
7057 vcpu->arch.xcr0 = XSTATE_FP;
7058
ad312c7c 7059 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7060}
d0752060
HB		 7061
7062void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7063{
2608d7a1 7064 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7065 return;
7066
2acf923e
DC		 7067 /*
7068 * Restore all possible states in the guest,
7069 * and assume host would use all available bits.
7070 * Guest xcr0 would be loaded later.
7071 */
7072 kvm_put_guest_xcr0(vcpu);
d0752060 7073 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7074 __kernel_fpu_begin();
003e2e8b 7075 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7076 trace_kvm_fpu(1);
d0752060 7077}
d0752060
HB		 7078
7079void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7080{
2acf923e
DC		 7081 kvm_put_guest_xcr0(vcpu);
7082
653f52c3
RR		 7083 if (!vcpu->guest_fpu_loaded) {
7084 vcpu->fpu_counter = 0;
d0752060 7085 return;
653f52c3 7086 }
d0752060
HB		 7087
7088 vcpu->guest_fpu_loaded = 0;
4f836347 7089 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7090 __kernel_fpu_end();
f096ed85 7091 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7092 /*
7093 * If using eager FPU mode, or if the guest is a frequent user
7094 * of the FPU, just leave the FPU active for next time.
7095 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7096 * the FPU in bursts will revert to loading it on demand.
7097 */
a9b4fb7e 7098 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7099 if (++vcpu->fpu_counter < 5)
7100 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7101 }
0c04851c 7102 trace_kvm_fpu(0);
d0752060 7103}
e9b11c17
ZX		 7104
7105void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7106{
12f9a48f 7107 kvmclock_reset(vcpu);
7f1ea208 7108
f5f48ee1 7109 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7110 kvm_x86_ops->vcpu_free(vcpu);
7111}
7112
7113struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7114 unsigned int id)
7115{
c447e76b
LL		 7116 struct kvm_vcpu *vcpu;
7117
6755bae8
ZA		 7118 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7119 printk_once(KERN_WARNING
7120 "kvm: SMP vm created on host with unstable TSC; "
7121 "guest TSC will not be reliable\n");
c447e76b
LL		 7122
7123 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7124
c447e76b 7125 return vcpu;
26e5215f 7126}
e9b11c17 7127
26e5215f
AK		 7128int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7129{
7130 int r;
e9b11c17 7131
19efffa2 7132 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7133 r = vcpu_load(vcpu);
7134 if (r)
7135 return r;
d28bc9dd 7136 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7137 kvm_mmu_setup(vcpu);
e9b11c17 7138 vcpu_put(vcpu);
26e5215f 7139 return r;
e9b11c17
ZX		 7140}
7141
31928aa5 7142void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7143{
8fe8ab46 7144 struct msr_data msr;
332967a3 7145 struct kvm *kvm = vcpu->kvm;
42897d86 7146
31928aa5
DD		 7147 if (vcpu_load(vcpu))
7148 return;
8fe8ab46
WA		 7149 msr.data = 0x0;
7150 msr.index = MSR_IA32_TSC;
7151 msr.host_initiated = true;
7152 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7153 vcpu_put(vcpu);
7154
630994b3
MT		 7155 if (!kvmclock_periodic_sync)
7156 return;
7157
332967a3
AJ		 7158 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7159 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7160}
7161
d40ccc62 7162void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7163{
9fc77441 7164 int r;
344d9588
GN		 7165 vcpu->arch.apf.msr_val = 0;
7166
9fc77441
MT		 7167 r = vcpu_load(vcpu);
7168 BUG_ON(r);
e9b11c17
ZX		 7169 kvm_mmu_unload(vcpu);
7170 vcpu_put(vcpu);
7171
7172 kvm_x86_ops->vcpu_free(vcpu);
7173}
7174
d28bc9dd 7175void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7176{
e69fab5d
PB		 7177 vcpu->arch.hflags = 0;
7178
7460fb4a
AK		 7179 atomic_set(&vcpu->arch.nmi_queued, 0);
7180 vcpu->arch.nmi_pending = 0;
448fa4a9 7181 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7182 kvm_clear_interrupt_queue(vcpu);
7183 kvm_clear_exception_queue(vcpu);
448fa4a9 7184
42dbaa5a 7185 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7186 kvm_update_dr0123(vcpu);
6f43ed01 7187 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7188 kvm_update_dr6(vcpu);
42dbaa5a 7189 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7190 kvm_update_dr7(vcpu);
42dbaa5a 7191
1119022c
NA		 7192 vcpu->arch.cr2 = 0;
7193
3842d135 7194 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7195 vcpu->arch.apf.msr_val = 0;
c9aaa895 7196 vcpu->arch.st.msr_val = 0;
3842d135 7197
12f9a48f
GC		 7198 kvmclock_reset(vcpu);
7199
af585b92
GN		 7200 kvm_clear_async_pf_completion_queue(vcpu);
7201 kvm_async_pf_hash_reset(vcpu);
7202 vcpu->arch.apf.halted = false;
3842d135 7203
64d60670 7204 if (!init_event) {
d28bc9dd 7205 kvm_pmu_reset(vcpu);
64d60670
PB		 7206 vcpu->arch.smbase = 0x30000;
7207 }
f5132b01 7208
66f7b72e
JS		 7209 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7210 vcpu->arch.regs_avail = ~0;
7211 vcpu->arch.regs_dirty = ~0;
7212
d28bc9dd 7213 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7214}
7215
2b4a273b 7216void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7217{
7218 struct kvm_segment cs;
7219
7220 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7221 cs.selector = vector << 8;
7222 cs.base = vector << 12;
7223 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7224 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7225}
7226
13a34e06 7227int kvm_arch_hardware_enable(void)
e9b11c17 7228{
ca84d1a2
ZA		 7229 struct kvm *kvm;
7230 struct kvm_vcpu *vcpu;
7231 int i;
0dd6a6ed
ZA		 7232 int ret;
7233 u64 local_tsc;
7234 u64 max_tsc = 0;
7235 bool stable, backwards_tsc = false;
18863bdd
AK		 7236
7237 kvm_shared_msr_cpu_online();
13a34e06 7238 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7239 if (ret != 0)
7240 return ret;
7241
4ea1636b 7242 local_tsc = rdtsc();
0dd6a6ed
ZA		 7243 stable = !check_tsc_unstable();
7244 list_for_each_entry(kvm, &vm_list, vm_list) {
7245 kvm_for_each_vcpu(i, vcpu, kvm) {
7246 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7247 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7248 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7249 backwards_tsc = true;
7250 if (vcpu->arch.last_host_tsc > max_tsc)
7251 max_tsc = vcpu->arch.last_host_tsc;
7252 }
7253 }
7254 }
7255
7256 /*
7257 * Sometimes, even reliable TSCs go backwards. This happens on
7258 * platforms that reset TSC during suspend or hibernate actions, but
7259 * maintain synchronization. We must compensate. Fortunately, we can
7260 * detect that condition here, which happens early in CPU bringup,
7261 * before any KVM threads can be running. Unfortunately, we can't
7262 * bring the TSCs fully up to date with real time, as we aren't yet far
7263 * enough into CPU bringup that we know how much real time has actually
7264 * elapsed; our helper function, get_kernel_ns() will be using boot
7265 * variables that haven't been updated yet.
7266 *
7267 * So we simply find the maximum observed TSC above, then record the
7268 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7269 * the adjustment will be applied. Note that we accumulate
7270 * adjustments, in case multiple suspend cycles happen before some VCPU
7271 * gets a chance to run again. In the event that no KVM threads get a
7272 * chance to run, we will miss the entire elapsed period, as we'll have
7273 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7274 * loose cycle time. This isn't too big a deal, since the loss will be
7275 * uniform across all VCPUs (not to mention the scenario is extremely
7276 * unlikely). It is possible that a second hibernate recovery happens
7277 * much faster than a first, causing the observed TSC here to be
7278 * smaller; this would require additional padding adjustment, which is
7279 * why we set last_host_tsc to the local tsc observed here.
7280 *
7281 * N.B. - this code below runs only on platforms with reliable TSC,
7282 * as that is the only way backwards_tsc is set above. Also note
7283 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7284 * have the same delta_cyc adjustment applied if backwards_tsc
7285 * is detected. Note further, this adjustment is only done once,
7286 * as we reset last_host_tsc on all VCPUs to stop this from being
7287 * called multiple times (one for each physical CPU bringup).
7288 *
4a969980 7289 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7290 * will be compensated by the logic in vcpu_load, which sets the TSC to
7291 * catchup mode. This will catchup all VCPUs to real time, but cannot
7292 * guarantee that they stay in perfect synchronization.
7293 */
7294 if (backwards_tsc) {
7295 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7296 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7297 list_for_each_entry(kvm, &vm_list, vm_list) {
7298 kvm_for_each_vcpu(i, vcpu, kvm) {
7299 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7300 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7301 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7302 }
7303
7304 /*
7305 * We have to disable TSC offset matching.. if you were
7306 * booting a VM while issuing an S4 host suspend....
7307 * you may have some problem. Solving this issue is
7308 * left as an exercise to the reader.
7309 */
7310 kvm->arch.last_tsc_nsec = 0;
7311 kvm->arch.last_tsc_write = 0;
7312 }
7313
7314 }
7315 return 0;
e9b11c17
ZX		 7316}
7317
13a34e06 7318void kvm_arch_hardware_disable(void)
e9b11c17 7319{
13a34e06
RK		 7320 kvm_x86_ops->hardware_disable();
7321 drop_user_return_notifiers();
e9b11c17
ZX		 7322}
7323
7324int kvm_arch_hardware_setup(void)
7325{
9e9c3fe4
NA		 7326 int r;
7327
7328 r = kvm_x86_ops->hardware_setup();
7329 if (r != 0)
7330 return r;
7331
7332 kvm_init_msr_list();
7333 return 0;
e9b11c17
ZX		 7334}
7335
7336void kvm_arch_hardware_unsetup(void)
7337{
7338 kvm_x86_ops->hardware_unsetup();
7339}
7340
7341void kvm_arch_check_processor_compat(void *rtn)
7342{
7343 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7344}
7345
7346bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7347{
7348 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7349}
7350EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7351
7352bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7353{
7354 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7355}
7356
3e515705
AK		 7357bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7358{
35754c98 7359 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7360}
7361
54e9818f
GN		 7362struct static_key kvm_no_apic_vcpu __read_mostly;
7363
e9b11c17
ZX		 7364int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7365{
7366 struct page *page;
7367 struct kvm *kvm;
7368 int r;
7369
7370 BUG_ON(vcpu->kvm == NULL);
7371 kvm = vcpu->kvm;
7372
6aef266c 7373 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7374 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7375 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7376 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7377 else
a4535290 7378 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7379
7380 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7381 if (!page) {
7382 r = -ENOMEM;
7383 goto fail;
7384 }
ad312c7c 7385 vcpu->arch.pio_data = page_address(page);
e9b11c17 7386
cc578287 7387 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7388
e9b11c17
ZX		 7389 r = kvm_mmu_create(vcpu);
7390 if (r < 0)
7391 goto fail_free_pio_data;
7392
7393 if (irqchip_in_kernel(kvm)) {
7394 r = kvm_create_lapic(vcpu);
7395 if (r < 0)
7396 goto fail_mmu_destroy;
54e9818f
GN		 7397 } else
7398 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7399
890ca9ae
HY		 7400 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7401 GFP_KERNEL);
7402 if (!vcpu->arch.mce_banks) {
7403 r = -ENOMEM;
443c39bc 7404 goto fail_free_lapic;
890ca9ae
HY		 7405 }
7406 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7407
f1797359
WY		 7408 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7409 r = -ENOMEM;
f5f48ee1 7410 goto fail_free_mce_banks;
f1797359 7411 }
f5f48ee1 7412
0ee6a517 7413 fx_init(vcpu);
66f7b72e 7414
ba904635 7415 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7416 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7417
7418 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7419 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7420
5a4f55cd
EK		 7421 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7422
74545705
RK		 7423 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7424
af585b92 7425 kvm_async_pf_hash_reset(vcpu);
f5132b01 7426 kvm_pmu_init(vcpu);
af585b92 7427
1c1a9ce9
SR		 7428 vcpu->arch.pending_external_vector = -1;
7429
e9b11c17 7430 return 0;
0ee6a517 7431
f5f48ee1
SY		 7432fail_free_mce_banks:
7433 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7434fail_free_lapic:
7435 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7436fail_mmu_destroy:
7437 kvm_mmu_destroy(vcpu);
7438fail_free_pio_data:
ad312c7c 7439 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7440fail:
7441 return r;
7442}
7443
7444void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7445{
f656ce01
MT		 7446 int idx;
7447
f5132b01 7448 kvm_pmu_destroy(vcpu);
36cb93fd 7449 kfree(vcpu->arch.mce_banks);
e9b11c17 7450 kvm_free_lapic(vcpu);
f656ce01 7451 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7452 kvm_mmu_destroy(vcpu);
f656ce01 7453 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7454 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7455 if (!lapic_in_kernel(vcpu))
54e9818f 7456 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7457}
d19a9cd2 7458
e790d9ef
RK		 7459void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7460{
ae97a3b8 7461 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7462}
7463
e08b9637 7464int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7465{
e08b9637
CO		 7466 if (type)
7467 return -EINVAL;
7468
6ef768fa 7469 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7470 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7471 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7472 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7473 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7474
5550af4d
SY		 7475 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7476 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7477 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7478 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7479 &kvm->arch.irq_sources_bitmap);
5550af4d 7480
038f8c11 7481 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7482 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7483 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7484
7485 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7486
7e44e449 7487 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7488 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7489
d89f5eff 7490 return 0;
d19a9cd2
ZX		 7491}
7492
7493static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7494{
9fc77441
MT		 7495 int r;
7496 r = vcpu_load(vcpu);
7497 BUG_ON(r);
d19a9cd2
ZX		 7498 kvm_mmu_unload(vcpu);
7499 vcpu_put(vcpu);
7500}
7501
7502static void kvm_free_vcpus(struct kvm *kvm)
7503{
7504 unsigned int i;
988a2cae 7505 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7506
7507 /*
7508 * Unpin any mmu pages first.
7509 */
af585b92
GN		 7510 kvm_for_each_vcpu(i, vcpu, kvm) {
7511 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7512 kvm_unload_vcpu_mmu(vcpu);
af585b92 7513 }
988a2cae
GN		 7514 kvm_for_each_vcpu(i, vcpu, kvm)
7515 kvm_arch_vcpu_free(vcpu);
7516
7517 mutex_lock(&kvm->lock);
7518 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7519 kvm->vcpus[i] = NULL;
d19a9cd2 7520
988a2cae
GN		 7521 atomic_set(&kvm->online_vcpus, 0);
7522 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7523}
7524
ad8ba2cd
SY		 7525void kvm_arch_sync_events(struct kvm *kvm)
7526{
332967a3 7527 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7528 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7529 kvm_free_all_assigned_devices(kvm);
aea924f6 7530 kvm_free_pit(kvm);
ad8ba2cd
SY		 7531}
7532
9da0e4d5
PB		 7533int __x86_set_memory_region(struct kvm *kvm,
7534 const struct kvm_userspace_memory_region *mem)
7535{
7536 int i, r;
7537
7538 /* Called with kvm->slots_lock held. */
7539 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7540
7541 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7542 struct kvm_userspace_memory_region m = *mem;
7543
7544 m.slot |= i << 16;
7545 r = __kvm_set_memory_region(kvm, &m);
7546 if (r < 0)
7547 return r;
7548 }
7549
7550 return 0;
7551}
7552EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7553
7554int x86_set_memory_region(struct kvm *kvm,
7555 const struct kvm_userspace_memory_region *mem)
7556{
7557 int r;
7558
7559 mutex_lock(&kvm->slots_lock);
7560 r = __x86_set_memory_region(kvm, mem);
7561 mutex_unlock(&kvm->slots_lock);
7562
7563 return r;
7564}
7565EXPORT_SYMBOL_GPL(x86_set_memory_region);
7566
d19a9cd2
ZX		 7567void kvm_arch_destroy_vm(struct kvm *kvm)
7568{
27469d29
AH		 7569 if (current->mm == kvm->mm) {
7570 /*
7571 * Free memory regions allocated on behalf of userspace,
7572 * unless the the memory map has changed due to process exit
7573 * or fd copying.
7574 */
7575 struct kvm_userspace_memory_region mem;
7576 memset(&mem, 0, sizeof(mem));
7577 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7578 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7579
7580 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7581 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7582
7583 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7584 x86_set_memory_region(kvm, &mem);
27469d29 7585 }
6eb55818 7586 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7587 kfree(kvm->arch.vpic);
7588 kfree(kvm->arch.vioapic);
d19a9cd2 7589 kvm_free_vcpus(kvm);
1e08ec4a 7590 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7591}
0de10343 7592
5587027c 7593void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7594 struct kvm_memory_slot *dont)
7595{
7596 int i;
7597
d89cc617
TY		 7598 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7599 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7600 kvfree(free->arch.rmap[i]);
d89cc617 7601 free->arch.rmap[i] = NULL;
77d11309 7602 }
d89cc617
TY		 7603 if (i == 0)
7604 continue;
7605
7606 if (!dont || free->arch.lpage_info[i - 1] !=
7607 dont->arch.lpage_info[i - 1]) {
548ef284 7608 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7609 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7610 }
7611 }
7612}
7613
5587027c
AK		 7614int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7615 unsigned long npages)
db3fe4eb
TY		 7616{
7617 int i;
7618
d89cc617 7619 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7620 unsigned long ugfn;
7621 int lpages;
d89cc617 7622 int level = i + 1;
db3fe4eb
TY		 7623
7624 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7625 slot->base_gfn, level) + 1;
7626
d89cc617
TY		 7627 slot->arch.rmap[i] =
7628 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7629 if (!slot->arch.rmap[i])
77d11309 7630 goto out_free;
d89cc617
TY		 7631 if (i == 0)
7632 continue;
77d11309 7633
d89cc617
TY		 7634 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7635 sizeof(*slot->arch.lpage_info[i - 1]));
7636 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7637 goto out_free;
7638
7639 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7640 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7641 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7642 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7643 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7644 /*
7645 * If the gfn and userspace address are not aligned wrt each
7646 * other, or if explicitly asked to, disable large page
7647 * support for this slot
7648 */
7649 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7650 !kvm_largepages_enabled()) {
7651 unsigned long j;
7652
7653 for (j = 0; j < lpages; ++j)
d89cc617 7654 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7655 }
7656 }
7657
7658 return 0;
7659
7660out_free:
d89cc617 7661 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7662 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7663 slot->arch.rmap[i] = NULL;
7664 if (i == 0)
7665 continue;
7666
548ef284 7667 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7668 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7669 }
7670 return -ENOMEM;
7671}
7672
15f46015 7673void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7674{
e6dff7d1
TY		 7675 /*
7676 * memslots->generation has been incremented.
7677 * mmio generation may have reached its maximum value.
7678 */
54bf36aa 7679 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7680}
7681
f7784b8e
MT		 7682int kvm_arch_prepare_memory_region(struct kvm *kvm,
7683 struct kvm_memory_slot *memslot,
09170a49 7684 const struct kvm_userspace_memory_region *mem,
7b6195a9 7685 enum kvm_mr_change change)
0de10343 7686{
7a905b14
TY		 7687 /*
7688 * Only private memory slots need to be mapped here since
7689 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7690 */
7b6195a9 7691 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7692 unsigned long userspace_addr;
604b38ac 7693
7a905b14
TY		 7694 /*
7695 * MAP_SHARED to prevent internal slot pages from being moved
7696 * by fork()/COW.
7697 */
7b6195a9 7698 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7699 PROT_READ | PROT_WRITE,
7700 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7701
7a905b14
TY		 7702 if (IS_ERR((void *)userspace_addr))
7703 return PTR_ERR((void *)userspace_addr);
604b38ac 7704
7a905b14 7705 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7706 }
7707
f7784b8e
MT		 7708 return 0;
7709}
7710
88178fd4
KH		 7711static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7712 struct kvm_memory_slot *new)
7713{
7714 /* Still write protect RO slot */
7715 if (new->flags & KVM_MEM_READONLY) {
7716 kvm_mmu_slot_remove_write_access(kvm, new);
7717 return;
7718 }
7719
7720 /*
7721 * Call kvm_x86_ops dirty logging hooks when they are valid.
7722 *
7723 * kvm_x86_ops->slot_disable_log_dirty is called when:
7724 *
7725 * - KVM_MR_CREATE with dirty logging is disabled
7726 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7727 *
7728 * The reason is, in case of PML, we need to set D-bit for any slots
7729 * with dirty logging disabled in order to eliminate unnecessary GPA
7730 * logging in PML buffer (and potential PML buffer full VMEXT). This
7731 * guarantees leaving PML enabled during guest's lifetime won't have
7732 * any additonal overhead from PML when guest is running with dirty
7733 * logging disabled for memory slots.
7734 *
7735 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7736 * to dirty logging mode.
7737 *
7738 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7739 *
7740 * In case of write protect:
7741 *
7742 * Write protect all pages for dirty logging.
7743 *
7744 * All the sptes including the large sptes which point to this
7745 * slot are set to readonly. We can not create any new large
7746 * spte on this slot until the end of the logging.
7747 *
7748 * See the comments in fast_page_fault().
7749 */
7750 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7751 if (kvm_x86_ops->slot_enable_log_dirty)
7752 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7753 else
7754 kvm_mmu_slot_remove_write_access(kvm, new);
7755 } else {
7756 if (kvm_x86_ops->slot_disable_log_dirty)
7757 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7758 }
7759}
7760
f7784b8e 7761void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7762 const struct kvm_userspace_memory_region *mem,
8482644a 7763 const struct kvm_memory_slot *old,
f36f3f28 7764 const struct kvm_memory_slot *new,
8482644a 7765 enum kvm_mr_change change)
f7784b8e 7766{
8482644a 7767 int nr_mmu_pages = 0;
f7784b8e 7768
f36f3f28 7769 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7770 int ret;
7771
8482644a
TY		 7772 ret = vm_munmap(old->userspace_addr,
7773 old->npages * PAGE_SIZE);
f7784b8e
MT		 7774 if (ret < 0)
7775 printk(KERN_WARNING
7776 "kvm_vm_ioctl_set_memory_region: "
7777 "failed to munmap memory\n");
7778 }
7779
48c0e4e9
XG		 7780 if (!kvm->arch.n_requested_mmu_pages)
7781 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7782
48c0e4e9 7783 if (nr_mmu_pages)
0de10343 7784 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7785
3ea3b7fa
WL		 7786 /*
7787 * Dirty logging tracks sptes in 4k granularity, meaning that large
7788 * sptes have to be split. If live migration is successful, the guest
7789 * in the source machine will be destroyed and large sptes will be
7790 * created in the destination. However, if the guest continues to run
7791 * in the source machine (for example if live migration fails), small
7792 * sptes will remain around and cause bad performance.
7793 *
7794 * Scan sptes if dirty logging has been stopped, dropping those
7795 * which can be collapsed into a single large-page spte. Later
7796 * page faults will create the large-page sptes.
7797 */
7798 if ((change != KVM_MR_DELETE) &&
7799 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7800 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7801 kvm_mmu_zap_collapsible_sptes(kvm, new);
7802
c972f3b1 7803 /*
88178fd4 7804 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7805 *
88178fd4
KH		 7806 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7807 * been zapped so no dirty logging staff is needed for old slot. For
7808 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7809 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7810 *
7811 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7812 */
88178fd4 7813 if (change != KVM_MR_DELETE)
f36f3f28 7814 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7815}
1d737c8a 7816
2df72e9b 7817void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7818{
6ca18b69 7819 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7820}
7821
2df72e9b
MT		 7822void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7823 struct kvm_memory_slot *slot)
7824{
6ca18b69 7825 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7826}
7827
1d737c8a
ZX		 7828int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7829{
b6b8a145
JK		 7830 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7831 kvm_x86_ops->check_nested_events(vcpu, false);
7832
af585b92
GN		 7833 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7834 !vcpu->arch.apf.halted)
7835 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7836 || kvm_apic_has_events(vcpu)
6aef266c 7837 || vcpu->arch.pv.pv_unhalted
7460fb4a 7838 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7839 (kvm_arch_interrupt_allowed(vcpu) &&
7840 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7841}
5736199a 7842
b6d33834 7843int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7844{
b6d33834 7845 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7846}
78646121
GN		 7847
7848int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7849{
7850 return kvm_x86_ops->interrupt_allowed(vcpu);
7851}
229456fc 7852
82b32774 7853unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7854{
82b32774
NA		 7855 if (is_64_bit_mode(vcpu))
7856 return kvm_rip_read(vcpu);
7857 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7858 kvm_rip_read(vcpu));
7859}
7860EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7861
82b32774
NA		 7862bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7863{
7864 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7865}
7866EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7867
94fe45da
JK		 7868unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7869{
7870 unsigned long rflags;
7871
7872 rflags = kvm_x86_ops->get_rflags(vcpu);
7873 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7874 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7875 return rflags;
7876}
7877EXPORT_SYMBOL_GPL(kvm_get_rflags);
7878
6addfc42 7879static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7880{
7881 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7882 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7883 rflags |= X86_EFLAGS_TF;
94fe45da 7884 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7885}
7886
7887void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7888{
7889 __kvm_set_rflags(vcpu, rflags);
3842d135 7890 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7891}
7892EXPORT_SYMBOL_GPL(kvm_set_rflags);
7893
56028d08
GN		 7894void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7895{
7896 int r;
7897
fb67e14f 7898 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7899 work->wakeup_all)
56028d08
GN		 7900 return;
7901
7902 r = kvm_mmu_reload(vcpu);
7903 if (unlikely(r))
7904 return;
7905
fb67e14f
XG		 7906 if (!vcpu->arch.mmu.direct_map &&
7907 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7908 return;
7909
56028d08
GN		 7910 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7911}
7912
af585b92
GN		 7913static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7914{
7915 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7916}
7917
7918static inline u32 kvm_async_pf_next_probe(u32 key)
7919{
7920 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7921}
7922
7923static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7924{
7925 u32 key = kvm_async_pf_hash_fn(gfn);
7926
7927 while (vcpu->arch.apf.gfns[key] != ~0)
7928 key = kvm_async_pf_next_probe(key);
7929
7930 vcpu->arch.apf.gfns[key] = gfn;
7931}
7932
7933static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7934{
7935 int i;
7936 u32 key = kvm_async_pf_hash_fn(gfn);
7937
7938 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7939 (vcpu->arch.apf.gfns[key] != gfn &&
7940 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7941 key = kvm_async_pf_next_probe(key);
7942
7943 return key;
7944}
7945
7946bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7947{
7948 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7949}
7950
7951static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7952{
7953 u32 i, j, k;
7954
7955 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7956 while (true) {
7957 vcpu->arch.apf.gfns[i] = ~0;
7958 do {
7959 j = kvm_async_pf_next_probe(j);
7960 if (vcpu->arch.apf.gfns[j] == ~0)
7961 return;
7962 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7963 /*
7964 * k lies cyclically in ]i,j]
7965 * | i.k.j |
7966 * |....j i.k.| or |.k..j i...|
7967 */
7968 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7969 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7970 i = j;
7971 }
7972}
7973
7c90705b
GN		 7974static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7975{
7976
7977 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7978 sizeof(val));
7979}
7980
af585b92
GN		 7981void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7982 struct kvm_async_pf *work)
7983{
6389ee94
AK		 7984 struct x86_exception fault;
7985
7c90705b 7986 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7987 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7988
7989 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7990 (vcpu->arch.apf.send_user_only &&
7991 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7992 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7993 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7994 fault.vector = PF_VECTOR;
7995 fault.error_code_valid = true;
7996 fault.error_code = 0;
7997 fault.nested_page_fault = false;
7998 fault.address = work->arch.token;
7999 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8000 }
af585b92
GN		 8001}
8002
8003void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8004 struct kvm_async_pf *work)
8005{
6389ee94
AK		 8006 struct x86_exception fault;
8007
7c90705b 8008 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8009 if (work->wakeup_all)
7c90705b
GN		 8010 work->arch.token = ~0; /* broadcast wakeup */
8011 else
8012 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8013
8014 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8015 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8016 fault.vector = PF_VECTOR;
8017 fault.error_code_valid = true;
8018 fault.error_code = 0;
8019 fault.nested_page_fault = false;
8020 fault.address = work->arch.token;
8021 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8022 }
e6d53e3b 8023 vcpu->arch.apf.halted = false;
a4fa1635 8024 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8025}
8026
8027bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8028{
8029 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8030 return true;
8031 else
8032 return !kvm_event_needs_reinjection(vcpu) &&
8033 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8034}
8035
5544eb9b
PB		 8036void kvm_arch_start_assignment(struct kvm *kvm)
8037{
8038 atomic_inc(&kvm->arch.assigned_device_count);
8039}
8040EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8041
8042void kvm_arch_end_assignment(struct kvm *kvm)
8043{
8044 atomic_dec(&kvm->arch.assigned_device_count);
8045}
8046EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8047
8048bool kvm_arch_has_assigned_device(struct kvm *kvm)
8049{
8050 return atomic_read(&kvm->arch.assigned_device_count);
8051}
8052EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8053
e0f0bbc5
AW		 8054void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8055{
8056 atomic_inc(&kvm->arch.noncoherent_dma_count);
8057}
8058EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8059
8060void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8061{
8062 atomic_dec(&kvm->arch.noncoherent_dma_count);
8063}
8064EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8065
8066bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8067{
8068 return atomic_read(&kvm->arch.noncoherent_dma_count);
8069}
8070EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8071
229456fc
MT		 8072EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8073EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8074EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8075EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8076EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8077EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8078EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8079EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8080EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8081EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8082EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8083EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8084EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8085EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
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