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Merge branch 'kvm-ppc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
2acf923e 703 vcpu->arch.xcr0 = xcr0;
56c103ec 704
d91cab78 705 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 706 kvm_update_cpuid(vcpu);
2acf923e
DC		 707 return 0;
708}
709
710int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
711{
764bcbc5
Z		 712 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
713 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 714 kvm_inject_gp(vcpu, 0);
715 return 1;
716 }
717 return 0;
718}
719EXPORT_SYMBOL_GPL(kvm_set_xcr);
720
a83b29c6 721int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 722{
fc78f519 723 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 724 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 725 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 726
0f12244f
GN		 727 if (cr4 & CR4_RESERVED_BITS)
728 return 1;
a03490ed 729
2acf923e
DC		 730 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
731 return 1;
732
c68b734f
YW		 733 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
734 return 1;
735
97ec8c06
FW		 736 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
737 return 1;
738
afcbf13f 739 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 740 return 1;
741
b9baba86
HH		 742 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
743 return 1;
744
a03490ed 745 if (is_long_mode(vcpu)) {
0f12244f
GN		 746 if (!(cr4 & X86_CR4_PAE))
747 return 1;
a2edf57f
AK		 748 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
749 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 750 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
751 kvm_read_cr3(vcpu)))
0f12244f
GN		 752 return 1;
753
ad756a16
MJ		 754 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
755 if (!guest_cpuid_has_pcid(vcpu))
756 return 1;
757
758 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
759 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
760 return 1;
761 }
762
5e1746d6 763 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 764 return 1;
a03490ed 765
ad756a16
MJ		 766 if (((cr4 ^ old_cr4) & pdptr_bits) ||
767 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 768 kvm_mmu_reset_context(vcpu);
0f12244f 769
b9baba86 770 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 771 kvm_update_cpuid(vcpu);
2acf923e 772
0f12244f
GN		 773 return 0;
774}
2d3ad1f4 775EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 776
2390218b 777int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 778{
ac146235 779#ifdef CONFIG_X86_64
9d88fca7 780 cr3 &= ~CR3_PCID_INVD;
ac146235 781#endif
9d88fca7 782
9f8fe504 783 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 784 kvm_mmu_sync_roots(vcpu);
77c3913b 785 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 786 return 0;
d835dfec
AK		 787 }
788
a03490ed 789 if (is_long_mode(vcpu)) {
d9f89b88
JK		 790 if (cr3 & CR3_L_MODE_RESERVED_BITS)
791 return 1;
792 } else if (is_pae(vcpu) && is_paging(vcpu) &&
793 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 794 return 1;
a03490ed 795
0f12244f 796 vcpu->arch.cr3 = cr3;
aff48baa 797 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 798 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 802
eea1cff9 803int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 804{
0f12244f
GN		 805 if (cr8 & CR8_RESERVED_BITS)
806 return 1;
35754c98 807 if (lapic_in_kernel(vcpu))
a03490ed
CO		 808 kvm_lapic_set_tpr(vcpu, cr8);
809 else
ad312c7c 810 vcpu->arch.cr8 = cr8;
0f12244f
GN		 811 return 0;
812}
2d3ad1f4 813EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 814
2d3ad1f4 815unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 816{
35754c98 817 if (lapic_in_kernel(vcpu))
a03490ed
CO		 818 return kvm_lapic_get_cr8(vcpu);
819 else
ad312c7c 820 return vcpu->arch.cr8;
a03490ed 821}
2d3ad1f4 822EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 823
ae561ede
NA		 824static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
825{
826 int i;
827
828 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
829 for (i = 0; i < KVM_NR_DB_REGS; i++)
830 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
831 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
832 }
833}
834
73aaf249
JK		 835static void kvm_update_dr6(struct kvm_vcpu *vcpu)
836{
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
839}
840
c8639010
JK		 841static void kvm_update_dr7(struct kvm_vcpu *vcpu)
842{
843 unsigned long dr7;
844
845 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
846 dr7 = vcpu->arch.guest_debug_dr7;
847 else
848 dr7 = vcpu->arch.dr7;
849 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 850 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
851 if (dr7 & DR7_BP_EN_MASK)
852 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 853}
854
6f43ed01
NA		 855static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
856{
857 u64 fixed = DR6_FIXED_1;
858
859 if (!guest_cpuid_has_rtm(vcpu))
860 fixed |= DR6_RTM;
861 return fixed;
862}
863
338dbc97 864static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 865{
866 switch (dr) {
867 case 0 ... 3:
868 vcpu->arch.db[dr] = val;
869 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
870 vcpu->arch.eff_db[dr] = val;
871 break;
872 case 4:
020df079
GN		 873 /* fall through */
874 case 6:
338dbc97
GN		 875 if (val & 0xffffffff00000000ULL)
876 return -1; /* #GP */
6f43ed01 877 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 878 kvm_update_dr6(vcpu);
020df079
GN		 879 break;
880 case 5:
020df079
GN		 881 /* fall through */
882 default: /* 7 */
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
020df079 885 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 886 kvm_update_dr7(vcpu);
020df079
GN		 887 break;
888 }
889
890 return 0;
891}
338dbc97
GN		 892
893int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
894{
16f8a6f9 895 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 896 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 897 return 1;
898 }
899 return 0;
338dbc97 900}
020df079
GN		 901EXPORT_SYMBOL_GPL(kvm_set_dr);
902
16f8a6f9 903int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 904{
905 switch (dr) {
906 case 0 ... 3:
907 *val = vcpu->arch.db[dr];
908 break;
909 case 4:
020df079
GN		 910 /* fall through */
911 case 6:
73aaf249
JK		 912 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
913 *val = vcpu->arch.dr6;
914 else
915 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 916 break;
917 case 5:
020df079
GN		 918 /* fall through */
919 default: /* 7 */
920 *val = vcpu->arch.dr7;
921 break;
922 }
338dbc97
GN		 923 return 0;
924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_get_dr);
926
022cd0e8
AK		 927bool kvm_rdpmc(struct kvm_vcpu *vcpu)
928{
929 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
930 u64 data;
931 int err;
932
c6702c9d 933 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 934 if (err)
935 return err;
936 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
937 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
938 return err;
939}
940EXPORT_SYMBOL_GPL(kvm_rdpmc);
941
043405e1
CO		 942/*
943 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
944 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
945 *
946 * This list is modified at module load time to reflect the
e3267cbb 947 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 948 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
949 * may depend on host virtualization features rather than host cpu features.
043405e1 950 */
e3267cbb 951
043405e1
CO		 952static u32 msrs_to_save[] = {
953 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 954 MSR_STAR,
043405e1
CO		 955#ifdef CONFIG_X86_64
956 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
957#endif
b3897a49 958 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 959 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 960};
961
962static unsigned num_msrs_to_save;
963
62ef68bb
PB		 964static u32 emulated_msrs[] = {
965 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
966 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
967 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
968 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 969 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
970 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 971 HV_X64_MSR_RESET,
11c4b1ca 972 HV_X64_MSR_VP_INDEX,
9eec50b8 973 HV_X64_MSR_VP_RUNTIME,
5c919412 974 HV_X64_MSR_SCONTROL,
1f4b34f8 975 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 976 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
977 MSR_KVM_PV_EOI_EN,
978
ba904635 979 MSR_IA32_TSC_ADJUST,
a3e06bbe 980 MSR_IA32_TSCDEADLINE,
043405e1 981 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 982 MSR_IA32_MCG_STATUS,
983 MSR_IA32_MCG_CTL,
64d60670 984 MSR_IA32_SMBASE,
043405e1
CO		 985};
986
62ef68bb
PB		 987static unsigned num_emulated_msrs;
988
384bb783 989bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 990{
b69e8cae 991 if (efer & efer_reserved_bits)
384bb783 992 return false;
15c4a640 993
1b2fd70c
AG		 994 if (efer & EFER_FFXSR) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 999 return false;
1b2fd70c
AG		 1000 }
1001
d8017474
AG		 1002 if (efer & EFER_SVME) {
1003 struct kvm_cpuid_entry2 *feat;
1004
1005 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1006 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1007 return false;
d8017474
AG		 1008 }
1009
384bb783
JK		 1010 return true;
1011}
1012EXPORT_SYMBOL_GPL(kvm_valid_efer);
1013
1014static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1015{
1016 u64 old_efer = vcpu->arch.efer;
1017
1018 if (!kvm_valid_efer(vcpu, efer))
1019 return 1;
1020
1021 if (is_paging(vcpu)
1022 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1023 return 1;
1024
15c4a640 1025 efer &= ~EFER_LMA;
f6801dff 1026 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1027
a3d204e2
SY		 1028 kvm_x86_ops->set_efer(vcpu, efer);
1029
aad82703
SY		 1030 /* Update reserved bits */
1031 if ((efer ^ old_efer) & EFER_NX)
1032 kvm_mmu_reset_context(vcpu);
1033
b69e8cae 1034 return 0;
15c4a640
CO		 1035}
1036
f2b4b7dd
JR		 1037void kvm_enable_efer_bits(u64 mask)
1038{
1039 efer_reserved_bits &= ~mask;
1040}
1041EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1042
15c4a640
CO		 1043/*
1044 * Writes msr value into into the appropriate "register".
1045 * Returns 0 on success, non-0 otherwise.
1046 * Assumes vcpu_load() was already called.
1047 */
8fe8ab46 1048int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1049{
854e8bb1
NA		 1050 switch (msr->index) {
1051 case MSR_FS_BASE:
1052 case MSR_GS_BASE:
1053 case MSR_KERNEL_GS_BASE:
1054 case MSR_CSTAR:
1055 case MSR_LSTAR:
1056 if (is_noncanonical_address(msr->data))
1057 return 1;
1058 break;
1059 case MSR_IA32_SYSENTER_EIP:
1060 case MSR_IA32_SYSENTER_ESP:
1061 /*
1062 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1063 * non-canonical address is written on Intel but not on
1064 * AMD (which ignores the top 32-bits, because it does
1065 * not implement 64-bit SYSENTER).
1066 *
1067 * 64-bit code should hence be able to write a non-canonical
1068 * value on AMD. Making the address canonical ensures that
1069 * vmentry does not fail on Intel after writing a non-canonical
1070 * value, and that something deterministic happens if the guest
1071 * invokes 64-bit SYSENTER.
1072 */
1073 msr->data = get_canonical(msr->data);
1074 }
8fe8ab46 1075 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1076}
854e8bb1 1077EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1078
313a3dc7
CO		 1079/*
1080 * Adapt set_msr() to msr_io()'s calling convention
1081 */
609e36d3
PB		 1082static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1083{
1084 struct msr_data msr;
1085 int r;
1086
1087 msr.index = index;
1088 msr.host_initiated = true;
1089 r = kvm_get_msr(vcpu, &msr);
1090 if (r)
1091 return r;
1092
1093 *data = msr.data;
1094 return 0;
1095}
1096
313a3dc7
CO		 1097static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1098{
8fe8ab46
WA		 1099 struct msr_data msr;
1100
1101 msr.data = *data;
1102 msr.index = index;
1103 msr.host_initiated = true;
1104 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1105}
1106
16e8d74d
MT		 1107#ifdef CONFIG_X86_64
1108struct pvclock_gtod_data {
1109 seqcount_t seq;
1110
1111 struct { /* extract of a clocksource struct */
1112 int vclock_mode;
1113 cycle_t cycle_last;
1114 cycle_t mask;
1115 u32 mult;
1116 u32 shift;
1117 } clock;
1118
cbcf2dd3
TG		 1119 u64 boot_ns;
1120 u64 nsec_base;
16e8d74d
MT		 1121};
1122
1123static struct pvclock_gtod_data pvclock_gtod_data;
1124
1125static void update_pvclock_gtod(struct timekeeper *tk)
1126{
1127 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1128 u64 boot_ns;
1129
876e7881 1130 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1131
1132 write_seqcount_begin(&vdata->seq);
1133
1134 /* copy pvclock gtod data */
876e7881
PZ		 1135 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1136 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1137 vdata->clock.mask = tk->tkr_mono.mask;
1138 vdata->clock.mult = tk->tkr_mono.mult;
1139 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1140
cbcf2dd3 1141 vdata->boot_ns = boot_ns;
876e7881 1142 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1143
1144 write_seqcount_end(&vdata->seq);
1145}
1146#endif
1147
bab5bb39
NK		 1148void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1149{
1150 /*
1151 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1152 * vcpu_enter_guest. This function is only called from
1153 * the physical CPU that is running vcpu.
1154 */
1155 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1156}
16e8d74d 1157
18068523
GOC		 1158static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1159{
9ed3c444
AK		 1160 int version;
1161 int r;
50d0a0f9 1162 struct pvclock_wall_clock wc;
923de3cf 1163 struct timespec boot;
18068523
GOC		 1164
1165 if (!wall_clock)
1166 return;
1167
9ed3c444
AK		 1168 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1169 if (r)
1170 return;
1171
1172 if (version & 1)
1173 ++version; /* first time write, random junk */
1174
1175 ++version;
18068523 1176
1dab1345
NK		 1177 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1178 return;
18068523 1179
50d0a0f9
GH		 1180 /*
1181 * The guest calculates current wall clock time by adding
34c238a1 1182 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1183 * wall clock specified here. guest system time equals host
1184 * system time for us, thus we must fill in host boot time here.
1185 */
923de3cf 1186 getboottime(&boot);
50d0a0f9 1187
4b648665
BR		 1188 if (kvm->arch.kvmclock_offset) {
1189 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1190 boot = timespec_sub(boot, ts);
1191 }
50d0a0f9
GH		 1192 wc.sec = boot.tv_sec;
1193 wc.nsec = boot.tv_nsec;
1194 wc.version = version;
18068523
GOC		 1195
1196 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1197
1198 version++;
1199 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1200}
1201
50d0a0f9
GH		 1202static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1203{
b51012de
PB		 1204 do_shl32_div32(dividend, divisor);
1205 return dividend;
50d0a0f9
GH		 1206}
1207
3ae13faa 1208static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1209 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1210{
5f4e3f88 1211 uint64_t scaled64;
50d0a0f9
GH		 1212 int32_t shift = 0;
1213 uint64_t tps64;
1214 uint32_t tps32;
1215
3ae13faa
PB		 1216 tps64 = base_hz;
1217 scaled64 = scaled_hz;
50933623 1218 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1219 tps64 >>= 1;
1220 shift--;
1221 }
1222
1223 tps32 = (uint32_t)tps64;
50933623
JK		 1224 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1225 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1226 scaled64 >>= 1;
1227 else
1228 tps32 <<= 1;
50d0a0f9
GH		 1229 shift++;
1230 }
1231
5f4e3f88
ZA		 1232 *pshift = shift;
1233 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1234
3ae13faa
PB		 1235 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1236 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1237}
1238
d828199e 1239#ifdef CONFIG_X86_64
16e8d74d 1240static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1241#endif
16e8d74d 1242
c8076604 1243static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1244static unsigned long max_tsc_khz;
c8076604 1245
cc578287 1246static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1247{
cc578287
ZA		 1248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1249 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1250}
1251
cc578287 1252static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1253{
cc578287
ZA		 1254 u64 v = (u64)khz * (1000000 + ppm);
1255 do_div(v, 1000000);
1256 return v;
1e993611
JR		 1257}
1258
381d585c
HZ		 1259static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1260{
1261 u64 ratio;
1262
1263 /* Guest TSC same frequency as host TSC? */
1264 if (!scale) {
1265 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1266 return 0;
1267 }
1268
1269 /* TSC scaling supported? */
1270 if (!kvm_has_tsc_control) {
1271 if (user_tsc_khz > tsc_khz) {
1272 vcpu->arch.tsc_catchup = 1;
1273 vcpu->arch.tsc_always_catchup = 1;
1274 return 0;
1275 } else {
1276 WARN(1, "user requested TSC rate below hardware speed\n");
1277 return -1;
1278 }
1279 }
1280
1281 /* TSC scaling required - calculate ratio */
1282 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1283 user_tsc_khz, tsc_khz);
1284
1285 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1286 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1287 user_tsc_khz);
1288 return -1;
1289 }
1290
1291 vcpu->arch.tsc_scaling_ratio = ratio;
1292 return 0;
1293}
1294
4941b8cb 1295static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1296{
cc578287
ZA		 1297 u32 thresh_lo, thresh_hi;
1298 int use_scaling = 0;
217fc9cf 1299
03ba32ca 1300 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1301 if (user_tsc_khz == 0) {
ad721883
HZ		 1302 /* set tsc_scaling_ratio to a safe value */
1303 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1304 return -1;
ad721883 1305 }
03ba32ca 1306
c285545f 1307 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1308 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1309 &vcpu->arch.virtual_tsc_shift,
1310 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1311 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1312
1313 /*
1314 * Compute the variation in TSC rate which is acceptable
1315 * within the range of tolerance and decide if the
1316 * rate being applied is within that bounds of the hardware
1317 * rate. If so, no scaling or compensation need be done.
1318 */
1319 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1320 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1321 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1322 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1323 use_scaling = 1;
1324 }
4941b8cb 1325 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1326}
1327
1328static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1329{
e26101b1 1330 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1331 vcpu->arch.virtual_tsc_mult,
1332 vcpu->arch.virtual_tsc_shift);
e26101b1 1333 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1334 return tsc;
1335}
1336
69b0049a 1337static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1338{
1339#ifdef CONFIG_X86_64
1340 bool vcpus_matched;
b48aa97e
MT		 1341 struct kvm_arch *ka = &vcpu->kvm->arch;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1343
1344 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1345 atomic_read(&vcpu->kvm->online_vcpus));
1346
7f187922
MT		 1347 /*
1348 * Once the masterclock is enabled, always perform request in
1349 * order to update it.
1350 *
1351 * In order to enable masterclock, the host clocksource must be TSC
1352 * and the vcpus need to have matched TSCs. When that happens,
1353 * perform request to enable masterclock.
1354 */
1355 if (ka->use_master_clock ||
1356 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1358
1359 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1360 atomic_read(&vcpu->kvm->online_vcpus),
1361 ka->use_master_clock, gtod->clock.vclock_mode);
1362#endif
1363}
1364
ba904635
WA		 1365static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1366{
1367 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1368 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1369}
1370
35181e86
HZ		 1371/*
1372 * Multiply tsc by a fixed point number represented by ratio.
1373 *
1374 * The most significant 64-N bits (mult) of ratio represent the
1375 * integral part of the fixed point number; the remaining N bits
1376 * (frac) represent the fractional part, ie. ratio represents a fixed
1377 * point number (mult + frac * 2^(-N)).
1378 *
1379 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1380 */
1381static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1382{
1383 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1384}
1385
1386u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1387{
1388 u64 _tsc = tsc;
1389 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1390
1391 if (ratio != kvm_default_tsc_scaling_ratio)
1392 _tsc = __scale_tsc(ratio, tsc);
1393
1394 return _tsc;
1395}
1396EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1397
07c1419a
HZ		 1398static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1399{
1400 u64 tsc;
1401
1402 tsc = kvm_scale_tsc(vcpu, rdtsc());
1403
1404 return target_tsc - tsc;
1405}
1406
4ba76538
HZ		 1407u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1408{
1409 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1410}
1411EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1412
8fe8ab46 1413void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1414{
1415 struct kvm *kvm = vcpu->kvm;
f38e098f 1416 u64 offset, ns, elapsed;
99e3e30a 1417 unsigned long flags;
02626b6a 1418 s64 usdiff;
b48aa97e 1419 bool matched;
0d3da0d2 1420 bool already_matched;
8fe8ab46 1421 u64 data = msr->data;
99e3e30a 1422
038f8c11 1423 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1424 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1425 ns = get_kernel_ns();
f38e098f 1426 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1427
03ba32ca 1428 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1429 int faulted = 0;
1430
03ba32ca
MT		 1431 /* n.b - signed multiplication and division required */
1432 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1433#ifdef CONFIG_X86_64
03ba32ca 1434 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1435#else
03ba32ca 1436 /* do_div() only does unsigned */
8915aa27
MT		 1437 asm("1: idivl %[divisor]\n"
1438 "2: xor %%edx, %%edx\n"
1439 " movl $0, %[faulted]\n"
1440 "3:\n"
1441 ".section .fixup,\"ax\"\n"
1442 "4: movl $1, %[faulted]\n"
1443 " jmp 3b\n"
1444 ".previous\n"
1445
1446 _ASM_EXTABLE(1b, 4b)
1447
1448 : "=A"(usdiff), [faulted] "=r" (faulted)
1449 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1450
5d3cb0f6 1451#endif
03ba32ca
MT		 1452 do_div(elapsed, 1000);
1453 usdiff -= elapsed;
1454 if (usdiff < 0)
1455 usdiff = -usdiff;
8915aa27
MT		 1456
1457 /* idivl overflow => difference is larger than USEC_PER_SEC */
1458 if (faulted)
1459 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1460 } else
1461 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1462
1463 /*
5d3cb0f6
ZA		 1464 * Special case: TSC write with a small delta (1 second) of virtual
1465 * cycle time against real time is interpreted as an attempt to
1466 * synchronize the CPU.
1467 *
1468 * For a reliable TSC, we can match TSC offsets, and for an unstable
1469 * TSC, we add elapsed time in this computation. We could let the
1470 * compensation code attempt to catch up if we fall behind, but
1471 * it's better to try to match offsets from the beginning.
1472 */
02626b6a 1473 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1474 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1475 if (!check_tsc_unstable()) {
e26101b1 1476 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1477 pr_debug("kvm: matched tsc offset for %llu\n", data);
1478 } else {
857e4099 1479 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1480 data += delta;
07c1419a 1481 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1482 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1483 }
b48aa97e 1484 matched = true;
0d3da0d2 1485 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1486 } else {
1487 /*
1488 * We split periods of matched TSC writes into generations.
1489 * For each generation, we track the original measured
1490 * nanosecond time, offset, and write, so if TSCs are in
1491 * sync, we can match exact offset, and if not, we can match
4a969980 1492 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1493 *
1494 * These values are tracked in kvm->arch.cur_xxx variables.
1495 */
1496 kvm->arch.cur_tsc_generation++;
1497 kvm->arch.cur_tsc_nsec = ns;
1498 kvm->arch.cur_tsc_write = data;
1499 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1500 matched = false;
0d3da0d2 1501 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1502 kvm->arch.cur_tsc_generation, data);
f38e098f 1503 }
e26101b1
ZA		 1504
1505 /*
1506 * We also track th most recent recorded KHZ, write and time to
1507 * allow the matching interval to be extended at each write.
1508 */
f38e098f
ZA		 1509 kvm->arch.last_tsc_nsec = ns;
1510 kvm->arch.last_tsc_write = data;
5d3cb0f6 1511 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1512
b183aa58 1513 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1514
1515 /* Keep track of which generation this VCPU has synchronized to */
1516 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1517 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1518 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1519
ba904635
WA		 1520 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1521 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1522 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1523 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1524
1525 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1526 if (!matched) {
b48aa97e 1527 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1528 } else if (!already_matched) {
1529 kvm->arch.nr_vcpus_matched_tsc++;
1530 }
b48aa97e
MT		 1531
1532 kvm_track_tsc_matching(vcpu);
1533 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1534}
e26101b1 1535
99e3e30a
ZA		 1536EXPORT_SYMBOL_GPL(kvm_write_tsc);
1537
58ea6767
HZ		 1538static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1539 s64 adjustment)
1540{
1541 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1542}
1543
1544static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1545{
1546 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1547 WARN_ON(adjustment < 0);
1548 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1549 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1550}
1551
d828199e
MT		 1552#ifdef CONFIG_X86_64
1553
1554static cycle_t read_tsc(void)
1555{
03b9730b
AL		 1556 cycle_t ret = (cycle_t)rdtsc_ordered();
1557 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1558
1559 if (likely(ret >= last))
1560 return ret;
1561
1562 /*
1563 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1564 * predictable (it's just a function of time and the likely is
d828199e
MT		 1565 * very likely) and there's a data dependence, so force GCC
1566 * to generate a branch instead. I don't barrier() because
1567 * we don't actually need a barrier, and if this function
1568 * ever gets inlined it will generate worse code.
1569 */
1570 asm volatile ("");
1571 return last;
1572}
1573
1574static inline u64 vgettsc(cycle_t *cycle_now)
1575{
1576 long v;
1577 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1578
1579 *cycle_now = read_tsc();
1580
1581 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1582 return v * gtod->clock.mult;
1583}
1584
cbcf2dd3 1585static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1586{
cbcf2dd3 1587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1588 unsigned long seq;
d828199e 1589 int mode;
cbcf2dd3 1590 u64 ns;
d828199e 1591
d828199e
MT		 1592 do {
1593 seq = read_seqcount_begin(&gtod->seq);
1594 mode = gtod->clock.vclock_mode;
cbcf2dd3 1595 ns = gtod->nsec_base;
d828199e
MT		 1596 ns += vgettsc(cycle_now);
1597 ns >>= gtod->clock.shift;
cbcf2dd3 1598 ns += gtod->boot_ns;
d828199e 1599 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1600 *t = ns;
d828199e
MT		 1601
1602 return mode;
1603}
1604
1605/* returns true if host is using tsc clocksource */
1606static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1607{
d828199e
MT		 1608 /* checked again under seqlock below */
1609 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1610 return false;
1611
cbcf2dd3 1612 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1613}
1614#endif
1615
1616/*
1617 *
b48aa97e
MT		 1618 * Assuming a stable TSC across physical CPUS, and a stable TSC
1619 * across virtual CPUs, the following condition is possible.
1620 * Each numbered line represents an event visible to both
d828199e
MT		 1621 * CPUs at the next numbered event.
1622 *
1623 * "timespecX" represents host monotonic time. "tscX" represents
1624 * RDTSC value.
1625 *
1626 * VCPU0 on CPU0 | VCPU1 on CPU1
1627 *
1628 * 1. read timespec0,tsc0
1629 * 2. | timespec1 = timespec0 + N
1630 * | tsc1 = tsc0 + M
1631 * 3. transition to guest | transition to guest
1632 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1633 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1634 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1635 *
1636 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1637 *
1638 * - ret0 < ret1
1639 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1640 * ...
1641 * - 0 < N - M => M < N
1642 *
1643 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1644 * always the case (the difference between two distinct xtime instances
1645 * might be smaller then the difference between corresponding TSC reads,
1646 * when updating guest vcpus pvclock areas).
1647 *
1648 * To avoid that problem, do not allow visibility of distinct
1649 * system_timestamp/tsc_timestamp values simultaneously: use a master
1650 * copy of host monotonic time values. Update that master copy
1651 * in lockstep.
1652 *
b48aa97e 1653 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1654 *
1655 */
1656
1657static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1658{
1659#ifdef CONFIG_X86_64
1660 struct kvm_arch *ka = &kvm->arch;
1661 int vclock_mode;
b48aa97e
MT		 1662 bool host_tsc_clocksource, vcpus_matched;
1663
1664 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1665 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1666
1667 /*
1668 * If the host uses TSC clock, then passthrough TSC as stable
1669 * to the guest.
1670 */
b48aa97e 1671 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1672 &ka->master_kernel_ns,
1673 &ka->master_cycle_now);
1674
16a96021 1675 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1676 && !backwards_tsc_observed
1677 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1678
d828199e
MT		 1679 if (ka->use_master_clock)
1680 atomic_set(&kvm_guest_has_master_clock, 1);
1681
1682 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1683 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1684 vcpus_matched);
d828199e
MT		 1685#endif
1686}
1687
2860c4b1
PB		 1688void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1689{
1690 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1691}
1692
2e762ff7
MT		 1693static void kvm_gen_update_masterclock(struct kvm *kvm)
1694{
1695#ifdef CONFIG_X86_64
1696 int i;
1697 struct kvm_vcpu *vcpu;
1698 struct kvm_arch *ka = &kvm->arch;
1699
1700 spin_lock(&ka->pvclock_gtod_sync_lock);
1701 kvm_make_mclock_inprogress_request(kvm);
1702 /* no guest entries from this point */
1703 pvclock_update_vm_gtod_copy(kvm);
1704
1705 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1706 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1707
1708 /* guest entries allowed */
1709 kvm_for_each_vcpu(i, vcpu, kvm)
1710 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1711
1712 spin_unlock(&ka->pvclock_gtod_sync_lock);
1713#endif
1714}
1715
34c238a1 1716static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1717{
78db6a50 1718 unsigned long flags, tgt_tsc_khz;
18068523 1719 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1720 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1721 s64 kernel_ns;
d828199e 1722 u64 tsc_timestamp, host_tsc;
0b79459b 1723 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1724 u8 pvclock_flags;
d828199e
MT		 1725 bool use_master_clock;
1726
1727 kernel_ns = 0;
1728 host_tsc = 0;
18068523 1729
d828199e
MT		 1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
1734 spin_lock(&ka->pvclock_gtod_sync_lock);
1735 use_master_clock = ka->use_master_clock;
1736 if (use_master_clock) {
1737 host_tsc = ka->master_cycle_now;
1738 kernel_ns = ka->master_kernel_ns;
1739 }
1740 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1741
1742 /* Keep irq disabled to prevent changes to the clock */
1743 local_irq_save(flags);
78db6a50
PB		 1744 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1745 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1746 local_irq_restore(flags);
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1748 return 1;
1749 }
d828199e 1750 if (!use_master_clock) {
4ea1636b 1751 host_tsc = rdtsc();
d828199e
MT		 1752 kernel_ns = get_kernel_ns();
1753 }
1754
4ba76538 1755 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1756
c285545f
ZA		 1757 /*
1758 * We may have to catch up the TSC to match elapsed wall clock
1759 * time for two reasons, even if kvmclock is used.
1760 * 1) CPU could have been running below the maximum TSC rate
1761 * 2) Broken TSC compensation resets the base at each VCPU
1762 * entry to avoid unknown leaps of TSC even when running
1763 * again on the same CPU. This may cause apparent elapsed
1764 * time to disappear, and the guest to stand still or run
1765 * very slowly.
1766 */
1767 if (vcpu->tsc_catchup) {
1768 u64 tsc = compute_guest_tsc(v, kernel_ns);
1769 if (tsc > tsc_timestamp) {
f1e2b260 1770 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1771 tsc_timestamp = tsc;
1772 }
50d0a0f9
GH		 1773 }
1774
18068523
GOC		 1775 local_irq_restore(flags);
1776
0b79459b 1777 if (!vcpu->pv_time_enabled)
c285545f 1778 return 0;
18068523 1779
78db6a50
PB		 1780 if (kvm_has_tsc_control)
1781 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1782
1783 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1784 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1787 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1788 }
1789
1790 /* With all the info we got, fill in the values */
1d5f066e 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1793 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1794
09a0c3f1
OH		 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
5dca0d91
RK		 1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
18068523 1812 */
5dca0d91
RK		 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
78c0337a
MT		 1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
d828199e
MT		 1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
78c0337a
MT		 1834 vcpu->hv_clock.flags = pvclock_flags;
1835
ce1a5e60
DM		 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
0b79459b
AH		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
8cfdc000 1848 return 0;
c8076604
GH		 1849}
1850
0061d53d
MT		 1851/*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1863 */
1864
7e44e449
AJ		 1865#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1868{
1869 int i;
7e44e449
AJ		 1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1878 kvm_vcpu_kick(vcpu);
1879 }
1880}
1881
7e44e449
AJ		 1882static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883{
1884 struct kvm *kvm = v->kvm;
1885
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889}
1890
332967a3
AJ		 1891#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893static void kvmclock_sync_fn(struct work_struct *work)
1894{
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
630994b3
MT		 1900 if (!kvmclock_periodic_sync)
1901 return;
1902
332967a3
AJ		 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906}
1907
890ca9ae 1908static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1909{
890ca9ae
HY		 1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
15c4a640 1913 switch (msr) {
15c4a640 1914 case MSR_IA32_MCG_STATUS:
890ca9ae 1915 vcpu->arch.mcg_status = data;
15c4a640 1916 break;
c7ac679c 1917 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1927 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
890ca9ae 1933 if ((offset & 0x3) == 0 &&
114be429 1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942}
1943
ffde22ac
ES		 1944static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
ff5c2c03
SL		 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
ffde22ac 1964 goto out;
ff5c2c03 1965 }
54bf36aa 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1967 goto out_free;
1968 r = 0;
1969out_free:
1970 kfree(page);
1971out:
1972 return r;
1973}
1974
344d9588
GN		 1975static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976{
1977 gpa_t gpa = data & ~0x3f;
1978
4a969980 1979 /* Bits 2:5 are reserved, Should be zero */
6adba527 1980 if (data & 0x3c)
344d9588
GN		 1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
8f964525
AH		 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
344d9588
GN		 1993 return 1;
1994
6adba527 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998}
1999
12f9a48f
GC		 2000static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001{
0b79459b 2002 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2003}
2004
c9aaa895
GC		 2005static void record_steal_time(struct kvm_vcpu *vcpu)
2006{
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2008 return;
2009
2010 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2012 return;
2013
35f3fae1
WL		 2014 if (vcpu->arch.st.steal.version & 1)
2015 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2016
2017 vcpu->arch.st.steal.version += 1;
2018
2019 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2020 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2021
2022 smp_wmb();
2023
c54cdf14
LC		 2024 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2025 vcpu->arch.st.last_steal;
2026 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2027
2028 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2029 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2030
2031 smp_wmb();
2032
2033 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2034
2035 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2036 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2037}
2038
8fe8ab46 2039int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2040{
5753785f 2041 bool pr = false;
8fe8ab46
WA		 2042 u32 msr = msr_info->index;
2043 u64 data = msr_info->data;
5753785f 2044
15c4a640 2045 switch (msr) {
2e32b719
BP		 2046 case MSR_AMD64_NB_CFG:
2047 case MSR_IA32_UCODE_REV:
2048 case MSR_IA32_UCODE_WRITE:
2049 case MSR_VM_HSAVE_PA:
2050 case MSR_AMD64_PATCH_LOADER:
2051 case MSR_AMD64_BU_CFG2:
2052 break;
2053
15c4a640 2054 case MSR_EFER:
b69e8cae 2055 return set_efer(vcpu, data);
8f1589d9
AP		 2056 case MSR_K7_HWCR:
2057 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2058 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2059 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2060 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2061 if (data != 0) {
a737f256
CD		 2062 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2063 data);
8f1589d9
AP		 2064 return 1;
2065 }
15c4a640 2066 break;
f7c6d140
AP		 2067 case MSR_FAM10H_MMIO_CONF_BASE:
2068 if (data != 0) {
a737f256
CD		 2069 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2070 "0x%llx\n", data);
f7c6d140
AP		 2071 return 1;
2072 }
15c4a640 2073 break;
b5e2fec0
AG		 2074 case MSR_IA32_DEBUGCTLMSR:
2075 if (!data) {
2076 /* We support the non-activated case already */
2077 break;
2078 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2079 /* Values other than LBR and BTF are vendor-specific,
2080 thus reserved and should throw a #GP */
2081 return 1;
2082 }
a737f256
CD		 2083 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2084 __func__, data);
b5e2fec0 2085 break;
9ba075a6 2086 case 0x200 ... 0x2ff:
ff53604b 2087 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2088 case MSR_IA32_APICBASE:
58cb628d 2089 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2090 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2091 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2092 case MSR_IA32_TSCDEADLINE:
2093 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2094 break;
ba904635
WA		 2095 case MSR_IA32_TSC_ADJUST:
2096 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2097 if (!msr_info->host_initiated) {
d913b904 2098 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2099 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2100 }
2101 vcpu->arch.ia32_tsc_adjust_msr = data;
2102 }
2103 break;
15c4a640 2104 case MSR_IA32_MISC_ENABLE:
ad312c7c 2105 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2106 break;
64d60670
PB		 2107 case MSR_IA32_SMBASE:
2108 if (!msr_info->host_initiated)
2109 return 1;
2110 vcpu->arch.smbase = data;
2111 break;
11c6bffa 2112 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2113 case MSR_KVM_WALL_CLOCK:
2114 vcpu->kvm->arch.wall_clock = data;
2115 kvm_write_wall_clock(vcpu->kvm, data);
2116 break;
11c6bffa 2117 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2118 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2119 u64 gpa_offset;
54750f2c
MT		 2120 struct kvm_arch *ka = &vcpu->kvm->arch;
2121
12f9a48f 2122 kvmclock_reset(vcpu);
18068523 2123
54750f2c
MT		 2124 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2125 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2126
2127 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2128 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2129 &vcpu->requests);
2130
2131 ka->boot_vcpu_runs_old_kvmclock = tmp;
2132 }
2133
18068523 2134 vcpu->arch.time = data;
0061d53d 2135 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2136
2137 /* we verify if the enable bit is set... */
2138 if (!(data & 1))
2139 break;
2140
0b79459b 2141 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2142
0b79459b 2143 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2144 &vcpu->arch.pv_time, data & ~1ULL,
2145 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2146 vcpu->arch.pv_time_enabled = false;
2147 else
2148 vcpu->arch.pv_time_enabled = true;
32cad84f 2149
18068523
GOC		 2150 break;
2151 }
344d9588
GN		 2152 case MSR_KVM_ASYNC_PF_EN:
2153 if (kvm_pv_enable_async_pf(vcpu, data))
2154 return 1;
2155 break;
c9aaa895
GC		 2156 case MSR_KVM_STEAL_TIME:
2157
2158 if (unlikely(!sched_info_on()))
2159 return 1;
2160
2161 if (data & KVM_STEAL_RESERVED_MASK)
2162 return 1;
2163
2164 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2165 data & KVM_STEAL_VALID_BITS,
2166 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2167 return 1;
2168
2169 vcpu->arch.st.msr_val = data;
2170
2171 if (!(data & KVM_MSR_ENABLED))
2172 break;
2173
c9aaa895
GC		 2174 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2175
2176 break;
ae7a2a3f
MT		 2177 case MSR_KVM_PV_EOI_EN:
2178 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2179 return 1;
2180 break;
c9aaa895 2181
890ca9ae
HY		 2182 case MSR_IA32_MCG_CTL:
2183 case MSR_IA32_MCG_STATUS:
81760dcc 2184 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2185 return set_msr_mce(vcpu, msr, data);
71db6023 2186
6912ac32
WH		 2187 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2188 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2189 pr = true; /* fall through */
2190 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2191 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2192 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2193 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2194
2195 if (pr || data != 0)
a737f256
CD		 2196 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2197 "0x%x data 0x%llx\n", msr, data);
5753785f 2198 break;
84e0cefa
JS		 2199 case MSR_K7_CLK_CTL:
2200 /*
2201 * Ignore all writes to this no longer documented MSR.
2202 * Writes are only relevant for old K7 processors,
2203 * all pre-dating SVM, but a recommended workaround from
4a969980 2204 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2205 * affected processor models on the command line, hence
2206 * the need to ignore the workaround.
2207 */
2208 break;
55cd8e5a 2209 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2210 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2211 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2212 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2213 return kvm_hv_set_msr_common(vcpu, msr, data,
2214 msr_info->host_initiated);
91c9c3ed 2215 case MSR_IA32_BBL_CR_CTL3:
2216 /* Drop writes to this legacy MSR -- see rdmsr
2217 * counterpart for further detail.
2218 */
a737f256 2219 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2220 break;
2b036c6b
BO		 2221 case MSR_AMD64_OSVW_ID_LENGTH:
2222 if (!guest_cpuid_has_osvw(vcpu))
2223 return 1;
2224 vcpu->arch.osvw.length = data;
2225 break;
2226 case MSR_AMD64_OSVW_STATUS:
2227 if (!guest_cpuid_has_osvw(vcpu))
2228 return 1;
2229 vcpu->arch.osvw.status = data;
2230 break;
15c4a640 2231 default:
ffde22ac
ES		 2232 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2233 return xen_hvm_config(vcpu, data);
c6702c9d 2234 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2235 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2236 if (!ignore_msrs) {
a737f256
CD		 2237 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2238 msr, data);
ed85c068
AP		 2239 return 1;
2240 } else {
a737f256
CD		 2241 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2242 msr, data);
ed85c068
AP		 2243 break;
2244 }
15c4a640
CO		 2245 }
2246 return 0;
2247}
2248EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2249
2250
2251/*
2252 * Reads an msr value (of 'msr_index') into 'pdata'.
2253 * Returns 0 on success, non-0 otherwise.
2254 * Assumes vcpu_load() was already called.
2255 */
609e36d3 2256int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2257{
609e36d3 2258 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2259}
ff651cb6 2260EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2261
890ca9ae 2262static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2263{
2264 u64 data;
890ca9ae
HY		 2265 u64 mcg_cap = vcpu->arch.mcg_cap;
2266 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2267
2268 switch (msr) {
15c4a640
CO		 2269 case MSR_IA32_P5_MC_ADDR:
2270 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2271 data = 0;
2272 break;
15c4a640 2273 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2274 data = vcpu->arch.mcg_cap;
2275 break;
c7ac679c 2276 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2277 if (!(mcg_cap & MCG_CTL_P))
2278 return 1;
2279 data = vcpu->arch.mcg_ctl;
2280 break;
2281 case MSR_IA32_MCG_STATUS:
2282 data = vcpu->arch.mcg_status;
2283 break;
2284 default:
2285 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2286 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2287 u32 offset = msr - MSR_IA32_MC0_CTL;
2288 data = vcpu->arch.mce_banks[offset];
2289 break;
2290 }
2291 return 1;
2292 }
2293 *pdata = data;
2294 return 0;
2295}
2296
609e36d3 2297int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2298{
609e36d3 2299 switch (msr_info->index) {
890ca9ae 2300 case MSR_IA32_PLATFORM_ID:
15c4a640 2301 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2302 case MSR_IA32_DEBUGCTLMSR:
2303 case MSR_IA32_LASTBRANCHFROMIP:
2304 case MSR_IA32_LASTBRANCHTOIP:
2305 case MSR_IA32_LASTINTFROMIP:
2306 case MSR_IA32_LASTINTTOIP:
60af2ecd 2307 case MSR_K8_SYSCFG:
3afb1121
PB		 2308 case MSR_K8_TSEG_ADDR:
2309 case MSR_K8_TSEG_MASK:
60af2ecd 2310 case MSR_K7_HWCR:
61a6bd67 2311 case MSR_VM_HSAVE_PA:
1fdbd48c 2312 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2313 case MSR_AMD64_NB_CFG:
f7c6d140 2314 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2315 case MSR_AMD64_BU_CFG2:
609e36d3 2316 msr_info->data = 0;
15c4a640 2317 break;
6912ac32
WH		 2318 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2319 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2320 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2321 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2322 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2323 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2324 msr_info->data = 0;
5753785f 2325 break;
742bc670 2326 case MSR_IA32_UCODE_REV:
609e36d3 2327 msr_info->data = 0x100000000ULL;
742bc670 2328 break;
9ba075a6 2329 case MSR_MTRRcap:
9ba075a6 2330 case 0x200 ... 0x2ff:
ff53604b 2331 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2332 case 0xcd: /* fsb frequency */
609e36d3 2333 msr_info->data = 3;
15c4a640 2334 break;
7b914098
JS		 2335 /*
2336 * MSR_EBC_FREQUENCY_ID
2337 * Conservative value valid for even the basic CPU models.
2338 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2339 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2340 * and 266MHz for model 3, or 4. Set Core Clock
2341 * Frequency to System Bus Frequency Ratio to 1 (bits
2342 * 31:24) even though these are only valid for CPU
2343 * models > 2, however guests may end up dividing or
2344 * multiplying by zero otherwise.
2345 */
2346 case MSR_EBC_FREQUENCY_ID:
609e36d3 2347 msr_info->data = 1 << 24;
7b914098 2348 break;
15c4a640 2349 case MSR_IA32_APICBASE:
609e36d3 2350 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2351 break;
0105d1a5 2352 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2353 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2354 break;
a3e06bbe 2355 case MSR_IA32_TSCDEADLINE:
609e36d3 2356 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2357 break;
ba904635 2358 case MSR_IA32_TSC_ADJUST:
609e36d3 2359 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2360 break;
15c4a640 2361 case MSR_IA32_MISC_ENABLE:
609e36d3 2362 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2363 break;
64d60670
PB		 2364 case MSR_IA32_SMBASE:
2365 if (!msr_info->host_initiated)
2366 return 1;
2367 msr_info->data = vcpu->arch.smbase;
15c4a640 2368 break;
847f0ad8
AG		 2369 case MSR_IA32_PERF_STATUS:
2370 /* TSC increment by tick */
609e36d3 2371 msr_info->data = 1000ULL;
847f0ad8 2372 /* CPU multiplier */
b0996ae4 2373 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2374 break;
15c4a640 2375 case MSR_EFER:
609e36d3 2376 msr_info->data = vcpu->arch.efer;
15c4a640 2377 break;
18068523 2378 case MSR_KVM_WALL_CLOCK:
11c6bffa 2379 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2380 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2381 break;
2382 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2383 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2384 msr_info->data = vcpu->arch.time;
18068523 2385 break;
344d9588 2386 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2387 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2388 break;
c9aaa895 2389 case MSR_KVM_STEAL_TIME:
609e36d3 2390 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2391 break;
1d92128f 2392 case MSR_KVM_PV_EOI_EN:
609e36d3 2393 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2394 break;
890ca9ae
HY		 2395 case MSR_IA32_P5_MC_ADDR:
2396 case MSR_IA32_P5_MC_TYPE:
2397 case MSR_IA32_MCG_CAP:
2398 case MSR_IA32_MCG_CTL:
2399 case MSR_IA32_MCG_STATUS:
81760dcc 2400 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2401 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2402 case MSR_K7_CLK_CTL:
2403 /*
2404 * Provide expected ramp-up count for K7. All other
2405 * are set to zero, indicating minimum divisors for
2406 * every field.
2407 *
2408 * This prevents guest kernels on AMD host with CPU
2409 * type 6, model 8 and higher from exploding due to
2410 * the rdmsr failing.
2411 */
609e36d3 2412 msr_info->data = 0x20000000;
84e0cefa 2413 break;
55cd8e5a 2414 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2415 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2416 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2417 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2418 return kvm_hv_get_msr_common(vcpu,
2419 msr_info->index, &msr_info->data);
55cd8e5a 2420 break;
91c9c3ed 2421 case MSR_IA32_BBL_CR_CTL3:
2422 /* This legacy MSR exists but isn't fully documented in current
2423 * silicon. It is however accessed by winxp in very narrow
2424 * scenarios where it sets bit #19, itself documented as
2425 * a "reserved" bit. Best effort attempt to source coherent
2426 * read data here should the balance of the register be
2427 * interpreted by the guest:
2428 *
2429 * L2 cache control register 3: 64GB range, 256KB size,
2430 * enabled, latency 0x1, configured
2431 */
609e36d3 2432 msr_info->data = 0xbe702111;
91c9c3ed 2433 break;
2b036c6b
BO		 2434 case MSR_AMD64_OSVW_ID_LENGTH:
2435 if (!guest_cpuid_has_osvw(vcpu))
2436 return 1;
609e36d3 2437 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2438 break;
2439 case MSR_AMD64_OSVW_STATUS:
2440 if (!guest_cpuid_has_osvw(vcpu))
2441 return 1;
609e36d3 2442 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2443 break;
15c4a640 2444 default:
c6702c9d 2445 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2446 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2447 if (!ignore_msrs) {
609e36d3 2448 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2449 return 1;
2450 } else {
609e36d3
PB		 2451 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2452 msr_info->data = 0;
ed85c068
AP		 2453 }
2454 break;
15c4a640 2455 }
15c4a640
CO		 2456 return 0;
2457}
2458EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2459
313a3dc7
CO		 2460/*
2461 * Read or write a bunch of msrs. All parameters are kernel addresses.
2462 *
2463 * @return number of msrs set successfully.
2464 */
2465static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2466 struct kvm_msr_entry *entries,
2467 int (*do_msr)(struct kvm_vcpu *vcpu,
2468 unsigned index, u64 *data))
2469{
f656ce01 2470 int i, idx;
313a3dc7 2471
f656ce01 2472 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2473 for (i = 0; i < msrs->nmsrs; ++i)
2474 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2475 break;
f656ce01 2476 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2477
313a3dc7
CO		 2478 return i;
2479}
2480
2481/*
2482 * Read or write a bunch of msrs. Parameters are user addresses.
2483 *
2484 * @return number of msrs set successfully.
2485 */
2486static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2487 int (*do_msr)(struct kvm_vcpu *vcpu,
2488 unsigned index, u64 *data),
2489 int writeback)
2490{
2491 struct kvm_msrs msrs;
2492 struct kvm_msr_entry *entries;
2493 int r, n;
2494 unsigned size;
2495
2496 r = -EFAULT;
2497 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2498 goto out;
2499
2500 r = -E2BIG;
2501 if (msrs.nmsrs >= MAX_IO_MSRS)
2502 goto out;
2503
313a3dc7 2504 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2505 entries = memdup_user(user_msrs->entries, size);
2506 if (IS_ERR(entries)) {
2507 r = PTR_ERR(entries);
313a3dc7 2508 goto out;
ff5c2c03 2509 }
313a3dc7
CO		 2510
2511 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2512 if (r < 0)
2513 goto out_free;
2514
2515 r = -EFAULT;
2516 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2517 goto out_free;
2518
2519 r = n;
2520
2521out_free:
7a73c028 2522 kfree(entries);
313a3dc7
CO		 2523out:
2524 return r;
2525}
2526
784aa3d7 2527int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2528{
2529 int r;
2530
2531 switch (ext) {
2532 case KVM_CAP_IRQCHIP:
2533 case KVM_CAP_HLT:
2534 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2535 case KVM_CAP_SET_TSS_ADDR:
07716717 2536 case KVM_CAP_EXT_CPUID:
9c15bb1d 2537 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2538 case KVM_CAP_CLOCKSOURCE:
7837699f 2539 case KVM_CAP_PIT:
a28e4f5a 2540 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2541 case KVM_CAP_MP_STATE:
ed848624 2542 case KVM_CAP_SYNC_MMU:
a355c85c 2543 case KVM_CAP_USER_NMI:
52d939a0 2544 case KVM_CAP_REINJECT_CONTROL:
4925663a 2545 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2546 case KVM_CAP_IOEVENTFD:
f848a5a8 2547 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2548 case KVM_CAP_PIT2:
e9f42757 2549 case KVM_CAP_PIT_STATE2:
b927a3ce 2550 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2551 case KVM_CAP_XEN_HVM:
afbcf7ab 2552 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2553 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2554 case KVM_CAP_HYPERV:
10388a07 2555 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2556 case KVM_CAP_HYPERV_SPIN:
5c919412 2557 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2558 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2559 case KVM_CAP_DEBUGREGS:
d2be1651 2560 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2561 case KVM_CAP_XSAVE:
344d9588 2562 case KVM_CAP_ASYNC_PF:
92a1f12d 2563 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2564 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2565 case KVM_CAP_READONLY_MEM:
5f66b620 2566 case KVM_CAP_HYPERV_TIME:
100943c5 2567 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2568 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2569 case KVM_CAP_ENABLE_CAP_VM:
2570 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2571 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2572 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2573#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2574 case KVM_CAP_ASSIGN_DEV_IRQ:
2575 case KVM_CAP_PCI_2_3:
2576#endif
018d00d2
ZX		 2577 r = 1;
2578 break;
6d396b55
PB		 2579 case KVM_CAP_X86_SMM:
2580 /* SMBASE is usually relocated above 1M on modern chipsets,
2581 * and SMM handlers might indeed rely on 4G segment limits,
2582 * so do not report SMM to be available if real mode is
2583 * emulated via vm86 mode. Still, do not go to great lengths
2584 * to avoid userspace's usage of the feature, because it is a
2585 * fringe case that is not enabled except via specific settings
2586 * of the module parameters.
2587 */
2588 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2589 break;
542472b5
LV		 2590 case KVM_CAP_COALESCED_MMIO:
2591 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2592 break;
774ead3a
AK		 2593 case KVM_CAP_VAPIC:
2594 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2595 break;
f725230a 2596 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2597 r = KVM_SOFT_MAX_VCPUS;
2598 break;
2599 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2600 r = KVM_MAX_VCPUS;
2601 break;
a988b910 2602 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2603 r = KVM_USER_MEM_SLOTS;
a988b910 2604 break;
a68a6a72
MT		 2605 case KVM_CAP_PV_MMU: /* obsolete */
2606 r = 0;
2f333bcb 2607 break;
4cee4b72 2608#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2609 case KVM_CAP_IOMMU:
a1b60c1c 2610 r = iommu_present(&pci_bus_type);
62c476c7 2611 break;
4cee4b72 2612#endif
890ca9ae
HY		 2613 case KVM_CAP_MCE:
2614 r = KVM_MAX_MCE_BANKS;
2615 break;
2d5b5a66
SY		 2616 case KVM_CAP_XCRS:
2617 r = cpu_has_xsave;
2618 break;
92a1f12d
JR		 2619 case KVM_CAP_TSC_CONTROL:
2620 r = kvm_has_tsc_control;
2621 break;
018d00d2
ZX		 2622 default:
2623 r = 0;
2624 break;
2625 }
2626 return r;
2627
2628}
2629
043405e1
CO		 2630long kvm_arch_dev_ioctl(struct file *filp,
2631 unsigned int ioctl, unsigned long arg)
2632{
2633 void __user *argp = (void __user *)arg;
2634 long r;
2635
2636 switch (ioctl) {
2637 case KVM_GET_MSR_INDEX_LIST: {
2638 struct kvm_msr_list __user *user_msr_list = argp;
2639 struct kvm_msr_list msr_list;
2640 unsigned n;
2641
2642 r = -EFAULT;
2643 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2644 goto out;
2645 n = msr_list.nmsrs;
62ef68bb 2646 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2647 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2648 goto out;
2649 r = -E2BIG;
e125e7b6 2650 if (n < msr_list.nmsrs)
043405e1
CO		 2651 goto out;
2652 r = -EFAULT;
2653 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2654 num_msrs_to_save * sizeof(u32)))
2655 goto out;
e125e7b6 2656 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2657 &emulated_msrs,
62ef68bb 2658 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2659 goto out;
2660 r = 0;
2661 break;
2662 }
9c15bb1d
BP		 2663 case KVM_GET_SUPPORTED_CPUID:
2664 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2665 struct kvm_cpuid2 __user *cpuid_arg = argp;
2666 struct kvm_cpuid2 cpuid;
2667
2668 r = -EFAULT;
2669 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2670 goto out;
9c15bb1d
BP		 2671
2672 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2673 ioctl);
674eea0f
AK		 2674 if (r)
2675 goto out;
2676
2677 r = -EFAULT;
2678 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2679 goto out;
2680 r = 0;
2681 break;
2682 }
890ca9ae
HY		 2683 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2684 u64 mce_cap;
2685
2686 mce_cap = KVM_MCE_CAP_SUPPORTED;
2687 r = -EFAULT;
2688 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2689 goto out;
2690 r = 0;
2691 break;
2692 }
043405e1
CO		 2693 default:
2694 r = -EINVAL;
2695 }
2696out:
2697 return r;
2698}
2699
f5f48ee1
SY		 2700static void wbinvd_ipi(void *garbage)
2701{
2702 wbinvd();
2703}
2704
2705static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2706{
e0f0bbc5 2707 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2708}
2709
2860c4b1
PB		 2710static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2711{
2712 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2713}
2714
313a3dc7
CO		 2715void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2716{
f5f48ee1
SY		 2717 /* Address WBINVD may be executed by guest */
2718 if (need_emulate_wbinvd(vcpu)) {
2719 if (kvm_x86_ops->has_wbinvd_exit())
2720 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2721 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2722 smp_call_function_single(vcpu->cpu,
2723 wbinvd_ipi, NULL, 1);
2724 }
2725
313a3dc7 2726 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2727
0dd6a6ed
ZA		 2728 /* Apply any externally detected TSC adjustments (due to suspend) */
2729 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2730 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2731 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2732 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2733 }
8f6055cb 2734
48434c20 2735 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2736 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2737 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2738 if (tsc_delta < 0)
2739 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2740 if (check_tsc_unstable()) {
07c1419a 2741 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2742 vcpu->arch.last_guest_tsc);
2743 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2744 vcpu->arch.tsc_catchup = 1;
c285545f 2745 }
d98d07ca
MT		 2746 /*
2747 * On a host with synchronized TSC, there is no need to update
2748 * kvmclock on vcpu->cpu migration
2749 */
2750 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2751 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2752 if (vcpu->cpu != cpu)
2753 kvm_migrate_timers(vcpu);
e48672fa 2754 vcpu->cpu = cpu;
6b7d7e76 2755 }
c9aaa895 2756
c9aaa895 2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2758}
2759
2760void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2761{
02daab21 2762 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2763 kvm_put_guest_fpu(vcpu);
4ea1636b 2764 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2765}
2766
313a3dc7
CO		 2767static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2768 struct kvm_lapic_state *s)
2769{
d62caabb
AS		 2770 if (vcpu->arch.apicv_active)
2771 kvm_x86_ops->sync_pir_to_irr(vcpu);
2772
ad312c7c 2773 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2774
2775 return 0;
2776}
2777
2778static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2779 struct kvm_lapic_state *s)
2780{
64eb0620 2781 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2782 update_cr8_intercept(vcpu);
313a3dc7
CO		 2783
2784 return 0;
2785}
2786
127a457a
MG		 2787static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2788{
2789 return (!lapic_in_kernel(vcpu) ||
2790 kvm_apic_accept_pic_intr(vcpu));
2791}
2792
782d422b
MG		 2793/*
2794 * if userspace requested an interrupt window, check that the
2795 * interrupt window is open.
2796 *
2797 * No need to exit to userspace if we already have an interrupt queued.
2798 */
2799static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2800{
2801 return kvm_arch_interrupt_allowed(vcpu) &&
2802 !kvm_cpu_has_interrupt(vcpu) &&
2803 !kvm_event_needs_reinjection(vcpu) &&
2804 kvm_cpu_accept_dm_intr(vcpu);
2805}
2806
f77bc6a4
ZX		 2807static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2808 struct kvm_interrupt *irq)
2809{
02cdb50f 2810 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2811 return -EINVAL;
1c1a9ce9
SR		 2812
2813 if (!irqchip_in_kernel(vcpu->kvm)) {
2814 kvm_queue_interrupt(vcpu, irq->irq, false);
2815 kvm_make_request(KVM_REQ_EVENT, vcpu);
2816 return 0;
2817 }
2818
2819 /*
2820 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2821 * fail for in-kernel 8259.
2822 */
2823 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2824 return -ENXIO;
f77bc6a4 2825
1c1a9ce9
SR		 2826 if (vcpu->arch.pending_external_vector != -1)
2827 return -EEXIST;
f77bc6a4 2828
1c1a9ce9 2829 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2830 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2831 return 0;
2832}
2833
c4abb7c9
JK		 2834static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2835{
c4abb7c9 2836 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2837
2838 return 0;
2839}
2840
f077825a
PB		 2841static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2842{
64d60670
PB		 2843 kvm_make_request(KVM_REQ_SMI, vcpu);
2844
f077825a
PB		 2845 return 0;
2846}
2847
b209749f
AK		 2848static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2849 struct kvm_tpr_access_ctl *tac)
2850{
2851 if (tac->flags)
2852 return -EINVAL;
2853 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2854 return 0;
2855}
2856
890ca9ae
HY		 2857static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2858 u64 mcg_cap)
2859{
2860 int r;
2861 unsigned bank_num = mcg_cap & 0xff, bank;
2862
2863 r = -EINVAL;
a9e38c3e 2864 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2865 goto out;
2866 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2867 goto out;
2868 r = 0;
2869 vcpu->arch.mcg_cap = mcg_cap;
2870 /* Init IA32_MCG_CTL to all 1s */
2871 if (mcg_cap & MCG_CTL_P)
2872 vcpu->arch.mcg_ctl = ~(u64)0;
2873 /* Init IA32_MCi_CTL to all 1s */
2874 for (bank = 0; bank < bank_num; bank++)
2875 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2876out:
2877 return r;
2878}
2879
2880static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2881 struct kvm_x86_mce *mce)
2882{
2883 u64 mcg_cap = vcpu->arch.mcg_cap;
2884 unsigned bank_num = mcg_cap & 0xff;
2885 u64 *banks = vcpu->arch.mce_banks;
2886
2887 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2888 return -EINVAL;
2889 /*
2890 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2891 * reporting is disabled
2892 */
2893 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2894 vcpu->arch.mcg_ctl != ~(u64)0)
2895 return 0;
2896 banks += 4 * mce->bank;
2897 /*
2898 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2899 * reporting is disabled for the bank
2900 */
2901 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2902 return 0;
2903 if (mce->status & MCI_STATUS_UC) {
2904 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2905 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2906 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2907 return 0;
2908 }
2909 if (banks[1] & MCI_STATUS_VAL)
2910 mce->status |= MCI_STATUS_OVER;
2911 banks[2] = mce->addr;
2912 banks[3] = mce->misc;
2913 vcpu->arch.mcg_status = mce->mcg_status;
2914 banks[1] = mce->status;
2915 kvm_queue_exception(vcpu, MC_VECTOR);
2916 } else if (!(banks[1] & MCI_STATUS_VAL)
2917 || !(banks[1] & MCI_STATUS_UC)) {
2918 if (banks[1] & MCI_STATUS_VAL)
2919 mce->status |= MCI_STATUS_OVER;
2920 banks[2] = mce->addr;
2921 banks[3] = mce->misc;
2922 banks[1] = mce->status;
2923 } else
2924 banks[1] |= MCI_STATUS_OVER;
2925 return 0;
2926}
2927
3cfc3092
JK		 2928static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2929 struct kvm_vcpu_events *events)
2930{
7460fb4a 2931 process_nmi(vcpu);
03b82a30
JK		 2932 events->exception.injected =
2933 vcpu->arch.exception.pending &&
2934 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2935 events->exception.nr = vcpu->arch.exception.nr;
2936 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2937 events->exception.pad = 0;
3cfc3092
JK		 2938 events->exception.error_code = vcpu->arch.exception.error_code;
2939
03b82a30
JK		 2940 events->interrupt.injected =
2941 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2942 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2943 events->interrupt.soft = 0;
37ccdcbe 2944 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2945
2946 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2947 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2948 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2949 events->nmi.pad = 0;
3cfc3092 2950
66450a21 2951 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2952
f077825a
PB		 2953 events->smi.smm = is_smm(vcpu);
2954 events->smi.pending = vcpu->arch.smi_pending;
2955 events->smi.smm_inside_nmi =
2956 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2957 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2958
dab4b911 2959 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2960 | KVM_VCPUEVENT_VALID_SHADOW
2961 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2962 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2963}
2964
2965static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2966 struct kvm_vcpu_events *events)
2967{
dab4b911 2968 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2969 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2970 | KVM_VCPUEVENT_VALID_SHADOW
2971 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2972 return -EINVAL;
2973
7460fb4a 2974 process_nmi(vcpu);
3cfc3092
JK		 2975 vcpu->arch.exception.pending = events->exception.injected;
2976 vcpu->arch.exception.nr = events->exception.nr;
2977 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2978 vcpu->arch.exception.error_code = events->exception.error_code;
2979
2980 vcpu->arch.interrupt.pending = events->interrupt.injected;
2981 vcpu->arch.interrupt.nr = events->interrupt.nr;
2982 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2983 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2984 kvm_x86_ops->set_interrupt_shadow(vcpu,
2985 events->interrupt.shadow);
3cfc3092
JK		 2986
2987 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2988 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2989 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2990 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2991
66450a21 2992 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2993 lapic_in_kernel(vcpu))
66450a21 2994 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2995
f077825a
PB		 2996 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2997 if (events->smi.smm)
2998 vcpu->arch.hflags |= HF_SMM_MASK;
2999 else
3000 vcpu->arch.hflags &= ~HF_SMM_MASK;
3001 vcpu->arch.smi_pending = events->smi.pending;
3002 if (events->smi.smm_inside_nmi)
3003 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3004 else
3005 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3006 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3007 if (events->smi.latched_init)
3008 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3009 else
3010 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3011 }
3012 }
3013
3842d135
AK		 3014 kvm_make_request(KVM_REQ_EVENT, vcpu);
3015
3cfc3092
JK		 3016 return 0;
3017}
3018
a1efbe77
JK		 3019static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3020 struct kvm_debugregs *dbgregs)
3021{
73aaf249
JK		 3022 unsigned long val;
3023
a1efbe77 3024 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3025 kvm_get_dr(vcpu, 6, &val);
73aaf249 3026 dbgregs->dr6 = val;
a1efbe77
JK		 3027 dbgregs->dr7 = vcpu->arch.dr7;
3028 dbgregs->flags = 0;
97e69aa6 3029 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3030}
3031
3032static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3033 struct kvm_debugregs *dbgregs)
3034{
3035 if (dbgregs->flags)
3036 return -EINVAL;
3037
a1efbe77 3038 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3039 kvm_update_dr0123(vcpu);
a1efbe77 3040 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3041 kvm_update_dr6(vcpu);
a1efbe77 3042 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3043 kvm_update_dr7(vcpu);
a1efbe77 3044
a1efbe77
JK		 3045 return 0;
3046}
3047
df1daba7
PB		 3048#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3049
3050static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3051{
c47ada30 3052 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3053 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3054 u64 valid;
3055
3056 /*
3057 * Copy legacy XSAVE area, to avoid complications with CPUID
3058 * leaves 0 and 1 in the loop below.
3059 */
3060 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3061
3062 /* Set XSTATE_BV */
3063 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3064
3065 /*
3066 * Copy each region from the possibly compacted offset to the
3067 * non-compacted offset.
3068 */
d91cab78 3069 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3070 while (valid) {
3071 u64 feature = valid & -valid;
3072 int index = fls64(feature) - 1;
3073 void *src = get_xsave_addr(xsave, feature);
3074
3075 if (src) {
3076 u32 size, offset, ecx, edx;
3077 cpuid_count(XSTATE_CPUID, index,
3078 &size, &offset, &ecx, &edx);
3079 memcpy(dest + offset, src, size);
3080 }
3081
3082 valid -= feature;
3083 }
3084}
3085
3086static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3087{
c47ada30 3088 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3089 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3090 u64 valid;
3091
3092 /*
3093 * Copy legacy XSAVE area, to avoid complications with CPUID
3094 * leaves 0 and 1 in the loop below.
3095 */
3096 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3097
3098 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3099 xsave->header.xfeatures = xstate_bv;
df1daba7 3100 if (cpu_has_xsaves)
3a54450b 3101 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3102
3103 /*
3104 * Copy each region from the non-compacted offset to the
3105 * possibly compacted offset.
3106 */
d91cab78 3107 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3108 while (valid) {
3109 u64 feature = valid & -valid;
3110 int index = fls64(feature) - 1;
3111 void *dest = get_xsave_addr(xsave, feature);
3112
3113 if (dest) {
3114 u32 size, offset, ecx, edx;
3115 cpuid_count(XSTATE_CPUID, index,
3116 &size, &offset, &ecx, &edx);
3117 memcpy(dest, src + offset, size);
ee4100da 3118 }
df1daba7
PB		 3119
3120 valid -= feature;
3121 }
3122}
3123
2d5b5a66
SY		 3124static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3125 struct kvm_xsave *guest_xsave)
3126{
4344ee98 3127 if (cpu_has_xsave) {
df1daba7
PB		 3128 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3129 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3130 } else {
2d5b5a66 3131 memcpy(guest_xsave->region,
7366ed77 3132 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3133 sizeof(struct fxregs_state));
2d5b5a66 3134 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3135 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3136 }
3137}
3138
3139static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3140 struct kvm_xsave *guest_xsave)
3141{
3142 u64 xstate_bv =
3143 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3144
d7876f1b
PB		 3145 if (cpu_has_xsave) {
3146 /*
3147 * Here we allow setting states that are not present in
3148 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3149 * with old userspace.
3150 */
4ff41732 3151 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3152 return -EINVAL;
df1daba7 3153 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3154 } else {
d91cab78 3155 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3156 return -EINVAL;
7366ed77 3157 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3158 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3159 }
3160 return 0;
3161}
3162
3163static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3164 struct kvm_xcrs *guest_xcrs)
3165{
3166 if (!cpu_has_xsave) {
3167 guest_xcrs->nr_xcrs = 0;
3168 return;
3169 }
3170
3171 guest_xcrs->nr_xcrs = 1;
3172 guest_xcrs->flags = 0;
3173 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3174 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3175}
3176
3177static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3178 struct kvm_xcrs *guest_xcrs)
3179{
3180 int i, r = 0;
3181
3182 if (!cpu_has_xsave)
3183 return -EINVAL;
3184
3185 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3186 return -EINVAL;
3187
3188 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3189 /* Only support XCR0 currently */
c67a04cb 3190 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3191 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3192 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3193 break;
3194 }
3195 if (r)
3196 r = -EINVAL;
3197 return r;
3198}
3199
1c0b28c2
EM		 3200/*
3201 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3202 * stopped by the hypervisor. This function will be called from the host only.
3203 * EINVAL is returned when the host attempts to set the flag for a guest that
3204 * does not support pv clocks.
3205 */
3206static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3207{
0b79459b 3208 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3209 return -EINVAL;
51d59c6b 3210 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3211 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3212 return 0;
3213}
3214
5c919412
AS		 3215static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3216 struct kvm_enable_cap *cap)
3217{
3218 if (cap->flags)
3219 return -EINVAL;
3220
3221 switch (cap->cap) {
3222 case KVM_CAP_HYPERV_SYNIC:
3223 return kvm_hv_activate_synic(vcpu);
3224 default:
3225 return -EINVAL;
3226 }
3227}
3228
313a3dc7
CO		 3229long kvm_arch_vcpu_ioctl(struct file *filp,
3230 unsigned int ioctl, unsigned long arg)
3231{
3232 struct kvm_vcpu *vcpu = filp->private_data;
3233 void __user *argp = (void __user *)arg;
3234 int r;
d1ac91d8
AK		 3235 union {
3236 struct kvm_lapic_state *lapic;
3237 struct kvm_xsave *xsave;
3238 struct kvm_xcrs *xcrs;
3239 void *buffer;
3240 } u;
3241
3242 u.buffer = NULL;
313a3dc7
CO		 3243 switch (ioctl) {
3244 case KVM_GET_LAPIC: {
2204ae3c 3245 r = -EINVAL;
bce87cce 3246 if (!lapic_in_kernel(vcpu))
2204ae3c 3247 goto out;
d1ac91d8 3248 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3249
b772ff36 3250 r = -ENOMEM;
d1ac91d8 3251 if (!u.lapic)
b772ff36 3252 goto out;
d1ac91d8 3253 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3254 if (r)
3255 goto out;
3256 r = -EFAULT;
d1ac91d8 3257 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3258 goto out;
3259 r = 0;
3260 break;
3261 }
3262 case KVM_SET_LAPIC: {
2204ae3c 3263 r = -EINVAL;
bce87cce 3264 if (!lapic_in_kernel(vcpu))
2204ae3c 3265 goto out;
ff5c2c03 3266 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3267 if (IS_ERR(u.lapic))
3268 return PTR_ERR(u.lapic);
ff5c2c03 3269
d1ac91d8 3270 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3271 break;
3272 }
f77bc6a4
ZX		 3273 case KVM_INTERRUPT: {
3274 struct kvm_interrupt irq;
3275
3276 r = -EFAULT;
3277 if (copy_from_user(&irq, argp, sizeof irq))
3278 goto out;
3279 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3280 break;
3281 }
c4abb7c9
JK		 3282 case KVM_NMI: {
3283 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3284 break;
3285 }
f077825a
PB		 3286 case KVM_SMI: {
3287 r = kvm_vcpu_ioctl_smi(vcpu);
3288 break;
3289 }
313a3dc7
CO		 3290 case KVM_SET_CPUID: {
3291 struct kvm_cpuid __user *cpuid_arg = argp;
3292 struct kvm_cpuid cpuid;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3296 goto out;
3297 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3298 break;
3299 }
07716717
DK		 3300 case KVM_SET_CPUID2: {
3301 struct kvm_cpuid2 __user *cpuid_arg = argp;
3302 struct kvm_cpuid2 cpuid;
3303
3304 r = -EFAULT;
3305 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3306 goto out;
3307 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3308 cpuid_arg->entries);
07716717
DK		 3309 break;
3310 }
3311 case KVM_GET_CPUID2: {
3312 struct kvm_cpuid2 __user *cpuid_arg = argp;
3313 struct kvm_cpuid2 cpuid;
3314
3315 r = -EFAULT;
3316 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3317 goto out;
3318 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3319 cpuid_arg->entries);
07716717
DK		 3320 if (r)
3321 goto out;
3322 r = -EFAULT;
3323 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3324 goto out;
3325 r = 0;
3326 break;
3327 }
313a3dc7 3328 case KVM_GET_MSRS:
609e36d3 3329 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3330 break;
3331 case KVM_SET_MSRS:
3332 r = msr_io(vcpu, argp, do_set_msr, 0);
3333 break;
b209749f
AK		 3334 case KVM_TPR_ACCESS_REPORTING: {
3335 struct kvm_tpr_access_ctl tac;
3336
3337 r = -EFAULT;
3338 if (copy_from_user(&tac, argp, sizeof tac))
3339 goto out;
3340 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3341 if (r)
3342 goto out;
3343 r = -EFAULT;
3344 if (copy_to_user(argp, &tac, sizeof tac))
3345 goto out;
3346 r = 0;
3347 break;
3348 };
b93463aa
AK		 3349 case KVM_SET_VAPIC_ADDR: {
3350 struct kvm_vapic_addr va;
3351
3352 r = -EINVAL;
35754c98 3353 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3354 goto out;
3355 r = -EFAULT;
3356 if (copy_from_user(&va, argp, sizeof va))
3357 goto out;
fda4e2e8 3358 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3359 break;
3360 }
890ca9ae
HY		 3361 case KVM_X86_SETUP_MCE: {
3362 u64 mcg_cap;
3363
3364 r = -EFAULT;
3365 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3366 goto out;
3367 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3368 break;
3369 }
3370 case KVM_X86_SET_MCE: {
3371 struct kvm_x86_mce mce;
3372
3373 r = -EFAULT;
3374 if (copy_from_user(&mce, argp, sizeof mce))
3375 goto out;
3376 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3377 break;
3378 }
3cfc3092
JK		 3379 case KVM_GET_VCPU_EVENTS: {
3380 struct kvm_vcpu_events events;
3381
3382 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3383
3384 r = -EFAULT;
3385 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3386 break;
3387 r = 0;
3388 break;
3389 }
3390 case KVM_SET_VCPU_EVENTS: {
3391 struct kvm_vcpu_events events;
3392
3393 r = -EFAULT;
3394 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3395 break;
3396
3397 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3398 break;
3399 }
a1efbe77
JK		 3400 case KVM_GET_DEBUGREGS: {
3401 struct kvm_debugregs dbgregs;
3402
3403 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3404
3405 r = -EFAULT;
3406 if (copy_to_user(argp, &dbgregs,
3407 sizeof(struct kvm_debugregs)))
3408 break;
3409 r = 0;
3410 break;
3411 }
3412 case KVM_SET_DEBUGREGS: {
3413 struct kvm_debugregs dbgregs;
3414
3415 r = -EFAULT;
3416 if (copy_from_user(&dbgregs, argp,
3417 sizeof(struct kvm_debugregs)))
3418 break;
3419
3420 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3421 break;
3422 }
2d5b5a66 3423 case KVM_GET_XSAVE: {
d1ac91d8 3424 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3425 r = -ENOMEM;
d1ac91d8 3426 if (!u.xsave)
2d5b5a66
SY		 3427 break;
3428
d1ac91d8 3429 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3430
3431 r = -EFAULT;
d1ac91d8 3432 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3433 break;
3434 r = 0;
3435 break;
3436 }
3437 case KVM_SET_XSAVE: {
ff5c2c03 3438 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3439 if (IS_ERR(u.xsave))
3440 return PTR_ERR(u.xsave);
2d5b5a66 3441
d1ac91d8 3442 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3443 break;
3444 }
3445 case KVM_GET_XCRS: {
d1ac91d8 3446 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3447 r = -ENOMEM;
d1ac91d8 3448 if (!u.xcrs)
2d5b5a66
SY		 3449 break;
3450
d1ac91d8 3451 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3452
3453 r = -EFAULT;
d1ac91d8 3454 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3455 sizeof(struct kvm_xcrs)))
3456 break;
3457 r = 0;
3458 break;
3459 }
3460 case KVM_SET_XCRS: {
ff5c2c03 3461 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3462 if (IS_ERR(u.xcrs))
3463 return PTR_ERR(u.xcrs);
2d5b5a66 3464
d1ac91d8 3465 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3466 break;
3467 }
92a1f12d
JR		 3468 case KVM_SET_TSC_KHZ: {
3469 u32 user_tsc_khz;
3470
3471 r = -EINVAL;
92a1f12d
JR		 3472 user_tsc_khz = (u32)arg;
3473
3474 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3475 goto out;
3476
cc578287
ZA		 3477 if (user_tsc_khz == 0)
3478 user_tsc_khz = tsc_khz;
3479
381d585c
HZ		 3480 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3481 r = 0;
92a1f12d 3482
92a1f12d
JR		 3483 goto out;
3484 }
3485 case KVM_GET_TSC_KHZ: {
cc578287 3486 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3487 goto out;
3488 }
1c0b28c2
EM		 3489 case KVM_KVMCLOCK_CTRL: {
3490 r = kvm_set_guest_paused(vcpu);
3491 goto out;
3492 }
5c919412
AS		 3493 case KVM_ENABLE_CAP: {
3494 struct kvm_enable_cap cap;
3495
3496 r = -EFAULT;
3497 if (copy_from_user(&cap, argp, sizeof(cap)))
3498 goto out;
3499 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3500 break;
3501 }
313a3dc7
CO		 3502 default:
3503 r = -EINVAL;
3504 }
3505out:
d1ac91d8 3506 kfree(u.buffer);
313a3dc7
CO		 3507 return r;
3508}
3509
5b1c1493
CO		 3510int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3511{
3512 return VM_FAULT_SIGBUS;
3513}
3514
1fe779f8
CO		 3515static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3516{
3517 int ret;
3518
3519 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3520 return -EINVAL;
1fe779f8
CO		 3521 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3522 return ret;
3523}
3524
b927a3ce
SY		 3525static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3526 u64 ident_addr)
3527{
3528 kvm->arch.ept_identity_map_addr = ident_addr;
3529 return 0;
3530}
3531
1fe779f8
CO		 3532static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3533 u32 kvm_nr_mmu_pages)
3534{
3535 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3536 return -EINVAL;
3537
79fac95e 3538 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3539
3540 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3541 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3542
79fac95e 3543 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3544 return 0;
3545}
3546
3547static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3548{
39de71ec 3549 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3550}
3551
1fe779f8
CO		 3552static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3553{
3554 int r;
3555
3556 r = 0;
3557 switch (chip->chip_id) {
3558 case KVM_IRQCHIP_PIC_MASTER:
3559 memcpy(&chip->chip.pic,
3560 &pic_irqchip(kvm)->pics[0],
3561 sizeof(struct kvm_pic_state));
3562 break;
3563 case KVM_IRQCHIP_PIC_SLAVE:
3564 memcpy(&chip->chip.pic,
3565 &pic_irqchip(kvm)->pics[1],
3566 sizeof(struct kvm_pic_state));
3567 break;
3568 case KVM_IRQCHIP_IOAPIC:
eba0226b 3569 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3570 break;
3571 default:
3572 r = -EINVAL;
3573 break;
3574 }
3575 return r;
3576}
3577
3578static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3579{
3580 int r;
3581
3582 r = 0;
3583 switch (chip->chip_id) {
3584 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3585 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3586 memcpy(&pic_irqchip(kvm)->pics[0],
3587 &chip->chip.pic,
3588 sizeof(struct kvm_pic_state));
f4f51050 3589 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3590 break;
3591 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3592 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3593 memcpy(&pic_irqchip(kvm)->pics[1],
3594 &chip->chip.pic,
3595 sizeof(struct kvm_pic_state));
f4f51050 3596 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3597 break;
3598 case KVM_IRQCHIP_IOAPIC:
eba0226b 3599 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3600 break;
3601 default:
3602 r = -EINVAL;
3603 break;
3604 }
3605 kvm_pic_update_irq(pic_irqchip(kvm));
3606 return r;
3607}
3608
e0f63cb9
SY		 3609static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3610{
34f3941c
RK		 3611 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3612
3613 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3614
3615 mutex_lock(&kps->lock);
3616 memcpy(ps, &kps->channels, sizeof(*ps));
3617 mutex_unlock(&kps->lock);
2da29bcc 3618 return 0;
e0f63cb9
SY		 3619}
3620
3621static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3622{
0185604c 3623 int i;
09edea72
RK		 3624 struct kvm_pit *pit = kvm->arch.vpit;
3625
3626 mutex_lock(&pit->pit_state.lock);
34f3941c 3627 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3628 for (i = 0; i < 3; i++)
09edea72
RK		 3629 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3630 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3631 return 0;
e9f42757
BK		 3632}
3633
3634static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3635{
e9f42757
BK		 3636 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3637 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3638 sizeof(ps->channels));
3639 ps->flags = kvm->arch.vpit->pit_state.flags;
3640 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3641 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3642 return 0;
e9f42757
BK		 3643}
3644
3645static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3646{
2da29bcc 3647 int start = 0;
0185604c 3648 int i;
e9f42757 3649 u32 prev_legacy, cur_legacy;
09edea72
RK		 3650 struct kvm_pit *pit = kvm->arch.vpit;
3651
3652 mutex_lock(&pit->pit_state.lock);
3653 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3654 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3655 if (!prev_legacy && cur_legacy)
3656 start = 1;
09edea72
RK		 3657 memcpy(&pit->pit_state.channels, &ps->channels,
3658 sizeof(pit->pit_state.channels));
3659 pit->pit_state.flags = ps->flags;
0185604c 3660 for (i = 0; i < 3; i++)
09edea72 3661 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3662 start && i == 0);
09edea72 3663 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3664 return 0;
e0f63cb9
SY		 3665}
3666
52d939a0
MT		 3667static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3668 struct kvm_reinject_control *control)
3669{
71474e2f
RK		 3670 struct kvm_pit *pit = kvm->arch.vpit;
3671
3672 if (!pit)
52d939a0 3673 return -ENXIO;
b39c90b6 3674
71474e2f
RK		 3675 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3676 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3677 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3678 */
3679 mutex_lock(&pit->pit_state.lock);
3680 kvm_pit_set_reinject(pit, control->pit_reinject);
3681 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3682
52d939a0
MT		 3683 return 0;
3684}
3685
95d4c16c 3686/**
60c34612
TY		 3687 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3688 * @kvm: kvm instance
3689 * @log: slot id and address to which we copy the log
95d4c16c 3690 *
e108ff2f
PB		 3691 * Steps 1-4 below provide general overview of dirty page logging. See
3692 * kvm_get_dirty_log_protect() function description for additional details.
3693 *
3694 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3695 * always flush the TLB (step 4) even if previous step failed and the dirty
3696 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3697 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3698 * writes will be marked dirty for next log read.
95d4c16c 3699 *
60c34612
TY		 3700 * 1. Take a snapshot of the bit and clear it if needed.
3701 * 2. Write protect the corresponding page.
e108ff2f
PB		 3702 * 3. Copy the snapshot to the userspace.
3703 * 4. Flush TLB's if needed.
5bb064dc 3704 */
60c34612 3705int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3706{
60c34612 3707 bool is_dirty = false;
e108ff2f 3708 int r;
5bb064dc 3709
79fac95e 3710 mutex_lock(&kvm->slots_lock);
5bb064dc 3711
88178fd4
KH		 3712 /*
3713 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3714 */
3715 if (kvm_x86_ops->flush_log_dirty)
3716 kvm_x86_ops->flush_log_dirty(kvm);
3717
e108ff2f 3718 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3719
3720 /*
3721 * All the TLBs can be flushed out of mmu lock, see the comments in
3722 * kvm_mmu_slot_remove_write_access().
3723 */
e108ff2f 3724 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3725 if (is_dirty)
3726 kvm_flush_remote_tlbs(kvm);
3727
79fac95e 3728 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3729 return r;
3730}
3731
aa2fbe6d
YZ		 3732int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3733 bool line_status)
23d43cf9
CD		 3734{
3735 if (!irqchip_in_kernel(kvm))
3736 return -ENXIO;
3737
3738 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3739 irq_event->irq, irq_event->level,
3740 line_status);
23d43cf9
CD		 3741 return 0;
3742}
3743
90de4a18
NA		 3744static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3745 struct kvm_enable_cap *cap)
3746{
3747 int r;
3748
3749 if (cap->flags)
3750 return -EINVAL;
3751
3752 switch (cap->cap) {
3753 case KVM_CAP_DISABLE_QUIRKS:
3754 kvm->arch.disabled_quirks = cap->args[0];
3755 r = 0;
3756 break;
49df6397
SR		 3757 case KVM_CAP_SPLIT_IRQCHIP: {
3758 mutex_lock(&kvm->lock);
b053b2ae
SR		 3759 r = -EINVAL;
3760 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3761 goto split_irqchip_unlock;
49df6397
SR		 3762 r = -EEXIST;
3763 if (irqchip_in_kernel(kvm))
3764 goto split_irqchip_unlock;
3765 if (atomic_read(&kvm->online_vcpus))
3766 goto split_irqchip_unlock;
3767 r = kvm_setup_empty_irq_routing(kvm);
3768 if (r)
3769 goto split_irqchip_unlock;
3770 /* Pairs with irqchip_in_kernel. */
3771 smp_wmb();
3772 kvm->arch.irqchip_split = true;
b053b2ae 3773 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3774 r = 0;
3775split_irqchip_unlock:
3776 mutex_unlock(&kvm->lock);
3777 break;
3778 }
90de4a18
NA		 3779 default:
3780 r = -EINVAL;
3781 break;
3782 }
3783 return r;
3784}
3785
1fe779f8
CO		 3786long kvm_arch_vm_ioctl(struct file *filp,
3787 unsigned int ioctl, unsigned long arg)
3788{
3789 struct kvm *kvm = filp->private_data;
3790 void __user *argp = (void __user *)arg;
367e1319 3791 int r = -ENOTTY;
f0d66275
DH		 3792 /*
3793 * This union makes it completely explicit to gcc-3.x
3794 * that these two variables' stack usage should be
3795 * combined, not added together.
3796 */
3797 union {
3798 struct kvm_pit_state ps;
e9f42757 3799 struct kvm_pit_state2 ps2;
c5ff41ce 3800 struct kvm_pit_config pit_config;
f0d66275 3801 } u;
1fe779f8
CO		 3802
3803 switch (ioctl) {
3804 case KVM_SET_TSS_ADDR:
3805 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3806 break;
b927a3ce
SY		 3807 case KVM_SET_IDENTITY_MAP_ADDR: {
3808 u64 ident_addr;
3809
3810 r = -EFAULT;
3811 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3812 goto out;
3813 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3814 break;
3815 }
1fe779f8
CO		 3816 case KVM_SET_NR_MMU_PAGES:
3817 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3818 break;
3819 case KVM_GET_NR_MMU_PAGES:
3820 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3821 break;
3ddea128
MT		 3822 case KVM_CREATE_IRQCHIP: {
3823 struct kvm_pic *vpic;
3824
3825 mutex_lock(&kvm->lock);
3826 r = -EEXIST;
3827 if (kvm->arch.vpic)
3828 goto create_irqchip_unlock;
3e515705
AK		 3829 r = -EINVAL;
3830 if (atomic_read(&kvm->online_vcpus))
3831 goto create_irqchip_unlock;
1fe779f8 3832 r = -ENOMEM;
3ddea128
MT		 3833 vpic = kvm_create_pic(kvm);
3834 if (vpic) {
1fe779f8
CO		 3835 r = kvm_ioapic_init(kvm);
3836 if (r) {
175504cd 3837 mutex_lock(&kvm->slots_lock);
71ba994c 3838 kvm_destroy_pic(vpic);
175504cd 3839 mutex_unlock(&kvm->slots_lock);
3ddea128 3840 goto create_irqchip_unlock;
1fe779f8
CO		 3841 }
3842 } else
3ddea128 3843 goto create_irqchip_unlock;
399ec807
AK		 3844 r = kvm_setup_default_irq_routing(kvm);
3845 if (r) {
175504cd 3846 mutex_lock(&kvm->slots_lock);
3ddea128 3847 mutex_lock(&kvm->irq_lock);
72bb2fcd 3848 kvm_ioapic_destroy(kvm);
71ba994c 3849 kvm_destroy_pic(vpic);
3ddea128 3850 mutex_unlock(&kvm->irq_lock);
175504cd 3851 mutex_unlock(&kvm->slots_lock);
71ba994c 3852 goto create_irqchip_unlock;
399ec807 3853 }
71ba994c
PB		 3854 /* Write kvm->irq_routing before kvm->arch.vpic. */
3855 smp_wmb();
3856 kvm->arch.vpic = vpic;
3ddea128
MT		 3857 create_irqchip_unlock:
3858 mutex_unlock(&kvm->lock);
1fe779f8 3859 break;
3ddea128 3860 }
7837699f 3861 case KVM_CREATE_PIT:
c5ff41ce
JK		 3862 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3863 goto create_pit;
3864 case KVM_CREATE_PIT2:
3865 r = -EFAULT;
3866 if (copy_from_user(&u.pit_config, argp,
3867 sizeof(struct kvm_pit_config)))
3868 goto out;
3869 create_pit:
79fac95e 3870 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3871 r = -EEXIST;
3872 if (kvm->arch.vpit)
3873 goto create_pit_unlock;
7837699f 3874 r = -ENOMEM;
c5ff41ce 3875 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3876 if (kvm->arch.vpit)
3877 r = 0;
269e05e4 3878 create_pit_unlock:
79fac95e 3879 mutex_unlock(&kvm->slots_lock);
7837699f 3880 break;
1fe779f8
CO		 3881 case KVM_GET_IRQCHIP: {
3882 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3883 struct kvm_irqchip *chip;
1fe779f8 3884
ff5c2c03
SL		 3885 chip = memdup_user(argp, sizeof(*chip));
3886 if (IS_ERR(chip)) {
3887 r = PTR_ERR(chip);
1fe779f8 3888 goto out;
ff5c2c03
SL		 3889 }
3890
1fe779f8 3891 r = -ENXIO;
49df6397 3892 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3893 goto get_irqchip_out;
3894 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3895 if (r)
f0d66275 3896 goto get_irqchip_out;
1fe779f8 3897 r = -EFAULT;
f0d66275
DH		 3898 if (copy_to_user(argp, chip, sizeof *chip))
3899 goto get_irqchip_out;
1fe779f8 3900 r = 0;
f0d66275
DH		 3901 get_irqchip_out:
3902 kfree(chip);
1fe779f8
CO		 3903 break;
3904 }
3905 case KVM_SET_IRQCHIP: {
3906 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3907 struct kvm_irqchip *chip;
1fe779f8 3908
ff5c2c03
SL		 3909 chip = memdup_user(argp, sizeof(*chip));
3910 if (IS_ERR(chip)) {
3911 r = PTR_ERR(chip);
1fe779f8 3912 goto out;
ff5c2c03
SL		 3913 }
3914
1fe779f8 3915 r = -ENXIO;
49df6397 3916 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3917 goto set_irqchip_out;
3918 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3919 if (r)
f0d66275 3920 goto set_irqchip_out;
1fe779f8 3921 r = 0;
f0d66275
DH		 3922 set_irqchip_out:
3923 kfree(chip);
1fe779f8
CO		 3924 break;
3925 }
e0f63cb9 3926 case KVM_GET_PIT: {
e0f63cb9 3927 r = -EFAULT;
f0d66275 3928 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3929 goto out;
3930 r = -ENXIO;
3931 if (!kvm->arch.vpit)
3932 goto out;
f0d66275 3933 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3934 if (r)
3935 goto out;
3936 r = -EFAULT;
f0d66275 3937 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3938 goto out;
3939 r = 0;
3940 break;
3941 }
3942 case KVM_SET_PIT: {
e0f63cb9 3943 r = -EFAULT;
f0d66275 3944 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3945 goto out;
3946 r = -ENXIO;
3947 if (!kvm->arch.vpit)
3948 goto out;
f0d66275 3949 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3950 break;
3951 }
e9f42757
BK		 3952 case KVM_GET_PIT2: {
3953 r = -ENXIO;
3954 if (!kvm->arch.vpit)
3955 goto out;
3956 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3957 if (r)
3958 goto out;
3959 r = -EFAULT;
3960 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3961 goto out;
3962 r = 0;
3963 break;
3964 }
3965 case KVM_SET_PIT2: {
3966 r = -EFAULT;
3967 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3968 goto out;
3969 r = -ENXIO;
3970 if (!kvm->arch.vpit)
3971 goto out;
3972 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3973 break;
3974 }
52d939a0
MT		 3975 case KVM_REINJECT_CONTROL: {
3976 struct kvm_reinject_control control;
3977 r = -EFAULT;
3978 if (copy_from_user(&control, argp, sizeof(control)))
3979 goto out;
3980 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3981 break;
3982 }
d71ba788
PB		 3983 case KVM_SET_BOOT_CPU_ID:
3984 r = 0;
3985 mutex_lock(&kvm->lock);
3986 if (atomic_read(&kvm->online_vcpus) != 0)
3987 r = -EBUSY;
3988 else
3989 kvm->arch.bsp_vcpu_id = arg;
3990 mutex_unlock(&kvm->lock);
3991 break;
ffde22ac
ES		 3992 case KVM_XEN_HVM_CONFIG: {
3993 r = -EFAULT;
3994 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3995 sizeof(struct kvm_xen_hvm_config)))
3996 goto out;
3997 r = -EINVAL;
3998 if (kvm->arch.xen_hvm_config.flags)
3999 goto out;
4000 r = 0;
4001 break;
4002 }
afbcf7ab 4003 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4004 struct kvm_clock_data user_ns;
4005 u64 now_ns;
4006 s64 delta;
4007
4008 r = -EFAULT;
4009 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4010 goto out;
4011
4012 r = -EINVAL;
4013 if (user_ns.flags)
4014 goto out;
4015
4016 r = 0;
395c6b0a 4017 local_irq_disable();
759379dd 4018 now_ns = get_kernel_ns();
afbcf7ab 4019 delta = user_ns.clock - now_ns;
395c6b0a 4020 local_irq_enable();
afbcf7ab 4021 kvm->arch.kvmclock_offset = delta;
2e762ff7 4022 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4023 break;
4024 }
4025 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4026 struct kvm_clock_data user_ns;
4027 u64 now_ns;
4028
395c6b0a 4029 local_irq_disable();
759379dd 4030 now_ns = get_kernel_ns();
afbcf7ab 4031 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4032 local_irq_enable();
afbcf7ab 4033 user_ns.flags = 0;
97e69aa6 4034 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4035
4036 r = -EFAULT;
4037 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4038 goto out;
4039 r = 0;
4040 break;
4041 }
90de4a18
NA		 4042 case KVM_ENABLE_CAP: {
4043 struct kvm_enable_cap cap;
afbcf7ab 4044
90de4a18
NA		 4045 r = -EFAULT;
4046 if (copy_from_user(&cap, argp, sizeof(cap)))
4047 goto out;
4048 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4049 break;
4050 }
1fe779f8 4051 default:
c274e03a 4052 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4053 }
4054out:
4055 return r;
4056}
4057
a16b043c 4058static void kvm_init_msr_list(void)
043405e1
CO		 4059{
4060 u32 dummy[2];
4061 unsigned i, j;
4062
62ef68bb 4063 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4064 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4065 continue;
93c4adc7
PB		 4066
4067 /*
4068 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4069 * to the guests in some cases.
93c4adc7
PB		 4070 */
4071 switch (msrs_to_save[i]) {
4072 case MSR_IA32_BNDCFGS:
4073 if (!kvm_x86_ops->mpx_supported())
4074 continue;
4075 break;
9dbe6cf9
PB		 4076 case MSR_TSC_AUX:
4077 if (!kvm_x86_ops->rdtscp_supported())
4078 continue;
4079 break;
93c4adc7
PB		 4080 default:
4081 break;
4082 }
4083
043405e1
CO		 4084 if (j < i)
4085 msrs_to_save[j] = msrs_to_save[i];
4086 j++;
4087 }
4088 num_msrs_to_save = j;
62ef68bb
PB		 4089
4090 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4091 switch (emulated_msrs[i]) {
6d396b55
PB		 4092 case MSR_IA32_SMBASE:
4093 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4094 continue;
4095 break;
62ef68bb
PB		 4096 default:
4097 break;
4098 }
4099
4100 if (j < i)
4101 emulated_msrs[j] = emulated_msrs[i];
4102 j++;
4103 }
4104 num_emulated_msrs = j;
043405e1
CO		 4105}
4106
bda9020e
MT		 4107static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4108 const void *v)
bbd9b64e 4109{
70252a10
AK		 4110 int handled = 0;
4111 int n;
4112
4113 do {
4114 n = min(len, 8);
bce87cce 4115 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4116 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4117 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4118 break;
4119 handled += n;
4120 addr += n;
4121 len -= n;
4122 v += n;
4123 } while (len);
bbd9b64e 4124
70252a10 4125 return handled;
bbd9b64e
CO		 4126}
4127
bda9020e 4128static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4129{
70252a10
AK		 4130 int handled = 0;
4131 int n;
4132
4133 do {
4134 n = min(len, 8);
bce87cce 4135 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4136 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4137 addr, n, v))
4138 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4139 break;
4140 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4141 handled += n;
4142 addr += n;
4143 len -= n;
4144 v += n;
4145 } while (len);
bbd9b64e 4146
70252a10 4147 return handled;
bbd9b64e
CO		 4148}
4149
2dafc6c2
GN		 4150static void kvm_set_segment(struct kvm_vcpu *vcpu,
4151 struct kvm_segment *var, int seg)
4152{
4153 kvm_x86_ops->set_segment(vcpu, var, seg);
4154}
4155
4156void kvm_get_segment(struct kvm_vcpu *vcpu,
4157 struct kvm_segment *var, int seg)
4158{
4159 kvm_x86_ops->get_segment(vcpu, var, seg);
4160}
4161
54987b7a
PB		 4162gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4163 struct x86_exception *exception)
02f59dc9
JR		 4164{
4165 gpa_t t_gpa;
02f59dc9
JR		 4166
4167 BUG_ON(!mmu_is_nested(vcpu));
4168
4169 /* NPT walks are always user-walks */
4170 access |= PFERR_USER_MASK;
54987b7a 4171 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4172
4173 return t_gpa;
4174}
4175
ab9ae313
AK		 4176gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4177 struct x86_exception *exception)
1871c602
GN		 4178{
4179 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4181}
4182
ab9ae313
AK		 4183 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4184 struct x86_exception *exception)
1871c602
GN		 4185{
4186 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4187 access |= PFERR_FETCH_MASK;
ab9ae313 4188 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4189}
4190
ab9ae313
AK		 4191gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4192 struct x86_exception *exception)
1871c602
GN		 4193{
4194 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4195 access |= PFERR_WRITE_MASK;
ab9ae313 4196 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4197}
4198
4199/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4200gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4201 struct x86_exception *exception)
1871c602 4202{
ab9ae313 4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4204}
4205
4206static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4207 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4208 struct x86_exception *exception)
bbd9b64e
CO		 4209{
4210 void *data = val;
10589a46 4211 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4212
4213 while (bytes) {
14dfe855 4214 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4215 exception);
bbd9b64e 4216 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4217 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4218 int ret;
4219
bcc55cba 4220 if (gpa == UNMAPPED_GVA)
ab9ae313 4221 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4222 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4223 offset, toread);
10589a46 4224 if (ret < 0) {
c3cd7ffa 4225 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4226 goto out;
4227 }
bbd9b64e 4228
77c2002e
IE		 4229 bytes -= toread;
4230 data += toread;
4231 addr += toread;
bbd9b64e 4232 }
10589a46 4233out:
10589a46 4234 return r;
bbd9b64e 4235}
77c2002e 4236
1871c602 4237/* used for instruction fetching */
0f65dd70
AK		 4238static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4239 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4240 struct x86_exception *exception)
1871c602 4241{
0f65dd70 4242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4243 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4244 unsigned offset;
4245 int ret;
0f65dd70 4246
44583cba
PB		 4247 /* Inline kvm_read_guest_virt_helper for speed. */
4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4249 exception);
4250 if (unlikely(gpa == UNMAPPED_GVA))
4251 return X86EMUL_PROPAGATE_FAULT;
4252
4253 offset = addr & (PAGE_SIZE-1);
4254 if (WARN_ON(offset + bytes > PAGE_SIZE))
4255 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4256 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4257 offset, bytes);
44583cba
PB		 4258 if (unlikely(ret < 0))
4259 return X86EMUL_IO_NEEDED;
4260
4261 return X86EMUL_CONTINUE;
1871c602
GN		 4262}
4263
064aea77 4264int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4265 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4266 struct x86_exception *exception)
1871c602 4267{
0f65dd70 4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4270
1871c602 4271 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4272 exception);
1871c602 4273}
064aea77 4274EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4275
0f65dd70
AK		 4276static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4277 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4278 struct x86_exception *exception)
1871c602 4279{
0f65dd70 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4281 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4282}
4283
7a036a6f
RK		 4284static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4285 unsigned long addr, void *val, unsigned int bytes)
4286{
4287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4288 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4289
4290 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4291}
4292
6a4d7550 4293int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4294 gva_t addr, void *val,
2dafc6c2 4295 unsigned int bytes,
bcc55cba 4296 struct x86_exception *exception)
77c2002e 4297{
0f65dd70 4298 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4299 void *data = val;
4300 int r = X86EMUL_CONTINUE;
4301
4302 while (bytes) {
14dfe855
JR		 4303 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4304 PFERR_WRITE_MASK,
ab9ae313 4305 exception);
77c2002e
IE		 4306 unsigned offset = addr & (PAGE_SIZE-1);
4307 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4308 int ret;
4309
bcc55cba 4310 if (gpa == UNMAPPED_GVA)
ab9ae313 4311 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4312 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4313 if (ret < 0) {
c3cd7ffa 4314 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4315 goto out;
4316 }
4317
4318 bytes -= towrite;
4319 data += towrite;
4320 addr += towrite;
4321 }
4322out:
4323 return r;
4324}
6a4d7550 4325EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4326
af7cc7d1
XG		 4327static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4328 gpa_t *gpa, struct x86_exception *exception,
4329 bool write)
4330{
97d64b78
AK		 4331 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4332 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4333
be94f6b7
HH		 4334 /*
4335 * currently PKRU is only applied to ept enabled guest so
4336 * there is no pkey in EPT page table for L1 guest or EPT
4337 * shadow page table for L2 guest.
4338 */
97d64b78 4339 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4340 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4341 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4342 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4343 (gva & (PAGE_SIZE - 1));
4f022648 4344 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4345 return 1;
4346 }
4347
af7cc7d1
XG		 4348 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4349
4350 if (*gpa == UNMAPPED_GVA)
4351 return -1;
4352
4353 /* For APIC access vmexit */
4354 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4355 return 1;
4356
4f022648
XG		 4357 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4358 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4359 return 1;
4f022648 4360 }
bebb106a 4361
af7cc7d1
XG		 4362 return 0;
4363}
4364
3200f405 4365int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4366 const void *val, int bytes)
bbd9b64e
CO		 4367{
4368 int ret;
4369
54bf36aa 4370 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4371 if (ret < 0)
bbd9b64e 4372 return 0;
0eb05bf2 4373 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4374 return 1;
4375}
4376
77d197b2
XG		 4377struct read_write_emulator_ops {
4378 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4379 int bytes);
4380 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 void *val, int bytes);
4382 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 int bytes, void *val);
4384 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 void *val, int bytes);
4386 bool write;
4387};
4388
4389static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4390{
4391 if (vcpu->mmio_read_completed) {
77d197b2 4392 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4393 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4394 vcpu->mmio_read_completed = 0;
4395 return 1;
4396 }
4397
4398 return 0;
4399}
4400
4401static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 void *val, int bytes)
4403{
54bf36aa 4404 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4405}
4406
4407static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4409{
4410 return emulator_write_phys(vcpu, gpa, val, bytes);
4411}
4412
4413static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4414{
4415 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4416 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4417}
4418
4419static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4420 void *val, int bytes)
4421{
4422 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4423 return X86EMUL_IO_NEEDED;
4424}
4425
4426static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes)
4428{
f78146b0
AK		 4429 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4430
87da7e66 4431 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4432 return X86EMUL_CONTINUE;
4433}
4434
0fbe9b0b 4435static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4436 .read_write_prepare = read_prepare,
4437 .read_write_emulate = read_emulate,
4438 .read_write_mmio = vcpu_mmio_read,
4439 .read_write_exit_mmio = read_exit_mmio,
4440};
4441
0fbe9b0b 4442static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4443 .read_write_emulate = write_emulate,
4444 .read_write_mmio = write_mmio,
4445 .read_write_exit_mmio = write_exit_mmio,
4446 .write = true,
4447};
4448
22388a3c
XG		 4449static int emulator_read_write_onepage(unsigned long addr, void *val,
4450 unsigned int bytes,
4451 struct x86_exception *exception,
4452 struct kvm_vcpu *vcpu,
0fbe9b0b 4453 const struct read_write_emulator_ops *ops)
bbd9b64e 4454{
af7cc7d1
XG		 4455 gpa_t gpa;
4456 int handled, ret;
22388a3c 4457 bool write = ops->write;
f78146b0 4458 struct kvm_mmio_fragment *frag;
10589a46 4459
22388a3c 4460 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4461
af7cc7d1 4462 if (ret < 0)
bbd9b64e 4463 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4464
4465 /* For APIC access vmexit */
af7cc7d1 4466 if (ret)
bbd9b64e
CO		 4467 goto mmio;
4468
22388a3c 4469 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4470 return X86EMUL_CONTINUE;
4471
4472mmio:
4473 /*
4474 * Is this MMIO handled locally?
4475 */
22388a3c 4476 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4477 if (handled == bytes)
bbd9b64e 4478 return X86EMUL_CONTINUE;
bbd9b64e 4479
70252a10
AK		 4480 gpa += handled;
4481 bytes -= handled;
4482 val += handled;
4483
87da7e66
XG		 4484 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4485 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4486 frag->gpa = gpa;
4487 frag->data = val;
4488 frag->len = bytes;
f78146b0 4489 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4490}
4491
52eb5a6d
XL		 4492static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4493 unsigned long addr,
22388a3c
XG		 4494 void *val, unsigned int bytes,
4495 struct x86_exception *exception,
0fbe9b0b 4496 const struct read_write_emulator_ops *ops)
bbd9b64e 4497{
0f65dd70 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4499 gpa_t gpa;
4500 int rc;
4501
4502 if (ops->read_write_prepare &&
4503 ops->read_write_prepare(vcpu, val, bytes))
4504 return X86EMUL_CONTINUE;
4505
4506 vcpu->mmio_nr_fragments = 0;
0f65dd70 4507
bbd9b64e
CO		 4508 /* Crossing a page boundary? */
4509 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4510 int now;
bbd9b64e
CO		 4511
4512 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4513 rc = emulator_read_write_onepage(addr, val, now, exception,
4514 vcpu, ops);
4515
bbd9b64e
CO		 4516 if (rc != X86EMUL_CONTINUE)
4517 return rc;
4518 addr += now;
bac15531
NA		 4519 if (ctxt->mode != X86EMUL_MODE_PROT64)
4520 addr = (u32)addr;
bbd9b64e
CO		 4521 val += now;
4522 bytes -= now;
4523 }
22388a3c 4524
f78146b0
AK		 4525 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4526 vcpu, ops);
4527 if (rc != X86EMUL_CONTINUE)
4528 return rc;
4529
4530 if (!vcpu->mmio_nr_fragments)
4531 return rc;
4532
4533 gpa = vcpu->mmio_fragments[0].gpa;
4534
4535 vcpu->mmio_needed = 1;
4536 vcpu->mmio_cur_fragment = 0;
4537
87da7e66 4538 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4539 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4540 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4541 vcpu->run->mmio.phys_addr = gpa;
4542
4543 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4544}
4545
4546static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4547 unsigned long addr,
4548 void *val,
4549 unsigned int bytes,
4550 struct x86_exception *exception)
4551{
4552 return emulator_read_write(ctxt, addr, val, bytes,
4553 exception, &read_emultor);
4554}
4555
52eb5a6d 4556static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4557 unsigned long addr,
4558 const void *val,
4559 unsigned int bytes,
4560 struct x86_exception *exception)
4561{
4562 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4563 exception, &write_emultor);
bbd9b64e 4564}
bbd9b64e 4565
daea3e73
AK		 4566#define CMPXCHG_TYPE(t, ptr, old, new) \
4567 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4568
4569#ifdef CONFIG_X86_64
4570# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4571#else
4572# define CMPXCHG64(ptr, old, new) \
9749a6c0 4573 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4574#endif
4575
0f65dd70
AK		 4576static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4577 unsigned long addr,
bbd9b64e
CO		 4578 const void *old,
4579 const void *new,
4580 unsigned int bytes,
0f65dd70 4581 struct x86_exception *exception)
bbd9b64e 4582{
0f65dd70 4583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4584 gpa_t gpa;
4585 struct page *page;
4586 char *kaddr;
4587 bool exchanged;
2bacc55c 4588
daea3e73
AK		 4589 /* guests cmpxchg8b have to be emulated atomically */
4590 if (bytes > 8 || (bytes & (bytes - 1)))
4591 goto emul_write;
10589a46 4592
daea3e73 4593 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4594
daea3e73
AK		 4595 if (gpa == UNMAPPED_GVA ||
4596 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4597 goto emul_write;
2bacc55c 4598
daea3e73
AK		 4599 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4600 goto emul_write;
72dc67a6 4601
54bf36aa 4602 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4603 if (is_error_page(page))
c19b8bd6 4604 goto emul_write;
72dc67a6 4605
8fd75e12 4606 kaddr = kmap_atomic(page);
daea3e73
AK		 4607 kaddr += offset_in_page(gpa);
4608 switch (bytes) {
4609 case 1:
4610 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4611 break;
4612 case 2:
4613 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4614 break;
4615 case 4:
4616 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4617 break;
4618 case 8:
4619 exchanged = CMPXCHG64(kaddr, old, new);
4620 break;
4621 default:
4622 BUG();
2bacc55c 4623 }
8fd75e12 4624 kunmap_atomic(kaddr);
daea3e73
AK		 4625 kvm_release_page_dirty(page);
4626
4627 if (!exchanged)
4628 return X86EMUL_CMPXCHG_FAILED;
4629
54bf36aa 4630 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4631 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4632
4633 return X86EMUL_CONTINUE;
4a5f48f6 4634
3200f405 4635emul_write:
daea3e73 4636 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4637
0f65dd70 4638 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4639}
4640
cf8f70bf
GN		 4641static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4642{
4643 /* TODO: String I/O for in kernel device */
4644 int r;
4645
4646 if (vcpu->arch.pio.in)
e32edf4f 4647 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4648 vcpu->arch.pio.size, pd);
4649 else
e32edf4f 4650 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4651 vcpu->arch.pio.port, vcpu->arch.pio.size,
4652 pd);
4653 return r;
4654}
4655
6f6fbe98
XG		 4656static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4657 unsigned short port, void *val,
4658 unsigned int count, bool in)
cf8f70bf 4659{
cf8f70bf 4660 vcpu->arch.pio.port = port;
6f6fbe98 4661 vcpu->arch.pio.in = in;
7972995b 4662 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4663 vcpu->arch.pio.size = size;
4664
4665 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4666 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4667 return 1;
4668 }
4669
4670 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4671 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4672 vcpu->run->io.size = size;
4673 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4674 vcpu->run->io.count = count;
4675 vcpu->run->io.port = port;
4676
4677 return 0;
4678}
4679
6f6fbe98
XG		 4680static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4681 int size, unsigned short port, void *val,
4682 unsigned int count)
cf8f70bf 4683{
ca1d4a9e 4684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4685 int ret;
ca1d4a9e 4686
6f6fbe98
XG		 4687 if (vcpu->arch.pio.count)
4688 goto data_avail;
cf8f70bf 4689
6f6fbe98
XG		 4690 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4691 if (ret) {
4692data_avail:
4693 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4694 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4695 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4696 return 1;
4697 }
4698
cf8f70bf
GN		 4699 return 0;
4700}
4701
6f6fbe98
XG		 4702static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4703 int size, unsigned short port,
4704 const void *val, unsigned int count)
4705{
4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4707
4708 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4709 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4710 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4711}
4712
bbd9b64e
CO		 4713static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4714{
4715 return kvm_x86_ops->get_segment_base(vcpu, seg);
4716}
4717
3cb16fe7 4718static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4719{
3cb16fe7 4720 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4721}
4722
5cb56059 4723int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4724{
4725 if (!need_emulate_wbinvd(vcpu))
4726 return X86EMUL_CONTINUE;
4727
4728 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4729 int cpu = get_cpu();
4730
4731 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4732 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4733 wbinvd_ipi, NULL, 1);
2eec7343 4734 put_cpu();
f5f48ee1 4735 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4736 } else
4737 wbinvd();
f5f48ee1
SY		 4738 return X86EMUL_CONTINUE;
4739}
5cb56059
JS		 4740
4741int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4742{
4743 kvm_x86_ops->skip_emulated_instruction(vcpu);
4744 return kvm_emulate_wbinvd_noskip(vcpu);
4745}
f5f48ee1
SY		 4746EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4747
5cb56059
JS		 4748
4749
bcaf5cc5
AK		 4750static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4751{
5cb56059 4752 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4753}
4754
52eb5a6d
XL		 4755static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4756 unsigned long *dest)
bbd9b64e 4757{
16f8a6f9 4758 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4759}
4760
52eb5a6d
XL		 4761static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4762 unsigned long value)
bbd9b64e 4763{
338dbc97 4764
717746e3 4765 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4766}
4767
52a46617 4768static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4769{
52a46617 4770 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4771}
4772
717746e3 4773static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4774{
717746e3 4775 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4776 unsigned long value;
4777
4778 switch (cr) {
4779 case 0:
4780 value = kvm_read_cr0(vcpu);
4781 break;
4782 case 2:
4783 value = vcpu->arch.cr2;
4784 break;
4785 case 3:
9f8fe504 4786 value = kvm_read_cr3(vcpu);
52a46617
GN		 4787 break;
4788 case 4:
4789 value = kvm_read_cr4(vcpu);
4790 break;
4791 case 8:
4792 value = kvm_get_cr8(vcpu);
4793 break;
4794 default:
a737f256 4795 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4796 return 0;
4797 }
4798
4799 return value;
4800}
4801
717746e3 4802static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4803{
717746e3 4804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4805 int res = 0;
4806
52a46617
GN		 4807 switch (cr) {
4808 case 0:
49a9b07e 4809 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4810 break;
4811 case 2:
4812 vcpu->arch.cr2 = val;
4813 break;
4814 case 3:
2390218b 4815 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4816 break;
4817 case 4:
a83b29c6 4818 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4819 break;
4820 case 8:
eea1cff9 4821 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4822 break;
4823 default:
a737f256 4824 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4825 res = -1;
52a46617 4826 }
0f12244f
GN		 4827
4828 return res;
52a46617
GN		 4829}
4830
717746e3 4831static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4832{
717746e3 4833 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4834}
4835
4bff1e86 4836static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4837{
4bff1e86 4838 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4839}
4840
4bff1e86 4841static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4842{
4bff1e86 4843 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4844}
4845
1ac9d0cf
AK		 4846static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4847{
4848 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4849}
4850
4851static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4852{
4853 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4854}
4855
4bff1e86
AK		 4856static unsigned long emulator_get_cached_segment_base(
4857 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4858{
4bff1e86 4859 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4860}
4861
1aa36616
AK		 4862static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4863 struct desc_struct *desc, u32 *base3,
4864 int seg)
2dafc6c2
GN		 4865{
4866 struct kvm_segment var;
4867
4bff1e86 4868 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4869 *selector = var.selector;
2dafc6c2 4870
378a8b09
GN		 4871 if (var.unusable) {
4872 memset(desc, 0, sizeof(*desc));
2dafc6c2 4873 return false;
378a8b09 4874 }
2dafc6c2
GN		 4875
4876 if (var.g)
4877 var.limit >>= 12;
4878 set_desc_limit(desc, var.limit);
4879 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4880#ifdef CONFIG_X86_64
4881 if (base3)
4882 *base3 = var.base >> 32;
4883#endif
2dafc6c2
GN		 4884 desc->type = var.type;
4885 desc->s = var.s;
4886 desc->dpl = var.dpl;
4887 desc->p = var.present;
4888 desc->avl = var.avl;
4889 desc->l = var.l;
4890 desc->d = var.db;
4891 desc->g = var.g;
4892
4893 return true;
4894}
4895
1aa36616
AK		 4896static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4897 struct desc_struct *desc, u32 base3,
4898 int seg)
2dafc6c2 4899{
4bff1e86 4900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4901 struct kvm_segment var;
4902
1aa36616 4903 var.selector = selector;
2dafc6c2 4904 var.base = get_desc_base(desc);
5601d05b
GN		 4905#ifdef CONFIG_X86_64
4906 var.base |= ((u64)base3) << 32;
4907#endif
2dafc6c2
GN		 4908 var.limit = get_desc_limit(desc);
4909 if (desc->g)
4910 var.limit = (var.limit << 12) | 0xfff;
4911 var.type = desc->type;
2dafc6c2
GN		 4912 var.dpl = desc->dpl;
4913 var.db = desc->d;
4914 var.s = desc->s;
4915 var.l = desc->l;
4916 var.g = desc->g;
4917 var.avl = desc->avl;
4918 var.present = desc->p;
4919 var.unusable = !var.present;
4920 var.padding = 0;
4921
4922 kvm_set_segment(vcpu, &var, seg);
4923 return;
4924}
4925
717746e3
AK		 4926static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4927 u32 msr_index, u64 *pdata)
4928{
609e36d3
PB		 4929 struct msr_data msr;
4930 int r;
4931
4932 msr.index = msr_index;
4933 msr.host_initiated = false;
4934 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4935 if (r)
4936 return r;
4937
4938 *pdata = msr.data;
4939 return 0;
717746e3
AK		 4940}
4941
4942static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4943 u32 msr_index, u64 data)
4944{
8fe8ab46
WA		 4945 struct msr_data msr;
4946
4947 msr.data = data;
4948 msr.index = msr_index;
4949 msr.host_initiated = false;
4950 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4951}
4952
64d60670
PB		 4953static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4954{
4955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4956
4957 return vcpu->arch.smbase;
4958}
4959
4960static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4961{
4962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4963
4964 vcpu->arch.smbase = smbase;
4965}
4966
67f4d428
NA		 4967static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4968 u32 pmc)
4969{
c6702c9d 4970 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4971}
4972
222d21aa
AK		 4973static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4974 u32 pmc, u64 *pdata)
4975{
c6702c9d 4976 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4977}
4978
6c3287f7
AK		 4979static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4980{
4981 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4982}
4983
5037f6f3
AK		 4984static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4985{
4986 preempt_disable();
5197b808 4987 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4988 /*
4989 * CR0.TS may reference the host fpu state, not the guest fpu state,
4990 * so it may be clear at this point.
4991 */
4992 clts();
4993}
4994
4995static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4996{
4997 preempt_enable();
4998}
4999
2953538e 5000static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5001 struct x86_instruction_info *info,
c4f035c6
AK		 5002 enum x86_intercept_stage stage)
5003{
2953538e 5004 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5005}
5006
0017f93a 5007static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5008 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5009{
0017f93a 5010 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5011}
5012
dd856efa
AK		 5013static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5014{
5015 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5016}
5017
5018static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5019{
5020 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5021}
5022
801806d9
NA		 5023static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5024{
5025 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5026}
5027
0225fb50 5028static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5029 .read_gpr = emulator_read_gpr,
5030 .write_gpr = emulator_write_gpr,
1871c602 5031 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5032 .write_std = kvm_write_guest_virt_system,
7a036a6f 5033 .read_phys = kvm_read_guest_phys_system,
1871c602 5034 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5035 .read_emulated = emulator_read_emulated,
5036 .write_emulated = emulator_write_emulated,
5037 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5038 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5039 .pio_in_emulated = emulator_pio_in_emulated,
5040 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5041 .get_segment = emulator_get_segment,
5042 .set_segment = emulator_set_segment,
5951c442 5043 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5044 .get_gdt = emulator_get_gdt,
160ce1f1 5045 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5046 .set_gdt = emulator_set_gdt,
5047 .set_idt = emulator_set_idt,
52a46617
GN		 5048 .get_cr = emulator_get_cr,
5049 .set_cr = emulator_set_cr,
9c537244 5050 .cpl = emulator_get_cpl,
35aa5375
GN		 5051 .get_dr = emulator_get_dr,
5052 .set_dr = emulator_set_dr,
64d60670
PB		 5053 .get_smbase = emulator_get_smbase,
5054 .set_smbase = emulator_set_smbase,
717746e3
AK		 5055 .set_msr = emulator_set_msr,
5056 .get_msr = emulator_get_msr,
67f4d428 5057 .check_pmc = emulator_check_pmc,
222d21aa 5058 .read_pmc = emulator_read_pmc,
6c3287f7 5059 .halt = emulator_halt,
bcaf5cc5 5060 .wbinvd = emulator_wbinvd,
d6aa1000 5061 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5062 .get_fpu = emulator_get_fpu,
5063 .put_fpu = emulator_put_fpu,
c4f035c6 5064 .intercept = emulator_intercept,
bdb42f5a 5065 .get_cpuid = emulator_get_cpuid,
801806d9 5066 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5067};
5068
95cb2295
GN		 5069static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5070{
37ccdcbe 5071 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5072 /*
5073 * an sti; sti; sequence only disable interrupts for the first
5074 * instruction. So, if the last instruction, be it emulated or
5075 * not, left the system with the INT_STI flag enabled, it
5076 * means that the last instruction is an sti. We should not
5077 * leave the flag on in this case. The same goes for mov ss
5078 */
37ccdcbe
PB		 5079 if (int_shadow & mask)
5080 mask = 0;
6addfc42 5081 if (unlikely(int_shadow || mask)) {
95cb2295 5082 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5083 if (!mask)
5084 kvm_make_request(KVM_REQ_EVENT, vcpu);
5085 }
95cb2295
GN		 5086}
5087
ef54bcfe 5088static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5089{
5090 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5091 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5092 return kvm_propagate_fault(vcpu, &ctxt->exception);
5093
5094 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5095 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5096 ctxt->exception.error_code);
54b8486f 5097 else
da9cb575 5098 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5099 return false;
54b8486f
GN		 5100}
5101
8ec4722d
MG		 5102static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5103{
adf52235 5104 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5105 int cs_db, cs_l;
5106
8ec4722d
MG		 5107 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5108
adf52235
TY		 5109 ctxt->eflags = kvm_get_rflags(vcpu);
5110 ctxt->eip = kvm_rip_read(vcpu);
5111 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5112 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5113 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5114 cs_db ? X86EMUL_MODE_PROT32 :
5115 X86EMUL_MODE_PROT16;
a584539b 5116 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5117 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5118 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5119 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5120
dd856efa 5121 init_decode_cache(ctxt);
7ae441ea 5122 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5123}
5124
71f9833b 5125int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5126{
9d74191a 5127 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5128 int ret;
5129
5130 init_emulate_ctxt(vcpu);
5131
9dac77fa
AK		 5132 ctxt->op_bytes = 2;
5133 ctxt->ad_bytes = 2;
5134 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5135 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5136
5137 if (ret != X86EMUL_CONTINUE)
5138 return EMULATE_FAIL;
5139
9dac77fa 5140 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5141 kvm_rip_write(vcpu, ctxt->eip);
5142 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5143
5144 if (irq == NMI_VECTOR)
7460fb4a 5145 vcpu->arch.nmi_pending = 0;
63995653
MG		 5146 else
5147 vcpu->arch.interrupt.pending = false;
5148
5149 return EMULATE_DONE;
5150}
5151EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5152
6d77dbfc
GN		 5153static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5154{
fc3a9157
JR		 5155 int r = EMULATE_DONE;
5156
6d77dbfc
GN		 5157 ++vcpu->stat.insn_emulation_fail;
5158 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5159 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5160 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5161 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5162 vcpu->run->internal.ndata = 0;
5163 r = EMULATE_FAIL;
5164 }
6d77dbfc 5165 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5166
5167 return r;
6d77dbfc
GN		 5168}
5169
93c05d3e 5170static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5171 bool write_fault_to_shadow_pgtable,
5172 int emulation_type)
a6f177ef 5173{
95b3cf69 5174 gpa_t gpa = cr2;
ba049e93 5175 kvm_pfn_t pfn;
a6f177ef 5176
991eebf9
GN		 5177 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5178 return false;
5179
95b3cf69
XG		 5180 if (!vcpu->arch.mmu.direct_map) {
5181 /*
5182 * Write permission should be allowed since only
5183 * write access need to be emulated.
5184 */
5185 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5186
95b3cf69
XG		 5187 /*
5188 * If the mapping is invalid in guest, let cpu retry
5189 * it to generate fault.
5190 */
5191 if (gpa == UNMAPPED_GVA)
5192 return true;
5193 }
a6f177ef 5194
8e3d9d06
XG		 5195 /*
5196 * Do not retry the unhandleable instruction if it faults on the
5197 * readonly host memory, otherwise it will goto a infinite loop:
5198 * retry instruction -> write #PF -> emulation fail -> retry
5199 * instruction -> ...
5200 */
5201 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5202
5203 /*
5204 * If the instruction failed on the error pfn, it can not be fixed,
5205 * report the error to userspace.
5206 */
5207 if (is_error_noslot_pfn(pfn))
5208 return false;
5209
5210 kvm_release_pfn_clean(pfn);
5211
5212 /* The instructions are well-emulated on direct mmu. */
5213 if (vcpu->arch.mmu.direct_map) {
5214 unsigned int indirect_shadow_pages;
5215
5216 spin_lock(&vcpu->kvm->mmu_lock);
5217 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5218 spin_unlock(&vcpu->kvm->mmu_lock);
5219
5220 if (indirect_shadow_pages)
5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5222
a6f177ef 5223 return true;
8e3d9d06 5224 }
a6f177ef 5225
95b3cf69
XG		 5226 /*
5227 * if emulation was due to access to shadowed page table
5228 * and it failed try to unshadow page and re-enter the
5229 * guest to let CPU execute the instruction.
5230 */
5231 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5232
5233 /*
5234 * If the access faults on its page table, it can not
5235 * be fixed by unprotecting shadow page and it should
5236 * be reported to userspace.
5237 */
5238 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5239}
5240
1cb3f3ae
XG		 5241static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5242 unsigned long cr2, int emulation_type)
5243{
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5246
5247 last_retry_eip = vcpu->arch.last_retry_eip;
5248 last_retry_addr = vcpu->arch.last_retry_addr;
5249
5250 /*
5251 * If the emulation is caused by #PF and it is non-page_table
5252 * writing instruction, it means the VM-EXIT is caused by shadow
5253 * page protected, we can zap the shadow page and retry this
5254 * instruction directly.
5255 *
5256 * Note: if the guest uses a non-page-table modifying instruction
5257 * on the PDE that points to the instruction, then we will unmap
5258 * the instruction and go to an infinite loop. So, we cache the
5259 * last retried eip and the last fault address, if we meet the eip
5260 * and the address again, we can break out of the potential infinite
5261 * loop.
5262 */
5263 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5264
5265 if (!(emulation_type & EMULTYPE_RETRY))
5266 return false;
5267
5268 if (x86_page_table_writing_insn(ctxt))
5269 return false;
5270
5271 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5272 return false;
5273
5274 vcpu->arch.last_retry_eip = ctxt->eip;
5275 vcpu->arch.last_retry_addr = cr2;
5276
5277 if (!vcpu->arch.mmu.direct_map)
5278 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5279
22368028 5280 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5281
5282 return true;
5283}
5284
716d51ab
GN		 5285static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5286static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5287
64d60670 5288static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5289{
64d60670 5290 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5291 /* This is a good place to trace that we are exiting SMM. */
5292 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5293
64d60670
PB		 5294 if (unlikely(vcpu->arch.smi_pending)) {
5295 kvm_make_request(KVM_REQ_SMI, vcpu);
5296 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5297 } else {
5298 /* Process a latched INIT, if any. */
5299 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5300 }
5301 }
699023e2
PB		 5302
5303 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5304}
5305
5306static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5307{
5308 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5309
a584539b 5310 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5311
5312 if (changed & HF_SMM_MASK)
5313 kvm_smm_changed(vcpu);
a584539b
PB		 5314}
5315
4a1e10d5
PB		 5316static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5317 unsigned long *db)
5318{
5319 u32 dr6 = 0;
5320 int i;
5321 u32 enable, rwlen;
5322
5323 enable = dr7;
5324 rwlen = dr7 >> 16;
5325 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5326 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5327 dr6 |= (1 << i);
5328 return dr6;
5329}
5330
6addfc42 5331static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5332{
5333 struct kvm_run *kvm_run = vcpu->run;
5334
5335 /*
6addfc42
PB		 5336 * rflags is the old, "raw" value of the flags. The new value has
5337 * not been saved yet.
663f4c61
PB		 5338 *
5339 * This is correct even for TF set by the guest, because "the
5340 * processor will not generate this exception after the instruction
5341 * that sets the TF flag".
5342 */
663f4c61
PB		 5343 if (unlikely(rflags & X86_EFLAGS_TF)) {
5344 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5345 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5346 DR6_RTM;
663f4c61
PB		 5347 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5348 kvm_run->debug.arch.exception = DB_VECTOR;
5349 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5350 *r = EMULATE_USER_EXIT;
5351 } else {
5352 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5353 /*
5354 * "Certain debug exceptions may clear bit 0-3. The
5355 * remaining contents of the DR6 register are never
5356 * cleared by the processor".
5357 */
5358 vcpu->arch.dr6 &= ~15;
6f43ed01 5359 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5360 kvm_queue_exception(vcpu, DB_VECTOR);
5361 }
5362 }
5363}
5364
4a1e10d5
PB		 5365static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5366{
4a1e10d5
PB		 5367 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5368 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5369 struct kvm_run *kvm_run = vcpu->run;
5370 unsigned long eip = kvm_get_linear_rip(vcpu);
5371 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5372 vcpu->arch.guest_debug_dr7,
5373 vcpu->arch.eff_db);
5374
5375 if (dr6 != 0) {
6f43ed01 5376 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5377 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5378 kvm_run->debug.arch.exception = DB_VECTOR;
5379 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5380 *r = EMULATE_USER_EXIT;
5381 return true;
5382 }
5383 }
5384
4161a569
NA		 5385 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5386 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5387 unsigned long eip = kvm_get_linear_rip(vcpu);
5388 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5389 vcpu->arch.dr7,
5390 vcpu->arch.db);
5391
5392 if (dr6 != 0) {
5393 vcpu->arch.dr6 &= ~15;
6f43ed01 5394 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5395 kvm_queue_exception(vcpu, DB_VECTOR);
5396 *r = EMULATE_DONE;
5397 return true;
5398 }
5399 }
5400
5401 return false;
5402}
5403
51d8b661
AP		 5404int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5405 unsigned long cr2,
dc25e89e
AP		 5406 int emulation_type,
5407 void *insn,
5408 int insn_len)
bbd9b64e 5409{
95cb2295 5410 int r;
9d74191a 5411 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5412 bool writeback = true;
93c05d3e 5413 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5414
93c05d3e
XG		 5415 /*
5416 * Clear write_fault_to_shadow_pgtable here to ensure it is
5417 * never reused.
5418 */
5419 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5420 kvm_clear_exception_queue(vcpu);
8d7d8102 5421
571008da 5422 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5423 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5424
5425 /*
5426 * We will reenter on the same instruction since
5427 * we do not set complete_userspace_io. This does not
5428 * handle watchpoints yet, those would be handled in
5429 * the emulate_ops.
5430 */
5431 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5432 return r;
5433
9d74191a
TY		 5434 ctxt->interruptibility = 0;
5435 ctxt->have_exception = false;
e0ad0b47 5436 ctxt->exception.vector = -1;
9d74191a 5437 ctxt->perm_ok = false;
bbd9b64e 5438
b51e974f 5439 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5440
9d74191a 5441 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5442
e46479f8 5443 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5444 ++vcpu->stat.insn_emulation;
1d2887e2 5445 if (r != EMULATION_OK) {
4005996e
AK		 5446 if (emulation_type & EMULTYPE_TRAP_UD)
5447 return EMULATE_FAIL;
991eebf9
GN		 5448 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5449 emulation_type))
bbd9b64e 5450 return EMULATE_DONE;
6d77dbfc
GN		 5451 if (emulation_type & EMULTYPE_SKIP)
5452 return EMULATE_FAIL;
5453 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5454 }
5455 }
5456
ba8afb6b 5457 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5458 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5459 if (ctxt->eflags & X86_EFLAGS_RF)
5460 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5461 return EMULATE_DONE;
5462 }
5463
1cb3f3ae
XG		 5464 if (retry_instruction(ctxt, cr2, emulation_type))
5465 return EMULATE_DONE;
5466
7ae441ea 5467 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5468 changes registers values during IO operation */
7ae441ea
GN		 5469 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5470 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5471 emulator_invalidate_register_cache(ctxt);
7ae441ea 5472 }
4d2179e1 5473
5cd21917 5474restart:
9d74191a 5475 r = x86_emulate_insn(ctxt);
bbd9b64e 5476
775fde86
JR		 5477 if (r == EMULATION_INTERCEPTED)
5478 return EMULATE_DONE;
5479
d2ddd1c4 5480 if (r == EMULATION_FAILED) {
991eebf9
GN		 5481 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5482 emulation_type))
c3cd7ffa
GN		 5483 return EMULATE_DONE;
5484
6d77dbfc 5485 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5486 }
5487
9d74191a 5488 if (ctxt->have_exception) {
d2ddd1c4 5489 r = EMULATE_DONE;
ef54bcfe
PB		 5490 if (inject_emulated_exception(vcpu))
5491 return r;
d2ddd1c4 5492 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5493 if (!vcpu->arch.pio.in) {
5494 /* FIXME: return into emulator if single-stepping. */
3457e419 5495 vcpu->arch.pio.count = 0;
0912c977 5496 } else {
7ae441ea 5497 writeback = false;
716d51ab
GN		 5498 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5499 }
ac0a48c3 5500 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5501 } else if (vcpu->mmio_needed) {
5502 if (!vcpu->mmio_is_write)
5503 writeback = false;
ac0a48c3 5504 r = EMULATE_USER_EXIT;
716d51ab 5505 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5506 } else if (r == EMULATION_RESTART)
5cd21917 5507 goto restart;
d2ddd1c4
GN		 5508 else
5509 r = EMULATE_DONE;
f850e2e6 5510
7ae441ea 5511 if (writeback) {
6addfc42 5512 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5513 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5514 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5515 if (vcpu->arch.hflags != ctxt->emul_flags)
5516 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5517 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5518 if (r == EMULATE_DONE)
6addfc42 5519 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5520 if (!ctxt->have_exception ||
5521 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5522 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5523
5524 /*
5525 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5526 * do nothing, and it will be requested again as soon as
5527 * the shadow expires. But we still need to check here,
5528 * because POPF has no interrupt shadow.
5529 */
5530 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5532 } else
5533 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5534
5535 return r;
de7d789a 5536}
51d8b661 5537EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5538
cf8f70bf 5539int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5540{
cf8f70bf 5541 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5542 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5543 size, port, &val, 1);
cf8f70bf 5544 /* do not return to emulator after return from userspace */
7972995b 5545 vcpu->arch.pio.count = 0;
de7d789a
CO		 5546 return ret;
5547}
cf8f70bf 5548EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5549
8cfdc000
ZA		 5550static void tsc_bad(void *info)
5551{
0a3aee0d 5552 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5553}
5554
5555static void tsc_khz_changed(void *data)
c8076604 5556{
8cfdc000
ZA		 5557 struct cpufreq_freqs *freq = data;
5558 unsigned long khz = 0;
5559
5560 if (data)
5561 khz = freq->new;
5562 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5563 khz = cpufreq_quick_get(raw_smp_processor_id());
5564 if (!khz)
5565 khz = tsc_khz;
0a3aee0d 5566 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5567}
5568
c8076604
GH		 5569static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5570 void *data)
5571{
5572 struct cpufreq_freqs *freq = data;
5573 struct kvm *kvm;
5574 struct kvm_vcpu *vcpu;
5575 int i, send_ipi = 0;
5576
8cfdc000
ZA		 5577 /*
5578 * We allow guests to temporarily run on slowing clocks,
5579 * provided we notify them after, or to run on accelerating
5580 * clocks, provided we notify them before. Thus time never
5581 * goes backwards.
5582 *
5583 * However, we have a problem. We can't atomically update
5584 * the frequency of a given CPU from this function; it is
5585 * merely a notifier, which can be called from any CPU.
5586 * Changing the TSC frequency at arbitrary points in time
5587 * requires a recomputation of local variables related to
5588 * the TSC for each VCPU. We must flag these local variables
5589 * to be updated and be sure the update takes place with the
5590 * new frequency before any guests proceed.
5591 *
5592 * Unfortunately, the combination of hotplug CPU and frequency
5593 * change creates an intractable locking scenario; the order
5594 * of when these callouts happen is undefined with respect to
5595 * CPU hotplug, and they can race with each other. As such,
5596 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5597 * undefined; you can actually have a CPU frequency change take
5598 * place in between the computation of X and the setting of the
5599 * variable. To protect against this problem, all updates of
5600 * the per_cpu tsc_khz variable are done in an interrupt
5601 * protected IPI, and all callers wishing to update the value
5602 * must wait for a synchronous IPI to complete (which is trivial
5603 * if the caller is on the CPU already). This establishes the
5604 * necessary total order on variable updates.
5605 *
5606 * Note that because a guest time update may take place
5607 * anytime after the setting of the VCPU's request bit, the
5608 * correct TSC value must be set before the request. However,
5609 * to ensure the update actually makes it to any guest which
5610 * starts running in hardware virtualization between the set
5611 * and the acquisition of the spinlock, we must also ping the
5612 * CPU after setting the request bit.
5613 *
5614 */
5615
c8076604
GH		 5616 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5617 return 0;
5618 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5619 return 0;
8cfdc000
ZA		 5620
5621 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5622
2f303b74 5623 spin_lock(&kvm_lock);
c8076604 5624 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5625 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5626 if (vcpu->cpu != freq->cpu)
5627 continue;
c285545f 5628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5629 if (vcpu->cpu != smp_processor_id())
8cfdc000 5630 send_ipi = 1;
c8076604
GH		 5631 }
5632 }
2f303b74 5633 spin_unlock(&kvm_lock);
c8076604
GH		 5634
5635 if (freq->old < freq->new && send_ipi) {
5636 /*
5637 * We upscale the frequency. Must make the guest
5638 * doesn't see old kvmclock values while running with
5639 * the new frequency, otherwise we risk the guest sees
5640 * time go backwards.
5641 *
5642 * In case we update the frequency for another cpu
5643 * (which might be in guest context) send an interrupt
5644 * to kick the cpu out of guest context. Next time
5645 * guest context is entered kvmclock will be updated,
5646 * so the guest will not see stale values.
5647 */
8cfdc000 5648 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5649 }
5650 return 0;
5651}
5652
5653static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5654 .notifier_call = kvmclock_cpufreq_notifier
5655};
5656
5657static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5658 unsigned long action, void *hcpu)
5659{
5660 unsigned int cpu = (unsigned long)hcpu;
5661
5662 switch (action) {
5663 case CPU_ONLINE:
5664 case CPU_DOWN_FAILED:
5665 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5666 break;
5667 case CPU_DOWN_PREPARE:
5668 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5669 break;
5670 }
5671 return NOTIFY_OK;
5672}
5673
5674static struct notifier_block kvmclock_cpu_notifier_block = {
5675 .notifier_call = kvmclock_cpu_notifier,
5676 .priority = -INT_MAX
c8076604
GH		 5677};
5678
b820cc0c
ZA		 5679static void kvm_timer_init(void)
5680{
5681 int cpu;
5682
c285545f 5683 max_tsc_khz = tsc_khz;
460dd42e
SB		 5684
5685 cpu_notifier_register_begin();
b820cc0c 5686 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5687#ifdef CONFIG_CPU_FREQ
5688 struct cpufreq_policy policy;
5689 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5690 cpu = get_cpu();
5691 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5692 if (policy.cpuinfo.max_freq)
5693 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5694 put_cpu();
c285545f 5695#endif
b820cc0c
ZA		 5696 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5697 CPUFREQ_TRANSITION_NOTIFIER);
5698 }
c285545f 5699 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5700 for_each_online_cpu(cpu)
5701 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5702
5703 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5704 cpu_notifier_register_done();
5705
b820cc0c
ZA		 5706}
5707
ff9d07a0
ZY		 5708static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5709
f5132b01 5710int kvm_is_in_guest(void)
ff9d07a0 5711{
086c9855 5712 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5713}
5714
5715static int kvm_is_user_mode(void)
5716{
5717 int user_mode = 3;
dcf46b94 5718
086c9855
AS		 5719 if (__this_cpu_read(current_vcpu))
5720 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5721
ff9d07a0
ZY		 5722 return user_mode != 0;
5723}
5724
5725static unsigned long kvm_get_guest_ip(void)
5726{
5727 unsigned long ip = 0;
dcf46b94 5728
086c9855
AS		 5729 if (__this_cpu_read(current_vcpu))
5730 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5731
ff9d07a0
ZY		 5732 return ip;
5733}
5734
5735static struct perf_guest_info_callbacks kvm_guest_cbs = {
5736 .is_in_guest = kvm_is_in_guest,
5737 .is_user_mode = kvm_is_user_mode,
5738 .get_guest_ip = kvm_get_guest_ip,
5739};
5740
5741void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5742{
086c9855 5743 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5744}
5745EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5746
5747void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5748{
086c9855 5749 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5750}
5751EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5752
ce88decf
XG		 5753static void kvm_set_mmio_spte_mask(void)
5754{
5755 u64 mask;
5756 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5757
5758 /*
5759 * Set the reserved bits and the present bit of an paging-structure
5760 * entry to generate page fault with PFER.RSV = 1.
5761 */
885032b9 5762 /* Mask the reserved physical address bits. */
d1431483 5763 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5764
5765 /* Bit 62 is always reserved for 32bit host. */
5766 mask |= 0x3ull << 62;
5767
5768 /* Set the present bit. */
ce88decf
XG		 5769 mask |= 1ull;
5770
5771#ifdef CONFIG_X86_64
5772 /*
5773 * If reserved bit is not supported, clear the present bit to disable
5774 * mmio page fault.
5775 */
5776 if (maxphyaddr == 52)
5777 mask &= ~1ull;
5778#endif
5779
5780 kvm_mmu_set_mmio_spte_mask(mask);
5781}
5782
16e8d74d
MT		 5783#ifdef CONFIG_X86_64
5784static void pvclock_gtod_update_fn(struct work_struct *work)
5785{
d828199e
MT		 5786 struct kvm *kvm;
5787
5788 struct kvm_vcpu *vcpu;
5789 int i;
5790
2f303b74 5791 spin_lock(&kvm_lock);
d828199e
MT		 5792 list_for_each_entry(kvm, &vm_list, vm_list)
5793 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5794 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5795 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5796 spin_unlock(&kvm_lock);
16e8d74d
MT		 5797}
5798
5799static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5800
5801/*
5802 * Notification about pvclock gtod data update.
5803 */
5804static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5805 void *priv)
5806{
5807 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5808 struct timekeeper *tk = priv;
5809
5810 update_pvclock_gtod(tk);
5811
5812 /* disable master clock if host does not trust, or does not
5813 * use, TSC clocksource
5814 */
5815 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5816 atomic_read(&kvm_guest_has_master_clock) != 0)
5817 queue_work(system_long_wq, &pvclock_gtod_work);
5818
5819 return 0;
5820}
5821
5822static struct notifier_block pvclock_gtod_notifier = {
5823 .notifier_call = pvclock_gtod_notify,
5824};
5825#endif
5826
f8c16bba 5827int kvm_arch_init(void *opaque)
043405e1 5828{
b820cc0c 5829 int r;
6b61edf7 5830 struct kvm_x86_ops *ops = opaque;
f8c16bba 5831
f8c16bba
ZX		 5832 if (kvm_x86_ops) {
5833 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5834 r = -EEXIST;
5835 goto out;
f8c16bba
ZX		 5836 }
5837
5838 if (!ops->cpu_has_kvm_support()) {
5839 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5840 r = -EOPNOTSUPP;
5841 goto out;
f8c16bba
ZX		 5842 }
5843 if (ops->disabled_by_bios()) {
5844 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5845 r = -EOPNOTSUPP;
5846 goto out;
f8c16bba
ZX		 5847 }
5848
013f6a5d
MT		 5849 r = -ENOMEM;
5850 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5851 if (!shared_msrs) {
5852 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5853 goto out;
5854 }
5855
97db56ce
AK		 5856 r = kvm_mmu_module_init();
5857 if (r)
013f6a5d 5858 goto out_free_percpu;
97db56ce 5859
ce88decf 5860 kvm_set_mmio_spte_mask();
97db56ce 5861
f8c16bba 5862 kvm_x86_ops = ops;
920c8377 5863
7b52345e 5864 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5865 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5866
b820cc0c 5867 kvm_timer_init();
c8076604 5868
ff9d07a0
ZY		 5869 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5870
2acf923e
DC		 5871 if (cpu_has_xsave)
5872 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5873
c5cc421b 5874 kvm_lapic_init();
16e8d74d
MT		 5875#ifdef CONFIG_X86_64
5876 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5877#endif
5878
f8c16bba 5879 return 0;
56c6d28a 5880
013f6a5d
MT		 5881out_free_percpu:
5882 free_percpu(shared_msrs);
56c6d28a 5883out:
56c6d28a 5884 return r;
043405e1 5885}
8776e519 5886
f8c16bba
ZX		 5887void kvm_arch_exit(void)
5888{
ff9d07a0
ZY		 5889 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5890
888d256e
JK		 5891 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5892 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5893 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5894 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5895#ifdef CONFIG_X86_64
5896 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5897#endif
f8c16bba 5898 kvm_x86_ops = NULL;
56c6d28a 5899 kvm_mmu_module_exit();
013f6a5d 5900 free_percpu(shared_msrs);
56c6d28a 5901}
f8c16bba 5902
5cb56059 5903int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5904{
5905 ++vcpu->stat.halt_exits;
35754c98 5906 if (lapic_in_kernel(vcpu)) {
a4535290 5907 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5908 return 1;
5909 } else {
5910 vcpu->run->exit_reason = KVM_EXIT_HLT;
5911 return 0;
5912 }
5913}
5cb56059
JS		 5914EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5915
5916int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5917{
5918 kvm_x86_ops->skip_emulated_instruction(vcpu);
5919 return kvm_vcpu_halt(vcpu);
5920}
8776e519
HB		 5921EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5922
6aef266c
SV		 5923/*
5924 * kvm_pv_kick_cpu_op: Kick a vcpu.
5925 *
5926 * @apicid - apicid of vcpu to be kicked.
5927 */
5928static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5929{
24d2166b 5930 struct kvm_lapic_irq lapic_irq;
6aef266c 5931
24d2166b
R		 5932 lapic_irq.shorthand = 0;
5933 lapic_irq.dest_mode = 0;
5934 lapic_irq.dest_id = apicid;
93bbf0b8 5935 lapic_irq.msi_redir_hint = false;
6aef266c 5936
24d2166b 5937 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5938 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5939}
5940
d62caabb
AS		 5941void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5942{
5943 vcpu->arch.apicv_active = false;
5944 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5945}
5946
8776e519
HB		 5947int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5948{
5949 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5950 int op_64_bit, r = 1;
8776e519 5951
5cb56059
JS		 5952 kvm_x86_ops->skip_emulated_instruction(vcpu);
5953
55cd8e5a
GN		 5954 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5955 return kvm_hv_hypercall(vcpu);
5956
5fdbf976
MT		 5957 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5958 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5959 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5960 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5961 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5962
229456fc 5963 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5964
a449c7aa
NA		 5965 op_64_bit = is_64_bit_mode(vcpu);
5966 if (!op_64_bit) {
8776e519
HB		 5967 nr &= 0xFFFFFFFF;
5968 a0 &= 0xFFFFFFFF;
5969 a1 &= 0xFFFFFFFF;
5970 a2 &= 0xFFFFFFFF;
5971 a3 &= 0xFFFFFFFF;
5972 }
5973
07708c4a
JK		 5974 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5975 ret = -KVM_EPERM;
5976 goto out;
5977 }
5978
8776e519 5979 switch (nr) {
b93463aa
AK		 5980 case KVM_HC_VAPIC_POLL_IRQ:
5981 ret = 0;
5982 break;
6aef266c
SV		 5983 case KVM_HC_KICK_CPU:
5984 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5985 ret = 0;
5986 break;
8776e519
HB		 5987 default:
5988 ret = -KVM_ENOSYS;
5989 break;
5990 }
07708c4a 5991out:
a449c7aa
NA		 5992 if (!op_64_bit)
5993 ret = (u32)ret;
5fdbf976 5994 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5995 ++vcpu->stat.hypercalls;
2f333bcb 5996 return r;
8776e519
HB		 5997}
5998EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5999
b6785def 6000static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6001{
d6aa1000 6002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6003 char instruction[3];
5fdbf976 6004 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6005
8776e519 6006 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6007
9d74191a 6008 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6009}
6010
851ba692 6011static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6012{
782d422b
MG		 6013 return vcpu->run->request_interrupt_window &&
6014 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6015}
6016
851ba692 6017static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6018{
851ba692
AK		 6019 struct kvm_run *kvm_run = vcpu->run;
6020
91586a3b 6021 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6022 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6023 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6024 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6025 kvm_run->ready_for_interrupt_injection =
6026 pic_in_kernel(vcpu->kvm) ||
782d422b 6027 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6028}
6029
95ba8273
GN		 6030static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6031{
6032 int max_irr, tpr;
6033
6034 if (!kvm_x86_ops->update_cr8_intercept)
6035 return;
6036
bce87cce 6037 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6038 return;
6039
d62caabb
AS		 6040 if (vcpu->arch.apicv_active)
6041 return;
6042
8db3baa2
GN		 6043 if (!vcpu->arch.apic->vapic_addr)
6044 max_irr = kvm_lapic_find_highest_irr(vcpu);
6045 else
6046 max_irr = -1;
95ba8273
GN		 6047
6048 if (max_irr != -1)
6049 max_irr >>= 4;
6050
6051 tpr = kvm_lapic_get_cr8(vcpu);
6052
6053 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6054}
6055
b6b8a145 6056static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6057{
b6b8a145
JK		 6058 int r;
6059
95ba8273 6060 /* try to reinject previous events if any */
b59bb7bd 6061 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6062 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6063 vcpu->arch.exception.has_error_code,
6064 vcpu->arch.exception.error_code);
d6e8c854
NA		 6065
6066 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6067 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6068 X86_EFLAGS_RF);
6069
6bdf0662
NA		 6070 if (vcpu->arch.exception.nr == DB_VECTOR &&
6071 (vcpu->arch.dr7 & DR7_GD)) {
6072 vcpu->arch.dr7 &= ~DR7_GD;
6073 kvm_update_dr7(vcpu);
6074 }
6075
b59bb7bd
GN		 6076 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6077 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6078 vcpu->arch.exception.error_code,
6079 vcpu->arch.exception.reinject);
b6b8a145 6080 return 0;
b59bb7bd
GN		 6081 }
6082
95ba8273
GN		 6083 if (vcpu->arch.nmi_injected) {
6084 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6085 return 0;
95ba8273
GN		 6086 }
6087
6088 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6089 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6090 return 0;
6091 }
6092
6093 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6094 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6095 if (r != 0)
6096 return r;
95ba8273
GN		 6097 }
6098
6099 /* try to inject new event if pending */
321c5658
YS		 6100 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6101 --vcpu->arch.nmi_pending;
6102 vcpu->arch.nmi_injected = true;
6103 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6104 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6105 /*
6106 * Because interrupts can be injected asynchronously, we are
6107 * calling check_nested_events again here to avoid a race condition.
6108 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6109 * proposal and current concerns. Perhaps we should be setting
6110 * KVM_REQ_EVENT only on certain events and not unconditionally?
6111 */
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6114 if (r != 0)
6115 return r;
6116 }
95ba8273 6117 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6118 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6119 false);
6120 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6121 }
6122 }
b6b8a145 6123 return 0;
95ba8273
GN		 6124}
6125
7460fb4a
AK		 6126static void process_nmi(struct kvm_vcpu *vcpu)
6127{
6128 unsigned limit = 2;
6129
6130 /*
6131 * x86 is limited to one NMI running, and one NMI pending after it.
6132 * If an NMI is already in progress, limit further NMIs to just one.
6133 * Otherwise, allow two (and we'll inject the first one immediately).
6134 */
6135 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6136 limit = 1;
6137
6138 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6139 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6141}
6142
660a5d51
PB		 6143#define put_smstate(type, buf, offset, val) \
6144 *(type *)((buf) + (offset) - 0x7e00) = val
6145
6146static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6147{
6148 u32 flags = 0;
6149 flags |= seg->g << 23;
6150 flags |= seg->db << 22;
6151 flags |= seg->l << 21;
6152 flags |= seg->avl << 20;
6153 flags |= seg->present << 15;
6154 flags |= seg->dpl << 13;
6155 flags |= seg->s << 12;
6156 flags |= seg->type << 8;
6157 return flags;
6158}
6159
6160static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6161{
6162 struct kvm_segment seg;
6163 int offset;
6164
6165 kvm_get_segment(vcpu, &seg, n);
6166 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6167
6168 if (n < 3)
6169 offset = 0x7f84 + n * 12;
6170 else
6171 offset = 0x7f2c + (n - 3) * 12;
6172
6173 put_smstate(u32, buf, offset + 8, seg.base);
6174 put_smstate(u32, buf, offset + 4, seg.limit);
6175 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6176}
6177
efbb288a 6178#ifdef CONFIG_X86_64
660a5d51
PB		 6179static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6180{
6181 struct kvm_segment seg;
6182 int offset;
6183 u16 flags;
6184
6185 kvm_get_segment(vcpu, &seg, n);
6186 offset = 0x7e00 + n * 16;
6187
6188 flags = process_smi_get_segment_flags(&seg) >> 8;
6189 put_smstate(u16, buf, offset, seg.selector);
6190 put_smstate(u16, buf, offset + 2, flags);
6191 put_smstate(u32, buf, offset + 4, seg.limit);
6192 put_smstate(u64, buf, offset + 8, seg.base);
6193}
efbb288a 6194#endif
660a5d51
PB		 6195
6196static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6197{
6198 struct desc_ptr dt;
6199 struct kvm_segment seg;
6200 unsigned long val;
6201 int i;
6202
6203 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6204 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6205 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6206 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6207
6208 for (i = 0; i < 8; i++)
6209 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6210
6211 kvm_get_dr(vcpu, 6, &val);
6212 put_smstate(u32, buf, 0x7fcc, (u32)val);
6213 kvm_get_dr(vcpu, 7, &val);
6214 put_smstate(u32, buf, 0x7fc8, (u32)val);
6215
6216 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6217 put_smstate(u32, buf, 0x7fc4, seg.selector);
6218 put_smstate(u32, buf, 0x7f64, seg.base);
6219 put_smstate(u32, buf, 0x7f60, seg.limit);
6220 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6221
6222 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6223 put_smstate(u32, buf, 0x7fc0, seg.selector);
6224 put_smstate(u32, buf, 0x7f80, seg.base);
6225 put_smstate(u32, buf, 0x7f7c, seg.limit);
6226 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6227
6228 kvm_x86_ops->get_gdt(vcpu, &dt);
6229 put_smstate(u32, buf, 0x7f74, dt.address);
6230 put_smstate(u32, buf, 0x7f70, dt.size);
6231
6232 kvm_x86_ops->get_idt(vcpu, &dt);
6233 put_smstate(u32, buf, 0x7f58, dt.address);
6234 put_smstate(u32, buf, 0x7f54, dt.size);
6235
6236 for (i = 0; i < 6; i++)
6237 process_smi_save_seg_32(vcpu, buf, i);
6238
6239 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6240
6241 /* revision id */
6242 put_smstate(u32, buf, 0x7efc, 0x00020000);
6243 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6244}
6245
6246static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6247{
6248#ifdef CONFIG_X86_64
6249 struct desc_ptr dt;
6250 struct kvm_segment seg;
6251 unsigned long val;
6252 int i;
6253
6254 for (i = 0; i < 16; i++)
6255 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6256
6257 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6258 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6259
6260 kvm_get_dr(vcpu, 6, &val);
6261 put_smstate(u64, buf, 0x7f68, val);
6262 kvm_get_dr(vcpu, 7, &val);
6263 put_smstate(u64, buf, 0x7f60, val);
6264
6265 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6266 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6267 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6268
6269 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6270
6271 /* revision id */
6272 put_smstate(u32, buf, 0x7efc, 0x00020064);
6273
6274 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6275
6276 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6277 put_smstate(u16, buf, 0x7e90, seg.selector);
6278 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6279 put_smstate(u32, buf, 0x7e94, seg.limit);
6280 put_smstate(u64, buf, 0x7e98, seg.base);
6281
6282 kvm_x86_ops->get_idt(vcpu, &dt);
6283 put_smstate(u32, buf, 0x7e84, dt.size);
6284 put_smstate(u64, buf, 0x7e88, dt.address);
6285
6286 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6287 put_smstate(u16, buf, 0x7e70, seg.selector);
6288 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6289 put_smstate(u32, buf, 0x7e74, seg.limit);
6290 put_smstate(u64, buf, 0x7e78, seg.base);
6291
6292 kvm_x86_ops->get_gdt(vcpu, &dt);
6293 put_smstate(u32, buf, 0x7e64, dt.size);
6294 put_smstate(u64, buf, 0x7e68, dt.address);
6295
6296 for (i = 0; i < 6; i++)
6297 process_smi_save_seg_64(vcpu, buf, i);
6298#else
6299 WARN_ON_ONCE(1);
6300#endif
6301}
6302
64d60670
PB		 6303static void process_smi(struct kvm_vcpu *vcpu)
6304{
660a5d51 6305 struct kvm_segment cs, ds;
18c3626e 6306 struct desc_ptr dt;
660a5d51
PB		 6307 char buf[512];
6308 u32 cr0;
6309
64d60670
PB		 6310 if (is_smm(vcpu)) {
6311 vcpu->arch.smi_pending = true;
6312 return;
6313 }
6314
660a5d51
PB		 6315 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6316 vcpu->arch.hflags |= HF_SMM_MASK;
6317 memset(buf, 0, 512);
6318 if (guest_cpuid_has_longmode(vcpu))
6319 process_smi_save_state_64(vcpu, buf);
6320 else
6321 process_smi_save_state_32(vcpu, buf);
6322
54bf36aa 6323 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6324
6325 if (kvm_x86_ops->get_nmi_mask(vcpu))
6326 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6327 else
6328 kvm_x86_ops->set_nmi_mask(vcpu, true);
6329
6330 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6331 kvm_rip_write(vcpu, 0x8000);
6332
6333 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6334 kvm_x86_ops->set_cr0(vcpu, cr0);
6335 vcpu->arch.cr0 = cr0;
6336
6337 kvm_x86_ops->set_cr4(vcpu, 0);
6338
18c3626e
PB		 6339 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6340 dt.address = dt.size = 0;
6341 kvm_x86_ops->set_idt(vcpu, &dt);
6342
660a5d51
PB		 6343 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6344
6345 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6346 cs.base = vcpu->arch.smbase;
6347
6348 ds.selector = 0;
6349 ds.base = 0;
6350
6351 cs.limit = ds.limit = 0xffffffff;
6352 cs.type = ds.type = 0x3;
6353 cs.dpl = ds.dpl = 0;
6354 cs.db = ds.db = 0;
6355 cs.s = ds.s = 1;
6356 cs.l = ds.l = 0;
6357 cs.g = ds.g = 1;
6358 cs.avl = ds.avl = 0;
6359 cs.present = ds.present = 1;
6360 cs.unusable = ds.unusable = 0;
6361 cs.padding = ds.padding = 0;
6362
6363 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6369
6370 if (guest_cpuid_has_longmode(vcpu))
6371 kvm_x86_ops->set_efer(vcpu, 0);
6372
6373 kvm_update_cpuid(vcpu);
6374 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6375}
6376
2860c4b1
PB		 6377void kvm_make_scan_ioapic_request(struct kvm *kvm)
6378{
6379 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6380}
6381
3d81bc7e 6382static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6383{
5c919412
AS		 6384 u64 eoi_exit_bitmap[4];
6385
3d81bc7e
YZ		 6386 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6387 return;
c7c9c56c 6388
6308630b 6389 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6390
b053b2ae 6391 if (irqchip_split(vcpu->kvm))
6308630b 6392 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6393 else {
d62caabb
AS		 6394 if (vcpu->arch.apicv_active)
6395 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6396 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6397 }
5c919412
AS		 6398 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6399 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6400 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6401}
6402
a70656b6
RK		 6403static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6404{
6405 ++vcpu->stat.tlb_flush;
6406 kvm_x86_ops->tlb_flush(vcpu);
6407}
6408
4256f43f
TC		 6409void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6410{
c24ae0dc
TC		 6411 struct page *page = NULL;
6412
35754c98 6413 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6414 return;
6415
4256f43f
TC		 6416 if (!kvm_x86_ops->set_apic_access_page_addr)
6417 return;
6418
c24ae0dc 6419 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6420 if (is_error_page(page))
6421 return;
c24ae0dc
TC		 6422 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6423
6424 /*
6425 * Do not pin apic access page in memory, the MMU notifier
6426 * will call us again if it is migrated or swapped out.
6427 */
6428 put_page(page);
4256f43f
TC		 6429}
6430EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6431
fe71557a
TC		 6432void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6433 unsigned long address)
6434{
c24ae0dc
TC		 6435 /*
6436 * The physical address of apic access page is stored in the VMCS.
6437 * Update it when it becomes invalid.
6438 */
6439 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6440 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6441}
6442
9357d939 6443/*
362c698f 6444 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6445 * exiting to the userspace. Otherwise, the value will be returned to the
6446 * userspace.
6447 */
851ba692 6448static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6449{
6450 int r;
62a193ed
MG		 6451 bool req_int_win =
6452 dm_request_for_irq_injection(vcpu) &&
6453 kvm_cpu_accept_dm_intr(vcpu);
6454
730dca42 6455 bool req_immediate_exit = false;
b6c7a5dc 6456
3e007509 6457 if (vcpu->requests) {
a8eeb04a 6458 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6459 kvm_mmu_unload(vcpu);
a8eeb04a 6460 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6461 __kvm_migrate_timers(vcpu);
d828199e
MT		 6462 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6463 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6464 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6465 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6466 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6467 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6468 if (unlikely(r))
6469 goto out;
6470 }
a8eeb04a 6471 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6472 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6473 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6474 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6475 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6476 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6477 r = 0;
6478 goto out;
6479 }
a8eeb04a 6480 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6481 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6482 r = 0;
6483 goto out;
6484 }
a8eeb04a 6485 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6486 vcpu->fpu_active = 0;
6487 kvm_x86_ops->fpu_deactivate(vcpu);
6488 }
af585b92
GN		 6489 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6490 /* Page is swapped out. Do synthetic halt */
6491 vcpu->arch.apf.halted = true;
6492 r = 1;
6493 goto out;
6494 }
c9aaa895
GC		 6495 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6496 record_steal_time(vcpu);
64d60670
PB		 6497 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6498 process_smi(vcpu);
7460fb4a
AK		 6499 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6500 process_nmi(vcpu);
f5132b01 6501 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6502 kvm_pmu_handle_event(vcpu);
f5132b01 6503 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6504 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6505 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6506 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6507 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6508 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6509 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6510 vcpu->run->eoi.vector =
6511 vcpu->arch.pending_ioapic_eoi;
6512 r = 0;
6513 goto out;
6514 }
6515 }
3d81bc7e
YZ		 6516 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6517 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6518 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6519 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6520 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6521 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6522 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6523 r = 0;
6524 goto out;
6525 }
e516cebb
AS		 6526 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6527 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6528 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6529 r = 0;
6530 goto out;
6531 }
db397571
AS		 6532 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6534 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6535 r = 0;
6536 goto out;
6537 }
f3b138c5
AS		 6538
6539 /*
6540 * KVM_REQ_HV_STIMER has to be processed after
6541 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6542 * depend on the guest clock being up-to-date
6543 */
1f4b34f8
AS		 6544 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6545 kvm_hv_process_stimers(vcpu);
2f52d58c 6546 }
b93463aa 6547
bf9f6ac8
FW		 6548 /*
6549 * KVM_REQ_EVENT is not set when posted interrupts are set by
6550 * VT-d hardware, so we have to update RVI unconditionally.
6551 */
6552 if (kvm_lapic_enabled(vcpu)) {
6553 /*
6554 * Update architecture specific hints for APIC
6555 * virtual interrupt delivery.
6556 */
d62caabb 6557 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6558 kvm_x86_ops->hwapic_irr_update(vcpu,
6559 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6560 }
b93463aa 6561
b463a6f7 6562 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6563 kvm_apic_accept_events(vcpu);
6564 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6565 r = 1;
6566 goto out;
6567 }
6568
b6b8a145
JK		 6569 if (inject_pending_event(vcpu, req_int_win) != 0)
6570 req_immediate_exit = true;
b463a6f7 6571 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6572 else {
6573 if (vcpu->arch.nmi_pending)
6574 kvm_x86_ops->enable_nmi_window(vcpu);
6575 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6576 kvm_x86_ops->enable_irq_window(vcpu);
6577 }
b463a6f7
AK		 6578
6579 if (kvm_lapic_enabled(vcpu)) {
6580 update_cr8_intercept(vcpu);
6581 kvm_lapic_sync_to_vapic(vcpu);
6582 }
6583 }
6584
d8368af8
AK		 6585 r = kvm_mmu_reload(vcpu);
6586 if (unlikely(r)) {
d905c069 6587 goto cancel_injection;
d8368af8
AK		 6588 }
6589
b6c7a5dc
HB		 6590 preempt_disable();
6591
6592 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6593 if (vcpu->fpu_active)
6594 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6595 vcpu->mode = IN_GUEST_MODE;
6596
01b71917
MT		 6597 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6598
0f127d12
LT		 6599 /*
6600 * We should set ->mode before check ->requests,
6601 * Please see the comment in kvm_make_all_cpus_request.
6602 * This also orders the write to mode from any reads
6603 * to the page tables done while the VCPU is running.
6604 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6605 */
01b71917 6606 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6607
d94e1dc9 6608 local_irq_disable();
32f88400 6609
6b7e2d09 6610 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6611 || need_resched() || signal_pending(current)) {
6b7e2d09 6612 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6613 smp_wmb();
6c142801
AK		 6614 local_irq_enable();
6615 preempt_enable();
01b71917 6616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6617 r = 1;
d905c069 6618 goto cancel_injection;
6c142801
AK		 6619 }
6620
fc5b7f3b
DM		 6621 kvm_load_guest_xcr0(vcpu);
6622
d6185f20
NHE		 6623 if (req_immediate_exit)
6624 smp_send_reschedule(vcpu->cpu);
6625
8b89fe1f
PB		 6626 trace_kvm_entry(vcpu->vcpu_id);
6627 wait_lapic_expire(vcpu);
ccf73aaf 6628 __kvm_guest_enter();
b6c7a5dc 6629
42dbaa5a 6630 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6631 set_debugreg(0, 7);
6632 set_debugreg(vcpu->arch.eff_db[0], 0);
6633 set_debugreg(vcpu->arch.eff_db[1], 1);
6634 set_debugreg(vcpu->arch.eff_db[2], 2);
6635 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6636 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6637 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6638 }
b6c7a5dc 6639
851ba692 6640 kvm_x86_ops->run(vcpu);
b6c7a5dc 6641
c77fb5fe
PB		 6642 /*
6643 * Do this here before restoring debug registers on the host. And
6644 * since we do this before handling the vmexit, a DR access vmexit
6645 * can (a) read the correct value of the debug registers, (b) set
6646 * KVM_DEBUGREG_WONT_EXIT again.
6647 */
6648 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6649 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6650 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6651 kvm_update_dr0123(vcpu);
6652 kvm_update_dr6(vcpu);
6653 kvm_update_dr7(vcpu);
6654 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6655 }
6656
24f1e32c
FW		 6657 /*
6658 * If the guest has used debug registers, at least dr7
6659 * will be disabled while returning to the host.
6660 * If we don't have active breakpoints in the host, we don't
6661 * care about the messed up debug address registers. But if
6662 * we have some of them active, restore the old state.
6663 */
59d8eb53 6664 if (hw_breakpoint_active())
24f1e32c 6665 hw_breakpoint_restore();
42dbaa5a 6666
4ba76538 6667 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6668
6b7e2d09 6669 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6670 smp_wmb();
a547c6db 6671
fc5b7f3b
DM		 6672 kvm_put_guest_xcr0(vcpu);
6673
a547c6db
YZ		 6674 /* Interrupt is enabled by handle_external_intr() */
6675 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6676
6677 ++vcpu->stat.exits;
6678
6679 /*
6680 * We must have an instruction between local_irq_enable() and
6681 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6682 * the interrupt shadow. The stat.exits increment will do nicely.
6683 * But we need to prevent reordering, hence this barrier():
6684 */
6685 barrier();
6686
6687 kvm_guest_exit();
6688
6689 preempt_enable();
6690
f656ce01 6691 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6692
b6c7a5dc
HB		 6693 /*
6694 * Profile KVM exit RIPs:
6695 */
6696 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6697 unsigned long rip = kvm_rip_read(vcpu);
6698 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6699 }
6700
cc578287
ZA		 6701 if (unlikely(vcpu->arch.tsc_always_catchup))
6702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6703
5cfb1d5a
MT		 6704 if (vcpu->arch.apic_attention)
6705 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6706
851ba692 6707 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6708 return r;
6709
6710cancel_injection:
6711 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6712 if (unlikely(vcpu->arch.apic_attention))
6713 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6714out:
6715 return r;
6716}
b6c7a5dc 6717
362c698f
PB		 6718static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6719{
bf9f6ac8
FW		 6720 if (!kvm_arch_vcpu_runnable(vcpu) &&
6721 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6722 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6723 kvm_vcpu_block(vcpu);
6724 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6725
6726 if (kvm_x86_ops->post_block)
6727 kvm_x86_ops->post_block(vcpu);
6728
9c8fd1ba
PB		 6729 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6730 return 1;
6731 }
362c698f
PB		 6732
6733 kvm_apic_accept_events(vcpu);
6734 switch(vcpu->arch.mp_state) {
6735 case KVM_MP_STATE_HALTED:
6736 vcpu->arch.pv.pv_unhalted = false;
6737 vcpu->arch.mp_state =
6738 KVM_MP_STATE_RUNNABLE;
6739 case KVM_MP_STATE_RUNNABLE:
6740 vcpu->arch.apf.halted = false;
6741 break;
6742 case KVM_MP_STATE_INIT_RECEIVED:
6743 break;
6744 default:
6745 return -EINTR;
6746 break;
6747 }
6748 return 1;
6749}
09cec754 6750
5d9bc648
PB		 6751static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6752{
6753 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6754 !vcpu->arch.apf.halted);
6755}
6756
362c698f 6757static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6758{
6759 int r;
f656ce01 6760 struct kvm *kvm = vcpu->kvm;
d7690175 6761
f656ce01 6762 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6763
362c698f 6764 for (;;) {
58f800d5 6765 if (kvm_vcpu_running(vcpu)) {
851ba692 6766 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6767 } else {
362c698f 6768 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6769 }
6770
09cec754
GN		 6771 if (r <= 0)
6772 break;
6773
6774 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6775 if (kvm_cpu_has_pending_timer(vcpu))
6776 kvm_inject_pending_timer_irqs(vcpu);
6777
782d422b
MG		 6778 if (dm_request_for_irq_injection(vcpu) &&
6779 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6780 r = 0;
6781 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6782 ++vcpu->stat.request_irq_exits;
362c698f 6783 break;
09cec754 6784 }
af585b92
GN		 6785
6786 kvm_check_async_pf_completion(vcpu);
6787
09cec754
GN		 6788 if (signal_pending(current)) {
6789 r = -EINTR;
851ba692 6790 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6791 ++vcpu->stat.signal_exits;
362c698f 6792 break;
09cec754
GN		 6793 }
6794 if (need_resched()) {
f656ce01 6795 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6796 cond_resched();
f656ce01 6797 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6798 }
b6c7a5dc
HB		 6799 }
6800
f656ce01 6801 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6802
6803 return r;
6804}
6805
716d51ab
GN		 6806static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6807{
6808 int r;
6809 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6810 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6811 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6812 if (r != EMULATE_DONE)
6813 return 0;
6814 return 1;
6815}
6816
6817static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6818{
6819 BUG_ON(!vcpu->arch.pio.count);
6820
6821 return complete_emulated_io(vcpu);
6822}
6823
f78146b0
AK		 6824/*
6825 * Implements the following, as a state machine:
6826 *
6827 * read:
6828 * for each fragment
87da7e66
XG		 6829 * for each mmio piece in the fragment
6830 * write gpa, len
6831 * exit
6832 * copy data
f78146b0
AK		 6833 * execute insn
6834 *
6835 * write:
6836 * for each fragment
87da7e66
XG		 6837 * for each mmio piece in the fragment
6838 * write gpa, len
6839 * copy data
6840 * exit
f78146b0 6841 */
716d51ab 6842static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6843{
6844 struct kvm_run *run = vcpu->run;
f78146b0 6845 struct kvm_mmio_fragment *frag;
87da7e66 6846 unsigned len;
5287f194 6847
716d51ab 6848 BUG_ON(!vcpu->mmio_needed);
5287f194 6849
716d51ab 6850 /* Complete previous fragment */
87da7e66
XG		 6851 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6852 len = min(8u, frag->len);
716d51ab 6853 if (!vcpu->mmio_is_write)
87da7e66
XG		 6854 memcpy(frag->data, run->mmio.data, len);
6855
6856 if (frag->len <= 8) {
6857 /* Switch to the next fragment. */
6858 frag++;
6859 vcpu->mmio_cur_fragment++;
6860 } else {
6861 /* Go forward to the next mmio piece. */
6862 frag->data += len;
6863 frag->gpa += len;
6864 frag->len -= len;
6865 }
6866
a08d3b3b 6867 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6868 vcpu->mmio_needed = 0;
0912c977
PB		 6869
6870 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6871 if (vcpu->mmio_is_write)
716d51ab
GN		 6872 return 1;
6873 vcpu->mmio_read_completed = 1;
6874 return complete_emulated_io(vcpu);
6875 }
87da7e66 6876
716d51ab
GN		 6877 run->exit_reason = KVM_EXIT_MMIO;
6878 run->mmio.phys_addr = frag->gpa;
6879 if (vcpu->mmio_is_write)
87da7e66
XG		 6880 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6881 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6882 run->mmio.is_write = vcpu->mmio_is_write;
6883 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6884 return 0;
5287f194
AK		 6885}
6886
716d51ab 6887
b6c7a5dc
HB		 6888int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6889{
c5bedc68 6890 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6891 int r;
6892 sigset_t sigsaved;
6893
c4d72e2d 6894 fpu__activate_curr(fpu);
e5c30142 6895
ac9f6dc0
AK		 6896 if (vcpu->sigset_active)
6897 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6898
a4535290 6899 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6900 kvm_vcpu_block(vcpu);
66450a21 6901 kvm_apic_accept_events(vcpu);
d7690175 6902 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6903 r = -EAGAIN;
6904 goto out;
b6c7a5dc
HB		 6905 }
6906
b6c7a5dc 6907 /* re-sync apic's tpr */
35754c98 6908 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6909 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6910 r = -EINVAL;
6911 goto out;
6912 }
6913 }
b6c7a5dc 6914
716d51ab
GN		 6915 if (unlikely(vcpu->arch.complete_userspace_io)) {
6916 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6917 vcpu->arch.complete_userspace_io = NULL;
6918 r = cui(vcpu);
6919 if (r <= 0)
6920 goto out;
6921 } else
6922 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6923
362c698f 6924 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6925
6926out:
f1d86e46 6927 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6928 if (vcpu->sigset_active)
6929 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6930
b6c7a5dc
HB		 6931 return r;
6932}
6933
6934int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6935{
7ae441ea
GN		 6936 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6937 /*
6938 * We are here if userspace calls get_regs() in the middle of
6939 * instruction emulation. Registers state needs to be copied
4a969980 6940 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6941 * that usually, but some bad designed PV devices (vmware
6942 * backdoor interface) need this to work
6943 */
dd856efa 6944 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6945 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6946 }
5fdbf976
MT		 6947 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6948 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6949 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6950 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6951 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6952 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6953 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6954 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6955#ifdef CONFIG_X86_64
5fdbf976
MT		 6956 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6957 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6958 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6959 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6960 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6961 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6962 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6963 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6964#endif
6965
5fdbf976 6966 regs->rip = kvm_rip_read(vcpu);
91586a3b 6967 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6968
b6c7a5dc
HB		 6969 return 0;
6970}
6971
6972int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6973{
7ae441ea
GN		 6974 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6975 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6976
5fdbf976
MT		 6977 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6978 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6979 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6980 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6981 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6982 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6983 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6984 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6985#ifdef CONFIG_X86_64
5fdbf976
MT		 6986 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6987 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6988 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6989 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6990 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6991 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6992 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6993 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6994#endif
6995
5fdbf976 6996 kvm_rip_write(vcpu, regs->rip);
91586a3b 6997 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6998
b4f14abd
JK		 6999 vcpu->arch.exception.pending = false;
7000
3842d135
AK		 7001 kvm_make_request(KVM_REQ_EVENT, vcpu);
7002
b6c7a5dc
HB		 7003 return 0;
7004}
7005
b6c7a5dc
HB		 7006void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7007{
7008 struct kvm_segment cs;
7009
3e6e0aab 7010 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7011 *db = cs.db;
7012 *l = cs.l;
7013}
7014EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7015
7016int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7017 struct kvm_sregs *sregs)
7018{
89a27f4d 7019 struct desc_ptr dt;
b6c7a5dc 7020
3e6e0aab
GT		 7021 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7022 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7023 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7024 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7025 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7026 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7027
3e6e0aab
GT		 7028 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7029 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7030
7031 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7032 sregs->idt.limit = dt.size;
7033 sregs->idt.base = dt.address;
b6c7a5dc 7034 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7035 sregs->gdt.limit = dt.size;
7036 sregs->gdt.base = dt.address;
b6c7a5dc 7037
4d4ec087 7038 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7039 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7040 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7041 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7042 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7043 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7044 sregs->apic_base = kvm_get_apic_base(vcpu);
7045
923c61bb 7046 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7047
36752c9b 7048 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7049 set_bit(vcpu->arch.interrupt.nr,
7050 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7051
b6c7a5dc
HB		 7052 return 0;
7053}
7054
62d9f0db
MT		 7055int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7056 struct kvm_mp_state *mp_state)
7057{
66450a21 7058 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7059 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7060 vcpu->arch.pv.pv_unhalted)
7061 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7062 else
7063 mp_state->mp_state = vcpu->arch.mp_state;
7064
62d9f0db
MT		 7065 return 0;
7066}
7067
7068int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7069 struct kvm_mp_state *mp_state)
7070{
bce87cce 7071 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7072 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7073 return -EINVAL;
7074
7075 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7076 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7077 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7078 } else
7079 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7080 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7081 return 0;
7082}
7083
7f3d35fd
KW		 7084int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7085 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7086{
9d74191a 7087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7088 int ret;
e01c2426 7089
8ec4722d 7090 init_emulate_ctxt(vcpu);
c697518a 7091
7f3d35fd 7092 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7093 has_error_code, error_code);
c697518a 7094
c697518a 7095 if (ret)
19d04437 7096 return EMULATE_FAIL;
37817f29 7097
9d74191a
TY		 7098 kvm_rip_write(vcpu, ctxt->eip);
7099 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7100 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7101 return EMULATE_DONE;
37817f29
IE		 7102}
7103EXPORT_SYMBOL_GPL(kvm_task_switch);
7104
b6c7a5dc
HB		 7105int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7106 struct kvm_sregs *sregs)
7107{
58cb628d 7108 struct msr_data apic_base_msr;
b6c7a5dc 7109 int mmu_reset_needed = 0;
63f42e02 7110 int pending_vec, max_bits, idx;
89a27f4d 7111 struct desc_ptr dt;
b6c7a5dc 7112
6d1068b3
PM		 7113 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7114 return -EINVAL;
7115
89a27f4d
GN		 7116 dt.size = sregs->idt.limit;
7117 dt.address = sregs->idt.base;
b6c7a5dc 7118 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7119 dt.size = sregs->gdt.limit;
7120 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7121 kvm_x86_ops->set_gdt(vcpu, &dt);
7122
ad312c7c 7123 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7124 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7125 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7126 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7127
2d3ad1f4 7128 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7129
f6801dff 7130 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7131 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7132 apic_base_msr.data = sregs->apic_base;
7133 apic_base_msr.host_initiated = true;
7134 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7135
4d4ec087 7136 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7137 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7138 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7139
fc78f519 7140 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7141 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7142 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7143 kvm_update_cpuid(vcpu);
63f42e02
XG		 7144
7145 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7146 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7147 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7148 mmu_reset_needed = 1;
7149 }
63f42e02 7150 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7151
7152 if (mmu_reset_needed)
7153 kvm_mmu_reset_context(vcpu);
7154
a50abc3b 7155 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7156 pending_vec = find_first_bit(
7157 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7158 if (pending_vec < max_bits) {
66fd3f7f 7159 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7160 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7161 }
7162
3e6e0aab
GT		 7163 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7164 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7165 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7166 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7167 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7168 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7169
3e6e0aab
GT		 7170 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7171 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7172
5f0269f5
ME		 7173 update_cr8_intercept(vcpu);
7174
9c3e4aab 7175 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7176 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7177 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7178 !is_protmode(vcpu))
9c3e4aab
MT		 7179 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7180
3842d135
AK		 7181 kvm_make_request(KVM_REQ_EVENT, vcpu);
7182
b6c7a5dc
HB		 7183 return 0;
7184}
7185
d0bfb940
JK		 7186int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7187 struct kvm_guest_debug *dbg)
b6c7a5dc 7188{
355be0b9 7189 unsigned long rflags;
ae675ef0 7190 int i, r;
b6c7a5dc 7191
4f926bf2
JK		 7192 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7193 r = -EBUSY;
7194 if (vcpu->arch.exception.pending)
2122ff5e 7195 goto out;
4f926bf2
JK		 7196 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7197 kvm_queue_exception(vcpu, DB_VECTOR);
7198 else
7199 kvm_queue_exception(vcpu, BP_VECTOR);
7200 }
7201
91586a3b
JK		 7202 /*
7203 * Read rflags as long as potentially injected trace flags are still
7204 * filtered out.
7205 */
7206 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7207
7208 vcpu->guest_debug = dbg->control;
7209 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7210 vcpu->guest_debug = 0;
7211
7212 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7213 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7214 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7215 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7216 } else {
7217 for (i = 0; i < KVM_NR_DB_REGS; i++)
7218 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7219 }
c8639010 7220 kvm_update_dr7(vcpu);
ae675ef0 7221
f92653ee
JK		 7222 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7223 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7224 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7225
91586a3b
JK		 7226 /*
7227 * Trigger an rflags update that will inject or remove the trace
7228 * flags.
7229 */
7230 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7231
a96036b8 7232 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7233
4f926bf2 7234 r = 0;
d0bfb940 7235
2122ff5e 7236out:
b6c7a5dc
HB		 7237
7238 return r;
7239}
7240
8b006791
ZX		 7241/*
7242 * Translate a guest virtual address to a guest physical address.
7243 */
7244int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7245 struct kvm_translation *tr)
7246{
7247 unsigned long vaddr = tr->linear_address;
7248 gpa_t gpa;
f656ce01 7249 int idx;
8b006791 7250
f656ce01 7251 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7252 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7253 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7254 tr->physical_address = gpa;
7255 tr->valid = gpa != UNMAPPED_GVA;
7256 tr->writeable = 1;
7257 tr->usermode = 0;
8b006791
ZX		 7258
7259 return 0;
7260}
7261
d0752060
HB		 7262int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7263{
c47ada30 7264 struct fxregs_state *fxsave =
7366ed77 7265 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7266
d0752060
HB		 7267 memcpy(fpu->fpr, fxsave->st_space, 128);
7268 fpu->fcw = fxsave->cwd;
7269 fpu->fsw = fxsave->swd;
7270 fpu->ftwx = fxsave->twd;
7271 fpu->last_opcode = fxsave->fop;
7272 fpu->last_ip = fxsave->rip;
7273 fpu->last_dp = fxsave->rdp;
7274 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7275
d0752060
HB		 7276 return 0;
7277}
7278
7279int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7280{
c47ada30 7281 struct fxregs_state *fxsave =
7366ed77 7282 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7283
d0752060
HB		 7284 memcpy(fxsave->st_space, fpu->fpr, 128);
7285 fxsave->cwd = fpu->fcw;
7286 fxsave->swd = fpu->fsw;
7287 fxsave->twd = fpu->ftwx;
7288 fxsave->fop = fpu->last_opcode;
7289 fxsave->rip = fpu->last_ip;
7290 fxsave->rdp = fpu->last_dp;
7291 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7292
d0752060
HB		 7293 return 0;
7294}
7295
0ee6a517 7296static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7297{
bf935b0b 7298 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7299 if (cpu_has_xsaves)
7366ed77 7300 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7301 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7302
2acf923e
DC		 7303 /*
7304 * Ensure guest xcr0 is valid for loading
7305 */
d91cab78 7306 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7307
ad312c7c 7308 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7309}
d0752060
HB		 7310
7311void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7312{
2608d7a1 7313 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7314 return;
7315
2acf923e
DC		 7316 /*
7317 * Restore all possible states in the guest,
7318 * and assume host would use all available bits.
7319 * Guest xcr0 would be loaded later.
7320 */
d0752060 7321 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7322 __kernel_fpu_begin();
003e2e8b 7323 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7324 trace_kvm_fpu(1);
d0752060 7325}
d0752060
HB		 7326
7327void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7328{
653f52c3
RR		 7329 if (!vcpu->guest_fpu_loaded) {
7330 vcpu->fpu_counter = 0;
d0752060 7331 return;
653f52c3 7332 }
d0752060
HB		 7333
7334 vcpu->guest_fpu_loaded = 0;
4f836347 7335 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7336 __kernel_fpu_end();
f096ed85 7337 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7338 /*
7339 * If using eager FPU mode, or if the guest is a frequent user
7340 * of the FPU, just leave the FPU active for next time.
7341 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7342 * the FPU in bursts will revert to loading it on demand.
7343 */
5a5fbdc0 7344 if (!use_eager_fpu()) {
653f52c3
RR		 7345 if (++vcpu->fpu_counter < 5)
7346 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7347 }
0c04851c 7348 trace_kvm_fpu(0);
d0752060 7349}
e9b11c17
ZX		 7350
7351void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7352{
12f9a48f 7353 kvmclock_reset(vcpu);
7f1ea208 7354
f5f48ee1 7355 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7356 kvm_x86_ops->vcpu_free(vcpu);
7357}
7358
7359struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7360 unsigned int id)
7361{
c447e76b
LL		 7362 struct kvm_vcpu *vcpu;
7363
6755bae8
ZA		 7364 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7365 printk_once(KERN_WARNING
7366 "kvm: SMP vm created on host with unstable TSC; "
7367 "guest TSC will not be reliable\n");
c447e76b
LL		 7368
7369 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7370
c447e76b 7371 return vcpu;
26e5215f 7372}
e9b11c17 7373
26e5215f
AK		 7374int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7375{
7376 int r;
e9b11c17 7377
19efffa2 7378 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7379 r = vcpu_load(vcpu);
7380 if (r)
7381 return r;
d28bc9dd 7382 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7383 kvm_mmu_setup(vcpu);
e9b11c17 7384 vcpu_put(vcpu);
26e5215f 7385 return r;
e9b11c17
ZX		 7386}
7387
31928aa5 7388void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7389{
8fe8ab46 7390 struct msr_data msr;
332967a3 7391 struct kvm *kvm = vcpu->kvm;
42897d86 7392
31928aa5
DD		 7393 if (vcpu_load(vcpu))
7394 return;
8fe8ab46
WA		 7395 msr.data = 0x0;
7396 msr.index = MSR_IA32_TSC;
7397 msr.host_initiated = true;
7398 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7399 vcpu_put(vcpu);
7400
630994b3
MT		 7401 if (!kvmclock_periodic_sync)
7402 return;
7403
332967a3
AJ		 7404 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7405 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7406}
7407
d40ccc62 7408void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7409{
9fc77441 7410 int r;
344d9588
GN		 7411 vcpu->arch.apf.msr_val = 0;
7412
9fc77441
MT		 7413 r = vcpu_load(vcpu);
7414 BUG_ON(r);
e9b11c17
ZX		 7415 kvm_mmu_unload(vcpu);
7416 vcpu_put(vcpu);
7417
7418 kvm_x86_ops->vcpu_free(vcpu);
7419}
7420
d28bc9dd 7421void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7422{
e69fab5d
PB		 7423 vcpu->arch.hflags = 0;
7424
7460fb4a
AK		 7425 atomic_set(&vcpu->arch.nmi_queued, 0);
7426 vcpu->arch.nmi_pending = 0;
448fa4a9 7427 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7428 kvm_clear_interrupt_queue(vcpu);
7429 kvm_clear_exception_queue(vcpu);
448fa4a9 7430
42dbaa5a 7431 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7432 kvm_update_dr0123(vcpu);
6f43ed01 7433 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7434 kvm_update_dr6(vcpu);
42dbaa5a 7435 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7436 kvm_update_dr7(vcpu);
42dbaa5a 7437
1119022c
NA		 7438 vcpu->arch.cr2 = 0;
7439
3842d135 7440 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7441 vcpu->arch.apf.msr_val = 0;
c9aaa895 7442 vcpu->arch.st.msr_val = 0;
3842d135 7443
12f9a48f
GC		 7444 kvmclock_reset(vcpu);
7445
af585b92
GN		 7446 kvm_clear_async_pf_completion_queue(vcpu);
7447 kvm_async_pf_hash_reset(vcpu);
7448 vcpu->arch.apf.halted = false;
3842d135 7449
64d60670 7450 if (!init_event) {
d28bc9dd 7451 kvm_pmu_reset(vcpu);
64d60670
PB		 7452 vcpu->arch.smbase = 0x30000;
7453 }
f5132b01 7454
66f7b72e
JS		 7455 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7456 vcpu->arch.regs_avail = ~0;
7457 vcpu->arch.regs_dirty = ~0;
7458
d28bc9dd 7459 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7460}
7461
2b4a273b 7462void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7463{
7464 struct kvm_segment cs;
7465
7466 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7467 cs.selector = vector << 8;
7468 cs.base = vector << 12;
7469 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7470 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7471}
7472
13a34e06 7473int kvm_arch_hardware_enable(void)
e9b11c17 7474{
ca84d1a2
ZA		 7475 struct kvm *kvm;
7476 struct kvm_vcpu *vcpu;
7477 int i;
0dd6a6ed
ZA		 7478 int ret;
7479 u64 local_tsc;
7480 u64 max_tsc = 0;
7481 bool stable, backwards_tsc = false;
18863bdd
AK		 7482
7483 kvm_shared_msr_cpu_online();
13a34e06 7484 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7485 if (ret != 0)
7486 return ret;
7487
4ea1636b 7488 local_tsc = rdtsc();
0dd6a6ed
ZA		 7489 stable = !check_tsc_unstable();
7490 list_for_each_entry(kvm, &vm_list, vm_list) {
7491 kvm_for_each_vcpu(i, vcpu, kvm) {
7492 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7493 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7494 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7495 backwards_tsc = true;
7496 if (vcpu->arch.last_host_tsc > max_tsc)
7497 max_tsc = vcpu->arch.last_host_tsc;
7498 }
7499 }
7500 }
7501
7502 /*
7503 * Sometimes, even reliable TSCs go backwards. This happens on
7504 * platforms that reset TSC during suspend or hibernate actions, but
7505 * maintain synchronization. We must compensate. Fortunately, we can
7506 * detect that condition here, which happens early in CPU bringup,
7507 * before any KVM threads can be running. Unfortunately, we can't
7508 * bring the TSCs fully up to date with real time, as we aren't yet far
7509 * enough into CPU bringup that we know how much real time has actually
7510 * elapsed; our helper function, get_kernel_ns() will be using boot
7511 * variables that haven't been updated yet.
7512 *
7513 * So we simply find the maximum observed TSC above, then record the
7514 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7515 * the adjustment will be applied. Note that we accumulate
7516 * adjustments, in case multiple suspend cycles happen before some VCPU
7517 * gets a chance to run again. In the event that no KVM threads get a
7518 * chance to run, we will miss the entire elapsed period, as we'll have
7519 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7520 * loose cycle time. This isn't too big a deal, since the loss will be
7521 * uniform across all VCPUs (not to mention the scenario is extremely
7522 * unlikely). It is possible that a second hibernate recovery happens
7523 * much faster than a first, causing the observed TSC here to be
7524 * smaller; this would require additional padding adjustment, which is
7525 * why we set last_host_tsc to the local tsc observed here.
7526 *
7527 * N.B. - this code below runs only on platforms with reliable TSC,
7528 * as that is the only way backwards_tsc is set above. Also note
7529 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7530 * have the same delta_cyc adjustment applied if backwards_tsc
7531 * is detected. Note further, this adjustment is only done once,
7532 * as we reset last_host_tsc on all VCPUs to stop this from being
7533 * called multiple times (one for each physical CPU bringup).
7534 *
4a969980 7535 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7536 * will be compensated by the logic in vcpu_load, which sets the TSC to
7537 * catchup mode. This will catchup all VCPUs to real time, but cannot
7538 * guarantee that they stay in perfect synchronization.
7539 */
7540 if (backwards_tsc) {
7541 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7542 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7543 list_for_each_entry(kvm, &vm_list, vm_list) {
7544 kvm_for_each_vcpu(i, vcpu, kvm) {
7545 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7546 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7547 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7548 }
7549
7550 /*
7551 * We have to disable TSC offset matching.. if you were
7552 * booting a VM while issuing an S4 host suspend....
7553 * you may have some problem. Solving this issue is
7554 * left as an exercise to the reader.
7555 */
7556 kvm->arch.last_tsc_nsec = 0;
7557 kvm->arch.last_tsc_write = 0;
7558 }
7559
7560 }
7561 return 0;
e9b11c17
ZX		 7562}
7563
13a34e06 7564void kvm_arch_hardware_disable(void)
e9b11c17 7565{
13a34e06
RK		 7566 kvm_x86_ops->hardware_disable();
7567 drop_user_return_notifiers();
e9b11c17
ZX		 7568}
7569
7570int kvm_arch_hardware_setup(void)
7571{
9e9c3fe4
NA		 7572 int r;
7573
7574 r = kvm_x86_ops->hardware_setup();
7575 if (r != 0)
7576 return r;
7577
35181e86
HZ		 7578 if (kvm_has_tsc_control) {
7579 /*
7580 * Make sure the user can only configure tsc_khz values that
7581 * fit into a signed integer.
7582 * A min value is not calculated needed because it will always
7583 * be 1 on all machines.
7584 */
7585 u64 max = min(0x7fffffffULL,
7586 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7587 kvm_max_guest_tsc_khz = max;
7588
ad721883 7589 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7590 }
ad721883 7591
9e9c3fe4
NA		 7592 kvm_init_msr_list();
7593 return 0;
e9b11c17
ZX		 7594}
7595
7596void kvm_arch_hardware_unsetup(void)
7597{
7598 kvm_x86_ops->hardware_unsetup();
7599}
7600
7601void kvm_arch_check_processor_compat(void *rtn)
7602{
7603 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7604}
7605
7606bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7607{
7608 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7609}
7610EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7611
7612bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7613{
7614 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7615}
7616
3e515705
AK		 7617bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7618{
35754c98 7619 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7620}
7621
54e9818f 7622struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7623EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7624
e9b11c17
ZX		 7625int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7626{
7627 struct page *page;
7628 struct kvm *kvm;
7629 int r;
7630
7631 BUG_ON(vcpu->kvm == NULL);
7632 kvm = vcpu->kvm;
7633
d62caabb 7634 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7635 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7636 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7637 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7638 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7639 else
a4535290 7640 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7641
7642 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7643 if (!page) {
7644 r = -ENOMEM;
7645 goto fail;
7646 }
ad312c7c 7647 vcpu->arch.pio_data = page_address(page);
e9b11c17 7648
cc578287 7649 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7650
e9b11c17
ZX		 7651 r = kvm_mmu_create(vcpu);
7652 if (r < 0)
7653 goto fail_free_pio_data;
7654
7655 if (irqchip_in_kernel(kvm)) {
7656 r = kvm_create_lapic(vcpu);
7657 if (r < 0)
7658 goto fail_mmu_destroy;
54e9818f
GN		 7659 } else
7660 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7661
890ca9ae
HY		 7662 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7663 GFP_KERNEL);
7664 if (!vcpu->arch.mce_banks) {
7665 r = -ENOMEM;
443c39bc 7666 goto fail_free_lapic;
890ca9ae
HY		 7667 }
7668 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7669
f1797359
WY		 7670 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7671 r = -ENOMEM;
f5f48ee1 7672 goto fail_free_mce_banks;
f1797359 7673 }
f5f48ee1 7674
0ee6a517 7675 fx_init(vcpu);
66f7b72e 7676
ba904635 7677 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7678 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7679
7680 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7681 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7682
5a4f55cd
EK		 7683 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7684
74545705
RK		 7685 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7686
af585b92 7687 kvm_async_pf_hash_reset(vcpu);
f5132b01 7688 kvm_pmu_init(vcpu);
af585b92 7689
1c1a9ce9
SR		 7690 vcpu->arch.pending_external_vector = -1;
7691
5c919412
AS		 7692 kvm_hv_vcpu_init(vcpu);
7693
e9b11c17 7694 return 0;
0ee6a517 7695
f5f48ee1
SY		 7696fail_free_mce_banks:
7697 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7698fail_free_lapic:
7699 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7700fail_mmu_destroy:
7701 kvm_mmu_destroy(vcpu);
7702fail_free_pio_data:
ad312c7c 7703 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7704fail:
7705 return r;
7706}
7707
7708void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7709{
f656ce01
MT		 7710 int idx;
7711
1f4b34f8 7712 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7713 kvm_pmu_destroy(vcpu);
36cb93fd 7714 kfree(vcpu->arch.mce_banks);
e9b11c17 7715 kvm_free_lapic(vcpu);
f656ce01 7716 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7717 kvm_mmu_destroy(vcpu);
f656ce01 7718 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7719 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7720 if (!lapic_in_kernel(vcpu))
54e9818f 7721 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7722}
d19a9cd2 7723
e790d9ef
RK		 7724void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7725{
ae97a3b8 7726 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7727}
7728
e08b9637 7729int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7730{
e08b9637
CO		 7731 if (type)
7732 return -EINVAL;
7733
6ef768fa 7734 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7735 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7736 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7737 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7738 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7739
5550af4d
SY		 7740 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7741 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7742 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7743 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7744 &kvm->arch.irq_sources_bitmap);
5550af4d 7745
038f8c11 7746 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7747 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7748 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7749
7750 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7751
7e44e449 7752 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7753 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7754
0eb05bf2 7755 kvm_page_track_init(kvm);
13d268ca 7756 kvm_mmu_init_vm(kvm);
0eb05bf2 7757
d89f5eff 7758 return 0;
d19a9cd2
ZX		 7759}
7760
7761static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7762{
9fc77441
MT		 7763 int r;
7764 r = vcpu_load(vcpu);
7765 BUG_ON(r);
d19a9cd2
ZX		 7766 kvm_mmu_unload(vcpu);
7767 vcpu_put(vcpu);
7768}
7769
7770static void kvm_free_vcpus(struct kvm *kvm)
7771{
7772 unsigned int i;
988a2cae 7773 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7774
7775 /*
7776 * Unpin any mmu pages first.
7777 */
af585b92
GN		 7778 kvm_for_each_vcpu(i, vcpu, kvm) {
7779 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7780 kvm_unload_vcpu_mmu(vcpu);
af585b92 7781 }
988a2cae
GN		 7782 kvm_for_each_vcpu(i, vcpu, kvm)
7783 kvm_arch_vcpu_free(vcpu);
7784
7785 mutex_lock(&kvm->lock);
7786 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7787 kvm->vcpus[i] = NULL;
d19a9cd2 7788
988a2cae
GN		 7789 atomic_set(&kvm->online_vcpus, 0);
7790 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7791}
7792
ad8ba2cd
SY		 7793void kvm_arch_sync_events(struct kvm *kvm)
7794{
332967a3 7795 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7796 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7797 kvm_free_all_assigned_devices(kvm);
aea924f6 7798 kvm_free_pit(kvm);
ad8ba2cd
SY		 7799}
7800
1d8007bd 7801int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7802{
7803 int i, r;
25188b99 7804 unsigned long hva;
f0d648bd
PB		 7805 struct kvm_memslots *slots = kvm_memslots(kvm);
7806 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7807
7808 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7809 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7810 return -EINVAL;
9da0e4d5 7811
f0d648bd
PB		 7812 slot = id_to_memslot(slots, id);
7813 if (size) {
7814 if (WARN_ON(slot->npages))
7815 return -EEXIST;
7816
7817 /*
7818 * MAP_SHARED to prevent internal slot pages from being moved
7819 * by fork()/COW.
7820 */
7821 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7822 MAP_SHARED | MAP_ANONYMOUS, 0);
7823 if (IS_ERR((void *)hva))
7824 return PTR_ERR((void *)hva);
7825 } else {
7826 if (!slot->npages)
7827 return 0;
7828
7829 hva = 0;
7830 }
7831
7832 old = *slot;
9da0e4d5 7833 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7834 struct kvm_userspace_memory_region m;
9da0e4d5 7835
1d8007bd
PB		 7836 m.slot = id | (i << 16);
7837 m.flags = 0;
7838 m.guest_phys_addr = gpa;
f0d648bd 7839 m.userspace_addr = hva;
1d8007bd 7840 m.memory_size = size;
9da0e4d5
PB		 7841 r = __kvm_set_memory_region(kvm, &m);
7842 if (r < 0)
7843 return r;
7844 }
7845
f0d648bd
PB		 7846 if (!size) {
7847 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7848 WARN_ON(r < 0);
7849 }
7850
9da0e4d5
PB		 7851 return 0;
7852}
7853EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7854
1d8007bd 7855int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7856{
7857 int r;
7858
7859 mutex_lock(&kvm->slots_lock);
1d8007bd 7860 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7861 mutex_unlock(&kvm->slots_lock);
7862
7863 return r;
7864}
7865EXPORT_SYMBOL_GPL(x86_set_memory_region);
7866
d19a9cd2
ZX		 7867void kvm_arch_destroy_vm(struct kvm *kvm)
7868{
27469d29
AH		 7869 if (current->mm == kvm->mm) {
7870 /*
7871 * Free memory regions allocated on behalf of userspace,
7872 * unless the the memory map has changed due to process exit
7873 * or fd copying.
7874 */
1d8007bd
PB		 7875 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7876 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7877 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7878 }
6eb55818 7879 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7880 kfree(kvm->arch.vpic);
7881 kfree(kvm->arch.vioapic);
d19a9cd2 7882 kvm_free_vcpus(kvm);
1e08ec4a 7883 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7884 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7885}
0de10343 7886
5587027c 7887void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7888 struct kvm_memory_slot *dont)
7889{
7890 int i;
7891
d89cc617
TY		 7892 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7893 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7894 kvfree(free->arch.rmap[i]);
d89cc617 7895 free->arch.rmap[i] = NULL;
77d11309 7896 }
d89cc617
TY		 7897 if (i == 0)
7898 continue;
7899
7900 if (!dont || free->arch.lpage_info[i - 1] !=
7901 dont->arch.lpage_info[i - 1]) {
548ef284 7902 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7903 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7904 }
7905 }
21ebbeda
XG		 7906
7907 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7908}
7909
5587027c
AK		 7910int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7911 unsigned long npages)
db3fe4eb
TY		 7912{
7913 int i;
7914
d89cc617 7915 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7916 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7917 unsigned long ugfn;
7918 int lpages;
d89cc617 7919 int level = i + 1;
db3fe4eb
TY		 7920
7921 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7922 slot->base_gfn, level) + 1;
7923
d89cc617
TY		 7924 slot->arch.rmap[i] =
7925 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7926 if (!slot->arch.rmap[i])
77d11309 7927 goto out_free;
d89cc617
TY		 7928 if (i == 0)
7929 continue;
77d11309 7930
92f94f1e
XG		 7931 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7932 if (!linfo)
db3fe4eb
TY		 7933 goto out_free;
7934
92f94f1e
XG		 7935 slot->arch.lpage_info[i - 1] = linfo;
7936
db3fe4eb 7937 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7938 linfo[0].disallow_lpage = 1;
db3fe4eb 7939 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7940 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7941 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7942 /*
7943 * If the gfn and userspace address are not aligned wrt each
7944 * other, or if explicitly asked to, disable large page
7945 * support for this slot
7946 */
7947 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7948 !kvm_largepages_enabled()) {
7949 unsigned long j;
7950
7951 for (j = 0; j < lpages; ++j)
92f94f1e 7952 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7953 }
7954 }
7955
21ebbeda
XG		 7956 if (kvm_page_track_create_memslot(slot, npages))
7957 goto out_free;
7958
db3fe4eb
TY		 7959 return 0;
7960
7961out_free:
d89cc617 7962 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7963 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7964 slot->arch.rmap[i] = NULL;
7965 if (i == 0)
7966 continue;
7967
548ef284 7968 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7969 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7970 }
7971 return -ENOMEM;
7972}
7973
15f46015 7974void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7975{
e6dff7d1
TY		 7976 /*
7977 * memslots->generation has been incremented.
7978 * mmio generation may have reached its maximum value.
7979 */
54bf36aa 7980 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7981}
7982
f7784b8e
MT		 7983int kvm_arch_prepare_memory_region(struct kvm *kvm,
7984 struct kvm_memory_slot *memslot,
09170a49 7985 const struct kvm_userspace_memory_region *mem,
7b6195a9 7986 enum kvm_mr_change change)
0de10343 7987{
f7784b8e
MT		 7988 return 0;
7989}
7990
88178fd4
KH		 7991static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7992 struct kvm_memory_slot *new)
7993{
7994 /* Still write protect RO slot */
7995 if (new->flags & KVM_MEM_READONLY) {
7996 kvm_mmu_slot_remove_write_access(kvm, new);
7997 return;
7998 }
7999
8000 /*
8001 * Call kvm_x86_ops dirty logging hooks when they are valid.
8002 *
8003 * kvm_x86_ops->slot_disable_log_dirty is called when:
8004 *
8005 * - KVM_MR_CREATE with dirty logging is disabled
8006 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8007 *
8008 * The reason is, in case of PML, we need to set D-bit for any slots
8009 * with dirty logging disabled in order to eliminate unnecessary GPA
8010 * logging in PML buffer (and potential PML buffer full VMEXT). This
8011 * guarantees leaving PML enabled during guest's lifetime won't have
8012 * any additonal overhead from PML when guest is running with dirty
8013 * logging disabled for memory slots.
8014 *
8015 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8016 * to dirty logging mode.
8017 *
8018 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8019 *
8020 * In case of write protect:
8021 *
8022 * Write protect all pages for dirty logging.
8023 *
8024 * All the sptes including the large sptes which point to this
8025 * slot are set to readonly. We can not create any new large
8026 * spte on this slot until the end of the logging.
8027 *
8028 * See the comments in fast_page_fault().
8029 */
8030 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8031 if (kvm_x86_ops->slot_enable_log_dirty)
8032 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8033 else
8034 kvm_mmu_slot_remove_write_access(kvm, new);
8035 } else {
8036 if (kvm_x86_ops->slot_disable_log_dirty)
8037 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8038 }
8039}
8040
f7784b8e 8041void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8042 const struct kvm_userspace_memory_region *mem,
8482644a 8043 const struct kvm_memory_slot *old,
f36f3f28 8044 const struct kvm_memory_slot *new,
8482644a 8045 enum kvm_mr_change change)
f7784b8e 8046{
8482644a 8047 int nr_mmu_pages = 0;
f7784b8e 8048
48c0e4e9
XG		 8049 if (!kvm->arch.n_requested_mmu_pages)
8050 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8051
48c0e4e9 8052 if (nr_mmu_pages)
0de10343 8053 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8054
3ea3b7fa
WL		 8055 /*
8056 * Dirty logging tracks sptes in 4k granularity, meaning that large
8057 * sptes have to be split. If live migration is successful, the guest
8058 * in the source machine will be destroyed and large sptes will be
8059 * created in the destination. However, if the guest continues to run
8060 * in the source machine (for example if live migration fails), small
8061 * sptes will remain around and cause bad performance.
8062 *
8063 * Scan sptes if dirty logging has been stopped, dropping those
8064 * which can be collapsed into a single large-page spte. Later
8065 * page faults will create the large-page sptes.
8066 */
8067 if ((change != KVM_MR_DELETE) &&
8068 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8069 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8070 kvm_mmu_zap_collapsible_sptes(kvm, new);
8071
c972f3b1 8072 /*
88178fd4 8073 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8074 *
88178fd4
KH		 8075 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8076 * been zapped so no dirty logging staff is needed for old slot. For
8077 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8078 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8079 *
8080 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8081 */
88178fd4 8082 if (change != KVM_MR_DELETE)
f36f3f28 8083 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8084}
1d737c8a 8085
2df72e9b 8086void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8087{
6ca18b69 8088 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8089}
8090
2df72e9b
MT		 8091void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8092 struct kvm_memory_slot *slot)
8093{
6ca18b69 8094 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8095}
8096
5d9bc648
PB		 8097static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8098{
8099 if (!list_empty_careful(&vcpu->async_pf.done))
8100 return true;
8101
8102 if (kvm_apic_has_events(vcpu))
8103 return true;
8104
8105 if (vcpu->arch.pv.pv_unhalted)
8106 return true;
8107
8108 if (atomic_read(&vcpu->arch.nmi_queued))
8109 return true;
8110
73917739
PB		 8111 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8112 return true;
8113
5d9bc648
PB		 8114 if (kvm_arch_interrupt_allowed(vcpu) &&
8115 kvm_cpu_has_interrupt(vcpu))
8116 return true;
8117
1f4b34f8
AS		 8118 if (kvm_hv_has_stimer_pending(vcpu))
8119 return true;
8120
5d9bc648
PB		 8121 return false;
8122}
8123
1d737c8a
ZX		 8124int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8125{
b6b8a145
JK		 8126 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8127 kvm_x86_ops->check_nested_events(vcpu, false);
8128
5d9bc648 8129 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8130}
5736199a 8131
b6d33834 8132int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8133{
b6d33834 8134 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8135}
78646121
GN		 8136
8137int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8138{
8139 return kvm_x86_ops->interrupt_allowed(vcpu);
8140}
229456fc 8141
82b32774 8142unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8143{
82b32774
NA		 8144 if (is_64_bit_mode(vcpu))
8145 return kvm_rip_read(vcpu);
8146 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8147 kvm_rip_read(vcpu));
8148}
8149EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8150
82b32774
NA		 8151bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8152{
8153 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8154}
8155EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8156
94fe45da
JK		 8157unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8158{
8159 unsigned long rflags;
8160
8161 rflags = kvm_x86_ops->get_rflags(vcpu);
8162 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8163 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8164 return rflags;
8165}
8166EXPORT_SYMBOL_GPL(kvm_get_rflags);
8167
6addfc42 8168static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8169{
8170 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8171 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8172 rflags |= X86_EFLAGS_TF;
94fe45da 8173 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8174}
8175
8176void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8177{
8178 __kvm_set_rflags(vcpu, rflags);
3842d135 8179 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8180}
8181EXPORT_SYMBOL_GPL(kvm_set_rflags);
8182
56028d08
GN		 8183void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8184{
8185 int r;
8186
fb67e14f 8187 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8188 work->wakeup_all)
56028d08
GN		 8189 return;
8190
8191 r = kvm_mmu_reload(vcpu);
8192 if (unlikely(r))
8193 return;
8194
fb67e14f
XG		 8195 if (!vcpu->arch.mmu.direct_map &&
8196 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8197 return;
8198
56028d08
GN		 8199 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8200}
8201
af585b92
GN		 8202static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8203{
8204 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8205}
8206
8207static inline u32 kvm_async_pf_next_probe(u32 key)
8208{
8209 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8210}
8211
8212static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8213{
8214 u32 key = kvm_async_pf_hash_fn(gfn);
8215
8216 while (vcpu->arch.apf.gfns[key] != ~0)
8217 key = kvm_async_pf_next_probe(key);
8218
8219 vcpu->arch.apf.gfns[key] = gfn;
8220}
8221
8222static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8223{
8224 int i;
8225 u32 key = kvm_async_pf_hash_fn(gfn);
8226
8227 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8228 (vcpu->arch.apf.gfns[key] != gfn &&
8229 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8230 key = kvm_async_pf_next_probe(key);
8231
8232 return key;
8233}
8234
8235bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8236{
8237 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8238}
8239
8240static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8241{
8242 u32 i, j, k;
8243
8244 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8245 while (true) {
8246 vcpu->arch.apf.gfns[i] = ~0;
8247 do {
8248 j = kvm_async_pf_next_probe(j);
8249 if (vcpu->arch.apf.gfns[j] == ~0)
8250 return;
8251 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8252 /*
8253 * k lies cyclically in ]i,j]
8254 * | i.k.j |
8255 * |....j i.k.| or |.k..j i...|
8256 */
8257 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8258 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8259 i = j;
8260 }
8261}
8262
7c90705b
GN		 8263static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8264{
8265
8266 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8267 sizeof(val));
8268}
8269
af585b92
GN		 8270void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8271 struct kvm_async_pf *work)
8272{
6389ee94
AK		 8273 struct x86_exception fault;
8274
7c90705b 8275 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8276 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8277
8278 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8279 (vcpu->arch.apf.send_user_only &&
8280 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8281 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8282 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8283 fault.vector = PF_VECTOR;
8284 fault.error_code_valid = true;
8285 fault.error_code = 0;
8286 fault.nested_page_fault = false;
8287 fault.address = work->arch.token;
8288 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8289 }
af585b92
GN		 8290}
8291
8292void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8293 struct kvm_async_pf *work)
8294{
6389ee94
AK		 8295 struct x86_exception fault;
8296
7c90705b 8297 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8298 if (work->wakeup_all)
7c90705b
GN		 8299 work->arch.token = ~0; /* broadcast wakeup */
8300 else
8301 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8302
8303 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8304 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8305 fault.vector = PF_VECTOR;
8306 fault.error_code_valid = true;
8307 fault.error_code = 0;
8308 fault.nested_page_fault = false;
8309 fault.address = work->arch.token;
8310 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8311 }
e6d53e3b 8312 vcpu->arch.apf.halted = false;
a4fa1635 8313 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8314}
8315
8316bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8317{
8318 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8319 return true;
8320 else
8321 return !kvm_event_needs_reinjection(vcpu) &&
8322 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8323}
8324
5544eb9b
PB		 8325void kvm_arch_start_assignment(struct kvm *kvm)
8326{
8327 atomic_inc(&kvm->arch.assigned_device_count);
8328}
8329EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8330
8331void kvm_arch_end_assignment(struct kvm *kvm)
8332{
8333 atomic_dec(&kvm->arch.assigned_device_count);
8334}
8335EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8336
8337bool kvm_arch_has_assigned_device(struct kvm *kvm)
8338{
8339 return atomic_read(&kvm->arch.assigned_device_count);
8340}
8341EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8342
e0f0bbc5
AW		 8343void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8344{
8345 atomic_inc(&kvm->arch.noncoherent_dma_count);
8346}
8347EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8348
8349void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8350{
8351 atomic_dec(&kvm->arch.noncoherent_dma_count);
8352}
8353EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8354
8355bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8356{
8357 return atomic_read(&kvm->arch.noncoherent_dma_count);
8358}
8359EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8360
14717e20
AW		 8361bool kvm_arch_has_irq_bypass(void)
8362{
8363 return kvm_x86_ops->update_pi_irte != NULL;
8364}
8365
87276880
FW		 8366int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8367 struct irq_bypass_producer *prod)
8368{
8369 struct kvm_kernel_irqfd *irqfd =
8370 container_of(cons, struct kvm_kernel_irqfd, consumer);
8371
14717e20 8372 irqfd->producer = prod;
87276880 8373
14717e20
AW		 8374 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8375 prod->irq, irqfd->gsi, 1);
87276880
FW		 8376}
8377
8378void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8379 struct irq_bypass_producer *prod)
8380{
8381 int ret;
8382 struct kvm_kernel_irqfd *irqfd =
8383 container_of(cons, struct kvm_kernel_irqfd, consumer);
8384
87276880
FW		 8385 WARN_ON(irqfd->producer != prod);
8386 irqfd->producer = NULL;
8387
8388 /*
8389 * When producer of consumer is unregistered, we change back to
8390 * remapped mode, so we can re-use the current implementation
8391 * when the irq is masked/disabed or the consumer side (KVM
8392 * int this case doesn't want to receive the interrupts.
8393 */
8394 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8395 if (ret)
8396 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8397 " fails: %d\n", irqfd->consumer.token, ret);
8398}
8399
8400int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8401 uint32_t guest_irq, bool set)
8402{
8403 if (!kvm_x86_ops->update_pi_irte)
8404 return -EINVAL;
8405
8406 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8407}
8408
52004014
FW		 8409bool kvm_vector_hashing_enabled(void)
8410{
8411 return vector_hashing;
8412}
8413EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8414
229456fc 8415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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