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NVMe: Protect against badly formatted CQEs
[mirror_ubuntu-bionic-kernel.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b60503ba
MW		 45#define NVME_Q_DEPTH 1024
46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 48#define ADMIN_TIMEOUT (60 * HZ)
edd10d33 49#define IOD_TIMEOUT (4 * NVME_IO_TIMEOUT)
b60503ba 50
b355084a
KB		 51unsigned char io_timeout = 30;
52module_param(io_timeout, byte, 0644);
53MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba
MW		 54
55static int nvme_major;
56module_param(nvme_major, int, 0);
57
58ffacb5
MW		 58static int use_threaded_interrupts;
59module_param(use_threaded_interrupts, int, 0);
60
1fa6aead
MW		 61static DEFINE_SPINLOCK(dev_list_lock);
62static LIST_HEAD(dev_list);
63static struct task_struct *nvme_thread;
9a6b9458 64static struct workqueue_struct *nvme_workq;
b9afca3e 65static wait_queue_head_t nvme_kthread_wait;
1fa6aead 66
d4b4ff8e
KB		 67static void nvme_reset_failed_dev(struct work_struct *ws);
68
4d115420
KB		 69struct async_cmd_info {
70 struct kthread_work work;
71 struct kthread_worker *worker;
72 u32 result;
73 int status;
74 void *ctx;
75};
1fa6aead 76
b60503ba
MW		 77/*
78 * An NVM Express queue. Each device has at least two (one for admin
79 * commands and one for I/O commands).
80 */
81struct nvme_queue {
5a92e700 82 struct rcu_head r_head;
b60503ba 83 struct device *q_dmadev;
091b6092 84 struct nvme_dev *dev;
3193f07b 85 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 86 spinlock_t q_lock;
87 struct nvme_command *sq_cmds;
88 volatile struct nvme_completion *cqes;
89 dma_addr_t sq_dma_addr;
90 dma_addr_t cq_dma_addr;
91 wait_queue_head_t sq_full;
1fa6aead 92 wait_queue_t sq_cong_wait;
b60503ba 93 struct bio_list sq_cong;
edd10d33 94 struct list_head iod_bio;
b60503ba
MW		 95 u32 __iomem *q_db;
96 u16 q_depth;
97 u16 cq_vector;
98 u16 sq_head;
99 u16 sq_tail;
100 u16 cq_head;
c30341dc 101 u16 qid;
e9539f47
MW		 102 u8 cq_phase;
103 u8 cqe_seen;
22404274 104 u8 q_suspended;
42f61420 105 cpumask_var_t cpu_mask;
4d115420 106 struct async_cmd_info cmdinfo;
b60503ba
MW		 107 unsigned long cmdid_data[];
108};
109
110/*
111 * Check we didin't inadvertently grow the command struct
112 */
113static inline void _nvme_check_size(void)
114{
115 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
117 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 120 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 121 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 122 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
124 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
125 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 126 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 127}
128
edd10d33 129typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 130 struct nvme_completion *);
131
e85248e5 132struct nvme_cmd_info {
c2f5b650
MW		 133 nvme_completion_fn fn;
134 void *ctx;
e85248e5 135 unsigned long timeout;
c30341dc 136 int aborted;
e85248e5
MW		 137};
138
139static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
140{
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
142}
143
22404274
KB		 144static unsigned nvme_queue_extra(int depth)
145{
146 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
147}
148
b60503ba 149/**
714a7a22
MW		 150 * alloc_cmdid() - Allocate a Command ID
151 * @nvmeq: The queue that will be used for this command
152 * @ctx: A pointer that will be passed to the handler
c2f5b650 153 * @handler: The function to call on completion
b60503ba
MW		 154 *
155 * Allocate a Command ID for a queue. The data passed in will
156 * be passed to the completion handler. This is implemented by using
157 * the bottom two bits of the ctx pointer to store the handler ID.
158 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
159 * We can change this if it becomes a problem.
184d2944
MW		 160 *
161 * May be called with local interrupts disabled and the q_lock held,
162 * or with interrupts enabled and no locks held.
b60503ba 163 */
c2f5b650
MW		 164static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
165 nvme_completion_fn handler, unsigned timeout)
b60503ba 166{
e6d15f79 167 int depth = nvmeq->q_depth - 1;
e85248e5 168 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 169 int cmdid;
170
b60503ba
MW		 171 do {
172 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
173 if (cmdid >= depth)
174 return -EBUSY;
175 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
176
c2f5b650
MW		 177 info[cmdid].fn = handler;
178 info[cmdid].ctx = ctx;
e85248e5 179 info[cmdid].timeout = jiffies + timeout;
c30341dc 180 info[cmdid].aborted = 0;
b60503ba
MW		 181 return cmdid;
182}
183
184static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 185 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 186{
187 int cmdid;
188 wait_event_killable(nvmeq->sq_full,
e85248e5 189 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 190 return (cmdid < 0) ? -EINTR : cmdid;
191}
192
c2f5b650
MW		 193/* Special values must be less than 0x1000 */
194#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 195#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
196#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
197#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 198#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 199#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 200
edd10d33 201static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 202 struct nvme_completion *cqe)
203{
204 if (ctx == CMD_CTX_CANCELLED)
205 return;
206 if (ctx == CMD_CTX_FLUSH)
207 return;
c30341dc 208 if (ctx == CMD_CTX_ABORT) {
edd10d33 209 ++nvmeq->dev->abort_limit;
c30341dc
KB		 210 return;
211 }
c2f5b650 212 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 213 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 214 "completed id %d twice on queue %d\n",
215 cqe->command_id, le16_to_cpup(&cqe->sq_id));
216 return;
217 }
218 if (ctx == CMD_CTX_INVALID) {
edd10d33 219 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 220 "invalid id %d completed on queue %d\n",
221 cqe->command_id, le16_to_cpup(&cqe->sq_id));
222 return;
223 }
224
edd10d33 225 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 226}
227
edd10d33 228static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 229 struct nvme_completion *cqe)
230{
231 struct async_cmd_info *cmdinfo = ctx;
232 cmdinfo->result = le32_to_cpup(&cqe->result);
233 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
234 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
235}
236
184d2944
MW		 237/*
238 * Called with local interrupts disabled and the q_lock held. May not sleep.
239 */
c2f5b650
MW		 240static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
241 nvme_completion_fn *fn)
b60503ba 242{
c2f5b650 243 void *ctx;
e85248e5 244 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 245
94bbac40
KB		 246 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
247 if (fn)
248 *fn = special_completion;
48e3d398 249 return CMD_CTX_INVALID;
c2f5b650 250 }
859361a2
KB		 251 if (fn)
252 *fn = info[cmdid].fn;
c2f5b650
MW		 253 ctx = info[cmdid].ctx;
254 info[cmdid].fn = special_completion;
e85248e5 255 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 256 clear_bit(cmdid, nvmeq->cmdid_data);
257 wake_up(&nvmeq->sq_full);
c2f5b650 258 return ctx;
b60503ba
MW		 259}
260
c2f5b650
MW		 261static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
262 nvme_completion_fn *fn)
3c0cf138 263{
c2f5b650 264 void *ctx;
e85248e5 265 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 266 if (fn)
267 *fn = info[cmdid].fn;
268 ctx = info[cmdid].ctx;
269 info[cmdid].fn = special_completion;
e85248e5 270 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 271 return ctx;
3c0cf138
MW		 272}
273
5a92e700 274static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 275{
5a92e700 276 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 277}
278
4f5099af 279static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 280{
42f61420 281 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 282 rcu_read_lock();
42f61420 283 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 284}
285
4f5099af 286static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 287{
5a92e700 288 rcu_read_unlock();
42f61420 289 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 290}
291
4f5099af
KB		 292static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
293 __acquires(RCU)
b60503ba 294{
4f5099af
KB		 295 rcu_read_lock();
296 return rcu_dereference(dev->queues[q_idx]);
297}
298
299static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
300{
301 rcu_read_unlock();
b60503ba
MW		 302}
303
304/**
714a7a22 305 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 306 * @nvmeq: The queue to use
307 * @cmd: The command to send
308 *
309 * Safe to use from interrupt context
310 */
311static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
312{
313 unsigned long flags;
314 u16 tail;
b60503ba 315 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 316 if (nvmeq->q_suspended) {
317 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
318 return -EBUSY;
319 }
b60503ba
MW		 320 tail = nvmeq->sq_tail;
321 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 322 if (++tail == nvmeq->q_depth)
323 tail = 0;
7547881d 324 writel(tail, nvmeq->q_db);
b60503ba
MW		 325 nvmeq->sq_tail = tail;
326 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
327
328 return 0;
329}
330
eca18b23 331static __le64 **iod_list(struct nvme_iod *iod)
e025344c 332{
eca18b23 333 return ((void *)iod) + iod->offset;
e025344c
SMM		 334}
335
eca18b23
MW		 336/*
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
339 * the I/O.
340 */
341static int nvme_npages(unsigned size)
342{
343 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
344 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
345}
b60503ba 346
eca18b23
MW		 347static struct nvme_iod *
348nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 349{
eca18b23
MW		 350 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
351 sizeof(__le64 *) * nvme_npages(nbytes) +
352 sizeof(struct scatterlist) * nseg, gfp);
353
354 if (iod) {
355 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
356 iod->npages = -1;
357 iod->length = nbytes;
2b196034 358 iod->nents = 0;
edd10d33 359 iod->first_dma = 0ULL;
6198221f 360 iod->start_time = jiffies;
eca18b23
MW		 361 }
362
363 return iod;
b60503ba
MW		 364}
365
5d0f6131 366void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 367{
eca18b23
MW		 368 const int last_prp = PAGE_SIZE / 8 - 1;
369 int i;
370 __le64 **list = iod_list(iod);
371 dma_addr_t prp_dma = iod->first_dma;
372
373 if (iod->npages == 0)
374 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
375 for (i = 0; i < iod->npages; i++) {
376 __le64 *prp_list = list[i];
377 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
378 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
379 prp_dma = next_prp_dma;
380 }
381 kfree(iod);
b60503ba
MW		 382}
383
6198221f
KB		 384static void nvme_start_io_acct(struct bio *bio)
385{
386 struct gendisk *disk = bio->bi_bdev->bd_disk;
387 const int rw = bio_data_dir(bio);
388 int cpu = part_stat_lock();
389 part_round_stats(cpu, &disk->part0);
390 part_stat_inc(cpu, &disk->part0, ios[rw]);
391 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
392 part_inc_in_flight(&disk->part0, rw);
393 part_stat_unlock();
394}
395
396static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
397{
398 struct gendisk *disk = bio->bi_bdev->bd_disk;
399 const int rw = bio_data_dir(bio);
400 unsigned long duration = jiffies - start_time;
401 int cpu = part_stat_lock();
402 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
403 part_round_stats(cpu, &disk->part0);
404 part_dec_in_flight(&disk->part0, rw);
405 part_stat_unlock();
406}
407
edd10d33 408static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 409 struct nvme_completion *cqe)
410{
eca18b23
MW		 411 struct nvme_iod *iod = ctx;
412 struct bio *bio = iod->private;
b60503ba
MW		 413 u16 status = le16_to_cpup(&cqe->status) >> 1;
414
edd10d33
KB		 415 if (unlikely(status)) {
416 if (!(status & NVME_SC_DNR ||
417 bio->bi_rw & REQ_FAILFAST_MASK) &&
418 (jiffies - iod->start_time) < IOD_TIMEOUT) {
419 if (!waitqueue_active(&nvmeq->sq_full))
420 add_wait_queue(&nvmeq->sq_full,
421 &nvmeq->sq_cong_wait);
422 list_add_tail(&iod->node, &nvmeq->iod_bio);
423 wake_up(&nvmeq->sq_full);
424 return;
425 }
426 }
9e59d091 427 if (iod->nents) {
edd10d33 428 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 429 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 430 nvme_end_io_acct(bio, iod->start_time);
431 }
edd10d33 432 nvme_free_iod(nvmeq->dev, iod);
427e9708 433 if (status)
1ad2f893 434 bio_endio(bio, -EIO);
427e9708 435 else
1ad2f893 436 bio_endio(bio, 0);
b60503ba
MW		 437}
438
184d2944 439/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 440int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
441 gfp_t gfp)
ff22b54f 442{
99802a7a 443 struct dma_pool *pool;
eca18b23
MW		 444 int length = total_len;
445 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 446 int dma_len = sg_dma_len(sg);
447 u64 dma_addr = sg_dma_address(sg);
448 int offset = offset_in_page(dma_addr);
e025344c 449 __le64 *prp_list;
eca18b23 450 __le64 **list = iod_list(iod);
e025344c 451 dma_addr_t prp_dma;
eca18b23 452 int nprps, i;
ff22b54f 453
ff22b54f
MW		 454 length -= (PAGE_SIZE - offset);
455 if (length <= 0)
eca18b23 456 return total_len;
ff22b54f
MW		 457
458 dma_len -= (PAGE_SIZE - offset);
459 if (dma_len) {
460 dma_addr += (PAGE_SIZE - offset);
461 } else {
462 sg = sg_next(sg);
463 dma_addr = sg_dma_address(sg);
464 dma_len = sg_dma_len(sg);
465 }
466
467 if (length <= PAGE_SIZE) {
edd10d33 468 iod->first_dma = dma_addr;
eca18b23 469 return total_len;
e025344c
SMM		 470 }
471
472 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 473 if (nprps <= (256 / 8)) {
474 pool = dev->prp_small_pool;
eca18b23 475 iod->npages = 0;
99802a7a
MW		 476 } else {
477 pool = dev->prp_page_pool;
eca18b23 478 iod->npages = 1;
99802a7a
MW		 479 }
480
b77954cb
MW		 481 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
482 if (!prp_list) {
edd10d33 483 iod->first_dma = dma_addr;
eca18b23
MW		 484 iod->npages = -1;
485 return (total_len - length) + PAGE_SIZE;
b77954cb 486 }
eca18b23
MW		 487 list[0] = prp_list;
488 iod->first_dma = prp_dma;
e025344c
SMM		 489 i = 0;
490 for (;;) {
7523d834 491 if (i == PAGE_SIZE / 8) {
e025344c 492 __le64 *old_prp_list = prp_list;
b77954cb 493 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 494 if (!prp_list)
495 return total_len - length;
496 list[iod->npages++] = prp_list;
7523d834
MW		 497 prp_list[0] = old_prp_list[i - 1];
498 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
499 i = 1;
e025344c
SMM		 500 }
501 prp_list[i++] = cpu_to_le64(dma_addr);
502 dma_len -= PAGE_SIZE;
503 dma_addr += PAGE_SIZE;
504 length -= PAGE_SIZE;
505 if (length <= 0)
506 break;
507 if (dma_len > 0)
508 continue;
509 BUG_ON(dma_len < 0);
510 sg = sg_next(sg);
511 dma_addr = sg_dma_address(sg);
512 dma_len = sg_dma_len(sg);
ff22b54f
MW		 513 }
514
eca18b23 515 return total_len;
ff22b54f
MW		 516}
517
427e9708 518static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 519 int len)
427e9708 520{
20d0189b
KO		 521 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
522 if (!split)
427e9708
KB		 523 return -ENOMEM;
524
20d0189b
KO		 525 bio_chain(split, bio);
526
edd10d33 527 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 528 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 529 bio_list_add(&nvmeq->sq_cong, split);
530 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 531 wake_up(&nvmeq->sq_full);
427e9708
KB		 532
533 return 0;
534}
535
1ad2f893
MW		 536/* NVMe scatterlists require no holes in the virtual address */
537#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
538 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
539
427e9708 540static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 541 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
542{
7988613b
KO		 543 struct bio_vec bvec, bvprv;
544 struct bvec_iter iter;
76830840 545 struct scatterlist *sg = NULL;
7988613b
KO		 546 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
547 int first = 1;
159b67d7
KB		 548
549 if (nvmeq->dev->stripe_size)
550 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 551 ((bio->bi_iter.bi_sector << 9) &
552 (nvmeq->dev->stripe_size - 1));
b60503ba 553
eca18b23 554 sg_init_table(iod->sg, psegs);
7988613b
KO		 555 bio_for_each_segment(bvec, bio, iter) {
556 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
557 sg->length += bvec.bv_len;
76830840 558 } else {
7988613b
KO		 559 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
560 return nvme_split_and_submit(bio, nvmeq,
20d0189b 561 length);
427e9708 562
eca18b23 563 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 564 sg_set_page(sg, bvec.bv_page,
565 bvec.bv_len, bvec.bv_offset);
76830840
MW		 566 nsegs++;
567 }
159b67d7 568
7988613b 569 if (split_len - length < bvec.bv_len)
20d0189b 570 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 571 length += bvec.bv_len;
76830840 572 bvprv = bvec;
7988613b 573 first = 0;
b60503ba 574 }
eca18b23 575 iod->nents = nsegs;
76830840 576 sg_mark_end(sg);
427e9708 577 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 578 return -ENOMEM;
427e9708 579
4f024f37 580 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 581 return length;
b60503ba
MW		 582}
583
0e5e4f0e
KB		 584static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
585 struct bio *bio, struct nvme_iod *iod, int cmdid)
586{
edd10d33
KB		 587 struct nvme_dsm_range *range =
588 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 589 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
590
0e5e4f0e 591 range->cattr = cpu_to_le32(0);
4f024f37
KO		 592 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
593 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 594
595 memset(cmnd, 0, sizeof(*cmnd));
596 cmnd->dsm.opcode = nvme_cmd_dsm;
597 cmnd->dsm.command_id = cmdid;
598 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
599 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
600 cmnd->dsm.nr = 0;
601 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
602
603 if (++nvmeq->sq_tail == nvmeq->q_depth)
604 nvmeq->sq_tail = 0;
605 writel(nvmeq->sq_tail, nvmeq->q_db);
606
607 return 0;
608}
609
00df5cb4
MW		 610static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
611 int cmdid)
612{
613 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
614
615 memset(cmnd, 0, sizeof(*cmnd));
616 cmnd->common.opcode = nvme_cmd_flush;
617 cmnd->common.command_id = cmdid;
618 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
619
620 if (++nvmeq->sq_tail == nvmeq->q_depth)
621 nvmeq->sq_tail = 0;
622 writel(nvmeq->sq_tail, nvmeq->q_db);
623
624 return 0;
625}
626
5d0f6131 627int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 628{
629 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 630 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 631 if (unlikely(cmdid < 0))
632 return cmdid;
633
634 return nvme_submit_flush(nvmeq, ns, cmdid);
635}
636
edd10d33 637static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 638{
edd10d33
KB		 639 struct bio *bio = iod->private;
640 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 641 struct nvme_command *cmnd;
edd10d33 642 int cmdid;
b60503ba
MW		 643 u16 control;
644 u32 dsmgmt;
00df5cb4 645
ff976d72 646 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 647 if (unlikely(cmdid < 0))
edd10d33 648 return cmdid;
b60503ba 649
edd10d33
KB		 650 if (bio->bi_rw & REQ_DISCARD)
651 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
652 if ((bio->bi_rw & REQ_FLUSH) && !iod->nents)
00df5cb4
MW		 653 return nvme_submit_flush(nvmeq, ns, cmdid);
654
b60503ba
MW		 655 control = 0;
656 if (bio->bi_rw & REQ_FUA)
657 control |= NVME_RW_FUA;
658 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
659 control |= NVME_RW_LR;
660
661 dsmgmt = 0;
662 if (bio->bi_rw & REQ_RAHEAD)
663 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
664
ff22b54f 665 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 666 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 667
edd10d33 668 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 669 cmnd->rw.command_id = cmdid;
670 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 671 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
672 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 673 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 674 cmnd->rw.length =
675 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 676 cmnd->rw.control = cpu_to_le16(control);
677 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 678
b60503ba
MW		 679 if (++nvmeq->sq_tail == nvmeq->q_depth)
680 nvmeq->sq_tail = 0;
7547881d 681 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 682
1974b1ae 683 return 0;
edd10d33
KB		 684}
685
686/*
687 * Called with local interrupts disabled and the q_lock held. May not sleep.
688 */
689static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
690 struct bio *bio)
691{
692 struct nvme_iod *iod;
693 int psegs = bio_phys_segments(ns->queue, bio);
694 int result;
695
696 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
697 result = nvme_submit_flush_data(nvmeq, ns);
698 if (result)
699 return result;
700 }
701
702 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
703 if (!iod)
704 return -ENOMEM;
705
706 iod->private = bio;
707 if (bio->bi_rw & REQ_DISCARD) {
708 void *range;
709 /*
710 * We reuse the small pool to allocate the 16-byte range here
711 * as it is not worth having a special pool for these or
712 * additional cases to handle freeing the iod.
713 */
714 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
715 GFP_ATOMIC,
716 &iod->first_dma);
717 if (!range) {
718 result = -ENOMEM;
719 goto free_iod;
720 }
721 iod_list(iod)[0] = (__le64 *)range;
722 iod->npages = 0;
723 } else if (psegs) {
724 result = nvme_map_bio(nvmeq, iod, bio,
725 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
726 psegs);
727 if (result <= 0)
728 goto free_iod;
729 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
730 result) {
731 result = -ENOMEM;
732 goto free_iod;
733 }
734 nvme_start_io_acct(bio);
735 }
736 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
737 if (!waitqueue_active(&nvmeq->sq_full))
738 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
739 list_add_tail(&iod->node, &nvmeq->iod_bio);
740 }
741 return 0;
1974b1ae 742
eca18b23
MW		 743 free_iod:
744 nvme_free_iod(nvmeq->dev, iod);
eeee3226 745 return result;
b60503ba
MW		 746}
747
e9539f47 748static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 749{
82123460 750 u16 head, phase;
b60503ba 751
b60503ba 752 head = nvmeq->cq_head;
82123460 753 phase = nvmeq->cq_phase;
b60503ba
MW		 754
755 for (;;) {
c2f5b650
MW		 756 void *ctx;
757 nvme_completion_fn fn;
b60503ba 758 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 759 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 760 break;
761 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
762 if (++head == nvmeq->q_depth) {
763 head = 0;
82123460 764 phase = !phase;
b60503ba
MW		 765 }
766
c2f5b650 767 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 768 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 769 }
770
771 /* If the controller ignores the cq head doorbell and continuously
772 * writes to the queue, it is theoretically possible to wrap around
773 * the queue twice and mistakenly return IRQ_NONE. Linux only
774 * requires that 0.1% of your interrupts are handled, so this isn't
775 * a big problem.
776 */
82123460 777 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 778 return 0;
b60503ba 779
b80d5ccc 780 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 781 nvmeq->cq_head = head;
82123460 782 nvmeq->cq_phase = phase;
b60503ba 783
e9539f47
MW		 784 nvmeq->cqe_seen = 1;
785 return 1;
b60503ba
MW		 786}
787
7d822457
MW		 788static void nvme_make_request(struct request_queue *q, struct bio *bio)
789{
790 struct nvme_ns *ns = q->queuedata;
791 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
792 int result = -EBUSY;
793
cd638946
KB		 794 if (!nvmeq) {
795 put_nvmeq(NULL);
796 bio_endio(bio, -EIO);
797 return;
798 }
799
7d822457 800 spin_lock_irq(&nvmeq->q_lock);
22404274 801 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 802 result = nvme_submit_bio_queue(nvmeq, ns, bio);
803 if (unlikely(result)) {
edd10d33 804 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 805 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
806 bio_list_add(&nvmeq->sq_cong, bio);
807 }
808
809 nvme_process_cq(nvmeq);
810 spin_unlock_irq(&nvmeq->q_lock);
811 put_nvmeq(nvmeq);
812}
813
b60503ba 814static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 815{
816 irqreturn_t result;
817 struct nvme_queue *nvmeq = data;
818 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 819 nvme_process_cq(nvmeq);
820 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
821 nvmeq->cqe_seen = 0;
58ffacb5
MW		 822 spin_unlock(&nvmeq->q_lock);
823 return result;
824}
825
826static irqreturn_t nvme_irq_check(int irq, void *data)
827{
828 struct nvme_queue *nvmeq = data;
829 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
830 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
831 return IRQ_NONE;
832 return IRQ_WAKE_THREAD;
833}
834
3c0cf138
MW		 835static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
836{
837 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 838 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 839 spin_unlock_irq(&nvmeq->q_lock);
840}
841
c2f5b650
MW		 842struct sync_cmd_info {
843 struct task_struct *task;
844 u32 result;
845 int status;
846};
847
edd10d33 848static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 849 struct nvme_completion *cqe)
850{
851 struct sync_cmd_info *cmdinfo = ctx;
852 cmdinfo->result = le32_to_cpup(&cqe->result);
853 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
854 wake_up_process(cmdinfo->task);
855}
856
b60503ba
MW		 857/*
858 * Returns 0 on success. If the result is negative, it's a Linux error code;
859 * if the result is positive, it's an NVM Express status code
860 */
4f5099af
KB		 861static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
862 struct nvme_command *cmd,
5d0f6131 863 u32 *result, unsigned timeout)
b60503ba 864{
4f5099af 865 int cmdid, ret;
b60503ba 866 struct sync_cmd_info cmdinfo;
4f5099af
KB		 867 struct nvme_queue *nvmeq;
868
869 nvmeq = lock_nvmeq(dev, q_idx);
870 if (!nvmeq) {
871 unlock_nvmeq(nvmeq);
872 return -ENODEV;
873 }
b60503ba
MW		 874
875 cmdinfo.task = current;
876 cmdinfo.status = -EINTR;
877
4f5099af
KB		 878 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
879 if (cmdid < 0) {
880 unlock_nvmeq(nvmeq);
b60503ba 881 return cmdid;
4f5099af 882 }
b60503ba
MW		 883 cmd->common.command_id = cmdid;
884
3c0cf138 885 set_current_state(TASK_KILLABLE);
4f5099af
KB		 886 ret = nvme_submit_cmd(nvmeq, cmd);
887 if (ret) {
888 free_cmdid(nvmeq, cmdid, NULL);
889 unlock_nvmeq(nvmeq);
890 set_current_state(TASK_RUNNING);
891 return ret;
892 }
893 unlock_nvmeq(nvmeq);
78f8d257 894 schedule_timeout(timeout);
b60503ba 895
3c0cf138 896 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 897 nvmeq = lock_nvmeq(dev, q_idx);
898 if (nvmeq)
899 nvme_abort_command(nvmeq, cmdid);
900 unlock_nvmeq(nvmeq);
3c0cf138
MW		 901 return -EINTR;
902 }
903
b60503ba
MW		 904 if (result)
905 *result = cmdinfo.result;
906
907 return cmdinfo.status;
908}
909
4d115420
KB		 910static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
911 struct nvme_command *cmd,
912 struct async_cmd_info *cmdinfo, unsigned timeout)
913{
914 int cmdid;
915
916 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
917 if (cmdid < 0)
918 return cmdid;
919 cmdinfo->status = -EINTR;
920 cmd->common.command_id = cmdid;
4f5099af 921 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 922}
923
5d0f6131 924int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 925 u32 *result)
926{
4f5099af
KB		 927 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
928}
929
930int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
931 u32 *result)
932{
933 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
934 NVME_IO_TIMEOUT);
b60503ba
MW		 935}
936
4d115420
KB		 937static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
938 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
939{
5a92e700 940 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 941 ADMIN_TIMEOUT);
942}
943
b60503ba
MW		 944static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
945{
946 int status;
947 struct nvme_command c;
948
949 memset(&c, 0, sizeof(c));
950 c.delete_queue.opcode = opcode;
951 c.delete_queue.qid = cpu_to_le16(id);
952
953 status = nvme_submit_admin_cmd(dev, &c, NULL);
954 if (status)
955 return -EIO;
956 return 0;
957}
958
959static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
960 struct nvme_queue *nvmeq)
961{
962 int status;
963 struct nvme_command c;
964 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
965
966 memset(&c, 0, sizeof(c));
967 c.create_cq.opcode = nvme_admin_create_cq;
968 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
969 c.create_cq.cqid = cpu_to_le16(qid);
970 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
971 c.create_cq.cq_flags = cpu_to_le16(flags);
972 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
973
974 status = nvme_submit_admin_cmd(dev, &c, NULL);
975 if (status)
976 return -EIO;
977 return 0;
978}
979
980static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
981 struct nvme_queue *nvmeq)
982{
983 int status;
984 struct nvme_command c;
985 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
986
987 memset(&c, 0, sizeof(c));
988 c.create_sq.opcode = nvme_admin_create_sq;
989 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
990 c.create_sq.sqid = cpu_to_le16(qid);
991 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
992 c.create_sq.sq_flags = cpu_to_le16(flags);
993 c.create_sq.cqid = cpu_to_le16(qid);
994
995 status = nvme_submit_admin_cmd(dev, &c, NULL);
996 if (status)
997 return -EIO;
998 return 0;
999}
1000
1001static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1002{
1003 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1004}
1005
1006static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1007{
1008 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1009}
1010
5d0f6131 1011int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1012 dma_addr_t dma_addr)
1013{
1014 struct nvme_command c;
1015
1016 memset(&c, 0, sizeof(c));
1017 c.identify.opcode = nvme_admin_identify;
1018 c.identify.nsid = cpu_to_le32(nsid);
1019 c.identify.prp1 = cpu_to_le64(dma_addr);
1020 c.identify.cns = cpu_to_le32(cns);
1021
1022 return nvme_submit_admin_cmd(dev, &c, NULL);
1023}
1024
5d0f6131 1025int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1026 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1027{
1028 struct nvme_command c;
1029
1030 memset(&c, 0, sizeof(c));
1031 c.features.opcode = nvme_admin_get_features;
a42cecce 1032 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1033 c.features.prp1 = cpu_to_le64(dma_addr);
1034 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1035
08df1e05 1036 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1037}
1038
5d0f6131
VV		 1039int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1040 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1041{
1042 struct nvme_command c;
1043
1044 memset(&c, 0, sizeof(c));
1045 c.features.opcode = nvme_admin_set_features;
1046 c.features.prp1 = cpu_to_le64(dma_addr);
1047 c.features.fid = cpu_to_le32(fid);
1048 c.features.dword11 = cpu_to_le32(dword11);
1049
bc5fc7e4
MW		 1050 return nvme_submit_admin_cmd(dev, &c, result);
1051}
1052
c30341dc
KB		 1053/**
1054 * nvme_abort_cmd - Attempt aborting a command
1055 * @cmdid: Command id of a timed out IO
1056 * @queue: The queue with timed out IO
1057 *
1058 * Schedule controller reset if the command was already aborted once before and
1059 * still hasn't been returned to the driver, or if this is the admin queue.
1060 */
1061static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1062{
1063 int a_cmdid;
1064 struct nvme_command cmd;
1065 struct nvme_dev *dev = nvmeq->dev;
1066 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1067 struct nvme_queue *adminq;
c30341dc
KB		 1068
1069 if (!nvmeq->qid || info[cmdid].aborted) {
1070 if (work_busy(&dev->reset_work))
1071 return;
1072 list_del_init(&dev->node);
1073 dev_warn(&dev->pci_dev->dev,
1074 "I/O %d QID %d timeout, reset controller\n", cmdid,
1075 nvmeq->qid);
9ca97374 1076 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1077 queue_work(nvme_workq, &dev->reset_work);
1078 return;
1079 }
1080
1081 if (!dev->abort_limit)
1082 return;
1083
5a92e700
KB		 1084 adminq = rcu_dereference(dev->queues[0]);
1085 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1086 ADMIN_TIMEOUT);
1087 if (a_cmdid < 0)
1088 return;
1089
1090 memset(&cmd, 0, sizeof(cmd));
1091 cmd.abort.opcode = nvme_admin_abort_cmd;
1092 cmd.abort.cid = cmdid;
1093 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1094 cmd.abort.command_id = a_cmdid;
1095
1096 --dev->abort_limit;
1097 info[cmdid].aborted = 1;
1098 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1099
1100 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1101 nvmeq->qid);
5a92e700 1102 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1103}
1104
a09115b2
MW		 1105/**
1106 * nvme_cancel_ios - Cancel outstanding I/Os
1107 * @queue: The queue to cancel I/Os on
1108 * @timeout: True to only cancel I/Os which have timed out
1109 */
1110static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1111{
1112 int depth = nvmeq->q_depth - 1;
1113 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1114 unsigned long now = jiffies;
1115 int cmdid;
1116
1117 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1118 void *ctx;
1119 nvme_completion_fn fn;
1120 static struct nvme_completion cqe = {
af2d9ca7 1121 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1122 };
1123
1124 if (timeout && !time_after(now, info[cmdid].timeout))
1125 continue;
053ab702
KB		 1126 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1127 continue;
c30341dc
KB		 1128 if (timeout && nvmeq->dev->initialized) {
1129 nvme_abort_cmd(cmdid, nvmeq);
1130 continue;
1131 }
1132 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1133 nvmeq->qid);
a09115b2 1134 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1135 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1136 }
1137}
1138
5a92e700 1139static void nvme_free_queue(struct rcu_head *r)
9e866774 1140{
5a92e700
KB		 1141 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1142
22404274
KB		 1143 spin_lock_irq(&nvmeq->q_lock);
1144 while (bio_list_peek(&nvmeq->sq_cong)) {
1145 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1146 bio_endio(bio, -EIO);
1147 }
edd10d33
KB		 1148 while (!list_empty(&nvmeq->iod_bio)) {
1149 static struct nvme_completion cqe = {
1150 .status = cpu_to_le16(
1151 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1152 };
1153 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1154 struct nvme_iod,
1155 node);
1156 list_del(&iod->node);
1157 bio_completion(nvmeq, iod, &cqe);
1158 }
22404274
KB		 1159 spin_unlock_irq(&nvmeq->q_lock);
1160
9e866774
MW		 1161 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1162 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1163 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1164 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1165 if (nvmeq->qid)
1166 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1167 kfree(nvmeq);
1168}
1169
a1a5ef99 1170static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1171{
1172 int i;
1173
a1a5ef99 1174 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1175 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1176 rcu_assign_pointer(dev->queues[i], NULL);
1177 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1178 dev->queue_count--;
22404274
KB		 1179 }
1180}
1181
4d115420
KB		 1182/**
1183 * nvme_suspend_queue - put queue into suspended state
1184 * @nvmeq - queue to suspend
1185 *
1186 * Returns 1 if already suspended, 0 otherwise.
1187 */
1188static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1189{
4d115420 1190 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1191
a09115b2 1192 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1193 if (nvmeq->q_suspended) {
1194 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1195 return 1;
3295874b 1196 }
22404274 1197 nvmeq->q_suspended = 1;
42f61420 1198 nvmeq->dev->online_queues--;
a09115b2
MW		 1199 spin_unlock_irq(&nvmeq->q_lock);
1200
aba2080f
MW		 1201 irq_set_affinity_hint(vector, NULL);
1202 free_irq(vector, nvmeq);
b60503ba 1203
4d115420
KB		 1204 return 0;
1205}
b60503ba 1206
4d115420
KB		 1207static void nvme_clear_queue(struct nvme_queue *nvmeq)
1208{
22404274
KB		 1209 spin_lock_irq(&nvmeq->q_lock);
1210 nvme_process_cq(nvmeq);
1211 nvme_cancel_ios(nvmeq, false);
1212 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1213}
1214
4d115420
KB		 1215static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1216{
5a92e700 1217 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1218
1219 if (!nvmeq)
1220 return;
1221 if (nvme_suspend_queue(nvmeq))
1222 return;
1223
0e53d180
KB		 1224 /* Don't tell the adapter to delete the admin queue.
1225 * Don't tell a removed adapter to delete IO queues. */
1226 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1227 adapter_delete_sq(dev, qid);
1228 adapter_delete_cq(dev, qid);
1229 }
4d115420 1230 nvme_clear_queue(nvmeq);
b60503ba
MW		 1231}
1232
1233static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1234 int depth, int vector)
1235{
1236 struct device *dmadev = &dev->pci_dev->dev;
22404274 1237 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1238 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1239 if (!nvmeq)
1240 return NULL;
1241
1242 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1243 &nvmeq->cq_dma_addr, GFP_KERNEL);
1244 if (!nvmeq->cqes)
1245 goto free_nvmeq;
1246 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1247
1248 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1249 &nvmeq->sq_dma_addr, GFP_KERNEL);
1250 if (!nvmeq->sq_cmds)
1251 goto free_cqdma;
1252
42f61420
KB		 1253 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1254 goto free_sqdma;
1255
b60503ba 1256 nvmeq->q_dmadev = dmadev;
091b6092 1257 nvmeq->dev = dev;
3193f07b
MW		 1258 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1259 dev->instance, qid);
b60503ba
MW		 1260 spin_lock_init(&nvmeq->q_lock);
1261 nvmeq->cq_head = 0;
82123460 1262 nvmeq->cq_phase = 1;
b60503ba 1263 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1264 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1265 bio_list_init(&nvmeq->sq_cong);
edd10d33 1266 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1267 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1268 nvmeq->q_depth = depth;
1269 nvmeq->cq_vector = vector;
c30341dc 1270 nvmeq->qid = qid;
22404274
KB		 1271 nvmeq->q_suspended = 1;
1272 dev->queue_count++;
5a92e700 1273 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1274
1275 return nvmeq;
1276
42f61420
KB		 1277 free_sqdma:
1278 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1279 nvmeq->sq_dma_addr);
b60503ba 1280 free_cqdma:
68b8eca5 1281 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1282 nvmeq->cq_dma_addr);
1283 free_nvmeq:
1284 kfree(nvmeq);
1285 return NULL;
1286}
1287
3001082c
MW		 1288static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1289 const char *name)
1290{
58ffacb5
MW		 1291 if (use_threaded_interrupts)
1292 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1293 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1294 name, nvmeq);
3001082c 1295 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1296 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1297}
1298
22404274 1299static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1300{
22404274
KB		 1301 struct nvme_dev *dev = nvmeq->dev;
1302 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1303
22404274
KB		 1304 nvmeq->sq_tail = 0;
1305 nvmeq->cq_head = 0;
1306 nvmeq->cq_phase = 1;
b80d5ccc 1307 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1308 memset(nvmeq->cmdid_data, 0, extra);
1309 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1310 nvme_cancel_ios(nvmeq, false);
1311 nvmeq->q_suspended = 0;
42f61420 1312 dev->online_queues++;
22404274
KB		 1313}
1314
1315static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1316{
1317 struct nvme_dev *dev = nvmeq->dev;
1318 int result;
3f85d50b 1319
b60503ba
MW		 1320 result = adapter_alloc_cq(dev, qid, nvmeq);
1321 if (result < 0)
22404274 1322 return result;
b60503ba
MW		 1323
1324 result = adapter_alloc_sq(dev, qid, nvmeq);
1325 if (result < 0)
1326 goto release_cq;
1327
3193f07b 1328 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1329 if (result < 0)
1330 goto release_sq;
1331
0a8d44cb 1332 spin_lock_irq(&nvmeq->q_lock);
22404274 1333 nvme_init_queue(nvmeq, qid);
0a8d44cb 1334 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1335
1336 return result;
b60503ba
MW		 1337
1338 release_sq:
1339 adapter_delete_sq(dev, qid);
1340 release_cq:
1341 adapter_delete_cq(dev, qid);
22404274 1342 return result;
b60503ba
MW		 1343}
1344
ba47e386
MW		 1345static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1346{
1347 unsigned long timeout;
1348 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1349
1350 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1351
1352 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1353 msleep(100);
1354 if (fatal_signal_pending(current))
1355 return -EINTR;
1356 if (time_after(jiffies, timeout)) {
1357 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1358 "Device not ready; aborting %s\n", enabled ?
1359 "initialisation" : "reset");
ba47e386
MW		 1360 return -ENODEV;
1361 }
1362 }
1363
1364 return 0;
1365}
1366
1367/*
1368 * If the device has been passed off to us in an enabled state, just clear
1369 * the enabled bit. The spec says we should set the 'shutdown notification
1370 * bits', but doing so may cause the device to complete commands to the
1371 * admin queue ... and we don't know what memory that might be pointing at!
1372 */
1373static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1374{
44af146a
MW		 1375 u32 cc = readl(&dev->bar->cc);
1376
1377 if (cc & NVME_CC_ENABLE)
1378 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1379 return nvme_wait_ready(dev, cap, false);
1380}
1381
1382static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1383{
1384 return nvme_wait_ready(dev, cap, true);
1385}
1386
1894d8f1
KB		 1387static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1388{
1389 unsigned long timeout;
1390 u32 cc;
1391
1392 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1393 writel(cc, &dev->bar->cc);
1394
1395 timeout = 2 * HZ + jiffies;
1396 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1397 NVME_CSTS_SHST_CMPLT) {
1398 msleep(100);
1399 if (fatal_signal_pending(current))
1400 return -EINTR;
1401 if (time_after(jiffies, timeout)) {
1402 dev_err(&dev->pci_dev->dev,
1403 "Device shutdown incomplete; abort shutdown\n");
1404 return -ENODEV;
1405 }
1406 }
1407
1408 return 0;
1409}
1410
8d85fce7 1411static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1412{
ba47e386 1413 int result;
b60503ba 1414 u32 aqa;
ba47e386 1415 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1416 struct nvme_queue *nvmeq;
1417
ba47e386
MW		 1418 result = nvme_disable_ctrl(dev, cap);
1419 if (result < 0)
1420 return result;
b60503ba 1421
5a92e700 1422 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1423 if (!nvmeq) {
1424 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1425 if (!nvmeq)
1426 return -ENOMEM;
cd638946 1427 }
b60503ba
MW		 1428
1429 aqa = nvmeq->q_depth - 1;
1430 aqa |= aqa << 16;
1431
1432 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1433 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1434 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1435 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1436
1437 writel(aqa, &dev->bar->aqa);
1438 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1439 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1440 writel(dev->ctrl_config, &dev->bar->cc);
1441
ba47e386 1442 result = nvme_enable_ctrl(dev, cap);
025c557a 1443 if (result)
cd638946 1444 return result;
9e866774 1445
3193f07b 1446 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1447 if (result)
cd638946 1448 return result;
025c557a 1449
0a8d44cb 1450 spin_lock_irq(&nvmeq->q_lock);
22404274 1451 nvme_init_queue(nvmeq, 0);
0a8d44cb 1452 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1453 return result;
1454}
1455
5d0f6131 1456struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1457 unsigned long addr, unsigned length)
b60503ba 1458{
36c14ed9 1459 int i, err, count, nents, offset;
7fc3cdab
MW		 1460 struct scatterlist *sg;
1461 struct page **pages;
eca18b23 1462 struct nvme_iod *iod;
36c14ed9
MW		 1463
1464 if (addr & 3)
eca18b23 1465 return ERR_PTR(-EINVAL);
5460fc03 1466 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1467 return ERR_PTR(-EINVAL);
7fc3cdab 1468
36c14ed9 1469 offset = offset_in_page(addr);
7fc3cdab
MW		 1470 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1471 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1472 if (!pages)
1473 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1474
1475 err = get_user_pages_fast(addr, count, 1, pages);
1476 if (err < count) {
1477 count = err;
1478 err = -EFAULT;
1479 goto put_pages;
1480 }
7fc3cdab 1481
eca18b23
MW		 1482 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1483 sg = iod->sg;
36c14ed9 1484 sg_init_table(sg, count);
d0ba1e49
MW		 1485 for (i = 0; i < count; i++) {
1486 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1487 min_t(unsigned, length, PAGE_SIZE - offset),
1488 offset);
d0ba1e49
MW		 1489 length -= (PAGE_SIZE - offset);
1490 offset = 0;
7fc3cdab 1491 }
fe304c43 1492 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1493 iod->nents = count;
7fc3cdab
MW		 1494
1495 err = -ENOMEM;
1496 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1497 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1498 if (!nents)
eca18b23 1499 goto free_iod;
b60503ba 1500
7fc3cdab 1501 kfree(pages);
eca18b23 1502 return iod;
b60503ba 1503
eca18b23
MW		 1504 free_iod:
1505 kfree(iod);
7fc3cdab
MW		 1506 put_pages:
1507 for (i = 0; i < count; i++)
1508 put_page(pages[i]);
1509 kfree(pages);
eca18b23 1510 return ERR_PTR(err);
7fc3cdab 1511}
b60503ba 1512
5d0f6131 1513void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1514 struct nvme_iod *iod)
7fc3cdab 1515{
1c2ad9fa 1516 int i;
b60503ba 1517
1c2ad9fa
MW		 1518 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1519 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1520
1c2ad9fa
MW		 1521 for (i = 0; i < iod->nents; i++)
1522 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1523}
b60503ba 1524
a53295b6
MW		 1525static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1526{
1527 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1528 struct nvme_user_io io;
1529 struct nvme_command c;
f410c680
KB		 1530 unsigned length, meta_len;
1531 int status, i;
1532 struct nvme_iod *iod, *meta_iod = NULL;
1533 dma_addr_t meta_dma_addr;
1534 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1535
1536 if (copy_from_user(&io, uio, sizeof(io)))
1537 return -EFAULT;
6c7d4945 1538 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1539 meta_len = (io.nblocks + 1) * ns->ms;
1540
1541 if (meta_len && ((io.metadata & 3) || !io.metadata))
1542 return -EINVAL;
6c7d4945
MW		 1543
1544 switch (io.opcode) {
1545 case nvme_cmd_write:
1546 case nvme_cmd_read:
6bbf1acd 1547 case nvme_cmd_compare:
eca18b23 1548 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1549 break;
6c7d4945 1550 default:
6bbf1acd 1551 return -EINVAL;
6c7d4945
MW		 1552 }
1553
eca18b23
MW		 1554 if (IS_ERR(iod))
1555 return PTR_ERR(iod);
a53295b6
MW		 1556
1557 memset(&c, 0, sizeof(c));
1558 c.rw.opcode = io.opcode;
1559 c.rw.flags = io.flags;
6c7d4945 1560 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1561 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1562 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1563 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1564 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1565 c.rw.reftag = cpu_to_le32(io.reftag);
1566 c.rw.apptag = cpu_to_le16(io.apptag);
1567 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1568
1569 if (meta_len) {
1b56749e
KB		 1570 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1571 meta_len);
f410c680
KB		 1572 if (IS_ERR(meta_iod)) {
1573 status = PTR_ERR(meta_iod);
1574 meta_iod = NULL;
1575 goto unmap;
1576 }
1577
1578 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1579 &meta_dma_addr, GFP_KERNEL);
1580 if (!meta_mem) {
1581 status = -ENOMEM;
1582 goto unmap;
1583 }
1584
1585 if (io.opcode & 1) {
1586 int meta_offset = 0;
1587
1588 for (i = 0; i < meta_iod->nents; i++) {
1589 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1590 meta_iod->sg[i].offset;
1591 memcpy(meta_mem + meta_offset, meta,
1592 meta_iod->sg[i].length);
1593 kunmap_atomic(meta);
1594 meta_offset += meta_iod->sg[i].length;
1595 }
1596 }
1597
1598 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1599 }
1600
edd10d33
KB		 1601 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1602 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1603 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1604
b77954cb
MW		 1605 if (length != (io.nblocks + 1) << ns->lba_shift)
1606 status = -ENOMEM;
1607 else
4f5099af 1608 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1609
f410c680
KB		 1610 if (meta_len) {
1611 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1612 int meta_offset = 0;
1613
1614 for (i = 0; i < meta_iod->nents; i++) {
1615 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1616 meta_iod->sg[i].offset;
1617 memcpy(meta, meta_mem + meta_offset,
1618 meta_iod->sg[i].length);
1619 kunmap_atomic(meta);
1620 meta_offset += meta_iod->sg[i].length;
1621 }
1622 }
1623
1624 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1625 meta_dma_addr);
1626 }
1627
1628 unmap:
1c2ad9fa 1629 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1630 nvme_free_iod(dev, iod);
f410c680
KB		 1631
1632 if (meta_iod) {
1633 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1634 nvme_free_iod(dev, meta_iod);
1635 }
1636
a53295b6
MW		 1637 return status;
1638}
1639
50af8bae 1640static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1641 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1642{
6bbf1acd 1643 struct nvme_admin_cmd cmd;
6ee44cdc 1644 struct nvme_command c;
eca18b23 1645 int status, length;
c7d36ab8 1646 struct nvme_iod *uninitialized_var(iod);
94f370ca 1647 unsigned timeout;
6ee44cdc 1648
6bbf1acd
MW		 1649 if (!capable(CAP_SYS_ADMIN))
1650 return -EACCES;
1651 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1652 return -EFAULT;
6ee44cdc
MW		 1653
1654 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1655 c.common.opcode = cmd.opcode;
1656 c.common.flags = cmd.flags;
1657 c.common.nsid = cpu_to_le32(cmd.nsid);
1658 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1659 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1660 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1661 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1662 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1663 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1664 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1665 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1666
1667 length = cmd.data_len;
1668 if (cmd.data_len) {
49742188
MW		 1669 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1670 length);
eca18b23
MW		 1671 if (IS_ERR(iod))
1672 return PTR_ERR(iod);
edd10d33
KB		 1673 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1674 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1675 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1676 }
1677
94f370ca
KB		 1678 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1679 ADMIN_TIMEOUT;
6bbf1acd 1680 if (length != cmd.data_len)
b77954cb
MW		 1681 status = -ENOMEM;
1682 else
4f5099af 1683 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1684
6bbf1acd 1685 if (cmd.data_len) {
1c2ad9fa 1686 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1687 nvme_free_iod(dev, iod);
6bbf1acd 1688 }
f4f117f6 1689
cf90bc48 1690 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1691 sizeof(cmd.result)))
1692 status = -EFAULT;
1693
6ee44cdc
MW		 1694 return status;
1695}
1696
b60503ba
MW		 1697static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1698 unsigned long arg)
1699{
1700 struct nvme_ns *ns = bdev->bd_disk->private_data;
1701
1702 switch (cmd) {
6bbf1acd 1703 case NVME_IOCTL_ID:
c3bfe717 1704 force_successful_syscall_return();
6bbf1acd
MW		 1705 return ns->ns_id;
1706 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1707 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1708 case NVME_IOCTL_SUBMIT_IO:
1709 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1710 case SG_GET_VERSION_NUM:
1711 return nvme_sg_get_version_num((void __user *)arg);
1712 case SG_IO:
1713 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1714 default:
1715 return -ENOTTY;
1716 }
1717}
1718
320a3827
KB		 1719#ifdef CONFIG_COMPAT
1720static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1721 unsigned int cmd, unsigned long arg)
1722{
1723 struct nvme_ns *ns = bdev->bd_disk->private_data;
1724
1725 switch (cmd) {
1726 case SG_IO:
1727 return nvme_sg_io32(ns, arg);
1728 }
1729 return nvme_ioctl(bdev, mode, cmd, arg);
1730}
1731#else
1732#define nvme_compat_ioctl NULL
1733#endif
1734
9ac27090
KB		 1735static int nvme_open(struct block_device *bdev, fmode_t mode)
1736{
1737 struct nvme_ns *ns = bdev->bd_disk->private_data;
1738 struct nvme_dev *dev = ns->dev;
1739
1740 kref_get(&dev->kref);
1741 return 0;
1742}
1743
1744static void nvme_free_dev(struct kref *kref);
1745
1746static void nvme_release(struct gendisk *disk, fmode_t mode)
1747{
1748 struct nvme_ns *ns = disk->private_data;
1749 struct nvme_dev *dev = ns->dev;
1750
1751 kref_put(&dev->kref, nvme_free_dev);
1752}
1753
4cc09e2d
KB		 1754static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1755{
1756 /* some standard values */
1757 geo->heads = 1 << 6;
1758 geo->sectors = 1 << 5;
1759 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1760 return 0;
1761}
1762
b60503ba
MW		 1763static const struct block_device_operations nvme_fops = {
1764 .owner = THIS_MODULE,
1765 .ioctl = nvme_ioctl,
320a3827 1766 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1767 .open = nvme_open,
1768 .release = nvme_release,
4cc09e2d 1769 .getgeo = nvme_getgeo,
b60503ba
MW		 1770};
1771
edd10d33
KB		 1772static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1773{
1774 struct nvme_iod *iod, *next;
1775
1776 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1777 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1778 break;
1779 list_del(&iod->node);
1780 if (bio_list_empty(&nvmeq->sq_cong) &&
1781 list_empty(&nvmeq->iod_bio))
1782 remove_wait_queue(&nvmeq->sq_full,
1783 &nvmeq->sq_cong_wait);
1784 }
1785}
1786
1fa6aead
MW		 1787static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1788{
1789 while (bio_list_peek(&nvmeq->sq_cong)) {
1790 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1791 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1792
edd10d33
KB		 1793 if (bio_list_empty(&nvmeq->sq_cong) &&
1794 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1795 remove_wait_queue(&nvmeq->sq_full,
1796 &nvmeq->sq_cong_wait);
1fa6aead 1797 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1798 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1799 add_wait_queue(&nvmeq->sq_full,
1800 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1801 bio_list_add_head(&nvmeq->sq_cong, bio);
1802 break;
1803 }
1804 }
1805}
1806
1807static int nvme_kthread(void *data)
1808{
d4b4ff8e 1809 struct nvme_dev *dev, *next;
1fa6aead
MW		 1810
1811 while (!kthread_should_stop()) {
564a232c 1812 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1813 spin_lock(&dev_list_lock);
d4b4ff8e 1814 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1815 int i;
d4b4ff8e
KB		 1816 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1817 dev->initialized) {
1818 if (work_busy(&dev->reset_work))
1819 continue;
1820 list_del_init(&dev->node);
1821 dev_warn(&dev->pci_dev->dev,
1822 "Failed status, reset controller\n");
9ca97374 1823 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1824 queue_work(nvme_workq, &dev->reset_work);
1825 continue;
1826 }
5a92e700 1827 rcu_read_lock();
1fa6aead 1828 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1829 struct nvme_queue *nvmeq =
1830 rcu_dereference(dev->queues[i]);
740216fc
MW		 1831 if (!nvmeq)
1832 continue;
1fa6aead 1833 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1834 if (nvmeq->q_suspended)
1835 goto unlock;
bc57a0f7 1836 nvme_process_cq(nvmeq);
a09115b2 1837 nvme_cancel_ios(nvmeq, true);
1fa6aead 1838 nvme_resubmit_bios(nvmeq);
edd10d33 1839 nvme_resubmit_iods(nvmeq);
22404274 1840 unlock:
1fa6aead
MW		 1841 spin_unlock_irq(&nvmeq->q_lock);
1842 }
5a92e700 1843 rcu_read_unlock();
1fa6aead
MW		 1844 }
1845 spin_unlock(&dev_list_lock);
acb7aa0d 1846 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1847 }
1848 return 0;
1849}
1850
0e5e4f0e
KB		 1851static void nvme_config_discard(struct nvme_ns *ns)
1852{
1853 u32 logical_block_size = queue_logical_block_size(ns->queue);
1854 ns->queue->limits.discard_zeroes_data = 0;
1855 ns->queue->limits.discard_alignment = logical_block_size;
1856 ns->queue->limits.discard_granularity = logical_block_size;
1857 ns->queue->limits.max_discard_sectors = 0xffffffff;
1858 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1859}
1860
c3bfe717 1861static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1862 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1863{
1864 struct nvme_ns *ns;
1865 struct gendisk *disk;
1866 int lbaf;
1867
1868 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1869 return NULL;
1870
1871 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1872 if (!ns)
1873 return NULL;
1874 ns->queue = blk_alloc_queue(GFP_KERNEL);
1875 if (!ns->queue)
1876 goto out_free_ns;
4eeb9215
MW		 1877 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1878 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1879 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1880 blk_queue_make_request(ns->queue, nvme_make_request);
1881 ns->dev = dev;
1882 ns->queue->queuedata = ns;
1883
469071a3 1884 disk = alloc_disk(0);
b60503ba
MW		 1885 if (!disk)
1886 goto out_free_queue;
5aff9382 1887 ns->ns_id = nsid;
b60503ba
MW		 1888 ns->disk = disk;
1889 lbaf = id->flbas & 0xf;
1890 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1891 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1892 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1893 if (dev->max_hw_sectors)
1894 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1895
1896 disk->major = nvme_major;
469071a3 1897 disk->first_minor = 0;
b60503ba
MW		 1898 disk->fops = &nvme_fops;
1899 disk->private_data = ns;
1900 disk->queue = ns->queue;
388f037f 1901 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1902 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1903 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1904 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1905
0e5e4f0e
KB		 1906 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1907 nvme_config_discard(ns);
1908
b60503ba
MW		 1909 return ns;
1910
1911 out_free_queue:
1912 blk_cleanup_queue(ns->queue);
1913 out_free_ns:
1914 kfree(ns);
1915 return NULL;
1916}
1917
42f61420
KB		 1918static int nvme_find_closest_node(int node)
1919{
1920 int n, val, min_val = INT_MAX, best_node = node;
1921
1922 for_each_online_node(n) {
1923 if (n == node)
1924 continue;
1925 val = node_distance(node, n);
1926 if (val < min_val) {
1927 min_val = val;
1928 best_node = n;
1929 }
1930 }
1931 return best_node;
1932}
1933
1934static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1935 int count)
1936{
1937 int cpu;
1938 for_each_cpu(cpu, qmask) {
1939 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1940 break;
1941 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1942 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1943 }
1944}
1945
1946static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1947 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1948{
1949 int next_cpu;
1950 for_each_cpu(next_cpu, new_mask) {
1951 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1952 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1953 cpumask_and(mask, mask, unassigned_cpus);
1954 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1955 }
1956}
1957
1958static void nvme_create_io_queues(struct nvme_dev *dev)
1959{
1960 unsigned i, max;
1961
1962 max = min(dev->max_qid, num_online_cpus());
1963 for (i = dev->queue_count; i <= max; i++)
1964 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1965 break;
1966
1967 max = min(dev->queue_count - 1, num_online_cpus());
1968 for (i = dev->online_queues; i <= max; i++)
1969 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1970 break;
1971}
1972
1973/*
1974 * If there are fewer queues than online cpus, this will try to optimally
1975 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1976 * thread siblings, core, socket, closest node, then whatever else is
1977 * available.
1978 */
1979static void nvme_assign_io_queues(struct nvme_dev *dev)
1980{
1981 unsigned cpu, cpus_per_queue, queues, remainder, i;
1982 cpumask_var_t unassigned_cpus;
1983
1984 nvme_create_io_queues(dev);
1985
1986 queues = min(dev->online_queues - 1, num_online_cpus());
1987 if (!queues)
1988 return;
1989
1990 cpus_per_queue = num_online_cpus() / queues;
1991 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
1992
1993 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
1994 return;
1995
1996 cpumask_copy(unassigned_cpus, cpu_online_mask);
1997 cpu = cpumask_first(unassigned_cpus);
1998 for (i = 1; i <= queues; i++) {
1999 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2000 cpumask_t mask;
2001
2002 cpumask_clear(nvmeq->cpu_mask);
2003 if (!cpumask_weight(unassigned_cpus)) {
2004 unlock_nvmeq(nvmeq);
2005 break;
2006 }
2007
2008 mask = *get_cpu_mask(cpu);
2009 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2010 if (cpus_weight(mask) < cpus_per_queue)
2011 nvme_add_cpus(&mask, unassigned_cpus,
2012 topology_thread_cpumask(cpu),
2013 nvmeq, cpus_per_queue);
2014 if (cpus_weight(mask) < cpus_per_queue)
2015 nvme_add_cpus(&mask, unassigned_cpus,
2016 topology_core_cpumask(cpu),
2017 nvmeq, cpus_per_queue);
2018 if (cpus_weight(mask) < cpus_per_queue)
2019 nvme_add_cpus(&mask, unassigned_cpus,
2020 cpumask_of_node(cpu_to_node(cpu)),
2021 nvmeq, cpus_per_queue);
2022 if (cpus_weight(mask) < cpus_per_queue)
2023 nvme_add_cpus(&mask, unassigned_cpus,
2024 cpumask_of_node(
2025 nvme_find_closest_node(
2026 cpu_to_node(cpu))),
2027 nvmeq, cpus_per_queue);
2028 if (cpus_weight(mask) < cpus_per_queue)
2029 nvme_add_cpus(&mask, unassigned_cpus,
2030 unassigned_cpus,
2031 nvmeq, cpus_per_queue);
2032
2033 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2034 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2035 dev->instance, i);
2036
2037 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2038 nvmeq->cpu_mask);
2039 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2040 nvmeq->cpu_mask);
2041 cpu = cpumask_next(cpu, unassigned_cpus);
2042 if (remainder && !--remainder)
2043 cpus_per_queue++;
2044 unlock_nvmeq(nvmeq);
2045 }
2046 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2047 dev->instance);
2048 i = 0;
2049 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2050 for_each_cpu(cpu, unassigned_cpus)
2051 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2052 free_cpumask_var(unassigned_cpus);
2053}
2054
b3b06812 2055static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2056{
2057 int status;
2058 u32 result;
b3b06812 2059 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2060
df348139 2061 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2062 &result);
27e8166c
MW		 2063 if (status < 0)
2064 return status;
2065 if (status > 0) {
2066 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2067 status);
2068 return -EBUSY;
2069 }
b60503ba
MW		 2070 return min(result & 0xffff, result >> 16) + 1;
2071}
2072
9d713c2b
KB		 2073static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2074{
b80d5ccc 2075 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2076}
2077
33b1e95c
KB		 2078static int nvme_cpu_notify(struct notifier_block *self,
2079 unsigned long action, void *hcpu)
2080{
2081 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2082 switch (action) {
2083 case CPU_ONLINE:
2084 case CPU_DEAD:
2085 nvme_assign_io_queues(dev);
2086 break;
2087 }
2088 return NOTIFY_OK;
2089}
2090
8d85fce7 2091static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2092{
5a92e700 2093 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2094 struct pci_dev *pdev = dev->pci_dev;
42f61420 2095 int result, i, vecs, nr_io_queues, size;
b60503ba 2096
42f61420 2097 nr_io_queues = num_possible_cpus();
b348b7d5 2098 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2099 if (result < 0)
2100 return result;
b348b7d5
MW		 2101 if (result < nr_io_queues)
2102 nr_io_queues = result;
b60503ba 2103
9d713c2b
KB		 2104 size = db_bar_size(dev, nr_io_queues);
2105 if (size > 8192) {
f1938f6e 2106 iounmap(dev->bar);
9d713c2b
KB		 2107 do {
2108 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2109 if (dev->bar)
2110 break;
2111 if (!--nr_io_queues)
2112 return -ENOMEM;
2113 size = db_bar_size(dev, nr_io_queues);
2114 } while (1);
f1938f6e 2115 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2116 adminq->q_db = dev->dbs;
f1938f6e
MW		 2117 }
2118
9d713c2b 2119 /* Deregister the admin queue's interrupt */
3193f07b 2120 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2121
be577fab 2122 for (i = 0; i < nr_io_queues; i++)
1b23484b 2123 dev->entry[i].entry = i;
be577fab
AG		 2124 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2125 if (vecs < 0) {
2126 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2127 if (vecs < 0) {
2128 vecs = 1;
2129 } else {
2130 for (i = 0; i < vecs; i++)
2131 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2132 }
2133 }
2134
063a8096
MW		 2135 /*
2136 * Should investigate if there's a performance win from allocating
2137 * more queues than interrupt vectors; it might allow the submission
2138 * path to scale better, even if the receive path is limited by the
2139 * number of interrupts.
2140 */
2141 nr_io_queues = vecs;
42f61420 2142 dev->max_qid = nr_io_queues;
063a8096 2143
3193f07b 2144 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2145 if (result) {
3193f07b 2146 adminq->q_suspended = 1;
22404274 2147 goto free_queues;
9d713c2b 2148 }
1b23484b 2149
cd638946 2150 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2151 nvme_free_queues(dev, nr_io_queues + 1);
2152 nvme_assign_io_queues(dev);
9ecdc946 2153
33b1e95c
KB		 2154 dev->nb.notifier_call = &nvme_cpu_notify;
2155 result = register_hotcpu_notifier(&dev->nb);
2156 if (result)
2157 goto free_queues;
b60503ba 2158
22404274 2159 return 0;
b60503ba 2160
22404274 2161 free_queues:
a1a5ef99 2162 nvme_free_queues(dev, 1);
22404274 2163 return result;
b60503ba
MW		 2164}
2165
422ef0c7
MW		 2166/*
2167 * Return: error value if an error occurred setting up the queues or calling
2168 * Identify Device. 0 if these succeeded, even if adding some of the
2169 * namespaces failed. At the moment, these failures are silent. TBD which
2170 * failures should be reported.
2171 */
8d85fce7 2172static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2173{
68608c26 2174 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2175 int res;
2176 unsigned nn, i;
cbb6218f 2177 struct nvme_ns *ns;
51814232 2178 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2179 struct nvme_id_ns *id_ns;
2180 void *mem;
b60503ba 2181 dma_addr_t dma_addr;
159b67d7 2182 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2183
68608c26 2184 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2185 if (!mem)
2186 return -ENOMEM;
b60503ba 2187
bc5fc7e4 2188 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2189 if (res) {
27e8166c 2190 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2191 res = -EIO;
cbb6218f 2192 goto out;
b60503ba
MW		 2193 }
2194
bc5fc7e4 2195 ctrl = mem;
51814232 2196 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2197 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2198 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2199 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2200 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2201 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2202 if (ctrl->mdts)
8fc23e03 2203 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2204 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2205 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2206 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2207
bc5fc7e4 2208 id_ns = mem;
2b2c1896 2209 for (i = 1; i <= nn; i++) {
bc5fc7e4 2210 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2211 if (res)
2212 continue;
2213
bc5fc7e4 2214 if (id_ns->ncap == 0)
b60503ba
MW		 2215 continue;
2216
bc5fc7e4 2217 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2218 dma_addr + 4096, NULL);
b60503ba 2219 if (res)
12209036 2220 memset(mem + 4096, 0, 4096);
b60503ba 2221
bc5fc7e4 2222 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2223 if (ns)
2224 list_add_tail(&ns->list, &dev->namespaces);
2225 }
2226 list_for_each_entry(ns, &dev->namespaces, list)
2227 add_disk(ns->disk);
422ef0c7 2228 res = 0;
b60503ba 2229
bc5fc7e4 2230 out:
684f5c20 2231 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2232 return res;
2233}
2234
0877cb0d
KB		 2235static int nvme_dev_map(struct nvme_dev *dev)
2236{
42f61420 2237 u64 cap;
0877cb0d
KB		 2238 int bars, result = -ENOMEM;
2239 struct pci_dev *pdev = dev->pci_dev;
2240
2241 if (pci_enable_device_mem(pdev))
2242 return result;
2243
2244 dev->entry[0].vector = pdev->irq;
2245 pci_set_master(pdev);
2246 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2247 if (pci_request_selected_regions(pdev, bars, "nvme"))
2248 goto disable_pci;
2249
052d0efa
RK		 2250 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2251 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2252 goto disable;
0877cb0d 2253
0877cb0d
KB		 2254 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2255 if (!dev->bar)
2256 goto disable;
0e53d180
KB		 2257 if (readl(&dev->bar->csts) == -1) {
2258 result = -ENODEV;
2259 goto unmap;
2260 }
42f61420
KB		 2261 cap = readq(&dev->bar->cap);
2262 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2263 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2264 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2265
2266 return 0;
2267
0e53d180
KB		 2268 unmap:
2269 iounmap(dev->bar);
2270 dev->bar = NULL;
0877cb0d
KB		 2271 disable:
2272 pci_release_regions(pdev);
2273 disable_pci:
2274 pci_disable_device(pdev);
2275 return result;
2276}
2277
2278static void nvme_dev_unmap(struct nvme_dev *dev)
2279{
2280 if (dev->pci_dev->msi_enabled)
2281 pci_disable_msi(dev->pci_dev);
2282 else if (dev->pci_dev->msix_enabled)
2283 pci_disable_msix(dev->pci_dev);
2284
2285 if (dev->bar) {
2286 iounmap(dev->bar);
2287 dev->bar = NULL;
9a6b9458 2288 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2289 }
2290
0877cb0d
KB		 2291 if (pci_is_enabled(dev->pci_dev))
2292 pci_disable_device(dev->pci_dev);
2293}
2294
4d115420
KB		 2295struct nvme_delq_ctx {
2296 struct task_struct *waiter;
2297 struct kthread_worker *worker;
2298 atomic_t refcount;
2299};
2300
2301static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2302{
2303 dq->waiter = current;
2304 mb();
2305
2306 for (;;) {
2307 set_current_state(TASK_KILLABLE);
2308 if (!atomic_read(&dq->refcount))
2309 break;
2310 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2311 fatal_signal_pending(current)) {
2312 set_current_state(TASK_RUNNING);
2313
2314 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2315 nvme_disable_queue(dev, 0);
2316
2317 send_sig(SIGKILL, dq->worker->task, 1);
2318 flush_kthread_worker(dq->worker);
2319 return;
2320 }
2321 }
2322 set_current_state(TASK_RUNNING);
2323}
2324
2325static void nvme_put_dq(struct nvme_delq_ctx *dq)
2326{
2327 atomic_dec(&dq->refcount);
2328 if (dq->waiter)
2329 wake_up_process(dq->waiter);
2330}
2331
2332static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2333{
2334 atomic_inc(&dq->refcount);
2335 return dq;
2336}
2337
2338static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2339{
2340 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2341
2342 nvme_clear_queue(nvmeq);
2343 nvme_put_dq(dq);
2344}
2345
2346static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2347 kthread_work_func_t fn)
2348{
2349 struct nvme_command c;
2350
2351 memset(&c, 0, sizeof(c));
2352 c.delete_queue.opcode = opcode;
2353 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2354
2355 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2356 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2357}
2358
2359static void nvme_del_cq_work_handler(struct kthread_work *work)
2360{
2361 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2362 cmdinfo.work);
2363 nvme_del_queue_end(nvmeq);
2364}
2365
2366static int nvme_delete_cq(struct nvme_queue *nvmeq)
2367{
2368 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2369 nvme_del_cq_work_handler);
2370}
2371
2372static void nvme_del_sq_work_handler(struct kthread_work *work)
2373{
2374 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2375 cmdinfo.work);
2376 int status = nvmeq->cmdinfo.status;
2377
2378 if (!status)
2379 status = nvme_delete_cq(nvmeq);
2380 if (status)
2381 nvme_del_queue_end(nvmeq);
2382}
2383
2384static int nvme_delete_sq(struct nvme_queue *nvmeq)
2385{
2386 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2387 nvme_del_sq_work_handler);
2388}
2389
2390static void nvme_del_queue_start(struct kthread_work *work)
2391{
2392 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2393 cmdinfo.work);
2394 allow_signal(SIGKILL);
2395 if (nvme_delete_sq(nvmeq))
2396 nvme_del_queue_end(nvmeq);
2397}
2398
2399static void nvme_disable_io_queues(struct nvme_dev *dev)
2400{
2401 int i;
2402 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2403 struct nvme_delq_ctx dq;
2404 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2405 &worker, "nvme%d", dev->instance);
2406
2407 if (IS_ERR(kworker_task)) {
2408 dev_err(&dev->pci_dev->dev,
2409 "Failed to create queue del task\n");
2410 for (i = dev->queue_count - 1; i > 0; i--)
2411 nvme_disable_queue(dev, i);
2412 return;
2413 }
2414
2415 dq.waiter = NULL;
2416 atomic_set(&dq.refcount, 0);
2417 dq.worker = &worker;
2418 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2419 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2420
2421 if (nvme_suspend_queue(nvmeq))
2422 continue;
2423 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2424 nvmeq->cmdinfo.worker = dq.worker;
2425 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2426 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2427 }
2428 nvme_wait_dq(&dq, dev);
2429 kthread_stop(kworker_task);
2430}
2431
b9afca3e
DM		 2432/*
2433* Remove the node from the device list and check
2434* for whether or not we need to stop the nvme_thread.
2435*/
2436static void nvme_dev_list_remove(struct nvme_dev *dev)
2437{
2438 struct task_struct *tmp = NULL;
2439
2440 spin_lock(&dev_list_lock);
2441 list_del_init(&dev->node);
2442 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2443 tmp = nvme_thread;
2444 nvme_thread = NULL;
2445 }
2446 spin_unlock(&dev_list_lock);
2447
2448 if (tmp)
2449 kthread_stop(tmp);
2450}
2451
f0b50732 2452static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2453{
22404274
KB		 2454 int i;
2455
d4b4ff8e 2456 dev->initialized = 0;
33b1e95c 2457 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2458
b9afca3e 2459 nvme_dev_list_remove(dev);
1fa6aead 2460
4d115420
KB		 2461 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2462 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2463 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2464 nvme_suspend_queue(nvmeq);
2465 nvme_clear_queue(nvmeq);
2466 }
2467 } else {
2468 nvme_disable_io_queues(dev);
1894d8f1 2469 nvme_shutdown_ctrl(dev);
4d115420
KB		 2470 nvme_disable_queue(dev, 0);
2471 }
f0b50732
KB		 2472 nvme_dev_unmap(dev);
2473}
2474
2475static void nvme_dev_remove(struct nvme_dev *dev)
2476{
9ac27090 2477 struct nvme_ns *ns;
f0b50732 2478
9ac27090
KB		 2479 list_for_each_entry(ns, &dev->namespaces, list) {
2480 if (ns->disk->flags & GENHD_FL_UP)
2481 del_gendisk(ns->disk);
2482 if (!blk_queue_dying(ns->queue))
2483 blk_cleanup_queue(ns->queue);
b60503ba 2484 }
b60503ba
MW		 2485}
2486
091b6092
MW		 2487static int nvme_setup_prp_pools(struct nvme_dev *dev)
2488{
2489 struct device *dmadev = &dev->pci_dev->dev;
2490 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2491 PAGE_SIZE, PAGE_SIZE, 0);
2492 if (!dev->prp_page_pool)
2493 return -ENOMEM;
2494
99802a7a
MW		 2495 /* Optimisation for I/Os between 4k and 128k */
2496 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2497 256, 256, 0);
2498 if (!dev->prp_small_pool) {
2499 dma_pool_destroy(dev->prp_page_pool);
2500 return -ENOMEM;
2501 }
091b6092
MW		 2502 return 0;
2503}
2504
2505static void nvme_release_prp_pools(struct nvme_dev *dev)
2506{
2507 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2508 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2509}
2510
cd58ad7d
QSA		 2511static DEFINE_IDA(nvme_instance_ida);
2512
2513static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2514{
cd58ad7d
QSA		 2515 int instance, error;
2516
2517 do {
2518 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2519 return -ENODEV;
2520
2521 spin_lock(&dev_list_lock);
2522 error = ida_get_new(&nvme_instance_ida, &instance);
2523 spin_unlock(&dev_list_lock);
2524 } while (error == -EAGAIN);
2525
2526 if (error)
2527 return -ENODEV;
2528
2529 dev->instance = instance;
2530 return 0;
b60503ba
MW		 2531}
2532
2533static void nvme_release_instance(struct nvme_dev *dev)
2534{
cd58ad7d
QSA		 2535 spin_lock(&dev_list_lock);
2536 ida_remove(&nvme_instance_ida, dev->instance);
2537 spin_unlock(&dev_list_lock);
b60503ba
MW		 2538}
2539
9ac27090
KB		 2540static void nvme_free_namespaces(struct nvme_dev *dev)
2541{
2542 struct nvme_ns *ns, *next;
2543
2544 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2545 list_del(&ns->list);
2546 put_disk(ns->disk);
2547 kfree(ns);
2548 }
2549}
2550
5e82e952
KB		 2551static void nvme_free_dev(struct kref *kref)
2552{
2553 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2554
2555 nvme_free_namespaces(dev);
42f61420 2556 free_percpu(dev->io_queue);
5e82e952
KB		 2557 kfree(dev->queues);
2558 kfree(dev->entry);
2559 kfree(dev);
2560}
2561
2562static int nvme_dev_open(struct inode *inode, struct file *f)
2563{
2564 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2565 miscdev);
2566 kref_get(&dev->kref);
2567 f->private_data = dev;
2568 return 0;
2569}
2570
2571static int nvme_dev_release(struct inode *inode, struct file *f)
2572{
2573 struct nvme_dev *dev = f->private_data;
2574 kref_put(&dev->kref, nvme_free_dev);
2575 return 0;
2576}
2577
2578static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2579{
2580 struct nvme_dev *dev = f->private_data;
2581 switch (cmd) {
2582 case NVME_IOCTL_ADMIN_CMD:
2583 return nvme_user_admin_cmd(dev, (void __user *)arg);
2584 default:
2585 return -ENOTTY;
2586 }
2587}
2588
2589static const struct file_operations nvme_dev_fops = {
2590 .owner = THIS_MODULE,
2591 .open = nvme_dev_open,
2592 .release = nvme_dev_release,
2593 .unlocked_ioctl = nvme_dev_ioctl,
2594 .compat_ioctl = nvme_dev_ioctl,
2595};
2596
f0b50732
KB		 2597static int nvme_dev_start(struct nvme_dev *dev)
2598{
2599 int result;
b9afca3e 2600 bool start_thread = false;
f0b50732
KB		 2601
2602 result = nvme_dev_map(dev);
2603 if (result)
2604 return result;
2605
2606 result = nvme_configure_admin_queue(dev);
2607 if (result)
2608 goto unmap;
2609
2610 spin_lock(&dev_list_lock);
b9afca3e
DM		 2611 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2612 start_thread = true;
2613 nvme_thread = NULL;
2614 }
f0b50732
KB		 2615 list_add(&dev->node, &dev_list);
2616 spin_unlock(&dev_list_lock);
2617
b9afca3e
DM		 2618 if (start_thread) {
2619 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2620 wake_up(&nvme_kthread_wait);
2621 } else
2622 wait_event_killable(nvme_kthread_wait, nvme_thread);
2623
2624 if (IS_ERR_OR_NULL(nvme_thread)) {
2625 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2626 goto disable;
2627 }
2628
f0b50732 2629 result = nvme_setup_io_queues(dev);
d82e8bfd 2630 if (result && result != -EBUSY)
f0b50732
KB		 2631 goto disable;
2632
d82e8bfd 2633 return result;
f0b50732
KB		 2634
2635 disable:
a1a5ef99 2636 nvme_disable_queue(dev, 0);
b9afca3e 2637 nvme_dev_list_remove(dev);
f0b50732
KB		 2638 unmap:
2639 nvme_dev_unmap(dev);
2640 return result;
2641}
2642
9a6b9458
KB		 2643static int nvme_remove_dead_ctrl(void *arg)
2644{
2645 struct nvme_dev *dev = (struct nvme_dev *)arg;
2646 struct pci_dev *pdev = dev->pci_dev;
2647
2648 if (pci_get_drvdata(pdev))
2649 pci_stop_and_remove_bus_device(pdev);
2650 kref_put(&dev->kref, nvme_free_dev);
2651 return 0;
2652}
2653
2654static void nvme_remove_disks(struct work_struct *ws)
2655{
9a6b9458
KB		 2656 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2657
2658 nvme_dev_remove(dev);
5a92e700 2659 nvme_free_queues(dev, 1);
9a6b9458
KB		 2660}
2661
2662static int nvme_dev_resume(struct nvme_dev *dev)
2663{
2664 int ret;
2665
2666 ret = nvme_dev_start(dev);
2667 if (ret && ret != -EBUSY)
2668 return ret;
2669 if (ret == -EBUSY) {
2670 spin_lock(&dev_list_lock);
9ca97374 2671 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2672 queue_work(nvme_workq, &dev->reset_work);
2673 spin_unlock(&dev_list_lock);
2674 }
d4b4ff8e 2675 dev->initialized = 1;
9a6b9458
KB		 2676 return 0;
2677}
2678
2679static void nvme_dev_reset(struct nvme_dev *dev)
2680{
2681 nvme_dev_shutdown(dev);
2682 if (nvme_dev_resume(dev)) {
2683 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2684 kref_get(&dev->kref);
2685 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2686 dev->instance))) {
2687 dev_err(&dev->pci_dev->dev,
2688 "Failed to start controller remove task\n");
2689 kref_put(&dev->kref, nvme_free_dev);
2690 }
2691 }
2692}
2693
2694static void nvme_reset_failed_dev(struct work_struct *ws)
2695{
2696 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2697 nvme_dev_reset(dev);
2698}
2699
9ca97374
TH		 2700static void nvme_reset_workfn(struct work_struct *work)
2701{
2702 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2703 dev->reset_workfn(work);
2704}
2705
8d85fce7 2706static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2707{
0877cb0d 2708 int result = -ENOMEM;
b60503ba
MW		 2709 struct nvme_dev *dev;
2710
2711 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2712 if (!dev)
2713 return -ENOMEM;
2714 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2715 GFP_KERNEL);
2716 if (!dev->entry)
2717 goto free;
1b23484b
MW		 2718 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2719 GFP_KERNEL);
b60503ba
MW		 2720 if (!dev->queues)
2721 goto free;
42f61420
KB		 2722 dev->io_queue = alloc_percpu(unsigned short);
2723 if (!dev->io_queue)
2724 goto free;
b60503ba
MW		 2725
2726 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2727 dev->reset_workfn = nvme_reset_failed_dev;
2728 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
b60503ba 2729 dev->pci_dev = pdev;
9a6b9458 2730 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2731 result = nvme_set_instance(dev);
2732 if (result)
0877cb0d 2733 goto free;
b60503ba 2734
091b6092
MW		 2735 result = nvme_setup_prp_pools(dev);
2736 if (result)
0877cb0d 2737 goto release;
091b6092 2738
fb35e914 2739 kref_init(&dev->kref);
f0b50732 2740 result = nvme_dev_start(dev);
d82e8bfd
KB		 2741 if (result) {
2742 if (result == -EBUSY)
2743 goto create_cdev;
0877cb0d 2744 goto release_pools;
d82e8bfd 2745 }
b60503ba 2746
740216fc 2747 result = nvme_dev_add(dev);
d82e8bfd 2748 if (result)
f0b50732 2749 goto shutdown;
740216fc 2750
d82e8bfd 2751 create_cdev:
5e82e952
KB		 2752 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2753 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2754 dev->miscdev.parent = &pdev->dev;
2755 dev->miscdev.name = dev->name;
2756 dev->miscdev.fops = &nvme_dev_fops;
2757 result = misc_register(&dev->miscdev);
2758 if (result)
2759 goto remove;
2760
d4b4ff8e 2761 dev->initialized = 1;
b60503ba
MW		 2762 return 0;
2763
5e82e952
KB		 2764 remove:
2765 nvme_dev_remove(dev);
9ac27090 2766 nvme_free_namespaces(dev);
f0b50732
KB		 2767 shutdown:
2768 nvme_dev_shutdown(dev);
0877cb0d 2769 release_pools:
a1a5ef99 2770 nvme_free_queues(dev, 0);
091b6092 2771 nvme_release_prp_pools(dev);
0877cb0d
KB		 2772 release:
2773 nvme_release_instance(dev);
b60503ba 2774 free:
42f61420 2775 free_percpu(dev->io_queue);
b60503ba
MW		 2776 kfree(dev->queues);
2777 kfree(dev->entry);
2778 kfree(dev);
2779 return result;
2780}
2781
09ece142
KB		 2782static void nvme_shutdown(struct pci_dev *pdev)
2783{
2784 struct nvme_dev *dev = pci_get_drvdata(pdev);
2785 nvme_dev_shutdown(dev);
2786}
2787
8d85fce7 2788static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2789{
2790 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2791
2792 spin_lock(&dev_list_lock);
2793 list_del_init(&dev->node);
2794 spin_unlock(&dev_list_lock);
2795
2796 pci_set_drvdata(pdev, NULL);
2797 flush_work(&dev->reset_work);
5e82e952 2798 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2799 nvme_dev_remove(dev);
2800 nvme_dev_shutdown(dev);
a1a5ef99 2801 nvme_free_queues(dev, 0);
5a92e700 2802 rcu_barrier();
9a6b9458
KB		 2803 nvme_release_instance(dev);
2804 nvme_release_prp_pools(dev);
5e82e952 2805 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2806}
2807
2808/* These functions are yet to be implemented */
2809#define nvme_error_detected NULL
2810#define nvme_dump_registers NULL
2811#define nvme_link_reset NULL
2812#define nvme_slot_reset NULL
2813#define nvme_error_resume NULL
cd638946 2814
671a6018 2815#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2816static int nvme_suspend(struct device *dev)
2817{
2818 struct pci_dev *pdev = to_pci_dev(dev);
2819 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2820
2821 nvme_dev_shutdown(ndev);
2822 return 0;
2823}
2824
2825static int nvme_resume(struct device *dev)
2826{
2827 struct pci_dev *pdev = to_pci_dev(dev);
2828 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2829
9a6b9458 2830 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2831 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2832 queue_work(nvme_workq, &ndev->reset_work);
2833 }
2834 return 0;
cd638946 2835}
671a6018 2836#endif
cd638946
KB		 2837
2838static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2839
1d352035 2840static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2841 .error_detected = nvme_error_detected,
2842 .mmio_enabled = nvme_dump_registers,
2843 .link_reset = nvme_link_reset,
2844 .slot_reset = nvme_slot_reset,
2845 .resume = nvme_error_resume,
2846};
2847
2848/* Move to pci_ids.h later */
2849#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2850
6eb0d698 2851static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2852 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2853 { 0, }
2854};
2855MODULE_DEVICE_TABLE(pci, nvme_id_table);
2856
2857static struct pci_driver nvme_driver = {
2858 .name = "nvme",
2859 .id_table = nvme_id_table,
2860 .probe = nvme_probe,
8d85fce7 2861 .remove = nvme_remove,
09ece142 2862 .shutdown = nvme_shutdown,
cd638946
KB		 2863 .driver = {
2864 .pm = &nvme_dev_pm_ops,
2865 },
b60503ba
MW		 2866 .err_handler = &nvme_err_handler,
2867};
2868
2869static int __init nvme_init(void)
2870{
0ac13140 2871 int result;
1fa6aead 2872
b9afca3e 2873 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2874
9a6b9458
KB		 2875 nvme_workq = create_singlethread_workqueue("nvme");
2876 if (!nvme_workq)
b9afca3e 2877 return -ENOMEM;
9a6b9458 2878
5c42ea16
KB		 2879 result = register_blkdev(nvme_major, "nvme");
2880 if (result < 0)
9a6b9458 2881 goto kill_workq;
5c42ea16 2882 else if (result > 0)
0ac13140 2883 nvme_major = result;
b60503ba
MW		 2884
2885 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2886 if (result)
2887 goto unregister_blkdev;
2888 return 0;
b60503ba 2889
1fa6aead 2890 unregister_blkdev:
b60503ba 2891 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2892 kill_workq:
2893 destroy_workqueue(nvme_workq);
b60503ba
MW		 2894 return result;
2895}
2896
2897static void __exit nvme_exit(void)
2898{
2899 pci_unregister_driver(&nvme_driver);
2900 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2901 destroy_workqueue(nvme_workq);
b9afca3e 2902 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
b60503ba
MW		 2903}
2904
2905MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2906MODULE_LICENSE("GPL");
6eb0d698 2907MODULE_VERSION("0.9");
b60503ba
MW		 2908module_init(nvme_init);
2909module_exit(nvme_exit);
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