]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
e6017571 | 31 | #include <linux/sched/clock.h> |
760285e7 | 32 | #include <drm/i915_drm.h> |
80824003 | 33 | #include "i915_drv.h" |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_crtc_helper.h> | |
9338203c | 36 | #include <drm/drm_encoder.h> |
760285e7 | 37 | #include <drm/drm_fb_helper.h> |
b1ba124d | 38 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 39 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 40 | #include <drm/drm_rect.h> |
10f81c19 | 41 | #include <drm/drm_atomic.h> |
913d8d11 | 42 | |
1d5bfac9 DV |
43 | /** |
44 | * _wait_for - magic (register) wait macro | |
45 | * | |
46 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
47 | * contexts. Note that it's important that we check the condition again after | |
48 | * having timed out, since the timeout could be due to preemption or similar and | |
49 | * we've never had a chance to check the condition before the timeout. | |
0351b939 TU |
50 | * |
51 | * TODO: When modesetting has fully transitioned to atomic, the below | |
52 | * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts | |
53 | * added. | |
1d5bfac9 | 54 | */ |
3f177625 TU |
55 | #define _wait_for(COND, US, W) ({ \ |
56 | unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ | |
b0876afd DG |
57 | int ret__; \ |
58 | for (;;) { \ | |
59 | bool expired__ = time_after(jiffies, timeout__); \ | |
60 | if (COND) { \ | |
61 | ret__ = 0; \ | |
62 | break; \ | |
63 | } \ | |
64 | if (expired__) { \ | |
65 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
66 | break; \ |
67 | } \ | |
9848de08 | 68 | if ((W) && drm_can_sleep()) { \ |
3f177625 | 69 | usleep_range((W), (W)*2); \ |
0cc2764c BW |
70 | } else { \ |
71 | cpu_relax(); \ | |
72 | } \ | |
913d8d11 CW |
73 | } \ |
74 | ret__; \ | |
75 | }) | |
76 | ||
3f177625 | 77 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) |
3f177625 | 78 | |
0351b939 TU |
79 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
80 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
18f4b843 | 81 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic()) |
0351b939 | 82 | #else |
18f4b843 | 83 | # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0) |
0351b939 TU |
84 | #endif |
85 | ||
18f4b843 TU |
86 | #define _wait_for_atomic(COND, US, ATOMIC) \ |
87 | ({ \ | |
88 | int cpu, ret, timeout = (US) * 1000; \ | |
89 | u64 base; \ | |
90 | _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \ | |
0351b939 | 91 | BUILD_BUG_ON((US) > 50000); \ |
18f4b843 TU |
92 | if (!(ATOMIC)) { \ |
93 | preempt_disable(); \ | |
94 | cpu = smp_processor_id(); \ | |
95 | } \ | |
96 | base = local_clock(); \ | |
97 | for (;;) { \ | |
98 | u64 now = local_clock(); \ | |
99 | if (!(ATOMIC)) \ | |
100 | preempt_enable(); \ | |
101 | if (COND) { \ | |
102 | ret = 0; \ | |
103 | break; \ | |
104 | } \ | |
105 | if (now - base >= timeout) { \ | |
106 | ret = -ETIMEDOUT; \ | |
0351b939 TU |
107 | break; \ |
108 | } \ | |
109 | cpu_relax(); \ | |
18f4b843 TU |
110 | if (!(ATOMIC)) { \ |
111 | preempt_disable(); \ | |
112 | if (unlikely(cpu != smp_processor_id())) { \ | |
113 | timeout -= now - base; \ | |
114 | cpu = smp_processor_id(); \ | |
115 | base = local_clock(); \ | |
116 | } \ | |
117 | } \ | |
0351b939 | 118 | } \ |
18f4b843 TU |
119 | ret; \ |
120 | }) | |
121 | ||
122 | #define wait_for_us(COND, US) \ | |
123 | ({ \ | |
124 | int ret__; \ | |
125 | BUILD_BUG_ON(!__builtin_constant_p(US)); \ | |
126 | if ((US) > 10) \ | |
127 | ret__ = _wait_for((COND), (US), 10); \ | |
128 | else \ | |
129 | ret__ = _wait_for_atomic((COND), (US), 0); \ | |
0351b939 TU |
130 | ret__; \ |
131 | }) | |
132 | ||
18f4b843 TU |
133 | #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1) |
134 | #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1) | |
481b6af3 | 135 | |
49938ac4 JN |
136 | #define KHz(x) (1000 * (x)) |
137 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 138 | |
79e53945 JB |
139 | /* |
140 | * Display related stuff | |
141 | */ | |
142 | ||
143 | /* store information about an Ixxx DVO */ | |
144 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
145 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
146 | #define MAX_OUTPUTS 6 | |
147 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 148 | |
4726e0b0 SK |
149 | /* Maximum cursor sizes */ |
150 | #define GEN2_CURSOR_WIDTH 64 | |
151 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
152 | #define MAX_CURSOR_WIDTH 256 |
153 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 154 | |
79e53945 JB |
155 | #define INTEL_I2C_BUS_DVO 1 |
156 | #define INTEL_I2C_BUS_SDVO 2 | |
157 | ||
158 | /* these are outputs from the chip - integrated only | |
159 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
160 | enum intel_output_type { |
161 | INTEL_OUTPUT_UNUSED = 0, | |
162 | INTEL_OUTPUT_ANALOG = 1, | |
163 | INTEL_OUTPUT_DVO = 2, | |
164 | INTEL_OUTPUT_SDVO = 3, | |
165 | INTEL_OUTPUT_LVDS = 4, | |
166 | INTEL_OUTPUT_TVOUT = 5, | |
167 | INTEL_OUTPUT_HDMI = 6, | |
cca0502b | 168 | INTEL_OUTPUT_DP = 7, |
6847d71b PZ |
169 | INTEL_OUTPUT_EDP = 8, |
170 | INTEL_OUTPUT_DSI = 9, | |
171 | INTEL_OUTPUT_UNKNOWN = 10, | |
172 | INTEL_OUTPUT_DP_MST = 11, | |
173 | }; | |
79e53945 JB |
174 | |
175 | #define INTEL_DVO_CHIP_NONE 0 | |
176 | #define INTEL_DVO_CHIP_LVDS 1 | |
177 | #define INTEL_DVO_CHIP_TMDS 2 | |
178 | #define INTEL_DVO_CHIP_TVOUT 4 | |
179 | ||
dfba2e2d SK |
180 | #define INTEL_DSI_VIDEO_MODE 0 |
181 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 182 | |
79e53945 JB |
183 | struct intel_framebuffer { |
184 | struct drm_framebuffer base; | |
05394f39 | 185 | struct drm_i915_gem_object *obj; |
2d7a215f | 186 | struct intel_rotation_info rot_info; |
6687c906 VS |
187 | |
188 | /* for each plane in the normal GTT view */ | |
189 | struct { | |
190 | unsigned int x, y; | |
191 | } normal[2]; | |
192 | /* for each plane in the rotated GTT view */ | |
193 | struct { | |
194 | unsigned int x, y; | |
195 | unsigned int pitch; /* pixels */ | |
196 | } rotated[2]; | |
79e53945 JB |
197 | }; |
198 | ||
37811fcc CW |
199 | struct intel_fbdev { |
200 | struct drm_fb_helper helper; | |
8bcd4553 | 201 | struct intel_framebuffer *fb; |
058d88c4 | 202 | struct i915_vma *vma; |
43cee314 | 203 | async_cookie_t cookie; |
d978ef14 | 204 | int preferred_bpp; |
37811fcc | 205 | }; |
79e53945 | 206 | |
21d40d37 | 207 | struct intel_encoder { |
4ef69c7a | 208 | struct drm_encoder base; |
9a935856 | 209 | |
6847d71b | 210 | enum intel_output_type type; |
03cdc1d4 | 211 | enum port port; |
bc079e8b | 212 | unsigned int cloneable; |
21d40d37 | 213 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 | 214 | bool (*compute_config)(struct intel_encoder *, |
0a478c27 ML |
215 | struct intel_crtc_state *, |
216 | struct drm_connector_state *); | |
fd6bbda9 ML |
217 | void (*pre_pll_enable)(struct intel_encoder *, |
218 | struct intel_crtc_state *, | |
219 | struct drm_connector_state *); | |
220 | void (*pre_enable)(struct intel_encoder *, | |
221 | struct intel_crtc_state *, | |
222 | struct drm_connector_state *); | |
223 | void (*enable)(struct intel_encoder *, | |
224 | struct intel_crtc_state *, | |
225 | struct drm_connector_state *); | |
226 | void (*disable)(struct intel_encoder *, | |
227 | struct intel_crtc_state *, | |
228 | struct drm_connector_state *); | |
229 | void (*post_disable)(struct intel_encoder *, | |
230 | struct intel_crtc_state *, | |
231 | struct drm_connector_state *); | |
232 | void (*post_pll_disable)(struct intel_encoder *, | |
233 | struct intel_crtc_state *, | |
234 | struct drm_connector_state *); | |
f0947c37 DV |
235 | /* Read out the current hw state of this connector, returning true if |
236 | * the encoder is active. If the encoder is enabled it also set the pipe | |
237 | * it is connected to in the pipe parameter. */ | |
238 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 239 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 240 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
241 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
242 | * be set correctly before calling this function. */ | |
045ac3b5 | 243 | void (*get_config)(struct intel_encoder *, |
5cec258b | 244 | struct intel_crtc_state *pipe_config); |
62b69566 ACO |
245 | /* Returns a mask of power domains that need to be referenced as part |
246 | * of the hardware state readout code. */ | |
247 | u64 (*get_power_domains)(struct intel_encoder *encoder); | |
07f9cd0b ID |
248 | /* |
249 | * Called during system suspend after all pending requests for the | |
250 | * encoder are flushed (for example for DP AUX transactions) and | |
251 | * device interrupts are disabled. | |
252 | */ | |
253 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 254 | int crtc_mask; |
1d843f9d | 255 | enum hpd_pin hpd_pin; |
79f255a0 | 256 | enum intel_display_power_domain power_domain; |
f1a3acea PD |
257 | /* for communication with audio component; protected by av_mutex */ |
258 | const struct drm_connector *audio_connector; | |
79e53945 JB |
259 | }; |
260 | ||
1d508706 | 261 | struct intel_panel { |
dd06f90e | 262 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 263 | struct drm_display_mode *downclock_mode; |
4d891523 | 264 | int fitting_mode; |
58c68779 JN |
265 | |
266 | /* backlight */ | |
267 | struct { | |
c91c9f32 | 268 | bool present; |
58c68779 | 269 | u32 level; |
6dda730e | 270 | u32 min; |
7bd688cd | 271 | u32 max; |
58c68779 | 272 | bool enabled; |
636baebf JN |
273 | bool combination_mode; /* gen 2/4 only */ |
274 | bool active_low_pwm; | |
32b421e7 | 275 | bool alternate_pwm_increment; /* lpt+ */ |
b029e66f SK |
276 | |
277 | /* PWM chip */ | |
022e4e52 SK |
278 | bool util_pin_active_low; /* bxt+ */ |
279 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
280 | struct pwm_device *pwm; |
281 | ||
58c68779 | 282 | struct backlight_device *device; |
ab656bb9 | 283 | |
5507faeb JN |
284 | /* Connector and platform specific backlight functions */ |
285 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
286 | uint32_t (*get)(struct intel_connector *connector); | |
287 | void (*set)(struct intel_connector *connector, uint32_t level); | |
288 | void (*disable)(struct intel_connector *connector); | |
289 | void (*enable)(struct intel_connector *connector); | |
290 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, | |
291 | uint32_t hz); | |
292 | void (*power)(struct intel_connector *, bool enable); | |
293 | } backlight; | |
1d508706 JN |
294 | }; |
295 | ||
5daa55eb ZW |
296 | struct intel_connector { |
297 | struct drm_connector base; | |
9a935856 DV |
298 | /* |
299 | * The fixed encoder this connector is connected to. | |
300 | */ | |
df0e9248 | 301 | struct intel_encoder *encoder; |
9a935856 | 302 | |
8e1b56a4 JN |
303 | /* ACPI device id for ACPI and driver cooperation */ |
304 | u32 acpi_device_id; | |
305 | ||
f0947c37 DV |
306 | /* Reads out the current hw, returning true if the connector is enabled |
307 | * and active (i.e. dpms ON state). */ | |
308 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
309 | |
310 | /* Panel info for eDP and LVDS */ | |
311 | struct intel_panel panel; | |
9cd300e0 JN |
312 | |
313 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
314 | struct edid *edid; | |
beb60608 | 315 | struct edid *detect_edid; |
821450c6 EE |
316 | |
317 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
318 | state of connector->polled in case hotplug storm detection changes it */ | |
319 | u8 polled; | |
0e32b39c DA |
320 | |
321 | void *port; /* store this opaque as its illegal to dereference it */ | |
322 | ||
323 | struct intel_dp *mst_port; | |
5daa55eb ZW |
324 | }; |
325 | ||
9e2c8475 | 326 | struct dpll { |
80ad9206 VS |
327 | /* given values */ |
328 | int n; | |
329 | int m1, m2; | |
330 | int p1, p2; | |
331 | /* derived values */ | |
332 | int dot; | |
333 | int vco; | |
334 | int m; | |
335 | int p; | |
9e2c8475 | 336 | }; |
80ad9206 | 337 | |
de419ab6 ML |
338 | struct intel_atomic_state { |
339 | struct drm_atomic_state base; | |
340 | ||
bb0f4aab VS |
341 | struct { |
342 | /* | |
343 | * Logical state of cdclk (used for all scaling, watermark, | |
344 | * etc. calculations and checks). This is computed as if all | |
345 | * enabled crtcs were active. | |
346 | */ | |
347 | struct intel_cdclk_state logical; | |
348 | ||
349 | /* | |
350 | * Actual state of cdclk, can be different from the logical | |
351 | * state only when all crtc's are DPMS off. | |
352 | */ | |
353 | struct intel_cdclk_state actual; | |
354 | } cdclk; | |
1a617b77 | 355 | |
565602d7 ML |
356 | bool dpll_set, modeset; |
357 | ||
8b4a7d05 MR |
358 | /* |
359 | * Does this transaction change the pipes that are active? This mask | |
360 | * tracks which CRTC's have changed their active state at the end of | |
361 | * the transaction (not counting the temporary disable during modesets). | |
362 | * This mask should only be non-zero when intel_state->modeset is true, | |
363 | * but the converse is not necessarily true; simply changing a mode may | |
364 | * not flip the final active status of any CRTC's | |
365 | */ | |
366 | unsigned int active_pipe_changes; | |
367 | ||
565602d7 ML |
368 | unsigned int active_crtcs; |
369 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
370 | ||
2c42e535 | 371 | struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; |
ed4a6a7c MR |
372 | |
373 | /* | |
374 | * Current watermarks can't be trusted during hardware readout, so | |
375 | * don't bother calculating intermediate watermarks. | |
376 | */ | |
377 | bool skip_intermediate_wm; | |
98d39494 MR |
378 | |
379 | /* Gen9+ only */ | |
734fa01f | 380 | struct skl_wm_values wm_results; |
c004a90b CW |
381 | |
382 | struct i915_sw_fence commit_ready; | |
eb955eee CW |
383 | |
384 | struct llist_node freed; | |
de419ab6 ML |
385 | }; |
386 | ||
eeca778a | 387 | struct intel_plane_state { |
2b875c22 | 388 | struct drm_plane_state base; |
eeca778a | 389 | struct drm_rect clip; |
be1e3415 | 390 | struct i915_vma *vma; |
32b7eeec | 391 | |
b63a16f6 VS |
392 | struct { |
393 | u32 offset; | |
394 | int x, y; | |
395 | } main; | |
8d970654 VS |
396 | struct { |
397 | u32 offset; | |
398 | int x, y; | |
399 | } aux; | |
b63a16f6 | 400 | |
a0864d59 VS |
401 | /* plane control register */ |
402 | u32 ctl; | |
403 | ||
be41e336 CK |
404 | /* |
405 | * scaler_id | |
406 | * = -1 : not using a scaler | |
407 | * >= 0 : using a scalers | |
408 | * | |
409 | * plane requiring a scaler: | |
410 | * - During check_plane, its bit is set in | |
411 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 412 | * update_scaler_plane. |
be41e336 CK |
413 | * - scaler_id indicates the scaler it got assigned. |
414 | * | |
415 | * plane doesn't require a scaler: | |
416 | * - this can happen when scaling is no more required or plane simply | |
417 | * got disabled. | |
418 | * - During check_plane, corresponding bit is reset in | |
419 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 420 | * update_scaler_plane. |
be41e336 CK |
421 | */ |
422 | int scaler_id; | |
818ed961 ML |
423 | |
424 | struct drm_intel_sprite_colorkey ckey; | |
eeca778a GP |
425 | }; |
426 | ||
5724dbd1 | 427 | struct intel_initial_plane_config { |
2d14030b | 428 | struct intel_framebuffer *fb; |
49af449b | 429 | unsigned int tiling; |
46f297fb JB |
430 | int size; |
431 | u32 base; | |
432 | }; | |
433 | ||
be41e336 CK |
434 | #define SKL_MIN_SRC_W 8 |
435 | #define SKL_MAX_SRC_W 4096 | |
436 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 437 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
438 | #define SKL_MIN_DST_W 8 |
439 | #define SKL_MAX_DST_W 4096 | |
440 | #define SKL_MIN_DST_H 8 | |
6156a456 | 441 | #define SKL_MAX_DST_H 4096 |
be41e336 CK |
442 | |
443 | struct intel_scaler { | |
be41e336 CK |
444 | int in_use; |
445 | uint32_t mode; | |
446 | }; | |
447 | ||
448 | struct intel_crtc_scaler_state { | |
449 | #define SKL_NUM_SCALERS 2 | |
450 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
451 | ||
452 | /* | |
453 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
454 | * | |
455 | * If a bit is set, a user is using a scaler. | |
456 | * Here user can be a plane or crtc as defined below: | |
457 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
458 | * bit 31 - crtc | |
459 | * | |
460 | * Instead of creating a new index to cover planes and crtc, using | |
461 | * existing drm_plane_index for planes which is well less than 31 | |
462 | * planes and bit 31 for crtc. This should be fine to cover all | |
463 | * our platforms. | |
464 | * | |
465 | * intel_atomic_setup_scalers will setup available scalers to users | |
466 | * requesting scalers. It will gracefully fail if request exceeds | |
467 | * avilability. | |
468 | */ | |
469 | #define SKL_CRTC_INDEX 31 | |
470 | unsigned scaler_users; | |
471 | ||
472 | /* scaler used by crtc for panel fitting purpose */ | |
473 | int scaler_id; | |
474 | }; | |
475 | ||
1ed51de9 DV |
476 | /* drm_mode->private_flags */ |
477 | #define I915_MODE_FLAG_INHERITED 1 | |
478 | ||
4e0963c7 MR |
479 | struct intel_pipe_wm { |
480 | struct intel_wm_level wm[5]; | |
71f0a626 | 481 | struct intel_wm_level raw_wm[5]; |
4e0963c7 MR |
482 | uint32_t linetime; |
483 | bool fbc_wm_enabled; | |
484 | bool pipe_enabled; | |
485 | bool sprites_enabled; | |
486 | bool sprites_scaled; | |
487 | }; | |
488 | ||
a62163e9 | 489 | struct skl_plane_wm { |
4e0963c7 MR |
490 | struct skl_wm_level wm[8]; |
491 | struct skl_wm_level trans_wm; | |
a62163e9 L |
492 | }; |
493 | ||
494 | struct skl_pipe_wm { | |
495 | struct skl_plane_wm planes[I915_MAX_PLANES]; | |
4e0963c7 MR |
496 | uint32_t linetime; |
497 | }; | |
498 | ||
855c79f5 VS |
499 | enum vlv_wm_level { |
500 | VLV_WM_LEVEL_PM2, | |
501 | VLV_WM_LEVEL_PM5, | |
502 | VLV_WM_LEVEL_DDR_DVFS, | |
503 | NUM_VLV_WM_LEVELS, | |
504 | }; | |
505 | ||
506 | struct vlv_wm_state { | |
507 | struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS]; | |
508 | struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS]; | |
855c79f5 | 509 | uint8_t num_levels; |
855c79f5 VS |
510 | bool cxsr; |
511 | }; | |
512 | ||
814e7f0b VS |
513 | struct vlv_fifo_state { |
514 | u16 plane[I915_MAX_PLANES]; | |
515 | }; | |
516 | ||
e8f1f02e MR |
517 | struct intel_crtc_wm_state { |
518 | union { | |
519 | struct { | |
520 | /* | |
521 | * Intermediate watermarks; these can be | |
522 | * programmed immediately since they satisfy | |
523 | * both the current configuration we're | |
524 | * switching away from and the new | |
525 | * configuration we're switching to. | |
526 | */ | |
527 | struct intel_pipe_wm intermediate; | |
528 | ||
529 | /* | |
530 | * Optimal watermarks, programmed post-vblank | |
531 | * when this state is committed. | |
532 | */ | |
533 | struct intel_pipe_wm optimal; | |
534 | } ilk; | |
535 | ||
536 | struct { | |
537 | /* gen9+ only needs 1-step wm programming */ | |
538 | struct skl_pipe_wm optimal; | |
ce0ba283 | 539 | struct skl_ddb_entry ddb; |
e8f1f02e | 540 | } skl; |
855c79f5 VS |
541 | |
542 | struct { | |
5012e604 VS |
543 | /* "raw" watermarks (not inverted) */ |
544 | struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS]; | |
4841da51 VS |
545 | /* intermediate watermarks (inverted) */ |
546 | struct vlv_wm_state intermediate; | |
855c79f5 VS |
547 | /* optimal watermarks (inverted) */ |
548 | struct vlv_wm_state optimal; | |
814e7f0b VS |
549 | /* display FIFO split */ |
550 | struct vlv_fifo_state fifo_state; | |
855c79f5 | 551 | } vlv; |
e8f1f02e MR |
552 | }; |
553 | ||
554 | /* | |
555 | * Platforms with two-step watermark programming will need to | |
556 | * update watermark programming post-vblank to switch from the | |
557 | * safe intermediate watermarks to the optimal final | |
558 | * watermarks. | |
559 | */ | |
560 | bool need_postvbl_update; | |
561 | }; | |
562 | ||
5cec258b | 563 | struct intel_crtc_state { |
2d112de7 ACO |
564 | struct drm_crtc_state base; |
565 | ||
bb760063 DV |
566 | /** |
567 | * quirks - bitfield with hw state readout quirks | |
568 | * | |
569 | * For various reasons the hw state readout code might not be able to | |
570 | * completely faithfully read out the current state. These cases are | |
571 | * tracked with quirk flags so that fastboot and state checker can act | |
572 | * accordingly. | |
573 | */ | |
9953599b | 574 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
575 | unsigned long quirks; |
576 | ||
cd202f69 | 577 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
578 | bool update_pipe; /* can a fast modeset be performed? */ |
579 | bool disable_cxsr; | |
caed361d | 580 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 581 | bool fb_changed; /* fb on any of the planes is changed */ |
236c48e6 | 582 | bool fifo_changed; /* FIFO split is changed */ |
bfd16b2a | 583 | |
37327abd VS |
584 | /* Pipe source size (ie. panel fitter input size) |
585 | * All planes will be positioned inside this space, | |
586 | * and get clipped at the edges. */ | |
587 | int pipe_src_w, pipe_src_h; | |
588 | ||
a7d1b3f4 VS |
589 | /* |
590 | * Pipe pixel rate, adjusted for | |
591 | * panel fitter/pipe scaler downscaling. | |
592 | */ | |
593 | unsigned int pixel_rate; | |
594 | ||
5bfe2ac0 DV |
595 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
596 | * between pch encoders and cpu encoders. */ | |
597 | bool has_pch_encoder; | |
50f3b016 | 598 | |
e43823ec JB |
599 | /* Are we sending infoframes on the attached port */ |
600 | bool has_infoframe; | |
601 | ||
3b117c8f | 602 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
603 | * pipe on Haswell and later (where we have a special eDP transcoder) |
604 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
605 | enum transcoder cpu_transcoder; |
606 | ||
50f3b016 DV |
607 | /* |
608 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
609 | * range fed into the crtcs. | |
610 | */ | |
611 | bool limited_color_range; | |
612 | ||
253c84c8 VS |
613 | /* Bitmask of encoder types (enum intel_output_type) |
614 | * driven by the pipe. | |
615 | */ | |
616 | unsigned int output_types; | |
617 | ||
6897b4b5 DV |
618 | /* Whether we should send NULL infoframes. Required for audio. */ |
619 | bool has_hdmi_sink; | |
620 | ||
9ed109a7 DV |
621 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
622 | * has_dp_encoder is set. */ | |
623 | bool has_audio; | |
624 | ||
d8b32247 DV |
625 | /* |
626 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
627 | * plane bpp. | |
628 | */ | |
965e0c48 | 629 | bool dither; |
f47709a9 | 630 | |
611032bf MN |
631 | /* |
632 | * Dither gets enabled for 18bpp which causes CRC mismatch errors for | |
633 | * compliance video pattern tests. | |
634 | * Disable dither only if it is a compliance test request for | |
635 | * 18bpp. | |
636 | */ | |
637 | bool dither_force_disable; | |
638 | ||
f47709a9 DV |
639 | /* Controls for the clock computation, to override various stages. */ |
640 | bool clock_set; | |
641 | ||
09ede541 DV |
642 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
643 | * work correctly, we need to track this at runtime.*/ | |
644 | bool sdvo_tv_clock; | |
645 | ||
e29c22c0 DV |
646 | /* |
647 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
648 | * required. This is set in the 2nd loop of calling encoder's | |
649 | * ->compute_config if the first pick doesn't work out. | |
650 | */ | |
651 | bool bw_constrained; | |
652 | ||
f47709a9 DV |
653 | /* Settings for the intel dpll used on pretty much everything but |
654 | * haswell. */ | |
80ad9206 | 655 | struct dpll dpll; |
f47709a9 | 656 | |
8106ddbd ACO |
657 | /* Selected dpll when shared or NULL. */ |
658 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 659 | |
66e985c0 DV |
660 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
661 | struct intel_dpll_hw_state dpll_hw_state; | |
662 | ||
47eacbab VS |
663 | /* DSI PLL registers */ |
664 | struct { | |
665 | u32 ctrl, div; | |
666 | } dsi_pll; | |
667 | ||
965e0c48 | 668 | int pipe_bpp; |
6cf86a5e | 669 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 670 | |
439d7ac0 PB |
671 | /* m2_n2 for eDP downclock */ |
672 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 673 | bool has_drrs; |
439d7ac0 | 674 | |
ff9a6750 DV |
675 | /* |
676 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
677 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
678 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 679 | */ |
ff9a6750 DV |
680 | int port_clock; |
681 | ||
6cc5f341 DV |
682 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
683 | unsigned pixel_multiplier; | |
2dd24552 | 684 | |
90a6b7b0 VS |
685 | uint8_t lane_count; |
686 | ||
95a7a2ae ID |
687 | /* |
688 | * Used by platforms having DP/HDMI PHY with programmable lane | |
689 | * latency optimization. | |
690 | */ | |
691 | uint8_t lane_lat_optim_mask; | |
692 | ||
2dd24552 | 693 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
694 | struct { |
695 | u32 control; | |
696 | u32 pgm_ratios; | |
68fc8742 | 697 | u32 lvds_border_bits; |
b074cec8 JB |
698 | } gmch_pfit; |
699 | ||
700 | /* Panel fitter placement and size for Ironlake+ */ | |
701 | struct { | |
702 | u32 pos; | |
703 | u32 size; | |
fd4daa9c | 704 | bool enabled; |
fabf6e51 | 705 | bool force_thru; |
b074cec8 | 706 | } pch_pfit; |
33d29b14 | 707 | |
ca3a0ff8 | 708 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 709 | int fdi_lanes; |
ca3a0ff8 | 710 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
711 | |
712 | bool ips_enabled; | |
cf532bb2 | 713 | |
f51be2e0 PZ |
714 | bool enable_fbc; |
715 | ||
cf532bb2 | 716 | bool double_wide; |
0e32b39c | 717 | |
0e32b39c | 718 | int pbn; |
be41e336 CK |
719 | |
720 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
721 | |
722 | /* w/a for waiting 2 vblanks during crtc enable */ | |
723 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
724 | |
725 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
726 | bool disable_lp_wm; | |
4e0963c7 | 727 | |
e8f1f02e | 728 | struct intel_crtc_wm_state wm; |
05dc698c LL |
729 | |
730 | /* Gamma mode programmed on the pipe */ | |
731 | uint32_t gamma_mode; | |
e9728bd8 VS |
732 | |
733 | /* bitmask of visible planes (enum plane_id) */ | |
734 | u8 active_planes; | |
15953637 SS |
735 | |
736 | /* HDMI scrambling status */ | |
737 | bool hdmi_scrambling; | |
738 | ||
739 | /* HDMI High TMDS char rate ratio */ | |
740 | bool hdmi_high_tmds_clock_ratio; | |
b8cecdf5 DV |
741 | }; |
742 | ||
79e53945 JB |
743 | struct intel_crtc { |
744 | struct drm_crtc base; | |
80824003 JB |
745 | enum pipe pipe; |
746 | enum plane plane; | |
79e53945 | 747 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
748 | /* |
749 | * Whether the crtc and the connected output pipeline is active. Implies | |
750 | * that crtc->enabled is set, i.e. the current mode configuration has | |
751 | * some outputs connected to this crtc. | |
08a48469 DV |
752 | */ |
753 | bool active; | |
652c393a | 754 | bool lowfreq_avail; |
d97d7b48 | 755 | u8 plane_ids_mask; |
d8fc70b7 | 756 | unsigned long long enabled_power_domains; |
02e792fb | 757 | struct intel_overlay *overlay; |
5a21b665 | 758 | struct intel_flip_work *flip_work; |
cda4b7d3 | 759 | |
b4a98e57 CW |
760 | atomic_t unpin_work_count; |
761 | ||
e506a0c6 DV |
762 | /* Display surface base address adjustement for pageflips. Note that on |
763 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
764 | * handled in the hw itself (with the TILEOFF register). */ | |
54ea9da8 | 765 | u32 dspaddr_offset; |
2db3366b PZ |
766 | int adjusted_x; |
767 | int adjusted_y; | |
e506a0c6 | 768 | |
cda4b7d3 | 769 | uint32_t cursor_addr; |
4b0e333e | 770 | uint32_t cursor_cntl; |
dc41c154 | 771 | uint32_t cursor_size; |
4b0e333e | 772 | uint32_t cursor_base; |
4b645f14 | 773 | |
6e3c9717 | 774 | struct intel_crtc_state *config; |
b8cecdf5 | 775 | |
8af29b0c CW |
776 | /* global reset count when the last flip was submitted */ |
777 | unsigned int reset_count; | |
5a21b665 | 778 | |
8664281b PZ |
779 | /* Access to these should be protected by dev_priv->irq_lock. */ |
780 | bool cpu_fifo_underrun_disabled; | |
781 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
782 | |
783 | /* per-pipe watermark state */ | |
784 | struct { | |
785 | /* watermarks currently being used */ | |
4e0963c7 MR |
786 | union { |
787 | struct intel_pipe_wm ilk; | |
7eb4941f | 788 | struct vlv_wm_state vlv; |
4e0963c7 | 789 | } active; |
0b2ae6d7 | 790 | } wm; |
8d7849db | 791 | |
80715b2f | 792 | int scanline_offset; |
32b7eeec | 793 | |
eb120ef6 JB |
794 | struct { |
795 | unsigned start_vbl_count; | |
796 | ktime_t start_vbl_time; | |
797 | int min_vbl, max_vbl; | |
798 | int scanline_start; | |
799 | } debug; | |
85a62bf9 | 800 | |
be41e336 CK |
801 | /* scalers available on this crtc */ |
802 | int num_scalers; | |
79e53945 JB |
803 | }; |
804 | ||
b840d907 JB |
805 | struct intel_plane { |
806 | struct drm_plane base; | |
b14e5848 VS |
807 | u8 plane; |
808 | enum plane_id id; | |
b840d907 | 809 | enum pipe pipe; |
2d354c34 | 810 | bool can_scale; |
b840d907 | 811 | int max_downscale; |
a9ff8714 | 812 | uint32_t frontbuffer_bit; |
526682e9 | 813 | |
8e7d688b MR |
814 | /* |
815 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
816 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 817 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
818 | */ |
819 | ||
b840d907 | 820 | void (*update_plane)(struct drm_plane *plane, |
2fde1391 ML |
821 | const struct intel_crtc_state *crtc_state, |
822 | const struct intel_plane_state *plane_state); | |
b39d53f6 | 823 | void (*disable_plane)(struct drm_plane *plane, |
7fabf5ef | 824 | struct drm_crtc *crtc); |
c59cb179 | 825 | int (*check_plane)(struct drm_plane *plane, |
061e4b8d | 826 | struct intel_crtc_state *crtc_state, |
c59cb179 | 827 | struct intel_plane_state *state); |
b840d907 JB |
828 | }; |
829 | ||
b445e3b0 | 830 | struct intel_watermark_params { |
ae9400ca TU |
831 | u16 fifo_size; |
832 | u16 max_wm; | |
833 | u8 default_wm; | |
834 | u8 guard_size; | |
835 | u8 cacheline_size; | |
b445e3b0 ED |
836 | }; |
837 | ||
838 | struct cxsr_latency { | |
c13fb778 TU |
839 | bool is_desktop : 1; |
840 | bool is_ddr3 : 1; | |
44a655ca TU |
841 | u16 fsb_freq; |
842 | u16 mem_freq; | |
843 | u16 display_sr; | |
844 | u16 display_hpll_disable; | |
845 | u16 cursor_sr; | |
846 | u16 cursor_hpll_disable; | |
b445e3b0 ED |
847 | }; |
848 | ||
de419ab6 | 849 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 850 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 851 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 852 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 853 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 854 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 855 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 856 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
155e6369 | 857 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 858 | |
f5bbfca3 | 859 | struct intel_hdmi { |
f0f59a00 | 860 | i915_reg_t hdmi_reg; |
f5bbfca3 | 861 | int ddc_bus; |
b1ba124d VS |
862 | struct { |
863 | enum drm_dp_dual_mode_type type; | |
864 | int max_tmds_clock; | |
865 | } dp_dual_mode; | |
0f2a2a75 | 866 | bool limited_color_range; |
55bc60db | 867 | bool color_range_auto; |
f5bbfca3 ED |
868 | bool has_hdmi_sink; |
869 | bool has_audio; | |
870 | enum hdmi_force_audio force_audio; | |
abedc077 | 871 | bool rgb_quant_range_selectable; |
94a11ddc | 872 | enum hdmi_picture_aspect aspect_ratio; |
d8b4c43a | 873 | struct intel_connector *attached_connector; |
f5bbfca3 | 874 | void (*write_infoframe)(struct drm_encoder *encoder, |
ac240288 | 875 | const struct intel_crtc_state *crtc_state, |
178f736a | 876 | enum hdmi_infoframe_type type, |
fff63867 | 877 | const void *frame, ssize_t len); |
687f4d06 | 878 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 879 | bool enable, |
ac240288 ML |
880 | const struct intel_crtc_state *crtc_state, |
881 | const struct drm_connector_state *conn_state); | |
cda0aaaf VS |
882 | bool (*infoframe_enabled)(struct drm_encoder *encoder, |
883 | const struct intel_crtc_state *pipe_config); | |
f5bbfca3 ED |
884 | }; |
885 | ||
0e32b39c | 886 | struct intel_dp_mst_encoder; |
b091cd92 | 887 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 888 | |
fe3cd48d R |
889 | /* |
890 | * enum link_m_n_set: | |
891 | * When platform provides two set of M_N registers for dp, we can | |
892 | * program them and switch between them incase of DRRS. | |
893 | * But When only one such register is provided, we have to program the | |
894 | * required divider value on that registers itself based on the DRRS state. | |
895 | * | |
896 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
897 | * dp_m2_n2 on M2_N2 registers (If supported) | |
898 | * | |
899 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
900 | * M2_N2 registers are not supported | |
901 | */ | |
902 | ||
903 | enum link_m_n_set { | |
904 | /* Sets the m1_n1 and m2_n2 */ | |
905 | M1_N1 = 0, | |
906 | M2_N2 | |
907 | }; | |
908 | ||
7b3fc170 ID |
909 | struct intel_dp_desc { |
910 | u8 oui[3]; | |
911 | u8 device_id[6]; | |
912 | u8 hw_rev; | |
913 | u8 sw_major_rev; | |
914 | u8 sw_minor_rev; | |
915 | } __packed; | |
916 | ||
c1617abc MN |
917 | struct intel_dp_compliance_data { |
918 | unsigned long edid; | |
611032bf MN |
919 | uint8_t video_pattern; |
920 | uint16_t hdisplay, vdisplay; | |
921 | uint8_t bpc; | |
c1617abc MN |
922 | }; |
923 | ||
924 | struct intel_dp_compliance { | |
925 | unsigned long test_type; | |
926 | struct intel_dp_compliance_data test_data; | |
927 | bool test_active; | |
da15f7cb MN |
928 | int test_link_rate; |
929 | u8 test_lane_count; | |
c1617abc MN |
930 | }; |
931 | ||
54d63ca6 | 932 | struct intel_dp { |
f0f59a00 VS |
933 | i915_reg_t output_reg; |
934 | i915_reg_t aux_ch_ctl_reg; | |
935 | i915_reg_t aux_ch_data_reg[5]; | |
54d63ca6 | 936 | uint32_t DP; |
901c2daf VS |
937 | int link_rate; |
938 | uint8_t lane_count; | |
30d9aa42 | 939 | uint8_t sink_count; |
64ee2fd2 | 940 | bool link_mst; |
54d63ca6 | 941 | bool has_audio; |
7d23e3c3 | 942 | bool detect_done; |
c92bd2fa | 943 | bool channel_eq_status; |
d7e8ef02 | 944 | bool reset_link_params; |
54d63ca6 | 945 | enum hdmi_force_audio force_audio; |
0f2a2a75 | 946 | bool limited_color_range; |
55bc60db | 947 | bool color_range_auto; |
54d63ca6 | 948 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 949 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 950 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
86ee27b5 | 951 | uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
55cfc580 JN |
952 | /* source rates */ |
953 | int num_source_rates; | |
954 | const int *source_rates; | |
68f357cb JN |
955 | /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ |
956 | int num_sink_rates; | |
94ca719e | 957 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
68f357cb | 958 | bool use_rate_select; |
975ee5fc JN |
959 | /* intersection of source and sink rates */ |
960 | int num_common_rates; | |
961 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
e6c0c64a JN |
962 | /* Max lane count for the current link */ |
963 | int max_link_lane_count; | |
964 | /* Max rate for the current link */ | |
965 | int max_link_rate; | |
7b3fc170 ID |
966 | /* sink or branch descriptor */ |
967 | struct intel_dp_desc desc; | |
9d1a1031 | 968 | struct drm_dp_aux aux; |
5432fcaf | 969 | enum intel_display_power_domain aux_power_domain; |
54d63ca6 SK |
970 | uint8_t train_set[4]; |
971 | int panel_power_up_delay; | |
972 | int panel_power_down_delay; | |
973 | int panel_power_cycle_delay; | |
974 | int backlight_on_delay; | |
975 | int backlight_off_delay; | |
54d63ca6 SK |
976 | struct delayed_work panel_vdd_work; |
977 | bool want_panel_vdd; | |
dce56b3c PZ |
978 | unsigned long last_power_on; |
979 | unsigned long last_backlight_off; | |
d28d4731 | 980 | ktime_t panel_power_off_time; |
5d42f82a | 981 | |
01527b31 CT |
982 | struct notifier_block edp_notifier; |
983 | ||
a4a5d2f8 VS |
984 | /* |
985 | * Pipe whose power sequencer is currently locked into | |
986 | * this port. Only relevant on VLV/CHV. | |
987 | */ | |
988 | enum pipe pps_pipe; | |
9f2bdb00 VS |
989 | /* |
990 | * Pipe currently driving the port. Used for preventing | |
991 | * the use of the PPS for any pipe currentrly driving | |
992 | * external DP as that will mess things up on VLV. | |
993 | */ | |
994 | enum pipe active_pipe; | |
78597996 ID |
995 | /* |
996 | * Set if the sequencer may be reset due to a power transition, | |
997 | * requiring a reinitialization. Only relevant on BXT. | |
998 | */ | |
999 | bool pps_reset; | |
36b5f425 | 1000 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 1001 | |
0e32b39c DA |
1002 | bool can_mst; /* this port supports mst */ |
1003 | bool is_mst; | |
19e0b4ca | 1004 | int active_mst_links; |
0e32b39c | 1005 | /* connector directly attached - won't be use for modeset in mst world */ |
dd06f90e | 1006 | struct intel_connector *attached_connector; |
ec5b01dd | 1007 | |
0e32b39c DA |
1008 | /* mst connector list */ |
1009 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
1010 | struct drm_dp_mst_topology_mgr mst_mgr; | |
1011 | ||
ec5b01dd | 1012 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
1013 | /* |
1014 | * This function returns the value we have to program the AUX_CTL | |
1015 | * register with to kick off an AUX transaction. | |
1016 | */ | |
1017 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
1018 | bool has_aux_irq, | |
1019 | int send_bytes, | |
1020 | uint32_t aux_clock_divider); | |
ad64217b ACO |
1021 | |
1022 | /* This is called before a link training is starterd */ | |
1023 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
1024 | ||
c5d5ab7a | 1025 | /* Displayport compliance testing */ |
c1617abc | 1026 | struct intel_dp_compliance compliance; |
54d63ca6 SK |
1027 | }; |
1028 | ||
dbe9e61b SS |
1029 | struct intel_lspcon { |
1030 | bool active; | |
1031 | enum drm_lspcon_mode mode; | |
dbe9e61b SS |
1032 | }; |
1033 | ||
da63a9f2 PZ |
1034 | struct intel_digital_port { |
1035 | struct intel_encoder base; | |
174edf1f | 1036 | enum port port; |
bcf53de4 | 1037 | u32 saved_port_bits; |
da63a9f2 PZ |
1038 | struct intel_dp dp; |
1039 | struct intel_hdmi hdmi; | |
dbe9e61b | 1040 | struct intel_lspcon lspcon; |
b2c5c181 | 1041 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 1042 | bool release_cl2_override; |
ccb1a831 | 1043 | uint8_t max_lanes; |
62b69566 | 1044 | enum intel_display_power_domain ddi_io_power_domain; |
da63a9f2 PZ |
1045 | }; |
1046 | ||
0e32b39c DA |
1047 | struct intel_dp_mst_encoder { |
1048 | struct intel_encoder base; | |
1049 | enum pipe pipe; | |
1050 | struct intel_digital_port *primary; | |
0552f765 | 1051 | struct intel_connector *connector; |
0e32b39c DA |
1052 | }; |
1053 | ||
65d64cc5 | 1054 | static inline enum dpio_channel |
89b667f8 JB |
1055 | vlv_dport_to_channel(struct intel_digital_port *dport) |
1056 | { | |
1057 | switch (dport->port) { | |
1058 | case PORT_B: | |
00fc31b7 | 1059 | case PORT_D: |
e4607fcf | 1060 | return DPIO_CH0; |
89b667f8 | 1061 | case PORT_C: |
e4607fcf | 1062 | return DPIO_CH1; |
89b667f8 JB |
1063 | default: |
1064 | BUG(); | |
1065 | } | |
1066 | } | |
1067 | ||
65d64cc5 VS |
1068 | static inline enum dpio_phy |
1069 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
1070 | { | |
1071 | switch (dport->port) { | |
1072 | case PORT_B: | |
1073 | case PORT_C: | |
1074 | return DPIO_PHY0; | |
1075 | case PORT_D: | |
1076 | return DPIO_PHY1; | |
1077 | default: | |
1078 | BUG(); | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | static inline enum dpio_channel | |
eb69b0e5 CML |
1083 | vlv_pipe_to_channel(enum pipe pipe) |
1084 | { | |
1085 | switch (pipe) { | |
1086 | case PIPE_A: | |
1087 | case PIPE_C: | |
1088 | return DPIO_CH0; | |
1089 | case PIPE_B: | |
1090 | return DPIO_CH1; | |
1091 | default: | |
1092 | BUG(); | |
1093 | } | |
1094 | } | |
1095 | ||
e2af48c6 | 1096 | static inline struct intel_crtc * |
b91eb5cc | 1097 | intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
f875c15a | 1098 | { |
f875c15a CW |
1099 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
1100 | } | |
1101 | ||
e2af48c6 | 1102 | static inline struct intel_crtc * |
b91eb5cc | 1103 | intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) |
417ae147 | 1104 | { |
417ae147 CW |
1105 | return dev_priv->plane_to_crtc_mapping[plane]; |
1106 | } | |
1107 | ||
51cbaf01 ML |
1108 | struct intel_flip_work { |
1109 | struct work_struct unpin_work; | |
1110 | struct work_struct mmio_work; | |
1111 | ||
5a21b665 | 1112 | struct drm_crtc *crtc; |
be1e3415 | 1113 | struct i915_vma *old_vma; |
5a21b665 DV |
1114 | struct drm_framebuffer *old_fb; |
1115 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 1116 | struct drm_pending_vblank_event *event; |
e7d841ca | 1117 | atomic_t pending; |
5a21b665 DV |
1118 | u32 flip_count; |
1119 | u32 gtt_offset; | |
1120 | struct drm_i915_gem_request *flip_queued_req; | |
66f59c5c | 1121 | u32 flip_queued_vblank; |
5a21b665 DV |
1122 | u32 flip_ready_vblank; |
1123 | unsigned int rotation; | |
4e5359cd SF |
1124 | }; |
1125 | ||
5f1aae65 | 1126 | struct intel_load_detect_pipe { |
edde3617 | 1127 | struct drm_atomic_state *restore_state; |
5f1aae65 | 1128 | }; |
79e53945 | 1129 | |
5f1aae65 PZ |
1130 | static inline struct intel_encoder * |
1131 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
1132 | { |
1133 | return to_intel_connector(connector)->encoder; | |
1134 | } | |
1135 | ||
da63a9f2 PZ |
1136 | static inline struct intel_digital_port * |
1137 | enc_to_dig_port(struct drm_encoder *encoder) | |
1138 | { | |
9a5da00b ACO |
1139 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
1140 | ||
1141 | switch (intel_encoder->type) { | |
1142 | case INTEL_OUTPUT_UNKNOWN: | |
1143 | WARN_ON(!HAS_DDI(to_i915(encoder->dev))); | |
1144 | case INTEL_OUTPUT_DP: | |
1145 | case INTEL_OUTPUT_EDP: | |
1146 | case INTEL_OUTPUT_HDMI: | |
1147 | return container_of(encoder, struct intel_digital_port, | |
1148 | base.base); | |
1149 | default: | |
1150 | return NULL; | |
1151 | } | |
9ff8c9ba ID |
1152 | } |
1153 | ||
0e32b39c DA |
1154 | static inline struct intel_dp_mst_encoder * |
1155 | enc_to_mst(struct drm_encoder *encoder) | |
1156 | { | |
1157 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
1158 | } | |
1159 | ||
9ff8c9ba ID |
1160 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1161 | { | |
1162 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1163 | } |
1164 | ||
1165 | static inline struct intel_digital_port * | |
1166 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1167 | { | |
1168 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1169 | } | |
1170 | ||
dd75f6dd ID |
1171 | static inline struct intel_lspcon * |
1172 | dp_to_lspcon(struct intel_dp *intel_dp) | |
1173 | { | |
1174 | return &dp_to_dig_port(intel_dp)->lspcon; | |
1175 | } | |
1176 | ||
da63a9f2 PZ |
1177 | static inline struct intel_digital_port * |
1178 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1179 | { | |
1180 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1181 | } |
1182 | ||
47339cd9 | 1183 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1184 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1185 | enum pipe pipe, bool enable); |
a72e4c9f | 1186 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 PZ |
1187 | enum transcoder pch_transcoder, |
1188 | bool enable); | |
1f7247c0 DV |
1189 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe); | |
1191 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
1192 | enum transcoder pch_transcoder); | |
aca7b684 VS |
1193 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1194 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
1195 | |
1196 | /* i915_irq.c */ | |
480c8033 DV |
1197 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1198 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
f4e9af4f AG |
1199 | void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask); |
1200 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); | |
1201 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); | |
480c8033 DV |
1202 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1203 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
dc97997a | 1204 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
91d14251 TU |
1205 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
1206 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); | |
1300b4f8 CW |
1207 | |
1208 | static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, | |
1209 | u32 mask) | |
1210 | { | |
1211 | return mask & ~i915->rps.pm_intrmsk_mbz; | |
1212 | } | |
1213 | ||
b963291c DV |
1214 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1215 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1216 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1217 | { | |
1218 | /* | |
1219 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1220 | * this is the only thing we need to check. | |
1221 | */ | |
2aeb7d3a | 1222 | return dev_priv->pm.irqs_enabled; |
9df7575f JB |
1223 | } |
1224 | ||
a225f079 | 1225 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be DL |
1226 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
1227 | unsigned int pipe_mask); | |
aae8ba84 VS |
1228 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
1229 | unsigned int pipe_mask); | |
26705e20 SAK |
1230 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); |
1231 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); | |
1232 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); | |
5f1aae65 | 1233 | |
5f1aae65 | 1234 | /* intel_crt.c */ |
c39055b0 | 1235 | void intel_crt_init(struct drm_i915_private *dev_priv); |
9504a892 | 1236 | void intel_crt_reset(struct drm_encoder *encoder); |
5f1aae65 PZ |
1237 | |
1238 | /* intel_ddi.c */ | |
b7076546 ML |
1239 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
1240 | struct intel_crtc_state *old_crtc_state, | |
1241 | struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
1242 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
1243 | const struct intel_crtc_state *crtc_state); | |
c39055b0 | 1244 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); |
87440425 PZ |
1245 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
1246 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
3dc38eea | 1247 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); |
87440425 PZ |
1248 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1249 | enum transcoder cpu_transcoder); | |
3dc38eea ACO |
1250 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1251 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); | |
44a126ba PZ |
1252 | struct intel_encoder * |
1253 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); | |
3dc38eea | 1254 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); |
ad64217b | 1255 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 | 1256 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
9935f7fa LY |
1257 | bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
1258 | struct intel_crtc *intel_crtc); | |
87440425 | 1259 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1260 | struct intel_crtc_state *pipe_config); |
5f1aae65 | 1261 | |
0e32b39c | 1262 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1263 | struct intel_crtc_state *pipe_config); |
3dc38eea ACO |
1264 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1265 | bool state); | |
f8896f5d | 1266 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
ffe5111e VS |
1267 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); |
1268 | ||
d88c4afd VS |
1269 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, |
1270 | int plane, unsigned int height); | |
b680c37a | 1271 | |
7c10a2b5 | 1272 | /* intel_audio.c */ |
88212941 | 1273 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
bbf35e9d ML |
1274 | void intel_audio_codec_enable(struct intel_encoder *encoder, |
1275 | const struct intel_crtc_state *crtc_state, | |
1276 | const struct drm_connector_state *conn_state); | |
69bfe1a9 | 1277 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
58fddc28 ID |
1278 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1279 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
eef57324 JA |
1280 | void intel_audio_init(struct drm_i915_private *dev_priv); |
1281 | void intel_audio_deinit(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 1282 | |
7ff89ca2 | 1283 | /* intel_cdclk.c */ |
e1cd3325 PZ |
1284 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
1285 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
1286 | void bxt_init_cdclk(struct drm_i915_private *dev_priv); | |
1287 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); | |
7ff89ca2 VS |
1288 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); |
1289 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv); | |
1290 | void intel_update_cdclk(struct drm_i915_private *dev_priv); | |
1291 | void intel_update_rawclk(struct drm_i915_private *dev_priv); | |
49cd97a3 VS |
1292 | bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, |
1293 | const struct intel_cdclk_state *b); | |
b0587e4d VS |
1294 | void intel_set_cdclk(struct drm_i915_private *dev_priv, |
1295 | const struct intel_cdclk_state *cdclk_state); | |
7ff89ca2 | 1296 | |
b680c37a | 1297 | /* intel_display.c */ |
65f2130c | 1298 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); |
19ab4ed3 | 1299 | void intel_update_rawclk(struct drm_i915_private *dev_priv); |
49cd97a3 | 1300 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1301 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1302 | const char *name, u32 reg, int ref_freq); | |
7ff89ca2 VS |
1303 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
1304 | const char *name, u32 reg); | |
b7076546 ML |
1305 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); |
1306 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
65a3fea0 | 1307 | extern const struct drm_plane_funcs intel_plane_funcs; |
88212941 | 1308 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
6687c906 | 1309 | unsigned int intel_fb_xy_to_linear(int x, int y, |
2949056c VS |
1310 | const struct intel_plane_state *state, |
1311 | int plane); | |
6687c906 | 1312 | void intel_add_fb_offsets(int *x, int *y, |
2949056c | 1313 | const struct intel_plane_state *state, int plane); |
1663b9d6 | 1314 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
49d73912 | 1315 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); |
7d993739 TU |
1316 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1317 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
87440425 | 1318 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
70e0bd74 | 1319 | int intel_display_suspend(struct drm_device *dev); |
8090ba8c | 1320 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); |
87440425 | 1321 | void intel_encoder_destroy(struct drm_encoder *encoder); |
08d9bc92 ACO |
1322 | int intel_connector_init(struct intel_connector *); |
1323 | struct intel_connector *intel_connector_alloc(void); | |
87440425 | 1324 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
87440425 PZ |
1325 | void intel_connector_attach_encoder(struct intel_connector *connector, |
1326 | struct intel_encoder *encoder); | |
87440425 PZ |
1327 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
1328 | struct drm_crtc *crtc); | |
752aa88a | 1329 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
1330 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1331 | struct drm_file *file_priv); | |
87440425 PZ |
1332 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1333 | enum pipe pipe); | |
2d84d2b3 VS |
1334 | static inline bool |
1335 | intel_crtc_has_type(const struct intel_crtc_state *crtc_state, | |
1336 | enum intel_output_type type) | |
1337 | { | |
1338 | return crtc_state->output_types & (1 << type); | |
1339 | } | |
37a5650b VS |
1340 | static inline bool |
1341 | intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) | |
1342 | { | |
1343 | return crtc_state->output_types & | |
cca0502b | 1344 | ((1 << INTEL_OUTPUT_DP) | |
37a5650b VS |
1345 | (1 << INTEL_OUTPUT_DP_MST) | |
1346 | (1 << INTEL_OUTPUT_EDP)); | |
1347 | } | |
4f905cf9 | 1348 | static inline void |
0f0f74bc | 1349 | intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) |
4f905cf9 | 1350 | { |
0f0f74bc | 1351 | drm_wait_one_vblank(&dev_priv->drm, pipe); |
4f905cf9 | 1352 | } |
0c241d5b | 1353 | static inline void |
0f0f74bc | 1354 | intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) |
0c241d5b | 1355 | { |
b91eb5cc | 1356 | const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
0c241d5b VS |
1357 | |
1358 | if (crtc->active) | |
0f0f74bc | 1359 | intel_wait_for_vblank(dev_priv, pipe); |
0c241d5b | 1360 | } |
a2991414 ML |
1361 | |
1362 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
1363 | ||
87440425 | 1364 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1365 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1366 | struct intel_digital_port *dport, |
1367 | unsigned int expected_mask); | |
87440425 PZ |
1368 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
1369 | struct drm_display_mode *mode, | |
51fd371b RC |
1370 | struct intel_load_detect_pipe *old, |
1371 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1372 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1373 | struct intel_load_detect_pipe *old, |
1374 | struct drm_modeset_acquire_ctx *ctx); | |
058d88c4 CW |
1375 | struct i915_vma * |
1376 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation); | |
be1e3415 | 1377 | void intel_unpin_fb_vma(struct i915_vma *vma); |
a8bb6818 | 1378 | struct drm_framebuffer * |
24dbf51a CW |
1379 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
1380 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5a21b665 | 1381 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); |
51cbaf01 | 1382 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); |
5a21b665 | 1383 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); |
6beb8c23 | 1384 | int intel_prepare_plane_fb(struct drm_plane *plane, |
1832040d | 1385 | struct drm_plane_state *new_state); |
38f3ce3a | 1386 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
1832040d | 1387 | struct drm_plane_state *old_state); |
a98b3431 MR |
1388 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1389 | const struct drm_plane_state *state, | |
1390 | struct drm_property *property, | |
1391 | uint64_t *val); | |
1392 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1393 | struct drm_plane_state *state, | |
1394 | struct drm_property *property, | |
1395 | uint64_t val); | |
da20eabd ML |
1396 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
1397 | struct drm_plane_state *plane_state); | |
716c2e55 | 1398 | |
7abd4b35 ACO |
1399 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1400 | enum pipe pipe); | |
1401 | ||
30ad9814 | 1402 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 1403 | const struct dpll *dpll); |
30ad9814 | 1404 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); |
8802e5b6 | 1405 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1406 | |
716c2e55 | 1407 | /* modesetting asserts */ |
b680c37a DV |
1408 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1409 | enum pipe pipe); | |
55607e8a DV |
1410 | void assert_pll(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe, bool state); | |
1412 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1413 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1414 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1415 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1416 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1417 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1418 | enum pipe pipe, bool state); | |
1419 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1420 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1421 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1422 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1423 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
4f2d9934 | 1424 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c | 1425 | const struct intel_plane_state *state, int plane); |
c033666a CW |
1426 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1427 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
a14cb6fc PZ |
1428 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1429 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
da2f41d1 | 1430 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
664326f8 SK |
1431 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1432 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
f62c79b3 | 1433 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
c89e39f3 | 1434 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
0a9d2bed AM |
1435 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
1436 | void skl_disable_dc6(struct drm_i915_private *dev_priv); | |
87440425 | 1437 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1438 | struct intel_crtc_state *pipe_config); |
fe3cd48d | 1439 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
87440425 | 1440 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
5ab7b0b7 | 1441 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 ACO |
1442 | struct dpll *best_clock); |
1443 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1444 | |
525b9311 | 1445 | bool intel_crtc_active(struct intel_crtc *crtc); |
20bc8673 VS |
1446 | void hsw_enable_ips(struct intel_crtc *crtc); |
1447 | void hsw_disable_ips(struct intel_crtc *crtc); | |
79f255a0 | 1448 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); |
f6a83288 | 1449 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1450 | struct intel_crtc_state *pipe_config); |
86adf9d7 | 1451 | |
e435d6e5 | 1452 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
6156a456 | 1453 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
8ea30864 | 1454 | |
be1e3415 CW |
1455 | static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) |
1456 | { | |
1457 | return i915_ggtt_offset(state->vma); | |
1458 | } | |
dedf278c | 1459 | |
2e881264 VS |
1460 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
1461 | const struct intel_plane_state *plane_state); | |
d2196774 VS |
1462 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
1463 | unsigned int rotation); | |
b63a16f6 | 1464 | int skl_check_plane_surface(struct intel_plane_state *plane_state); |
f9407ae1 | 1465 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); |
121920fa | 1466 | |
eb805623 | 1467 | /* intel_csr.c */ |
f4448375 | 1468 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1469 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1470 | void intel_csr_ucode_fini(struct drm_i915_private *); |
f74ed08d ID |
1471 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
1472 | void intel_csr_ucode_resume(struct drm_i915_private *); | |
eb805623 | 1473 | |
5f1aae65 | 1474 | /* intel_dp.c */ |
c39055b0 ACO |
1475 | bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, |
1476 | enum port port); | |
87440425 PZ |
1477 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1478 | struct intel_connector *intel_connector); | |
901c2daf | 1479 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1480 | int link_rate, uint8_t lane_count, |
1481 | bool link_mst); | |
fdb14d33 MN |
1482 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
1483 | int link_rate, uint8_t lane_count); | |
87440425 | 1484 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 PZ |
1485 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
1486 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
bf93ba67 ID |
1487 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1488 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | |
87440425 | 1489 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
d2e216d0 | 1490 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 | 1491 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1492 | struct intel_crtc_state *pipe_config, |
1493 | struct drm_connector_state *conn_state); | |
dd11bc10 | 1494 | bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port); |
b2c5c181 DV |
1495 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1496 | bool long_hpd); | |
4be73780 DV |
1497 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1498 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 1499 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1500 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1501 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
0e32b39c DA |
1502 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
1503 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1504 | void intel_dp_mst_resume(struct drm_device *dev); | |
50fec21a | 1505 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
ed4e9c1d | 1506 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1507 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
78597996 | 1508 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1509 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1510 | void intel_plane_destroy(struct drm_plane *plane); |
85cb48a1 ML |
1511 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
1512 | struct intel_crtc_state *crtc_state); | |
1513 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, | |
1514 | struct intel_crtc_state *crtc_state); | |
5748b6a1 CW |
1515 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
1516 | unsigned int frontbuffer_bits); | |
1517 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, | |
1518 | unsigned int frontbuffer_bits); | |
0bc12bcb | 1519 | |
94223d04 ACO |
1520 | void |
1521 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1522 | uint8_t dp_train_pat); | |
1523 | void | |
1524 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1525 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1526 | uint8_t | |
1527 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1528 | uint8_t | |
1529 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1530 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1531 | uint8_t *link_bw, uint8_t *rate_select); | |
e588fa18 | 1532 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
94223d04 ACO |
1533 | bool |
1534 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
1535 | ||
419b1b7a ACO |
1536 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
1537 | { | |
1538 | return ~((1 << lane_count) - 1) & 0xf; | |
1539 | } | |
1540 | ||
24e807e7 | 1541 | bool intel_dp_read_dpcd(struct intel_dp *intel_dp); |
489375c8 ID |
1542 | bool __intel_dp_read_desc(struct intel_dp *intel_dp, |
1543 | struct intel_dp_desc *desc); | |
12a47a42 | 1544 | bool intel_dp_read_desc(struct intel_dp *intel_dp); |
22a2c8e0 DP |
1545 | int intel_dp_link_required(int pixel_clock, int bpp); |
1546 | int intel_dp_max_data_rate(int max_link_clock, int max_lanes); | |
390b4e00 ID |
1547 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
1548 | struct intel_digital_port *port); | |
24e807e7 | 1549 | |
e7156c83 YA |
1550 | /* intel_dp_aux_backlight.c */ |
1551 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); | |
1552 | ||
0e32b39c DA |
1553 | /* intel_dp_mst.c */ |
1554 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1555 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 1556 | /* intel_dsi.c */ |
c39055b0 | 1557 | void intel_dsi_init(struct drm_i915_private *dev_priv); |
5f1aae65 | 1558 | |
90198355 JN |
1559 | /* intel_dsi_dcs_backlight.c */ |
1560 | int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); | |
5f1aae65 PZ |
1561 | |
1562 | /* intel_dvo.c */ | |
c39055b0 | 1563 | void intel_dvo_init(struct drm_i915_private *dev_priv); |
19625e85 L |
1564 | /* intel_hotplug.c */ |
1565 | void intel_hpd_poll_init(struct drm_i915_private *dev_priv); | |
5f1aae65 PZ |
1566 | |
1567 | ||
0632fef6 | 1568 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 1569 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 1570 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 1571 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4520f53a | 1572 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 1573 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1574 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1575 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1576 | #else |
1577 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1578 | { | |
1579 | return 0; | |
1580 | } | |
5f1aae65 | 1581 | |
e00bf696 | 1582 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a DV |
1583 | { |
1584 | } | |
1585 | ||
1586 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1587 | { | |
1588 | } | |
1589 | ||
82e3b8c1 | 1590 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1591 | { |
1592 | } | |
1593 | ||
d9c409d6 JN |
1594 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
1595 | { | |
1596 | } | |
1597 | ||
0632fef6 | 1598 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1599 | { |
1600 | } | |
1601 | #endif | |
5f1aae65 | 1602 | |
7ff0ebcc | 1603 | /* intel_fbc.c */ |
f51be2e0 PZ |
1604 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
1605 | struct drm_atomic_state *state); | |
0e631adc | 1606 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1607 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
1608 | struct intel_crtc_state *crtc_state, | |
1609 | struct intel_plane_state *plane_state); | |
1eb52238 | 1610 | void intel_fbc_post_update(struct intel_crtc *crtc); |
7ff0ebcc | 1611 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 1612 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
faf68d92 ML |
1613 | void intel_fbc_enable(struct intel_crtc *crtc, |
1614 | struct intel_crtc_state *crtc_state, | |
1615 | struct intel_plane_state *plane_state); | |
c937ab3e PZ |
1616 | void intel_fbc_disable(struct intel_crtc *crtc); |
1617 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
1618 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1619 | unsigned int frontbuffer_bits, | |
1620 | enum fb_op_origin origin); | |
1621 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1622 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 1623 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
61a585d6 | 1624 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1625 | |
5f1aae65 | 1626 | /* intel_hdmi.c */ |
c39055b0 ACO |
1627 | void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, |
1628 | enum port port); | |
87440425 PZ |
1629 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1630 | struct intel_connector *intel_connector); | |
1631 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1632 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
0a478c27 ML |
1633 | struct intel_crtc_state *pipe_config, |
1634 | struct drm_connector_state *conn_state); | |
15953637 SS |
1635 | void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder, |
1636 | struct drm_connector *connector, | |
1637 | bool high_tmds_clock_ratio, | |
1638 | bool scrambling); | |
b2ccb822 | 1639 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
5f1aae65 PZ |
1640 | |
1641 | ||
1642 | /* intel_lvds.c */ | |
c39055b0 | 1643 | void intel_lvds_init(struct drm_i915_private *dev_priv); |
97a824e1 | 1644 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev); |
87440425 | 1645 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
5f1aae65 PZ |
1646 | |
1647 | ||
1648 | /* intel_modes.c */ | |
1649 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1650 | struct edid *edid); |
5f1aae65 | 1651 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1652 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1653 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
7949dd47 | 1654 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
5f1aae65 PZ |
1655 | |
1656 | ||
1657 | /* intel_overlay.c */ | |
1ee8da6d CW |
1658 | void intel_setup_overlay(struct drm_i915_private *dev_priv); |
1659 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv); | |
87440425 | 1660 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
1ee8da6d CW |
1661 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
1662 | struct drm_file *file_priv); | |
1663 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
1664 | struct drm_file *file_priv); | |
1362b776 | 1665 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
1666 | |
1667 | ||
1668 | /* intel_panel.c */ | |
87440425 | 1669 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1670 | struct drm_display_mode *fixed_mode, |
1671 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1672 | void intel_panel_fini(struct intel_panel *panel); |
1673 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1674 | struct drm_display_mode *adjusted_mode); | |
1675 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1676 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
1677 | int fitting_mode); |
1678 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1679 | struct intel_crtc_state *pipe_config, |
87440425 | 1680 | int fitting_mode); |
6dda730e JN |
1681 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1682 | u32 level, u32 max); | |
fda9ee98 CW |
1683 | int intel_panel_setup_backlight(struct drm_connector *connector, |
1684 | enum pipe pipe); | |
752aa88a JB |
1685 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1686 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1687 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
1650be74 | 1688 | enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv); |
ec9ed197 | 1689 | extern struct drm_display_mode *intel_find_panel_downclock( |
a318b4c4 | 1690 | struct drm_i915_private *dev_priv, |
ec9ed197 VK |
1691 | struct drm_display_mode *fixed_mode, |
1692 | struct drm_connector *connector); | |
e63d87c0 CW |
1693 | |
1694 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) | |
1ebaa0b9 | 1695 | int intel_backlight_device_register(struct intel_connector *connector); |
e63d87c0 CW |
1696 | void intel_backlight_device_unregister(struct intel_connector *connector); |
1697 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
1ebaa0b9 CW |
1698 | static int intel_backlight_device_register(struct intel_connector *connector) |
1699 | { | |
1700 | return 0; | |
1701 | } | |
e63d87c0 CW |
1702 | static inline void intel_backlight_device_unregister(struct intel_connector *connector) |
1703 | { | |
1704 | } | |
1705 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
0962c3c9 | 1706 | |
5f1aae65 | 1707 | |
0bc12bcb | 1708 | /* intel_psr.c */ |
0bc12bcb RV |
1709 | void intel_psr_enable(struct intel_dp *intel_dp); |
1710 | void intel_psr_disable(struct intel_dp *intel_dp); | |
5748b6a1 | 1711 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
20c8838b | 1712 | unsigned frontbuffer_bits); |
5748b6a1 | 1713 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 RV |
1714 | unsigned frontbuffer_bits, |
1715 | enum fb_op_origin origin); | |
c39055b0 | 1716 | void intel_psr_init(struct drm_i915_private *dev_priv); |
5748b6a1 | 1717 | void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, |
20c8838b | 1718 | unsigned frontbuffer_bits); |
0bc12bcb | 1719 | |
9c065a7d DV |
1720 | /* intel_runtime_pm.c */ |
1721 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1722 | void intel_power_domains_fini(struct drm_i915_private *); |
73dfc227 ID |
1723 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
1724 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); | |
8d8c386c | 1725 | void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); |
d7d7c9ee ID |
1726 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
1727 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); | |
f458ebbc | 1728 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9895ad03 DS |
1729 | const char * |
1730 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 1731 | |
f458ebbc DV |
1732 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1733 | enum intel_display_power_domain domain); | |
1734 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1735 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1736 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1737 | enum intel_display_power_domain domain); | |
09731280 ID |
1738 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
1739 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1740 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1741 | enum intel_display_power_domain domain); | |
da5827c3 ID |
1742 | |
1743 | static inline void | |
1744 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) | |
1745 | { | |
1746 | WARN_ONCE(dev_priv->pm.suspended, | |
1747 | "Device suspended during HW access\n"); | |
1748 | } | |
1749 | ||
1750 | static inline void | |
1751 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) | |
1752 | { | |
1753 | assert_rpm_device_not_suspended(dev_priv); | |
1f58c8e7 CW |
1754 | WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count), |
1755 | "RPM wakelock ref not held during HW access"); | |
da5827c3 ID |
1756 | } |
1757 | ||
1f814dac ID |
1758 | /** |
1759 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
1760 | * @dev_priv: i915 device instance | |
1761 | * | |
1762 | * This function disable asserts that check if we hold an RPM wakelock | |
1763 | * reference, while keeping the device-not-suspended checks still enabled. | |
1764 | * It's meant to be used only in special circumstances where our rule about | |
1765 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
1766 | * to this rule at any point where we access the HW or want to keep the HW in | |
1767 | * an active state we must hold an RPM wakelock reference acquired via one of | |
1768 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
1769 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
1770 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
1771 | * users should avoid using this function. | |
1772 | * | |
1773 | * Any calls to this function must have a symmetric call to | |
1774 | * enable_rpm_wakeref_asserts(). | |
1775 | */ | |
1776 | static inline void | |
1777 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1778 | { | |
1779 | atomic_inc(&dev_priv->pm.wakeref_count); | |
1780 | } | |
1781 | ||
1782 | /** | |
1783 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
1784 | * @dev_priv: i915 device instance | |
1785 | * | |
1786 | * This function re-enables the RPM assert checks after disabling them with | |
1787 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
1788 | * circumstances otherwise its use should be avoided. | |
1789 | * | |
1790 | * Any calls to this function must have a symmetric call to | |
1791 | * disable_rpm_wakeref_asserts(). | |
1792 | */ | |
1793 | static inline void | |
1794 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1795 | { | |
1796 | atomic_dec(&dev_priv->pm.wakeref_count); | |
1797 | } | |
1798 | ||
9c065a7d | 1799 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
09731280 | 1800 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
9c065a7d DV |
1801 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
1802 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1803 | ||
d9bc89d9 DV |
1804 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
1805 | ||
e0fce78f VS |
1806 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1807 | bool override, unsigned int mask); | |
b0b33846 VS |
1808 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1809 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
1810 | |
1811 | ||
5f1aae65 | 1812 | /* intel_pm.c */ |
46f16e63 | 1813 | void intel_init_clock_gating(struct drm_i915_private *dev_priv); |
712bf364 | 1814 | void intel_suspend_hw(struct drm_i915_private *dev_priv); |
5db94019 | 1815 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv); |
432081bc | 1816 | void intel_update_watermarks(struct intel_crtc *crtc); |
62d75df7 | 1817 | void intel_init_pm(struct drm_i915_private *dev_priv); |
bb400da9 | 1818 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
192aa181 | 1819 | void intel_pm_setup(struct drm_i915_private *dev_priv); |
87440425 PZ |
1820 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
1821 | void intel_gpu_ips_teardown(void); | |
dc97997a | 1822 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f CW |
1823 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); |
1824 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); | |
dc97997a | 1825 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f | 1826 | void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv); |
dc97997a | 1827 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); |
54b4f68f | 1828 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); |
43cf3bf0 CW |
1829 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1830 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 1831 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1854d5ca | 1832 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
1833 | struct intel_rps_client *rps, |
1834 | unsigned long submitted); | |
91d14251 | 1835 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req); |
6eb1a681 | 1836 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 1837 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 1838 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
1839 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
1840 | struct skl_ddb_allocation *ddb /* out */); | |
bf9d99ad | 1841 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
1842 | struct skl_pipe_wm *out); | |
602ae835 | 1843 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv); |
16dcdc4e PZ |
1844 | bool intel_can_enable_sagv(struct drm_atomic_state *state); |
1845 | int intel_enable_sagv(struct drm_i915_private *dev_priv); | |
1846 | int intel_disable_sagv(struct drm_i915_private *dev_priv); | |
45ece230 | 1847 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
1848 | const struct skl_wm_level *l2); | |
5eff503b ML |
1849 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, |
1850 | const struct skl_ddb_entry *ddb, | |
1851 | int ignore); | |
ed4a6a7c | 1852 | bool ilk_disable_lp_wm(struct drm_device *dev); |
dc97997a CW |
1853 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); |
1854 | static inline int intel_enable_rc6(void) | |
1855 | { | |
1856 | return i915.enable_rc6; | |
1857 | } | |
72662e10 | 1858 | |
5f1aae65 | 1859 | /* intel_sdvo.c */ |
c39055b0 | 1860 | bool intel_sdvo_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 1861 | i915_reg_t reg, enum port port); |
96a02917 | 1862 | |
2b28bb1b | 1863 | |
5f1aae65 | 1864 | /* intel_sprite.c */ |
dfd2e9ab VS |
1865 | int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
1866 | int usecs); | |
580503c7 | 1867 | struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, |
b079bd17 | 1868 | enum pipe pipe, int plane); |
87440425 PZ |
1869 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1870 | struct drm_file *file_priv); | |
34e0adbb | 1871 | void intel_pipe_update_start(struct intel_crtc *crtc); |
51cbaf01 | 1872 | void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); |
5f1aae65 PZ |
1873 | |
1874 | /* intel_tv.c */ | |
c39055b0 | 1875 | void intel_tv_init(struct drm_i915_private *dev_priv); |
20ddf665 | 1876 | |
ea2c67bb | 1877 | /* intel_atomic.c */ |
2545e4a6 MR |
1878 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
1879 | const struct drm_connector_state *state, | |
1880 | struct drm_property *property, | |
1881 | uint64_t *val); | |
1356837e MR |
1882 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
1883 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
1884 | struct drm_crtc_state *state); | |
de419ab6 ML |
1885 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
1886 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
de419ab6 | 1887 | |
10f81c19 ACO |
1888 | static inline struct intel_crtc_state * |
1889 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
1890 | struct intel_crtc *crtc) | |
1891 | { | |
1892 | struct drm_crtc_state *crtc_state; | |
1893 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
1894 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 1895 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
1896 | |
1897 | return to_intel_crtc_state(crtc_state); | |
1898 | } | |
e3bddded | 1899 | |
ccc24b39 MK |
1900 | static inline struct intel_crtc_state * |
1901 | intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state, | |
1902 | struct intel_crtc *crtc) | |
1903 | { | |
1904 | struct drm_crtc_state *crtc_state; | |
1905 | ||
1906 | crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base); | |
1907 | ||
1908 | if (crtc_state) | |
1909 | return to_intel_crtc_state(crtc_state); | |
1910 | else | |
1911 | return NULL; | |
1912 | } | |
1913 | ||
e3bddded ML |
1914 | static inline struct intel_plane_state * |
1915 | intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, | |
1916 | struct intel_plane *plane) | |
1917 | { | |
1918 | struct drm_plane_state *plane_state; | |
1919 | ||
1920 | plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); | |
1921 | ||
1922 | return to_intel_plane_state(plane_state); | |
1923 | } | |
1924 | ||
6ebc6923 ACO |
1925 | int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, |
1926 | struct intel_crtc *intel_crtc, | |
1927 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
1928 | |
1929 | /* intel_atomic_plane.c */ | |
8e7d688b | 1930 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
ea2c67bb MR |
1931 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
1932 | void intel_plane_destroy_state(struct drm_plane *plane, | |
1933 | struct drm_plane_state *state); | |
1934 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
f79f2692 ML |
1935 | int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, |
1936 | struct intel_plane_state *intel_state); | |
ea2c67bb | 1937 | |
8563b1e8 LL |
1938 | /* intel_color.c */ |
1939 | void intel_color_init(struct drm_crtc *crtc); | |
82cf435b | 1940 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
b95c5321 ML |
1941 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
1942 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); | |
8563b1e8 | 1943 | |
dbe9e61b SS |
1944 | /* intel_lspcon.c */ |
1945 | bool lspcon_init(struct intel_digital_port *intel_dig_port); | |
910530c0 | 1946 | void lspcon_resume(struct intel_lspcon *lspcon); |
357c0ae9 | 1947 | void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); |
731035fe TV |
1948 | |
1949 | /* intel_pipe_crc.c */ | |
1950 | int intel_pipe_crc_create(struct drm_minor *minor); | |
8c6b709d TV |
1951 | #ifdef CONFIG_DEBUG_FS |
1952 | int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, | |
1953 | size_t *values_cnt); | |
1954 | #else | |
1955 | #define intel_crtc_set_crc_source NULL | |
1956 | #endif | |
731035fe | 1957 | extern const struct file_operations i915_display_crc_ctl_fops; |
79e53945 | 1958 | #endif /* __INTEL_DRV_H__ */ |