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KVM: VMX: Split segments reload in vmx_load_host_state()
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
6aa8b732 20#include "vmx.h"
e495606d
AK		 21#include "segment_descriptor.h"
22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
07031e14 27#include <linux/profile.h>
e8edc6e0 28#include <linux/sched.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
a2fa3e9f
GH		 36struct vmcs {
37 u32 revision_id;
38 u32 abort;
39 char data[0];
40};
41
42struct vcpu_vmx {
fb3f0f51 43 struct kvm_vcpu vcpu;
a2fa3e9f
GH		 44 int launched;
45 struct kvm_msr_entry *guest_msrs;
46 struct kvm_msr_entry *host_msrs;
47 int nmsrs;
48 int save_nmsrs;
49 int msr_offset_efer;
50#ifdef CONFIG_X86_64
51 int msr_offset_kernel_gs_base;
52#endif
53 struct vmcs *vmcs;
54 struct {
55 int loaded;
56 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 57 int gs_ldt_reload_needed;
58 int fs_reload_needed;
a2fa3e9f
GH		 59 }host_state;
60
61};
62
63static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
64{
fb3f0f51 65 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 66}
67
75880a01
AK		 68static int init_rmode_tss(struct kvm *kvm);
69
6aa8b732
AK		 70static DEFINE_PER_CPU(struct vmcs *, vmxarea);
71static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
72
fdef3ad1
HQ		 73static struct page *vmx_io_bitmap_a;
74static struct page *vmx_io_bitmap_b;
75
2cc51560 76#define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
6aa8b732 77
1c3d14fe 78static struct vmcs_config {
6aa8b732
AK		 79 int size;
80 int order;
81 u32 revision_id;
1c3d14fe
YS		 82 u32 pin_based_exec_ctrl;
83 u32 cpu_based_exec_ctrl;
84 u32 vmexit_ctrl;
85 u32 vmentry_ctrl;
86} vmcs_config;
6aa8b732
AK		 87
88#define VMX_SEGMENT_FIELD(seg) \
89 [VCPU_SREG_##seg] = { \
90 .selector = GUEST_##seg##_SELECTOR, \
91 .base = GUEST_##seg##_BASE, \
92 .limit = GUEST_##seg##_LIMIT, \
93 .ar_bytes = GUEST_##seg##_AR_BYTES, \
94 }
95
96static struct kvm_vmx_segment_field {
97 unsigned selector;
98 unsigned base;
99 unsigned limit;
100 unsigned ar_bytes;
101} kvm_vmx_segment_fields[] = {
102 VMX_SEGMENT_FIELD(CS),
103 VMX_SEGMENT_FIELD(DS),
104 VMX_SEGMENT_FIELD(ES),
105 VMX_SEGMENT_FIELD(FS),
106 VMX_SEGMENT_FIELD(GS),
107 VMX_SEGMENT_FIELD(SS),
108 VMX_SEGMENT_FIELD(TR),
109 VMX_SEGMENT_FIELD(LDTR),
110};
111
4d56c8a7
AK		 112/*
113 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
114 * away by decrementing the array size.
115 */
6aa8b732 116static const u32 vmx_msr_index[] = {
05b3e0c2 117#ifdef CONFIG_X86_64
6aa8b732
AK		 118 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
119#endif
120 MSR_EFER, MSR_K6_STAR,
121};
9d8f549d 122#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 123
a2fa3e9f
GH		 124static void load_msrs(struct kvm_msr_entry *e, int n)
125{
126 int i;
127
128 for (i = 0; i < n; ++i)
129 wrmsrl(e[i].index, e[i].data);
130}
131
132static void save_msrs(struct kvm_msr_entry *e, int n)
133{
134 int i;
135
136 for (i = 0; i < n; ++i)
137 rdmsrl(e[i].index, e[i].data);
138}
139
140static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
2cc51560
ED		 141{
142 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
143}
144
8b9cf98c 145static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
2cc51560 146{
a2fa3e9f
GH		 147 int efer_offset = vmx->msr_offset_efer;
148 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
149 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560
ED		 150}
151
6aa8b732
AK		 152static inline int is_page_fault(u32 intr_info)
153{
154 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155 INTR_INFO_VALID_MASK)) ==
156 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
157}
158
2ab455cc
AL		 159static inline int is_no_device(u32 intr_info)
160{
161 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162 INTR_INFO_VALID_MASK)) ==
163 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
164}
165
6aa8b732
AK		 166static inline int is_external_interrupt(u32 intr_info)
167{
168 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
169 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
170}
171
8b9cf98c 172static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 173{
174 int i;
175
a2fa3e9f
GH		 176 for (i = 0; i < vmx->nmsrs; ++i)
177 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 178 return i;
179 return -1;
180}
181
8b9cf98c 182static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 183{
184 int i;
185
8b9cf98c 186 i = __find_msr_index(vmx, msr);
a75beee6 187 if (i >= 0)
a2fa3e9f 188 return &vmx->guest_msrs[i];
8b6d44c7 189 return NULL;
7725f0ba
AK		 190}
191
6aa8b732
AK		 192static void vmcs_clear(struct vmcs *vmcs)
193{
194 u64 phys_addr = __pa(vmcs);
195 u8 error;
196
197 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
198 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
199 : "cc", "memory");
200 if (error)
201 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
202 vmcs, phys_addr);
203}
204
205static void __vcpu_clear(void *arg)
206{
8b9cf98c 207 struct vcpu_vmx *vmx = arg;
d3b2c338 208 int cpu = raw_smp_processor_id();
6aa8b732 209
8b9cf98c 210 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 211 vmcs_clear(vmx->vmcs);
212 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 213 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 214 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 215}
216
8b9cf98c 217static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 218{
8b9cf98c
RR		 219 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
220 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
221 vmx, 0, 1);
8d0be2b3 222 else
8b9cf98c
RR		 223 __vcpu_clear(vmx);
224 vmx->launched = 0;
8d0be2b3
AK		 225}
226
6aa8b732
AK		 227static unsigned long vmcs_readl(unsigned long field)
228{
229 unsigned long value;
230
231 asm volatile (ASM_VMX_VMREAD_RDX_RAX
232 : "=a"(value) : "d"(field) : "cc");
233 return value;
234}
235
236static u16 vmcs_read16(unsigned long field)
237{
238 return vmcs_readl(field);
239}
240
241static u32 vmcs_read32(unsigned long field)
242{
243 return vmcs_readl(field);
244}
245
246static u64 vmcs_read64(unsigned long field)
247{
05b3e0c2 248#ifdef CONFIG_X86_64
6aa8b732
AK		 249 return vmcs_readl(field);
250#else
251 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
252#endif
253}
254
e52de1b8
AK		 255static noinline void vmwrite_error(unsigned long field, unsigned long value)
256{
257 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
258 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
259 dump_stack();
260}
261
6aa8b732
AK		 262static void vmcs_writel(unsigned long field, unsigned long value)
263{
264 u8 error;
265
266 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
267 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 268 if (unlikely(error))
269 vmwrite_error(field, value);
6aa8b732
AK		 270}
271
272static void vmcs_write16(unsigned long field, u16 value)
273{
274 vmcs_writel(field, value);
275}
276
277static void vmcs_write32(unsigned long field, u32 value)
278{
279 vmcs_writel(field, value);
280}
281
282static void vmcs_write64(unsigned long field, u64 value)
283{
05b3e0c2 284#ifdef CONFIG_X86_64
6aa8b732
AK		 285 vmcs_writel(field, value);
286#else
287 vmcs_writel(field, value);
288 asm volatile ("");
289 vmcs_writel(field+1, value >> 32);
290#endif
291}
292
2ab455cc
AL		 293static void vmcs_clear_bits(unsigned long field, u32 mask)
294{
295 vmcs_writel(field, vmcs_readl(field) & ~mask);
296}
297
298static void vmcs_set_bits(unsigned long field, u32 mask)
299{
300 vmcs_writel(field, vmcs_readl(field) | mask);
301}
302
abd3f2d6
AK		 303static void update_exception_bitmap(struct kvm_vcpu *vcpu)
304{
305 u32 eb;
306
307 eb = 1u << PF_VECTOR;
308 if (!vcpu->fpu_active)
309 eb |= 1u << NM_VECTOR;
310 if (vcpu->guest_debug.enabled)
311 eb |= 1u << 1;
312 if (vcpu->rmode.active)
313 eb = ~0;
314 vmcs_write32(EXCEPTION_BITMAP, eb);
315}
316
33ed6329
AK		 317static void reload_tss(void)
318{
319#ifndef CONFIG_X86_64
320
321 /*
322 * VT restores TR but not its size. Useless.
323 */
324 struct descriptor_table gdt;
325 struct segment_descriptor *descs;
326
327 get_gdt(&gdt);
328 descs = (void *)gdt.base;
329 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
330 load_TR_desc();
331#endif
332}
333
8b9cf98c 334static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560
ED		 335{
336 u64 trans_efer;
a2fa3e9f 337 int efer_offset = vmx->msr_offset_efer;
2cc51560 338
a2fa3e9f 339 trans_efer = vmx->host_msrs[efer_offset].data;
2cc51560 340 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
a2fa3e9f 341 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560 342 wrmsrl(MSR_EFER, trans_efer);
8b9cf98c 343 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 344}
345
8b9cf98c 346static void vmx_save_host_state(struct vcpu_vmx *vmx)
33ed6329 347{
a2fa3e9f 348 if (vmx->host_state.loaded)
33ed6329
AK		 349 return;
350
a2fa3e9f 351 vmx->host_state.loaded = 1;
33ed6329
AK		 352 /*
353 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
354 * allow segment selectors with cpl > 0 or ti == 1.
355 */
a2fa3e9f 356 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 357 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 358 vmx->host_state.fs_sel = read_fs();
152d3f2f 359 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 360 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 361 vmx->host_state.fs_reload_needed = 0;
362 } else {
33ed6329 363 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 364 vmx->host_state.fs_reload_needed = 1;
33ed6329 365 }
a2fa3e9f
GH		 366 vmx->host_state.gs_sel = read_gs();
367 if (!(vmx->host_state.gs_sel & 7))
368 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 369 else {
370 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 371 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 372 }
373
374#ifdef CONFIG_X86_64
375 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
376 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
377#else
a2fa3e9f
GH		 378 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
379 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 380#endif
707c0874
AK		 381
382#ifdef CONFIG_X86_64
8b9cf98c 383 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 384 save_msrs(vmx->host_msrs +
385 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 386 }
387#endif
a2fa3e9f 388 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
8b9cf98c
RR		 389 if (msr_efer_need_save_restore(vmx))
390 load_transition_efer(vmx);
33ed6329
AK		 391}
392
8b9cf98c 393static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 394{
15ad7146 395 unsigned long flags;
33ed6329 396
a2fa3e9f 397 if (!vmx->host_state.loaded)
33ed6329
AK		 398 return;
399
a2fa3e9f 400 vmx->host_state.loaded = 0;
152d3f2f 401 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 402 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 403 if (vmx->host_state.gs_ldt_reload_needed) {
404 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 405 /*
406 * If we have to reload gs, we must take care to
407 * preserve our gs base.
408 */
15ad7146 409 local_irq_save(flags);
a2fa3e9f 410 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 411#ifdef CONFIG_X86_64
412 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
413#endif
15ad7146 414 local_irq_restore(flags);
33ed6329 415 }
152d3f2f 416 reload_tss();
a2fa3e9f
GH		 417 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
418 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
8b9cf98c 419 if (msr_efer_need_save_restore(vmx))
a2fa3e9f 420 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
33ed6329
AK		 421}
422
6aa8b732
AK		 423/*
424 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
425 * vcpu mutex is already taken.
426 */
15ad7146 427static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 428{
a2fa3e9f
GH		 429 struct vcpu_vmx *vmx = to_vmx(vcpu);
430 u64 phys_addr = __pa(vmx->vmcs);
7700270e 431 u64 tsc_this, delta;
6aa8b732 432
8d0be2b3 433 if (vcpu->cpu != cpu)
8b9cf98c 434 vcpu_clear(vmx);
6aa8b732 435
a2fa3e9f 436 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 437 u8 error;
438
a2fa3e9f 439 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 440 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
441 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
442 : "cc");
443 if (error)
444 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 445 vmx->vmcs, phys_addr);
6aa8b732
AK		 446 }
447
448 if (vcpu->cpu != cpu) {
449 struct descriptor_table dt;
450 unsigned long sysenter_esp;
451
452 vcpu->cpu = cpu;
453 /*
454 * Linux uses per-cpu TSS and GDT, so set these when switching
455 * processors.
456 */
457 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
458 get_gdt(&dt);
459 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
460
461 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
462 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 463
464 /*
465 * Make sure the time stamp counter is monotonous.
466 */
467 rdtscll(tsc_this);
468 delta = vcpu->host_tsc - tsc_this;
469 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 470 }
6aa8b732
AK		 471}
472
473static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
474{
8b9cf98c 475 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 476 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 477}
478
5fd86fcf
AK		 479static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
480{
481 if (vcpu->fpu_active)
482 return;
483 vcpu->fpu_active = 1;
707d92fa
RR		 484 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
485 if (vcpu->cr0 & X86_CR0_TS)
486 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 487 update_exception_bitmap(vcpu);
488}
489
490static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
491{
492 if (!vcpu->fpu_active)
493 return;
494 vcpu->fpu_active = 0;
707d92fa 495 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 496 update_exception_bitmap(vcpu);
497}
498
774c47f1
AK		 499static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
500{
8b9cf98c 501 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 502}
503
6aa8b732
AK		 504static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
505{
506 return vmcs_readl(GUEST_RFLAGS);
507}
508
509static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
510{
511 vmcs_writel(GUEST_RFLAGS, rflags);
512}
513
514static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
515{
516 unsigned long rip;
517 u32 interruptibility;
518
519 rip = vmcs_readl(GUEST_RIP);
520 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
521 vmcs_writel(GUEST_RIP, rip);
522
523 /*
524 * We emulated an instruction, so temporary interrupt blocking
525 * should be removed, if set.
526 */
527 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
528 if (interruptibility & 3)
529 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
530 interruptibility & ~3);
c1150d8c 531 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 532}
533
534static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
535{
536 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
537 vmcs_readl(GUEST_RIP));
538 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
539 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
540 GP_VECTOR |
541 INTR_TYPE_EXCEPTION |
542 INTR_INFO_DELIEVER_CODE_MASK |
543 INTR_INFO_VALID_MASK);
544}
545
a75beee6
ED		 546/*
547 * Swap MSR entry in host/guest MSR entry array.
548 */
54e11fa1 549#ifdef CONFIG_X86_64
8b9cf98c 550static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 551{
a2fa3e9f
GH		 552 struct kvm_msr_entry tmp;
553
554 tmp = vmx->guest_msrs[to];
555 vmx->guest_msrs[to] = vmx->guest_msrs[from];
556 vmx->guest_msrs[from] = tmp;
557 tmp = vmx->host_msrs[to];
558 vmx->host_msrs[to] = vmx->host_msrs[from];
559 vmx->host_msrs[from] = tmp;
a75beee6 560}
54e11fa1 561#endif
a75beee6 562
e38aea3e
AK		 563/*
564 * Set up the vmcs to automatically save and restore system
565 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
566 * mode, as fiddling with msrs is very expensive.
567 */
8b9cf98c 568static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 569{
2cc51560 570 int save_nmsrs;
e38aea3e 571
a75beee6
ED		 572 save_nmsrs = 0;
573#ifdef CONFIG_X86_64
8b9cf98c 574 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 575 int index;
576
8b9cf98c 577 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 578 if (index >= 0)
8b9cf98c
RR		 579 move_msr_up(vmx, index, save_nmsrs++);
580 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 581 if (index >= 0)
8b9cf98c
RR		 582 move_msr_up(vmx, index, save_nmsrs++);
583 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 584 if (index >= 0)
8b9cf98c
RR		 585 move_msr_up(vmx, index, save_nmsrs++);
586 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 587 if (index >= 0)
8b9cf98c 588 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 589 /*
590 * MSR_K6_STAR is only needed on long mode guests, and only
591 * if efer.sce is enabled.
592 */
8b9cf98c
RR		 593 index = __find_msr_index(vmx, MSR_K6_STAR);
594 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
595 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 596 }
597#endif
a2fa3e9f 598 vmx->save_nmsrs = save_nmsrs;
e38aea3e 599
4d56c8a7 600#ifdef CONFIG_X86_64
a2fa3e9f 601 vmx->msr_offset_kernel_gs_base =
8b9cf98c 602 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 603#endif
8b9cf98c 604 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 605}
606
6aa8b732
AK		 607/*
608 * reads and returns guest's timestamp counter "register"
609 * guest_tsc = host_tsc + tsc_offset -- 21.3
610 */
611static u64 guest_read_tsc(void)
612{
613 u64 host_tsc, tsc_offset;
614
615 rdtscll(host_tsc);
616 tsc_offset = vmcs_read64(TSC_OFFSET);
617 return host_tsc + tsc_offset;
618}
619
620/*
621 * writes 'guest_tsc' into guest's timestamp counter "register"
622 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
623 */
624static void guest_write_tsc(u64 guest_tsc)
625{
626 u64 host_tsc;
627
628 rdtscll(host_tsc);
629 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
630}
631
6aa8b732
AK		 632/*
633 * Reads an msr value (of 'msr_index') into 'pdata'.
634 * Returns 0 on success, non-0 otherwise.
635 * Assumes vcpu_load() was already called.
636 */
637static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
638{
639 u64 data;
a2fa3e9f 640 struct kvm_msr_entry *msr;
6aa8b732
AK		 641
642 if (!pdata) {
643 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
644 return -EINVAL;
645 }
646
647 switch (msr_index) {
05b3e0c2 648#ifdef CONFIG_X86_64
6aa8b732
AK		 649 case MSR_FS_BASE:
650 data = vmcs_readl(GUEST_FS_BASE);
651 break;
652 case MSR_GS_BASE:
653 data = vmcs_readl(GUEST_GS_BASE);
654 break;
655 case MSR_EFER:
3bab1f5d 656 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 657#endif
658 case MSR_IA32_TIME_STAMP_COUNTER:
659 data = guest_read_tsc();
660 break;
661 case MSR_IA32_SYSENTER_CS:
662 data = vmcs_read32(GUEST_SYSENTER_CS);
663 break;
664 case MSR_IA32_SYSENTER_EIP:
f5b42c33 665 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 666 break;
667 case MSR_IA32_SYSENTER_ESP:
f5b42c33 668 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 669 break;
6aa8b732 670 default:
8b9cf98c 671 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 672 if (msr) {
673 data = msr->data;
674 break;
6aa8b732 675 }
3bab1f5d 676 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 677 }
678
679 *pdata = data;
680 return 0;
681}
682
683/*
684 * Writes msr value into into the appropriate "register".
685 * Returns 0 on success, non-0 otherwise.
686 * Assumes vcpu_load() was already called.
687 */
688static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
689{
a2fa3e9f
GH		 690 struct vcpu_vmx *vmx = to_vmx(vcpu);
691 struct kvm_msr_entry *msr;
2cc51560
ED		 692 int ret = 0;
693
6aa8b732 694 switch (msr_index) {
05b3e0c2 695#ifdef CONFIG_X86_64
3bab1f5d 696 case MSR_EFER:
2cc51560 697 ret = kvm_set_msr_common(vcpu, msr_index, data);
a2fa3e9f 698 if (vmx->host_state.loaded)
8b9cf98c 699 load_transition_efer(vmx);
2cc51560 700 break;
6aa8b732
AK		 701 case MSR_FS_BASE:
702 vmcs_writel(GUEST_FS_BASE, data);
703 break;
704 case MSR_GS_BASE:
705 vmcs_writel(GUEST_GS_BASE, data);
706 break;
707#endif
708 case MSR_IA32_SYSENTER_CS:
709 vmcs_write32(GUEST_SYSENTER_CS, data);
710 break;
711 case MSR_IA32_SYSENTER_EIP:
f5b42c33 712 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 713 break;
714 case MSR_IA32_SYSENTER_ESP:
f5b42c33 715 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 716 break;
d27d4aca 717 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 718 guest_write_tsc(data);
719 break;
6aa8b732 720 default:
8b9cf98c 721 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 722 if (msr) {
723 msr->data = data;
a2fa3e9f
GH		 724 if (vmx->host_state.loaded)
725 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 726 break;
6aa8b732 727 }
2cc51560 728 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 729 }
730
2cc51560 731 return ret;
6aa8b732
AK		 732}
733
734/*
735 * Sync the rsp and rip registers into the vcpu structure. This allows
736 * registers to be accessed by indexing vcpu->regs.
737 */
738static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
739{
740 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
741 vcpu->rip = vmcs_readl(GUEST_RIP);
742}
743
744/*
745 * Syncs rsp and rip back into the vmcs. Should be called after possible
746 * modification.
747 */
748static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
749{
750 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
751 vmcs_writel(GUEST_RIP, vcpu->rip);
752}
753
754static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
755{
756 unsigned long dr7 = 0x400;
6aa8b732
AK		 757 int old_singlestep;
758
6aa8b732
AK		 759 old_singlestep = vcpu->guest_debug.singlestep;
760
761 vcpu->guest_debug.enabled = dbg->enabled;
762 if (vcpu->guest_debug.enabled) {
763 int i;
764
765 dr7 |= 0x200; /* exact */
766 for (i = 0; i < 4; ++i) {
767 if (!dbg->breakpoints[i].enabled)
768 continue;
769 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
770 dr7 |= 2 << (i*2); /* global enable */
771 dr7 |= 0 << (i*4+16); /* execution breakpoint */
772 }
773
6aa8b732 774 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 775 } else
6aa8b732 776 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 777
778 if (old_singlestep && !vcpu->guest_debug.singlestep) {
779 unsigned long flags;
780
781 flags = vmcs_readl(GUEST_RFLAGS);
782 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
783 vmcs_writel(GUEST_RFLAGS, flags);
784 }
785
abd3f2d6 786 update_exception_bitmap(vcpu);
6aa8b732
AK		 787 vmcs_writel(GUEST_DR7, dr7);
788
789 return 0;
790}
791
792static __init int cpu_has_kvm_support(void)
793{
794 unsigned long ecx = cpuid_ecx(1);
795 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
796}
797
798static __init int vmx_disabled_by_bios(void)
799{
800 u64 msr;
801
802 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 803 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
804 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
805 == MSR_IA32_FEATURE_CONTROL_LOCKED;
806 /* locked but not enabled */
6aa8b732
AK		 807}
808
774c47f1 809static void hardware_enable(void *garbage)
6aa8b732
AK		 810{
811 int cpu = raw_smp_processor_id();
812 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
813 u64 old;
814
815 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 816 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
817 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
818 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
819 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 820 /* enable and lock */
62b3ffb8
YS		 821 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
822 MSR_IA32_FEATURE_CONTROL_LOCKED |
823 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 824 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 825 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
826 : "memory", "cc");
827}
828
829static void hardware_disable(void *garbage)
830{
831 asm volatile (ASM_VMX_VMXOFF : : : "cc");
832}
833
1c3d14fe
YS		 834static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
835 u32 msr, u32* result)
836{
837 u32 vmx_msr_low, vmx_msr_high;
838 u32 ctl = ctl_min | ctl_opt;
839
840 rdmsr(msr, vmx_msr_low, vmx_msr_high);
841
842 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
843 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
844
845 /* Ensure minimum (required) set of control bits are supported. */
846 if (ctl_min & ~ctl)
002c7f7c 847 return -EIO;
1c3d14fe
YS		 848
849 *result = ctl;
850 return 0;
851}
852
002c7f7c 853static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 854{
855 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 856 u32 min, opt;
857 u32 _pin_based_exec_control = 0;
858 u32 _cpu_based_exec_control = 0;
859 u32 _vmexit_control = 0;
860 u32 _vmentry_control = 0;
861
862 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
863 opt = 0;
864 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
865 &_pin_based_exec_control) < 0)
002c7f7c 866 return -EIO;
1c3d14fe
YS		 867
868 min = CPU_BASED_HLT_EXITING |
869#ifdef CONFIG_X86_64
870 CPU_BASED_CR8_LOAD_EXITING |
871 CPU_BASED_CR8_STORE_EXITING |
872#endif
873 CPU_BASED_USE_IO_BITMAPS |
874 CPU_BASED_MOV_DR_EXITING |
875 CPU_BASED_USE_TSC_OFFSETING;
876 opt = 0;
877 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
878 &_cpu_based_exec_control) < 0)
002c7f7c 879 return -EIO;
1c3d14fe
YS		 880
881 min = 0;
882#ifdef CONFIG_X86_64
883 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
884#endif
885 opt = 0;
886 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
887 &_vmexit_control) < 0)
002c7f7c 888 return -EIO;
1c3d14fe
YS		 889
890 min = opt = 0;
891 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
892 &_vmentry_control) < 0)
002c7f7c 893 return -EIO;
6aa8b732 894
c68876fd 895 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 896
897 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
898 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 899 return -EIO;
1c3d14fe
YS		 900
901#ifdef CONFIG_X86_64
902 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
903 if (vmx_msr_high & (1u<<16))
002c7f7c 904 return -EIO;
1c3d14fe
YS		 905#endif
906
907 /* Require Write-Back (WB) memory type for VMCS accesses. */
908 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 909 return -EIO;
1c3d14fe 910
002c7f7c
YS		 911 vmcs_conf->size = vmx_msr_high & 0x1fff;
912 vmcs_conf->order = get_order(vmcs_config.size);
913 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 914
002c7f7c
YS		 915 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
916 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
917 vmcs_conf->vmexit_ctrl = _vmexit_control;
918 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 919
920 return 0;
c68876fd 921}
6aa8b732
AK		 922
923static struct vmcs *alloc_vmcs_cpu(int cpu)
924{
925 int node = cpu_to_node(cpu);
926 struct page *pages;
927 struct vmcs *vmcs;
928
1c3d14fe 929 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 930 if (!pages)
931 return NULL;
932 vmcs = page_address(pages);
1c3d14fe
YS		 933 memset(vmcs, 0, vmcs_config.size);
934 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 935 return vmcs;
936}
937
938static struct vmcs *alloc_vmcs(void)
939{
d3b2c338 940 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 941}
942
943static void free_vmcs(struct vmcs *vmcs)
944{
1c3d14fe 945 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 946}
947
39959588 948static void free_kvm_area(void)
6aa8b732
AK		 949{
950 int cpu;
951
952 for_each_online_cpu(cpu)
953 free_vmcs(per_cpu(vmxarea, cpu));
954}
955
6aa8b732
AK		 956static __init int alloc_kvm_area(void)
957{
958 int cpu;
959
960 for_each_online_cpu(cpu) {
961 struct vmcs *vmcs;
962
963 vmcs = alloc_vmcs_cpu(cpu);
964 if (!vmcs) {
965 free_kvm_area();
966 return -ENOMEM;
967 }
968
969 per_cpu(vmxarea, cpu) = vmcs;
970 }
971 return 0;
972}
973
974static __init int hardware_setup(void)
975{
002c7f7c
YS		 976 if (setup_vmcs_config(&vmcs_config) < 0)
977 return -EIO;
6aa8b732
AK		 978 return alloc_kvm_area();
979}
980
981static __exit void hardware_unsetup(void)
982{
983 free_kvm_area();
984}
985
6aa8b732
AK		 986static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
987{
988 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
989
6af11b9e 990 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 991 vmcs_write16(sf->selector, save->selector);
992 vmcs_writel(sf->base, save->base);
993 vmcs_write32(sf->limit, save->limit);
994 vmcs_write32(sf->ar_bytes, save->ar);
995 } else {
996 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
997 << AR_DPL_SHIFT;
998 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
999 }
1000}
1001
1002static void enter_pmode(struct kvm_vcpu *vcpu)
1003{
1004 unsigned long flags;
1005
1006 vcpu->rmode.active = 0;
1007
1008 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1009 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1010 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1011
1012 flags = vmcs_readl(GUEST_RFLAGS);
1013 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
1014 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1015 vmcs_writel(GUEST_RFLAGS, flags);
1016
66aee91a
RR		 1017 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1018 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1019
1020 update_exception_bitmap(vcpu);
1021
1022 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1023 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1024 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1025 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1026
1027 vmcs_write16(GUEST_SS_SELECTOR, 0);
1028 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1029
1030 vmcs_write16(GUEST_CS_SELECTOR,
1031 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1032 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1033}
1034
33f5fa16 1035static gva_t rmode_tss_base(struct kvm* kvm)
6aa8b732
AK		 1036{
1037 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1038 return base_gfn << PAGE_SHIFT;
1039}
1040
1041static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1042{
1043 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1044
1045 save->selector = vmcs_read16(sf->selector);
1046 save->base = vmcs_readl(sf->base);
1047 save->limit = vmcs_read32(sf->limit);
1048 save->ar = vmcs_read32(sf->ar_bytes);
1049 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1050 vmcs_write32(sf->limit, 0xffff);
1051 vmcs_write32(sf->ar_bytes, 0xf3);
1052}
1053
1054static void enter_rmode(struct kvm_vcpu *vcpu)
1055{
1056 unsigned long flags;
1057
1058 vcpu->rmode.active = 1;
1059
1060 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1061 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1062
1063 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1064 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1065
1066 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1067 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1068
1069 flags = vmcs_readl(GUEST_RFLAGS);
1070 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1071
1072 flags |= IOPL_MASK | X86_EFLAGS_VM;
1073
1074 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1075 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1076 update_exception_bitmap(vcpu);
1077
1078 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1079 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1080 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1081
1082 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1083 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1084 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1085 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1086 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1087
1088 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1089 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1090 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1091 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01
AK		 1092
1093 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1094}
1095
05b3e0c2 1096#ifdef CONFIG_X86_64
6aa8b732
AK		 1097
1098static void enter_lmode(struct kvm_vcpu *vcpu)
1099{
1100 u32 guest_tr_ar;
1101
1102 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1103 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1104 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1105 __FUNCTION__);
1106 vmcs_write32(GUEST_TR_AR_BYTES,
1107 (guest_tr_ar & ~AR_TYPE_MASK)
1108 | AR_TYPE_BUSY_64_TSS);
1109 }
1110
1111 vcpu->shadow_efer |= EFER_LMA;
1112
8b9cf98c 1113 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1114 vmcs_write32(VM_ENTRY_CONTROLS,
1115 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1116 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1117}
1118
1119static void exit_lmode(struct kvm_vcpu *vcpu)
1120{
1121 vcpu->shadow_efer &= ~EFER_LMA;
1122
1123 vmcs_write32(VM_ENTRY_CONTROLS,
1124 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1125 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1126}
1127
1128#endif
1129
25c4c276 1130static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1131{
399badf3
AK		 1132 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1133 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1134}
1135
6aa8b732
AK		 1136static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1137{
5fd86fcf
AK		 1138 vmx_fpu_deactivate(vcpu);
1139
707d92fa 1140 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1141 enter_pmode(vcpu);
1142
707d92fa 1143 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1144 enter_rmode(vcpu);
1145
05b3e0c2 1146#ifdef CONFIG_X86_64
6aa8b732 1147 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1148 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1149 enter_lmode(vcpu);
707d92fa 1150 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1151 exit_lmode(vcpu);
1152 }
1153#endif
1154
1155 vmcs_writel(CR0_READ_SHADOW, cr0);
1156 vmcs_writel(GUEST_CR0,
1157 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1158 vcpu->cr0 = cr0;
5fd86fcf 1159
707d92fa 1160 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1161 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1162}
1163
6aa8b732
AK		 1164static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1165{
1166 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1167 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1168 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1169}
1170
1171static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1172{
1173 vmcs_writel(CR4_READ_SHADOW, cr4);
1174 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1175 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1176 vcpu->cr4 = cr4;
1177}
1178
05b3e0c2 1179#ifdef CONFIG_X86_64
6aa8b732
AK		 1180
1181static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1182{
8b9cf98c
RR		 1183 struct vcpu_vmx *vmx = to_vmx(vcpu);
1184 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1185
1186 vcpu->shadow_efer = efer;
1187 if (efer & EFER_LMA) {
1188 vmcs_write32(VM_ENTRY_CONTROLS,
1189 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1190 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1191 msr->data = efer;
1192
1193 } else {
1194 vmcs_write32(VM_ENTRY_CONTROLS,
1195 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1196 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1197
1198 msr->data = efer & ~EFER_LME;
1199 }
8b9cf98c 1200 setup_msrs(vmx);
6aa8b732
AK		 1201}
1202
1203#endif
1204
1205static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1206{
1207 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1208
1209 return vmcs_readl(sf->base);
1210}
1211
1212static void vmx_get_segment(struct kvm_vcpu *vcpu,
1213 struct kvm_segment *var, int seg)
1214{
1215 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1216 u32 ar;
1217
1218 var->base = vmcs_readl(sf->base);
1219 var->limit = vmcs_read32(sf->limit);
1220 var->selector = vmcs_read16(sf->selector);
1221 ar = vmcs_read32(sf->ar_bytes);
1222 if (ar & AR_UNUSABLE_MASK)
1223 ar = 0;
1224 var->type = ar & 15;
1225 var->s = (ar >> 4) & 1;
1226 var->dpl = (ar >> 5) & 3;
1227 var->present = (ar >> 7) & 1;
1228 var->avl = (ar >> 12) & 1;
1229 var->l = (ar >> 13) & 1;
1230 var->db = (ar >> 14) & 1;
1231 var->g = (ar >> 15) & 1;
1232 var->unusable = (ar >> 16) & 1;
1233}
1234
653e3108 1235static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1236{
6aa8b732
AK		 1237 u32 ar;
1238
653e3108 1239 if (var->unusable)
6aa8b732
AK		 1240 ar = 1 << 16;
1241 else {
1242 ar = var->type & 15;
1243 ar |= (var->s & 1) << 4;
1244 ar |= (var->dpl & 3) << 5;
1245 ar |= (var->present & 1) << 7;
1246 ar |= (var->avl & 1) << 12;
1247 ar |= (var->l & 1) << 13;
1248 ar |= (var->db & 1) << 14;
1249 ar |= (var->g & 1) << 15;
1250 }
f7fbf1fd
UL		 1251 if (ar == 0) /* a 0 value means unusable */
1252 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1253
1254 return ar;
1255}
1256
1257static void vmx_set_segment(struct kvm_vcpu *vcpu,
1258 struct kvm_segment *var, int seg)
1259{
1260 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1261 u32 ar;
1262
1263 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1264 vcpu->rmode.tr.selector = var->selector;
1265 vcpu->rmode.tr.base = var->base;
1266 vcpu->rmode.tr.limit = var->limit;
1267 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1268 return;
1269 }
1270 vmcs_writel(sf->base, var->base);
1271 vmcs_write32(sf->limit, var->limit);
1272 vmcs_write16(sf->selector, var->selector);
1273 if (vcpu->rmode.active && var->s) {
1274 /*
1275 * Hack real-mode segments into vm86 compatibility.
1276 */
1277 if (var->base == 0xffff0000 && var->selector == 0xf000)
1278 vmcs_writel(sf->base, 0xf0000);
1279 ar = 0xf3;
1280 } else
1281 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1282 vmcs_write32(sf->ar_bytes, ar);
1283}
1284
6aa8b732
AK		 1285static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1286{
1287 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1288
1289 *db = (ar >> 14) & 1;
1290 *l = (ar >> 13) & 1;
1291}
1292
1293static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1294{
1295 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1296 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1297}
1298
1299static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1300{
1301 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1302 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1303}
1304
1305static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1306{
1307 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1308 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1309}
1310
1311static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1312{
1313 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1314 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1315}
1316
1317static int init_rmode_tss(struct kvm* kvm)
1318{
1319 struct page *p1, *p2, *p3;
1320 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1321 char *page;
1322
954bbbc2
AK		 1323 p1 = gfn_to_page(kvm, fn++);
1324 p2 = gfn_to_page(kvm, fn++);
1325 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1326
1327 if (!p1 || !p2 || !p3) {
1328 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1329 return 0;
1330 }
1331
1332 page = kmap_atomic(p1, KM_USER0);
a3870c47 1333 clear_page(page);
6aa8b732
AK		 1334 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1335 kunmap_atomic(page, KM_USER0);
1336
1337 page = kmap_atomic(p2, KM_USER0);
a3870c47 1338 clear_page(page);
6aa8b732
AK		 1339 kunmap_atomic(page, KM_USER0);
1340
1341 page = kmap_atomic(p3, KM_USER0);
a3870c47 1342 clear_page(page);
6aa8b732
AK		 1343 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1344 kunmap_atomic(page, KM_USER0);
1345
1346 return 1;
1347}
1348
6aa8b732
AK		 1349static void seg_setup(int seg)
1350{
1351 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1352
1353 vmcs_write16(sf->selector, 0);
1354 vmcs_writel(sf->base, 0);
1355 vmcs_write32(sf->limit, 0xffff);
1356 vmcs_write32(sf->ar_bytes, 0x93);
1357}
1358
1359/*
1360 * Sets up the vmcs for emulated real mode.
1361 */
8b9cf98c 1362static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1363{
1364 u32 host_sysenter_cs;
1365 u32 junk;
1366 unsigned long a;
1367 struct descriptor_table dt;
1368 int i;
1369 int ret = 0;
cd2276a7 1370 unsigned long kvm_vmx_return;
6aa8b732 1371
8b9cf98c 1372 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1373 ret = -ENOMEM;
1374 goto out;
1375 }
1376
8b9cf98c
RR		 1377 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1378 vmx->vcpu.cr8 = 0;
1379 vmx->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1380 if (vmx->vcpu.vcpu_id == 0)
1381 vmx->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1382
8b9cf98c 1383 fx_init(&vmx->vcpu);
6aa8b732
AK		 1384
1385 /*
1386 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1387 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1388 */
1389 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1390 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1391 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1392 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1393
1394 seg_setup(VCPU_SREG_DS);
1395 seg_setup(VCPU_SREG_ES);
1396 seg_setup(VCPU_SREG_FS);
1397 seg_setup(VCPU_SREG_GS);
1398 seg_setup(VCPU_SREG_SS);
1399
1400 vmcs_write16(GUEST_TR_SELECTOR, 0);
1401 vmcs_writel(GUEST_TR_BASE, 0);
1402 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1403 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1404
1405 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1406 vmcs_writel(GUEST_LDTR_BASE, 0);
1407 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1408 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1409
1410 vmcs_write32(GUEST_SYSENTER_CS, 0);
1411 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1412 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1413
1414 vmcs_writel(GUEST_RFLAGS, 0x02);
1415 vmcs_writel(GUEST_RIP, 0xfff0);
1416 vmcs_writel(GUEST_RSP, 0);
1417
6aa8b732
AK		 1418 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1419 vmcs_writel(GUEST_DR7, 0x400);
1420
1421 vmcs_writel(GUEST_GDTR_BASE, 0);
1422 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1423
1424 vmcs_writel(GUEST_IDTR_BASE, 0);
1425 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1426
1427 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1428 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1429 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1430
1431 /* I/O */
fdef3ad1
HQ		 1432 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1433 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1434
1435 guest_write_tsc(0);
1436
1437 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1438
1439 /* Special registers */
1440 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1441
1442 /* Control */
1c3d14fe
YS		 1443 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1444 vmcs_config.pin_based_exec_ctrl);
1445 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1446 vmcs_config.cpu_based_exec_ctrl);
6aa8b732 1447
6aa8b732
AK		 1448 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1449 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1450 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1451
1452 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1453 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1454 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1455
1456 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1457 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1458 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1459 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1460 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1461 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1462#ifdef CONFIG_X86_64
6aa8b732
AK		 1463 rdmsrl(MSR_FS_BASE, a);
1464 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1465 rdmsrl(MSR_GS_BASE, a);
1466 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1467#else
1468 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1469 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1470#endif
1471
1472 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1473
1474 get_idt(&dt);
1475 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1476
cd2276a7
AK		 1477 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1478 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1479 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1480 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1481 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1482
1483 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1484 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1485 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1486 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1487 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1488 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1489
6aa8b732
AK		 1490 for (i = 0; i < NR_VMX_MSR; ++i) {
1491 u32 index = vmx_msr_index[i];
1492 u32 data_low, data_high;
1493 u64 data;
a2fa3e9f 1494 int j = vmx->nmsrs;
6aa8b732
AK		 1495
1496 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1497 continue;
432bd6cb
AK		 1498 if (wrmsr_safe(index, data_low, data_high) < 0)
1499 continue;
6aa8b732 1500 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1501 vmx->host_msrs[j].index = index;
1502 vmx->host_msrs[j].reserved = 0;
1503 vmx->host_msrs[j].data = data;
1504 vmx->guest_msrs[j] = vmx->host_msrs[j];
1505 ++vmx->nmsrs;
6aa8b732 1506 }
6aa8b732 1507
8b9cf98c 1508 setup_msrs(vmx);
e38aea3e 1509
1c3d14fe 1510 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1511
1512 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1513 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1514
6aa8b732
AK		 1515 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1516
3b99ab24 1517#ifdef CONFIG_X86_64
6aa8b732
AK		 1518 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1519 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1520#endif
6aa8b732 1521
25c4c276 1522 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1523 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1524
8b9cf98c
RR		 1525 vmx->vcpu.cr0 = 0x60000010;
1526 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1527 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1528#ifdef CONFIG_X86_64
8b9cf98c 1529 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1530#endif
8b9cf98c
RR		 1531 vmx_fpu_activate(&vmx->vcpu);
1532 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1533
1534 return 0;
1535
6aa8b732
AK		 1536out:
1537 return ret;
1538}
1539
1540static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1541{
1542 u16 ent[2];
1543 u16 cs;
1544 u16 ip;
1545 unsigned long flags;
1546 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1547 u16 sp = vmcs_readl(GUEST_RSP);
1548 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1549
3964994b 1550 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1551 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1552 __FUNCTION__,
1553 vmcs_readl(GUEST_RSP),
1554 vmcs_readl(GUEST_SS_BASE),
1555 vmcs_read32(GUEST_SS_LIMIT));
1556 return;
1557 }
1558
e7d5d76c
LV		 1559 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1560 X86EMUL_CONTINUE) {
6aa8b732
AK		 1561 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1562 return;
1563 }
1564
1565 flags = vmcs_readl(GUEST_RFLAGS);
1566 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1567 ip = vmcs_readl(GUEST_RIP);
1568
1569
e7d5d76c
LV		 1570 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1571 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1572 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1573 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1574 return;
1575 }
1576
1577 vmcs_writel(GUEST_RFLAGS, flags &
1578 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1579 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1580 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1581 vmcs_writel(GUEST_RIP, ent[0]);
1582 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1583}
1584
1585static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1586{
1587 int word_index = __ffs(vcpu->irq_summary);
1588 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1589 int irq = word_index * BITS_PER_LONG + bit_index;
1590
1591 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1592 if (!vcpu->irq_pending[word_index])
1593 clear_bit(word_index, &vcpu->irq_summary);
1594
1595 if (vcpu->rmode.active) {
1596 inject_rmode_irq(vcpu, irq);
1597 return;
1598 }
1599 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1600 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1601}
1602
c1150d8c
DL		 1603
1604static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1605 struct kvm_run *kvm_run)
6aa8b732 1606{
c1150d8c
DL		 1607 u32 cpu_based_vm_exec_control;
1608
1609 vcpu->interrupt_window_open =
1610 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1611 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1612
1613 if (vcpu->interrupt_window_open &&
1614 vcpu->irq_summary &&
1615 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1616 /*
c1150d8c 1617 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1618 */
1619 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1620
1621 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1622 if (!vcpu->interrupt_window_open &&
1623 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1624 /*
1625 * Interrupts blocked. Wait for unblock.
1626 */
c1150d8c
DL		 1627 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1628 else
1629 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1630 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1631}
1632
1633static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1634{
1635 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1636
1637 set_debugreg(dbg->bp[0], 0);
1638 set_debugreg(dbg->bp[1], 1);
1639 set_debugreg(dbg->bp[2], 2);
1640 set_debugreg(dbg->bp[3], 3);
1641
1642 if (dbg->singlestep) {
1643 unsigned long flags;
1644
1645 flags = vmcs_readl(GUEST_RFLAGS);
1646 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1647 vmcs_writel(GUEST_RFLAGS, flags);
1648 }
1649}
1650
1651static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1652 int vec, u32 err_code)
1653{
1654 if (!vcpu->rmode.active)
1655 return 0;
1656
b3f37707
NK		 1657 /*
1658 * Instruction with address size override prefix opcode 0x67
1659 * Cause the #SS fault with 0 error code in VM86 mode.
1660 */
1661 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1662 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1663 return 1;
1664 return 0;
1665}
1666
1667static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1668{
1669 u32 intr_info, error_code;
1670 unsigned long cr2, rip;
1671 u32 vect_info;
1672 enum emulation_result er;
e2dec939 1673 int r;
6aa8b732
AK		 1674
1675 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1676 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1677
1678 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1679 !is_page_fault(intr_info)) {
1680 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1681 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1682 }
1683
1684 if (is_external_interrupt(vect_info)) {
1685 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1686 set_bit(irq, vcpu->irq_pending);
1687 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1688 }
1689
1690 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1691 asm ("int $2");
1692 return 1;
1693 }
2ab455cc
AL		 1694
1695 if (is_no_device(intr_info)) {
5fd86fcf 1696 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1697 return 1;
1698 }
1699
6aa8b732
AK		 1700 error_code = 0;
1701 rip = vmcs_readl(GUEST_RIP);
1702 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1703 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1704 if (is_page_fault(intr_info)) {
1705 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1706
11ec2804 1707 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1708 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1709 if (r < 0) {
11ec2804 1710 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1711 return r;
1712 }
1713 if (!r) {
11ec2804 1714 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1715 return 1;
1716 }
1717
1718 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
11ec2804 1719 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1720
1721 switch (er) {
1722 case EMULATE_DONE:
1723 return 1;
1724 case EMULATE_DO_MMIO:
1165f5fe 1725 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1726 return 0;
1727 case EMULATE_FAIL:
1728 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1729 break;
1730 default:
1731 BUG();
1732 }
1733 }
1734
1735 if (vcpu->rmode.active &&
1736 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1737 error_code)) {
1738 if (vcpu->halt_request) {
1739 vcpu->halt_request = 0;
1740 return kvm_emulate_halt(vcpu);
1741 }
6aa8b732 1742 return 1;
72d6e5a0 1743 }
6aa8b732
AK		 1744
1745 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1746 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1747 return 0;
1748 }
1749 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1750 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1751 kvm_run->ex.error_code = error_code;
1752 return 0;
1753}
1754
1755static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1756 struct kvm_run *kvm_run)
1757{
1165f5fe 1758 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1759 return 1;
1760}
1761
988ad74f
AK		 1762static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1763{
1764 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1765 return 0;
1766}
6aa8b732 1767
6aa8b732
AK		 1768static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1769{
1770 u64 exit_qualification;
039576c0
AK		 1771 int size, down, in, string, rep;
1772 unsigned port;
6aa8b732 1773
1165f5fe 1774 ++vcpu->stat.io_exits;
6aa8b732 1775 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0 1776 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1777
1778 if (string) {
1779 if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1780 return 0;
1781 return 1;
1782 }
1783
1784 size = (exit_qualification & 7) + 1;
1785 in = (exit_qualification & 8) != 0;
039576c0 1786 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1787 rep = (exit_qualification & 32) != 0;
1788 port = exit_qualification >> 16;
e70669ab 1789
3090dd73 1790 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1791}
1792
102d8325
IM		 1793static void
1794vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1795{
1796 /*
1797 * Patch in the VMCALL instruction:
1798 */
1799 hypercall[0] = 0x0f;
1800 hypercall[1] = 0x01;
1801 hypercall[2] = 0xc1;
1802 hypercall[3] = 0xc3;
1803}
1804
6aa8b732
AK		 1805static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1806{
1807 u64 exit_qualification;
1808 int cr;
1809 int reg;
1810
1811 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1812 cr = exit_qualification & 15;
1813 reg = (exit_qualification >> 8) & 15;
1814 switch ((exit_qualification >> 4) & 3) {
1815 case 0: /* mov to cr */
1816 switch (cr) {
1817 case 0:
1818 vcpu_load_rsp_rip(vcpu);
1819 set_cr0(vcpu, vcpu->regs[reg]);
1820 skip_emulated_instruction(vcpu);
1821 return 1;
1822 case 3:
1823 vcpu_load_rsp_rip(vcpu);
1824 set_cr3(vcpu, vcpu->regs[reg]);
1825 skip_emulated_instruction(vcpu);
1826 return 1;
1827 case 4:
1828 vcpu_load_rsp_rip(vcpu);
1829 set_cr4(vcpu, vcpu->regs[reg]);
1830 skip_emulated_instruction(vcpu);
1831 return 1;
1832 case 8:
1833 vcpu_load_rsp_rip(vcpu);
1834 set_cr8(vcpu, vcpu->regs[reg]);
1835 skip_emulated_instruction(vcpu);
253abdee
YS		 1836 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1837 return 0;
6aa8b732
AK		 1838 };
1839 break;
25c4c276
AL		 1840 case 2: /* clts */
1841 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1842 vmx_fpu_deactivate(vcpu);
707d92fa 1843 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1844 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1845 vmx_fpu_activate(vcpu);
25c4c276
AL		 1846 skip_emulated_instruction(vcpu);
1847 return 1;
6aa8b732
AK		 1848 case 1: /*mov from cr*/
1849 switch (cr) {
1850 case 3:
1851 vcpu_load_rsp_rip(vcpu);
1852 vcpu->regs[reg] = vcpu->cr3;
1853 vcpu_put_rsp_rip(vcpu);
1854 skip_emulated_instruction(vcpu);
1855 return 1;
1856 case 8:
6aa8b732
AK		 1857 vcpu_load_rsp_rip(vcpu);
1858 vcpu->regs[reg] = vcpu->cr8;
1859 vcpu_put_rsp_rip(vcpu);
1860 skip_emulated_instruction(vcpu);
1861 return 1;
1862 }
1863 break;
1864 case 3: /* lmsw */
1865 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1866
1867 skip_emulated_instruction(vcpu);
1868 return 1;
1869 default:
1870 break;
1871 }
1872 kvm_run->exit_reason = 0;
f0242478 1873 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 1874 (int)(exit_qualification >> 4) & 3, cr);
1875 return 0;
1876}
1877
1878static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1879{
1880 u64 exit_qualification;
1881 unsigned long val;
1882 int dr, reg;
1883
1884 /*
1885 * FIXME: this code assumes the host is debugging the guest.
1886 * need to deal with guest debugging itself too.
1887 */
1888 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1889 dr = exit_qualification & 7;
1890 reg = (exit_qualification >> 8) & 15;
1891 vcpu_load_rsp_rip(vcpu);
1892 if (exit_qualification & 16) {
1893 /* mov from dr */
1894 switch (dr) {
1895 case 6:
1896 val = 0xffff0ff0;
1897 break;
1898 case 7:
1899 val = 0x400;
1900 break;
1901 default:
1902 val = 0;
1903 }
1904 vcpu->regs[reg] = val;
1905 } else {
1906 /* mov to dr */
1907 }
1908 vcpu_put_rsp_rip(vcpu);
1909 skip_emulated_instruction(vcpu);
1910 return 1;
1911}
1912
1913static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1914{
06465c5a
AK		 1915 kvm_emulate_cpuid(vcpu);
1916 return 1;
6aa8b732
AK		 1917}
1918
1919static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1920{
1921 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1922 u64 data;
1923
1924 if (vmx_get_msr(vcpu, ecx, &data)) {
1925 vmx_inject_gp(vcpu, 0);
1926 return 1;
1927 }
1928
1929 /* FIXME: handling of bits 32:63 of rax, rdx */
1930 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1931 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1932 skip_emulated_instruction(vcpu);
1933 return 1;
1934}
1935
1936static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1937{
1938 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1939 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1940 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1941
1942 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1943 vmx_inject_gp(vcpu, 0);
1944 return 1;
1945 }
1946
1947 skip_emulated_instruction(vcpu);
1948 return 1;
1949}
1950
c1150d8c
DL		 1951static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1952 struct kvm_run *kvm_run)
1953{
1954 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1955 kvm_run->cr8 = vcpu->cr8;
1956 kvm_run->apic_base = vcpu->apic_base;
1957 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1958 vcpu->irq_summary == 0);
1959}
1960
6aa8b732
AK		 1961static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1962 struct kvm_run *kvm_run)
1963{
c1150d8c
DL		 1964 /*
1965 * If the user space waits to inject interrupts, exit as soon as
1966 * possible
1967 */
1968 if (kvm_run->request_interrupt_window &&
022a9308 1969 !vcpu->irq_summary) {
c1150d8c 1970 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 1971 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1972 return 0;
1973 }
6aa8b732
AK		 1974 return 1;
1975}
1976
1977static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1978{
1979 skip_emulated_instruction(vcpu);
d3bef15f 1980 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 1981}
1982
c21415e8
IM		 1983static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1984{
510043da 1985 skip_emulated_instruction(vcpu);
270fd9b9 1986 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 1987}
1988
6aa8b732
AK		 1989/*
1990 * The exit handlers return 1 if the exit was handled fully and guest execution
1991 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1992 * to be done to userspace and return 0.
1993 */
1994static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1995 struct kvm_run *kvm_run) = {
1996 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1997 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 1998 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 1999 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2000 [EXIT_REASON_CR_ACCESS] = handle_cr,
2001 [EXIT_REASON_DR_ACCESS] = handle_dr,
2002 [EXIT_REASON_CPUID] = handle_cpuid,
2003 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2004 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2005 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2006 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2007 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 2008};
2009
2010static const int kvm_vmx_max_exit_handlers =
50a3485c 2011 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2012
2013/*
2014 * The guest has exited. See if we can fix it or if we need userspace
2015 * assistance.
2016 */
2017static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2018{
2019 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2020 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2021
2022 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2023 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2024 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2025 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2026 if (exit_reason < kvm_vmx_max_exit_handlers
2027 && kvm_vmx_exit_handlers[exit_reason])
2028 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2029 else {
2030 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2031 kvm_run->hw.hardware_exit_reason = exit_reason;
2032 }
2033 return 0;
2034}
2035
c1150d8c
DL		 2036/*
2037 * Check if userspace requested an interrupt window, and that the
2038 * interrupt window is open.
2039 *
2040 * No need to exit to userspace if we already have an interrupt queued.
2041 */
2042static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2043 struct kvm_run *kvm_run)
2044{
2045 return (!vcpu->irq_summary &&
2046 kvm_run->request_interrupt_window &&
2047 vcpu->interrupt_window_open &&
2048 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2049}
2050
d9e368d6
AK		 2051static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2052{
d9e368d6
AK		 2053}
2054
6aa8b732
AK		 2055static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2056{
a2fa3e9f 2057 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2058 u8 fail;
e2dec939 2059 int r;
6aa8b732 2060
e6adf283 2061preempted:
6aa8b732
AK		 2062 if (vcpu->guest_debug.enabled)
2063 kvm_guest_debug_pre(vcpu);
2064
e6adf283 2065again:
9ae0448f
SL		 2066 r = kvm_mmu_reload(vcpu);
2067 if (unlikely(r))
2068 goto out;
2069
15ad7146
AK		 2070 preempt_disable();
2071
8b9cf98c 2072 vmx_save_host_state(vmx);
e6adf283
AK		 2073 kvm_load_guest_fpu(vcpu);
2074
2075 /*
2076 * Loading guest fpu may have cleared host cr0.ts
2077 */
2078 vmcs_writel(HOST_CR0, read_cr0());
2079
d9e368d6
AK		 2080 local_irq_disable();
2081
7e66f350
AK		 2082 if (signal_pending(current)) {
2083 local_irq_enable();
2084 preempt_enable();
2085 r = -EINTR;
2086 kvm_run->exit_reason = KVM_EXIT_INTR;
2087 ++vcpu->stat.signal_exits;
2088 goto out;
2089 }
2090
2091 if (!vcpu->mmio_read_completed)
2092 do_interrupt_requests(vcpu, kvm_run);
2093
d9e368d6
AK		 2094 vcpu->guest_mode = 1;
2095 if (vcpu->requests)
2096 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2097 vmx_flush_tlb(vcpu);
2098
6aa8b732
AK		 2099 asm (
2100 /* Store host registers */
05b3e0c2 2101#ifdef CONFIG_X86_64
6aa8b732
AK		 2102 "push %%rax; push %%rbx; push %%rdx;"
2103 "push %%rsi; push %%rdi; push %%rbp;"
2104 "push %%r8; push %%r9; push %%r10; push %%r11;"
2105 "push %%r12; push %%r13; push %%r14; push %%r15;"
2106 "push %%rcx \n\t"
2107 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2108#else
2109 "pusha; push %%ecx \n\t"
2110 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2111#endif
2112 /* Check if vmlaunch of vmresume is needed */
2113 "cmp $0, %1 \n\t"
2114 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2115#ifdef CONFIG_X86_64
6aa8b732
AK		 2116 "mov %c[cr2](%3), %%rax \n\t"
2117 "mov %%rax, %%cr2 \n\t"
2118 "mov %c[rax](%3), %%rax \n\t"
2119 "mov %c[rbx](%3), %%rbx \n\t"
2120 "mov %c[rdx](%3), %%rdx \n\t"
2121 "mov %c[rsi](%3), %%rsi \n\t"
2122 "mov %c[rdi](%3), %%rdi \n\t"
2123 "mov %c[rbp](%3), %%rbp \n\t"
2124 "mov %c[r8](%3), %%r8 \n\t"
2125 "mov %c[r9](%3), %%r9 \n\t"
2126 "mov %c[r10](%3), %%r10 \n\t"
2127 "mov %c[r11](%3), %%r11 \n\t"
2128 "mov %c[r12](%3), %%r12 \n\t"
2129 "mov %c[r13](%3), %%r13 \n\t"
2130 "mov %c[r14](%3), %%r14 \n\t"
2131 "mov %c[r15](%3), %%r15 \n\t"
2132 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2133#else
2134 "mov %c[cr2](%3), %%eax \n\t"
2135 "mov %%eax, %%cr2 \n\t"
2136 "mov %c[rax](%3), %%eax \n\t"
2137 "mov %c[rbx](%3), %%ebx \n\t"
2138 "mov %c[rdx](%3), %%edx \n\t"
2139 "mov %c[rsi](%3), %%esi \n\t"
2140 "mov %c[rdi](%3), %%edi \n\t"
2141 "mov %c[rbp](%3), %%ebp \n\t"
2142 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2143#endif
2144 /* Enter guest mode */
cd2276a7 2145 "jne .Llaunched \n\t"
6aa8b732 2146 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2147 "jmp .Lkvm_vmx_return \n\t"
2148 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2149 ".Lkvm_vmx_return: "
6aa8b732 2150 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2151#ifdef CONFIG_X86_64
96958231 2152 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2153 "mov %%rax, %c[rax](%3) \n\t"
2154 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2155 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2156 "mov %%rdx, %c[rdx](%3) \n\t"
2157 "mov %%rsi, %c[rsi](%3) \n\t"
2158 "mov %%rdi, %c[rdi](%3) \n\t"
2159 "mov %%rbp, %c[rbp](%3) \n\t"
2160 "mov %%r8, %c[r8](%3) \n\t"
2161 "mov %%r9, %c[r9](%3) \n\t"
2162 "mov %%r10, %c[r10](%3) \n\t"
2163 "mov %%r11, %c[r11](%3) \n\t"
2164 "mov %%r12, %c[r12](%3) \n\t"
2165 "mov %%r13, %c[r13](%3) \n\t"
2166 "mov %%r14, %c[r14](%3) \n\t"
2167 "mov %%r15, %c[r15](%3) \n\t"
2168 "mov %%cr2, %%rax \n\t"
2169 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2170 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2171
2172 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2173 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2174 "pop %%rbp; pop %%rdi; pop %%rsi;"
2175 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2176#else
96958231 2177 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2178 "mov %%eax, %c[rax](%3) \n\t"
2179 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2180 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2181 "mov %%edx, %c[rdx](%3) \n\t"
2182 "mov %%esi, %c[rsi](%3) \n\t"
2183 "mov %%edi, %c[rdi](%3) \n\t"
2184 "mov %%ebp, %c[rbp](%3) \n\t"
2185 "mov %%cr2, %%eax \n\t"
2186 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2187 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2188
2189 "pop %%ecx; popa \n\t"
2190#endif
2191 "setbe %0 \n\t"
e0015489 2192 : "=q" (fail)
a2fa3e9f 2193 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2194 "c"(vcpu),
2195 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2196 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2197 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2198 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2199 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2200 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2201 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2202#ifdef CONFIG_X86_64
6aa8b732
AK		 2203 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2204 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2205 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2206 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2207 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2208 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2209 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2210 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2211#endif
2212 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2213 : "cc", "memory" );
2214
d9e368d6
AK		 2215 vcpu->guest_mode = 0;
2216 local_irq_enable();
2217
1165f5fe 2218 ++vcpu->stat.exits;
6aa8b732 2219
c1150d8c 2220 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2221
6aa8b732 2222 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146
AK		 2223 vmx->launched = 1;
2224
2225 preempt_enable();
6aa8b732 2226
05e0c8c3 2227 if (unlikely(fail)) {
8eb7d334
AK		 2228 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2229 kvm_run->fail_entry.hardware_entry_failure_reason
2230 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2231 r = 0;
05e0c8c3
AK		 2232 goto out;
2233 }
2234 /*
2235 * Profile KVM exit RIPs:
2236 */
2237 if (unlikely(prof_on == KVM_PROFILING))
2238 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2239
05e0c8c3
AK		 2240 r = kvm_handle_exit(kvm_run, vcpu);
2241 if (r > 0) {
05e0c8c3
AK		 2242 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2243 r = -EINTR;
2244 kvm_run->exit_reason = KVM_EXIT_INTR;
2245 ++vcpu->stat.request_irq_exits;
2246 goto out;
2247 }
2248 if (!need_resched()) {
2249 ++vcpu->stat.light_exits;
2250 goto again;
6aa8b732
AK		 2251 }
2252 }
c1150d8c 2253
e6adf283 2254out:
e6adf283
AK		 2255 if (r > 0) {
2256 kvm_resched(vcpu);
2257 goto preempted;
2258 }
2259
c1150d8c 2260 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2261 return r;
6aa8b732
AK		 2262}
2263
6aa8b732
AK		 2264static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2265 unsigned long addr,
2266 u32 err_code)
2267{
2268 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2269
1165f5fe 2270 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2271
2272 if (is_page_fault(vect_info)) {
2273 printk(KERN_DEBUG "inject_page_fault: "
2274 "double fault 0x%lx @ 0x%lx\n",
2275 addr, vmcs_readl(GUEST_RIP));
2276 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2277 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2278 DF_VECTOR |
2279 INTR_TYPE_EXCEPTION |
2280 INTR_INFO_DELIEVER_CODE_MASK |
2281 INTR_INFO_VALID_MASK);
2282 return;
2283 }
2284 vcpu->cr2 = addr;
2285 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2286 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2287 PF_VECTOR |
2288 INTR_TYPE_EXCEPTION |
2289 INTR_INFO_DELIEVER_CODE_MASK |
2290 INTR_INFO_VALID_MASK);
2291
2292}
2293
2294static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2295{
a2fa3e9f
GH		 2296 struct vcpu_vmx *vmx = to_vmx(vcpu);
2297
2298 if (vmx->vmcs) {
8b9cf98c 2299 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2300 free_vmcs(vmx->vmcs);
2301 vmx->vmcs = NULL;
6aa8b732
AK		 2302 }
2303}
2304
2305static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2306{
fb3f0f51
RR		 2307 struct vcpu_vmx *vmx = to_vmx(vcpu);
2308
6aa8b732 2309 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2310 kfree(vmx->host_msrs);
2311 kfree(vmx->guest_msrs);
2312 kvm_vcpu_uninit(vcpu);
a4770347 2313 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2314}
2315
fb3f0f51 2316static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2317{
fb3f0f51 2318 int err;
c16f862d 2319 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2320 int cpu;
6aa8b732 2321
a2fa3e9f 2322 if (!vmx)
fb3f0f51
RR		 2323 return ERR_PTR(-ENOMEM);
2324
2325 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2326 if (err)
2327 goto free_vcpu;
965b58a5 2328
a2fa3e9f 2329 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2330 if (!vmx->guest_msrs) {
2331 err = -ENOMEM;
2332 goto uninit_vcpu;
2333 }
965b58a5 2334
a2fa3e9f
GH		 2335 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2336 if (!vmx->host_msrs)
fb3f0f51 2337 goto free_guest_msrs;
965b58a5 2338
a2fa3e9f
GH		 2339 vmx->vmcs = alloc_vmcs();
2340 if (!vmx->vmcs)
fb3f0f51 2341 goto free_msrs;
a2fa3e9f
GH		 2342
2343 vmcs_clear(vmx->vmcs);
2344
15ad7146
AK		 2345 cpu = get_cpu();
2346 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2347 err = vmx_vcpu_setup(vmx);
fb3f0f51 2348 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2349 put_cpu();
fb3f0f51
RR		 2350 if (err)
2351 goto free_vmcs;
2352
2353 return &vmx->vcpu;
2354
2355free_vmcs:
2356 free_vmcs(vmx->vmcs);
2357free_msrs:
2358 kfree(vmx->host_msrs);
2359free_guest_msrs:
2360 kfree(vmx->guest_msrs);
2361uninit_vcpu:
2362 kvm_vcpu_uninit(&vmx->vcpu);
2363free_vcpu:
a4770347 2364 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2365 return ERR_PTR(err);
6aa8b732
AK		 2366}
2367
002c7f7c
YS		 2368static void __init vmx_check_processor_compat(void *rtn)
2369{
2370 struct vmcs_config vmcs_conf;
2371
2372 *(int *)rtn = 0;
2373 if (setup_vmcs_config(&vmcs_conf) < 0)
2374 *(int *)rtn = -EIO;
2375 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2376 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2377 smp_processor_id());
2378 *(int *)rtn = -EIO;
2379 }
2380}
2381
6aa8b732
AK		 2382static struct kvm_arch_ops vmx_arch_ops = {
2383 .cpu_has_kvm_support = cpu_has_kvm_support,
2384 .disabled_by_bios = vmx_disabled_by_bios,
2385 .hardware_setup = hardware_setup,
2386 .hardware_unsetup = hardware_unsetup,
002c7f7c 2387 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2388 .hardware_enable = hardware_enable,
2389 .hardware_disable = hardware_disable,
2390
2391 .vcpu_create = vmx_create_vcpu,
2392 .vcpu_free = vmx_free_vcpu,
2393
2394 .vcpu_load = vmx_vcpu_load,
2395 .vcpu_put = vmx_vcpu_put,
774c47f1 2396 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2397
2398 .set_guest_debug = set_guest_debug,
2399 .get_msr = vmx_get_msr,
2400 .set_msr = vmx_set_msr,
2401 .get_segment_base = vmx_get_segment_base,
2402 .get_segment = vmx_get_segment,
2403 .set_segment = vmx_set_segment,
6aa8b732 2404 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2405 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2406 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2407 .set_cr3 = vmx_set_cr3,
2408 .set_cr4 = vmx_set_cr4,
05b3e0c2 2409#ifdef CONFIG_X86_64
6aa8b732
AK		 2410 .set_efer = vmx_set_efer,
2411#endif
2412 .get_idt = vmx_get_idt,
2413 .set_idt = vmx_set_idt,
2414 .get_gdt = vmx_get_gdt,
2415 .set_gdt = vmx_set_gdt,
2416 .cache_regs = vcpu_load_rsp_rip,
2417 .decache_regs = vcpu_put_rsp_rip,
2418 .get_rflags = vmx_get_rflags,
2419 .set_rflags = vmx_set_rflags,
2420
2421 .tlb_flush = vmx_flush_tlb,
2422 .inject_page_fault = vmx_inject_page_fault,
2423
2424 .inject_gp = vmx_inject_gp,
2425
2426 .run = vmx_vcpu_run,
2427 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2428 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2429};
2430
2431static int __init vmx_init(void)
2432{
fdef3ad1
HQ		 2433 void *iova;
2434 int r;
2435
2436 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2437 if (!vmx_io_bitmap_a)
2438 return -ENOMEM;
2439
2440 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2441 if (!vmx_io_bitmap_b) {
2442 r = -ENOMEM;
2443 goto out;
2444 }
2445
2446 /*
2447 * Allow direct access to the PC debug port (it is often used for I/O
2448 * delays, but the vmexits simply slow things down).
2449 */
2450 iova = kmap(vmx_io_bitmap_a);
2451 memset(iova, 0xff, PAGE_SIZE);
2452 clear_bit(0x80, iova);
cd0536d7 2453 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2454
2455 iova = kmap(vmx_io_bitmap_b);
2456 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2457 kunmap(vmx_io_bitmap_b);
fdef3ad1 2458
c16f862d 2459 r = kvm_init_arch(&vmx_arch_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2460 if (r)
2461 goto out1;
2462
2463 return 0;
2464
2465out1:
2466 __free_page(vmx_io_bitmap_b);
2467out:
2468 __free_page(vmx_io_bitmap_a);
2469 return r;
6aa8b732
AK		 2470}
2471
2472static void __exit vmx_exit(void)
2473{
fdef3ad1
HQ		 2474 __free_page(vmx_io_bitmap_b);
2475 __free_page(vmx_io_bitmap_a);
2476
6aa8b732
AK		 2477 kvm_exit_arch();
2478}
2479
2480module_init(vmx_init)
2481module_exit(vmx_exit)
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