]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: implement 'movnti mem, reg'
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
85f455f7 20#include "irq.h"
6aa8b732 21#include "vmx.h"
e495606d
AK		 22#include "segment_descriptor.h"
23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
a2fa3e9f
GH		 36struct vmcs {
37 u32 revision_id;
38 u32 abort;
39 char data[0];
40};
41
42struct vcpu_vmx {
fb3f0f51 43 struct kvm_vcpu vcpu;
a2fa3e9f 44 int launched;
29bd8a78 45 u8 fail;
a2fa3e9f
GH		 46 struct kvm_msr_entry *guest_msrs;
47 struct kvm_msr_entry *host_msrs;
48 int nmsrs;
49 int save_nmsrs;
50 int msr_offset_efer;
51#ifdef CONFIG_X86_64
52 int msr_offset_kernel_gs_base;
53#endif
54 struct vmcs *vmcs;
55 struct {
56 int loaded;
57 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 58 int gs_ldt_reload_needed;
59 int fs_reload_needed;
a2fa3e9f
GH		 60 }host_state;
61
62};
63
64static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
65{
fb3f0f51 66 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 67}
68
75880a01
AK		 69static int init_rmode_tss(struct kvm *kvm);
70
6aa8b732
AK		 71static DEFINE_PER_CPU(struct vmcs *, vmxarea);
72static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
73
fdef3ad1
HQ		 74static struct page *vmx_io_bitmap_a;
75static struct page *vmx_io_bitmap_b;
76
2cc51560 77#define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
6aa8b732 78
1c3d14fe 79static struct vmcs_config {
6aa8b732
AK		 80 int size;
81 int order;
82 u32 revision_id;
1c3d14fe
YS		 83 u32 pin_based_exec_ctrl;
84 u32 cpu_based_exec_ctrl;
85 u32 vmexit_ctrl;
86 u32 vmentry_ctrl;
87} vmcs_config;
6aa8b732
AK		 88
89#define VMX_SEGMENT_FIELD(seg) \
90 [VCPU_SREG_##seg] = { \
91 .selector = GUEST_##seg##_SELECTOR, \
92 .base = GUEST_##seg##_BASE, \
93 .limit = GUEST_##seg##_LIMIT, \
94 .ar_bytes = GUEST_##seg##_AR_BYTES, \
95 }
96
97static struct kvm_vmx_segment_field {
98 unsigned selector;
99 unsigned base;
100 unsigned limit;
101 unsigned ar_bytes;
102} kvm_vmx_segment_fields[] = {
103 VMX_SEGMENT_FIELD(CS),
104 VMX_SEGMENT_FIELD(DS),
105 VMX_SEGMENT_FIELD(ES),
106 VMX_SEGMENT_FIELD(FS),
107 VMX_SEGMENT_FIELD(GS),
108 VMX_SEGMENT_FIELD(SS),
109 VMX_SEGMENT_FIELD(TR),
110 VMX_SEGMENT_FIELD(LDTR),
111};
112
4d56c8a7
AK		 113/*
114 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
115 * away by decrementing the array size.
116 */
6aa8b732 117static const u32 vmx_msr_index[] = {
05b3e0c2 118#ifdef CONFIG_X86_64
6aa8b732
AK		 119 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
120#endif
121 MSR_EFER, MSR_K6_STAR,
122};
9d8f549d 123#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 124
a2fa3e9f
GH		 125static void load_msrs(struct kvm_msr_entry *e, int n)
126{
127 int i;
128
129 for (i = 0; i < n; ++i)
130 wrmsrl(e[i].index, e[i].data);
131}
132
133static void save_msrs(struct kvm_msr_entry *e, int n)
134{
135 int i;
136
137 for (i = 0; i < n; ++i)
138 rdmsrl(e[i].index, e[i].data);
139}
140
141static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
2cc51560
ED		 142{
143 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
144}
145
8b9cf98c 146static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
2cc51560 147{
a2fa3e9f
GH		 148 int efer_offset = vmx->msr_offset_efer;
149 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
150 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560
ED		 151}
152
6aa8b732
AK		 153static inline int is_page_fault(u32 intr_info)
154{
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
158}
159
2ab455cc
AL		 160static inline int is_no_device(u32 intr_info)
161{
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
165}
166
6aa8b732
AK		 167static inline int is_external_interrupt(u32 intr_info)
168{
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171}
172
6e5d865c
YS		 173static inline int cpu_has_vmx_tpr_shadow(void)
174{
175 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
176}
177
178static inline int vm_need_tpr_shadow(struct kvm *kvm)
179{
180 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
181}
182
8b9cf98c 183static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 184{
185 int i;
186
a2fa3e9f
GH		 187 for (i = 0; i < vmx->nmsrs; ++i)
188 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 189 return i;
190 return -1;
191}
192
8b9cf98c 193static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 194{
195 int i;
196
8b9cf98c 197 i = __find_msr_index(vmx, msr);
a75beee6 198 if (i >= 0)
a2fa3e9f 199 return &vmx->guest_msrs[i];
8b6d44c7 200 return NULL;
7725f0ba
AK		 201}
202
6aa8b732
AK		 203static void vmcs_clear(struct vmcs *vmcs)
204{
205 u64 phys_addr = __pa(vmcs);
206 u8 error;
207
208 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
209 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210 : "cc", "memory");
211 if (error)
212 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
213 vmcs, phys_addr);
214}
215
216static void __vcpu_clear(void *arg)
217{
8b9cf98c 218 struct vcpu_vmx *vmx = arg;
d3b2c338 219 int cpu = raw_smp_processor_id();
6aa8b732 220
8b9cf98c 221 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 222 vmcs_clear(vmx->vmcs);
223 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 224 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 225 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 226}
227
8b9cf98c 228static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 229{
8b9cf98c
RR		 230 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
231 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
232 vmx, 0, 1);
8d0be2b3 233 else
8b9cf98c
RR		 234 __vcpu_clear(vmx);
235 vmx->launched = 0;
8d0be2b3
AK		 236}
237
6aa8b732
AK		 238static unsigned long vmcs_readl(unsigned long field)
239{
240 unsigned long value;
241
242 asm volatile (ASM_VMX_VMREAD_RDX_RAX
243 : "=a"(value) : "d"(field) : "cc");
244 return value;
245}
246
247static u16 vmcs_read16(unsigned long field)
248{
249 return vmcs_readl(field);
250}
251
252static u32 vmcs_read32(unsigned long field)
253{
254 return vmcs_readl(field);
255}
256
257static u64 vmcs_read64(unsigned long field)
258{
05b3e0c2 259#ifdef CONFIG_X86_64
6aa8b732
AK		 260 return vmcs_readl(field);
261#else
262 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
263#endif
264}
265
e52de1b8
AK		 266static noinline void vmwrite_error(unsigned long field, unsigned long value)
267{
268 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
269 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
270 dump_stack();
271}
272
6aa8b732
AK		 273static void vmcs_writel(unsigned long field, unsigned long value)
274{
275 u8 error;
276
277 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
278 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 279 if (unlikely(error))
280 vmwrite_error(field, value);
6aa8b732
AK		 281}
282
283static void vmcs_write16(unsigned long field, u16 value)
284{
285 vmcs_writel(field, value);
286}
287
288static void vmcs_write32(unsigned long field, u32 value)
289{
290 vmcs_writel(field, value);
291}
292
293static void vmcs_write64(unsigned long field, u64 value)
294{
05b3e0c2 295#ifdef CONFIG_X86_64
6aa8b732
AK		 296 vmcs_writel(field, value);
297#else
298 vmcs_writel(field, value);
299 asm volatile ("");
300 vmcs_writel(field+1, value >> 32);
301#endif
302}
303
2ab455cc
AL		 304static void vmcs_clear_bits(unsigned long field, u32 mask)
305{
306 vmcs_writel(field, vmcs_readl(field) & ~mask);
307}
308
309static void vmcs_set_bits(unsigned long field, u32 mask)
310{
311 vmcs_writel(field, vmcs_readl(field) | mask);
312}
313
abd3f2d6
AK		 314static void update_exception_bitmap(struct kvm_vcpu *vcpu)
315{
316 u32 eb;
317
318 eb = 1u << PF_VECTOR;
319 if (!vcpu->fpu_active)
320 eb |= 1u << NM_VECTOR;
321 if (vcpu->guest_debug.enabled)
322 eb |= 1u << 1;
323 if (vcpu->rmode.active)
324 eb = ~0;
325 vmcs_write32(EXCEPTION_BITMAP, eb);
326}
327
33ed6329
AK		 328static void reload_tss(void)
329{
330#ifndef CONFIG_X86_64
331
332 /*
333 * VT restores TR but not its size. Useless.
334 */
335 struct descriptor_table gdt;
336 struct segment_descriptor *descs;
337
338 get_gdt(&gdt);
339 descs = (void *)gdt.base;
340 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
341 load_TR_desc();
342#endif
343}
344
8b9cf98c 345static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560
ED		 346{
347 u64 trans_efer;
a2fa3e9f 348 int efer_offset = vmx->msr_offset_efer;
2cc51560 349
a2fa3e9f 350 trans_efer = vmx->host_msrs[efer_offset].data;
2cc51560 351 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
a2fa3e9f 352 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560 353 wrmsrl(MSR_EFER, trans_efer);
8b9cf98c 354 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 355}
356
04d2cc77 357static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 358{
04d2cc77
AK		 359 struct vcpu_vmx *vmx = to_vmx(vcpu);
360
a2fa3e9f 361 if (vmx->host_state.loaded)
33ed6329
AK		 362 return;
363
a2fa3e9f 364 vmx->host_state.loaded = 1;
33ed6329
AK		 365 /*
366 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
367 * allow segment selectors with cpl > 0 or ti == 1.
368 */
a2fa3e9f 369 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 370 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 371 vmx->host_state.fs_sel = read_fs();
152d3f2f 372 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 373 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 374 vmx->host_state.fs_reload_needed = 0;
375 } else {
33ed6329 376 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 377 vmx->host_state.fs_reload_needed = 1;
33ed6329 378 }
a2fa3e9f
GH		 379 vmx->host_state.gs_sel = read_gs();
380 if (!(vmx->host_state.gs_sel & 7))
381 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 382 else {
383 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 384 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 385 }
386
387#ifdef CONFIG_X86_64
388 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
389 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
390#else
a2fa3e9f
GH		 391 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
392 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 393#endif
707c0874
AK		 394
395#ifdef CONFIG_X86_64
8b9cf98c 396 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 397 save_msrs(vmx->host_msrs +
398 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 399 }
400#endif
a2fa3e9f 401 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
8b9cf98c
RR		 402 if (msr_efer_need_save_restore(vmx))
403 load_transition_efer(vmx);
33ed6329
AK		 404}
405
8b9cf98c 406static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 407{
15ad7146 408 unsigned long flags;
33ed6329 409
a2fa3e9f 410 if (!vmx->host_state.loaded)
33ed6329
AK		 411 return;
412
a2fa3e9f 413 vmx->host_state.loaded = 0;
152d3f2f 414 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 415 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 416 if (vmx->host_state.gs_ldt_reload_needed) {
417 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 418 /*
419 * If we have to reload gs, we must take care to
420 * preserve our gs base.
421 */
15ad7146 422 local_irq_save(flags);
a2fa3e9f 423 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 424#ifdef CONFIG_X86_64
425 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
426#endif
15ad7146 427 local_irq_restore(flags);
33ed6329 428 }
152d3f2f 429 reload_tss();
a2fa3e9f
GH		 430 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
431 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
8b9cf98c 432 if (msr_efer_need_save_restore(vmx))
a2fa3e9f 433 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
33ed6329
AK		 434}
435
6aa8b732
AK		 436/*
437 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
438 * vcpu mutex is already taken.
439 */
15ad7146 440static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 441{
a2fa3e9f
GH		 442 struct vcpu_vmx *vmx = to_vmx(vcpu);
443 u64 phys_addr = __pa(vmx->vmcs);
7700270e 444 u64 tsc_this, delta;
6aa8b732 445
a3d7f85f 446 if (vcpu->cpu != cpu) {
8b9cf98c 447 vcpu_clear(vmx);
a3d7f85f
ED		 448 kvm_migrate_apic_timer(vcpu);
449 }
6aa8b732 450
a2fa3e9f 451 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 452 u8 error;
453
a2fa3e9f 454 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 455 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
456 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
457 : "cc");
458 if (error)
459 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 460 vmx->vmcs, phys_addr);
6aa8b732
AK		 461 }
462
463 if (vcpu->cpu != cpu) {
464 struct descriptor_table dt;
465 unsigned long sysenter_esp;
466
467 vcpu->cpu = cpu;
468 /*
469 * Linux uses per-cpu TSS and GDT, so set these when switching
470 * processors.
471 */
472 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
473 get_gdt(&dt);
474 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
475
476 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
477 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 478
479 /*
480 * Make sure the time stamp counter is monotonous.
481 */
482 rdtscll(tsc_this);
483 delta = vcpu->host_tsc - tsc_this;
484 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 485 }
6aa8b732
AK		 486}
487
488static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
489{
8b9cf98c 490 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 491 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 492}
493
5fd86fcf
AK		 494static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
495{
496 if (vcpu->fpu_active)
497 return;
498 vcpu->fpu_active = 1;
707d92fa
RR		 499 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
500 if (vcpu->cr0 & X86_CR0_TS)
501 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 502 update_exception_bitmap(vcpu);
503}
504
505static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
506{
507 if (!vcpu->fpu_active)
508 return;
509 vcpu->fpu_active = 0;
707d92fa 510 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 511 update_exception_bitmap(vcpu);
512}
513
774c47f1
AK		 514static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
515{
8b9cf98c 516 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 517}
518
6aa8b732
AK		 519static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
520{
521 return vmcs_readl(GUEST_RFLAGS);
522}
523
524static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
525{
526 vmcs_writel(GUEST_RFLAGS, rflags);
527}
528
529static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
530{
531 unsigned long rip;
532 u32 interruptibility;
533
534 rip = vmcs_readl(GUEST_RIP);
535 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
536 vmcs_writel(GUEST_RIP, rip);
537
538 /*
539 * We emulated an instruction, so temporary interrupt blocking
540 * should be removed, if set.
541 */
542 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
543 if (interruptibility & 3)
544 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
545 interruptibility & ~3);
c1150d8c 546 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 547}
548
549static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
550{
551 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
552 vmcs_readl(GUEST_RIP));
553 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
554 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
555 GP_VECTOR |
556 INTR_TYPE_EXCEPTION |
557 INTR_INFO_DELIEVER_CODE_MASK |
558 INTR_INFO_VALID_MASK);
559}
560
a75beee6
ED		 561/*
562 * Swap MSR entry in host/guest MSR entry array.
563 */
54e11fa1 564#ifdef CONFIG_X86_64
8b9cf98c 565static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 566{
a2fa3e9f
GH		 567 struct kvm_msr_entry tmp;
568
569 tmp = vmx->guest_msrs[to];
570 vmx->guest_msrs[to] = vmx->guest_msrs[from];
571 vmx->guest_msrs[from] = tmp;
572 tmp = vmx->host_msrs[to];
573 vmx->host_msrs[to] = vmx->host_msrs[from];
574 vmx->host_msrs[from] = tmp;
a75beee6 575}
54e11fa1 576#endif
a75beee6 577
e38aea3e
AK		 578/*
579 * Set up the vmcs to automatically save and restore system
580 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
581 * mode, as fiddling with msrs is very expensive.
582 */
8b9cf98c 583static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 584{
2cc51560 585 int save_nmsrs;
e38aea3e 586
a75beee6
ED		 587 save_nmsrs = 0;
588#ifdef CONFIG_X86_64
8b9cf98c 589 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 590 int index;
591
8b9cf98c 592 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 593 if (index >= 0)
8b9cf98c
RR		 594 move_msr_up(vmx, index, save_nmsrs++);
595 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 596 if (index >= 0)
8b9cf98c
RR		 597 move_msr_up(vmx, index, save_nmsrs++);
598 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 599 if (index >= 0)
8b9cf98c
RR		 600 move_msr_up(vmx, index, save_nmsrs++);
601 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 602 if (index >= 0)
8b9cf98c 603 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 604 /*
605 * MSR_K6_STAR is only needed on long mode guests, and only
606 * if efer.sce is enabled.
607 */
8b9cf98c
RR		 608 index = __find_msr_index(vmx, MSR_K6_STAR);
609 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
610 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 611 }
612#endif
a2fa3e9f 613 vmx->save_nmsrs = save_nmsrs;
e38aea3e 614
4d56c8a7 615#ifdef CONFIG_X86_64
a2fa3e9f 616 vmx->msr_offset_kernel_gs_base =
8b9cf98c 617 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 618#endif
8b9cf98c 619 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 620}
621
6aa8b732
AK		 622/*
623 * reads and returns guest's timestamp counter "register"
624 * guest_tsc = host_tsc + tsc_offset -- 21.3
625 */
626static u64 guest_read_tsc(void)
627{
628 u64 host_tsc, tsc_offset;
629
630 rdtscll(host_tsc);
631 tsc_offset = vmcs_read64(TSC_OFFSET);
632 return host_tsc + tsc_offset;
633}
634
635/*
636 * writes 'guest_tsc' into guest's timestamp counter "register"
637 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
638 */
639static void guest_write_tsc(u64 guest_tsc)
640{
641 u64 host_tsc;
642
643 rdtscll(host_tsc);
644 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
645}
646
6aa8b732
AK		 647/*
648 * Reads an msr value (of 'msr_index') into 'pdata'.
649 * Returns 0 on success, non-0 otherwise.
650 * Assumes vcpu_load() was already called.
651 */
652static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
653{
654 u64 data;
a2fa3e9f 655 struct kvm_msr_entry *msr;
6aa8b732
AK		 656
657 if (!pdata) {
658 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
659 return -EINVAL;
660 }
661
662 switch (msr_index) {
05b3e0c2 663#ifdef CONFIG_X86_64
6aa8b732
AK		 664 case MSR_FS_BASE:
665 data = vmcs_readl(GUEST_FS_BASE);
666 break;
667 case MSR_GS_BASE:
668 data = vmcs_readl(GUEST_GS_BASE);
669 break;
670 case MSR_EFER:
3bab1f5d 671 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 672#endif
673 case MSR_IA32_TIME_STAMP_COUNTER:
674 data = guest_read_tsc();
675 break;
676 case MSR_IA32_SYSENTER_CS:
677 data = vmcs_read32(GUEST_SYSENTER_CS);
678 break;
679 case MSR_IA32_SYSENTER_EIP:
f5b42c33 680 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 681 break;
682 case MSR_IA32_SYSENTER_ESP:
f5b42c33 683 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 684 break;
6aa8b732 685 default:
8b9cf98c 686 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 687 if (msr) {
688 data = msr->data;
689 break;
6aa8b732 690 }
3bab1f5d 691 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 692 }
693
694 *pdata = data;
695 return 0;
696}
697
698/*
699 * Writes msr value into into the appropriate "register".
700 * Returns 0 on success, non-0 otherwise.
701 * Assumes vcpu_load() was already called.
702 */
703static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
704{
a2fa3e9f
GH		 705 struct vcpu_vmx *vmx = to_vmx(vcpu);
706 struct kvm_msr_entry *msr;
2cc51560
ED		 707 int ret = 0;
708
6aa8b732 709 switch (msr_index) {
05b3e0c2 710#ifdef CONFIG_X86_64
3bab1f5d 711 case MSR_EFER:
2cc51560 712 ret = kvm_set_msr_common(vcpu, msr_index, data);
a2fa3e9f 713 if (vmx->host_state.loaded)
8b9cf98c 714 load_transition_efer(vmx);
2cc51560 715 break;
6aa8b732
AK		 716 case MSR_FS_BASE:
717 vmcs_writel(GUEST_FS_BASE, data);
718 break;
719 case MSR_GS_BASE:
720 vmcs_writel(GUEST_GS_BASE, data);
721 break;
722#endif
723 case MSR_IA32_SYSENTER_CS:
724 vmcs_write32(GUEST_SYSENTER_CS, data);
725 break;
726 case MSR_IA32_SYSENTER_EIP:
f5b42c33 727 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 728 break;
729 case MSR_IA32_SYSENTER_ESP:
f5b42c33 730 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 731 break;
d27d4aca 732 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 733 guest_write_tsc(data);
734 break;
6aa8b732 735 default:
8b9cf98c 736 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 737 if (msr) {
738 msr->data = data;
a2fa3e9f
GH		 739 if (vmx->host_state.loaded)
740 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 741 break;
6aa8b732 742 }
2cc51560 743 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 744 }
745
2cc51560 746 return ret;
6aa8b732
AK		 747}
748
749/*
750 * Sync the rsp and rip registers into the vcpu structure. This allows
751 * registers to be accessed by indexing vcpu->regs.
752 */
753static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
754{
755 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
756 vcpu->rip = vmcs_readl(GUEST_RIP);
757}
758
759/*
760 * Syncs rsp and rip back into the vmcs. Should be called after possible
761 * modification.
762 */
763static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
764{
765 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
766 vmcs_writel(GUEST_RIP, vcpu->rip);
767}
768
769static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
770{
771 unsigned long dr7 = 0x400;
6aa8b732
AK		 772 int old_singlestep;
773
6aa8b732
AK		 774 old_singlestep = vcpu->guest_debug.singlestep;
775
776 vcpu->guest_debug.enabled = dbg->enabled;
777 if (vcpu->guest_debug.enabled) {
778 int i;
779
780 dr7 |= 0x200; /* exact */
781 for (i = 0; i < 4; ++i) {
782 if (!dbg->breakpoints[i].enabled)
783 continue;
784 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
785 dr7 |= 2 << (i*2); /* global enable */
786 dr7 |= 0 << (i*4+16); /* execution breakpoint */
787 }
788
6aa8b732 789 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 790 } else
6aa8b732 791 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 792
793 if (old_singlestep && !vcpu->guest_debug.singlestep) {
794 unsigned long flags;
795
796 flags = vmcs_readl(GUEST_RFLAGS);
797 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
798 vmcs_writel(GUEST_RFLAGS, flags);
799 }
800
abd3f2d6 801 update_exception_bitmap(vcpu);
6aa8b732
AK		 802 vmcs_writel(GUEST_DR7, dr7);
803
804 return 0;
805}
806
2a8067f1
ED		 807static int vmx_get_irq(struct kvm_vcpu *vcpu)
808{
809 u32 idtv_info_field;
810
811 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
812 if (idtv_info_field & INTR_INFO_VALID_MASK) {
813 if (is_external_interrupt(idtv_info_field))
814 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
815 else
816 printk("pending exception: not handled yet\n");
817 }
818 return -1;
819}
820
6aa8b732
AK		 821static __init int cpu_has_kvm_support(void)
822{
823 unsigned long ecx = cpuid_ecx(1);
824 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
825}
826
827static __init int vmx_disabled_by_bios(void)
828{
829 u64 msr;
830
831 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 832 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
833 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
834 == MSR_IA32_FEATURE_CONTROL_LOCKED;
835 /* locked but not enabled */
6aa8b732
AK		 836}
837
774c47f1 838static void hardware_enable(void *garbage)
6aa8b732
AK		 839{
840 int cpu = raw_smp_processor_id();
841 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
842 u64 old;
843
844 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 845 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
846 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
847 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
848 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 849 /* enable and lock */
62b3ffb8
YS		 850 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
851 MSR_IA32_FEATURE_CONTROL_LOCKED |
852 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 853 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 854 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
855 : "memory", "cc");
856}
857
858static void hardware_disable(void *garbage)
859{
860 asm volatile (ASM_VMX_VMXOFF : : : "cc");
861}
862
1c3d14fe
YS		 863static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
864 u32 msr, u32* result)
865{
866 u32 vmx_msr_low, vmx_msr_high;
867 u32 ctl = ctl_min | ctl_opt;
868
869 rdmsr(msr, vmx_msr_low, vmx_msr_high);
870
871 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
872 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
873
874 /* Ensure minimum (required) set of control bits are supported. */
875 if (ctl_min & ~ctl)
002c7f7c 876 return -EIO;
1c3d14fe
YS		 877
878 *result = ctl;
879 return 0;
880}
881
002c7f7c 882static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 883{
884 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 885 u32 min, opt;
886 u32 _pin_based_exec_control = 0;
887 u32 _cpu_based_exec_control = 0;
888 u32 _vmexit_control = 0;
889 u32 _vmentry_control = 0;
890
891 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
892 opt = 0;
893 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
894 &_pin_based_exec_control) < 0)
002c7f7c 895 return -EIO;
1c3d14fe
YS		 896
897 min = CPU_BASED_HLT_EXITING |
898#ifdef CONFIG_X86_64
899 CPU_BASED_CR8_LOAD_EXITING |
900 CPU_BASED_CR8_STORE_EXITING |
901#endif
902 CPU_BASED_USE_IO_BITMAPS |
903 CPU_BASED_MOV_DR_EXITING |
904 CPU_BASED_USE_TSC_OFFSETING;
6e5d865c
YS		 905#ifdef CONFIG_X86_64
906 opt = CPU_BASED_TPR_SHADOW;
907#else
1c3d14fe 908 opt = 0;
6e5d865c 909#endif
1c3d14fe
YS		 910 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
911 &_cpu_based_exec_control) < 0)
002c7f7c 912 return -EIO;
6e5d865c
YS		 913#ifdef CONFIG_X86_64
914 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
915 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
916 ~CPU_BASED_CR8_STORE_EXITING;
917#endif
1c3d14fe
YS		 918
919 min = 0;
920#ifdef CONFIG_X86_64
921 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
922#endif
923 opt = 0;
924 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
925 &_vmexit_control) < 0)
002c7f7c 926 return -EIO;
1c3d14fe
YS		 927
928 min = opt = 0;
929 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
930 &_vmentry_control) < 0)
002c7f7c 931 return -EIO;
6aa8b732 932
c68876fd 933 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 934
935 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
936 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 937 return -EIO;
1c3d14fe
YS		 938
939#ifdef CONFIG_X86_64
940 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
941 if (vmx_msr_high & (1u<<16))
002c7f7c 942 return -EIO;
1c3d14fe
YS		 943#endif
944
945 /* Require Write-Back (WB) memory type for VMCS accesses. */
946 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 947 return -EIO;
1c3d14fe 948
002c7f7c
YS		 949 vmcs_conf->size = vmx_msr_high & 0x1fff;
950 vmcs_conf->order = get_order(vmcs_config.size);
951 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 952
002c7f7c
YS		 953 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
954 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
955 vmcs_conf->vmexit_ctrl = _vmexit_control;
956 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 957
958 return 0;
c68876fd 959}
6aa8b732
AK		 960
961static struct vmcs *alloc_vmcs_cpu(int cpu)
962{
963 int node = cpu_to_node(cpu);
964 struct page *pages;
965 struct vmcs *vmcs;
966
1c3d14fe 967 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 968 if (!pages)
969 return NULL;
970 vmcs = page_address(pages);
1c3d14fe
YS		 971 memset(vmcs, 0, vmcs_config.size);
972 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 973 return vmcs;
974}
975
976static struct vmcs *alloc_vmcs(void)
977{
d3b2c338 978 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 979}
980
981static void free_vmcs(struct vmcs *vmcs)
982{
1c3d14fe 983 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 984}
985
39959588 986static void free_kvm_area(void)
6aa8b732
AK		 987{
988 int cpu;
989
990 for_each_online_cpu(cpu)
991 free_vmcs(per_cpu(vmxarea, cpu));
992}
993
6aa8b732
AK		 994static __init int alloc_kvm_area(void)
995{
996 int cpu;
997
998 for_each_online_cpu(cpu) {
999 struct vmcs *vmcs;
1000
1001 vmcs = alloc_vmcs_cpu(cpu);
1002 if (!vmcs) {
1003 free_kvm_area();
1004 return -ENOMEM;
1005 }
1006
1007 per_cpu(vmxarea, cpu) = vmcs;
1008 }
1009 return 0;
1010}
1011
1012static __init int hardware_setup(void)
1013{
002c7f7c
YS		 1014 if (setup_vmcs_config(&vmcs_config) < 0)
1015 return -EIO;
6aa8b732
AK		 1016 return alloc_kvm_area();
1017}
1018
1019static __exit void hardware_unsetup(void)
1020{
1021 free_kvm_area();
1022}
1023
6aa8b732
AK		 1024static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1025{
1026 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1027
6af11b9e 1028 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1029 vmcs_write16(sf->selector, save->selector);
1030 vmcs_writel(sf->base, save->base);
1031 vmcs_write32(sf->limit, save->limit);
1032 vmcs_write32(sf->ar_bytes, save->ar);
1033 } else {
1034 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1035 << AR_DPL_SHIFT;
1036 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1037 }
1038}
1039
1040static void enter_pmode(struct kvm_vcpu *vcpu)
1041{
1042 unsigned long flags;
1043
1044 vcpu->rmode.active = 0;
1045
1046 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1047 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1048 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1049
1050 flags = vmcs_readl(GUEST_RFLAGS);
1051 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
1052 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1053 vmcs_writel(GUEST_RFLAGS, flags);
1054
66aee91a
RR		 1055 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1056 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1057
1058 update_exception_bitmap(vcpu);
1059
1060 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1061 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1062 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1063 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1064
1065 vmcs_write16(GUEST_SS_SELECTOR, 0);
1066 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1067
1068 vmcs_write16(GUEST_CS_SELECTOR,
1069 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1070 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1071}
1072
33f5fa16 1073static gva_t rmode_tss_base(struct kvm* kvm)
6aa8b732
AK		 1074{
1075 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1076 return base_gfn << PAGE_SHIFT;
1077}
1078
1079static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1080{
1081 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1082
1083 save->selector = vmcs_read16(sf->selector);
1084 save->base = vmcs_readl(sf->base);
1085 save->limit = vmcs_read32(sf->limit);
1086 save->ar = vmcs_read32(sf->ar_bytes);
1087 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1088 vmcs_write32(sf->limit, 0xffff);
1089 vmcs_write32(sf->ar_bytes, 0xf3);
1090}
1091
1092static void enter_rmode(struct kvm_vcpu *vcpu)
1093{
1094 unsigned long flags;
1095
1096 vcpu->rmode.active = 1;
1097
1098 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1099 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1100
1101 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1102 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1103
1104 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1105 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1106
1107 flags = vmcs_readl(GUEST_RFLAGS);
1108 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1109
1110 flags |= IOPL_MASK | X86_EFLAGS_VM;
1111
1112 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1113 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1114 update_exception_bitmap(vcpu);
1115
1116 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1117 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1118 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1119
1120 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1121 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1122 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1123 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1124 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1125
1126 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1127 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1128 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1129 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1130
8668a3c4 1131 kvm_mmu_reset_context(vcpu);
75880a01 1132 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1133}
1134
05b3e0c2 1135#ifdef CONFIG_X86_64
6aa8b732
AK		 1136
1137static void enter_lmode(struct kvm_vcpu *vcpu)
1138{
1139 u32 guest_tr_ar;
1140
1141 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1142 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1143 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1144 __FUNCTION__);
1145 vmcs_write32(GUEST_TR_AR_BYTES,
1146 (guest_tr_ar & ~AR_TYPE_MASK)
1147 | AR_TYPE_BUSY_64_TSS);
1148 }
1149
1150 vcpu->shadow_efer |= EFER_LMA;
1151
8b9cf98c 1152 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1153 vmcs_write32(VM_ENTRY_CONTROLS,
1154 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1155 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1156}
1157
1158static void exit_lmode(struct kvm_vcpu *vcpu)
1159{
1160 vcpu->shadow_efer &= ~EFER_LMA;
1161
1162 vmcs_write32(VM_ENTRY_CONTROLS,
1163 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1164 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1165}
1166
1167#endif
1168
25c4c276 1169static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1170{
399badf3
AK		 1171 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1172 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1173}
1174
6aa8b732
AK		 1175static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1176{
5fd86fcf
AK		 1177 vmx_fpu_deactivate(vcpu);
1178
707d92fa 1179 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1180 enter_pmode(vcpu);
1181
707d92fa 1182 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1183 enter_rmode(vcpu);
1184
05b3e0c2 1185#ifdef CONFIG_X86_64
6aa8b732 1186 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1187 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1188 enter_lmode(vcpu);
707d92fa 1189 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1190 exit_lmode(vcpu);
1191 }
1192#endif
1193
1194 vmcs_writel(CR0_READ_SHADOW, cr0);
1195 vmcs_writel(GUEST_CR0,
1196 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1197 vcpu->cr0 = cr0;
5fd86fcf 1198
707d92fa 1199 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1200 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1201}
1202
6aa8b732
AK		 1203static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1204{
1205 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1206 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1207 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1208}
1209
1210static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1211{
1212 vmcs_writel(CR4_READ_SHADOW, cr4);
1213 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1214 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1215 vcpu->cr4 = cr4;
1216}
1217
05b3e0c2 1218#ifdef CONFIG_X86_64
6aa8b732
AK		 1219
1220static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1221{
8b9cf98c
RR		 1222 struct vcpu_vmx *vmx = to_vmx(vcpu);
1223 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1224
1225 vcpu->shadow_efer = efer;
1226 if (efer & EFER_LMA) {
1227 vmcs_write32(VM_ENTRY_CONTROLS,
1228 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1229 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1230 msr->data = efer;
1231
1232 } else {
1233 vmcs_write32(VM_ENTRY_CONTROLS,
1234 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1235 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1236
1237 msr->data = efer & ~EFER_LME;
1238 }
8b9cf98c 1239 setup_msrs(vmx);
6aa8b732
AK		 1240}
1241
1242#endif
1243
1244static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1245{
1246 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1247
1248 return vmcs_readl(sf->base);
1249}
1250
1251static void vmx_get_segment(struct kvm_vcpu *vcpu,
1252 struct kvm_segment *var, int seg)
1253{
1254 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1255 u32 ar;
1256
1257 var->base = vmcs_readl(sf->base);
1258 var->limit = vmcs_read32(sf->limit);
1259 var->selector = vmcs_read16(sf->selector);
1260 ar = vmcs_read32(sf->ar_bytes);
1261 if (ar & AR_UNUSABLE_MASK)
1262 ar = 0;
1263 var->type = ar & 15;
1264 var->s = (ar >> 4) & 1;
1265 var->dpl = (ar >> 5) & 3;
1266 var->present = (ar >> 7) & 1;
1267 var->avl = (ar >> 12) & 1;
1268 var->l = (ar >> 13) & 1;
1269 var->db = (ar >> 14) & 1;
1270 var->g = (ar >> 15) & 1;
1271 var->unusable = (ar >> 16) & 1;
1272}
1273
653e3108 1274static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1275{
6aa8b732
AK		 1276 u32 ar;
1277
653e3108 1278 if (var->unusable)
6aa8b732
AK		 1279 ar = 1 << 16;
1280 else {
1281 ar = var->type & 15;
1282 ar |= (var->s & 1) << 4;
1283 ar |= (var->dpl & 3) << 5;
1284 ar |= (var->present & 1) << 7;
1285 ar |= (var->avl & 1) << 12;
1286 ar |= (var->l & 1) << 13;
1287 ar |= (var->db & 1) << 14;
1288 ar |= (var->g & 1) << 15;
1289 }
f7fbf1fd
UL		 1290 if (ar == 0) /* a 0 value means unusable */
1291 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1292
1293 return ar;
1294}
1295
1296static void vmx_set_segment(struct kvm_vcpu *vcpu,
1297 struct kvm_segment *var, int seg)
1298{
1299 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1300 u32 ar;
1301
1302 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1303 vcpu->rmode.tr.selector = var->selector;
1304 vcpu->rmode.tr.base = var->base;
1305 vcpu->rmode.tr.limit = var->limit;
1306 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1307 return;
1308 }
1309 vmcs_writel(sf->base, var->base);
1310 vmcs_write32(sf->limit, var->limit);
1311 vmcs_write16(sf->selector, var->selector);
1312 if (vcpu->rmode.active && var->s) {
1313 /*
1314 * Hack real-mode segments into vm86 compatibility.
1315 */
1316 if (var->base == 0xffff0000 && var->selector == 0xf000)
1317 vmcs_writel(sf->base, 0xf0000);
1318 ar = 0xf3;
1319 } else
1320 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1321 vmcs_write32(sf->ar_bytes, ar);
1322}
1323
6aa8b732
AK		 1324static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1325{
1326 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1327
1328 *db = (ar >> 14) & 1;
1329 *l = (ar >> 13) & 1;
1330}
1331
1332static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1333{
1334 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1335 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1336}
1337
1338static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1339{
1340 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1341 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1342}
1343
1344static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1345{
1346 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1347 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1348}
1349
1350static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1351{
1352 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1353 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1354}
1355
1356static int init_rmode_tss(struct kvm* kvm)
1357{
1358 struct page *p1, *p2, *p3;
1359 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1360 char *page;
1361
954bbbc2
AK		 1362 p1 = gfn_to_page(kvm, fn++);
1363 p2 = gfn_to_page(kvm, fn++);
1364 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1365
1366 if (!p1 || !p2 || !p3) {
1367 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1368 return 0;
1369 }
1370
1371 page = kmap_atomic(p1, KM_USER0);
a3870c47 1372 clear_page(page);
6aa8b732
AK		 1373 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1374 kunmap_atomic(page, KM_USER0);
1375
1376 page = kmap_atomic(p2, KM_USER0);
a3870c47 1377 clear_page(page);
6aa8b732
AK		 1378 kunmap_atomic(page, KM_USER0);
1379
1380 page = kmap_atomic(p3, KM_USER0);
a3870c47 1381 clear_page(page);
6aa8b732
AK		 1382 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1383 kunmap_atomic(page, KM_USER0);
1384
1385 return 1;
1386}
1387
6aa8b732
AK		 1388static void seg_setup(int seg)
1389{
1390 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1391
1392 vmcs_write16(sf->selector, 0);
1393 vmcs_writel(sf->base, 0);
1394 vmcs_write32(sf->limit, 0xffff);
1395 vmcs_write32(sf->ar_bytes, 0x93);
1396}
1397
1398/*
1399 * Sets up the vmcs for emulated real mode.
1400 */
8b9cf98c 1401static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1402{
1403 u32 host_sysenter_cs;
1404 u32 junk;
1405 unsigned long a;
1406 struct descriptor_table dt;
1407 int i;
1408 int ret = 0;
cd2276a7 1409 unsigned long kvm_vmx_return;
7017fc3d 1410 u64 msr;
6e5d865c 1411 u32 exec_control;
6aa8b732 1412
8b9cf98c 1413 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1414 ret = -ENOMEM;
1415 goto out;
1416 }
1417
c5ec1534
HQ		 1418 vmx->vcpu.rmode.active = 0;
1419
8b9cf98c 1420 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
7017fc3d
ED		 1421 set_cr8(&vmx->vcpu, 0);
1422 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
8b9cf98c 1423 if (vmx->vcpu.vcpu_id == 0)
7017fc3d
ED		 1424 msr |= MSR_IA32_APICBASE_BSP;
1425 kvm_set_apic_base(&vmx->vcpu, msr);
6aa8b732 1426
8b9cf98c 1427 fx_init(&vmx->vcpu);
6aa8b732
AK		 1428
1429 /*
1430 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1431 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1432 */
c5ec1534
HQ		 1433 if (vmx->vcpu.vcpu_id == 0) {
1434 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1435 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1436 } else {
1437 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1438 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1439 }
6aa8b732
AK		 1440 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1441 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1442
1443 seg_setup(VCPU_SREG_DS);
1444 seg_setup(VCPU_SREG_ES);
1445 seg_setup(VCPU_SREG_FS);
1446 seg_setup(VCPU_SREG_GS);
1447 seg_setup(VCPU_SREG_SS);
1448
1449 vmcs_write16(GUEST_TR_SELECTOR, 0);
1450 vmcs_writel(GUEST_TR_BASE, 0);
1451 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1452 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1453
1454 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1455 vmcs_writel(GUEST_LDTR_BASE, 0);
1456 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1457 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1458
1459 vmcs_write32(GUEST_SYSENTER_CS, 0);
1460 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1461 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1462
1463 vmcs_writel(GUEST_RFLAGS, 0x02);
c5ec1534
HQ		 1464 if (vmx->vcpu.vcpu_id == 0)
1465 vmcs_writel(GUEST_RIP, 0xfff0);
1466 else
1467 vmcs_writel(GUEST_RIP, 0);
6aa8b732
AK		 1468 vmcs_writel(GUEST_RSP, 0);
1469
6aa8b732
AK		 1470 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1471 vmcs_writel(GUEST_DR7, 0x400);
1472
1473 vmcs_writel(GUEST_GDTR_BASE, 0);
1474 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1475
1476 vmcs_writel(GUEST_IDTR_BASE, 0);
1477 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1478
1479 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1480 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1481 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1482
1483 /* I/O */
fdef3ad1
HQ		 1484 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1485 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1486
1487 guest_write_tsc(0);
1488
1489 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1490
1491 /* Special registers */
1492 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1493
1494 /* Control */
1c3d14fe
YS		 1495 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1496 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1497
1498 exec_control = vmcs_config.cpu_based_exec_ctrl;
1499 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1500 exec_control &= ~CPU_BASED_TPR_SHADOW;
1501#ifdef CONFIG_X86_64
1502 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1503 CPU_BASED_CR8_LOAD_EXITING;
1504#endif
1505 }
1506 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1507
6aa8b732
AK		 1508 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1509 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1510 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1511
1512 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1513 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1514 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1515
1516 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1517 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1518 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1519 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1520 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1521 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1522#ifdef CONFIG_X86_64
6aa8b732
AK		 1523 rdmsrl(MSR_FS_BASE, a);
1524 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1525 rdmsrl(MSR_GS_BASE, a);
1526 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1527#else
1528 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1529 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1530#endif
1531
1532 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1533
1534 get_idt(&dt);
1535 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1536
cd2276a7
AK		 1537 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1538 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1539 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1540 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1541 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1542
1543 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1544 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1545 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1546 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1547 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1548 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1549
6aa8b732
AK		 1550 for (i = 0; i < NR_VMX_MSR; ++i) {
1551 u32 index = vmx_msr_index[i];
1552 u32 data_low, data_high;
1553 u64 data;
a2fa3e9f 1554 int j = vmx->nmsrs;
6aa8b732
AK		 1555
1556 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1557 continue;
432bd6cb
AK		 1558 if (wrmsr_safe(index, data_low, data_high) < 0)
1559 continue;
6aa8b732 1560 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1561 vmx->host_msrs[j].index = index;
1562 vmx->host_msrs[j].reserved = 0;
1563 vmx->host_msrs[j].data = data;
1564 vmx->guest_msrs[j] = vmx->host_msrs[j];
1565 ++vmx->nmsrs;
6aa8b732 1566 }
6aa8b732 1567
8b9cf98c 1568 setup_msrs(vmx);
e38aea3e 1569
1c3d14fe 1570 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1571
1572 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1573 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1574
6aa8b732
AK		 1575 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1576
3b99ab24 1577#ifdef CONFIG_X86_64
6e5d865c
YS		 1578 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1579 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1580 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1581 page_to_phys(vmx->vcpu.apic->regs_page));
1582 vmcs_write32(TPR_THRESHOLD, 0);
3b99ab24 1583#endif
6aa8b732 1584
25c4c276 1585 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1586 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1587
8b9cf98c
RR		 1588 vmx->vcpu.cr0 = 0x60000010;
1589 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1590 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1591#ifdef CONFIG_X86_64
8b9cf98c 1592 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1593#endif
8b9cf98c
RR		 1594 vmx_fpu_activate(&vmx->vcpu);
1595 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1596
1597 return 0;
1598
6aa8b732
AK		 1599out:
1600 return ret;
1601}
1602
04d2cc77
AK		 1603static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1604{
1605 struct vcpu_vmx *vmx = to_vmx(vcpu);
1606
1607 vmx_vcpu_setup(vmx);
1608}
1609
6aa8b732
AK		 1610static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1611{
1612 u16 ent[2];
1613 u16 cs;
1614 u16 ip;
1615 unsigned long flags;
1616 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1617 u16 sp = vmcs_readl(GUEST_RSP);
1618 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1619
3964994b 1620 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1621 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1622 __FUNCTION__,
1623 vmcs_readl(GUEST_RSP),
1624 vmcs_readl(GUEST_SS_BASE),
1625 vmcs_read32(GUEST_SS_LIMIT));
1626 return;
1627 }
1628
e7d5d76c
LV		 1629 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1630 X86EMUL_CONTINUE) {
6aa8b732
AK		 1631 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1632 return;
1633 }
1634
1635 flags = vmcs_readl(GUEST_RFLAGS);
1636 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1637 ip = vmcs_readl(GUEST_RIP);
1638
1639
e7d5d76c
LV		 1640 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1641 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1642 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1643 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1644 return;
1645 }
1646
1647 vmcs_writel(GUEST_RFLAGS, flags &
1648 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1649 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1650 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1651 vmcs_writel(GUEST_RIP, ent[0]);
1652 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1653}
1654
85f455f7
ED		 1655static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1656{
1657 if (vcpu->rmode.active) {
1658 inject_rmode_irq(vcpu, irq);
1659 return;
1660 }
1661 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1662 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1663}
1664
6aa8b732
AK		 1665static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1666{
1667 int word_index = __ffs(vcpu->irq_summary);
1668 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1669 int irq = word_index * BITS_PER_LONG + bit_index;
1670
1671 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1672 if (!vcpu->irq_pending[word_index])
1673 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1674 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1675}
1676
c1150d8c
DL		 1677
1678static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1679 struct kvm_run *kvm_run)
6aa8b732 1680{
c1150d8c
DL		 1681 u32 cpu_based_vm_exec_control;
1682
1683 vcpu->interrupt_window_open =
1684 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1685 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1686
1687 if (vcpu->interrupt_window_open &&
1688 vcpu->irq_summary &&
1689 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1690 /*
c1150d8c 1691 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1692 */
1693 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1694
1695 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1696 if (!vcpu->interrupt_window_open &&
1697 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1698 /*
1699 * Interrupts blocked. Wait for unblock.
1700 */
c1150d8c
DL		 1701 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1702 else
1703 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1704 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1705}
1706
1707static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1708{
1709 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1710
1711 set_debugreg(dbg->bp[0], 0);
1712 set_debugreg(dbg->bp[1], 1);
1713 set_debugreg(dbg->bp[2], 2);
1714 set_debugreg(dbg->bp[3], 3);
1715
1716 if (dbg->singlestep) {
1717 unsigned long flags;
1718
1719 flags = vmcs_readl(GUEST_RFLAGS);
1720 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1721 vmcs_writel(GUEST_RFLAGS, flags);
1722 }
1723}
1724
1725static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1726 int vec, u32 err_code)
1727{
1728 if (!vcpu->rmode.active)
1729 return 0;
1730
b3f37707
NK		 1731 /*
1732 * Instruction with address size override prefix opcode 0x67
1733 * Cause the #SS fault with 0 error code in VM86 mode.
1734 */
1735 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1736 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1737 return 1;
1738 return 0;
1739}
1740
1741static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1742{
1743 u32 intr_info, error_code;
1744 unsigned long cr2, rip;
1745 u32 vect_info;
1746 enum emulation_result er;
e2dec939 1747 int r;
6aa8b732
AK		 1748
1749 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1750 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1751
1752 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1753 !is_page_fault(intr_info)) {
1754 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1755 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1756 }
1757
85f455f7 1758 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1759 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1760 set_bit(irq, vcpu->irq_pending);
1761 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1762 }
1763
1b6269db
AK		 1764 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1765 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1766
1767 if (is_no_device(intr_info)) {
5fd86fcf 1768 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1769 return 1;
1770 }
1771
6aa8b732
AK		 1772 error_code = 0;
1773 rip = vmcs_readl(GUEST_RIP);
1774 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1775 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1776 if (is_page_fault(intr_info)) {
1777 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1778
11ec2804 1779 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1780 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1781 if (r < 0) {
11ec2804 1782 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1783 return r;
1784 }
1785 if (!r) {
11ec2804 1786 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1787 return 1;
1788 }
1789
1790 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
11ec2804 1791 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1792
1793 switch (er) {
1794 case EMULATE_DONE:
1795 return 1;
1796 case EMULATE_DO_MMIO:
1165f5fe 1797 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1798 return 0;
1799 case EMULATE_FAIL:
054b1369 1800 kvm_report_emulation_failure(vcpu, "pagetable");
6aa8b732
AK		 1801 break;
1802 default:
1803 BUG();
1804 }
1805 }
1806
1807 if (vcpu->rmode.active &&
1808 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1809 error_code)) {
1810 if (vcpu->halt_request) {
1811 vcpu->halt_request = 0;
1812 return kvm_emulate_halt(vcpu);
1813 }
6aa8b732 1814 return 1;
72d6e5a0 1815 }
6aa8b732
AK		 1816
1817 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1818 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1819 return 0;
1820 }
1821 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1822 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1823 kvm_run->ex.error_code = error_code;
1824 return 0;
1825}
1826
1827static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1828 struct kvm_run *kvm_run)
1829{
1165f5fe 1830 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1831 return 1;
1832}
1833
988ad74f
AK		 1834static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1835{
1836 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1837 return 0;
1838}
6aa8b732 1839
6aa8b732
AK		 1840static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1841{
bfdaab09 1842 unsigned long exit_qualification;
039576c0
AK		 1843 int size, down, in, string, rep;
1844 unsigned port;
6aa8b732 1845
1165f5fe 1846 ++vcpu->stat.io_exits;
bfdaab09 1847 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1848 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1849
1850 if (string) {
1851 if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1852 return 0;
1853 return 1;
1854 }
1855
1856 size = (exit_qualification & 7) + 1;
1857 in = (exit_qualification & 8) != 0;
039576c0 1858 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1859 rep = (exit_qualification & 32) != 0;
1860 port = exit_qualification >> 16;
e70669ab 1861
3090dd73 1862 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1863}
1864
102d8325
IM		 1865static void
1866vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1867{
1868 /*
1869 * Patch in the VMCALL instruction:
1870 */
1871 hypercall[0] = 0x0f;
1872 hypercall[1] = 0x01;
1873 hypercall[2] = 0xc1;
1874 hypercall[3] = 0xc3;
1875}
1876
6aa8b732
AK		 1877static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1878{
bfdaab09 1879 unsigned long exit_qualification;
6aa8b732
AK		 1880 int cr;
1881 int reg;
1882
bfdaab09 1883 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1884 cr = exit_qualification & 15;
1885 reg = (exit_qualification >> 8) & 15;
1886 switch ((exit_qualification >> 4) & 3) {
1887 case 0: /* mov to cr */
1888 switch (cr) {
1889 case 0:
1890 vcpu_load_rsp_rip(vcpu);
1891 set_cr0(vcpu, vcpu->regs[reg]);
1892 skip_emulated_instruction(vcpu);
1893 return 1;
1894 case 3:
1895 vcpu_load_rsp_rip(vcpu);
1896 set_cr3(vcpu, vcpu->regs[reg]);
1897 skip_emulated_instruction(vcpu);
1898 return 1;
1899 case 4:
1900 vcpu_load_rsp_rip(vcpu);
1901 set_cr4(vcpu, vcpu->regs[reg]);
1902 skip_emulated_instruction(vcpu);
1903 return 1;
1904 case 8:
1905 vcpu_load_rsp_rip(vcpu);
1906 set_cr8(vcpu, vcpu->regs[reg]);
1907 skip_emulated_instruction(vcpu);
253abdee
YS		 1908 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1909 return 0;
6aa8b732
AK		 1910 };
1911 break;
25c4c276
AL		 1912 case 2: /* clts */
1913 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1914 vmx_fpu_deactivate(vcpu);
707d92fa 1915 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1916 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1917 vmx_fpu_activate(vcpu);
25c4c276
AL		 1918 skip_emulated_instruction(vcpu);
1919 return 1;
6aa8b732
AK		 1920 case 1: /*mov from cr*/
1921 switch (cr) {
1922 case 3:
1923 vcpu_load_rsp_rip(vcpu);
1924 vcpu->regs[reg] = vcpu->cr3;
1925 vcpu_put_rsp_rip(vcpu);
1926 skip_emulated_instruction(vcpu);
1927 return 1;
1928 case 8:
6aa8b732 1929 vcpu_load_rsp_rip(vcpu);
7017fc3d 1930 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 1931 vcpu_put_rsp_rip(vcpu);
1932 skip_emulated_instruction(vcpu);
1933 return 1;
1934 }
1935 break;
1936 case 3: /* lmsw */
1937 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1938
1939 skip_emulated_instruction(vcpu);
1940 return 1;
1941 default:
1942 break;
1943 }
1944 kvm_run->exit_reason = 0;
f0242478 1945 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 1946 (int)(exit_qualification >> 4) & 3, cr);
1947 return 0;
1948}
1949
1950static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1951{
bfdaab09 1952 unsigned long exit_qualification;
6aa8b732
AK		 1953 unsigned long val;
1954 int dr, reg;
1955
1956 /*
1957 * FIXME: this code assumes the host is debugging the guest.
1958 * need to deal with guest debugging itself too.
1959 */
bfdaab09 1960 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1961 dr = exit_qualification & 7;
1962 reg = (exit_qualification >> 8) & 15;
1963 vcpu_load_rsp_rip(vcpu);
1964 if (exit_qualification & 16) {
1965 /* mov from dr */
1966 switch (dr) {
1967 case 6:
1968 val = 0xffff0ff0;
1969 break;
1970 case 7:
1971 val = 0x400;
1972 break;
1973 default:
1974 val = 0;
1975 }
1976 vcpu->regs[reg] = val;
1977 } else {
1978 /* mov to dr */
1979 }
1980 vcpu_put_rsp_rip(vcpu);
1981 skip_emulated_instruction(vcpu);
1982 return 1;
1983}
1984
1985static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1986{
06465c5a
AK		 1987 kvm_emulate_cpuid(vcpu);
1988 return 1;
6aa8b732
AK		 1989}
1990
1991static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1992{
1993 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1994 u64 data;
1995
1996 if (vmx_get_msr(vcpu, ecx, &data)) {
1997 vmx_inject_gp(vcpu, 0);
1998 return 1;
1999 }
2000
2001 /* FIXME: handling of bits 32:63 of rax, rdx */
2002 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2003 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2004 skip_emulated_instruction(vcpu);
2005 return 1;
2006}
2007
2008static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2009{
2010 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2011 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2012 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2013
2014 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2015 vmx_inject_gp(vcpu, 0);
2016 return 1;
2017 }
2018
2019 skip_emulated_instruction(vcpu);
2020 return 1;
2021}
2022
6e5d865c
YS		 2023static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2024 struct kvm_run *kvm_run)
2025{
2026 return 1;
2027}
2028
6aa8b732
AK		 2029static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2030 struct kvm_run *kvm_run)
2031{
85f455f7
ED		 2032 u32 cpu_based_vm_exec_control;
2033
2034 /* clear pending irq */
2035 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2036 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2037 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2038 /*
2039 * If the user space waits to inject interrupts, exit as soon as
2040 * possible
2041 */
2042 if (kvm_run->request_interrupt_window &&
022a9308 2043 !vcpu->irq_summary) {
c1150d8c 2044 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2045 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2046 return 0;
2047 }
6aa8b732
AK		 2048 return 1;
2049}
2050
2051static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2052{
2053 skip_emulated_instruction(vcpu);
d3bef15f 2054 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2055}
2056
c21415e8
IM		 2057static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2058{
510043da 2059 skip_emulated_instruction(vcpu);
270fd9b9 2060 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 2061}
2062
6aa8b732
AK		 2063/*
2064 * The exit handlers return 1 if the exit was handled fully and guest execution
2065 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2066 * to be done to userspace and return 0.
2067 */
2068static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2069 struct kvm_run *kvm_run) = {
2070 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2071 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2072 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2073 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2074 [EXIT_REASON_CR_ACCESS] = handle_cr,
2075 [EXIT_REASON_DR_ACCESS] = handle_dr,
2076 [EXIT_REASON_CPUID] = handle_cpuid,
2077 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2078 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2079 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2080 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2081 [EXIT_REASON_VMCALL] = handle_vmcall,
6e5d865c 2082 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
6aa8b732
AK		 2083};
2084
2085static const int kvm_vmx_max_exit_handlers =
50a3485c 2086 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2087
2088/*
2089 * The guest has exited. See if we can fix it or if we need userspace
2090 * assistance.
2091 */
2092static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2093{
2094 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2095 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78
AK		 2096 struct vcpu_vmx *vmx = to_vmx(vcpu);
2097
2098 if (unlikely(vmx->fail)) {
2099 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2100 kvm_run->fail_entry.hardware_entry_failure_reason
2101 = vmcs_read32(VM_INSTRUCTION_ERROR);
2102 return 0;
2103 }
6aa8b732
AK		 2104
2105 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2106 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2107 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2108 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2109 if (exit_reason < kvm_vmx_max_exit_handlers
2110 && kvm_vmx_exit_handlers[exit_reason])
2111 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2112 else {
2113 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2114 kvm_run->hw.hardware_exit_reason = exit_reason;
2115 }
2116 return 0;
2117}
2118
d9e368d6
AK		 2119static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2120{
d9e368d6
AK		 2121}
2122
6e5d865c
YS		 2123static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2124{
2125 int max_irr, tpr;
2126
2127 if (!vm_need_tpr_shadow(vcpu->kvm))
2128 return;
2129
2130 if (!kvm_lapic_enabled(vcpu) ||
2131 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2132 vmcs_write32(TPR_THRESHOLD, 0);
2133 return;
2134 }
2135
2136 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2137 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2138}
2139
85f455f7
ED		 2140static void enable_irq_window(struct kvm_vcpu *vcpu)
2141{
2142 u32 cpu_based_vm_exec_control;
2143
2144 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2145 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2146 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2147}
2148
2149static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2150{
2151 u32 idtv_info_field, intr_info_field;
2152 int has_ext_irq, interrupt_window_open;
1b9778da 2153 int vector;
85f455f7 2154
1b9778da 2155 kvm_inject_pending_timer_irqs(vcpu);
6e5d865c
YS		 2156 update_tpr_threshold(vcpu);
2157
85f455f7
ED		 2158 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2159 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2160 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2161 if (intr_info_field & INTR_INFO_VALID_MASK) {
2162 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2163 /* TODO: fault when IDT_Vectoring */
2164 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2165 }
2166 if (has_ext_irq)
2167 enable_irq_window(vcpu);
2168 return;
2169 }
2170 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2171 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2172 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2173 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2174
2175 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2176 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2177 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2178 if (unlikely(has_ext_irq))
2179 enable_irq_window(vcpu);
2180 return;
2181 }
2182 if (!has_ext_irq)
2183 return;
2184 interrupt_window_open =
2185 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2186 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2187 if (interrupt_window_open) {
2188 vector = kvm_cpu_get_interrupt(vcpu);
2189 vmx_inject_irq(vcpu, vector);
2190 kvm_timer_intr_post(vcpu, vector);
2191 } else
85f455f7
ED		 2192 enable_irq_window(vcpu);
2193}
2194
04d2cc77 2195static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2196{
a2fa3e9f 2197 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2198 u32 intr_info;
e6adf283
AK		 2199
2200 /*
2201 * Loading guest fpu may have cleared host cr0.ts
2202 */
2203 vmcs_writel(HOST_CR0, read_cr0());
2204
6aa8b732
AK		 2205 asm (
2206 /* Store host registers */
05b3e0c2 2207#ifdef CONFIG_X86_64
6aa8b732
AK		 2208 "push %%rax; push %%rbx; push %%rdx;"
2209 "push %%rsi; push %%rdi; push %%rbp;"
2210 "push %%r8; push %%r9; push %%r10; push %%r11;"
2211 "push %%r12; push %%r13; push %%r14; push %%r15;"
2212 "push %%rcx \n\t"
2213 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2214#else
2215 "pusha; push %%ecx \n\t"
2216 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2217#endif
2218 /* Check if vmlaunch of vmresume is needed */
2219 "cmp $0, %1 \n\t"
2220 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2221#ifdef CONFIG_X86_64
6aa8b732
AK		 2222 "mov %c[cr2](%3), %%rax \n\t"
2223 "mov %%rax, %%cr2 \n\t"
2224 "mov %c[rax](%3), %%rax \n\t"
2225 "mov %c[rbx](%3), %%rbx \n\t"
2226 "mov %c[rdx](%3), %%rdx \n\t"
2227 "mov %c[rsi](%3), %%rsi \n\t"
2228 "mov %c[rdi](%3), %%rdi \n\t"
2229 "mov %c[rbp](%3), %%rbp \n\t"
2230 "mov %c[r8](%3), %%r8 \n\t"
2231 "mov %c[r9](%3), %%r9 \n\t"
2232 "mov %c[r10](%3), %%r10 \n\t"
2233 "mov %c[r11](%3), %%r11 \n\t"
2234 "mov %c[r12](%3), %%r12 \n\t"
2235 "mov %c[r13](%3), %%r13 \n\t"
2236 "mov %c[r14](%3), %%r14 \n\t"
2237 "mov %c[r15](%3), %%r15 \n\t"
2238 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2239#else
2240 "mov %c[cr2](%3), %%eax \n\t"
2241 "mov %%eax, %%cr2 \n\t"
2242 "mov %c[rax](%3), %%eax \n\t"
2243 "mov %c[rbx](%3), %%ebx \n\t"
2244 "mov %c[rdx](%3), %%edx \n\t"
2245 "mov %c[rsi](%3), %%esi \n\t"
2246 "mov %c[rdi](%3), %%edi \n\t"
2247 "mov %c[rbp](%3), %%ebp \n\t"
2248 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2249#endif
2250 /* Enter guest mode */
cd2276a7 2251 "jne .Llaunched \n\t"
6aa8b732 2252 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2253 "jmp .Lkvm_vmx_return \n\t"
2254 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2255 ".Lkvm_vmx_return: "
6aa8b732 2256 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2257#ifdef CONFIG_X86_64
96958231 2258 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2259 "mov %%rax, %c[rax](%3) \n\t"
2260 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2261 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2262 "mov %%rdx, %c[rdx](%3) \n\t"
2263 "mov %%rsi, %c[rsi](%3) \n\t"
2264 "mov %%rdi, %c[rdi](%3) \n\t"
2265 "mov %%rbp, %c[rbp](%3) \n\t"
2266 "mov %%r8, %c[r8](%3) \n\t"
2267 "mov %%r9, %c[r9](%3) \n\t"
2268 "mov %%r10, %c[r10](%3) \n\t"
2269 "mov %%r11, %c[r11](%3) \n\t"
2270 "mov %%r12, %c[r12](%3) \n\t"
2271 "mov %%r13, %c[r13](%3) \n\t"
2272 "mov %%r14, %c[r14](%3) \n\t"
2273 "mov %%r15, %c[r15](%3) \n\t"
2274 "mov %%cr2, %%rax \n\t"
2275 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2276 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2277
2278 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2279 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2280 "pop %%rbp; pop %%rdi; pop %%rsi;"
2281 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2282#else
96958231 2283 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2284 "mov %%eax, %c[rax](%3) \n\t"
2285 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2286 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2287 "mov %%edx, %c[rdx](%3) \n\t"
2288 "mov %%esi, %c[rsi](%3) \n\t"
2289 "mov %%edi, %c[rdi](%3) \n\t"
2290 "mov %%ebp, %c[rbp](%3) \n\t"
2291 "mov %%cr2, %%eax \n\t"
2292 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2293 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2294
2295 "pop %%ecx; popa \n\t"
2296#endif
2297 "setbe %0 \n\t"
29bd8a78 2298 : "=q" (vmx->fail)
a2fa3e9f 2299 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2300 "c"(vcpu),
2301 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2302 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2303 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2304 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2305 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2306 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2307 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2308#ifdef CONFIG_X86_64
6aa8b732
AK		 2309 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2310 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2311 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2312 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2313 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2314 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2315 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2316 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2317#endif
2318 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2319 : "cc", "memory" );
2320
c1150d8c 2321 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2322
6aa8b732 2323 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2324 vmx->launched = 1;
1b6269db
AK		 2325
2326 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2327
2328 /* We need to handle NMIs before interrupts are enabled */
2329 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2330 asm("int $2");
6aa8b732
AK		 2331}
2332
6aa8b732
AK		 2333static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2334 unsigned long addr,
2335 u32 err_code)
2336{
2337 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2338
1165f5fe 2339 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2340
2341 if (is_page_fault(vect_info)) {
2342 printk(KERN_DEBUG "inject_page_fault: "
2343 "double fault 0x%lx @ 0x%lx\n",
2344 addr, vmcs_readl(GUEST_RIP));
2345 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2346 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2347 DF_VECTOR |
2348 INTR_TYPE_EXCEPTION |
2349 INTR_INFO_DELIEVER_CODE_MASK |
2350 INTR_INFO_VALID_MASK);
2351 return;
2352 }
2353 vcpu->cr2 = addr;
2354 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2356 PF_VECTOR |
2357 INTR_TYPE_EXCEPTION |
2358 INTR_INFO_DELIEVER_CODE_MASK |
2359 INTR_INFO_VALID_MASK);
2360
2361}
2362
2363static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2364{
a2fa3e9f
GH		 2365 struct vcpu_vmx *vmx = to_vmx(vcpu);
2366
2367 if (vmx->vmcs) {
8b9cf98c 2368 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2369 free_vmcs(vmx->vmcs);
2370 vmx->vmcs = NULL;
6aa8b732
AK		 2371 }
2372}
2373
2374static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2375{
fb3f0f51
RR		 2376 struct vcpu_vmx *vmx = to_vmx(vcpu);
2377
6aa8b732 2378 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2379 kfree(vmx->host_msrs);
2380 kfree(vmx->guest_msrs);
2381 kvm_vcpu_uninit(vcpu);
a4770347 2382 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2383}
2384
fb3f0f51 2385static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2386{
fb3f0f51 2387 int err;
c16f862d 2388 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2389 int cpu;
6aa8b732 2390
a2fa3e9f 2391 if (!vmx)
fb3f0f51
RR		 2392 return ERR_PTR(-ENOMEM);
2393
2394 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2395 if (err)
2396 goto free_vcpu;
965b58a5 2397
97222cc8
ED		 2398 if (irqchip_in_kernel(kvm)) {
2399 err = kvm_create_lapic(&vmx->vcpu);
2400 if (err < 0)
2401 goto free_vcpu;
2402 }
2403
a2fa3e9f 2404 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2405 if (!vmx->guest_msrs) {
2406 err = -ENOMEM;
2407 goto uninit_vcpu;
2408 }
965b58a5 2409
a2fa3e9f
GH		 2410 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2411 if (!vmx->host_msrs)
fb3f0f51 2412 goto free_guest_msrs;
965b58a5 2413
a2fa3e9f
GH		 2414 vmx->vmcs = alloc_vmcs();
2415 if (!vmx->vmcs)
fb3f0f51 2416 goto free_msrs;
a2fa3e9f
GH		 2417
2418 vmcs_clear(vmx->vmcs);
2419
15ad7146
AK		 2420 cpu = get_cpu();
2421 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2422 err = vmx_vcpu_setup(vmx);
fb3f0f51 2423 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2424 put_cpu();
fb3f0f51
RR		 2425 if (err)
2426 goto free_vmcs;
2427
2428 return &vmx->vcpu;
2429
2430free_vmcs:
2431 free_vmcs(vmx->vmcs);
2432free_msrs:
2433 kfree(vmx->host_msrs);
2434free_guest_msrs:
2435 kfree(vmx->guest_msrs);
2436uninit_vcpu:
2437 kvm_vcpu_uninit(&vmx->vcpu);
2438free_vcpu:
a4770347 2439 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2440 return ERR_PTR(err);
6aa8b732
AK		 2441}
2442
002c7f7c
YS		 2443static void __init vmx_check_processor_compat(void *rtn)
2444{
2445 struct vmcs_config vmcs_conf;
2446
2447 *(int *)rtn = 0;
2448 if (setup_vmcs_config(&vmcs_conf) < 0)
2449 *(int *)rtn = -EIO;
2450 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2451 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2452 smp_processor_id());
2453 *(int *)rtn = -EIO;
2454 }
2455}
2456
cbdd1bea 2457static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2458 .cpu_has_kvm_support = cpu_has_kvm_support,
2459 .disabled_by_bios = vmx_disabled_by_bios,
2460 .hardware_setup = hardware_setup,
2461 .hardware_unsetup = hardware_unsetup,
002c7f7c 2462 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2463 .hardware_enable = hardware_enable,
2464 .hardware_disable = hardware_disable,
2465
2466 .vcpu_create = vmx_create_vcpu,
2467 .vcpu_free = vmx_free_vcpu,
04d2cc77 2468 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2469
04d2cc77 2470 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2471 .vcpu_load = vmx_vcpu_load,
2472 .vcpu_put = vmx_vcpu_put,
774c47f1 2473 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2474
2475 .set_guest_debug = set_guest_debug,
04d2cc77 2476 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2477 .get_msr = vmx_get_msr,
2478 .set_msr = vmx_set_msr,
2479 .get_segment_base = vmx_get_segment_base,
2480 .get_segment = vmx_get_segment,
2481 .set_segment = vmx_set_segment,
6aa8b732 2482 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2483 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2484 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2485 .set_cr3 = vmx_set_cr3,
2486 .set_cr4 = vmx_set_cr4,
05b3e0c2 2487#ifdef CONFIG_X86_64
6aa8b732
AK		 2488 .set_efer = vmx_set_efer,
2489#endif
2490 .get_idt = vmx_get_idt,
2491 .set_idt = vmx_set_idt,
2492 .get_gdt = vmx_get_gdt,
2493 .set_gdt = vmx_set_gdt,
2494 .cache_regs = vcpu_load_rsp_rip,
2495 .decache_regs = vcpu_put_rsp_rip,
2496 .get_rflags = vmx_get_rflags,
2497 .set_rflags = vmx_set_rflags,
2498
2499 .tlb_flush = vmx_flush_tlb,
2500 .inject_page_fault = vmx_inject_page_fault,
2501
2502 .inject_gp = vmx_inject_gp,
2503
2504 .run = vmx_vcpu_run,
04d2cc77 2505 .handle_exit = kvm_handle_exit,
6aa8b732 2506 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2507 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2508 .get_irq = vmx_get_irq,
2509 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2510 .inject_pending_irq = vmx_intr_assist,
2511 .inject_pending_vectors = do_interrupt_requests,
6aa8b732
AK		 2512};
2513
2514static int __init vmx_init(void)
2515{
fdef3ad1
HQ		 2516 void *iova;
2517 int r;
2518
2519 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2520 if (!vmx_io_bitmap_a)
2521 return -ENOMEM;
2522
2523 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2524 if (!vmx_io_bitmap_b) {
2525 r = -ENOMEM;
2526 goto out;
2527 }
2528
2529 /*
2530 * Allow direct access to the PC debug port (it is often used for I/O
2531 * delays, but the vmexits simply slow things down).
2532 */
2533 iova = kmap(vmx_io_bitmap_a);
2534 memset(iova, 0xff, PAGE_SIZE);
2535 clear_bit(0x80, iova);
cd0536d7 2536 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2537
2538 iova = kmap(vmx_io_bitmap_b);
2539 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2540 kunmap(vmx_io_bitmap_b);
fdef3ad1 2541
cbdd1bea 2542 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2543 if (r)
2544 goto out1;
2545
2546 return 0;
2547
2548out1:
2549 __free_page(vmx_io_bitmap_b);
2550out:
2551 __free_page(vmx_io_bitmap_a);
2552 return r;
6aa8b732
AK		 2553}
2554
2555static void __exit vmx_exit(void)
2556{
fdef3ad1
HQ		 2557 __free_page(vmx_io_bitmap_b);
2558 __free_page(vmx_io_bitmap_a);
2559
cbdd1bea 2560 kvm_exit_x86();
6aa8b732
AK		 2561}
2562
2563module_init(vmx_init)
2564module_exit(vmx_exit)
Ubuntu Artful kernel mirror