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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 FB |
26 | #include <stdlib.h> |
27 | #include <stdio.h> | |
28 | #include <stdarg.h> | |
29 | #include <string.h> | |
30 | #include <errno.h> | |
31 | #include <unistd.h> | |
32 | #include <inttypes.h> | |
33 | ||
6180a181 FB |
34 | #include "cpu.h" |
35 | #include "exec-all.h" | |
ca10f867 | 36 | #include "qemu-common.h" |
b67d9a52 | 37 | #include "tcg.h" |
b3c7724c | 38 | #include "hw/hw.h" |
74576198 | 39 | #include "osdep.h" |
7ba1e619 | 40 | #include "kvm.h" |
53a5960a PB |
41 | #if defined(CONFIG_USER_ONLY) |
42 | #include <qemu.h> | |
43 | #endif | |
54936004 | 44 | |
fd6ce8f6 | 45 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 46 | //#define DEBUG_FLUSH |
9fa3e853 | 47 | //#define DEBUG_TLB |
67d3b957 | 48 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
49 | |
50 | /* make various TB consistency checks */ | |
5fafdf24 TS |
51 | //#define DEBUG_TB_CHECK |
52 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 53 | |
1196be37 | 54 | //#define DEBUG_IOPORT |
db7b5426 | 55 | //#define DEBUG_SUBPAGE |
1196be37 | 56 | |
99773bd4 PB |
57 | #if !defined(CONFIG_USER_ONLY) |
58 | /* TB consistency checks only implemented for usermode emulation. */ | |
59 | #undef DEBUG_TB_CHECK | |
60 | #endif | |
61 | ||
9fa3e853 FB |
62 | #define SMC_BITMAP_USE_THRESHOLD 10 |
63 | ||
108c49b8 FB |
64 | #if defined(TARGET_SPARC64) |
65 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 | |
5dcb6b91 BS |
66 | #elif defined(TARGET_SPARC) |
67 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
bedb69ea JM |
68 | #elif defined(TARGET_ALPHA) |
69 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
70 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 | |
108c49b8 FB |
71 | #elif defined(TARGET_PPC64) |
72 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 | |
4a1418e0 | 73 | #elif defined(TARGET_X86_64) |
00f82b8a | 74 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
4a1418e0 | 75 | #elif defined(TARGET_I386) |
00f82b8a | 76 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
108c49b8 | 77 | #else |
108c49b8 FB |
78 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
79 | #endif | |
80 | ||
bdaf78e0 | 81 | static TranslationBlock *tbs; |
26a5f13b | 82 | int code_gen_max_blocks; |
9fa3e853 | 83 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 84 | static int nb_tbs; |
eb51d102 | 85 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 86 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 87 | |
141ac468 BS |
88 | #if defined(__arm__) || defined(__sparc_v9__) |
89 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
90 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
91 | section close to code segment. */ |
92 | #define code_gen_section \ | |
93 | __attribute__((__section__(".gen_code"))) \ | |
94 | __attribute__((aligned (32))) | |
f8e2af11 SW |
95 | #elif defined(_WIN32) |
96 | /* Maximum alignment for Win32 is 16. */ | |
97 | #define code_gen_section \ | |
98 | __attribute__((aligned (16))) | |
d03d860b BS |
99 | #else |
100 | #define code_gen_section \ | |
101 | __attribute__((aligned (32))) | |
102 | #endif | |
103 | ||
104 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
105 | static uint8_t *code_gen_buffer; |
106 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 107 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 108 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
109 | uint8_t *code_gen_ptr; |
110 | ||
e2eef170 | 111 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 112 | int phys_ram_fd; |
1ccde1cb | 113 | uint8_t *phys_ram_dirty; |
74576198 | 114 | static int in_migration; |
94a6b54f PB |
115 | |
116 | typedef struct RAMBlock { | |
117 | uint8_t *host; | |
c227f099 AL |
118 | ram_addr_t offset; |
119 | ram_addr_t length; | |
94a6b54f PB |
120 | struct RAMBlock *next; |
121 | } RAMBlock; | |
122 | ||
123 | static RAMBlock *ram_blocks; | |
124 | /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug) | |
ccbb4d44 | 125 | then we can no longer assume contiguous ram offsets, and external uses |
94a6b54f | 126 | of this variable will break. */ |
c227f099 | 127 | ram_addr_t last_ram_offset; |
e2eef170 | 128 | #endif |
9fa3e853 | 129 | |
6a00d601 FB |
130 | CPUState *first_cpu; |
131 | /* current CPU in the current thread. It is only valid inside | |
132 | cpu_exec() */ | |
5fafdf24 | 133 | CPUState *cpu_single_env; |
2e70f6ef | 134 | /* 0 = Do not count executed instructions. |
bf20dc07 | 135 | 1 = Precise instruction counting. |
2e70f6ef PB |
136 | 2 = Adaptive rate instruction counting. */ |
137 | int use_icount = 0; | |
138 | /* Current instruction counter. While executing translated code this may | |
139 | include some instructions that have not yet been executed. */ | |
140 | int64_t qemu_icount; | |
6a00d601 | 141 | |
54936004 | 142 | typedef struct PageDesc { |
92e873b9 | 143 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 144 | TranslationBlock *first_tb; |
9fa3e853 FB |
145 | /* in order to optimize self modifying code, we count the number |
146 | of lookups we do to a given page to use a bitmap */ | |
147 | unsigned int code_write_count; | |
148 | uint8_t *code_bitmap; | |
149 | #if defined(CONFIG_USER_ONLY) | |
150 | unsigned long flags; | |
151 | #endif | |
54936004 FB |
152 | } PageDesc; |
153 | ||
92e873b9 | 154 | typedef struct PhysPageDesc { |
0f459d16 | 155 | /* offset in host memory of the page + io_index in the low bits */ |
c227f099 AL |
156 | ram_addr_t phys_offset; |
157 | ram_addr_t region_offset; | |
92e873b9 FB |
158 | } PhysPageDesc; |
159 | ||
54936004 | 160 | #define L2_BITS 10 |
bedb69ea JM |
161 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
162 | /* XXX: this is a temporary hack for alpha target. | |
163 | * In the future, this is to be replaced by a multi-level table | |
164 | * to actually be able to handle the complete 64 bits address space. | |
165 | */ | |
166 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) | |
167 | #else | |
03875444 | 168 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
bedb69ea | 169 | #endif |
54936004 FB |
170 | |
171 | #define L1_SIZE (1 << L1_BITS) | |
172 | #define L2_SIZE (1 << L2_BITS) | |
173 | ||
83fb7adf FB |
174 | unsigned long qemu_real_host_page_size; |
175 | unsigned long qemu_host_page_bits; | |
176 | unsigned long qemu_host_page_size; | |
177 | unsigned long qemu_host_page_mask; | |
54936004 | 178 | |
92e873b9 | 179 | /* XXX: for system emulation, it could just be an array */ |
54936004 | 180 | static PageDesc *l1_map[L1_SIZE]; |
bdaf78e0 | 181 | static PhysPageDesc **l1_phys_map; |
54936004 | 182 | |
e2eef170 PB |
183 | #if !defined(CONFIG_USER_ONLY) |
184 | static void io_mem_init(void); | |
185 | ||
33417e70 | 186 | /* io memory support */ |
33417e70 FB |
187 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
188 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 189 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 190 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
191 | static int io_mem_watch; |
192 | #endif | |
33417e70 | 193 | |
34865134 | 194 | /* log support */ |
1e8b27ca JR |
195 | #ifdef WIN32 |
196 | static const char *logfilename = "qemu.log"; | |
197 | #else | |
d9b630fd | 198 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 199 | #endif |
34865134 FB |
200 | FILE *logfile; |
201 | int loglevel; | |
e735b91c | 202 | static int log_append = 0; |
34865134 | 203 | |
e3db7226 FB |
204 | /* statistics */ |
205 | static int tlb_flush_count; | |
206 | static int tb_flush_count; | |
207 | static int tb_phys_invalidate_count; | |
208 | ||
db7b5426 | 209 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
c227f099 AL |
210 | typedef struct subpage_t { |
211 | target_phys_addr_t base; | |
d60efc6b BS |
212 | CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4]; |
213 | CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4]; | |
3ee89922 | 214 | void *opaque[TARGET_PAGE_SIZE][2][4]; |
c227f099 AL |
215 | ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; |
216 | } subpage_t; | |
db7b5426 | 217 | |
7cb69cae FB |
218 | #ifdef _WIN32 |
219 | static void map_exec(void *addr, long size) | |
220 | { | |
221 | DWORD old_protect; | |
222 | VirtualProtect(addr, size, | |
223 | PAGE_EXECUTE_READWRITE, &old_protect); | |
224 | ||
225 | } | |
226 | #else | |
227 | static void map_exec(void *addr, long size) | |
228 | { | |
4369415f | 229 | unsigned long start, end, page_size; |
7cb69cae | 230 | |
4369415f | 231 | page_size = getpagesize(); |
7cb69cae | 232 | start = (unsigned long)addr; |
4369415f | 233 | start &= ~(page_size - 1); |
7cb69cae FB |
234 | |
235 | end = (unsigned long)addr + size; | |
4369415f FB |
236 | end += page_size - 1; |
237 | end &= ~(page_size - 1); | |
7cb69cae FB |
238 | |
239 | mprotect((void *)start, end - start, | |
240 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
241 | } | |
242 | #endif | |
243 | ||
b346ff46 | 244 | static void page_init(void) |
54936004 | 245 | { |
83fb7adf | 246 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 247 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
248 | #ifdef _WIN32 |
249 | { | |
250 | SYSTEM_INFO system_info; | |
251 | ||
252 | GetSystemInfo(&system_info); | |
253 | qemu_real_host_page_size = system_info.dwPageSize; | |
254 | } | |
255 | #else | |
256 | qemu_real_host_page_size = getpagesize(); | |
257 | #endif | |
83fb7adf FB |
258 | if (qemu_host_page_size == 0) |
259 | qemu_host_page_size = qemu_real_host_page_size; | |
260 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
261 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
262 | qemu_host_page_bits = 0; | |
263 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
264 | qemu_host_page_bits++; | |
265 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
108c49b8 FB |
266 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
267 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); | |
50a9569b AZ |
268 | |
269 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
270 | { | |
271 | long long startaddr, endaddr; | |
272 | FILE *f; | |
273 | int n; | |
274 | ||
c8a706fe | 275 | mmap_lock(); |
0776590d | 276 | last_brk = (unsigned long)sbrk(0); |
50a9569b AZ |
277 | f = fopen("/proc/self/maps", "r"); |
278 | if (f) { | |
279 | do { | |
280 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); | |
281 | if (n == 2) { | |
e0b8d65a BS |
282 | startaddr = MIN(startaddr, |
283 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
284 | endaddr = MIN(endaddr, | |
285 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); | |
b5fc909e | 286 | page_set_flags(startaddr & TARGET_PAGE_MASK, |
50a9569b AZ |
287 | TARGET_PAGE_ALIGN(endaddr), |
288 | PAGE_RESERVED); | |
289 | } | |
290 | } while (!feof(f)); | |
291 | fclose(f); | |
292 | } | |
c8a706fe | 293 | mmap_unlock(); |
50a9569b AZ |
294 | } |
295 | #endif | |
54936004 FB |
296 | } |
297 | ||
434929bf | 298 | static inline PageDesc **page_l1_map(target_ulong index) |
54936004 | 299 | { |
17e2377a PB |
300 | #if TARGET_LONG_BITS > 32 |
301 | /* Host memory outside guest VM. For 32-bit targets we have already | |
302 | excluded high addresses. */ | |
d8173e0f | 303 | if (index > ((target_ulong)L2_SIZE * L1_SIZE)) |
17e2377a PB |
304 | return NULL; |
305 | #endif | |
434929bf AL |
306 | return &l1_map[index >> L2_BITS]; |
307 | } | |
308 | ||
309 | static inline PageDesc *page_find_alloc(target_ulong index) | |
310 | { | |
311 | PageDesc **lp, *p; | |
312 | lp = page_l1_map(index); | |
313 | if (!lp) | |
314 | return NULL; | |
315 | ||
54936004 FB |
316 | p = *lp; |
317 | if (!p) { | |
318 | /* allocate if not found */ | |
17e2377a | 319 | #if defined(CONFIG_USER_ONLY) |
17e2377a PB |
320 | size_t len = sizeof(PageDesc) * L2_SIZE; |
321 | /* Don't use qemu_malloc because it may recurse. */ | |
660f11be | 322 | p = mmap(NULL, len, PROT_READ | PROT_WRITE, |
17e2377a | 323 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); |
54936004 | 324 | *lp = p; |
fb1c2cd7 AJ |
325 | if (h2g_valid(p)) { |
326 | unsigned long addr = h2g(p); | |
17e2377a PB |
327 | page_set_flags(addr & TARGET_PAGE_MASK, |
328 | TARGET_PAGE_ALIGN(addr + len), | |
329 | PAGE_RESERVED); | |
330 | } | |
331 | #else | |
332 | p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE); | |
333 | *lp = p; | |
334 | #endif | |
54936004 FB |
335 | } |
336 | return p + (index & (L2_SIZE - 1)); | |
337 | } | |
338 | ||
00f82b8a | 339 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 340 | { |
434929bf AL |
341 | PageDesc **lp, *p; |
342 | lp = page_l1_map(index); | |
343 | if (!lp) | |
344 | return NULL; | |
54936004 | 345 | |
434929bf | 346 | p = *lp; |
660f11be BS |
347 | if (!p) { |
348 | return NULL; | |
349 | } | |
fd6ce8f6 FB |
350 | return p + (index & (L2_SIZE - 1)); |
351 | } | |
352 | ||
c227f099 | 353 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 354 | { |
108c49b8 | 355 | void **lp, **p; |
e3f4e2a4 | 356 | PhysPageDesc *pd; |
92e873b9 | 357 | |
108c49b8 FB |
358 | p = (void **)l1_phys_map; |
359 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 | |
360 | ||
361 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) | |
362 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS | |
363 | #endif | |
364 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); | |
92e873b9 FB |
365 | p = *lp; |
366 | if (!p) { | |
367 | /* allocate if not found */ | |
108c49b8 FB |
368 | if (!alloc) |
369 | return NULL; | |
370 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); | |
371 | memset(p, 0, sizeof(void *) * L1_SIZE); | |
372 | *lp = p; | |
373 | } | |
374 | #endif | |
375 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); | |
e3f4e2a4 PB |
376 | pd = *lp; |
377 | if (!pd) { | |
378 | int i; | |
108c49b8 FB |
379 | /* allocate if not found */ |
380 | if (!alloc) | |
381 | return NULL; | |
e3f4e2a4 PB |
382 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
383 | *lp = pd; | |
67c4d23c | 384 | for (i = 0; i < L2_SIZE; i++) { |
e3f4e2a4 | 385 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
67c4d23c PB |
386 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
387 | } | |
92e873b9 | 388 | } |
e3f4e2a4 | 389 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
92e873b9 FB |
390 | } |
391 | ||
c227f099 | 392 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 393 | { |
108c49b8 | 394 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
395 | } |
396 | ||
9fa3e853 | 397 | #if !defined(CONFIG_USER_ONLY) |
c227f099 AL |
398 | static void tlb_protect_code(ram_addr_t ram_addr); |
399 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 400 | target_ulong vaddr); |
c8a706fe PB |
401 | #define mmap_lock() do { } while(0) |
402 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 403 | #endif |
fd6ce8f6 | 404 | |
4369415f FB |
405 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
406 | ||
407 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 408 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
409 | user mode. It will change when a dedicated libc will be used */ |
410 | #define USE_STATIC_CODE_GEN_BUFFER | |
411 | #endif | |
412 | ||
413 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
414 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; | |
415 | #endif | |
416 | ||
8fcd3692 | 417 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 418 | { |
4369415f FB |
419 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
420 | code_gen_buffer = static_code_gen_buffer; | |
421 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
422 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
423 | #else | |
26a5f13b FB |
424 | code_gen_buffer_size = tb_size; |
425 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
426 | #if defined(CONFIG_USER_ONLY) |
427 | /* in user mode, phys_ram_size is not meaningful */ | |
428 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
429 | #else | |
ccbb4d44 | 430 | /* XXX: needs adjustments */ |
94a6b54f | 431 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 432 | #endif |
26a5f13b FB |
433 | } |
434 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
435 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
436 | /* The code gen buffer location may have constraints depending on | |
437 | the host cpu and OS */ | |
438 | #if defined(__linux__) | |
439 | { | |
440 | int flags; | |
141ac468 BS |
441 | void *start = NULL; |
442 | ||
26a5f13b FB |
443 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
444 | #if defined(__x86_64__) | |
445 | flags |= MAP_32BIT; | |
446 | /* Cannot map more than that */ | |
447 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
448 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
449 | #elif defined(__sparc_v9__) |
450 | // Map the buffer below 2G, so we can use direct calls and branches | |
451 | flags |= MAP_FIXED; | |
452 | start = (void *) 0x60000000UL; | |
453 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
454 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 455 | #elif defined(__arm__) |
63d41246 | 456 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
457 | flags |= MAP_FIXED; |
458 | start = (void *) 0x01000000UL; | |
459 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
460 | code_gen_buffer_size = 16 * 1024 * 1024; | |
26a5f13b | 461 | #endif |
141ac468 BS |
462 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
463 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
464 | flags, -1, 0); |
465 | if (code_gen_buffer == MAP_FAILED) { | |
466 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
467 | exit(1); | |
468 | } | |
469 | } | |
a167ba50 | 470 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
06e67a82 AL |
471 | { |
472 | int flags; | |
473 | void *addr = NULL; | |
474 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
475 | #if defined(__x86_64__) | |
476 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
477 | * 0x40000000 is free */ | |
478 | flags |= MAP_FIXED; | |
479 | addr = (void *)0x40000000; | |
480 | /* Cannot map more than that */ | |
481 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
482 | code_gen_buffer_size = (800 * 1024 * 1024); | |
483 | #endif | |
484 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
485 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
486 | flags, -1, 0); | |
487 | if (code_gen_buffer == MAP_FAILED) { | |
488 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
489 | exit(1); | |
490 | } | |
491 | } | |
26a5f13b FB |
492 | #else |
493 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
494 | map_exec(code_gen_buffer, code_gen_buffer_size); |
495 | #endif | |
4369415f | 496 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
497 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
498 | code_gen_buffer_max_size = code_gen_buffer_size - | |
499 | code_gen_max_block_size(); | |
500 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
501 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
502 | } | |
503 | ||
504 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
505 | (in bytes) allocated to the translation buffer. Zero means default | |
506 | size. */ | |
507 | void cpu_exec_init_all(unsigned long tb_size) | |
508 | { | |
26a5f13b FB |
509 | cpu_gen_init(); |
510 | code_gen_alloc(tb_size); | |
511 | code_gen_ptr = code_gen_buffer; | |
4369415f | 512 | page_init(); |
e2eef170 | 513 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 514 | io_mem_init(); |
e2eef170 | 515 | #endif |
26a5f13b FB |
516 | } |
517 | ||
9656f324 PB |
518 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
519 | ||
d4bfa4d7 | 520 | static void cpu_common_pre_save(void *opaque) |
9656f324 | 521 | { |
d4bfa4d7 | 522 | CPUState *env = opaque; |
9656f324 | 523 | |
4c0960c0 | 524 | cpu_synchronize_state(env); |
9656f324 PB |
525 | } |
526 | ||
e7f4eff7 | 527 | static int cpu_common_pre_load(void *opaque) |
9656f324 PB |
528 | { |
529 | CPUState *env = opaque; | |
530 | ||
4c0960c0 | 531 | cpu_synchronize_state(env); |
e7f4eff7 JQ |
532 | return 0; |
533 | } | |
534 | ||
e59fb374 | 535 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
536 | { |
537 | CPUState *env = opaque; | |
9656f324 | 538 | |
3098dba0 AJ |
539 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
540 | version_id is increased. */ | |
541 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
542 | tlb_flush(env, 1); |
543 | ||
544 | return 0; | |
545 | } | |
e7f4eff7 JQ |
546 | |
547 | static const VMStateDescription vmstate_cpu_common = { | |
548 | .name = "cpu_common", | |
549 | .version_id = 1, | |
550 | .minimum_version_id = 1, | |
551 | .minimum_version_id_old = 1, | |
552 | .pre_save = cpu_common_pre_save, | |
553 | .pre_load = cpu_common_pre_load, | |
554 | .post_load = cpu_common_post_load, | |
555 | .fields = (VMStateField []) { | |
556 | VMSTATE_UINT32(halted, CPUState), | |
557 | VMSTATE_UINT32(interrupt_request, CPUState), | |
558 | VMSTATE_END_OF_LIST() | |
559 | } | |
560 | }; | |
9656f324 PB |
561 | #endif |
562 | ||
950f1472 GC |
563 | CPUState *qemu_get_cpu(int cpu) |
564 | { | |
565 | CPUState *env = first_cpu; | |
566 | ||
567 | while (env) { | |
568 | if (env->cpu_index == cpu) | |
569 | break; | |
570 | env = env->next_cpu; | |
571 | } | |
572 | ||
573 | return env; | |
574 | } | |
575 | ||
6a00d601 | 576 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 577 | { |
6a00d601 FB |
578 | CPUState **penv; |
579 | int cpu_index; | |
580 | ||
c2764719 PB |
581 | #if defined(CONFIG_USER_ONLY) |
582 | cpu_list_lock(); | |
583 | #endif | |
6a00d601 FB |
584 | env->next_cpu = NULL; |
585 | penv = &first_cpu; | |
586 | cpu_index = 0; | |
587 | while (*penv != NULL) { | |
1e9fa730 | 588 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
589 | cpu_index++; |
590 | } | |
591 | env->cpu_index = cpu_index; | |
268a362c | 592 | env->numa_node = 0; |
72cf2d4f BS |
593 | QTAILQ_INIT(&env->breakpoints); |
594 | QTAILQ_INIT(&env->watchpoints); | |
6a00d601 | 595 | *penv = env; |
c2764719 PB |
596 | #if defined(CONFIG_USER_ONLY) |
597 | cpu_list_unlock(); | |
598 | #endif | |
b3c7724c | 599 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
e7f4eff7 | 600 | vmstate_register(cpu_index, &vmstate_cpu_common, env); |
b3c7724c PB |
601 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
602 | cpu_save, cpu_load, env); | |
603 | #endif | |
fd6ce8f6 FB |
604 | } |
605 | ||
9fa3e853 FB |
606 | static inline void invalidate_page_bitmap(PageDesc *p) |
607 | { | |
608 | if (p->code_bitmap) { | |
59817ccb | 609 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
610 | p->code_bitmap = NULL; |
611 | } | |
612 | p->code_write_count = 0; | |
613 | } | |
614 | ||
fd6ce8f6 FB |
615 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
616 | static void page_flush_tb(void) | |
617 | { | |
618 | int i, j; | |
619 | PageDesc *p; | |
620 | ||
621 | for(i = 0; i < L1_SIZE; i++) { | |
622 | p = l1_map[i]; | |
623 | if (p) { | |
9fa3e853 FB |
624 | for(j = 0; j < L2_SIZE; j++) { |
625 | p->first_tb = NULL; | |
626 | invalidate_page_bitmap(p); | |
627 | p++; | |
628 | } | |
fd6ce8f6 FB |
629 | } |
630 | } | |
631 | } | |
632 | ||
633 | /* flush all the translation blocks */ | |
d4e8164f | 634 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 635 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 636 | { |
6a00d601 | 637 | CPUState *env; |
0124311e | 638 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
639 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
640 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
641 | nb_tbs, nb_tbs > 0 ? | |
642 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 643 | #endif |
26a5f13b | 644 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
645 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
646 | ||
fd6ce8f6 | 647 | nb_tbs = 0; |
3b46e624 | 648 | |
6a00d601 FB |
649 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
650 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
651 | } | |
9fa3e853 | 652 | |
8a8a608f | 653 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 654 | page_flush_tb(); |
9fa3e853 | 655 | |
fd6ce8f6 | 656 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
657 | /* XXX: flush processor icache at this point if cache flush is |
658 | expensive */ | |
e3db7226 | 659 | tb_flush_count++; |
fd6ce8f6 FB |
660 | } |
661 | ||
662 | #ifdef DEBUG_TB_CHECK | |
663 | ||
bc98a7ef | 664 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
665 | { |
666 | TranslationBlock *tb; | |
667 | int i; | |
668 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
669 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
670 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
671 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
672 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
673 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
674 | " PC=%08lx size=%04x\n", | |
99773bd4 | 675 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
676 | } |
677 | } | |
678 | } | |
679 | } | |
680 | ||
681 | /* verify that all the pages have correct rights for code */ | |
682 | static void tb_page_check(void) | |
683 | { | |
684 | TranslationBlock *tb; | |
685 | int i, flags1, flags2; | |
3b46e624 | 686 | |
99773bd4 PB |
687 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
688 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
689 | flags1 = page_get_flags(tb->pc); |
690 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
691 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
692 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 693 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
694 | } |
695 | } | |
696 | } | |
697 | } | |
698 | ||
699 | #endif | |
700 | ||
701 | /* invalidate one TB */ | |
702 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
703 | int next_offset) | |
704 | { | |
705 | TranslationBlock *tb1; | |
706 | for(;;) { | |
707 | tb1 = *ptb; | |
708 | if (tb1 == tb) { | |
709 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
710 | break; | |
711 | } | |
712 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
713 | } | |
714 | } | |
715 | ||
9fa3e853 FB |
716 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
717 | { | |
718 | TranslationBlock *tb1; | |
719 | unsigned int n1; | |
720 | ||
721 | for(;;) { | |
722 | tb1 = *ptb; | |
723 | n1 = (long)tb1 & 3; | |
724 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
725 | if (tb1 == tb) { | |
726 | *ptb = tb1->page_next[n1]; | |
727 | break; | |
728 | } | |
729 | ptb = &tb1->page_next[n1]; | |
730 | } | |
731 | } | |
732 | ||
d4e8164f FB |
733 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
734 | { | |
735 | TranslationBlock *tb1, **ptb; | |
736 | unsigned int n1; | |
737 | ||
738 | ptb = &tb->jmp_next[n]; | |
739 | tb1 = *ptb; | |
740 | if (tb1) { | |
741 | /* find tb(n) in circular list */ | |
742 | for(;;) { | |
743 | tb1 = *ptb; | |
744 | n1 = (long)tb1 & 3; | |
745 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
746 | if (n1 == n && tb1 == tb) | |
747 | break; | |
748 | if (n1 == 2) { | |
749 | ptb = &tb1->jmp_first; | |
750 | } else { | |
751 | ptb = &tb1->jmp_next[n1]; | |
752 | } | |
753 | } | |
754 | /* now we can suppress tb(n) from the list */ | |
755 | *ptb = tb->jmp_next[n]; | |
756 | ||
757 | tb->jmp_next[n] = NULL; | |
758 | } | |
759 | } | |
760 | ||
761 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
762 | another TB */ | |
763 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
764 | { | |
765 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
766 | } | |
767 | ||
2e70f6ef | 768 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 769 | { |
6a00d601 | 770 | CPUState *env; |
8a40a180 | 771 | PageDesc *p; |
d4e8164f | 772 | unsigned int h, n1; |
c227f099 | 773 | target_phys_addr_t phys_pc; |
8a40a180 | 774 | TranslationBlock *tb1, *tb2; |
3b46e624 | 775 | |
8a40a180 FB |
776 | /* remove the TB from the hash list */ |
777 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
778 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 779 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
780 | offsetof(TranslationBlock, phys_hash_next)); |
781 | ||
782 | /* remove the TB from the page list */ | |
783 | if (tb->page_addr[0] != page_addr) { | |
784 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
785 | tb_page_remove(&p->first_tb, tb); | |
786 | invalidate_page_bitmap(p); | |
787 | } | |
788 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
789 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
790 | tb_page_remove(&p->first_tb, tb); | |
791 | invalidate_page_bitmap(p); | |
792 | } | |
793 | ||
36bdbe54 | 794 | tb_invalidated_flag = 1; |
59817ccb | 795 | |
fd6ce8f6 | 796 | /* remove the TB from the hash list */ |
8a40a180 | 797 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
798 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
799 | if (env->tb_jmp_cache[h] == tb) | |
800 | env->tb_jmp_cache[h] = NULL; | |
801 | } | |
d4e8164f FB |
802 | |
803 | /* suppress this TB from the two jump lists */ | |
804 | tb_jmp_remove(tb, 0); | |
805 | tb_jmp_remove(tb, 1); | |
806 | ||
807 | /* suppress any remaining jumps to this TB */ | |
808 | tb1 = tb->jmp_first; | |
809 | for(;;) { | |
810 | n1 = (long)tb1 & 3; | |
811 | if (n1 == 2) | |
812 | break; | |
813 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
814 | tb2 = tb1->jmp_next[n1]; | |
815 | tb_reset_jump(tb1, n1); | |
816 | tb1->jmp_next[n1] = NULL; | |
817 | tb1 = tb2; | |
818 | } | |
819 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 820 | |
e3db7226 | 821 | tb_phys_invalidate_count++; |
9fa3e853 FB |
822 | } |
823 | ||
824 | static inline void set_bits(uint8_t *tab, int start, int len) | |
825 | { | |
826 | int end, mask, end1; | |
827 | ||
828 | end = start + len; | |
829 | tab += start >> 3; | |
830 | mask = 0xff << (start & 7); | |
831 | if ((start & ~7) == (end & ~7)) { | |
832 | if (start < end) { | |
833 | mask &= ~(0xff << (end & 7)); | |
834 | *tab |= mask; | |
835 | } | |
836 | } else { | |
837 | *tab++ |= mask; | |
838 | start = (start + 8) & ~7; | |
839 | end1 = end & ~7; | |
840 | while (start < end1) { | |
841 | *tab++ = 0xff; | |
842 | start += 8; | |
843 | } | |
844 | if (start < end) { | |
845 | mask = ~(0xff << (end & 7)); | |
846 | *tab |= mask; | |
847 | } | |
848 | } | |
849 | } | |
850 | ||
851 | static void build_page_bitmap(PageDesc *p) | |
852 | { | |
853 | int n, tb_start, tb_end; | |
854 | TranslationBlock *tb; | |
3b46e624 | 855 | |
b2a7081a | 856 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
857 | |
858 | tb = p->first_tb; | |
859 | while (tb != NULL) { | |
860 | n = (long)tb & 3; | |
861 | tb = (TranslationBlock *)((long)tb & ~3); | |
862 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
863 | if (n == 0) { | |
864 | /* NOTE: tb_end may be after the end of the page, but | |
865 | it is not a problem */ | |
866 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
867 | tb_end = tb_start + tb->size; | |
868 | if (tb_end > TARGET_PAGE_SIZE) | |
869 | tb_end = TARGET_PAGE_SIZE; | |
870 | } else { | |
871 | tb_start = 0; | |
872 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
873 | } | |
874 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
875 | tb = tb->page_next[n]; | |
876 | } | |
877 | } | |
878 | ||
2e70f6ef PB |
879 | TranslationBlock *tb_gen_code(CPUState *env, |
880 | target_ulong pc, target_ulong cs_base, | |
881 | int flags, int cflags) | |
d720b93d FB |
882 | { |
883 | TranslationBlock *tb; | |
884 | uint8_t *tc_ptr; | |
885 | target_ulong phys_pc, phys_page2, virt_page2; | |
886 | int code_gen_size; | |
887 | ||
c27004ec FB |
888 | phys_pc = get_phys_addr_code(env, pc); |
889 | tb = tb_alloc(pc); | |
d720b93d FB |
890 | if (!tb) { |
891 | /* flush must be done */ | |
892 | tb_flush(env); | |
893 | /* cannot fail at this point */ | |
c27004ec | 894 | tb = tb_alloc(pc); |
2e70f6ef PB |
895 | /* Don't forget to invalidate previous TB info. */ |
896 | tb_invalidated_flag = 1; | |
d720b93d FB |
897 | } |
898 | tc_ptr = code_gen_ptr; | |
899 | tb->tc_ptr = tc_ptr; | |
900 | tb->cs_base = cs_base; | |
901 | tb->flags = flags; | |
902 | tb->cflags = cflags; | |
d07bde88 | 903 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 904 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 905 | |
d720b93d | 906 | /* check next page if needed */ |
c27004ec | 907 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 908 | phys_page2 = -1; |
c27004ec | 909 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
910 | phys_page2 = get_phys_addr_code(env, virt_page2); |
911 | } | |
912 | tb_link_phys(tb, phys_pc, phys_page2); | |
2e70f6ef | 913 | return tb; |
d720b93d | 914 | } |
3b46e624 | 915 | |
9fa3e853 FB |
916 | /* invalidate all TBs which intersect with the target physical page |
917 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
918 | the same physical page. 'is_cpu_write_access' should be true if called |
919 | from a real cpu write access: the virtual CPU will exit the current | |
920 | TB if code is modified inside this TB. */ | |
c227f099 | 921 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
922 | int is_cpu_write_access) |
923 | { | |
6b917547 | 924 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 925 | CPUState *env = cpu_single_env; |
9fa3e853 | 926 | target_ulong tb_start, tb_end; |
6b917547 AL |
927 | PageDesc *p; |
928 | int n; | |
929 | #ifdef TARGET_HAS_PRECISE_SMC | |
930 | int current_tb_not_found = is_cpu_write_access; | |
931 | TranslationBlock *current_tb = NULL; | |
932 | int current_tb_modified = 0; | |
933 | target_ulong current_pc = 0; | |
934 | target_ulong current_cs_base = 0; | |
935 | int current_flags = 0; | |
936 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
937 | |
938 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 939 | if (!p) |
9fa3e853 | 940 | return; |
5fafdf24 | 941 | if (!p->code_bitmap && |
d720b93d FB |
942 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
943 | is_cpu_write_access) { | |
9fa3e853 FB |
944 | /* build code bitmap */ |
945 | build_page_bitmap(p); | |
946 | } | |
947 | ||
948 | /* we remove all the TBs in the range [start, end[ */ | |
949 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
950 | tb = p->first_tb; | |
951 | while (tb != NULL) { | |
952 | n = (long)tb & 3; | |
953 | tb = (TranslationBlock *)((long)tb & ~3); | |
954 | tb_next = tb->page_next[n]; | |
955 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
956 | if (n == 0) { | |
957 | /* NOTE: tb_end may be after the end of the page, but | |
958 | it is not a problem */ | |
959 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
960 | tb_end = tb_start + tb->size; | |
961 | } else { | |
962 | tb_start = tb->page_addr[1]; | |
963 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
964 | } | |
965 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
966 | #ifdef TARGET_HAS_PRECISE_SMC |
967 | if (current_tb_not_found) { | |
968 | current_tb_not_found = 0; | |
969 | current_tb = NULL; | |
2e70f6ef | 970 | if (env->mem_io_pc) { |
d720b93d | 971 | /* now we have a real cpu fault */ |
2e70f6ef | 972 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
973 | } |
974 | } | |
975 | if (current_tb == tb && | |
2e70f6ef | 976 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
977 | /* If we are modifying the current TB, we must stop |
978 | its execution. We could be more precise by checking | |
979 | that the modification is after the current PC, but it | |
980 | would require a specialized function to partially | |
981 | restore the CPU state */ | |
3b46e624 | 982 | |
d720b93d | 983 | current_tb_modified = 1; |
5fafdf24 | 984 | cpu_restore_state(current_tb, env, |
2e70f6ef | 985 | env->mem_io_pc, NULL); |
6b917547 AL |
986 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
987 | ¤t_flags); | |
d720b93d FB |
988 | } |
989 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
990 | /* we need to do that to handle the case where a signal |
991 | occurs while doing tb_phys_invalidate() */ | |
992 | saved_tb = NULL; | |
993 | if (env) { | |
994 | saved_tb = env->current_tb; | |
995 | env->current_tb = NULL; | |
996 | } | |
9fa3e853 | 997 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
998 | if (env) { |
999 | env->current_tb = saved_tb; | |
1000 | if (env->interrupt_request && env->current_tb) | |
1001 | cpu_interrupt(env, env->interrupt_request); | |
1002 | } | |
9fa3e853 FB |
1003 | } |
1004 | tb = tb_next; | |
1005 | } | |
1006 | #if !defined(CONFIG_USER_ONLY) | |
1007 | /* if no code remaining, no need to continue to use slow writes */ | |
1008 | if (!p->first_tb) { | |
1009 | invalidate_page_bitmap(p); | |
d720b93d | 1010 | if (is_cpu_write_access) { |
2e70f6ef | 1011 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1012 | } |
1013 | } | |
1014 | #endif | |
1015 | #ifdef TARGET_HAS_PRECISE_SMC | |
1016 | if (current_tb_modified) { | |
1017 | /* we generate a block containing just the instruction | |
1018 | modifying the memory. It will ensure that it cannot modify | |
1019 | itself */ | |
ea1c1802 | 1020 | env->current_tb = NULL; |
2e70f6ef | 1021 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1022 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1023 | } |
fd6ce8f6 | 1024 | #endif |
9fa3e853 | 1025 | } |
fd6ce8f6 | 1026 | |
9fa3e853 | 1027 | /* len must be <= 8 and start must be a multiple of len */ |
c227f099 | 1028 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
1029 | { |
1030 | PageDesc *p; | |
1031 | int offset, b; | |
59817ccb | 1032 | #if 0 |
a4193c8a | 1033 | if (1) { |
93fcfe39 AL |
1034 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1035 | cpu_single_env->mem_io_vaddr, len, | |
1036 | cpu_single_env->eip, | |
1037 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1038 | } |
1039 | #endif | |
9fa3e853 | 1040 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1041 | if (!p) |
9fa3e853 FB |
1042 | return; |
1043 | if (p->code_bitmap) { | |
1044 | offset = start & ~TARGET_PAGE_MASK; | |
1045 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1046 | if (b & ((1 << len) - 1)) | |
1047 | goto do_invalidate; | |
1048 | } else { | |
1049 | do_invalidate: | |
d720b93d | 1050 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1051 | } |
1052 | } | |
1053 | ||
9fa3e853 | 1054 | #if !defined(CONFIG_SOFTMMU) |
c227f099 | 1055 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 1056 | unsigned long pc, void *puc) |
9fa3e853 | 1057 | { |
6b917547 | 1058 | TranslationBlock *tb; |
9fa3e853 | 1059 | PageDesc *p; |
6b917547 | 1060 | int n; |
d720b93d | 1061 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1062 | TranslationBlock *current_tb = NULL; |
d720b93d | 1063 | CPUState *env = cpu_single_env; |
6b917547 AL |
1064 | int current_tb_modified = 0; |
1065 | target_ulong current_pc = 0; | |
1066 | target_ulong current_cs_base = 0; | |
1067 | int current_flags = 0; | |
d720b93d | 1068 | #endif |
9fa3e853 FB |
1069 | |
1070 | addr &= TARGET_PAGE_MASK; | |
1071 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1072 | if (!p) |
9fa3e853 FB |
1073 | return; |
1074 | tb = p->first_tb; | |
d720b93d FB |
1075 | #ifdef TARGET_HAS_PRECISE_SMC |
1076 | if (tb && pc != 0) { | |
1077 | current_tb = tb_find_pc(pc); | |
1078 | } | |
1079 | #endif | |
9fa3e853 FB |
1080 | while (tb != NULL) { |
1081 | n = (long)tb & 3; | |
1082 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1083 | #ifdef TARGET_HAS_PRECISE_SMC |
1084 | if (current_tb == tb && | |
2e70f6ef | 1085 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1086 | /* If we are modifying the current TB, we must stop |
1087 | its execution. We could be more precise by checking | |
1088 | that the modification is after the current PC, but it | |
1089 | would require a specialized function to partially | |
1090 | restore the CPU state */ | |
3b46e624 | 1091 | |
d720b93d FB |
1092 | current_tb_modified = 1; |
1093 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1094 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1095 | ¤t_flags); | |
d720b93d FB |
1096 | } |
1097 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1098 | tb_phys_invalidate(tb, addr); |
1099 | tb = tb->page_next[n]; | |
1100 | } | |
fd6ce8f6 | 1101 | p->first_tb = NULL; |
d720b93d FB |
1102 | #ifdef TARGET_HAS_PRECISE_SMC |
1103 | if (current_tb_modified) { | |
1104 | /* we generate a block containing just the instruction | |
1105 | modifying the memory. It will ensure that it cannot modify | |
1106 | itself */ | |
ea1c1802 | 1107 | env->current_tb = NULL; |
2e70f6ef | 1108 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1109 | cpu_resume_from_signal(env, puc); |
1110 | } | |
1111 | #endif | |
fd6ce8f6 | 1112 | } |
9fa3e853 | 1113 | #endif |
fd6ce8f6 FB |
1114 | |
1115 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1116 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 1117 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
1118 | { |
1119 | PageDesc *p; | |
9fa3e853 FB |
1120 | TranslationBlock *last_first_tb; |
1121 | ||
1122 | tb->page_addr[n] = page_addr; | |
3a7d929e | 1123 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1124 | tb->page_next[n] = p->first_tb; |
1125 | last_first_tb = p->first_tb; | |
1126 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1127 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1128 | |
107db443 | 1129 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1130 | |
9fa3e853 | 1131 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1132 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1133 | target_ulong addr; |
1134 | PageDesc *p2; | |
9fa3e853 FB |
1135 | int prot; |
1136 | ||
fd6ce8f6 FB |
1137 | /* force the host page as non writable (writes will have a |
1138 | page fault + mprotect overhead) */ | |
53a5960a | 1139 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1140 | prot = 0; |
53a5960a PB |
1141 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1142 | addr += TARGET_PAGE_SIZE) { | |
1143 | ||
1144 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1145 | if (!p2) | |
1146 | continue; | |
1147 | prot |= p2->flags; | |
1148 | p2->flags &= ~PAGE_WRITE; | |
1149 | page_get_flags(addr); | |
1150 | } | |
5fafdf24 | 1151 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1152 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1153 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1154 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1155 | page_addr); |
fd6ce8f6 | 1156 | #endif |
fd6ce8f6 | 1157 | } |
9fa3e853 FB |
1158 | #else |
1159 | /* if some code is already present, then the pages are already | |
1160 | protected. So we handle the case where only the first TB is | |
1161 | allocated in a physical page */ | |
1162 | if (!last_first_tb) { | |
6a00d601 | 1163 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1164 | } |
1165 | #endif | |
d720b93d FB |
1166 | |
1167 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1168 | } |
1169 | ||
1170 | /* Allocate a new translation block. Flush the translation buffer if | |
1171 | too many translation blocks or too much generated code. */ | |
c27004ec | 1172 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1173 | { |
1174 | TranslationBlock *tb; | |
fd6ce8f6 | 1175 | |
26a5f13b FB |
1176 | if (nb_tbs >= code_gen_max_blocks || |
1177 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1178 | return NULL; |
fd6ce8f6 FB |
1179 | tb = &tbs[nb_tbs++]; |
1180 | tb->pc = pc; | |
b448f2f3 | 1181 | tb->cflags = 0; |
d4e8164f FB |
1182 | return tb; |
1183 | } | |
1184 | ||
2e70f6ef PB |
1185 | void tb_free(TranslationBlock *tb) |
1186 | { | |
bf20dc07 | 1187 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1188 | Ignore the hard cases and just back up if this TB happens to |
1189 | be the last one generated. */ | |
1190 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1191 | code_gen_ptr = tb->tc_ptr; | |
1192 | nb_tbs--; | |
1193 | } | |
1194 | } | |
1195 | ||
9fa3e853 FB |
1196 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1197 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 1198 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 1199 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 1200 | { |
9fa3e853 FB |
1201 | unsigned int h; |
1202 | TranslationBlock **ptb; | |
1203 | ||
c8a706fe PB |
1204 | /* Grab the mmap lock to stop another thread invalidating this TB |
1205 | before we are done. */ | |
1206 | mmap_lock(); | |
9fa3e853 FB |
1207 | /* add in the physical hash table */ |
1208 | h = tb_phys_hash_func(phys_pc); | |
1209 | ptb = &tb_phys_hash[h]; | |
1210 | tb->phys_hash_next = *ptb; | |
1211 | *ptb = tb; | |
fd6ce8f6 FB |
1212 | |
1213 | /* add in the page list */ | |
9fa3e853 FB |
1214 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1215 | if (phys_page2 != -1) | |
1216 | tb_alloc_page(tb, 1, phys_page2); | |
1217 | else | |
1218 | tb->page_addr[1] = -1; | |
9fa3e853 | 1219 | |
d4e8164f FB |
1220 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1221 | tb->jmp_next[0] = NULL; | |
1222 | tb->jmp_next[1] = NULL; | |
1223 | ||
1224 | /* init original jump addresses */ | |
1225 | if (tb->tb_next_offset[0] != 0xffff) | |
1226 | tb_reset_jump(tb, 0); | |
1227 | if (tb->tb_next_offset[1] != 0xffff) | |
1228 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1229 | |
1230 | #ifdef DEBUG_TB_CHECK | |
1231 | tb_page_check(); | |
1232 | #endif | |
c8a706fe | 1233 | mmap_unlock(); |
fd6ce8f6 FB |
1234 | } |
1235 | ||
9fa3e853 FB |
1236 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1237 | tb[1].tc_ptr. Return NULL if not found */ | |
1238 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1239 | { |
9fa3e853 FB |
1240 | int m_min, m_max, m; |
1241 | unsigned long v; | |
1242 | TranslationBlock *tb; | |
a513fe19 FB |
1243 | |
1244 | if (nb_tbs <= 0) | |
1245 | return NULL; | |
1246 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1247 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1248 | return NULL; | |
1249 | /* binary search (cf Knuth) */ | |
1250 | m_min = 0; | |
1251 | m_max = nb_tbs - 1; | |
1252 | while (m_min <= m_max) { | |
1253 | m = (m_min + m_max) >> 1; | |
1254 | tb = &tbs[m]; | |
1255 | v = (unsigned long)tb->tc_ptr; | |
1256 | if (v == tc_ptr) | |
1257 | return tb; | |
1258 | else if (tc_ptr < v) { | |
1259 | m_max = m - 1; | |
1260 | } else { | |
1261 | m_min = m + 1; | |
1262 | } | |
5fafdf24 | 1263 | } |
a513fe19 FB |
1264 | return &tbs[m_max]; |
1265 | } | |
7501267e | 1266 | |
ea041c0e FB |
1267 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1268 | ||
1269 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1270 | { | |
1271 | TranslationBlock *tb1, *tb_next, **ptb; | |
1272 | unsigned int n1; | |
1273 | ||
1274 | tb1 = tb->jmp_next[n]; | |
1275 | if (tb1 != NULL) { | |
1276 | /* find head of list */ | |
1277 | for(;;) { | |
1278 | n1 = (long)tb1 & 3; | |
1279 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1280 | if (n1 == 2) | |
1281 | break; | |
1282 | tb1 = tb1->jmp_next[n1]; | |
1283 | } | |
1284 | /* we are now sure now that tb jumps to tb1 */ | |
1285 | tb_next = tb1; | |
1286 | ||
1287 | /* remove tb from the jmp_first list */ | |
1288 | ptb = &tb_next->jmp_first; | |
1289 | for(;;) { | |
1290 | tb1 = *ptb; | |
1291 | n1 = (long)tb1 & 3; | |
1292 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1293 | if (n1 == n && tb1 == tb) | |
1294 | break; | |
1295 | ptb = &tb1->jmp_next[n1]; | |
1296 | } | |
1297 | *ptb = tb->jmp_next[n]; | |
1298 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1299 | |
ea041c0e FB |
1300 | /* suppress the jump to next tb in generated code */ |
1301 | tb_reset_jump(tb, n); | |
1302 | ||
0124311e | 1303 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1304 | tb_reset_jump_recursive(tb_next); |
1305 | } | |
1306 | } | |
1307 | ||
1308 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1309 | { | |
1310 | tb_reset_jump_recursive2(tb, 0); | |
1311 | tb_reset_jump_recursive2(tb, 1); | |
1312 | } | |
1313 | ||
1fddef4b | 1314 | #if defined(TARGET_HAS_ICE) |
d720b93d FB |
1315 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1316 | { | |
c227f099 | 1317 | target_phys_addr_t addr; |
9b3c35e0 | 1318 | target_ulong pd; |
c227f099 | 1319 | ram_addr_t ram_addr; |
c2f07f81 | 1320 | PhysPageDesc *p; |
d720b93d | 1321 | |
c2f07f81 PB |
1322 | addr = cpu_get_phys_page_debug(env, pc); |
1323 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1324 | if (!p) { | |
1325 | pd = IO_MEM_UNASSIGNED; | |
1326 | } else { | |
1327 | pd = p->phys_offset; | |
1328 | } | |
1329 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1330 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1331 | } |
c27004ec | 1332 | #endif |
d720b93d | 1333 | |
6658ffb8 | 1334 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1335 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1336 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1337 | { |
b4051334 | 1338 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1339 | CPUWatchpoint *wp; |
6658ffb8 | 1340 | |
b4051334 AL |
1341 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1342 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1343 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1344 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1345 | return -EINVAL; | |
1346 | } | |
a1d1bb31 | 1347 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1348 | |
1349 | wp->vaddr = addr; | |
b4051334 | 1350 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1351 | wp->flags = flags; |
1352 | ||
2dc9f411 | 1353 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1354 | if (flags & BP_GDB) |
72cf2d4f | 1355 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1356 | else |
72cf2d4f | 1357 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1358 | |
6658ffb8 | 1359 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1360 | |
1361 | if (watchpoint) | |
1362 | *watchpoint = wp; | |
1363 | return 0; | |
6658ffb8 PB |
1364 | } |
1365 | ||
a1d1bb31 AL |
1366 | /* Remove a specific watchpoint. */ |
1367 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1368 | int flags) | |
6658ffb8 | 1369 | { |
b4051334 | 1370 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1371 | CPUWatchpoint *wp; |
6658ffb8 | 1372 | |
72cf2d4f | 1373 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1374 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1375 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1376 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1377 | return 0; |
1378 | } | |
1379 | } | |
a1d1bb31 | 1380 | return -ENOENT; |
6658ffb8 PB |
1381 | } |
1382 | ||
a1d1bb31 AL |
1383 | /* Remove a specific watchpoint by reference. */ |
1384 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1385 | { | |
72cf2d4f | 1386 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1387 | |
a1d1bb31 AL |
1388 | tlb_flush_page(env, watchpoint->vaddr); |
1389 | ||
1390 | qemu_free(watchpoint); | |
1391 | } | |
1392 | ||
1393 | /* Remove all matching watchpoints. */ | |
1394 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1395 | { | |
c0ce998e | 1396 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1397 | |
72cf2d4f | 1398 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1399 | if (wp->flags & mask) |
1400 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1401 | } |
7d03f82f EI |
1402 | } |
1403 | ||
a1d1bb31 AL |
1404 | /* Add a breakpoint. */ |
1405 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1406 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1407 | { |
1fddef4b | 1408 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1409 | CPUBreakpoint *bp; |
3b46e624 | 1410 | |
a1d1bb31 | 1411 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1412 | |
a1d1bb31 AL |
1413 | bp->pc = pc; |
1414 | bp->flags = flags; | |
1415 | ||
2dc9f411 | 1416 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1417 | if (flags & BP_GDB) |
72cf2d4f | 1418 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1419 | else |
72cf2d4f | 1420 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1421 | |
d720b93d | 1422 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1423 | |
1424 | if (breakpoint) | |
1425 | *breakpoint = bp; | |
4c3a88a2 FB |
1426 | return 0; |
1427 | #else | |
a1d1bb31 | 1428 | return -ENOSYS; |
4c3a88a2 FB |
1429 | #endif |
1430 | } | |
1431 | ||
a1d1bb31 AL |
1432 | /* Remove a specific breakpoint. */ |
1433 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1434 | { | |
7d03f82f | 1435 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1436 | CPUBreakpoint *bp; |
1437 | ||
72cf2d4f | 1438 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1439 | if (bp->pc == pc && bp->flags == flags) { |
1440 | cpu_breakpoint_remove_by_ref(env, bp); | |
1441 | return 0; | |
1442 | } | |
7d03f82f | 1443 | } |
a1d1bb31 AL |
1444 | return -ENOENT; |
1445 | #else | |
1446 | return -ENOSYS; | |
7d03f82f EI |
1447 | #endif |
1448 | } | |
1449 | ||
a1d1bb31 AL |
1450 | /* Remove a specific breakpoint by reference. */ |
1451 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1452 | { |
1fddef4b | 1453 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1454 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1455 | |
a1d1bb31 AL |
1456 | breakpoint_invalidate(env, breakpoint->pc); |
1457 | ||
1458 | qemu_free(breakpoint); | |
1459 | #endif | |
1460 | } | |
1461 | ||
1462 | /* Remove all matching breakpoints. */ | |
1463 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1464 | { | |
1465 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1466 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1467 | |
72cf2d4f | 1468 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1469 | if (bp->flags & mask) |
1470 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1471 | } |
4c3a88a2 FB |
1472 | #endif |
1473 | } | |
1474 | ||
c33a346e FB |
1475 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1476 | CPU loop after each instruction */ | |
1477 | void cpu_single_step(CPUState *env, int enabled) | |
1478 | { | |
1fddef4b | 1479 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1480 | if (env->singlestep_enabled != enabled) { |
1481 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1482 | if (kvm_enabled()) |
1483 | kvm_update_guest_debug(env, 0); | |
1484 | else { | |
ccbb4d44 | 1485 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1486 | /* XXX: only flush what is necessary */ |
1487 | tb_flush(env); | |
1488 | } | |
c33a346e FB |
1489 | } |
1490 | #endif | |
1491 | } | |
1492 | ||
34865134 FB |
1493 | /* enable or disable low levels log */ |
1494 | void cpu_set_log(int log_flags) | |
1495 | { | |
1496 | loglevel = log_flags; | |
1497 | if (loglevel && !logfile) { | |
11fcfab4 | 1498 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1499 | if (!logfile) { |
1500 | perror(logfilename); | |
1501 | _exit(1); | |
1502 | } | |
9fa3e853 FB |
1503 | #if !defined(CONFIG_SOFTMMU) |
1504 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1505 | { | |
b55266b5 | 1506 | static char logfile_buf[4096]; |
9fa3e853 FB |
1507 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1508 | } | |
bf65f53f FN |
1509 | #elif !defined(_WIN32) |
1510 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1511 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1512 | #endif |
e735b91c PB |
1513 | log_append = 1; |
1514 | } | |
1515 | if (!loglevel && logfile) { | |
1516 | fclose(logfile); | |
1517 | logfile = NULL; | |
34865134 FB |
1518 | } |
1519 | } | |
1520 | ||
1521 | void cpu_set_log_filename(const char *filename) | |
1522 | { | |
1523 | logfilename = strdup(filename); | |
e735b91c PB |
1524 | if (logfile) { |
1525 | fclose(logfile); | |
1526 | logfile = NULL; | |
1527 | } | |
1528 | cpu_set_log(loglevel); | |
34865134 | 1529 | } |
c33a346e | 1530 | |
3098dba0 | 1531 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1532 | { |
2f7bb878 | 1533 | #if defined(CONFIG_USE_NPTL) |
3098dba0 AJ |
1534 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1535 | problem and hope the cpu will stop of its own accord. For userspace | |
1536 | emulation this often isn't actually as bad as it sounds. Often | |
1537 | signals are used primarily to interrupt blocking syscalls. */ | |
1538 | #else | |
ea041c0e | 1539 | TranslationBlock *tb; |
c227f099 | 1540 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1541 | |
3098dba0 AJ |
1542 | tb = env->current_tb; |
1543 | /* if the cpu is currently executing code, we must unlink it and | |
1544 | all the potentially executing TB */ | |
1545 | if (tb && !testandset(&interrupt_lock)) { | |
1546 | env->current_tb = NULL; | |
1547 | tb_reset_jump_recursive(tb); | |
1548 | resetlock(&interrupt_lock); | |
be214e6c | 1549 | } |
3098dba0 AJ |
1550 | #endif |
1551 | } | |
1552 | ||
1553 | /* mask must never be zero, except for A20 change call */ | |
1554 | void cpu_interrupt(CPUState *env, int mask) | |
1555 | { | |
1556 | int old_mask; | |
be214e6c | 1557 | |
2e70f6ef | 1558 | old_mask = env->interrupt_request; |
68a79315 | 1559 | env->interrupt_request |= mask; |
3098dba0 | 1560 | |
8edac960 AL |
1561 | #ifndef CONFIG_USER_ONLY |
1562 | /* | |
1563 | * If called from iothread context, wake the target cpu in | |
1564 | * case its halted. | |
1565 | */ | |
1566 | if (!qemu_cpu_self(env)) { | |
1567 | qemu_cpu_kick(env); | |
1568 | return; | |
1569 | } | |
1570 | #endif | |
1571 | ||
2e70f6ef | 1572 | if (use_icount) { |
266910c4 | 1573 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1574 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1575 | if (!can_do_io(env) |
be214e6c | 1576 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1577 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1578 | } | |
1579 | #endif | |
1580 | } else { | |
3098dba0 | 1581 | cpu_unlink_tb(env); |
ea041c0e FB |
1582 | } |
1583 | } | |
1584 | ||
b54ad049 FB |
1585 | void cpu_reset_interrupt(CPUState *env, int mask) |
1586 | { | |
1587 | env->interrupt_request &= ~mask; | |
1588 | } | |
1589 | ||
3098dba0 AJ |
1590 | void cpu_exit(CPUState *env) |
1591 | { | |
1592 | env->exit_request = 1; | |
1593 | cpu_unlink_tb(env); | |
1594 | } | |
1595 | ||
c7cd6a37 | 1596 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1597 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1598 | "show generated host assembly code for each compiled TB" }, |
1599 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1600 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1601 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1602 | "show micro ops for each compiled TB" }, |
f193c797 | 1603 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1604 | "show micro ops " |
1605 | #ifdef TARGET_I386 | |
1606 | "before eflags optimization and " | |
f193c797 | 1607 | #endif |
e01a1157 | 1608 | "after liveness analysis" }, |
f193c797 FB |
1609 | { CPU_LOG_INT, "int", |
1610 | "show interrupts/exceptions in short format" }, | |
1611 | { CPU_LOG_EXEC, "exec", | |
1612 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1613 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1614 | "show CPU state before block translation" }, |
f193c797 FB |
1615 | #ifdef TARGET_I386 |
1616 | { CPU_LOG_PCALL, "pcall", | |
1617 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1618 | { CPU_LOG_RESET, "cpu_reset", |
1619 | "show CPU state before CPU resets" }, | |
f193c797 | 1620 | #endif |
8e3a9fd2 | 1621 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1622 | { CPU_LOG_IOPORT, "ioport", |
1623 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1624 | #endif |
f193c797 FB |
1625 | { 0, NULL, NULL }, |
1626 | }; | |
1627 | ||
1628 | static int cmp1(const char *s1, int n, const char *s2) | |
1629 | { | |
1630 | if (strlen(s2) != n) | |
1631 | return 0; | |
1632 | return memcmp(s1, s2, n) == 0; | |
1633 | } | |
3b46e624 | 1634 | |
f193c797 FB |
1635 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1636 | int cpu_str_to_log_mask(const char *str) | |
1637 | { | |
c7cd6a37 | 1638 | const CPULogItem *item; |
f193c797 FB |
1639 | int mask; |
1640 | const char *p, *p1; | |
1641 | ||
1642 | p = str; | |
1643 | mask = 0; | |
1644 | for(;;) { | |
1645 | p1 = strchr(p, ','); | |
1646 | if (!p1) | |
1647 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1648 | if(cmp1(p,p1-p,"all")) { |
1649 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1650 | mask |= item->mask; | |
1651 | } | |
1652 | } else { | |
f193c797 FB |
1653 | for(item = cpu_log_items; item->mask != 0; item++) { |
1654 | if (cmp1(p, p1 - p, item->name)) | |
1655 | goto found; | |
1656 | } | |
1657 | return 0; | |
8e3a9fd2 | 1658 | } |
f193c797 FB |
1659 | found: |
1660 | mask |= item->mask; | |
1661 | if (*p1 != ',') | |
1662 | break; | |
1663 | p = p1 + 1; | |
1664 | } | |
1665 | return mask; | |
1666 | } | |
ea041c0e | 1667 | |
7501267e FB |
1668 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1669 | { | |
1670 | va_list ap; | |
493ae1f0 | 1671 | va_list ap2; |
7501267e FB |
1672 | |
1673 | va_start(ap, fmt); | |
493ae1f0 | 1674 | va_copy(ap2, ap); |
7501267e FB |
1675 | fprintf(stderr, "qemu: fatal: "); |
1676 | vfprintf(stderr, fmt, ap); | |
1677 | fprintf(stderr, "\n"); | |
1678 | #ifdef TARGET_I386 | |
7fe48483 FB |
1679 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1680 | #else | |
1681 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1682 | #endif |
93fcfe39 AL |
1683 | if (qemu_log_enabled()) { |
1684 | qemu_log("qemu: fatal: "); | |
1685 | qemu_log_vprintf(fmt, ap2); | |
1686 | qemu_log("\n"); | |
f9373291 | 1687 | #ifdef TARGET_I386 |
93fcfe39 | 1688 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1689 | #else |
93fcfe39 | 1690 | log_cpu_state(env, 0); |
f9373291 | 1691 | #endif |
31b1a7b4 | 1692 | qemu_log_flush(); |
93fcfe39 | 1693 | qemu_log_close(); |
924edcae | 1694 | } |
493ae1f0 | 1695 | va_end(ap2); |
f9373291 | 1696 | va_end(ap); |
7501267e FB |
1697 | abort(); |
1698 | } | |
1699 | ||
c5be9f08 TS |
1700 | CPUState *cpu_copy(CPUState *env) |
1701 | { | |
01ba9816 | 1702 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1703 | CPUState *next_cpu = new_env->next_cpu; |
1704 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1705 | #if defined(TARGET_HAS_ICE) |
1706 | CPUBreakpoint *bp; | |
1707 | CPUWatchpoint *wp; | |
1708 | #endif | |
1709 | ||
c5be9f08 | 1710 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1711 | |
1712 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1713 | new_env->next_cpu = next_cpu; |
1714 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1715 | |
1716 | /* Clone all break/watchpoints. | |
1717 | Note: Once we support ptrace with hw-debug register access, make sure | |
1718 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1719 | QTAILQ_INIT(&env->breakpoints); |
1720 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1721 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1722 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1723 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1724 | } | |
72cf2d4f | 1725 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1726 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1727 | wp->flags, NULL); | |
1728 | } | |
1729 | #endif | |
1730 | ||
c5be9f08 TS |
1731 | return new_env; |
1732 | } | |
1733 | ||
0124311e FB |
1734 | #if !defined(CONFIG_USER_ONLY) |
1735 | ||
5c751e99 EI |
1736 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1737 | { | |
1738 | unsigned int i; | |
1739 | ||
1740 | /* Discard jump cache entries for any tb which might potentially | |
1741 | overlap the flushed page. */ | |
1742 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1743 | memset (&env->tb_jmp_cache[i], 0, | |
1744 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1745 | ||
1746 | i = tb_jmp_cache_hash_page(addr); | |
1747 | memset (&env->tb_jmp_cache[i], 0, | |
1748 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1749 | } | |
1750 | ||
08738984 IK |
1751 | static CPUTLBEntry s_cputlb_empty_entry = { |
1752 | .addr_read = -1, | |
1753 | .addr_write = -1, | |
1754 | .addr_code = -1, | |
1755 | .addend = -1, | |
1756 | }; | |
1757 | ||
ee8b7021 FB |
1758 | /* NOTE: if flush_global is true, also flush global entries (not |
1759 | implemented yet) */ | |
1760 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1761 | { |
33417e70 | 1762 | int i; |
0124311e | 1763 | |
9fa3e853 FB |
1764 | #if defined(DEBUG_TLB) |
1765 | printf("tlb_flush:\n"); | |
1766 | #endif | |
0124311e FB |
1767 | /* must reset current TB so that interrupts cannot modify the |
1768 | links while we are modifying them */ | |
1769 | env->current_tb = NULL; | |
1770 | ||
33417e70 | 1771 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1772 | int mmu_idx; |
1773 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1774 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1775 | } |
33417e70 | 1776 | } |
9fa3e853 | 1777 | |
8a40a180 | 1778 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1779 | |
e3db7226 | 1780 | tlb_flush_count++; |
33417e70 FB |
1781 | } |
1782 | ||
274da6b2 | 1783 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1784 | { |
5fafdf24 | 1785 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1786 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1787 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1788 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1789 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1790 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1791 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1792 | } |
61382a50 FB |
1793 | } |
1794 | ||
2e12669a | 1795 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1796 | { |
8a40a180 | 1797 | int i; |
cfde4bd9 | 1798 | int mmu_idx; |
0124311e | 1799 | |
9fa3e853 | 1800 | #if defined(DEBUG_TLB) |
108c49b8 | 1801 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1802 | #endif |
0124311e FB |
1803 | /* must reset current TB so that interrupts cannot modify the |
1804 | links while we are modifying them */ | |
1805 | env->current_tb = NULL; | |
61382a50 FB |
1806 | |
1807 | addr &= TARGET_PAGE_MASK; | |
1808 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
1809 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1810 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 1811 | |
5c751e99 | 1812 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
1813 | } |
1814 | ||
9fa3e853 FB |
1815 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1816 | can be detected */ | |
c227f099 | 1817 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1818 | { |
5fafdf24 | 1819 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1820 | ram_addr + TARGET_PAGE_SIZE, |
1821 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1822 | } |
1823 | ||
9fa3e853 | 1824 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1825 | tested for self modifying code */ |
c227f099 | 1826 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1827 | target_ulong vaddr) |
9fa3e853 | 1828 | { |
3a7d929e | 1829 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1830 | } |
1831 | ||
5fafdf24 | 1832 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1833 | unsigned long start, unsigned long length) |
1834 | { | |
1835 | unsigned long addr; | |
84b7b8e7 FB |
1836 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1837 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1838 | if ((addr - start) < length) { |
0f459d16 | 1839 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
1840 | } |
1841 | } | |
1842 | } | |
1843 | ||
5579c7f3 | 1844 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 1845 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1846 | int dirty_flags) |
1ccde1cb FB |
1847 | { |
1848 | CPUState *env; | |
4f2ac237 | 1849 | unsigned long length, start1; |
0a962c02 FB |
1850 | int i, mask, len; |
1851 | uint8_t *p; | |
1ccde1cb FB |
1852 | |
1853 | start &= TARGET_PAGE_MASK; | |
1854 | end = TARGET_PAGE_ALIGN(end); | |
1855 | ||
1856 | length = end - start; | |
1857 | if (length == 0) | |
1858 | return; | |
0a962c02 | 1859 | len = length >> TARGET_PAGE_BITS; |
f23db169 FB |
1860 | mask = ~dirty_flags; |
1861 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1862 | for(i = 0; i < len; i++) | |
1863 | p[i] &= mask; | |
1864 | ||
1ccde1cb FB |
1865 | /* we modify the TLB cache so that the dirty bit will be set again |
1866 | when accessing the range */ | |
5579c7f3 PB |
1867 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
1868 | /* Chek that we don't span multiple blocks - this breaks the | |
1869 | address comparisons below. */ | |
1870 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
1871 | != (end - 1) - start) { | |
1872 | abort(); | |
1873 | } | |
1874 | ||
6a00d601 | 1875 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
1876 | int mmu_idx; |
1877 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
1878 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1879 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
1880 | start1, length); | |
1881 | } | |
6a00d601 | 1882 | } |
1ccde1cb FB |
1883 | } |
1884 | ||
74576198 AL |
1885 | int cpu_physical_memory_set_dirty_tracking(int enable) |
1886 | { | |
1887 | in_migration = enable; | |
b0a46a33 JK |
1888 | if (kvm_enabled()) { |
1889 | return kvm_set_migration_log(enable); | |
1890 | } | |
74576198 AL |
1891 | return 0; |
1892 | } | |
1893 | ||
1894 | int cpu_physical_memory_get_dirty_tracking(void) | |
1895 | { | |
1896 | return in_migration; | |
1897 | } | |
1898 | ||
c227f099 AL |
1899 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
1900 | target_phys_addr_t end_addr) | |
2bec46dc | 1901 | { |
151f7749 JK |
1902 | int ret = 0; |
1903 | ||
2bec46dc | 1904 | if (kvm_enabled()) |
151f7749 JK |
1905 | ret = kvm_physical_sync_dirty_bitmap(start_addr, end_addr); |
1906 | return ret; | |
2bec46dc AL |
1907 | } |
1908 | ||
3a7d929e FB |
1909 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
1910 | { | |
c227f099 | 1911 | ram_addr_t ram_addr; |
5579c7f3 | 1912 | void *p; |
3a7d929e | 1913 | |
84b7b8e7 | 1914 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
1915 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
1916 | + tlb_entry->addend); | |
1917 | ram_addr = qemu_ram_addr_from_host(p); | |
3a7d929e | 1918 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 1919 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
1920 | } |
1921 | } | |
1922 | } | |
1923 | ||
1924 | /* update the TLB according to the current state of the dirty bits */ | |
1925 | void cpu_tlb_update_dirty(CPUState *env) | |
1926 | { | |
1927 | int i; | |
cfde4bd9 IY |
1928 | int mmu_idx; |
1929 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
1930 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
1931 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
1932 | } | |
3a7d929e FB |
1933 | } |
1934 | ||
0f459d16 | 1935 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 1936 | { |
0f459d16 PB |
1937 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
1938 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
1939 | } |
1940 | ||
0f459d16 PB |
1941 | /* update the TLB corresponding to virtual page vaddr |
1942 | so that it is no longer dirty */ | |
1943 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 1944 | { |
1ccde1cb | 1945 | int i; |
cfde4bd9 | 1946 | int mmu_idx; |
1ccde1cb | 1947 | |
0f459d16 | 1948 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 1949 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
1950 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1951 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
1952 | } |
1953 | ||
59817ccb FB |
1954 | /* add a new TLB entry. At most one entry for a given virtual address |
1955 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
1956 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
1957 | conflicting with the host address space). */ | |
5fafdf24 | 1958 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 1959 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 1960 | int mmu_idx, int is_softmmu) |
9fa3e853 | 1961 | { |
92e873b9 | 1962 | PhysPageDesc *p; |
4f2ac237 | 1963 | unsigned long pd; |
9fa3e853 | 1964 | unsigned int index; |
4f2ac237 | 1965 | target_ulong address; |
0f459d16 | 1966 | target_ulong code_address; |
c227f099 | 1967 | target_phys_addr_t addend; |
9fa3e853 | 1968 | int ret; |
84b7b8e7 | 1969 | CPUTLBEntry *te; |
a1d1bb31 | 1970 | CPUWatchpoint *wp; |
c227f099 | 1971 | target_phys_addr_t iotlb; |
9fa3e853 | 1972 | |
92e873b9 | 1973 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
1974 | if (!p) { |
1975 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
1976 | } else { |
1977 | pd = p->phys_offset; | |
9fa3e853 FB |
1978 | } |
1979 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
1980 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
1981 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
1982 | #endif |
1983 | ||
1984 | ret = 0; | |
0f459d16 PB |
1985 | address = vaddr; |
1986 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
1987 | /* IO memory case (romd handled later) */ | |
1988 | address |= TLB_MMIO; | |
1989 | } | |
5579c7f3 | 1990 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
1991 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
1992 | /* Normal RAM. */ | |
1993 | iotlb = pd & TARGET_PAGE_MASK; | |
1994 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
1995 | iotlb |= IO_MEM_NOTDIRTY; | |
1996 | else | |
1997 | iotlb |= IO_MEM_ROM; | |
1998 | } else { | |
ccbb4d44 | 1999 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2000 | It would be nice to pass an offset from the base address |
2001 | of that region. This would avoid having to special case RAM, | |
2002 | and avoid full address decoding in every device. | |
2003 | We can't use the high bits of pd for this because | |
2004 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2005 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2006 | if (p) { | |
8da3ff18 PB |
2007 | iotlb += p->region_offset; |
2008 | } else { | |
2009 | iotlb += paddr; | |
2010 | } | |
0f459d16 PB |
2011 | } |
2012 | ||
2013 | code_address = address; | |
2014 | /* Make accesses to pages with watchpoints go via the | |
2015 | watchpoint trap routines. */ | |
72cf2d4f | 2016 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2017 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
0f459d16 PB |
2018 | iotlb = io_mem_watch + paddr; |
2019 | /* TODO: The memory case can be optimized by not trapping | |
2020 | reads of pages with a write breakpoint. */ | |
2021 | address |= TLB_MMIO; | |
6658ffb8 | 2022 | } |
0f459d16 | 2023 | } |
d79acba4 | 2024 | |
0f459d16 PB |
2025 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2026 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2027 | te = &env->tlb_table[mmu_idx][index]; | |
2028 | te->addend = addend - vaddr; | |
2029 | if (prot & PAGE_READ) { | |
2030 | te->addr_read = address; | |
2031 | } else { | |
2032 | te->addr_read = -1; | |
2033 | } | |
5c751e99 | 2034 | |
0f459d16 PB |
2035 | if (prot & PAGE_EXEC) { |
2036 | te->addr_code = code_address; | |
2037 | } else { | |
2038 | te->addr_code = -1; | |
2039 | } | |
2040 | if (prot & PAGE_WRITE) { | |
2041 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2042 | (pd & IO_MEM_ROMD)) { | |
2043 | /* Write access calls the I/O callback. */ | |
2044 | te->addr_write = address | TLB_MMIO; | |
2045 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2046 | !cpu_physical_memory_is_dirty(pd)) { | |
2047 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2048 | } else { |
0f459d16 | 2049 | te->addr_write = address; |
9fa3e853 | 2050 | } |
0f459d16 PB |
2051 | } else { |
2052 | te->addr_write = -1; | |
9fa3e853 | 2053 | } |
9fa3e853 FB |
2054 | return ret; |
2055 | } | |
2056 | ||
0124311e FB |
2057 | #else |
2058 | ||
ee8b7021 | 2059 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2060 | { |
2061 | } | |
2062 | ||
2e12669a | 2063 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2064 | { |
2065 | } | |
2066 | ||
5fafdf24 | 2067 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 2068 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 2069 | int mmu_idx, int is_softmmu) |
9fa3e853 FB |
2070 | { |
2071 | return 0; | |
2072 | } | |
0124311e | 2073 | |
edf8e2af MW |
2074 | /* |
2075 | * Walks guest process memory "regions" one by one | |
2076 | * and calls callback function 'fn' for each region. | |
2077 | */ | |
2078 | int walk_memory_regions(void *priv, | |
2079 | int (*fn)(void *, unsigned long, unsigned long, unsigned long)) | |
33417e70 | 2080 | { |
9fa3e853 | 2081 | unsigned long start, end; |
edf8e2af | 2082 | PageDesc *p = NULL; |
9fa3e853 | 2083 | int i, j, prot, prot1; |
edf8e2af | 2084 | int rc = 0; |
33417e70 | 2085 | |
edf8e2af | 2086 | start = end = -1; |
9fa3e853 | 2087 | prot = 0; |
edf8e2af MW |
2088 | |
2089 | for (i = 0; i <= L1_SIZE; i++) { | |
2090 | p = (i < L1_SIZE) ? l1_map[i] : NULL; | |
2091 | for (j = 0; j < L2_SIZE; j++) { | |
2092 | prot1 = (p == NULL) ? 0 : p[j].flags; | |
2093 | /* | |
2094 | * "region" is one continuous chunk of memory | |
2095 | * that has same protection flags set. | |
2096 | */ | |
9fa3e853 FB |
2097 | if (prot1 != prot) { |
2098 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); | |
2099 | if (start != -1) { | |
edf8e2af MW |
2100 | rc = (*fn)(priv, start, end, prot); |
2101 | /* callback can stop iteration by returning != 0 */ | |
2102 | if (rc != 0) | |
2103 | return (rc); | |
9fa3e853 FB |
2104 | } |
2105 | if (prot1 != 0) | |
2106 | start = end; | |
2107 | else | |
2108 | start = -1; | |
2109 | prot = prot1; | |
2110 | } | |
edf8e2af | 2111 | if (p == NULL) |
9fa3e853 FB |
2112 | break; |
2113 | } | |
33417e70 | 2114 | } |
edf8e2af MW |
2115 | return (rc); |
2116 | } | |
2117 | ||
2118 | static int dump_region(void *priv, unsigned long start, | |
2119 | unsigned long end, unsigned long prot) | |
2120 | { | |
2121 | FILE *f = (FILE *)priv; | |
2122 | ||
2123 | (void) fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
2124 | start, end, end - start, | |
2125 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2126 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2127 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2128 | ||
2129 | return (0); | |
2130 | } | |
2131 | ||
2132 | /* dump memory mappings */ | |
2133 | void page_dump(FILE *f) | |
2134 | { | |
2135 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2136 | "start", "end", "size", "prot"); | |
2137 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2138 | } |
2139 | ||
53a5960a | 2140 | int page_get_flags(target_ulong address) |
33417e70 | 2141 | { |
9fa3e853 FB |
2142 | PageDesc *p; |
2143 | ||
2144 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2145 | if (!p) |
9fa3e853 FB |
2146 | return 0; |
2147 | return p->flags; | |
2148 | } | |
2149 | ||
2150 | /* modify the flags of a page and invalidate the code if | |
ccbb4d44 | 2151 | necessary. The flag PAGE_WRITE_ORG is positioned automatically |
9fa3e853 | 2152 | depending on PAGE_WRITE */ |
53a5960a | 2153 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 FB |
2154 | { |
2155 | PageDesc *p; | |
53a5960a | 2156 | target_ulong addr; |
9fa3e853 | 2157 | |
c8a706fe | 2158 | /* mmap_lock should already be held. */ |
9fa3e853 FB |
2159 | start = start & TARGET_PAGE_MASK; |
2160 | end = TARGET_PAGE_ALIGN(end); | |
2161 | if (flags & PAGE_WRITE) | |
2162 | flags |= PAGE_WRITE_ORG; | |
9fa3e853 FB |
2163 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2164 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); | |
17e2377a PB |
2165 | /* We may be called for host regions that are outside guest |
2166 | address space. */ | |
2167 | if (!p) | |
2168 | return; | |
9fa3e853 FB |
2169 | /* if the write protection is set, then we invalidate the code |
2170 | inside */ | |
5fafdf24 | 2171 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2172 | (flags & PAGE_WRITE) && |
2173 | p->first_tb) { | |
d720b93d | 2174 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2175 | } |
2176 | p->flags = flags; | |
2177 | } | |
33417e70 FB |
2178 | } |
2179 | ||
3d97b40b TS |
2180 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2181 | { | |
2182 | PageDesc *p; | |
2183 | target_ulong end; | |
2184 | target_ulong addr; | |
2185 | ||
55f280c9 AZ |
2186 | if (start + len < start) |
2187 | /* we've wrapped around */ | |
2188 | return -1; | |
2189 | ||
3d97b40b TS |
2190 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2191 | start = start & TARGET_PAGE_MASK; | |
2192 | ||
3d97b40b TS |
2193 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
2194 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2195 | if( !p ) | |
2196 | return -1; | |
2197 | if( !(p->flags & PAGE_VALID) ) | |
2198 | return -1; | |
2199 | ||
dae3270c | 2200 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2201 | return -1; |
dae3270c FB |
2202 | if (flags & PAGE_WRITE) { |
2203 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2204 | return -1; | |
2205 | /* unprotect the page if it was put read-only because it | |
2206 | contains translated code */ | |
2207 | if (!(p->flags & PAGE_WRITE)) { | |
2208 | if (!page_unprotect(addr, 0, NULL)) | |
2209 | return -1; | |
2210 | } | |
2211 | return 0; | |
2212 | } | |
3d97b40b TS |
2213 | } |
2214 | return 0; | |
2215 | } | |
2216 | ||
9fa3e853 | 2217 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2218 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2219 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
2220 | { |
2221 | unsigned int page_index, prot, pindex; | |
2222 | PageDesc *p, *p1; | |
53a5960a | 2223 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2224 | |
c8a706fe PB |
2225 | /* Technically this isn't safe inside a signal handler. However we |
2226 | know this only ever happens in a synchronous SEGV handler, so in | |
2227 | practice it seems to be ok. */ | |
2228 | mmap_lock(); | |
2229 | ||
83fb7adf | 2230 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
2231 | page_index = host_start >> TARGET_PAGE_BITS; |
2232 | p1 = page_find(page_index); | |
c8a706fe PB |
2233 | if (!p1) { |
2234 | mmap_unlock(); | |
9fa3e853 | 2235 | return 0; |
c8a706fe | 2236 | } |
83fb7adf | 2237 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
2238 | p = p1; |
2239 | prot = 0; | |
2240 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2241 | prot |= p->flags; | |
2242 | p++; | |
2243 | } | |
2244 | /* if the page was really writable, then we change its | |
2245 | protection back to writable */ | |
2246 | if (prot & PAGE_WRITE_ORG) { | |
2247 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
2248 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 2249 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
2250 | (prot & PAGE_BITS) | PAGE_WRITE); |
2251 | p1[pindex].flags |= PAGE_WRITE; | |
2252 | /* and since the content will be modified, we must invalidate | |
2253 | the corresponding translated code. */ | |
d720b93d | 2254 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
2255 | #ifdef DEBUG_TB_CHECK |
2256 | tb_invalidate_check(address); | |
2257 | #endif | |
c8a706fe | 2258 | mmap_unlock(); |
9fa3e853 FB |
2259 | return 1; |
2260 | } | |
2261 | } | |
c8a706fe | 2262 | mmap_unlock(); |
9fa3e853 FB |
2263 | return 0; |
2264 | } | |
2265 | ||
6a00d601 FB |
2266 | static inline void tlb_set_dirty(CPUState *env, |
2267 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2268 | { |
2269 | } | |
9fa3e853 FB |
2270 | #endif /* defined(CONFIG_USER_ONLY) */ |
2271 | ||
e2eef170 | 2272 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2273 | |
c227f099 AL |
2274 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2275 | ram_addr_t memory, ram_addr_t region_offset); | |
2276 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2277 | ram_addr_t orig_memory, ram_addr_t region_offset); | |
db7b5426 BS |
2278 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2279 | need_subpage) \ | |
2280 | do { \ | |
2281 | if (addr > start_addr) \ | |
2282 | start_addr2 = 0; \ | |
2283 | else { \ | |
2284 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2285 | if (start_addr2 > 0) \ | |
2286 | need_subpage = 1; \ | |
2287 | } \ | |
2288 | \ | |
49e9fba2 | 2289 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2290 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2291 | else { \ | |
2292 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2293 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2294 | need_subpage = 1; \ | |
2295 | } \ | |
2296 | } while (0) | |
2297 | ||
8f2498f9 MT |
2298 | /* register physical memory. |
2299 | For RAM, 'size' must be a multiple of the target page size. | |
2300 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2301 | io memory page. The address used when calling the IO function is |
2302 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2303 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2304 | before calculating this offset. This should not be a problem unless |
2305 | the low bits of start_addr and region_offset differ. */ | |
c227f099 AL |
2306 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
2307 | ram_addr_t size, | |
2308 | ram_addr_t phys_offset, | |
2309 | ram_addr_t region_offset) | |
33417e70 | 2310 | { |
c227f099 | 2311 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2312 | PhysPageDesc *p; |
9d42037b | 2313 | CPUState *env; |
c227f099 | 2314 | ram_addr_t orig_size = size; |
db7b5426 | 2315 | void *subpage; |
33417e70 | 2316 | |
7ba1e619 AL |
2317 | if (kvm_enabled()) |
2318 | kvm_set_phys_mem(start_addr, size, phys_offset); | |
2319 | ||
67c4d23c PB |
2320 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2321 | region_offset = start_addr; | |
2322 | } | |
8da3ff18 | 2323 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2324 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2325 | end_addr = start_addr + (target_phys_addr_t)size; |
49e9fba2 | 2326 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
db7b5426 BS |
2327 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2328 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2329 | ram_addr_t orig_memory = p->phys_offset; |
2330 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2331 | int need_subpage = 0; |
2332 | ||
2333 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2334 | need_subpage); | |
4254fab8 | 2335 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2336 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2337 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2338 | &p->phys_offset, orig_memory, |
2339 | p->region_offset); | |
db7b5426 BS |
2340 | } else { |
2341 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2342 | >> IO_MEM_SHIFT]; | |
2343 | } | |
8da3ff18 PB |
2344 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2345 | region_offset); | |
2346 | p->region_offset = 0; | |
db7b5426 BS |
2347 | } else { |
2348 | p->phys_offset = phys_offset; | |
2349 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2350 | (phys_offset & IO_MEM_ROMD)) | |
2351 | phys_offset += TARGET_PAGE_SIZE; | |
2352 | } | |
2353 | } else { | |
2354 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2355 | p->phys_offset = phys_offset; | |
8da3ff18 | 2356 | p->region_offset = region_offset; |
db7b5426 | 2357 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2358 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2359 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2360 | } else { |
c227f099 | 2361 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2362 | int need_subpage = 0; |
2363 | ||
2364 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2365 | end_addr2, need_subpage); | |
2366 | ||
4254fab8 | 2367 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 | 2368 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2369 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2370 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2371 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2372 | phys_offset, region_offset); |
2373 | p->region_offset = 0; | |
db7b5426 BS |
2374 | } |
2375 | } | |
2376 | } | |
8da3ff18 | 2377 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2378 | } |
3b46e624 | 2379 | |
9d42037b FB |
2380 | /* since each CPU stores ram addresses in its TLB cache, we must |
2381 | reset the modified entries */ | |
2382 | /* XXX: slow ! */ | |
2383 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2384 | tlb_flush(env, 1); | |
2385 | } | |
33417e70 FB |
2386 | } |
2387 | ||
ba863458 | 2388 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2389 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2390 | { |
2391 | PhysPageDesc *p; | |
2392 | ||
2393 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2394 | if (!p) | |
2395 | return IO_MEM_UNASSIGNED; | |
2396 | return p->phys_offset; | |
2397 | } | |
2398 | ||
c227f099 | 2399 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2400 | { |
2401 | if (kvm_enabled()) | |
2402 | kvm_coalesce_mmio_region(addr, size); | |
2403 | } | |
2404 | ||
c227f099 | 2405 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2406 | { |
2407 | if (kvm_enabled()) | |
2408 | kvm_uncoalesce_mmio_region(addr, size); | |
2409 | } | |
2410 | ||
c227f099 | 2411 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
94a6b54f PB |
2412 | { |
2413 | RAMBlock *new_block; | |
2414 | ||
94a6b54f PB |
2415 | size = TARGET_PAGE_ALIGN(size); |
2416 | new_block = qemu_malloc(sizeof(*new_block)); | |
2417 | ||
6b02494d AG |
2418 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
2419 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ | |
2420 | new_block->host = mmap((void*)0x1000000, size, PROT_EXEC|PROT_READ|PROT_WRITE, | |
2421 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
2422 | #else | |
94a6b54f | 2423 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2424 | #endif |
ccb167e9 IE |
2425 | #ifdef MADV_MERGEABLE |
2426 | madvise(new_block->host, size, MADV_MERGEABLE); | |
2427 | #endif | |
94a6b54f PB |
2428 | new_block->offset = last_ram_offset; |
2429 | new_block->length = size; | |
2430 | ||
2431 | new_block->next = ram_blocks; | |
2432 | ram_blocks = new_block; | |
2433 | ||
2434 | phys_ram_dirty = qemu_realloc(phys_ram_dirty, | |
2435 | (last_ram_offset + size) >> TARGET_PAGE_BITS); | |
2436 | memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS), | |
2437 | 0xff, size >> TARGET_PAGE_BITS); | |
2438 | ||
2439 | last_ram_offset += size; | |
2440 | ||
6f0437e8 JK |
2441 | if (kvm_enabled()) |
2442 | kvm_setup_guest_memory(new_block->host, size); | |
2443 | ||
94a6b54f PB |
2444 | return new_block->offset; |
2445 | } | |
e9a1ab19 | 2446 | |
c227f099 | 2447 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2448 | { |
94a6b54f | 2449 | /* TODO: implement this. */ |
e9a1ab19 FB |
2450 | } |
2451 | ||
dc828ca1 | 2452 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2453 | With the exception of the softmmu code in this file, this should |
2454 | only be used for local memory (e.g. video ram) that the device owns, | |
2455 | and knows it isn't going to access beyond the end of the block. | |
2456 | ||
2457 | It should not be used for general purpose DMA. | |
2458 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2459 | */ | |
c227f099 | 2460 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 2461 | { |
94a6b54f PB |
2462 | RAMBlock *prev; |
2463 | RAMBlock **prevp; | |
2464 | RAMBlock *block; | |
2465 | ||
94a6b54f PB |
2466 | prev = NULL; |
2467 | prevp = &ram_blocks; | |
2468 | block = ram_blocks; | |
2469 | while (block && (block->offset > addr | |
2470 | || block->offset + block->length <= addr)) { | |
2471 | if (prev) | |
2472 | prevp = &prev->next; | |
2473 | prev = block; | |
2474 | block = block->next; | |
2475 | } | |
2476 | if (!block) { | |
2477 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2478 | abort(); | |
2479 | } | |
2480 | /* Move this entry to to start of the list. */ | |
2481 | if (prev) { | |
2482 | prev->next = block->next; | |
2483 | block->next = *prevp; | |
2484 | *prevp = block; | |
2485 | } | |
2486 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
2487 | } |
2488 | ||
5579c7f3 PB |
2489 | /* Some of the softmmu routines need to translate from a host pointer |
2490 | (typically a TLB entry) back to a ram offset. */ | |
c227f099 | 2491 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
5579c7f3 | 2492 | { |
94a6b54f PB |
2493 | RAMBlock *prev; |
2494 | RAMBlock **prevp; | |
2495 | RAMBlock *block; | |
2496 | uint8_t *host = ptr; | |
2497 | ||
94a6b54f PB |
2498 | prev = NULL; |
2499 | prevp = &ram_blocks; | |
2500 | block = ram_blocks; | |
2501 | while (block && (block->host > host | |
2502 | || block->host + block->length <= host)) { | |
2503 | if (prev) | |
2504 | prevp = &prev->next; | |
2505 | prev = block; | |
2506 | block = block->next; | |
2507 | } | |
2508 | if (!block) { | |
2509 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2510 | abort(); | |
2511 | } | |
2512 | return block->offset + (host - block->host); | |
5579c7f3 PB |
2513 | } |
2514 | ||
c227f099 | 2515 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2516 | { |
67d3b957 | 2517 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2518 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2519 | #endif |
faed1c2a | 2520 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2521 | do_unassigned_access(addr, 0, 0, 0, 1); |
2522 | #endif | |
2523 | return 0; | |
2524 | } | |
2525 | ||
c227f099 | 2526 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2527 | { |
2528 | #ifdef DEBUG_UNASSIGNED | |
2529 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2530 | #endif | |
faed1c2a | 2531 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2532 | do_unassigned_access(addr, 0, 0, 0, 2); |
2533 | #endif | |
2534 | return 0; | |
2535 | } | |
2536 | ||
c227f099 | 2537 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2538 | { |
2539 | #ifdef DEBUG_UNASSIGNED | |
2540 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2541 | #endif | |
faed1c2a | 2542 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2543 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2544 | #endif |
33417e70 FB |
2545 | return 0; |
2546 | } | |
2547 | ||
c227f099 | 2548 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2549 | { |
67d3b957 | 2550 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2551 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2552 | #endif |
faed1c2a | 2553 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2554 | do_unassigned_access(addr, 1, 0, 0, 1); |
2555 | #endif | |
2556 | } | |
2557 | ||
c227f099 | 2558 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2559 | { |
2560 | #ifdef DEBUG_UNASSIGNED | |
2561 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2562 | #endif | |
faed1c2a | 2563 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2564 | do_unassigned_access(addr, 1, 0, 0, 2); |
2565 | #endif | |
2566 | } | |
2567 | ||
c227f099 | 2568 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2569 | { |
2570 | #ifdef DEBUG_UNASSIGNED | |
2571 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2572 | #endif | |
faed1c2a | 2573 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2574 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 2575 | #endif |
33417e70 FB |
2576 | } |
2577 | ||
d60efc6b | 2578 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 2579 | unassigned_mem_readb, |
e18231a3 BS |
2580 | unassigned_mem_readw, |
2581 | unassigned_mem_readl, | |
33417e70 FB |
2582 | }; |
2583 | ||
d60efc6b | 2584 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 2585 | unassigned_mem_writeb, |
e18231a3 BS |
2586 | unassigned_mem_writew, |
2587 | unassigned_mem_writel, | |
33417e70 FB |
2588 | }; |
2589 | ||
c227f099 | 2590 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2591 | uint32_t val) |
9fa3e853 | 2592 | { |
3a7d929e | 2593 | int dirty_flags; |
3a7d929e FB |
2594 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2595 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2596 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2597 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2598 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2599 | #endif |
3a7d929e | 2600 | } |
5579c7f3 | 2601 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2602 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2603 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2604 | /* we remove the notdirty callback only if the code has been | |
2605 | flushed */ | |
2606 | if (dirty_flags == 0xff) | |
2e70f6ef | 2607 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2608 | } |
2609 | ||
c227f099 | 2610 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2611 | uint32_t val) |
9fa3e853 | 2612 | { |
3a7d929e | 2613 | int dirty_flags; |
3a7d929e FB |
2614 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2615 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2616 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2617 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2618 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2619 | #endif |
3a7d929e | 2620 | } |
5579c7f3 | 2621 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2622 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2623 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2624 | /* we remove the notdirty callback only if the code has been | |
2625 | flushed */ | |
2626 | if (dirty_flags == 0xff) | |
2e70f6ef | 2627 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2628 | } |
2629 | ||
c227f099 | 2630 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2631 | uint32_t val) |
9fa3e853 | 2632 | { |
3a7d929e | 2633 | int dirty_flags; |
3a7d929e FB |
2634 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2635 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2636 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2637 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2638 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2639 | #endif |
3a7d929e | 2640 | } |
5579c7f3 | 2641 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2642 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2643 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2644 | /* we remove the notdirty callback only if the code has been | |
2645 | flushed */ | |
2646 | if (dirty_flags == 0xff) | |
2e70f6ef | 2647 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2648 | } |
2649 | ||
d60efc6b | 2650 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
2651 | NULL, /* never used */ |
2652 | NULL, /* never used */ | |
2653 | NULL, /* never used */ | |
2654 | }; | |
2655 | ||
d60efc6b | 2656 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
2657 | notdirty_mem_writeb, |
2658 | notdirty_mem_writew, | |
2659 | notdirty_mem_writel, | |
2660 | }; | |
2661 | ||
0f459d16 | 2662 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 2663 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
2664 | { |
2665 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
2666 | target_ulong pc, cs_base; |
2667 | TranslationBlock *tb; | |
0f459d16 | 2668 | target_ulong vaddr; |
a1d1bb31 | 2669 | CPUWatchpoint *wp; |
06d55cc1 | 2670 | int cpu_flags; |
0f459d16 | 2671 | |
06d55cc1 AL |
2672 | if (env->watchpoint_hit) { |
2673 | /* We re-entered the check after replacing the TB. Now raise | |
2674 | * the debug interrupt so that is will trigger after the | |
2675 | * current instruction. */ | |
2676 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
2677 | return; | |
2678 | } | |
2e70f6ef | 2679 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 2680 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
2681 | if ((vaddr == (wp->vaddr & len_mask) || |
2682 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
2683 | wp->flags |= BP_WATCHPOINT_HIT; |
2684 | if (!env->watchpoint_hit) { | |
2685 | env->watchpoint_hit = wp; | |
2686 | tb = tb_find_pc(env->mem_io_pc); | |
2687 | if (!tb) { | |
2688 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
2689 | "pc=%p", (void *)env->mem_io_pc); | |
2690 | } | |
2691 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
2692 | tb_phys_invalidate(tb, -1); | |
2693 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2694 | env->exception_index = EXCP_DEBUG; | |
2695 | } else { | |
2696 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
2697 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
2698 | } | |
2699 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 2700 | } |
6e140f28 AL |
2701 | } else { |
2702 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2703 | } |
2704 | } | |
2705 | } | |
2706 | ||
6658ffb8 PB |
2707 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2708 | so these check for a hit then pass through to the normal out-of-line | |
2709 | phys routines. */ | |
c227f099 | 2710 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2711 | { |
b4051334 | 2712 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
2713 | return ldub_phys(addr); |
2714 | } | |
2715 | ||
c227f099 | 2716 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2717 | { |
b4051334 | 2718 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
2719 | return lduw_phys(addr); |
2720 | } | |
2721 | ||
c227f099 | 2722 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 2723 | { |
b4051334 | 2724 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
2725 | return ldl_phys(addr); |
2726 | } | |
2727 | ||
c227f099 | 2728 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2729 | uint32_t val) |
2730 | { | |
b4051334 | 2731 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
2732 | stb_phys(addr, val); |
2733 | } | |
2734 | ||
c227f099 | 2735 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2736 | uint32_t val) |
2737 | { | |
b4051334 | 2738 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
2739 | stw_phys(addr, val); |
2740 | } | |
2741 | ||
c227f099 | 2742 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
2743 | uint32_t val) |
2744 | { | |
b4051334 | 2745 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
2746 | stl_phys(addr, val); |
2747 | } | |
2748 | ||
d60efc6b | 2749 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
2750 | watch_mem_readb, |
2751 | watch_mem_readw, | |
2752 | watch_mem_readl, | |
2753 | }; | |
2754 | ||
d60efc6b | 2755 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
2756 | watch_mem_writeb, |
2757 | watch_mem_writew, | |
2758 | watch_mem_writel, | |
2759 | }; | |
6658ffb8 | 2760 | |
c227f099 | 2761 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
2762 | unsigned int len) |
2763 | { | |
db7b5426 BS |
2764 | uint32_t ret; |
2765 | unsigned int idx; | |
2766 | ||
8da3ff18 | 2767 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2768 | #if defined(DEBUG_SUBPAGE) |
2769 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
2770 | mmio, len, addr, idx); | |
2771 | #endif | |
8da3ff18 PB |
2772 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], |
2773 | addr + mmio->region_offset[idx][0][len]); | |
db7b5426 BS |
2774 | |
2775 | return ret; | |
2776 | } | |
2777 | ||
c227f099 | 2778 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
2779 | uint32_t value, unsigned int len) |
2780 | { | |
db7b5426 BS |
2781 | unsigned int idx; |
2782 | ||
8da3ff18 | 2783 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
2784 | #if defined(DEBUG_SUBPAGE) |
2785 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
2786 | mmio, len, addr, idx, value); | |
2787 | #endif | |
8da3ff18 PB |
2788 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], |
2789 | addr + mmio->region_offset[idx][1][len], | |
2790 | value); | |
db7b5426 BS |
2791 | } |
2792 | ||
c227f099 | 2793 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2794 | { |
2795 | #if defined(DEBUG_SUBPAGE) | |
2796 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2797 | #endif | |
2798 | ||
2799 | return subpage_readlen(opaque, addr, 0); | |
2800 | } | |
2801 | ||
c227f099 | 2802 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
2803 | uint32_t value) |
2804 | { | |
2805 | #if defined(DEBUG_SUBPAGE) | |
2806 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2807 | #endif | |
2808 | subpage_writelen(opaque, addr, value, 0); | |
2809 | } | |
2810 | ||
c227f099 | 2811 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2812 | { |
2813 | #if defined(DEBUG_SUBPAGE) | |
2814 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2815 | #endif | |
2816 | ||
2817 | return subpage_readlen(opaque, addr, 1); | |
2818 | } | |
2819 | ||
c227f099 | 2820 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
2821 | uint32_t value) |
2822 | { | |
2823 | #if defined(DEBUG_SUBPAGE) | |
2824 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2825 | #endif | |
2826 | subpage_writelen(opaque, addr, value, 1); | |
2827 | } | |
2828 | ||
c227f099 | 2829 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
2830 | { |
2831 | #if defined(DEBUG_SUBPAGE) | |
2832 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
2833 | #endif | |
2834 | ||
2835 | return subpage_readlen(opaque, addr, 2); | |
2836 | } | |
2837 | ||
2838 | static void subpage_writel (void *opaque, | |
c227f099 | 2839 | target_phys_addr_t addr, uint32_t value) |
db7b5426 BS |
2840 | { |
2841 | #if defined(DEBUG_SUBPAGE) | |
2842 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
2843 | #endif | |
2844 | subpage_writelen(opaque, addr, value, 2); | |
2845 | } | |
2846 | ||
d60efc6b | 2847 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
2848 | &subpage_readb, |
2849 | &subpage_readw, | |
2850 | &subpage_readl, | |
2851 | }; | |
2852 | ||
d60efc6b | 2853 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
2854 | &subpage_writeb, |
2855 | &subpage_writew, | |
2856 | &subpage_writel, | |
2857 | }; | |
2858 | ||
c227f099 AL |
2859 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2860 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
2861 | { |
2862 | int idx, eidx; | |
4254fab8 | 2863 | unsigned int i; |
db7b5426 BS |
2864 | |
2865 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2866 | return -1; | |
2867 | idx = SUBPAGE_IDX(start); | |
2868 | eidx = SUBPAGE_IDX(end); | |
2869 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 2870 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
2871 | mmio, start, end, idx, eidx, memory); |
2872 | #endif | |
2873 | memory >>= IO_MEM_SHIFT; | |
2874 | for (; idx <= eidx; idx++) { | |
4254fab8 | 2875 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
2876 | if (io_mem_read[memory][i]) { |
2877 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
2878 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
8da3ff18 | 2879 | mmio->region_offset[idx][0][i] = region_offset; |
3ee89922 BS |
2880 | } |
2881 | if (io_mem_write[memory][i]) { | |
2882 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
2883 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
8da3ff18 | 2884 | mmio->region_offset[idx][1][i] = region_offset; |
3ee89922 | 2885 | } |
4254fab8 | 2886 | } |
db7b5426 BS |
2887 | } |
2888 | ||
2889 | return 0; | |
2890 | } | |
2891 | ||
c227f099 AL |
2892 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2893 | ram_addr_t orig_memory, ram_addr_t region_offset) | |
db7b5426 | 2894 | { |
c227f099 | 2895 | subpage_t *mmio; |
db7b5426 BS |
2896 | int subpage_memory; |
2897 | ||
c227f099 | 2898 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
2899 | |
2900 | mmio->base = base; | |
1eed09cb | 2901 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 2902 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
2903 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
2904 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 2905 | #endif |
1eec614b AL |
2906 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
2907 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory, | |
8da3ff18 | 2908 | region_offset); |
db7b5426 BS |
2909 | |
2910 | return mmio; | |
2911 | } | |
2912 | ||
88715657 AL |
2913 | static int get_free_io_mem_idx(void) |
2914 | { | |
2915 | int i; | |
2916 | ||
2917 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
2918 | if (!io_mem_used[i]) { | |
2919 | io_mem_used[i] = 1; | |
2920 | return i; | |
2921 | } | |
c6703b47 | 2922 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
2923 | return -1; |
2924 | } | |
2925 | ||
33417e70 FB |
2926 | /* mem_read and mem_write are arrays of functions containing the |
2927 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 2928 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 2929 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
2930 | modified. If it is zero, a new io zone is allocated. The return |
2931 | value can be used with cpu_register_physical_memory(). (-1) is | |
2932 | returned if error. */ | |
1eed09cb | 2933 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
2934 | CPUReadMemoryFunc * const *mem_read, |
2935 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb | 2936 | void *opaque) |
33417e70 | 2937 | { |
4254fab8 | 2938 | int i, subwidth = 0; |
33417e70 FB |
2939 | |
2940 | if (io_index <= 0) { | |
88715657 AL |
2941 | io_index = get_free_io_mem_idx(); |
2942 | if (io_index == -1) | |
2943 | return io_index; | |
33417e70 | 2944 | } else { |
1eed09cb | 2945 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
2946 | if (io_index >= IO_MEM_NB_ENTRIES) |
2947 | return -1; | |
2948 | } | |
b5ff1b31 | 2949 | |
33417e70 | 2950 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
2951 | if (!mem_read[i] || !mem_write[i]) |
2952 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
2953 | io_mem_read[io_index][i] = mem_read[i]; |
2954 | io_mem_write[io_index][i] = mem_write[i]; | |
2955 | } | |
a4193c8a | 2956 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 2957 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 2958 | } |
61382a50 | 2959 | |
d60efc6b BS |
2960 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
2961 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb AK |
2962 | void *opaque) |
2963 | { | |
2964 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
2965 | } | |
2966 | ||
88715657 AL |
2967 | void cpu_unregister_io_memory(int io_table_address) |
2968 | { | |
2969 | int i; | |
2970 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
2971 | ||
2972 | for (i=0;i < 3; i++) { | |
2973 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
2974 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
2975 | } | |
2976 | io_mem_opaque[io_index] = NULL; | |
2977 | io_mem_used[io_index] = 0; | |
2978 | } | |
2979 | ||
e9179ce1 AK |
2980 | static void io_mem_init(void) |
2981 | { | |
2982 | int i; | |
2983 | ||
2984 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
2985 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
2986 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
2987 | for (i=0; i<5; i++) | |
2988 | io_mem_used[i] = 1; | |
2989 | ||
2990 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
2991 | watch_mem_write, NULL); | |
e9179ce1 AK |
2992 | } |
2993 | ||
e2eef170 PB |
2994 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2995 | ||
13eb76e0 FB |
2996 | /* physical memory access (slow version, mainly for debug) */ |
2997 | #if defined(CONFIG_USER_ONLY) | |
c227f099 | 2998 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
2999 | int len, int is_write) |
3000 | { | |
3001 | int l, flags; | |
3002 | target_ulong page; | |
53a5960a | 3003 | void * p; |
13eb76e0 FB |
3004 | |
3005 | while (len > 0) { | |
3006 | page = addr & TARGET_PAGE_MASK; | |
3007 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3008 | if (l > len) | |
3009 | l = len; | |
3010 | flags = page_get_flags(page); | |
3011 | if (!(flags & PAGE_VALID)) | |
3012 | return; | |
3013 | if (is_write) { | |
3014 | if (!(flags & PAGE_WRITE)) | |
3015 | return; | |
579a97f7 | 3016 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3017 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
579a97f7 FB |
3018 | /* FIXME - should this return an error rather than just fail? */ |
3019 | return; | |
72fb7daa AJ |
3020 | memcpy(p, buf, l); |
3021 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3022 | } else { |
3023 | if (!(flags & PAGE_READ)) | |
3024 | return; | |
579a97f7 | 3025 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3026 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
579a97f7 FB |
3027 | /* FIXME - should this return an error rather than just fail? */ |
3028 | return; | |
72fb7daa | 3029 | memcpy(buf, p, l); |
5b257578 | 3030 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3031 | } |
3032 | len -= l; | |
3033 | buf += l; | |
3034 | addr += l; | |
3035 | } | |
3036 | } | |
8df1cd07 | 3037 | |
13eb76e0 | 3038 | #else |
c227f099 | 3039 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3040 | int len, int is_write) |
3041 | { | |
3042 | int l, io_index; | |
3043 | uint8_t *ptr; | |
3044 | uint32_t val; | |
c227f099 | 3045 | target_phys_addr_t page; |
2e12669a | 3046 | unsigned long pd; |
92e873b9 | 3047 | PhysPageDesc *p; |
3b46e624 | 3048 | |
13eb76e0 FB |
3049 | while (len > 0) { |
3050 | page = addr & TARGET_PAGE_MASK; | |
3051 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3052 | if (l > len) | |
3053 | l = len; | |
92e873b9 | 3054 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3055 | if (!p) { |
3056 | pd = IO_MEM_UNASSIGNED; | |
3057 | } else { | |
3058 | pd = p->phys_offset; | |
3059 | } | |
3b46e624 | 3060 | |
13eb76e0 | 3061 | if (is_write) { |
3a7d929e | 3062 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3063 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3064 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3065 | if (p) |
6c2934db | 3066 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3067 | /* XXX: could force cpu_single_env to NULL to avoid |
3068 | potential bugs */ | |
6c2934db | 3069 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3070 | /* 32 bit write access */ |
c27004ec | 3071 | val = ldl_p(buf); |
6c2934db | 3072 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3073 | l = 4; |
6c2934db | 3074 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3075 | /* 16 bit write access */ |
c27004ec | 3076 | val = lduw_p(buf); |
6c2934db | 3077 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3078 | l = 2; |
3079 | } else { | |
1c213d19 | 3080 | /* 8 bit write access */ |
c27004ec | 3081 | val = ldub_p(buf); |
6c2934db | 3082 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3083 | l = 1; |
3084 | } | |
3085 | } else { | |
b448f2f3 FB |
3086 | unsigned long addr1; |
3087 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3088 | /* RAM case */ |
5579c7f3 | 3089 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3090 | memcpy(ptr, buf, l); |
3a7d929e FB |
3091 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3092 | /* invalidate code */ | |
3093 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3094 | /* set dirty bit */ | |
5fafdf24 | 3095 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 3096 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 3097 | } |
13eb76e0 FB |
3098 | } |
3099 | } else { | |
5fafdf24 | 3100 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3101 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3102 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3103 | /* I/O case */ |
3104 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3105 | if (p) |
6c2934db AJ |
3106 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3107 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3108 | /* 32 bit read access */ |
6c2934db | 3109 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3110 | stl_p(buf, val); |
13eb76e0 | 3111 | l = 4; |
6c2934db | 3112 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3113 | /* 16 bit read access */ |
6c2934db | 3114 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3115 | stw_p(buf, val); |
13eb76e0 FB |
3116 | l = 2; |
3117 | } else { | |
1c213d19 | 3118 | /* 8 bit read access */ |
6c2934db | 3119 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3120 | stb_p(buf, val); |
13eb76e0 FB |
3121 | l = 1; |
3122 | } | |
3123 | } else { | |
3124 | /* RAM case */ | |
5579c7f3 | 3125 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3126 | (addr & ~TARGET_PAGE_MASK); |
3127 | memcpy(buf, ptr, l); | |
3128 | } | |
3129 | } | |
3130 | len -= l; | |
3131 | buf += l; | |
3132 | addr += l; | |
3133 | } | |
3134 | } | |
8df1cd07 | 3135 | |
d0ecd2aa | 3136 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3137 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3138 | const uint8_t *buf, int len) |
3139 | { | |
3140 | int l; | |
3141 | uint8_t *ptr; | |
c227f099 | 3142 | target_phys_addr_t page; |
d0ecd2aa FB |
3143 | unsigned long pd; |
3144 | PhysPageDesc *p; | |
3b46e624 | 3145 | |
d0ecd2aa FB |
3146 | while (len > 0) { |
3147 | page = addr & TARGET_PAGE_MASK; | |
3148 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3149 | if (l > len) | |
3150 | l = len; | |
3151 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3152 | if (!p) { | |
3153 | pd = IO_MEM_UNASSIGNED; | |
3154 | } else { | |
3155 | pd = p->phys_offset; | |
3156 | } | |
3b46e624 | 3157 | |
d0ecd2aa | 3158 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3159 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3160 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3161 | /* do nothing */ |
3162 | } else { | |
3163 | unsigned long addr1; | |
3164 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3165 | /* ROM/RAM case */ | |
5579c7f3 | 3166 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3167 | memcpy(ptr, buf, l); |
3168 | } | |
3169 | len -= l; | |
3170 | buf += l; | |
3171 | addr += l; | |
3172 | } | |
3173 | } | |
3174 | ||
6d16c2f8 AL |
3175 | typedef struct { |
3176 | void *buffer; | |
c227f099 AL |
3177 | target_phys_addr_t addr; |
3178 | target_phys_addr_t len; | |
6d16c2f8 AL |
3179 | } BounceBuffer; |
3180 | ||
3181 | static BounceBuffer bounce; | |
3182 | ||
ba223c29 AL |
3183 | typedef struct MapClient { |
3184 | void *opaque; | |
3185 | void (*callback)(void *opaque); | |
72cf2d4f | 3186 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3187 | } MapClient; |
3188 | ||
72cf2d4f BS |
3189 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3190 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3191 | |
3192 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3193 | { | |
3194 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3195 | ||
3196 | client->opaque = opaque; | |
3197 | client->callback = callback; | |
72cf2d4f | 3198 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3199 | return client; |
3200 | } | |
3201 | ||
3202 | void cpu_unregister_map_client(void *_client) | |
3203 | { | |
3204 | MapClient *client = (MapClient *)_client; | |
3205 | ||
72cf2d4f | 3206 | QLIST_REMOVE(client, link); |
34d5e948 | 3207 | qemu_free(client); |
ba223c29 AL |
3208 | } |
3209 | ||
3210 | static void cpu_notify_map_clients(void) | |
3211 | { | |
3212 | MapClient *client; | |
3213 | ||
72cf2d4f BS |
3214 | while (!QLIST_EMPTY(&map_client_list)) { |
3215 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3216 | client->callback(client->opaque); |
34d5e948 | 3217 | cpu_unregister_map_client(client); |
ba223c29 AL |
3218 | } |
3219 | } | |
3220 | ||
6d16c2f8 AL |
3221 | /* Map a physical memory region into a host virtual address. |
3222 | * May map a subset of the requested range, given by and returned in *plen. | |
3223 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3224 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3225 | * Use cpu_register_map_client() to know when retrying the map operation is |
3226 | * likely to succeed. | |
6d16c2f8 | 3227 | */ |
c227f099 AL |
3228 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3229 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3230 | int is_write) |
3231 | { | |
c227f099 AL |
3232 | target_phys_addr_t len = *plen; |
3233 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3234 | int l; |
3235 | uint8_t *ret = NULL; | |
3236 | uint8_t *ptr; | |
c227f099 | 3237 | target_phys_addr_t page; |
6d16c2f8 AL |
3238 | unsigned long pd; |
3239 | PhysPageDesc *p; | |
3240 | unsigned long addr1; | |
3241 | ||
3242 | while (len > 0) { | |
3243 | page = addr & TARGET_PAGE_MASK; | |
3244 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3245 | if (l > len) | |
3246 | l = len; | |
3247 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3248 | if (!p) { | |
3249 | pd = IO_MEM_UNASSIGNED; | |
3250 | } else { | |
3251 | pd = p->phys_offset; | |
3252 | } | |
3253 | ||
3254 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3255 | if (done || bounce.buffer) { | |
3256 | break; | |
3257 | } | |
3258 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3259 | bounce.addr = addr; | |
3260 | bounce.len = l; | |
3261 | if (!is_write) { | |
3262 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3263 | } | |
3264 | ptr = bounce.buffer; | |
3265 | } else { | |
3266 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3267 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3268 | } |
3269 | if (!done) { | |
3270 | ret = ptr; | |
3271 | } else if (ret + done != ptr) { | |
3272 | break; | |
3273 | } | |
3274 | ||
3275 | len -= l; | |
3276 | addr += l; | |
3277 | done += l; | |
3278 | } | |
3279 | *plen = done; | |
3280 | return ret; | |
3281 | } | |
3282 | ||
3283 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3284 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3285 | * the amount of memory that was actually read or written by the caller. | |
3286 | */ | |
c227f099 AL |
3287 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
3288 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
3289 | { |
3290 | if (buffer != bounce.buffer) { | |
3291 | if (is_write) { | |
c227f099 | 3292 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
6d16c2f8 AL |
3293 | while (access_len) { |
3294 | unsigned l; | |
3295 | l = TARGET_PAGE_SIZE; | |
3296 | if (l > access_len) | |
3297 | l = access_len; | |
3298 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3299 | /* invalidate code */ | |
3300 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3301 | /* set dirty bit */ | |
3302 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3303 | (0xff & ~CODE_DIRTY_FLAG); | |
3304 | } | |
3305 | addr1 += l; | |
3306 | access_len -= l; | |
3307 | } | |
3308 | } | |
3309 | return; | |
3310 | } | |
3311 | if (is_write) { | |
3312 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3313 | } | |
3314 | qemu_free(bounce.buffer); | |
3315 | bounce.buffer = NULL; | |
ba223c29 | 3316 | cpu_notify_map_clients(); |
6d16c2f8 | 3317 | } |
d0ecd2aa | 3318 | |
8df1cd07 | 3319 | /* warning: addr must be aligned */ |
c227f099 | 3320 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
3321 | { |
3322 | int io_index; | |
3323 | uint8_t *ptr; | |
3324 | uint32_t val; | |
3325 | unsigned long pd; | |
3326 | PhysPageDesc *p; | |
3327 | ||
3328 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3329 | if (!p) { | |
3330 | pd = IO_MEM_UNASSIGNED; | |
3331 | } else { | |
3332 | pd = p->phys_offset; | |
3333 | } | |
3b46e624 | 3334 | |
5fafdf24 | 3335 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3336 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3337 | /* I/O case */ |
3338 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3339 | if (p) |
3340 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3341 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3342 | } else { | |
3343 | /* RAM case */ | |
5579c7f3 | 3344 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3345 | (addr & ~TARGET_PAGE_MASK); |
3346 | val = ldl_p(ptr); | |
3347 | } | |
3348 | return val; | |
3349 | } | |
3350 | ||
84b7b8e7 | 3351 | /* warning: addr must be aligned */ |
c227f099 | 3352 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
3353 | { |
3354 | int io_index; | |
3355 | uint8_t *ptr; | |
3356 | uint64_t val; | |
3357 | unsigned long pd; | |
3358 | PhysPageDesc *p; | |
3359 | ||
3360 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3361 | if (!p) { | |
3362 | pd = IO_MEM_UNASSIGNED; | |
3363 | } else { | |
3364 | pd = p->phys_offset; | |
3365 | } | |
3b46e624 | 3366 | |
2a4188a3 FB |
3367 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3368 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3369 | /* I/O case */ |
3370 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3371 | if (p) |
3372 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3373 | #ifdef TARGET_WORDS_BIGENDIAN |
3374 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3375 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3376 | #else | |
3377 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3378 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3379 | #endif | |
3380 | } else { | |
3381 | /* RAM case */ | |
5579c7f3 | 3382 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3383 | (addr & ~TARGET_PAGE_MASK); |
3384 | val = ldq_p(ptr); | |
3385 | } | |
3386 | return val; | |
3387 | } | |
3388 | ||
aab33094 | 3389 | /* XXX: optimize */ |
c227f099 | 3390 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
3391 | { |
3392 | uint8_t val; | |
3393 | cpu_physical_memory_read(addr, &val, 1); | |
3394 | return val; | |
3395 | } | |
3396 | ||
3397 | /* XXX: optimize */ | |
c227f099 | 3398 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 FB |
3399 | { |
3400 | uint16_t val; | |
3401 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
3402 | return tswap16(val); | |
3403 | } | |
3404 | ||
8df1cd07 FB |
3405 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3406 | and the code inside is not invalidated. It is useful if the dirty | |
3407 | bits are used to track modified PTEs */ | |
c227f099 | 3408 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3409 | { |
3410 | int io_index; | |
3411 | uint8_t *ptr; | |
3412 | unsigned long pd; | |
3413 | PhysPageDesc *p; | |
3414 | ||
3415 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3416 | if (!p) { | |
3417 | pd = IO_MEM_UNASSIGNED; | |
3418 | } else { | |
3419 | pd = p->phys_offset; | |
3420 | } | |
3b46e624 | 3421 | |
3a7d929e | 3422 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3423 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3424 | if (p) |
3425 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3426 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3427 | } else { | |
74576198 | 3428 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3429 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3430 | stl_p(ptr, val); |
74576198 AL |
3431 | |
3432 | if (unlikely(in_migration)) { | |
3433 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3434 | /* invalidate code */ | |
3435 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3436 | /* set dirty bit */ | |
3437 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3438 | (0xff & ~CODE_DIRTY_FLAG); | |
3439 | } | |
3440 | } | |
8df1cd07 FB |
3441 | } |
3442 | } | |
3443 | ||
c227f099 | 3444 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
3445 | { |
3446 | int io_index; | |
3447 | uint8_t *ptr; | |
3448 | unsigned long pd; | |
3449 | PhysPageDesc *p; | |
3450 | ||
3451 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3452 | if (!p) { | |
3453 | pd = IO_MEM_UNASSIGNED; | |
3454 | } else { | |
3455 | pd = p->phys_offset; | |
3456 | } | |
3b46e624 | 3457 | |
bc98a7ef JM |
3458 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3459 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3460 | if (p) |
3461 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3462 | #ifdef TARGET_WORDS_BIGENDIAN |
3463 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3464 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3465 | #else | |
3466 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3467 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3468 | #endif | |
3469 | } else { | |
5579c7f3 | 3470 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3471 | (addr & ~TARGET_PAGE_MASK); |
3472 | stq_p(ptr, val); | |
3473 | } | |
3474 | } | |
3475 | ||
8df1cd07 | 3476 | /* warning: addr must be aligned */ |
c227f099 | 3477 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3478 | { |
3479 | int io_index; | |
3480 | uint8_t *ptr; | |
3481 | unsigned long pd; | |
3482 | PhysPageDesc *p; | |
3483 | ||
3484 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3485 | if (!p) { | |
3486 | pd = IO_MEM_UNASSIGNED; | |
3487 | } else { | |
3488 | pd = p->phys_offset; | |
3489 | } | |
3b46e624 | 3490 | |
3a7d929e | 3491 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3492 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3493 | if (p) |
3494 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3495 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3496 | } else { | |
3497 | unsigned long addr1; | |
3498 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3499 | /* RAM case */ | |
5579c7f3 | 3500 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3501 | stl_p(ptr, val); |
3a7d929e FB |
3502 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3503 | /* invalidate code */ | |
3504 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3505 | /* set dirty bit */ | |
f23db169 FB |
3506 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
3507 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 3508 | } |
8df1cd07 FB |
3509 | } |
3510 | } | |
3511 | ||
aab33094 | 3512 | /* XXX: optimize */ |
c227f099 | 3513 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3514 | { |
3515 | uint8_t v = val; | |
3516 | cpu_physical_memory_write(addr, &v, 1); | |
3517 | } | |
3518 | ||
3519 | /* XXX: optimize */ | |
c227f099 | 3520 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3521 | { |
3522 | uint16_t v = tswap16(val); | |
3523 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
3524 | } | |
3525 | ||
3526 | /* XXX: optimize */ | |
c227f099 | 3527 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
3528 | { |
3529 | val = tswap64(val); | |
3530 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3531 | } | |
3532 | ||
13eb76e0 FB |
3533 | #endif |
3534 | ||
5e2972fd | 3535 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 3536 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3537 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3538 | { |
3539 | int l; | |
c227f099 | 3540 | target_phys_addr_t phys_addr; |
9b3c35e0 | 3541 | target_ulong page; |
13eb76e0 FB |
3542 | |
3543 | while (len > 0) { | |
3544 | page = addr & TARGET_PAGE_MASK; | |
3545 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3546 | /* if no physical page mapped, return an error */ | |
3547 | if (phys_addr == -1) | |
3548 | return -1; | |
3549 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3550 | if (l > len) | |
3551 | l = len; | |
5e2972fd AL |
3552 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
3553 | #if !defined(CONFIG_USER_ONLY) | |
3554 | if (is_write) | |
3555 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
3556 | else | |
3557 | #endif | |
3558 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); | |
13eb76e0 FB |
3559 | len -= l; |
3560 | buf += l; | |
3561 | addr += l; | |
3562 | } | |
3563 | return 0; | |
3564 | } | |
3565 | ||
2e70f6ef PB |
3566 | /* in deterministic execution mode, instructions doing device I/Os |
3567 | must be at the end of the TB */ | |
3568 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3569 | { | |
3570 | TranslationBlock *tb; | |
3571 | uint32_t n, cflags; | |
3572 | target_ulong pc, cs_base; | |
3573 | uint64_t flags; | |
3574 | ||
3575 | tb = tb_find_pc((unsigned long)retaddr); | |
3576 | if (!tb) { | |
3577 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3578 | retaddr); | |
3579 | } | |
3580 | n = env->icount_decr.u16.low + tb->icount; | |
3581 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3582 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3583 | occurred. */ |
2e70f6ef PB |
3584 | n = n - env->icount_decr.u16.low; |
3585 | /* Generate a new TB ending on the I/O insn. */ | |
3586 | n++; | |
3587 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3588 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3589 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3590 | branch. */ |
3591 | #if defined(TARGET_MIPS) | |
3592 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3593 | env->active_tc.PC -= 4; | |
3594 | env->icount_decr.u16.low++; | |
3595 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3596 | } | |
3597 | #elif defined(TARGET_SH4) | |
3598 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3599 | && n > 1) { | |
3600 | env->pc -= 2; | |
3601 | env->icount_decr.u16.low++; | |
3602 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3603 | } | |
3604 | #endif | |
3605 | /* This should never happen. */ | |
3606 | if (n > CF_COUNT_MASK) | |
3607 | cpu_abort(env, "TB too big during recompile"); | |
3608 | ||
3609 | cflags = n | CF_LAST_IO; | |
3610 | pc = tb->pc; | |
3611 | cs_base = tb->cs_base; | |
3612 | flags = tb->flags; | |
3613 | tb_phys_invalidate(tb, -1); | |
3614 | /* FIXME: In theory this could raise an exception. In practice | |
3615 | we have already translated the block once so it's probably ok. */ | |
3616 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3617 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
3618 | the first in the TB) then we end up generating a whole new TB and |
3619 | repeating the fault, which is horribly inefficient. | |
3620 | Better would be to execute just this insn uncached, or generate a | |
3621 | second new TB. */ | |
3622 | cpu_resume_from_signal(env, NULL); | |
3623 | } | |
3624 | ||
e3db7226 FB |
3625 | void dump_exec_info(FILE *f, |
3626 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3627 | { | |
3628 | int i, target_code_size, max_target_code_size; | |
3629 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
3630 | TranslationBlock *tb; | |
3b46e624 | 3631 | |
e3db7226 FB |
3632 | target_code_size = 0; |
3633 | max_target_code_size = 0; | |
3634 | cross_page = 0; | |
3635 | direct_jmp_count = 0; | |
3636 | direct_jmp2_count = 0; | |
3637 | for(i = 0; i < nb_tbs; i++) { | |
3638 | tb = &tbs[i]; | |
3639 | target_code_size += tb->size; | |
3640 | if (tb->size > max_target_code_size) | |
3641 | max_target_code_size = tb->size; | |
3642 | if (tb->page_addr[1] != -1) | |
3643 | cross_page++; | |
3644 | if (tb->tb_next_offset[0] != 0xffff) { | |
3645 | direct_jmp_count++; | |
3646 | if (tb->tb_next_offset[1] != 0xffff) { | |
3647 | direct_jmp2_count++; | |
3648 | } | |
3649 | } | |
3650 | } | |
3651 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 3652 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
3653 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
3654 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
3655 | cpu_fprintf(f, "TB count %d/%d\n", | |
3656 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 3657 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
3658 | nb_tbs ? target_code_size / nb_tbs : 0, |
3659 | max_target_code_size); | |
5fafdf24 | 3660 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
3661 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
3662 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
3663 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
3664 | cross_page, | |
e3db7226 FB |
3665 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
3666 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 3667 | direct_jmp_count, |
e3db7226 FB |
3668 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
3669 | direct_jmp2_count, | |
3670 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 3671 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
3672 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
3673 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
3674 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 3675 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
3676 | } |
3677 | ||
5fafdf24 | 3678 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3679 | |
3680 | #define MMUSUFFIX _cmmu | |
3681 | #define GETPC() NULL | |
3682 | #define env cpu_single_env | |
b769d8fe | 3683 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3684 | |
3685 | #define SHIFT 0 | |
3686 | #include "softmmu_template.h" | |
3687 | ||
3688 | #define SHIFT 1 | |
3689 | #include "softmmu_template.h" | |
3690 | ||
3691 | #define SHIFT 2 | |
3692 | #include "softmmu_template.h" | |
3693 | ||
3694 | #define SHIFT 3 | |
3695 | #include "softmmu_template.h" | |
3696 | ||
3697 | #undef env | |
3698 | ||
3699 | #endif |