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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
7b31bbc2 | 19 | #include "qemu/osdep.h" |
da34e65c | 20 | #include "qapi/error.h" |
777872e5 | 21 | #ifndef _WIN32 |
d5a8f07c FB |
22 | #include <sys/mman.h> |
23 | #endif | |
54936004 | 24 | |
f348b6d1 | 25 | #include "qemu/cutils.h" |
6180a181 | 26 | #include "cpu.h" |
b67d9a52 | 27 | #include "tcg.h" |
b3c7724c | 28 | #include "hw/hw.h" |
4485bd26 | 29 | #if !defined(CONFIG_USER_ONLY) |
47c8ca53 | 30 | #include "hw/boards.h" |
4485bd26 | 31 | #endif |
cc9e98cb | 32 | #include "hw/qdev.h" |
9c17d615 | 33 | #include "sysemu/kvm.h" |
2ff3de68 | 34 | #include "sysemu/sysemu.h" |
0d09e41a | 35 | #include "hw/xen/xen.h" |
1de7afc9 PB |
36 | #include "qemu/timer.h" |
37 | #include "qemu/config-file.h" | |
75a34036 | 38 | #include "qemu/error-report.h" |
022c62cb | 39 | #include "exec/memory.h" |
9c17d615 | 40 | #include "sysemu/dma.h" |
022c62cb | 41 | #include "exec/address-spaces.h" |
53a5960a PB |
42 | #if defined(CONFIG_USER_ONLY) |
43 | #include <qemu.h> | |
432d268c | 44 | #else /* !CONFIG_USER_ONLY */ |
9c17d615 | 45 | #include "sysemu/xen-mapcache.h" |
6506e4f9 | 46 | #include "trace.h" |
53a5960a | 47 | #endif |
0d6d3c87 | 48 | #include "exec/cpu-all.h" |
0dc3f44a | 49 | #include "qemu/rcu_queue.h" |
4840f10e | 50 | #include "qemu/main-loop.h" |
5b6dd868 | 51 | #include "translate-all.h" |
7615936e | 52 | #include "sysemu/replay.h" |
0cac1b66 | 53 | |
022c62cb | 54 | #include "exec/memory-internal.h" |
220c3ebd | 55 | #include "exec/ram_addr.h" |
508127e2 | 56 | #include "exec/log.h" |
67d95c15 | 57 | |
b35ba30f | 58 | #include "qemu/range.h" |
794e8f30 MT |
59 | #ifndef _WIN32 |
60 | #include "qemu/mmap-alloc.h" | |
61 | #endif | |
b35ba30f | 62 | |
db7b5426 | 63 | //#define DEBUG_SUBPAGE |
1196be37 | 64 | |
e2eef170 | 65 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a MD |
66 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
67 | * are protected by the ramlist lock. | |
68 | */ | |
0d53d9fe | 69 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
70 | |
71 | static MemoryRegion *system_memory; | |
309cb471 | 72 | static MemoryRegion *system_io; |
62152b8a | 73 | |
f6790af6 AK |
74 | AddressSpace address_space_io; |
75 | AddressSpace address_space_memory; | |
2673a5da | 76 | |
0844e007 | 77 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 78 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 79 | |
7bd4f430 PB |
80 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
81 | #define RAM_PREALLOC (1 << 0) | |
82 | ||
dbcb8981 PB |
83 | /* RAM is mmap-ed with MAP_SHARED */ |
84 | #define RAM_SHARED (1 << 1) | |
85 | ||
62be4e3a MT |
86 | /* Only a portion of RAM (used_length) is actually used, and migrated. |
87 | * This used_length size can change across reboots. | |
88 | */ | |
89 | #define RAM_RESIZEABLE (1 << 2) | |
90 | ||
e2eef170 | 91 | #endif |
9fa3e853 | 92 | |
bdc44640 | 93 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
6a00d601 FB |
94 | /* current CPU in the current thread. It is only valid inside |
95 | cpu_exec() */ | |
f240eb6f | 96 | __thread CPUState *current_cpu; |
2e70f6ef | 97 | /* 0 = Do not count executed instructions. |
bf20dc07 | 98 | 1 = Precise instruction counting. |
2e70f6ef | 99 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 100 | int use_icount; |
6a00d601 | 101 | |
e2eef170 | 102 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 103 | |
1db8abb1 PB |
104 | typedef struct PhysPageEntry PhysPageEntry; |
105 | ||
106 | struct PhysPageEntry { | |
9736e55b | 107 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 108 | uint32_t skip : 6; |
9736e55b | 109 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 110 | uint32_t ptr : 26; |
1db8abb1 PB |
111 | }; |
112 | ||
8b795765 MT |
113 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
114 | ||
03f49957 | 115 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 116 | #define ADDR_SPACE_BITS 64 |
03f49957 | 117 | |
026736ce | 118 | #define P_L2_BITS 9 |
03f49957 PB |
119 | #define P_L2_SIZE (1 << P_L2_BITS) |
120 | ||
121 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
122 | ||
123 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 124 | |
53cb28cb | 125 | typedef struct PhysPageMap { |
79e2b9ae PB |
126 | struct rcu_head rcu; |
127 | ||
53cb28cb MA |
128 | unsigned sections_nb; |
129 | unsigned sections_nb_alloc; | |
130 | unsigned nodes_nb; | |
131 | unsigned nodes_nb_alloc; | |
132 | Node *nodes; | |
133 | MemoryRegionSection *sections; | |
134 | } PhysPageMap; | |
135 | ||
1db8abb1 | 136 | struct AddressSpaceDispatch { |
79e2b9ae PB |
137 | struct rcu_head rcu; |
138 | ||
729633c2 | 139 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
140 | /* This is a multi-level map on the physical address space. |
141 | * The bottom level has pointers to MemoryRegionSections. | |
142 | */ | |
143 | PhysPageEntry phys_map; | |
53cb28cb | 144 | PhysPageMap map; |
acc9d80b | 145 | AddressSpace *as; |
1db8abb1 PB |
146 | }; |
147 | ||
90260c6c JK |
148 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
149 | typedef struct subpage_t { | |
150 | MemoryRegion iomem; | |
acc9d80b | 151 | AddressSpace *as; |
90260c6c JK |
152 | hwaddr base; |
153 | uint16_t sub_section[TARGET_PAGE_SIZE]; | |
154 | } subpage_t; | |
155 | ||
b41aac4f LPF |
156 | #define PHYS_SECTION_UNASSIGNED 0 |
157 | #define PHYS_SECTION_NOTDIRTY 1 | |
158 | #define PHYS_SECTION_ROM 2 | |
159 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 160 | |
e2eef170 | 161 | static void io_mem_init(void); |
62152b8a | 162 | static void memory_map_init(void); |
09daed84 | 163 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 164 | |
1ec9b909 | 165 | static MemoryRegion io_mem_watch; |
32857f4d PM |
166 | |
167 | /** | |
168 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
169 | * @cpu: the CPU whose AddressSpace this is | |
170 | * @as: the AddressSpace itself | |
171 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
172 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
173 | */ | |
174 | struct CPUAddressSpace { | |
175 | CPUState *cpu; | |
176 | AddressSpace *as; | |
177 | struct AddressSpaceDispatch *memory_dispatch; | |
178 | MemoryListener tcg_as_listener; | |
179 | }; | |
180 | ||
6658ffb8 | 181 | #endif |
fd6ce8f6 | 182 | |
6d9a1304 | 183 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 184 | |
53cb28cb | 185 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 186 | { |
53cb28cb MA |
187 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
188 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc * 2, 16); | |
189 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); | |
190 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
d6f2ea22 | 191 | } |
f7bf5461 AK |
192 | } |
193 | ||
db94604b | 194 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
195 | { |
196 | unsigned i; | |
8b795765 | 197 | uint32_t ret; |
db94604b PB |
198 | PhysPageEntry e; |
199 | PhysPageEntry *p; | |
f7bf5461 | 200 | |
53cb28cb | 201 | ret = map->nodes_nb++; |
db94604b | 202 | p = map->nodes[ret]; |
f7bf5461 | 203 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 204 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
205 | |
206 | e.skip = leaf ? 0 : 1; | |
207 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 208 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 209 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 210 | } |
f7bf5461 | 211 | return ret; |
d6f2ea22 AK |
212 | } |
213 | ||
53cb28cb MA |
214 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
215 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 216 | int level) |
f7bf5461 AK |
217 | { |
218 | PhysPageEntry *p; | |
03f49957 | 219 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 220 | |
9736e55b | 221 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 222 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 223 | } |
db94604b | 224 | p = map->nodes[lp->ptr]; |
03f49957 | 225 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 226 | |
03f49957 | 227 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 228 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 229 | lp->skip = 0; |
c19e8800 | 230 | lp->ptr = leaf; |
07f07b31 AK |
231 | *index += step; |
232 | *nb -= step; | |
2999097b | 233 | } else { |
53cb28cb | 234 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
235 | } |
236 | ++lp; | |
f7bf5461 AK |
237 | } |
238 | } | |
239 | ||
ac1970fb | 240 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 241 | hwaddr index, hwaddr nb, |
2999097b | 242 | uint16_t leaf) |
f7bf5461 | 243 | { |
2999097b | 244 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 245 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 246 | |
53cb28cb | 247 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
248 | } |
249 | ||
b35ba30f MT |
250 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
251 | * and update our entry so we can skip it and go directly to the destination. | |
252 | */ | |
253 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *compacted) | |
254 | { | |
255 | unsigned valid_ptr = P_L2_SIZE; | |
256 | int valid = 0; | |
257 | PhysPageEntry *p; | |
258 | int i; | |
259 | ||
260 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
261 | return; | |
262 | } | |
263 | ||
264 | p = nodes[lp->ptr]; | |
265 | for (i = 0; i < P_L2_SIZE; i++) { | |
266 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
267 | continue; | |
268 | } | |
269 | ||
270 | valid_ptr = i; | |
271 | valid++; | |
272 | if (p[i].skip) { | |
273 | phys_page_compact(&p[i], nodes, compacted); | |
274 | } | |
275 | } | |
276 | ||
277 | /* We can only compress if there's only one child. */ | |
278 | if (valid != 1) { | |
279 | return; | |
280 | } | |
281 | ||
282 | assert(valid_ptr < P_L2_SIZE); | |
283 | ||
284 | /* Don't compress if it won't fit in the # of bits we have. */ | |
285 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
286 | return; | |
287 | } | |
288 | ||
289 | lp->ptr = p[valid_ptr].ptr; | |
290 | if (!p[valid_ptr].skip) { | |
291 | /* If our only child is a leaf, make this a leaf. */ | |
292 | /* By design, we should have made this node a leaf to begin with so we | |
293 | * should never reach here. | |
294 | * But since it's so simple to handle this, let's do it just in case we | |
295 | * change this rule. | |
296 | */ | |
297 | lp->skip = 0; | |
298 | } else { | |
299 | lp->skip += p[valid_ptr].skip; | |
300 | } | |
301 | } | |
302 | ||
303 | static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb) | |
304 | { | |
305 | DECLARE_BITMAP(compacted, nodes_nb); | |
306 | ||
307 | if (d->phys_map.skip) { | |
53cb28cb | 308 | phys_page_compact(&d->phys_map, d->map.nodes, compacted); |
b35ba30f MT |
309 | } |
310 | } | |
311 | ||
29cb533d FZ |
312 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
313 | hwaddr addr) | |
314 | { | |
315 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
316 | * the section must cover the entire address space. | |
317 | */ | |
318 | return section->size.hi || | |
319 | range_covers_byte(section->offset_within_address_space, | |
320 | section->size.lo, addr); | |
321 | } | |
322 | ||
97115a8d | 323 | static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr, |
9affd6fc | 324 | Node *nodes, MemoryRegionSection *sections) |
92e873b9 | 325 | { |
31ab2b4a | 326 | PhysPageEntry *p; |
97115a8d | 327 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 328 | int i; |
f1f6e3b8 | 329 | |
9736e55b | 330 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 331 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 332 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 333 | } |
9affd6fc | 334 | p = nodes[lp.ptr]; |
03f49957 | 335 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 336 | } |
b35ba30f | 337 | |
29cb533d | 338 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
339 | return §ions[lp.ptr]; |
340 | } else { | |
341 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
342 | } | |
f3705d53 AK |
343 | } |
344 | ||
e5548617 BS |
345 | bool memory_region_is_unassigned(MemoryRegion *mr) |
346 | { | |
2a8e7499 | 347 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 348 | && mr != &io_mem_watch; |
fd6ce8f6 | 349 | } |
149f54b5 | 350 | |
79e2b9ae | 351 | /* Called from RCU critical section */ |
c7086b4a | 352 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
353 | hwaddr addr, |
354 | bool resolve_subpage) | |
9f029603 | 355 | { |
729633c2 | 356 | MemoryRegionSection *section = atomic_read(&d->mru_section); |
90260c6c | 357 | subpage_t *subpage; |
729633c2 | 358 | bool update; |
90260c6c | 359 | |
729633c2 FZ |
360 | if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] && |
361 | section_covers_addr(section, addr)) { | |
362 | update = false; | |
363 | } else { | |
364 | section = phys_page_find(d->phys_map, addr, d->map.nodes, | |
365 | d->map.sections); | |
366 | update = true; | |
367 | } | |
90260c6c JK |
368 | if (resolve_subpage && section->mr->subpage) { |
369 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 370 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c | 371 | } |
729633c2 FZ |
372 | if (update) { |
373 | atomic_set(&d->mru_section, section); | |
374 | } | |
90260c6c | 375 | return section; |
9f029603 JK |
376 | } |
377 | ||
79e2b9ae | 378 | /* Called from RCU critical section */ |
90260c6c | 379 | static MemoryRegionSection * |
c7086b4a | 380 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 381 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
382 | { |
383 | MemoryRegionSection *section; | |
965eb2fc | 384 | MemoryRegion *mr; |
a87f3954 | 385 | Int128 diff; |
149f54b5 | 386 | |
c7086b4a | 387 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
388 | /* Compute offset within MemoryRegionSection */ |
389 | addr -= section->offset_within_address_space; | |
390 | ||
391 | /* Compute offset within MemoryRegion */ | |
392 | *xlat = addr + section->offset_within_region; | |
393 | ||
965eb2fc | 394 | mr = section->mr; |
b242e0e0 PB |
395 | |
396 | /* MMIO registers can be expected to perform full-width accesses based only | |
397 | * on their address, without considering adjacent registers that could | |
398 | * decode to completely different MemoryRegions. When such registers | |
399 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
400 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
401 | * here. | |
402 | * | |
403 | * If the length is small (as is the case for address_space_ldl/stl), | |
404 | * everything works fine. If the incoming length is large, however, | |
405 | * the caller really has to do the clamping through memory_access_size. | |
406 | */ | |
965eb2fc | 407 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 408 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
409 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
410 | } | |
149f54b5 PB |
411 | return section; |
412 | } | |
90260c6c | 413 | |
41063e1e | 414 | /* Called from RCU critical section */ |
5c8a00ce PB |
415 | MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, |
416 | hwaddr *xlat, hwaddr *plen, | |
417 | bool is_write) | |
90260c6c | 418 | { |
30951157 AK |
419 | IOMMUTLBEntry iotlb; |
420 | MemoryRegionSection *section; | |
421 | MemoryRegion *mr; | |
30951157 AK |
422 | |
423 | for (;;) { | |
79e2b9ae PB |
424 | AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch); |
425 | section = address_space_translate_internal(d, addr, &addr, plen, true); | |
30951157 AK |
426 | mr = section->mr; |
427 | ||
428 | if (!mr->iommu_ops) { | |
429 | break; | |
430 | } | |
431 | ||
8d7b8cb9 | 432 | iotlb = mr->iommu_ops->translate(mr, addr, is_write); |
30951157 AK |
433 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) |
434 | | (addr & iotlb.addr_mask)); | |
23820dbf | 435 | *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1); |
30951157 AK |
436 | if (!(iotlb.perm & (1 << is_write))) { |
437 | mr = &io_mem_unassigned; | |
438 | break; | |
439 | } | |
440 | ||
441 | as = iotlb.target_as; | |
442 | } | |
443 | ||
fe680d0d | 444 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 445 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 446 | *plen = MIN(page, *plen); |
a87f3954 PB |
447 | } |
448 | ||
30951157 AK |
449 | *xlat = addr; |
450 | return mr; | |
90260c6c JK |
451 | } |
452 | ||
79e2b9ae | 453 | /* Called from RCU critical section */ |
90260c6c | 454 | MemoryRegionSection * |
d7898cda | 455 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
9d82b5a7 | 456 | hwaddr *xlat, hwaddr *plen) |
90260c6c | 457 | { |
30951157 | 458 | MemoryRegionSection *section; |
d7898cda PM |
459 | AddressSpaceDispatch *d = cpu->cpu_ases[asidx].memory_dispatch; |
460 | ||
461 | section = address_space_translate_internal(d, addr, xlat, plen, false); | |
30951157 AK |
462 | |
463 | assert(!section->mr->iommu_ops); | |
464 | return section; | |
90260c6c | 465 | } |
5b6dd868 | 466 | #endif |
fd6ce8f6 | 467 | |
b170fce3 | 468 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
469 | |
470 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 471 | { |
259186a7 | 472 | CPUState *cpu = opaque; |
a513fe19 | 473 | |
5b6dd868 BS |
474 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
475 | version_id is increased. */ | |
259186a7 | 476 | cpu->interrupt_request &= ~0x01; |
c01a71c1 | 477 | tlb_flush(cpu, 1); |
5b6dd868 BS |
478 | |
479 | return 0; | |
a513fe19 | 480 | } |
7501267e | 481 | |
6c3bff0e PD |
482 | static int cpu_common_pre_load(void *opaque) |
483 | { | |
484 | CPUState *cpu = opaque; | |
485 | ||
adee6424 | 486 | cpu->exception_index = -1; |
6c3bff0e PD |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
491 | static bool cpu_common_exception_index_needed(void *opaque) | |
492 | { | |
493 | CPUState *cpu = opaque; | |
494 | ||
adee6424 | 495 | return tcg_enabled() && cpu->exception_index != -1; |
6c3bff0e PD |
496 | } |
497 | ||
498 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
499 | .name = "cpu_common/exception_index", | |
500 | .version_id = 1, | |
501 | .minimum_version_id = 1, | |
5cd8cada | 502 | .needed = cpu_common_exception_index_needed, |
6c3bff0e PD |
503 | .fields = (VMStateField[]) { |
504 | VMSTATE_INT32(exception_index, CPUState), | |
505 | VMSTATE_END_OF_LIST() | |
506 | } | |
507 | }; | |
508 | ||
bac05aa9 AS |
509 | static bool cpu_common_crash_occurred_needed(void *opaque) |
510 | { | |
511 | CPUState *cpu = opaque; | |
512 | ||
513 | return cpu->crash_occurred; | |
514 | } | |
515 | ||
516 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
517 | .name = "cpu_common/crash_occurred", | |
518 | .version_id = 1, | |
519 | .minimum_version_id = 1, | |
520 | .needed = cpu_common_crash_occurred_needed, | |
521 | .fields = (VMStateField[]) { | |
522 | VMSTATE_BOOL(crash_occurred, CPUState), | |
523 | VMSTATE_END_OF_LIST() | |
524 | } | |
525 | }; | |
526 | ||
1a1562f5 | 527 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
528 | .name = "cpu_common", |
529 | .version_id = 1, | |
530 | .minimum_version_id = 1, | |
6c3bff0e | 531 | .pre_load = cpu_common_pre_load, |
5b6dd868 | 532 | .post_load = cpu_common_post_load, |
35d08458 | 533 | .fields = (VMStateField[]) { |
259186a7 AF |
534 | VMSTATE_UINT32(halted, CPUState), |
535 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 | 536 | VMSTATE_END_OF_LIST() |
6c3bff0e | 537 | }, |
5cd8cada JQ |
538 | .subsections = (const VMStateDescription*[]) { |
539 | &vmstate_cpu_common_exception_index, | |
bac05aa9 | 540 | &vmstate_cpu_common_crash_occurred, |
5cd8cada | 541 | NULL |
5b6dd868 BS |
542 | } |
543 | }; | |
1a1562f5 | 544 | |
5b6dd868 | 545 | #endif |
ea041c0e | 546 | |
38d8f5c8 | 547 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 548 | { |
bdc44640 | 549 | CPUState *cpu; |
ea041c0e | 550 | |
bdc44640 | 551 | CPU_FOREACH(cpu) { |
55e5c285 | 552 | if (cpu->cpu_index == index) { |
bdc44640 | 553 | return cpu; |
55e5c285 | 554 | } |
ea041c0e | 555 | } |
5b6dd868 | 556 | |
bdc44640 | 557 | return NULL; |
ea041c0e FB |
558 | } |
559 | ||
09daed84 | 560 | #if !defined(CONFIG_USER_ONLY) |
56943e8c | 561 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx) |
09daed84 | 562 | { |
12ebc9a7 PM |
563 | CPUAddressSpace *newas; |
564 | ||
565 | /* Target code should have set num_ases before calling us */ | |
566 | assert(asidx < cpu->num_ases); | |
567 | ||
56943e8c PM |
568 | if (asidx == 0) { |
569 | /* address space 0 gets the convenience alias */ | |
570 | cpu->as = as; | |
571 | } | |
572 | ||
12ebc9a7 PM |
573 | /* KVM cannot currently support multiple address spaces. */ |
574 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 575 | |
12ebc9a7 PM |
576 | if (!cpu->cpu_ases) { |
577 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 578 | } |
32857f4d | 579 | |
12ebc9a7 PM |
580 | newas = &cpu->cpu_ases[asidx]; |
581 | newas->cpu = cpu; | |
582 | newas->as = as; | |
56943e8c | 583 | if (tcg_enabled()) { |
12ebc9a7 PM |
584 | newas->tcg_as_listener.commit = tcg_commit; |
585 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 586 | } |
09daed84 | 587 | } |
651a5bc0 PM |
588 | |
589 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
590 | { | |
591 | /* Return the AddressSpace corresponding to the specified index */ | |
592 | return cpu->cpu_ases[asidx].as; | |
593 | } | |
09daed84 EI |
594 | #endif |
595 | ||
b7bca733 BR |
596 | #ifndef CONFIG_USER_ONLY |
597 | static DECLARE_BITMAP(cpu_index_map, MAX_CPUMASK_BITS); | |
598 | ||
599 | static int cpu_get_free_index(Error **errp) | |
600 | { | |
601 | int cpu = find_first_zero_bit(cpu_index_map, MAX_CPUMASK_BITS); | |
602 | ||
603 | if (cpu >= MAX_CPUMASK_BITS) { | |
604 | error_setg(errp, "Trying to use more CPUs than max of %d", | |
605 | MAX_CPUMASK_BITS); | |
606 | return -1; | |
607 | } | |
608 | ||
609 | bitmap_set(cpu_index_map, cpu, 1); | |
610 | return cpu; | |
611 | } | |
612 | ||
613 | void cpu_exec_exit(CPUState *cpu) | |
614 | { | |
615 | if (cpu->cpu_index == -1) { | |
616 | /* cpu_index was never allocated by this @cpu or was already freed. */ | |
617 | return; | |
618 | } | |
619 | ||
620 | bitmap_clear(cpu_index_map, cpu->cpu_index, 1); | |
621 | cpu->cpu_index = -1; | |
622 | } | |
623 | #else | |
624 | ||
625 | static int cpu_get_free_index(Error **errp) | |
626 | { | |
627 | CPUState *some_cpu; | |
628 | int cpu_index = 0; | |
629 | ||
630 | CPU_FOREACH(some_cpu) { | |
631 | cpu_index++; | |
632 | } | |
633 | return cpu_index; | |
634 | } | |
635 | ||
636 | void cpu_exec_exit(CPUState *cpu) | |
637 | { | |
638 | } | |
639 | #endif | |
640 | ||
4bad9e39 | 641 | void cpu_exec_init(CPUState *cpu, Error **errp) |
ea041c0e | 642 | { |
b170fce3 | 643 | CPUClass *cc = CPU_GET_CLASS(cpu); |
5b6dd868 | 644 | int cpu_index; |
b7bca733 | 645 | Error *local_err = NULL; |
5b6dd868 | 646 | |
56943e8c | 647 | cpu->as = NULL; |
12ebc9a7 | 648 | cpu->num_ases = 0; |
56943e8c | 649 | |
291135b5 | 650 | #ifndef CONFIG_USER_ONLY |
291135b5 | 651 | cpu->thread_id = qemu_get_thread_id(); |
6731d864 PC |
652 | |
653 | /* This is a softmmu CPU object, so create a property for it | |
654 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
655 | * because that file is compiled only once for both user-mode | |
656 | * and system builds.) The default if no link is set up is to use | |
657 | * the system address space. | |
658 | */ | |
659 | object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION, | |
660 | (Object **)&cpu->memory, | |
661 | qdev_prop_allow_set_link_before_realize, | |
662 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
663 | &error_abort); | |
664 | cpu->memory = system_memory; | |
665 | object_ref(OBJECT(cpu->memory)); | |
291135b5 EH |
666 | #endif |
667 | ||
5b6dd868 BS |
668 | #if defined(CONFIG_USER_ONLY) |
669 | cpu_list_lock(); | |
670 | #endif | |
b7bca733 BR |
671 | cpu_index = cpu->cpu_index = cpu_get_free_index(&local_err); |
672 | if (local_err) { | |
673 | error_propagate(errp, local_err); | |
674 | #if defined(CONFIG_USER_ONLY) | |
675 | cpu_list_unlock(); | |
676 | #endif | |
677 | return; | |
5b6dd868 | 678 | } |
bdc44640 | 679 | QTAILQ_INSERT_TAIL(&cpus, cpu, node); |
5b6dd868 BS |
680 | #if defined(CONFIG_USER_ONLY) |
681 | cpu_list_unlock(); | |
682 | #endif | |
e0d47944 AF |
683 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
684 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu); | |
685 | } | |
b170fce3 AF |
686 | if (cc->vmsd != NULL) { |
687 | vmstate_register(NULL, cpu_index, cc->vmsd, cpu); | |
688 | } | |
ea041c0e FB |
689 | } |
690 | ||
94df27fd | 691 | #if defined(CONFIG_USER_ONLY) |
00b941e5 | 692 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
94df27fd PB |
693 | { |
694 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
695 | } | |
696 | #else | |
00b941e5 | 697 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1e7855a5 | 698 | { |
5232e4c7 PM |
699 | MemTxAttrs attrs; |
700 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
701 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
e8262a1b | 702 | if (phys != -1) { |
5232e4c7 | 703 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, |
29d8ec7b | 704 | phys | (pc & ~TARGET_PAGE_MASK)); |
e8262a1b | 705 | } |
1e7855a5 | 706 | } |
c27004ec | 707 | #endif |
d720b93d | 708 | |
c527ee8f | 709 | #if defined(CONFIG_USER_ONLY) |
75a34036 | 710 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
c527ee8f PB |
711 | |
712 | { | |
713 | } | |
714 | ||
3ee887e8 PM |
715 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
716 | int flags) | |
717 | { | |
718 | return -ENOSYS; | |
719 | } | |
720 | ||
721 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
722 | { | |
723 | } | |
724 | ||
75a34036 | 725 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
c527ee8f PB |
726 | int flags, CPUWatchpoint **watchpoint) |
727 | { | |
728 | return -ENOSYS; | |
729 | } | |
730 | #else | |
6658ffb8 | 731 | /* Add a watchpoint. */ |
75a34036 | 732 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 733 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 734 | { |
c0ce998e | 735 | CPUWatchpoint *wp; |
6658ffb8 | 736 | |
05068c0d | 737 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 738 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
739 | error_report("tried to set invalid watchpoint at %" |
740 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
741 | return -EINVAL; |
742 | } | |
7267c094 | 743 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
744 | |
745 | wp->vaddr = addr; | |
05068c0d | 746 | wp->len = len; |
a1d1bb31 AL |
747 | wp->flags = flags; |
748 | ||
2dc9f411 | 749 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
750 | if (flags & BP_GDB) { |
751 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
752 | } else { | |
753 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
754 | } | |
6658ffb8 | 755 | |
31b030d4 | 756 | tlb_flush_page(cpu, addr); |
a1d1bb31 AL |
757 | |
758 | if (watchpoint) | |
759 | *watchpoint = wp; | |
760 | return 0; | |
6658ffb8 PB |
761 | } |
762 | ||
a1d1bb31 | 763 | /* Remove a specific watchpoint. */ |
75a34036 | 764 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 765 | int flags) |
6658ffb8 | 766 | { |
a1d1bb31 | 767 | CPUWatchpoint *wp; |
6658ffb8 | 768 | |
ff4700b0 | 769 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 770 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 771 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 772 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
773 | return 0; |
774 | } | |
775 | } | |
a1d1bb31 | 776 | return -ENOENT; |
6658ffb8 PB |
777 | } |
778 | ||
a1d1bb31 | 779 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 780 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 781 | { |
ff4700b0 | 782 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 783 | |
31b030d4 | 784 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 785 | |
7267c094 | 786 | g_free(watchpoint); |
a1d1bb31 AL |
787 | } |
788 | ||
789 | /* Remove all matching watchpoints. */ | |
75a34036 | 790 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 791 | { |
c0ce998e | 792 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 793 | |
ff4700b0 | 794 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
795 | if (wp->flags & mask) { |
796 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
797 | } | |
c0ce998e | 798 | } |
7d03f82f | 799 | } |
05068c0d PM |
800 | |
801 | /* Return true if this watchpoint address matches the specified | |
802 | * access (ie the address range covered by the watchpoint overlaps | |
803 | * partially or completely with the address range covered by the | |
804 | * access). | |
805 | */ | |
806 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
807 | vaddr addr, | |
808 | vaddr len) | |
809 | { | |
810 | /* We know the lengths are non-zero, but a little caution is | |
811 | * required to avoid errors in the case where the range ends | |
812 | * exactly at the top of the address space and so addr + len | |
813 | * wraps round to zero. | |
814 | */ | |
815 | vaddr wpend = wp->vaddr + wp->len - 1; | |
816 | vaddr addrend = addr + len - 1; | |
817 | ||
818 | return !(addr > wpend || wp->vaddr > addrend); | |
819 | } | |
820 | ||
c527ee8f | 821 | #endif |
7d03f82f | 822 | |
a1d1bb31 | 823 | /* Add a breakpoint. */ |
b3310ab3 | 824 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
a1d1bb31 | 825 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 826 | { |
c0ce998e | 827 | CPUBreakpoint *bp; |
3b46e624 | 828 | |
7267c094 | 829 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 830 | |
a1d1bb31 AL |
831 | bp->pc = pc; |
832 | bp->flags = flags; | |
833 | ||
2dc9f411 | 834 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 835 | if (flags & BP_GDB) { |
f0c3c505 | 836 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
00b941e5 | 837 | } else { |
f0c3c505 | 838 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
00b941e5 | 839 | } |
3b46e624 | 840 | |
f0c3c505 | 841 | breakpoint_invalidate(cpu, pc); |
a1d1bb31 | 842 | |
00b941e5 | 843 | if (breakpoint) { |
a1d1bb31 | 844 | *breakpoint = bp; |
00b941e5 | 845 | } |
4c3a88a2 | 846 | return 0; |
4c3a88a2 FB |
847 | } |
848 | ||
a1d1bb31 | 849 | /* Remove a specific breakpoint. */ |
b3310ab3 | 850 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
a1d1bb31 | 851 | { |
a1d1bb31 AL |
852 | CPUBreakpoint *bp; |
853 | ||
f0c3c505 | 854 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
a1d1bb31 | 855 | if (bp->pc == pc && bp->flags == flags) { |
b3310ab3 | 856 | cpu_breakpoint_remove_by_ref(cpu, bp); |
a1d1bb31 AL |
857 | return 0; |
858 | } | |
7d03f82f | 859 | } |
a1d1bb31 | 860 | return -ENOENT; |
7d03f82f EI |
861 | } |
862 | ||
a1d1bb31 | 863 | /* Remove a specific breakpoint by reference. */ |
b3310ab3 | 864 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
4c3a88a2 | 865 | { |
f0c3c505 AF |
866 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
867 | ||
868 | breakpoint_invalidate(cpu, breakpoint->pc); | |
a1d1bb31 | 869 | |
7267c094 | 870 | g_free(breakpoint); |
a1d1bb31 AL |
871 | } |
872 | ||
873 | /* Remove all matching breakpoints. */ | |
b3310ab3 | 874 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 875 | { |
c0ce998e | 876 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 877 | |
f0c3c505 | 878 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
b3310ab3 AF |
879 | if (bp->flags & mask) { |
880 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
881 | } | |
c0ce998e | 882 | } |
4c3a88a2 FB |
883 | } |
884 | ||
c33a346e FB |
885 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
886 | CPU loop after each instruction */ | |
3825b28f | 887 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 888 | { |
ed2803da AF |
889 | if (cpu->singlestep_enabled != enabled) { |
890 | cpu->singlestep_enabled = enabled; | |
891 | if (kvm_enabled()) { | |
38e478ec | 892 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 893 | } else { |
ccbb4d44 | 894 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 895 | /* XXX: only flush what is necessary */ |
bbd77c18 | 896 | tb_flush(cpu); |
e22a25c9 | 897 | } |
c33a346e | 898 | } |
c33a346e FB |
899 | } |
900 | ||
a47dddd7 | 901 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
7501267e FB |
902 | { |
903 | va_list ap; | |
493ae1f0 | 904 | va_list ap2; |
7501267e FB |
905 | |
906 | va_start(ap, fmt); | |
493ae1f0 | 907 | va_copy(ap2, ap); |
7501267e FB |
908 | fprintf(stderr, "qemu: fatal: "); |
909 | vfprintf(stderr, fmt, ap); | |
910 | fprintf(stderr, "\n"); | |
878096ee | 911 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
013a2942 | 912 | if (qemu_log_separate()) { |
93fcfe39 AL |
913 | qemu_log("qemu: fatal: "); |
914 | qemu_log_vprintf(fmt, ap2); | |
915 | qemu_log("\n"); | |
a0762859 | 916 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 917 | qemu_log_flush(); |
93fcfe39 | 918 | qemu_log_close(); |
924edcae | 919 | } |
493ae1f0 | 920 | va_end(ap2); |
f9373291 | 921 | va_end(ap); |
7615936e | 922 | replay_finish(); |
fd052bf6 RV |
923 | #if defined(CONFIG_USER_ONLY) |
924 | { | |
925 | struct sigaction act; | |
926 | sigfillset(&act.sa_mask); | |
927 | act.sa_handler = SIG_DFL; | |
928 | sigaction(SIGABRT, &act, NULL); | |
929 | } | |
930 | #endif | |
7501267e FB |
931 | abort(); |
932 | } | |
933 | ||
0124311e | 934 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a | 935 | /* Called from RCU critical section */ |
041603fe PB |
936 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
937 | { | |
938 | RAMBlock *block; | |
939 | ||
43771539 | 940 | block = atomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 941 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 942 | return block; |
041603fe | 943 | } |
0dc3f44a | 944 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
9b8424d5 | 945 | if (addr - block->offset < block->max_length) { |
041603fe PB |
946 | goto found; |
947 | } | |
948 | } | |
949 | ||
950 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
951 | abort(); | |
952 | ||
953 | found: | |
43771539 PB |
954 | /* It is safe to write mru_block outside the iothread lock. This |
955 | * is what happens: | |
956 | * | |
957 | * mru_block = xxx | |
958 | * rcu_read_unlock() | |
959 | * xxx removed from list | |
960 | * rcu_read_lock() | |
961 | * read mru_block | |
962 | * mru_block = NULL; | |
963 | * call_rcu(reclaim_ramblock, xxx); | |
964 | * rcu_read_unlock() | |
965 | * | |
966 | * atomic_rcu_set is not needed here. The block was already published | |
967 | * when it was placed into the list. Here we're just making an extra | |
968 | * copy of the pointer. | |
969 | */ | |
041603fe PB |
970 | ram_list.mru_block = block; |
971 | return block; | |
972 | } | |
973 | ||
a2f4d5be | 974 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 975 | { |
9a13565d | 976 | CPUState *cpu; |
041603fe | 977 | ram_addr_t start1; |
a2f4d5be JQ |
978 | RAMBlock *block; |
979 | ram_addr_t end; | |
980 | ||
981 | end = TARGET_PAGE_ALIGN(start + length); | |
982 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 983 | |
0dc3f44a | 984 | rcu_read_lock(); |
041603fe PB |
985 | block = qemu_get_ram_block(start); |
986 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 987 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
988 | CPU_FOREACH(cpu) { |
989 | tlb_reset_dirty(cpu, start1, length); | |
990 | } | |
0dc3f44a | 991 | rcu_read_unlock(); |
d24981d3 JQ |
992 | } |
993 | ||
5579c7f3 | 994 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
995 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
996 | ram_addr_t length, | |
997 | unsigned client) | |
1ccde1cb | 998 | { |
5b82b703 | 999 | DirtyMemoryBlocks *blocks; |
03eebc9e | 1000 | unsigned long end, page; |
5b82b703 | 1001 | bool dirty = false; |
03eebc9e SH |
1002 | |
1003 | if (length == 0) { | |
1004 | return false; | |
1005 | } | |
f23db169 | 1006 | |
03eebc9e SH |
1007 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
1008 | page = start >> TARGET_PAGE_BITS; | |
5b82b703 SH |
1009 | |
1010 | rcu_read_lock(); | |
1011 | ||
1012 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1013 | ||
1014 | while (page < end) { | |
1015 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1016 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1017 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1018 | ||
1019 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1020 | offset, num); | |
1021 | page += num; | |
1022 | } | |
1023 | ||
1024 | rcu_read_unlock(); | |
03eebc9e SH |
1025 | |
1026 | if (dirty && tcg_enabled()) { | |
a2f4d5be | 1027 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1028 | } |
03eebc9e SH |
1029 | |
1030 | return dirty; | |
1ccde1cb FB |
1031 | } |
1032 | ||
79e2b9ae | 1033 | /* Called from RCU critical section */ |
bb0e627a | 1034 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
149f54b5 PB |
1035 | MemoryRegionSection *section, |
1036 | target_ulong vaddr, | |
1037 | hwaddr paddr, hwaddr xlat, | |
1038 | int prot, | |
1039 | target_ulong *address) | |
e5548617 | 1040 | { |
a8170e5e | 1041 | hwaddr iotlb; |
e5548617 BS |
1042 | CPUWatchpoint *wp; |
1043 | ||
cc5bea60 | 1044 | if (memory_region_is_ram(section->mr)) { |
e5548617 BS |
1045 | /* Normal RAM. */ |
1046 | iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) | |
149f54b5 | 1047 | + xlat; |
e5548617 | 1048 | if (!section->readonly) { |
b41aac4f | 1049 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 1050 | } else { |
b41aac4f | 1051 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
1052 | } |
1053 | } else { | |
0b8e2c10 PM |
1054 | AddressSpaceDispatch *d; |
1055 | ||
1056 | d = atomic_rcu_read(§ion->address_space->dispatch); | |
1057 | iotlb = section - d->map.sections; | |
149f54b5 | 1058 | iotlb += xlat; |
e5548617 BS |
1059 | } |
1060 | ||
1061 | /* Make accesses to pages with watchpoints go via the | |
1062 | watchpoint trap routines. */ | |
ff4700b0 | 1063 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1064 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
e5548617 BS |
1065 | /* Avoid trapping reads of pages with a write breakpoint. */ |
1066 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 1067 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
1068 | *address |= TLB_MMIO; |
1069 | break; | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | return iotlb; | |
1075 | } | |
9fa3e853 FB |
1076 | #endif /* defined(CONFIG_USER_ONLY) */ |
1077 | ||
e2eef170 | 1078 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 1079 | |
c227f099 | 1080 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1081 | uint16_t section); |
acc9d80b | 1082 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base); |
54688b1e | 1083 | |
a2b257d6 IM |
1084 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align) = |
1085 | qemu_anon_ram_alloc; | |
91138037 MA |
1086 | |
1087 | /* | |
1088 | * Set a custom physical guest memory alloator. | |
1089 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1090 | * get rid of it eventually. | |
1091 | */ | |
a2b257d6 | 1092 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)) |
91138037 MA |
1093 | { |
1094 | phys_mem_alloc = alloc; | |
1095 | } | |
1096 | ||
53cb28cb MA |
1097 | static uint16_t phys_section_add(PhysPageMap *map, |
1098 | MemoryRegionSection *section) | |
5312bd8b | 1099 | { |
68f3f65b PB |
1100 | /* The physical section number is ORed with a page-aligned |
1101 | * pointer to produce the iotlb entries. Thus it should | |
1102 | * never overflow into the page-aligned value. | |
1103 | */ | |
53cb28cb | 1104 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1105 | |
53cb28cb MA |
1106 | if (map->sections_nb == map->sections_nb_alloc) { |
1107 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1108 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1109 | map->sections_nb_alloc); | |
5312bd8b | 1110 | } |
53cb28cb | 1111 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1112 | memory_region_ref(section->mr); |
53cb28cb | 1113 | return map->sections_nb++; |
5312bd8b AK |
1114 | } |
1115 | ||
058bc4b5 PB |
1116 | static void phys_section_destroy(MemoryRegion *mr) |
1117 | { | |
55b4e80b DS |
1118 | bool have_sub_page = mr->subpage; |
1119 | ||
dfde4e6e PB |
1120 | memory_region_unref(mr); |
1121 | ||
55b4e80b | 1122 | if (have_sub_page) { |
058bc4b5 | 1123 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1124 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1125 | g_free(subpage); |
1126 | } | |
1127 | } | |
1128 | ||
6092666e | 1129 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1130 | { |
9affd6fc PB |
1131 | while (map->sections_nb > 0) { |
1132 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1133 | phys_section_destroy(section->mr); |
1134 | } | |
9affd6fc PB |
1135 | g_free(map->sections); |
1136 | g_free(map->nodes); | |
5312bd8b AK |
1137 | } |
1138 | ||
ac1970fb | 1139 | static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section) |
0f0cb164 AK |
1140 | { |
1141 | subpage_t *subpage; | |
a8170e5e | 1142 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1143 | & TARGET_PAGE_MASK; |
97115a8d | 1144 | MemoryRegionSection *existing = phys_page_find(d->phys_map, base, |
53cb28cb | 1145 | d->map.nodes, d->map.sections); |
0f0cb164 AK |
1146 | MemoryRegionSection subsection = { |
1147 | .offset_within_address_space = base, | |
052e87b0 | 1148 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1149 | }; |
a8170e5e | 1150 | hwaddr start, end; |
0f0cb164 | 1151 | |
f3705d53 | 1152 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1153 | |
f3705d53 | 1154 | if (!(existing->mr->subpage)) { |
acc9d80b | 1155 | subpage = subpage_init(d->as, base); |
3be91e86 | 1156 | subsection.address_space = d->as; |
0f0cb164 | 1157 | subsection.mr = &subpage->iomem; |
ac1970fb | 1158 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1159 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1160 | } else { |
f3705d53 | 1161 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1162 | } |
1163 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1164 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1165 | subpage_register(subpage, start, end, |
1166 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1167 | } |
1168 | ||
1169 | ||
052e87b0 PB |
1170 | static void register_multipage(AddressSpaceDispatch *d, |
1171 | MemoryRegionSection *section) | |
33417e70 | 1172 | { |
a8170e5e | 1173 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1174 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1175 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1176 | TARGET_PAGE_BITS)); | |
dd81124b | 1177 | |
733d5ef5 PB |
1178 | assert(num_pages); |
1179 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1180 | } |
1181 | ||
ac1970fb | 1182 | static void mem_add(MemoryListener *listener, MemoryRegionSection *section) |
0f0cb164 | 1183 | { |
89ae337a | 1184 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
00752703 | 1185 | AddressSpaceDispatch *d = as->next_dispatch; |
99b9cc06 | 1186 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 1187 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1188 | |
733d5ef5 PB |
1189 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
1190 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1191 | - now.offset_within_address_space; | |
1192 | ||
052e87b0 | 1193 | now.size = int128_min(int128_make64(left), now.size); |
ac1970fb | 1194 | register_subpage(d, &now); |
733d5ef5 | 1195 | } else { |
052e87b0 | 1196 | now.size = int128_zero(); |
733d5ef5 | 1197 | } |
052e87b0 PB |
1198 | while (int128_ne(remain.size, now.size)) { |
1199 | remain.size = int128_sub(remain.size, now.size); | |
1200 | remain.offset_within_address_space += int128_get64(now.size); | |
1201 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 1202 | now = remain; |
052e87b0 | 1203 | if (int128_lt(remain.size, page_size)) { |
733d5ef5 | 1204 | register_subpage(d, &now); |
88266249 | 1205 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
052e87b0 | 1206 | now.size = page_size; |
ac1970fb | 1207 | register_subpage(d, &now); |
69b67646 | 1208 | } else { |
052e87b0 | 1209 | now.size = int128_and(now.size, int128_neg(page_size)); |
ac1970fb | 1210 | register_multipage(d, &now); |
69b67646 | 1211 | } |
0f0cb164 AK |
1212 | } |
1213 | } | |
1214 | ||
62a2744c SY |
1215 | void qemu_flush_coalesced_mmio_buffer(void) |
1216 | { | |
1217 | if (kvm_enabled()) | |
1218 | kvm_flush_coalesced_mmio_buffer(); | |
1219 | } | |
1220 | ||
b2a8658e UD |
1221 | void qemu_mutex_lock_ramlist(void) |
1222 | { | |
1223 | qemu_mutex_lock(&ram_list.mutex); | |
1224 | } | |
1225 | ||
1226 | void qemu_mutex_unlock_ramlist(void) | |
1227 | { | |
1228 | qemu_mutex_unlock(&ram_list.mutex); | |
1229 | } | |
1230 | ||
e1e84ba0 | 1231 | #ifdef __linux__ |
04b16653 AW |
1232 | static void *file_ram_alloc(RAMBlock *block, |
1233 | ram_addr_t memory, | |
7f56e740 PB |
1234 | const char *path, |
1235 | Error **errp) | |
c902760f | 1236 | { |
fd97fd44 | 1237 | bool unlink_on_error = false; |
c902760f | 1238 | char *filename; |
8ca761f6 PF |
1239 | char *sanitized_name; |
1240 | char *c; | |
794e8f30 | 1241 | void *area; |
c902760f | 1242 | int fd; |
e1fb6471 | 1243 | int64_t page_size; |
c902760f MT |
1244 | |
1245 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
7f56e740 PB |
1246 | error_setg(errp, |
1247 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
fd97fd44 | 1248 | return NULL; |
c902760f MT |
1249 | } |
1250 | ||
fd97fd44 MA |
1251 | for (;;) { |
1252 | fd = open(path, O_RDWR); | |
1253 | if (fd >= 0) { | |
1254 | /* @path names an existing file, use it */ | |
1255 | break; | |
8d31d6b6 | 1256 | } |
fd97fd44 MA |
1257 | if (errno == ENOENT) { |
1258 | /* @path names a file that doesn't exist, create it */ | |
1259 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1260 | if (fd >= 0) { | |
1261 | unlink_on_error = true; | |
1262 | break; | |
1263 | } | |
1264 | } else if (errno == EISDIR) { | |
1265 | /* @path names a directory, create a file there */ | |
1266 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
1267 | sanitized_name = g_strdup(memory_region_name(block->mr)); | |
1268 | for (c = sanitized_name; *c != '\0'; c++) { | |
1269 | if (*c == '/') { | |
1270 | *c = '_'; | |
1271 | } | |
1272 | } | |
8ca761f6 | 1273 | |
fd97fd44 MA |
1274 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1275 | sanitized_name); | |
1276 | g_free(sanitized_name); | |
8d31d6b6 | 1277 | |
fd97fd44 MA |
1278 | fd = mkstemp(filename); |
1279 | if (fd >= 0) { | |
1280 | unlink(filename); | |
1281 | g_free(filename); | |
1282 | break; | |
1283 | } | |
1284 | g_free(filename); | |
8d31d6b6 | 1285 | } |
fd97fd44 MA |
1286 | if (errno != EEXIST && errno != EINTR) { |
1287 | error_setg_errno(errp, errno, | |
1288 | "can't open backing store %s for guest RAM", | |
1289 | path); | |
1290 | goto error; | |
1291 | } | |
1292 | /* | |
1293 | * Try again on EINTR and EEXIST. The latter happens when | |
1294 | * something else creates the file between our two open(). | |
1295 | */ | |
8d31d6b6 | 1296 | } |
c902760f | 1297 | |
e1fb6471 MA |
1298 | page_size = qemu_fd_getpagesize(fd); |
1299 | block->mr->align = page_size; | |
fd97fd44 | 1300 | |
e1fb6471 | 1301 | if (memory < page_size) { |
fd97fd44 MA |
1302 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
1303 | "or larger than page size 0x%" PRIx64, | |
e1fb6471 | 1304 | memory, page_size); |
f9a49dfa | 1305 | goto error; |
c902760f | 1306 | } |
c902760f | 1307 | |
e1fb6471 | 1308 | memory = ROUND_UP(memory, page_size); |
c902760f MT |
1309 | |
1310 | /* | |
1311 | * ftruncate is not supported by hugetlbfs in older | |
1312 | * hosts, so don't bother bailing out on errors. | |
1313 | * If anything goes wrong with it under other filesystems, | |
1314 | * mmap will fail. | |
1315 | */ | |
7f56e740 | 1316 | if (ftruncate(fd, memory)) { |
9742bf26 | 1317 | perror("ftruncate"); |
7f56e740 | 1318 | } |
c902760f | 1319 | |
e1fb6471 | 1320 | area = qemu_ram_mmap(fd, memory, page_size, block->flags & RAM_SHARED); |
c902760f | 1321 | if (area == MAP_FAILED) { |
7f56e740 | 1322 | error_setg_errno(errp, errno, |
fd97fd44 | 1323 | "unable to map backing store for guest RAM"); |
9742bf26 | 1324 | close(fd); |
f9a49dfa | 1325 | goto error; |
c902760f | 1326 | } |
ef36fa14 MT |
1327 | |
1328 | if (mem_prealloc) { | |
38183310 | 1329 | os_mem_prealloc(fd, area, memory); |
ef36fa14 MT |
1330 | } |
1331 | ||
04b16653 | 1332 | block->fd = fd; |
c902760f | 1333 | return area; |
f9a49dfa MT |
1334 | |
1335 | error: | |
fd97fd44 MA |
1336 | if (unlink_on_error) { |
1337 | unlink(path); | |
1338 | } | |
1339 | close(fd); | |
f9a49dfa | 1340 | return NULL; |
c902760f MT |
1341 | } |
1342 | #endif | |
1343 | ||
0dc3f44a | 1344 | /* Called with the ramlist lock held. */ |
d17b5288 | 1345 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1346 | { |
1347 | RAMBlock *block, *next_block; | |
3e837b2c | 1348 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1349 | |
49cd9ac6 SH |
1350 | assert(size != 0); /* it would hand out same offset multiple times */ |
1351 | ||
0dc3f44a | 1352 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1353 | return 0; |
0d53d9fe | 1354 | } |
04b16653 | 1355 | |
0dc3f44a | 1356 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
f15fbc4b | 1357 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 | 1358 | |
62be4e3a | 1359 | end = block->offset + block->max_length; |
04b16653 | 1360 | |
0dc3f44a | 1361 | QLIST_FOREACH_RCU(next_block, &ram_list.blocks, next) { |
04b16653 AW |
1362 | if (next_block->offset >= end) { |
1363 | next = MIN(next, next_block->offset); | |
1364 | } | |
1365 | } | |
1366 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 1367 | offset = end; |
04b16653 AW |
1368 | mingap = next - end; |
1369 | } | |
1370 | } | |
3e837b2c AW |
1371 | |
1372 | if (offset == RAM_ADDR_MAX) { | |
1373 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1374 | (uint64_t)size); | |
1375 | abort(); | |
1376 | } | |
1377 | ||
04b16653 AW |
1378 | return offset; |
1379 | } | |
1380 | ||
652d7ec2 | 1381 | ram_addr_t last_ram_offset(void) |
d17b5288 AW |
1382 | { |
1383 | RAMBlock *block; | |
1384 | ram_addr_t last = 0; | |
1385 | ||
0dc3f44a MD |
1386 | rcu_read_lock(); |
1387 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { | |
62be4e3a | 1388 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1389 | } |
0dc3f44a | 1390 | rcu_read_unlock(); |
d17b5288 AW |
1391 | return last; |
1392 | } | |
1393 | ||
ddb97f1d JB |
1394 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1395 | { | |
1396 | int ret; | |
ddb97f1d JB |
1397 | |
1398 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1399 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1400 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1401 | if (ret) { | |
1402 | perror("qemu_madvise"); | |
1403 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1404 | "but dump_guest_core=off specified\n"); | |
1405 | } | |
1406 | } | |
1407 | } | |
1408 | ||
0dc3f44a MD |
1409 | /* Called within an RCU critical section, or while the ramlist lock |
1410 | * is held. | |
1411 | */ | |
20cfe881 | 1412 | static RAMBlock *find_ram_block(ram_addr_t addr) |
84b89d78 | 1413 | { |
20cfe881 | 1414 | RAMBlock *block; |
84b89d78 | 1415 | |
0dc3f44a | 1416 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
c5705a77 | 1417 | if (block->offset == addr) { |
20cfe881 | 1418 | return block; |
c5705a77 AK |
1419 | } |
1420 | } | |
20cfe881 HT |
1421 | |
1422 | return NULL; | |
1423 | } | |
1424 | ||
422148d3 DDAG |
1425 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1426 | { | |
1427 | return rb->idstr; | |
1428 | } | |
1429 | ||
ae3a7047 | 1430 | /* Called with iothread lock held. */ |
20cfe881 HT |
1431 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
1432 | { | |
ae3a7047 | 1433 | RAMBlock *new_block, *block; |
20cfe881 | 1434 | |
0dc3f44a | 1435 | rcu_read_lock(); |
ae3a7047 | 1436 | new_block = find_ram_block(addr); |
c5705a77 AK |
1437 | assert(new_block); |
1438 | assert(!new_block->idstr[0]); | |
84b89d78 | 1439 | |
09e5ab63 AL |
1440 | if (dev) { |
1441 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1442 | if (id) { |
1443 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1444 | g_free(id); |
84b89d78 CM |
1445 | } |
1446 | } | |
1447 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1448 | ||
0dc3f44a | 1449 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
c5705a77 | 1450 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
84b89d78 CM |
1451 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1452 | new_block->idstr); | |
1453 | abort(); | |
1454 | } | |
1455 | } | |
0dc3f44a | 1456 | rcu_read_unlock(); |
c5705a77 AK |
1457 | } |
1458 | ||
ae3a7047 | 1459 | /* Called with iothread lock held. */ |
20cfe881 HT |
1460 | void qemu_ram_unset_idstr(ram_addr_t addr) |
1461 | { | |
ae3a7047 | 1462 | RAMBlock *block; |
20cfe881 | 1463 | |
ae3a7047 MD |
1464 | /* FIXME: arch_init.c assumes that this is not called throughout |
1465 | * migration. Ignore the problem since hot-unplug during migration | |
1466 | * does not work anyway. | |
1467 | */ | |
1468 | ||
0dc3f44a | 1469 | rcu_read_lock(); |
ae3a7047 | 1470 | block = find_ram_block(addr); |
20cfe881 HT |
1471 | if (block) { |
1472 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1473 | } | |
0dc3f44a | 1474 | rcu_read_unlock(); |
20cfe881 HT |
1475 | } |
1476 | ||
8490fc78 LC |
1477 | static int memory_try_enable_merging(void *addr, size_t len) |
1478 | { | |
75cc7f01 | 1479 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1480 | /* disabled by the user */ |
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1485 | } | |
1486 | ||
62be4e3a MT |
1487 | /* Only legal before guest might have detected the memory size: e.g. on |
1488 | * incoming migration, or right after reset. | |
1489 | * | |
1490 | * As memory core doesn't know how is memory accessed, it is up to | |
1491 | * resize callback to update device state and/or add assertions to detect | |
1492 | * misuse, if necessary. | |
1493 | */ | |
1494 | int qemu_ram_resize(ram_addr_t base, ram_addr_t newsize, Error **errp) | |
1495 | { | |
1496 | RAMBlock *block = find_ram_block(base); | |
1497 | ||
1498 | assert(block); | |
1499 | ||
4ed023ce | 1500 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1501 | |
62be4e3a MT |
1502 | if (block->used_length == newsize) { |
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1507 | error_setg_errno(errp, EINVAL, | |
1508 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
1509 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
1510 | newsize, block->used_length); | |
1511 | return -EINVAL; | |
1512 | } | |
1513 | ||
1514 | if (block->max_length < newsize) { | |
1515 | error_setg_errno(errp, EINVAL, | |
1516 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
1517 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
1518 | newsize, block->max_length); | |
1519 | return -EINVAL; | |
1520 | } | |
1521 | ||
1522 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1523 | block->used_length = newsize; | |
58d2707e PB |
1524 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1525 | DIRTY_CLIENTS_ALL); | |
62be4e3a MT |
1526 | memory_region_set_size(block->mr, newsize); |
1527 | if (block->resized) { | |
1528 | block->resized(block->idstr, newsize, block->host); | |
1529 | } | |
1530 | return 0; | |
1531 | } | |
1532 | ||
5b82b703 SH |
1533 | /* Called with ram_list.mutex held */ |
1534 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1535 | ram_addr_t new_ram_size) | |
1536 | { | |
1537 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1538 | DIRTY_MEMORY_BLOCK_SIZE); | |
1539 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1540 | DIRTY_MEMORY_BLOCK_SIZE); | |
1541 | int i; | |
1542 | ||
1543 | /* Only need to extend if block count increased */ | |
1544 | if (new_num_blocks <= old_num_blocks) { | |
1545 | return; | |
1546 | } | |
1547 | ||
1548 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1549 | DirtyMemoryBlocks *old_blocks; | |
1550 | DirtyMemoryBlocks *new_blocks; | |
1551 | int j; | |
1552 | ||
1553 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
1554 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
1555 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1556 | ||
1557 | if (old_num_blocks) { | |
1558 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1559 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1560 | } | |
1561 | ||
1562 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1563 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1564 | } | |
1565 | ||
1566 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
1567 | ||
1568 | if (old_blocks) { | |
1569 | g_free_rcu(old_blocks, rcu); | |
1570 | } | |
1571 | } | |
1572 | } | |
1573 | ||
528f46af | 1574 | static void ram_block_add(RAMBlock *new_block, Error **errp) |
c5705a77 | 1575 | { |
e1c57ab8 | 1576 | RAMBlock *block; |
0d53d9fe | 1577 | RAMBlock *last_block = NULL; |
2152f5ca | 1578 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 1579 | Error *err = NULL; |
2152f5ca JQ |
1580 | |
1581 | old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS; | |
c5705a77 | 1582 | |
b2a8658e | 1583 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 1584 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
1585 | |
1586 | if (!new_block->host) { | |
1587 | if (xen_enabled()) { | |
9b8424d5 | 1588 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
1589 | new_block->mr, &err); |
1590 | if (err) { | |
1591 | error_propagate(errp, err); | |
1592 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1593 | return; |
37aa7a0e | 1594 | } |
e1c57ab8 | 1595 | } else { |
9b8424d5 | 1596 | new_block->host = phys_mem_alloc(new_block->max_length, |
a2b257d6 | 1597 | &new_block->mr->align); |
39228250 | 1598 | if (!new_block->host) { |
ef701d7b HT |
1599 | error_setg_errno(errp, errno, |
1600 | "cannot set up guest memory '%s'", | |
1601 | memory_region_name(new_block->mr)); | |
1602 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1603 | return; |
39228250 | 1604 | } |
9b8424d5 | 1605 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 1606 | } |
c902760f | 1607 | } |
94a6b54f | 1608 | |
dd631697 LZ |
1609 | new_ram_size = MAX(old_ram_size, |
1610 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1611 | if (new_ram_size > old_ram_size) { | |
1612 | migration_bitmap_extend(old_ram_size, new_ram_size); | |
5b82b703 | 1613 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 1614 | } |
0d53d9fe MD |
1615 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
1616 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1617 | * tail, so save the last element in last_block. | |
1618 | */ | |
0dc3f44a | 1619 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
0d53d9fe | 1620 | last_block = block; |
9b8424d5 | 1621 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
1622 | break; |
1623 | } | |
1624 | } | |
1625 | if (block) { | |
0dc3f44a | 1626 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 1627 | } else if (last_block) { |
0dc3f44a | 1628 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 1629 | } else { /* list is empty */ |
0dc3f44a | 1630 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 1631 | } |
0d6d3c87 | 1632 | ram_list.mru_block = NULL; |
94a6b54f | 1633 | |
0dc3f44a MD |
1634 | /* Write list before version */ |
1635 | smp_wmb(); | |
f798b07f | 1636 | ram_list.version++; |
b2a8658e | 1637 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1638 | |
9b8424d5 | 1639 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
1640 | new_block->used_length, |
1641 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 1642 | |
a904c911 PB |
1643 | if (new_block->host) { |
1644 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1645 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
1646 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); | |
1647 | if (kvm_enabled()) { | |
1648 | kvm_setup_guest_memory(new_block->host, new_block->max_length); | |
1649 | } | |
e1c57ab8 | 1650 | } |
94a6b54f | 1651 | } |
e9a1ab19 | 1652 | |
0b183fc8 | 1653 | #ifdef __linux__ |
528f46af FZ |
1654 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, |
1655 | bool share, const char *mem_path, | |
1656 | Error **errp) | |
e1c57ab8 PB |
1657 | { |
1658 | RAMBlock *new_block; | |
ef701d7b | 1659 | Error *local_err = NULL; |
e1c57ab8 PB |
1660 | |
1661 | if (xen_enabled()) { | |
7f56e740 | 1662 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 1663 | return NULL; |
e1c57ab8 PB |
1664 | } |
1665 | ||
1666 | if (phys_mem_alloc != qemu_anon_ram_alloc) { | |
1667 | /* | |
1668 | * file_ram_alloc() needs to allocate just like | |
1669 | * phys_mem_alloc, but we haven't bothered to provide | |
1670 | * a hook there. | |
1671 | */ | |
7f56e740 PB |
1672 | error_setg(errp, |
1673 | "-mem-path not supported with this accelerator"); | |
528f46af | 1674 | return NULL; |
e1c57ab8 PB |
1675 | } |
1676 | ||
4ed023ce | 1677 | size = HOST_PAGE_ALIGN(size); |
e1c57ab8 PB |
1678 | new_block = g_malloc0(sizeof(*new_block)); |
1679 | new_block->mr = mr; | |
9b8424d5 MT |
1680 | new_block->used_length = size; |
1681 | new_block->max_length = size; | |
dbcb8981 | 1682 | new_block->flags = share ? RAM_SHARED : 0; |
7f56e740 PB |
1683 | new_block->host = file_ram_alloc(new_block, size, |
1684 | mem_path, errp); | |
1685 | if (!new_block->host) { | |
1686 | g_free(new_block); | |
528f46af | 1687 | return NULL; |
7f56e740 PB |
1688 | } |
1689 | ||
528f46af | 1690 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
1691 | if (local_err) { |
1692 | g_free(new_block); | |
1693 | error_propagate(errp, local_err); | |
528f46af | 1694 | return NULL; |
ef701d7b | 1695 | } |
528f46af | 1696 | return new_block; |
e1c57ab8 | 1697 | } |
0b183fc8 | 1698 | #endif |
e1c57ab8 | 1699 | |
62be4e3a | 1700 | static |
528f46af FZ |
1701 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
1702 | void (*resized)(const char*, | |
1703 | uint64_t length, | |
1704 | void *host), | |
1705 | void *host, bool resizeable, | |
1706 | MemoryRegion *mr, Error **errp) | |
e1c57ab8 PB |
1707 | { |
1708 | RAMBlock *new_block; | |
ef701d7b | 1709 | Error *local_err = NULL; |
e1c57ab8 | 1710 | |
4ed023ce DDAG |
1711 | size = HOST_PAGE_ALIGN(size); |
1712 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
1713 | new_block = g_malloc0(sizeof(*new_block)); |
1714 | new_block->mr = mr; | |
62be4e3a | 1715 | new_block->resized = resized; |
9b8424d5 MT |
1716 | new_block->used_length = size; |
1717 | new_block->max_length = max_size; | |
62be4e3a | 1718 | assert(max_size >= size); |
e1c57ab8 PB |
1719 | new_block->fd = -1; |
1720 | new_block->host = host; | |
1721 | if (host) { | |
7bd4f430 | 1722 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 1723 | } |
62be4e3a MT |
1724 | if (resizeable) { |
1725 | new_block->flags |= RAM_RESIZEABLE; | |
1726 | } | |
528f46af | 1727 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
1728 | if (local_err) { |
1729 | g_free(new_block); | |
1730 | error_propagate(errp, local_err); | |
528f46af | 1731 | return NULL; |
ef701d7b | 1732 | } |
528f46af | 1733 | return new_block; |
e1c57ab8 PB |
1734 | } |
1735 | ||
528f46af | 1736 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
1737 | MemoryRegion *mr, Error **errp) |
1738 | { | |
1739 | return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); | |
1740 | } | |
1741 | ||
528f46af | 1742 | RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) |
6977dfe6 | 1743 | { |
62be4e3a MT |
1744 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); |
1745 | } | |
1746 | ||
528f46af | 1747 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
1748 | void (*resized)(const char*, |
1749 | uint64_t length, | |
1750 | void *host), | |
1751 | MemoryRegion *mr, Error **errp) | |
1752 | { | |
1753 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); | |
6977dfe6 YT |
1754 | } |
1755 | ||
43771539 PB |
1756 | static void reclaim_ramblock(RAMBlock *block) |
1757 | { | |
1758 | if (block->flags & RAM_PREALLOC) { | |
1759 | ; | |
1760 | } else if (xen_enabled()) { | |
1761 | xen_invalidate_map_cache_entry(block->host); | |
1762 | #ifndef _WIN32 | |
1763 | } else if (block->fd >= 0) { | |
2f3a2bb1 | 1764 | qemu_ram_munmap(block->host, block->max_length); |
43771539 PB |
1765 | close(block->fd); |
1766 | #endif | |
1767 | } else { | |
1768 | qemu_anon_ram_free(block->host, block->max_length); | |
1769 | } | |
1770 | g_free(block); | |
1771 | } | |
1772 | ||
f1060c55 | 1773 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 1774 | { |
b2a8658e | 1775 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
1776 | QLIST_REMOVE_RCU(block, next); |
1777 | ram_list.mru_block = NULL; | |
1778 | /* Write list before version */ | |
1779 | smp_wmb(); | |
1780 | ram_list.version++; | |
1781 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 1782 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
1783 | } |
1784 | ||
cd19cfa2 HY |
1785 | #ifndef _WIN32 |
1786 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
1787 | { | |
1788 | RAMBlock *block; | |
1789 | ram_addr_t offset; | |
1790 | int flags; | |
1791 | void *area, *vaddr; | |
1792 | ||
0dc3f44a | 1793 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
cd19cfa2 | 1794 | offset = addr - block->offset; |
9b8424d5 | 1795 | if (offset < block->max_length) { |
1240be24 | 1796 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 1797 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 1798 | ; |
dfeaf2ab MA |
1799 | } else if (xen_enabled()) { |
1800 | abort(); | |
cd19cfa2 HY |
1801 | } else { |
1802 | flags = MAP_FIXED; | |
3435f395 | 1803 | if (block->fd >= 0) { |
dbcb8981 PB |
1804 | flags |= (block->flags & RAM_SHARED ? |
1805 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
1806 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
1807 | flags, block->fd, offset); | |
cd19cfa2 | 1808 | } else { |
2eb9fbaa MA |
1809 | /* |
1810 | * Remap needs to match alloc. Accelerators that | |
1811 | * set phys_mem_alloc never remap. If they did, | |
1812 | * we'd need a remap hook here. | |
1813 | */ | |
1814 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
1815 | ||
cd19cfa2 HY |
1816 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
1817 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
1818 | flags, -1, 0); | |
cd19cfa2 HY |
1819 | } |
1820 | if (area != vaddr) { | |
f15fbc4b AP |
1821 | fprintf(stderr, "Could not remap addr: " |
1822 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
1823 | length, addr); |
1824 | exit(1); | |
1825 | } | |
8490fc78 | 1826 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 1827 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 1828 | } |
cd19cfa2 HY |
1829 | } |
1830 | } | |
1831 | } | |
1832 | #endif /* !_WIN32 */ | |
1833 | ||
a35ba7be PB |
1834 | int qemu_get_ram_fd(ram_addr_t addr) |
1835 | { | |
ae3a7047 MD |
1836 | RAMBlock *block; |
1837 | int fd; | |
a35ba7be | 1838 | |
0dc3f44a | 1839 | rcu_read_lock(); |
ae3a7047 MD |
1840 | block = qemu_get_ram_block(addr); |
1841 | fd = block->fd; | |
0dc3f44a | 1842 | rcu_read_unlock(); |
ae3a7047 | 1843 | return fd; |
a35ba7be PB |
1844 | } |
1845 | ||
56a571d9 TM |
1846 | void qemu_set_ram_fd(ram_addr_t addr, int fd) |
1847 | { | |
1848 | RAMBlock *block; | |
1849 | ||
1850 | rcu_read_lock(); | |
1851 | block = qemu_get_ram_block(addr); | |
1852 | block->fd = fd; | |
1853 | rcu_read_unlock(); | |
1854 | } | |
1855 | ||
3fd74b84 DM |
1856 | void *qemu_get_ram_block_host_ptr(ram_addr_t addr) |
1857 | { | |
ae3a7047 MD |
1858 | RAMBlock *block; |
1859 | void *ptr; | |
3fd74b84 | 1860 | |
0dc3f44a | 1861 | rcu_read_lock(); |
ae3a7047 MD |
1862 | block = qemu_get_ram_block(addr); |
1863 | ptr = ramblock_ptr(block, 0); | |
0dc3f44a | 1864 | rcu_read_unlock(); |
ae3a7047 | 1865 | return ptr; |
3fd74b84 DM |
1866 | } |
1867 | ||
1b5ec234 | 1868 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
1869 | * This should not be used for general purpose DMA. Use address_space_map |
1870 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
1871 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 1872 | * |
49b24afc | 1873 | * Called within RCU critical section. |
1b5ec234 | 1874 | */ |
3655cb9c | 1875 | void *qemu_get_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 1876 | { |
3655cb9c GA |
1877 | RAMBlock *block = ram_block; |
1878 | ||
1879 | if (block == NULL) { | |
1880 | block = qemu_get_ram_block(addr); | |
1881 | } | |
ae3a7047 MD |
1882 | |
1883 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
1884 | /* We need to check if the requested address is in the RAM |
1885 | * because we don't want to map the entire memory in QEMU. | |
1886 | * In that case just map until the end of the page. | |
1887 | */ | |
1888 | if (block->offset == 0) { | |
49b24afc | 1889 | return xen_map_cache(addr, 0, 0); |
0d6d3c87 | 1890 | } |
ae3a7047 MD |
1891 | |
1892 | block->host = xen_map_cache(block->offset, block->max_length, 1); | |
0d6d3c87 | 1893 | } |
49b24afc | 1894 | return ramblock_ptr(block, addr - block->offset); |
dc828ca1 PB |
1895 | } |
1896 | ||
38bee5dc | 1897 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
ae3a7047 | 1898 | * but takes a size argument. |
0dc3f44a | 1899 | * |
e81bcda5 | 1900 | * Called within RCU critical section. |
ae3a7047 | 1901 | */ |
3655cb9c GA |
1902 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
1903 | hwaddr *size) | |
38bee5dc | 1904 | { |
3655cb9c | 1905 | RAMBlock *block = ram_block; |
e81bcda5 | 1906 | ram_addr_t offset_inside_block; |
8ab934f9 SS |
1907 | if (*size == 0) { |
1908 | return NULL; | |
1909 | } | |
e81bcda5 | 1910 | |
3655cb9c GA |
1911 | if (block == NULL) { |
1912 | block = qemu_get_ram_block(addr); | |
1913 | } | |
e81bcda5 PB |
1914 | offset_inside_block = addr - block->offset; |
1915 | *size = MIN(*size, block->max_length - offset_inside_block); | |
1916 | ||
1917 | if (xen_enabled() && block->host == NULL) { | |
1918 | /* We need to check if the requested address is in the RAM | |
1919 | * because we don't want to map the entire memory in QEMU. | |
1920 | * In that case just map the requested area. | |
1921 | */ | |
1922 | if (block->offset == 0) { | |
1923 | return xen_map_cache(addr, *size, 1); | |
38bee5dc SS |
1924 | } |
1925 | ||
e81bcda5 | 1926 | block->host = xen_map_cache(block->offset, block->max_length, 1); |
38bee5dc | 1927 | } |
e81bcda5 PB |
1928 | |
1929 | return ramblock_ptr(block, offset_inside_block); | |
38bee5dc SS |
1930 | } |
1931 | ||
422148d3 DDAG |
1932 | /* |
1933 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
1934 | * in that RAMBlock. | |
1935 | * | |
1936 | * ptr: Host pointer to look up | |
1937 | * round_offset: If true round the result offset down to a page boundary | |
1938 | * *ram_addr: set to result ram_addr | |
1939 | * *offset: set to result offset within the RAMBlock | |
1940 | * | |
1941 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
1942 | * |
1943 | * By the time this function returns, the returned pointer is not protected | |
1944 | * by RCU anymore. If the caller is not within an RCU critical section and | |
1945 | * does not hold the iothread lock, it must have other means of protecting the | |
1946 | * pointer, such as a reference to the region that includes the incoming | |
1947 | * ram_addr_t. | |
1948 | */ | |
422148d3 DDAG |
1949 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
1950 | ram_addr_t *ram_addr, | |
1951 | ram_addr_t *offset) | |
5579c7f3 | 1952 | { |
94a6b54f PB |
1953 | RAMBlock *block; |
1954 | uint8_t *host = ptr; | |
1955 | ||
868bb33f | 1956 | if (xen_enabled()) { |
0dc3f44a | 1957 | rcu_read_lock(); |
e41d7c69 | 1958 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
422148d3 DDAG |
1959 | block = qemu_get_ram_block(*ram_addr); |
1960 | if (block) { | |
1961 | *offset = (host - block->host); | |
1962 | } | |
0dc3f44a | 1963 | rcu_read_unlock(); |
422148d3 | 1964 | return block; |
712c2b41 SS |
1965 | } |
1966 | ||
0dc3f44a MD |
1967 | rcu_read_lock(); |
1968 | block = atomic_rcu_read(&ram_list.mru_block); | |
9b8424d5 | 1969 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
1970 | goto found; |
1971 | } | |
1972 | ||
0dc3f44a | 1973 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { |
432d268c JN |
1974 | /* This case append when the block is not mapped. */ |
1975 | if (block->host == NULL) { | |
1976 | continue; | |
1977 | } | |
9b8424d5 | 1978 | if (host - block->host < block->max_length) { |
23887b79 | 1979 | goto found; |
f471a17e | 1980 | } |
94a6b54f | 1981 | } |
432d268c | 1982 | |
0dc3f44a | 1983 | rcu_read_unlock(); |
1b5ec234 | 1984 | return NULL; |
23887b79 PB |
1985 | |
1986 | found: | |
422148d3 DDAG |
1987 | *offset = (host - block->host); |
1988 | if (round_offset) { | |
1989 | *offset &= TARGET_PAGE_MASK; | |
1990 | } | |
1991 | *ram_addr = block->offset + *offset; | |
0dc3f44a | 1992 | rcu_read_unlock(); |
422148d3 DDAG |
1993 | return block; |
1994 | } | |
1995 | ||
e3dd7493 DDAG |
1996 | /* |
1997 | * Finds the named RAMBlock | |
1998 | * | |
1999 | * name: The name of RAMBlock to find | |
2000 | * | |
2001 | * Returns: RAMBlock (or NULL if not found) | |
2002 | */ | |
2003 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2004 | { | |
2005 | RAMBlock *block; | |
2006 | ||
2007 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { | |
2008 | if (!strcmp(name, block->idstr)) { | |
2009 | return block; | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | return NULL; | |
2014 | } | |
2015 | ||
422148d3 DDAG |
2016 | /* Some of the softmmu routines need to translate from a host pointer |
2017 | (typically a TLB entry) back to a ram offset. */ | |
2018 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) | |
2019 | { | |
2020 | RAMBlock *block; | |
2021 | ram_addr_t offset; /* Not used */ | |
2022 | ||
2023 | block = qemu_ram_block_from_host(ptr, false, ram_addr, &offset); | |
2024 | ||
2025 | if (!block) { | |
2026 | return NULL; | |
2027 | } | |
2028 | ||
2029 | return block->mr; | |
e890261f | 2030 | } |
f471a17e | 2031 | |
49b24afc | 2032 | /* Called within RCU critical section. */ |
a8170e5e | 2033 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
0e0df1e2 | 2034 | uint64_t val, unsigned size) |
9fa3e853 | 2035 | { |
52159192 | 2036 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
0e0df1e2 | 2037 | tb_invalidate_phys_page_fast(ram_addr, size); |
3a7d929e | 2038 | } |
0e0df1e2 AK |
2039 | switch (size) { |
2040 | case 1: | |
3655cb9c | 2041 | stb_p(qemu_get_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2042 | break; |
2043 | case 2: | |
3655cb9c | 2044 | stw_p(qemu_get_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2045 | break; |
2046 | case 4: | |
3655cb9c | 2047 | stl_p(qemu_get_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2048 | break; |
2049 | default: | |
2050 | abort(); | |
3a7d929e | 2051 | } |
58d2707e PB |
2052 | /* Set both VGA and migration bits for simplicity and to remove |
2053 | * the notdirty callback faster. | |
2054 | */ | |
2055 | cpu_physical_memory_set_dirty_range(ram_addr, size, | |
2056 | DIRTY_CLIENTS_NOCODE); | |
f23db169 FB |
2057 | /* we remove the notdirty callback only if the code has been |
2058 | flushed */ | |
a2cd8c85 | 2059 | if (!cpu_physical_memory_is_clean(ram_addr)) { |
bcae01e4 | 2060 | tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr); |
4917cf44 | 2061 | } |
9fa3e853 FB |
2062 | } |
2063 | ||
b018ddf6 PB |
2064 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
2065 | unsigned size, bool is_write) | |
2066 | { | |
2067 | return is_write; | |
2068 | } | |
2069 | ||
0e0df1e2 | 2070 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 2071 | .write = notdirty_mem_write, |
b018ddf6 | 2072 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 2073 | .endianness = DEVICE_NATIVE_ENDIAN, |
1ccde1cb FB |
2074 | }; |
2075 | ||
0f459d16 | 2076 | /* Generate a debug exception if a watchpoint has been hit. */ |
66b9b43c | 2077 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) |
0f459d16 | 2078 | { |
93afeade | 2079 | CPUState *cpu = current_cpu; |
568496c0 | 2080 | CPUClass *cc = CPU_GET_CLASS(cpu); |
93afeade | 2081 | CPUArchState *env = cpu->env_ptr; |
06d55cc1 | 2082 | target_ulong pc, cs_base; |
0f459d16 | 2083 | target_ulong vaddr; |
a1d1bb31 | 2084 | CPUWatchpoint *wp; |
06d55cc1 | 2085 | int cpu_flags; |
0f459d16 | 2086 | |
ff4700b0 | 2087 | if (cpu->watchpoint_hit) { |
06d55cc1 AL |
2088 | /* We re-entered the check after replacing the TB. Now raise |
2089 | * the debug interrupt so that is will trigger after the | |
2090 | * current instruction. */ | |
93afeade | 2091 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
2092 | return; |
2093 | } | |
93afeade | 2094 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
ff4700b0 | 2095 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d PM |
2096 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
2097 | && (wp->flags & flags)) { | |
08225676 PM |
2098 | if (flags == BP_MEM_READ) { |
2099 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2100 | } else { | |
2101 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2102 | } | |
2103 | wp->hitaddr = vaddr; | |
66b9b43c | 2104 | wp->hitattrs = attrs; |
ff4700b0 | 2105 | if (!cpu->watchpoint_hit) { |
568496c0 SF |
2106 | if (wp->flags & BP_CPU && |
2107 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2108 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2109 | continue; | |
2110 | } | |
ff4700b0 | 2111 | cpu->watchpoint_hit = wp; |
239c51a5 | 2112 | tb_check_watchpoint(cpu); |
6e140f28 | 2113 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
27103424 | 2114 | cpu->exception_index = EXCP_DEBUG; |
5638d180 | 2115 | cpu_loop_exit(cpu); |
6e140f28 AL |
2116 | } else { |
2117 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
648f034c | 2118 | tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); |
0ea8cb88 | 2119 | cpu_resume_from_signal(cpu, NULL); |
6e140f28 | 2120 | } |
06d55cc1 | 2121 | } |
6e140f28 AL |
2122 | } else { |
2123 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2124 | } |
2125 | } | |
2126 | } | |
2127 | ||
6658ffb8 PB |
2128 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2129 | so these check for a hit then pass through to the normal out-of-line | |
2130 | phys routines. */ | |
66b9b43c PM |
2131 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, |
2132 | unsigned size, MemTxAttrs attrs) | |
6658ffb8 | 2133 | { |
66b9b43c PM |
2134 | MemTxResult res; |
2135 | uint64_t data; | |
79ed0416 PM |
2136 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2137 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2138 | |
2139 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
1ec9b909 | 2140 | switch (size) { |
66b9b43c | 2141 | case 1: |
79ed0416 | 2142 | data = address_space_ldub(as, addr, attrs, &res); |
66b9b43c PM |
2143 | break; |
2144 | case 2: | |
79ed0416 | 2145 | data = address_space_lduw(as, addr, attrs, &res); |
66b9b43c PM |
2146 | break; |
2147 | case 4: | |
79ed0416 | 2148 | data = address_space_ldl(as, addr, attrs, &res); |
66b9b43c | 2149 | break; |
1ec9b909 AK |
2150 | default: abort(); |
2151 | } | |
66b9b43c PM |
2152 | *pdata = data; |
2153 | return res; | |
6658ffb8 PB |
2154 | } |
2155 | ||
66b9b43c PM |
2156 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, |
2157 | uint64_t val, unsigned size, | |
2158 | MemTxAttrs attrs) | |
6658ffb8 | 2159 | { |
66b9b43c | 2160 | MemTxResult res; |
79ed0416 PM |
2161 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2162 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2163 | |
2164 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
1ec9b909 | 2165 | switch (size) { |
67364150 | 2166 | case 1: |
79ed0416 | 2167 | address_space_stb(as, addr, val, attrs, &res); |
67364150 MF |
2168 | break; |
2169 | case 2: | |
79ed0416 | 2170 | address_space_stw(as, addr, val, attrs, &res); |
67364150 MF |
2171 | break; |
2172 | case 4: | |
79ed0416 | 2173 | address_space_stl(as, addr, val, attrs, &res); |
67364150 | 2174 | break; |
1ec9b909 AK |
2175 | default: abort(); |
2176 | } | |
66b9b43c | 2177 | return res; |
6658ffb8 PB |
2178 | } |
2179 | ||
1ec9b909 | 2180 | static const MemoryRegionOps watch_mem_ops = { |
66b9b43c PM |
2181 | .read_with_attrs = watch_mem_read, |
2182 | .write_with_attrs = watch_mem_write, | |
1ec9b909 | 2183 | .endianness = DEVICE_NATIVE_ENDIAN, |
6658ffb8 | 2184 | }; |
6658ffb8 | 2185 | |
f25a49e0 PM |
2186 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2187 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2188 | { |
acc9d80b | 2189 | subpage_t *subpage = opaque; |
ff6cff75 | 2190 | uint8_t buf[8]; |
5c9eb028 | 2191 | MemTxResult res; |
791af8c8 | 2192 | |
db7b5426 | 2193 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2194 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2195 | subpage, len, addr); |
db7b5426 | 2196 | #endif |
5c9eb028 PM |
2197 | res = address_space_read(subpage->as, addr + subpage->base, |
2198 | attrs, buf, len); | |
2199 | if (res) { | |
2200 | return res; | |
f25a49e0 | 2201 | } |
acc9d80b JK |
2202 | switch (len) { |
2203 | case 1: | |
f25a49e0 PM |
2204 | *data = ldub_p(buf); |
2205 | return MEMTX_OK; | |
acc9d80b | 2206 | case 2: |
f25a49e0 PM |
2207 | *data = lduw_p(buf); |
2208 | return MEMTX_OK; | |
acc9d80b | 2209 | case 4: |
f25a49e0 PM |
2210 | *data = ldl_p(buf); |
2211 | return MEMTX_OK; | |
ff6cff75 | 2212 | case 8: |
f25a49e0 PM |
2213 | *data = ldq_p(buf); |
2214 | return MEMTX_OK; | |
acc9d80b JK |
2215 | default: |
2216 | abort(); | |
2217 | } | |
db7b5426 BS |
2218 | } |
2219 | ||
f25a49e0 PM |
2220 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2221 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2222 | { |
acc9d80b | 2223 | subpage_t *subpage = opaque; |
ff6cff75 | 2224 | uint8_t buf[8]; |
acc9d80b | 2225 | |
db7b5426 | 2226 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2227 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2228 | " value %"PRIx64"\n", |
2229 | __func__, subpage, len, addr, value); | |
db7b5426 | 2230 | #endif |
acc9d80b JK |
2231 | switch (len) { |
2232 | case 1: | |
2233 | stb_p(buf, value); | |
2234 | break; | |
2235 | case 2: | |
2236 | stw_p(buf, value); | |
2237 | break; | |
2238 | case 4: | |
2239 | stl_p(buf, value); | |
2240 | break; | |
ff6cff75 PB |
2241 | case 8: |
2242 | stq_p(buf, value); | |
2243 | break; | |
acc9d80b JK |
2244 | default: |
2245 | abort(); | |
2246 | } | |
5c9eb028 PM |
2247 | return address_space_write(subpage->as, addr + subpage->base, |
2248 | attrs, buf, len); | |
db7b5426 BS |
2249 | } |
2250 | ||
c353e4cc | 2251 | static bool subpage_accepts(void *opaque, hwaddr addr, |
016e9d62 | 2252 | unsigned len, bool is_write) |
c353e4cc | 2253 | { |
acc9d80b | 2254 | subpage_t *subpage = opaque; |
c353e4cc | 2255 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2256 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2257 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2258 | #endif |
2259 | ||
acc9d80b | 2260 | return address_space_access_valid(subpage->as, addr + subpage->base, |
016e9d62 | 2261 | len, is_write); |
c353e4cc PB |
2262 | } |
2263 | ||
70c68e44 | 2264 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2265 | .read_with_attrs = subpage_read, |
2266 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2267 | .impl.min_access_size = 1, |
2268 | .impl.max_access_size = 8, | |
2269 | .valid.min_access_size = 1, | |
2270 | .valid.max_access_size = 8, | |
c353e4cc | 2271 | .valid.accepts = subpage_accepts, |
70c68e44 | 2272 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2273 | }; |
2274 | ||
c227f099 | 2275 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 2276 | uint16_t section) |
db7b5426 BS |
2277 | { |
2278 | int idx, eidx; | |
2279 | ||
2280 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2281 | return -1; | |
2282 | idx = SUBPAGE_IDX(start); | |
2283 | eidx = SUBPAGE_IDX(end); | |
2284 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2285 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2286 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2287 | #endif |
db7b5426 | 2288 | for (; idx <= eidx; idx++) { |
5312bd8b | 2289 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2290 | } |
2291 | ||
2292 | return 0; | |
2293 | } | |
2294 | ||
acc9d80b | 2295 | static subpage_t *subpage_init(AddressSpace *as, hwaddr base) |
db7b5426 | 2296 | { |
c227f099 | 2297 | subpage_t *mmio; |
db7b5426 | 2298 | |
7267c094 | 2299 | mmio = g_malloc0(sizeof(subpage_t)); |
1eec614b | 2300 | |
acc9d80b | 2301 | mmio->as = as; |
1eec614b | 2302 | mmio->base = base; |
2c9b15ca | 2303 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2304 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2305 | mmio->iomem.subpage = true; |
db7b5426 | 2306 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
2307 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
2308 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 2309 | #endif |
b41aac4f | 2310 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
2311 | |
2312 | return mmio; | |
2313 | } | |
2314 | ||
a656e22f PC |
2315 | static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as, |
2316 | MemoryRegion *mr) | |
5312bd8b | 2317 | { |
a656e22f | 2318 | assert(as); |
5312bd8b | 2319 | MemoryRegionSection section = { |
a656e22f | 2320 | .address_space = as, |
5312bd8b AK |
2321 | .mr = mr, |
2322 | .offset_within_address_space = 0, | |
2323 | .offset_within_region = 0, | |
052e87b0 | 2324 | .size = int128_2_64(), |
5312bd8b AK |
2325 | }; |
2326 | ||
53cb28cb | 2327 | return phys_section_add(map, §ion); |
5312bd8b AK |
2328 | } |
2329 | ||
a54c87b6 | 2330 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) |
aa102231 | 2331 | { |
a54c87b6 PM |
2332 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2333 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
32857f4d | 2334 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2335 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 PB |
2336 | |
2337 | return sections[index & ~TARGET_PAGE_MASK].mr; | |
aa102231 AK |
2338 | } |
2339 | ||
e9179ce1 AK |
2340 | static void io_mem_init(void) |
2341 | { | |
1f6245e5 | 2342 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); |
2c9b15ca | 2343 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2344 | NULL, UINT64_MAX); |
2c9b15ca | 2345 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
1f6245e5 | 2346 | NULL, UINT64_MAX); |
2c9b15ca | 2347 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1f6245e5 | 2348 | NULL, UINT64_MAX); |
e9179ce1 AK |
2349 | } |
2350 | ||
ac1970fb | 2351 | static void mem_begin(MemoryListener *listener) |
00752703 PB |
2352 | { |
2353 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); | |
53cb28cb MA |
2354 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2355 | uint16_t n; | |
2356 | ||
a656e22f | 2357 | n = dummy_section(&d->map, as, &io_mem_unassigned); |
53cb28cb | 2358 | assert(n == PHYS_SECTION_UNASSIGNED); |
a656e22f | 2359 | n = dummy_section(&d->map, as, &io_mem_notdirty); |
53cb28cb | 2360 | assert(n == PHYS_SECTION_NOTDIRTY); |
a656e22f | 2361 | n = dummy_section(&d->map, as, &io_mem_rom); |
53cb28cb | 2362 | assert(n == PHYS_SECTION_ROM); |
a656e22f | 2363 | n = dummy_section(&d->map, as, &io_mem_watch); |
53cb28cb | 2364 | assert(n == PHYS_SECTION_WATCH); |
00752703 | 2365 | |
9736e55b | 2366 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
00752703 PB |
2367 | d->as = as; |
2368 | as->next_dispatch = d; | |
2369 | } | |
2370 | ||
79e2b9ae PB |
2371 | static void address_space_dispatch_free(AddressSpaceDispatch *d) |
2372 | { | |
2373 | phys_sections_free(&d->map); | |
2374 | g_free(d); | |
2375 | } | |
2376 | ||
00752703 | 2377 | static void mem_commit(MemoryListener *listener) |
ac1970fb | 2378 | { |
89ae337a | 2379 | AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); |
0475d94f PB |
2380 | AddressSpaceDispatch *cur = as->dispatch; |
2381 | AddressSpaceDispatch *next = as->next_dispatch; | |
2382 | ||
53cb28cb | 2383 | phys_page_compact_all(next, next->map.nodes_nb); |
b35ba30f | 2384 | |
79e2b9ae | 2385 | atomic_rcu_set(&as->dispatch, next); |
53cb28cb | 2386 | if (cur) { |
79e2b9ae | 2387 | call_rcu(cur, address_space_dispatch_free, rcu); |
53cb28cb | 2388 | } |
9affd6fc PB |
2389 | } |
2390 | ||
1d71148e | 2391 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2392 | { |
32857f4d PM |
2393 | CPUAddressSpace *cpuas; |
2394 | AddressSpaceDispatch *d; | |
117712c3 AK |
2395 | |
2396 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2397 | reset the modified entries */ | |
32857f4d PM |
2398 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2399 | cpu_reloading_memory_map(); | |
2400 | /* The CPU and TLB are protected by the iothread lock. | |
2401 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2402 | * may have split the RCU critical section. | |
2403 | */ | |
2404 | d = atomic_rcu_read(&cpuas->as->dispatch); | |
2405 | cpuas->memory_dispatch = d; | |
2406 | tlb_flush(cpuas->cpu, 1); | |
50c1e149 AK |
2407 | } |
2408 | ||
ac1970fb AK |
2409 | void address_space_init_dispatch(AddressSpace *as) |
2410 | { | |
00752703 | 2411 | as->dispatch = NULL; |
89ae337a | 2412 | as->dispatch_listener = (MemoryListener) { |
ac1970fb | 2413 | .begin = mem_begin, |
00752703 | 2414 | .commit = mem_commit, |
ac1970fb AK |
2415 | .region_add = mem_add, |
2416 | .region_nop = mem_add, | |
2417 | .priority = 0, | |
2418 | }; | |
89ae337a | 2419 | memory_listener_register(&as->dispatch_listener, as); |
ac1970fb AK |
2420 | } |
2421 | ||
6e48e8f9 PB |
2422 | void address_space_unregister(AddressSpace *as) |
2423 | { | |
2424 | memory_listener_unregister(&as->dispatch_listener); | |
2425 | } | |
2426 | ||
83f3c251 AK |
2427 | void address_space_destroy_dispatch(AddressSpace *as) |
2428 | { | |
2429 | AddressSpaceDispatch *d = as->dispatch; | |
2430 | ||
79e2b9ae PB |
2431 | atomic_rcu_set(&as->dispatch, NULL); |
2432 | if (d) { | |
2433 | call_rcu(d, address_space_dispatch_free, rcu); | |
2434 | } | |
83f3c251 AK |
2435 | } |
2436 | ||
62152b8a AK |
2437 | static void memory_map_init(void) |
2438 | { | |
7267c094 | 2439 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2440 | |
57271d63 | 2441 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2442 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2443 | |
7267c094 | 2444 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2445 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2446 | 65536); | |
7dca8043 | 2447 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2448 | } |
2449 | ||
2450 | MemoryRegion *get_system_memory(void) | |
2451 | { | |
2452 | return system_memory; | |
2453 | } | |
2454 | ||
309cb471 AK |
2455 | MemoryRegion *get_system_io(void) |
2456 | { | |
2457 | return system_io; | |
2458 | } | |
2459 | ||
e2eef170 PB |
2460 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2461 | ||
13eb76e0 FB |
2462 | /* physical memory access (slow version, mainly for debug) */ |
2463 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 2464 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
a68fe89c | 2465 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2466 | { |
2467 | int l, flags; | |
2468 | target_ulong page; | |
53a5960a | 2469 | void * p; |
13eb76e0 FB |
2470 | |
2471 | while (len > 0) { | |
2472 | page = addr & TARGET_PAGE_MASK; | |
2473 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2474 | if (l > len) | |
2475 | l = len; | |
2476 | flags = page_get_flags(page); | |
2477 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 2478 | return -1; |
13eb76e0 FB |
2479 | if (is_write) { |
2480 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 2481 | return -1; |
579a97f7 | 2482 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2483 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 2484 | return -1; |
72fb7daa AJ |
2485 | memcpy(p, buf, l); |
2486 | unlock_user(p, addr, l); | |
13eb76e0 FB |
2487 | } else { |
2488 | if (!(flags & PAGE_READ)) | |
a68fe89c | 2489 | return -1; |
579a97f7 | 2490 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2491 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 2492 | return -1; |
72fb7daa | 2493 | memcpy(buf, p, l); |
5b257578 | 2494 | unlock_user(p, addr, 0); |
13eb76e0 FB |
2495 | } |
2496 | len -= l; | |
2497 | buf += l; | |
2498 | addr += l; | |
2499 | } | |
a68fe89c | 2500 | return 0; |
13eb76e0 | 2501 | } |
8df1cd07 | 2502 | |
13eb76e0 | 2503 | #else |
51d7a9eb | 2504 | |
845b6214 | 2505 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 2506 | hwaddr length) |
51d7a9eb | 2507 | { |
e87f7778 PB |
2508 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
2509 | /* No early return if dirty_log_mask is or becomes 0, because | |
2510 | * cpu_physical_memory_set_dirty_range will still call | |
2511 | * xen_modified_memory. | |
2512 | */ | |
2513 | if (dirty_log_mask) { | |
2514 | dirty_log_mask = | |
2515 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2516 | } | |
2517 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
2518 | tb_invalidate_phys_range(addr, addr + length); | |
2519 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
51d7a9eb | 2520 | } |
e87f7778 | 2521 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
2522 | } |
2523 | ||
23326164 | 2524 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 2525 | { |
e1622f4b | 2526 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
2527 | |
2528 | /* Regions are assumed to support 1-4 byte accesses unless | |
2529 | otherwise specified. */ | |
23326164 RH |
2530 | if (access_size_max == 0) { |
2531 | access_size_max = 4; | |
2532 | } | |
2533 | ||
2534 | /* Bound the maximum access by the alignment of the address. */ | |
2535 | if (!mr->ops->impl.unaligned) { | |
2536 | unsigned align_size_max = addr & -addr; | |
2537 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2538 | access_size_max = align_size_max; | |
2539 | } | |
82f2563f | 2540 | } |
23326164 RH |
2541 | |
2542 | /* Don't attempt accesses larger than the maximum. */ | |
2543 | if (l > access_size_max) { | |
2544 | l = access_size_max; | |
82f2563f | 2545 | } |
6554f5c0 | 2546 | l = pow2floor(l); |
23326164 RH |
2547 | |
2548 | return l; | |
82f2563f PB |
2549 | } |
2550 | ||
4840f10e | 2551 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 2552 | { |
4840f10e JK |
2553 | bool unlocked = !qemu_mutex_iothread_locked(); |
2554 | bool release_lock = false; | |
2555 | ||
2556 | if (unlocked && mr->global_locking) { | |
2557 | qemu_mutex_lock_iothread(); | |
2558 | unlocked = false; | |
2559 | release_lock = true; | |
2560 | } | |
125b3806 | 2561 | if (mr->flush_coalesced_mmio) { |
4840f10e JK |
2562 | if (unlocked) { |
2563 | qemu_mutex_lock_iothread(); | |
2564 | } | |
125b3806 | 2565 | qemu_flush_coalesced_mmio_buffer(); |
4840f10e JK |
2566 | if (unlocked) { |
2567 | qemu_mutex_unlock_iothread(); | |
2568 | } | |
125b3806 | 2569 | } |
4840f10e JK |
2570 | |
2571 | return release_lock; | |
125b3806 PB |
2572 | } |
2573 | ||
a203ac70 PB |
2574 | /* Called within RCU critical section. */ |
2575 | static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr, | |
2576 | MemTxAttrs attrs, | |
2577 | const uint8_t *buf, | |
2578 | int len, hwaddr addr1, | |
2579 | hwaddr l, MemoryRegion *mr) | |
13eb76e0 | 2580 | { |
13eb76e0 | 2581 | uint8_t *ptr; |
791af8c8 | 2582 | uint64_t val; |
3b643495 | 2583 | MemTxResult result = MEMTX_OK; |
4840f10e | 2584 | bool release_lock = false; |
3b46e624 | 2585 | |
a203ac70 | 2586 | for (;;) { |
eb7eeb88 PB |
2587 | if (!memory_access_is_direct(mr, true)) { |
2588 | release_lock |= prepare_mmio_access(mr); | |
2589 | l = memory_access_size(mr, l, addr1); | |
2590 | /* XXX: could force current_cpu to NULL to avoid | |
2591 | potential bugs */ | |
2592 | switch (l) { | |
2593 | case 8: | |
2594 | /* 64 bit write access */ | |
2595 | val = ldq_p(buf); | |
2596 | result |= memory_region_dispatch_write(mr, addr1, val, 8, | |
2597 | attrs); | |
2598 | break; | |
2599 | case 4: | |
2600 | /* 32 bit write access */ | |
2601 | val = ldl_p(buf); | |
2602 | result |= memory_region_dispatch_write(mr, addr1, val, 4, | |
2603 | attrs); | |
2604 | break; | |
2605 | case 2: | |
2606 | /* 16 bit write access */ | |
2607 | val = lduw_p(buf); | |
2608 | result |= memory_region_dispatch_write(mr, addr1, val, 2, | |
2609 | attrs); | |
2610 | break; | |
2611 | case 1: | |
2612 | /* 8 bit write access */ | |
2613 | val = ldub_p(buf); | |
2614 | result |= memory_region_dispatch_write(mr, addr1, val, 1, | |
2615 | attrs); | |
2616 | break; | |
2617 | default: | |
2618 | abort(); | |
13eb76e0 FB |
2619 | } |
2620 | } else { | |
eb7eeb88 PB |
2621 | addr1 += memory_region_get_ram_addr(mr); |
2622 | /* RAM case */ | |
3655cb9c | 2623 | ptr = qemu_get_ram_ptr(mr->ram_block, addr1); |
eb7eeb88 PB |
2624 | memcpy(ptr, buf, l); |
2625 | invalidate_and_set_dirty(mr, addr1, l); | |
13eb76e0 | 2626 | } |
4840f10e JK |
2627 | |
2628 | if (release_lock) { | |
2629 | qemu_mutex_unlock_iothread(); | |
2630 | release_lock = false; | |
2631 | } | |
2632 | ||
13eb76e0 FB |
2633 | len -= l; |
2634 | buf += l; | |
2635 | addr += l; | |
a203ac70 PB |
2636 | |
2637 | if (!len) { | |
2638 | break; | |
2639 | } | |
2640 | ||
2641 | l = len; | |
2642 | mr = address_space_translate(as, addr, &addr1, &l, true); | |
13eb76e0 | 2643 | } |
fd8aaa76 | 2644 | |
3b643495 | 2645 | return result; |
13eb76e0 | 2646 | } |
8df1cd07 | 2647 | |
a203ac70 PB |
2648 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
2649 | const uint8_t *buf, int len) | |
ac1970fb | 2650 | { |
eb7eeb88 | 2651 | hwaddr l; |
eb7eeb88 PB |
2652 | hwaddr addr1; |
2653 | MemoryRegion *mr; | |
2654 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 2655 | |
a203ac70 PB |
2656 | if (len > 0) { |
2657 | rcu_read_lock(); | |
eb7eeb88 | 2658 | l = len; |
a203ac70 PB |
2659 | mr = address_space_translate(as, addr, &addr1, &l, true); |
2660 | result = address_space_write_continue(as, addr, attrs, buf, len, | |
2661 | addr1, l, mr); | |
2662 | rcu_read_unlock(); | |
2663 | } | |
2664 | ||
2665 | return result; | |
2666 | } | |
2667 | ||
2668 | /* Called within RCU critical section. */ | |
2669 | MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr, | |
2670 | MemTxAttrs attrs, uint8_t *buf, | |
2671 | int len, hwaddr addr1, hwaddr l, | |
2672 | MemoryRegion *mr) | |
2673 | { | |
2674 | uint8_t *ptr; | |
2675 | uint64_t val; | |
2676 | MemTxResult result = MEMTX_OK; | |
2677 | bool release_lock = false; | |
eb7eeb88 | 2678 | |
a203ac70 | 2679 | for (;;) { |
eb7eeb88 PB |
2680 | if (!memory_access_is_direct(mr, false)) { |
2681 | /* I/O case */ | |
2682 | release_lock |= prepare_mmio_access(mr); | |
2683 | l = memory_access_size(mr, l, addr1); | |
2684 | switch (l) { | |
2685 | case 8: | |
2686 | /* 64 bit read access */ | |
2687 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, | |
2688 | attrs); | |
2689 | stq_p(buf, val); | |
2690 | break; | |
2691 | case 4: | |
2692 | /* 32 bit read access */ | |
2693 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, | |
2694 | attrs); | |
2695 | stl_p(buf, val); | |
2696 | break; | |
2697 | case 2: | |
2698 | /* 16 bit read access */ | |
2699 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, | |
2700 | attrs); | |
2701 | stw_p(buf, val); | |
2702 | break; | |
2703 | case 1: | |
2704 | /* 8 bit read access */ | |
2705 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, | |
2706 | attrs); | |
2707 | stb_p(buf, val); | |
2708 | break; | |
2709 | default: | |
2710 | abort(); | |
2711 | } | |
2712 | } else { | |
2713 | /* RAM case */ | |
8e41fb63 FZ |
2714 | ptr = qemu_get_ram_ptr(mr->ram_block, |
2715 | memory_region_get_ram_addr(mr) + addr1); | |
eb7eeb88 PB |
2716 | memcpy(buf, ptr, l); |
2717 | } | |
2718 | ||
2719 | if (release_lock) { | |
2720 | qemu_mutex_unlock_iothread(); | |
2721 | release_lock = false; | |
2722 | } | |
2723 | ||
2724 | len -= l; | |
2725 | buf += l; | |
2726 | addr += l; | |
a203ac70 PB |
2727 | |
2728 | if (!len) { | |
2729 | break; | |
2730 | } | |
2731 | ||
2732 | l = len; | |
2733 | mr = address_space_translate(as, addr, &addr1, &l, false); | |
2734 | } | |
2735 | ||
2736 | return result; | |
2737 | } | |
2738 | ||
3cc8f884 PB |
2739 | MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, |
2740 | MemTxAttrs attrs, uint8_t *buf, int len) | |
a203ac70 PB |
2741 | { |
2742 | hwaddr l; | |
2743 | hwaddr addr1; | |
2744 | MemoryRegion *mr; | |
2745 | MemTxResult result = MEMTX_OK; | |
2746 | ||
2747 | if (len > 0) { | |
2748 | rcu_read_lock(); | |
2749 | l = len; | |
2750 | mr = address_space_translate(as, addr, &addr1, &l, false); | |
2751 | result = address_space_read_continue(as, addr, attrs, buf, len, | |
2752 | addr1, l, mr); | |
2753 | rcu_read_unlock(); | |
eb7eeb88 | 2754 | } |
eb7eeb88 PB |
2755 | |
2756 | return result; | |
ac1970fb AK |
2757 | } |
2758 | ||
eb7eeb88 PB |
2759 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, |
2760 | uint8_t *buf, int len, bool is_write) | |
2761 | { | |
2762 | if (is_write) { | |
2763 | return address_space_write(as, addr, attrs, (uint8_t *)buf, len); | |
2764 | } else { | |
2765 | return address_space_read(as, addr, attrs, (uint8_t *)buf, len); | |
2766 | } | |
2767 | } | |
ac1970fb | 2768 | |
a8170e5e | 2769 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
2770 | int len, int is_write) |
2771 | { | |
5c9eb028 PM |
2772 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
2773 | buf, len, is_write); | |
ac1970fb AK |
2774 | } |
2775 | ||
582b55a9 AG |
2776 | enum write_rom_type { |
2777 | WRITE_DATA, | |
2778 | FLUSH_CACHE, | |
2779 | }; | |
2780 | ||
2a221651 | 2781 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, |
582b55a9 | 2782 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
d0ecd2aa | 2783 | { |
149f54b5 | 2784 | hwaddr l; |
d0ecd2aa | 2785 | uint8_t *ptr; |
149f54b5 | 2786 | hwaddr addr1; |
5c8a00ce | 2787 | MemoryRegion *mr; |
3b46e624 | 2788 | |
41063e1e | 2789 | rcu_read_lock(); |
d0ecd2aa | 2790 | while (len > 0) { |
149f54b5 | 2791 | l = len; |
2a221651 | 2792 | mr = address_space_translate(as, addr, &addr1, &l, true); |
3b46e624 | 2793 | |
5c8a00ce PB |
2794 | if (!(memory_region_is_ram(mr) || |
2795 | memory_region_is_romd(mr))) { | |
b242e0e0 | 2796 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 2797 | } else { |
5c8a00ce | 2798 | addr1 += memory_region_get_ram_addr(mr); |
d0ecd2aa | 2799 | /* ROM/RAM case */ |
3655cb9c | 2800 | ptr = qemu_get_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
2801 | switch (type) { |
2802 | case WRITE_DATA: | |
2803 | memcpy(ptr, buf, l); | |
845b6214 | 2804 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
2805 | break; |
2806 | case FLUSH_CACHE: | |
2807 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
2808 | break; | |
2809 | } | |
d0ecd2aa FB |
2810 | } |
2811 | len -= l; | |
2812 | buf += l; | |
2813 | addr += l; | |
2814 | } | |
41063e1e | 2815 | rcu_read_unlock(); |
d0ecd2aa FB |
2816 | } |
2817 | ||
582b55a9 | 2818 | /* used for ROM loading : can write in RAM and ROM */ |
2a221651 | 2819 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
582b55a9 AG |
2820 | const uint8_t *buf, int len) |
2821 | { | |
2a221651 | 2822 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); |
582b55a9 AG |
2823 | } |
2824 | ||
2825 | void cpu_flush_icache_range(hwaddr start, int len) | |
2826 | { | |
2827 | /* | |
2828 | * This function should do the same thing as an icache flush that was | |
2829 | * triggered from within the guest. For TCG we are always cache coherent, | |
2830 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
2831 | * the host's instruction cache at least. | |
2832 | */ | |
2833 | if (tcg_enabled()) { | |
2834 | return; | |
2835 | } | |
2836 | ||
2a221651 EI |
2837 | cpu_physical_memory_write_rom_internal(&address_space_memory, |
2838 | start, NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
2839 | } |
2840 | ||
6d16c2f8 | 2841 | typedef struct { |
d3e71559 | 2842 | MemoryRegion *mr; |
6d16c2f8 | 2843 | void *buffer; |
a8170e5e AK |
2844 | hwaddr addr; |
2845 | hwaddr len; | |
c2cba0ff | 2846 | bool in_use; |
6d16c2f8 AL |
2847 | } BounceBuffer; |
2848 | ||
2849 | static BounceBuffer bounce; | |
2850 | ||
ba223c29 | 2851 | typedef struct MapClient { |
e95205e1 | 2852 | QEMUBH *bh; |
72cf2d4f | 2853 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
2854 | } MapClient; |
2855 | ||
38e047b5 | 2856 | QemuMutex map_client_list_lock; |
72cf2d4f BS |
2857 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
2858 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 | 2859 | |
e95205e1 FZ |
2860 | static void cpu_unregister_map_client_do(MapClient *client) |
2861 | { | |
2862 | QLIST_REMOVE(client, link); | |
2863 | g_free(client); | |
2864 | } | |
2865 | ||
33b6c2ed FZ |
2866 | static void cpu_notify_map_clients_locked(void) |
2867 | { | |
2868 | MapClient *client; | |
2869 | ||
2870 | while (!QLIST_EMPTY(&map_client_list)) { | |
2871 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
2872 | qemu_bh_schedule(client->bh); |
2873 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
2874 | } |
2875 | } | |
2876 | ||
e95205e1 | 2877 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 2878 | { |
7267c094 | 2879 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 2880 | |
38e047b5 | 2881 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 2882 | client->bh = bh; |
72cf2d4f | 2883 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33b6c2ed FZ |
2884 | if (!atomic_read(&bounce.in_use)) { |
2885 | cpu_notify_map_clients_locked(); | |
2886 | } | |
38e047b5 | 2887 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2888 | } |
2889 | ||
38e047b5 | 2890 | void cpu_exec_init_all(void) |
ba223c29 | 2891 | { |
38e047b5 | 2892 | qemu_mutex_init(&ram_list.mutex); |
38e047b5 | 2893 | io_mem_init(); |
680a4783 | 2894 | memory_map_init(); |
38e047b5 | 2895 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
2896 | } |
2897 | ||
e95205e1 | 2898 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
2899 | { |
2900 | MapClient *client; | |
2901 | ||
e95205e1 FZ |
2902 | qemu_mutex_lock(&map_client_list_lock); |
2903 | QLIST_FOREACH(client, &map_client_list, link) { | |
2904 | if (client->bh == bh) { | |
2905 | cpu_unregister_map_client_do(client); | |
2906 | break; | |
2907 | } | |
ba223c29 | 2908 | } |
e95205e1 | 2909 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2910 | } |
2911 | ||
2912 | static void cpu_notify_map_clients(void) | |
2913 | { | |
38e047b5 | 2914 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 2915 | cpu_notify_map_clients_locked(); |
38e047b5 | 2916 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
2917 | } |
2918 | ||
51644ab7 PB |
2919 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write) |
2920 | { | |
5c8a00ce | 2921 | MemoryRegion *mr; |
51644ab7 PB |
2922 | hwaddr l, xlat; |
2923 | ||
41063e1e | 2924 | rcu_read_lock(); |
51644ab7 PB |
2925 | while (len > 0) { |
2926 | l = len; | |
5c8a00ce PB |
2927 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
2928 | if (!memory_access_is_direct(mr, is_write)) { | |
2929 | l = memory_access_size(mr, l, addr); | |
2930 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
51644ab7 PB |
2931 | return false; |
2932 | } | |
2933 | } | |
2934 | ||
2935 | len -= l; | |
2936 | addr += l; | |
2937 | } | |
41063e1e | 2938 | rcu_read_unlock(); |
51644ab7 PB |
2939 | return true; |
2940 | } | |
2941 | ||
6d16c2f8 AL |
2942 | /* Map a physical memory region into a host virtual address. |
2943 | * May map a subset of the requested range, given by and returned in *plen. | |
2944 | * May return NULL if resources needed to perform the mapping are exhausted. | |
2945 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
2946 | * Use cpu_register_map_client() to know when retrying the map operation is |
2947 | * likely to succeed. | |
6d16c2f8 | 2948 | */ |
ac1970fb | 2949 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
2950 | hwaddr addr, |
2951 | hwaddr *plen, | |
ac1970fb | 2952 | bool is_write) |
6d16c2f8 | 2953 | { |
a8170e5e | 2954 | hwaddr len = *plen; |
e3127ae0 PB |
2955 | hwaddr done = 0; |
2956 | hwaddr l, xlat, base; | |
2957 | MemoryRegion *mr, *this_mr; | |
2958 | ram_addr_t raddr; | |
e81bcda5 | 2959 | void *ptr; |
6d16c2f8 | 2960 | |
e3127ae0 PB |
2961 | if (len == 0) { |
2962 | return NULL; | |
2963 | } | |
38bee5dc | 2964 | |
e3127ae0 | 2965 | l = len; |
41063e1e | 2966 | rcu_read_lock(); |
e3127ae0 | 2967 | mr = address_space_translate(as, addr, &xlat, &l, is_write); |
41063e1e | 2968 | |
e3127ae0 | 2969 | if (!memory_access_is_direct(mr, is_write)) { |
c2cba0ff | 2970 | if (atomic_xchg(&bounce.in_use, true)) { |
41063e1e | 2971 | rcu_read_unlock(); |
e3127ae0 | 2972 | return NULL; |
6d16c2f8 | 2973 | } |
e85d9db5 KW |
2974 | /* Avoid unbounded allocations */ |
2975 | l = MIN(l, TARGET_PAGE_SIZE); | |
2976 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
2977 | bounce.addr = addr; |
2978 | bounce.len = l; | |
d3e71559 PB |
2979 | |
2980 | memory_region_ref(mr); | |
2981 | bounce.mr = mr; | |
e3127ae0 | 2982 | if (!is_write) { |
5c9eb028 PM |
2983 | address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED, |
2984 | bounce.buffer, l); | |
8ab934f9 | 2985 | } |
6d16c2f8 | 2986 | |
41063e1e | 2987 | rcu_read_unlock(); |
e3127ae0 PB |
2988 | *plen = l; |
2989 | return bounce.buffer; | |
2990 | } | |
2991 | ||
2992 | base = xlat; | |
2993 | raddr = memory_region_get_ram_addr(mr); | |
2994 | ||
2995 | for (;;) { | |
6d16c2f8 AL |
2996 | len -= l; |
2997 | addr += l; | |
e3127ae0 PB |
2998 | done += l; |
2999 | if (len == 0) { | |
3000 | break; | |
3001 | } | |
3002 | ||
3003 | l = len; | |
3004 | this_mr = address_space_translate(as, addr, &xlat, &l, is_write); | |
3005 | if (this_mr != mr || xlat != base + done) { | |
3006 | break; | |
3007 | } | |
6d16c2f8 | 3008 | } |
e3127ae0 | 3009 | |
d3e71559 | 3010 | memory_region_ref(mr); |
e3127ae0 | 3011 | *plen = done; |
3655cb9c | 3012 | ptr = qemu_ram_ptr_length(mr->ram_block, raddr + base, plen); |
e81bcda5 PB |
3013 | rcu_read_unlock(); |
3014 | ||
3015 | return ptr; | |
6d16c2f8 AL |
3016 | } |
3017 | ||
ac1970fb | 3018 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
3019 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
3020 | * the amount of memory that was actually read or written by the caller. | |
3021 | */ | |
a8170e5e AK |
3022 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
3023 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
3024 | { |
3025 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3026 | MemoryRegion *mr; |
3027 | ram_addr_t addr1; | |
3028 | ||
3029 | mr = qemu_ram_addr_from_host(buffer, &addr1); | |
3030 | assert(mr != NULL); | |
6d16c2f8 | 3031 | if (is_write) { |
845b6214 | 3032 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3033 | } |
868bb33f | 3034 | if (xen_enabled()) { |
e41d7c69 | 3035 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3036 | } |
d3e71559 | 3037 | memory_region_unref(mr); |
6d16c2f8 AL |
3038 | return; |
3039 | } | |
3040 | if (is_write) { | |
5c9eb028 PM |
3041 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3042 | bounce.buffer, access_len); | |
6d16c2f8 | 3043 | } |
f8a83245 | 3044 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3045 | bounce.buffer = NULL; |
d3e71559 | 3046 | memory_region_unref(bounce.mr); |
c2cba0ff | 3047 | atomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3048 | cpu_notify_map_clients(); |
6d16c2f8 | 3049 | } |
d0ecd2aa | 3050 | |
a8170e5e AK |
3051 | void *cpu_physical_memory_map(hwaddr addr, |
3052 | hwaddr *plen, | |
ac1970fb AK |
3053 | int is_write) |
3054 | { | |
3055 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
3056 | } | |
3057 | ||
a8170e5e AK |
3058 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
3059 | int is_write, hwaddr access_len) | |
ac1970fb AK |
3060 | { |
3061 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3062 | } | |
3063 | ||
8df1cd07 | 3064 | /* warning: addr must be aligned */ |
50013115 PM |
3065 | static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr, |
3066 | MemTxAttrs attrs, | |
3067 | MemTxResult *result, | |
3068 | enum device_endian endian) | |
8df1cd07 | 3069 | { |
8df1cd07 | 3070 | uint8_t *ptr; |
791af8c8 | 3071 | uint64_t val; |
5c8a00ce | 3072 | MemoryRegion *mr; |
149f54b5 PB |
3073 | hwaddr l = 4; |
3074 | hwaddr addr1; | |
50013115 | 3075 | MemTxResult r; |
4840f10e | 3076 | bool release_lock = false; |
8df1cd07 | 3077 | |
41063e1e | 3078 | rcu_read_lock(); |
fdfba1a2 | 3079 | mr = address_space_translate(as, addr, &addr1, &l, false); |
5c8a00ce | 3080 | if (l < 4 || !memory_access_is_direct(mr, false)) { |
4840f10e | 3081 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3082 | |
8df1cd07 | 3083 | /* I/O case */ |
50013115 | 3084 | r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs); |
1e78bcc1 AG |
3085 | #if defined(TARGET_WORDS_BIGENDIAN) |
3086 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
3087 | val = bswap32(val); | |
3088 | } | |
3089 | #else | |
3090 | if (endian == DEVICE_BIG_ENDIAN) { | |
3091 | val = bswap32(val); | |
3092 | } | |
3093 | #endif | |
8df1cd07 FB |
3094 | } else { |
3095 | /* RAM case */ | |
3655cb9c GA |
3096 | ptr = qemu_get_ram_ptr(mr->ram_block, |
3097 | (memory_region_get_ram_addr(mr) | |
06ef3525 | 3098 | & TARGET_PAGE_MASK) |
149f54b5 | 3099 | + addr1); |
1e78bcc1 AG |
3100 | switch (endian) { |
3101 | case DEVICE_LITTLE_ENDIAN: | |
3102 | val = ldl_le_p(ptr); | |
3103 | break; | |
3104 | case DEVICE_BIG_ENDIAN: | |
3105 | val = ldl_be_p(ptr); | |
3106 | break; | |
3107 | default: | |
3108 | val = ldl_p(ptr); | |
3109 | break; | |
3110 | } | |
50013115 PM |
3111 | r = MEMTX_OK; |
3112 | } | |
3113 | if (result) { | |
3114 | *result = r; | |
8df1cd07 | 3115 | } |
4840f10e JK |
3116 | if (release_lock) { |
3117 | qemu_mutex_unlock_iothread(); | |
3118 | } | |
41063e1e | 3119 | rcu_read_unlock(); |
8df1cd07 FB |
3120 | return val; |
3121 | } | |
3122 | ||
50013115 PM |
3123 | uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, |
3124 | MemTxAttrs attrs, MemTxResult *result) | |
3125 | { | |
3126 | return address_space_ldl_internal(as, addr, attrs, result, | |
3127 | DEVICE_NATIVE_ENDIAN); | |
3128 | } | |
3129 | ||
3130 | uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, | |
3131 | MemTxAttrs attrs, MemTxResult *result) | |
3132 | { | |
3133 | return address_space_ldl_internal(as, addr, attrs, result, | |
3134 | DEVICE_LITTLE_ENDIAN); | |
3135 | } | |
3136 | ||
3137 | uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, | |
3138 | MemTxAttrs attrs, MemTxResult *result) | |
3139 | { | |
3140 | return address_space_ldl_internal(as, addr, attrs, result, | |
3141 | DEVICE_BIG_ENDIAN); | |
3142 | } | |
3143 | ||
fdfba1a2 | 3144 | uint32_t ldl_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3145 | { |
50013115 | 3146 | return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3147 | } |
3148 | ||
fdfba1a2 | 3149 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3150 | { |
50013115 | 3151 | return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3152 | } |
3153 | ||
fdfba1a2 | 3154 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3155 | { |
50013115 | 3156 | return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3157 | } |
3158 | ||
84b7b8e7 | 3159 | /* warning: addr must be aligned */ |
50013115 PM |
3160 | static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr, |
3161 | MemTxAttrs attrs, | |
3162 | MemTxResult *result, | |
3163 | enum device_endian endian) | |
84b7b8e7 | 3164 | { |
84b7b8e7 FB |
3165 | uint8_t *ptr; |
3166 | uint64_t val; | |
5c8a00ce | 3167 | MemoryRegion *mr; |
149f54b5 PB |
3168 | hwaddr l = 8; |
3169 | hwaddr addr1; | |
50013115 | 3170 | MemTxResult r; |
4840f10e | 3171 | bool release_lock = false; |
84b7b8e7 | 3172 | |
41063e1e | 3173 | rcu_read_lock(); |
2c17449b | 3174 | mr = address_space_translate(as, addr, &addr1, &l, |
5c8a00ce PB |
3175 | false); |
3176 | if (l < 8 || !memory_access_is_direct(mr, false)) { | |
4840f10e | 3177 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3178 | |
84b7b8e7 | 3179 | /* I/O case */ |
50013115 | 3180 | r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs); |
968a5627 PB |
3181 | #if defined(TARGET_WORDS_BIGENDIAN) |
3182 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
3183 | val = bswap64(val); | |
3184 | } | |
3185 | #else | |
3186 | if (endian == DEVICE_BIG_ENDIAN) { | |
3187 | val = bswap64(val); | |
3188 | } | |
84b7b8e7 FB |
3189 | #endif |
3190 | } else { | |
3191 | /* RAM case */ | |
3655cb9c GA |
3192 | ptr = qemu_get_ram_ptr(mr->ram_block, |
3193 | (memory_region_get_ram_addr(mr) | |
06ef3525 | 3194 | & TARGET_PAGE_MASK) |
149f54b5 | 3195 | + addr1); |
1e78bcc1 AG |
3196 | switch (endian) { |
3197 | case DEVICE_LITTLE_ENDIAN: | |
3198 | val = ldq_le_p(ptr); | |
3199 | break; | |
3200 | case DEVICE_BIG_ENDIAN: | |
3201 | val = ldq_be_p(ptr); | |
3202 | break; | |
3203 | default: | |
3204 | val = ldq_p(ptr); | |
3205 | break; | |
3206 | } | |
50013115 PM |
3207 | r = MEMTX_OK; |
3208 | } | |
3209 | if (result) { | |
3210 | *result = r; | |
84b7b8e7 | 3211 | } |
4840f10e JK |
3212 | if (release_lock) { |
3213 | qemu_mutex_unlock_iothread(); | |
3214 | } | |
41063e1e | 3215 | rcu_read_unlock(); |
84b7b8e7 FB |
3216 | return val; |
3217 | } | |
3218 | ||
50013115 PM |
3219 | uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, |
3220 | MemTxAttrs attrs, MemTxResult *result) | |
3221 | { | |
3222 | return address_space_ldq_internal(as, addr, attrs, result, | |
3223 | DEVICE_NATIVE_ENDIAN); | |
3224 | } | |
3225 | ||
3226 | uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, | |
3227 | MemTxAttrs attrs, MemTxResult *result) | |
3228 | { | |
3229 | return address_space_ldq_internal(as, addr, attrs, result, | |
3230 | DEVICE_LITTLE_ENDIAN); | |
3231 | } | |
3232 | ||
3233 | uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, | |
3234 | MemTxAttrs attrs, MemTxResult *result) | |
3235 | { | |
3236 | return address_space_ldq_internal(as, addr, attrs, result, | |
3237 | DEVICE_BIG_ENDIAN); | |
3238 | } | |
3239 | ||
2c17449b | 3240 | uint64_t ldq_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3241 | { |
50013115 | 3242 | return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3243 | } |
3244 | ||
2c17449b | 3245 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3246 | { |
50013115 | 3247 | return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3248 | } |
3249 | ||
2c17449b | 3250 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3251 | { |
50013115 | 3252 | return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3253 | } |
3254 | ||
aab33094 | 3255 | /* XXX: optimize */ |
50013115 PM |
3256 | uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, |
3257 | MemTxAttrs attrs, MemTxResult *result) | |
aab33094 FB |
3258 | { |
3259 | uint8_t val; | |
50013115 PM |
3260 | MemTxResult r; |
3261 | ||
3262 | r = address_space_rw(as, addr, attrs, &val, 1, 0); | |
3263 | if (result) { | |
3264 | *result = r; | |
3265 | } | |
aab33094 FB |
3266 | return val; |
3267 | } | |
3268 | ||
50013115 PM |
3269 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr) |
3270 | { | |
3271 | return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); | |
3272 | } | |
3273 | ||
733f0b02 | 3274 | /* warning: addr must be aligned */ |
50013115 PM |
3275 | static inline uint32_t address_space_lduw_internal(AddressSpace *as, |
3276 | hwaddr addr, | |
3277 | MemTxAttrs attrs, | |
3278 | MemTxResult *result, | |
3279 | enum device_endian endian) | |
aab33094 | 3280 | { |
733f0b02 MT |
3281 | uint8_t *ptr; |
3282 | uint64_t val; | |
5c8a00ce | 3283 | MemoryRegion *mr; |
149f54b5 PB |
3284 | hwaddr l = 2; |
3285 | hwaddr addr1; | |
50013115 | 3286 | MemTxResult r; |
4840f10e | 3287 | bool release_lock = false; |
733f0b02 | 3288 | |
41063e1e | 3289 | rcu_read_lock(); |
41701aa4 | 3290 | mr = address_space_translate(as, addr, &addr1, &l, |
5c8a00ce PB |
3291 | false); |
3292 | if (l < 2 || !memory_access_is_direct(mr, false)) { | |
4840f10e | 3293 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3294 | |
733f0b02 | 3295 | /* I/O case */ |
50013115 | 3296 | r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs); |
1e78bcc1 AG |
3297 | #if defined(TARGET_WORDS_BIGENDIAN) |
3298 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
3299 | val = bswap16(val); | |
3300 | } | |
3301 | #else | |
3302 | if (endian == DEVICE_BIG_ENDIAN) { | |
3303 | val = bswap16(val); | |
3304 | } | |
3305 | #endif | |
733f0b02 MT |
3306 | } else { |
3307 | /* RAM case */ | |
3655cb9c GA |
3308 | ptr = qemu_get_ram_ptr(mr->ram_block, |
3309 | (memory_region_get_ram_addr(mr) | |
06ef3525 | 3310 | & TARGET_PAGE_MASK) |
149f54b5 | 3311 | + addr1); |
1e78bcc1 AG |
3312 | switch (endian) { |
3313 | case DEVICE_LITTLE_ENDIAN: | |
3314 | val = lduw_le_p(ptr); | |
3315 | break; | |
3316 | case DEVICE_BIG_ENDIAN: | |
3317 | val = lduw_be_p(ptr); | |
3318 | break; | |
3319 | default: | |
3320 | val = lduw_p(ptr); | |
3321 | break; | |
3322 | } | |
50013115 PM |
3323 | r = MEMTX_OK; |
3324 | } | |
3325 | if (result) { | |
3326 | *result = r; | |
733f0b02 | 3327 | } |
4840f10e JK |
3328 | if (release_lock) { |
3329 | qemu_mutex_unlock_iothread(); | |
3330 | } | |
41063e1e | 3331 | rcu_read_unlock(); |
733f0b02 | 3332 | return val; |
aab33094 FB |
3333 | } |
3334 | ||
50013115 PM |
3335 | uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, |
3336 | MemTxAttrs attrs, MemTxResult *result) | |
3337 | { | |
3338 | return address_space_lduw_internal(as, addr, attrs, result, | |
3339 | DEVICE_NATIVE_ENDIAN); | |
3340 | } | |
3341 | ||
3342 | uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, | |
3343 | MemTxAttrs attrs, MemTxResult *result) | |
3344 | { | |
3345 | return address_space_lduw_internal(as, addr, attrs, result, | |
3346 | DEVICE_LITTLE_ENDIAN); | |
3347 | } | |
3348 | ||
3349 | uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, | |
3350 | MemTxAttrs attrs, MemTxResult *result) | |
3351 | { | |
3352 | return address_space_lduw_internal(as, addr, attrs, result, | |
3353 | DEVICE_BIG_ENDIAN); | |
3354 | } | |
3355 | ||
41701aa4 | 3356 | uint32_t lduw_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3357 | { |
50013115 | 3358 | return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3359 | } |
3360 | ||
41701aa4 | 3361 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3362 | { |
50013115 | 3363 | return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3364 | } |
3365 | ||
41701aa4 | 3366 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr) |
1e78bcc1 | 3367 | { |
50013115 | 3368 | return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3369 | } |
3370 | ||
8df1cd07 FB |
3371 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3372 | and the code inside is not invalidated. It is useful if the dirty | |
3373 | bits are used to track modified PTEs */ | |
50013115 PM |
3374 | void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, |
3375 | MemTxAttrs attrs, MemTxResult *result) | |
8df1cd07 | 3376 | { |
8df1cd07 | 3377 | uint8_t *ptr; |
5c8a00ce | 3378 | MemoryRegion *mr; |
149f54b5 PB |
3379 | hwaddr l = 4; |
3380 | hwaddr addr1; | |
50013115 | 3381 | MemTxResult r; |
845b6214 | 3382 | uint8_t dirty_log_mask; |
4840f10e | 3383 | bool release_lock = false; |
8df1cd07 | 3384 | |
41063e1e | 3385 | rcu_read_lock(); |
2198a121 | 3386 | mr = address_space_translate(as, addr, &addr1, &l, |
5c8a00ce PB |
3387 | true); |
3388 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
4840f10e | 3389 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3390 | |
50013115 | 3391 | r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); |
8df1cd07 | 3392 | } else { |
5c8a00ce | 3393 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
3655cb9c | 3394 | ptr = qemu_get_ram_ptr(mr->ram_block, addr1); |
8df1cd07 | 3395 | stl_p(ptr, val); |
74576198 | 3396 | |
845b6214 PB |
3397 | dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
3398 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
58d2707e | 3399 | cpu_physical_memory_set_dirty_range(addr1, 4, dirty_log_mask); |
50013115 PM |
3400 | r = MEMTX_OK; |
3401 | } | |
3402 | if (result) { | |
3403 | *result = r; | |
8df1cd07 | 3404 | } |
4840f10e JK |
3405 | if (release_lock) { |
3406 | qemu_mutex_unlock_iothread(); | |
3407 | } | |
41063e1e | 3408 | rcu_read_unlock(); |
8df1cd07 FB |
3409 | } |
3410 | ||
50013115 PM |
3411 | void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) |
3412 | { | |
3413 | address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); | |
3414 | } | |
3415 | ||
8df1cd07 | 3416 | /* warning: addr must be aligned */ |
50013115 PM |
3417 | static inline void address_space_stl_internal(AddressSpace *as, |
3418 | hwaddr addr, uint32_t val, | |
3419 | MemTxAttrs attrs, | |
3420 | MemTxResult *result, | |
3421 | enum device_endian endian) | |
8df1cd07 | 3422 | { |
8df1cd07 | 3423 | uint8_t *ptr; |
5c8a00ce | 3424 | MemoryRegion *mr; |
149f54b5 PB |
3425 | hwaddr l = 4; |
3426 | hwaddr addr1; | |
50013115 | 3427 | MemTxResult r; |
4840f10e | 3428 | bool release_lock = false; |
8df1cd07 | 3429 | |
41063e1e | 3430 | rcu_read_lock(); |
ab1da857 | 3431 | mr = address_space_translate(as, addr, &addr1, &l, |
5c8a00ce PB |
3432 | true); |
3433 | if (l < 4 || !memory_access_is_direct(mr, true)) { | |
4840f10e | 3434 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3435 | |
1e78bcc1 AG |
3436 | #if defined(TARGET_WORDS_BIGENDIAN) |
3437 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
3438 | val = bswap32(val); | |
3439 | } | |
3440 | #else | |
3441 | if (endian == DEVICE_BIG_ENDIAN) { | |
3442 | val = bswap32(val); | |
3443 | } | |
3444 | #endif | |
50013115 | 3445 | r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); |
8df1cd07 | 3446 | } else { |
8df1cd07 | 3447 | /* RAM case */ |
5c8a00ce | 3448 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
3655cb9c | 3449 | ptr = qemu_get_ram_ptr(mr->ram_block, addr1); |
1e78bcc1 AG |
3450 | switch (endian) { |
3451 | case DEVICE_LITTLE_ENDIAN: | |
3452 | stl_le_p(ptr, val); | |
3453 | break; | |
3454 | case DEVICE_BIG_ENDIAN: | |
3455 | stl_be_p(ptr, val); | |
3456 | break; | |
3457 | default: | |
3458 | stl_p(ptr, val); | |
3459 | break; | |
3460 | } | |
845b6214 | 3461 | invalidate_and_set_dirty(mr, addr1, 4); |
50013115 PM |
3462 | r = MEMTX_OK; |
3463 | } | |
3464 | if (result) { | |
3465 | *result = r; | |
8df1cd07 | 3466 | } |
4840f10e JK |
3467 | if (release_lock) { |
3468 | qemu_mutex_unlock_iothread(); | |
3469 | } | |
41063e1e | 3470 | rcu_read_unlock(); |
8df1cd07 FB |
3471 | } |
3472 | ||
50013115 PM |
3473 | void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, |
3474 | MemTxAttrs attrs, MemTxResult *result) | |
3475 | { | |
3476 | address_space_stl_internal(as, addr, val, attrs, result, | |
3477 | DEVICE_NATIVE_ENDIAN); | |
3478 | } | |
3479 | ||
3480 | void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, | |
3481 | MemTxAttrs attrs, MemTxResult *result) | |
3482 | { | |
3483 | address_space_stl_internal(as, addr, val, attrs, result, | |
3484 | DEVICE_LITTLE_ENDIAN); | |
3485 | } | |
3486 | ||
3487 | void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, | |
3488 | MemTxAttrs attrs, MemTxResult *result) | |
3489 | { | |
3490 | address_space_stl_internal(as, addr, val, attrs, result, | |
3491 | DEVICE_BIG_ENDIAN); | |
3492 | } | |
3493 | ||
ab1da857 | 3494 | void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3495 | { |
50013115 | 3496 | address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3497 | } |
3498 | ||
ab1da857 | 3499 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3500 | { |
50013115 | 3501 | address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3502 | } |
3503 | ||
ab1da857 | 3504 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3505 | { |
50013115 | 3506 | address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3507 | } |
3508 | ||
aab33094 | 3509 | /* XXX: optimize */ |
50013115 PM |
3510 | void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, |
3511 | MemTxAttrs attrs, MemTxResult *result) | |
aab33094 FB |
3512 | { |
3513 | uint8_t v = val; | |
50013115 PM |
3514 | MemTxResult r; |
3515 | ||
3516 | r = address_space_rw(as, addr, attrs, &v, 1, 1); | |
3517 | if (result) { | |
3518 | *result = r; | |
3519 | } | |
3520 | } | |
3521 | ||
3522 | void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) | |
3523 | { | |
3524 | address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); | |
aab33094 FB |
3525 | } |
3526 | ||
733f0b02 | 3527 | /* warning: addr must be aligned */ |
50013115 PM |
3528 | static inline void address_space_stw_internal(AddressSpace *as, |
3529 | hwaddr addr, uint32_t val, | |
3530 | MemTxAttrs attrs, | |
3531 | MemTxResult *result, | |
3532 | enum device_endian endian) | |
aab33094 | 3533 | { |
733f0b02 | 3534 | uint8_t *ptr; |
5c8a00ce | 3535 | MemoryRegion *mr; |
149f54b5 PB |
3536 | hwaddr l = 2; |
3537 | hwaddr addr1; | |
50013115 | 3538 | MemTxResult r; |
4840f10e | 3539 | bool release_lock = false; |
733f0b02 | 3540 | |
41063e1e | 3541 | rcu_read_lock(); |
5ce5944d | 3542 | mr = address_space_translate(as, addr, &addr1, &l, true); |
5c8a00ce | 3543 | if (l < 2 || !memory_access_is_direct(mr, true)) { |
4840f10e | 3544 | release_lock |= prepare_mmio_access(mr); |
125b3806 | 3545 | |
1e78bcc1 AG |
3546 | #if defined(TARGET_WORDS_BIGENDIAN) |
3547 | if (endian == DEVICE_LITTLE_ENDIAN) { | |
3548 | val = bswap16(val); | |
3549 | } | |
3550 | #else | |
3551 | if (endian == DEVICE_BIG_ENDIAN) { | |
3552 | val = bswap16(val); | |
3553 | } | |
3554 | #endif | |
50013115 | 3555 | r = memory_region_dispatch_write(mr, addr1, val, 2, attrs); |
733f0b02 | 3556 | } else { |
733f0b02 | 3557 | /* RAM case */ |
5c8a00ce | 3558 | addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; |
3655cb9c | 3559 | ptr = qemu_get_ram_ptr(mr->ram_block, addr1); |
1e78bcc1 AG |
3560 | switch (endian) { |
3561 | case DEVICE_LITTLE_ENDIAN: | |
3562 | stw_le_p(ptr, val); | |
3563 | break; | |
3564 | case DEVICE_BIG_ENDIAN: | |
3565 | stw_be_p(ptr, val); | |
3566 | break; | |
3567 | default: | |
3568 | stw_p(ptr, val); | |
3569 | break; | |
3570 | } | |
845b6214 | 3571 | invalidate_and_set_dirty(mr, addr1, 2); |
50013115 PM |
3572 | r = MEMTX_OK; |
3573 | } | |
3574 | if (result) { | |
3575 | *result = r; | |
733f0b02 | 3576 | } |
4840f10e JK |
3577 | if (release_lock) { |
3578 | qemu_mutex_unlock_iothread(); | |
3579 | } | |
41063e1e | 3580 | rcu_read_unlock(); |
aab33094 FB |
3581 | } |
3582 | ||
50013115 PM |
3583 | void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, |
3584 | MemTxAttrs attrs, MemTxResult *result) | |
3585 | { | |
3586 | address_space_stw_internal(as, addr, val, attrs, result, | |
3587 | DEVICE_NATIVE_ENDIAN); | |
3588 | } | |
3589 | ||
3590 | void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, | |
3591 | MemTxAttrs attrs, MemTxResult *result) | |
3592 | { | |
3593 | address_space_stw_internal(as, addr, val, attrs, result, | |
3594 | DEVICE_LITTLE_ENDIAN); | |
3595 | } | |
3596 | ||
3597 | void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, | |
3598 | MemTxAttrs attrs, MemTxResult *result) | |
3599 | { | |
3600 | address_space_stw_internal(as, addr, val, attrs, result, | |
3601 | DEVICE_BIG_ENDIAN); | |
3602 | } | |
3603 | ||
5ce5944d | 3604 | void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3605 | { |
50013115 | 3606 | address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3607 | } |
3608 | ||
5ce5944d | 3609 | void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3610 | { |
50013115 | 3611 | address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3612 | } |
3613 | ||
5ce5944d | 3614 | void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) |
1e78bcc1 | 3615 | { |
50013115 | 3616 | address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3617 | } |
3618 | ||
aab33094 | 3619 | /* XXX: optimize */ |
50013115 PM |
3620 | void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, |
3621 | MemTxAttrs attrs, MemTxResult *result) | |
aab33094 | 3622 | { |
50013115 | 3623 | MemTxResult r; |
aab33094 | 3624 | val = tswap64(val); |
50013115 PM |
3625 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); |
3626 | if (result) { | |
3627 | *result = r; | |
3628 | } | |
aab33094 FB |
3629 | } |
3630 | ||
50013115 PM |
3631 | void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, |
3632 | MemTxAttrs attrs, MemTxResult *result) | |
1e78bcc1 | 3633 | { |
50013115 | 3634 | MemTxResult r; |
1e78bcc1 | 3635 | val = cpu_to_le64(val); |
50013115 PM |
3636 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); |
3637 | if (result) { | |
3638 | *result = r; | |
3639 | } | |
3640 | } | |
3641 | void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, | |
3642 | MemTxAttrs attrs, MemTxResult *result) | |
3643 | { | |
3644 | MemTxResult r; | |
3645 | val = cpu_to_be64(val); | |
3646 | r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); | |
3647 | if (result) { | |
3648 | *result = r; | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) | |
3653 | { | |
3654 | address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); | |
3655 | } | |
3656 | ||
3657 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) | |
3658 | { | |
3659 | address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); | |
1e78bcc1 AG |
3660 | } |
3661 | ||
f606604f | 3662 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) |
1e78bcc1 | 3663 | { |
50013115 | 3664 | address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); |
1e78bcc1 AG |
3665 | } |
3666 | ||
5e2972fd | 3667 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3668 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b448f2f3 | 3669 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3670 | { |
3671 | int l; | |
a8170e5e | 3672 | hwaddr phys_addr; |
9b3c35e0 | 3673 | target_ulong page; |
13eb76e0 FB |
3674 | |
3675 | while (len > 0) { | |
5232e4c7 PM |
3676 | int asidx; |
3677 | MemTxAttrs attrs; | |
3678 | ||
13eb76e0 | 3679 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3680 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3681 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3682 | /* if no physical page mapped, return an error */ |
3683 | if (phys_addr == -1) | |
3684 | return -1; | |
3685 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3686 | if (l > len) | |
3687 | l = len; | |
5e2972fd | 3688 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3689 | if (is_write) { |
5232e4c7 PM |
3690 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, |
3691 | phys_addr, buf, l); | |
2e38847b | 3692 | } else { |
5232e4c7 PM |
3693 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, |
3694 | MEMTXATTRS_UNSPECIFIED, | |
5c9eb028 | 3695 | buf, l, 0); |
2e38847b | 3696 | } |
13eb76e0 FB |
3697 | len -= l; |
3698 | buf += l; | |
3699 | addr += l; | |
3700 | } | |
3701 | return 0; | |
3702 | } | |
038629a6 DDAG |
3703 | |
3704 | /* | |
3705 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3706 | * target independent. | |
3707 | */ | |
3708 | size_t qemu_target_page_bits(void) | |
3709 | { | |
3710 | return TARGET_PAGE_BITS; | |
3711 | } | |
3712 | ||
a68fe89c | 3713 | #endif |
13eb76e0 | 3714 | |
8e4a424b BS |
3715 | /* |
3716 | * A helper function for the _utterly broken_ virtio device model to find out if | |
3717 | * it's running on a big endian machine. Don't do this at home kids! | |
3718 | */ | |
98ed8ecf GK |
3719 | bool target_words_bigendian(void); |
3720 | bool target_words_bigendian(void) | |
8e4a424b BS |
3721 | { |
3722 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3723 | return true; | |
3724 | #else | |
3725 | return false; | |
3726 | #endif | |
3727 | } | |
3728 | ||
76f35538 | 3729 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 3730 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3731 | { |
5c8a00ce | 3732 | MemoryRegion*mr; |
149f54b5 | 3733 | hwaddr l = 1; |
41063e1e | 3734 | bool res; |
76f35538 | 3735 | |
41063e1e | 3736 | rcu_read_lock(); |
5c8a00ce PB |
3737 | mr = address_space_translate(&address_space_memory, |
3738 | phys_addr, &phys_addr, &l, false); | |
76f35538 | 3739 | |
41063e1e PB |
3740 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
3741 | rcu_read_unlock(); | |
3742 | return res; | |
76f35538 | 3743 | } |
bd2fa51f | 3744 | |
e3807054 | 3745 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3746 | { |
3747 | RAMBlock *block; | |
e3807054 | 3748 | int ret = 0; |
bd2fa51f | 3749 | |
0dc3f44a MD |
3750 | rcu_read_lock(); |
3751 | QLIST_FOREACH_RCU(block, &ram_list.blocks, next) { | |
e3807054 DDAG |
3752 | ret = func(block->idstr, block->host, block->offset, |
3753 | block->used_length, opaque); | |
3754 | if (ret) { | |
3755 | break; | |
3756 | } | |
bd2fa51f | 3757 | } |
0dc3f44a | 3758 | rcu_read_unlock(); |
e3807054 | 3759 | return ret; |
bd2fa51f | 3760 | } |
ec3f8c99 | 3761 | #endif |