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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
0d09e41a PB |
27 | #include "hw/i386/pc.h" |
28 | #include "hw/char/serial.h" | |
bb3d5ea8 | 29 | #include "hw/char/parallel.h" |
9a52aa40 | 30 | #include "hw/hyperv/hv-balloon.h" |
87abaa5d | 31 | #include "hw/i386/fw_cfg.h" |
d8f23d61 | 32 | #include "hw/i386/vmport.h" |
54a40293 | 33 | #include "sysemu/cpus.h" |
06628267 | 34 | #include "hw/ide/internal.h" |
0d09e41a | 35 | #include "hw/timer/hpet.h" |
83c9f4ca | 36 | #include "hw/loader.h" |
bcdb9064 | 37 | #include "hw/rtc/mc146818rtc.h" |
852c27e2 | 38 | #include "hw/intc/i8259.h" |
0d09e41a | 39 | #include "hw/timer/i8254.h" |
47973a2d | 40 | #include "hw/input/i8042.h" |
0d09e41a | 41 | #include "hw/audio/pcspk.h" |
9c17d615 | 42 | #include "sysemu/sysemu.h" |
da278d58 | 43 | #include "sysemu/xen.h" |
71e8a915 | 44 | #include "sysemu/reset.h" |
a9dc68d9 | 45 | #include "kvm/kvm_i386.h" |
0d09e41a | 46 | #include "hw/xen/xen.h" |
33f0c061 | 47 | #include "qapi/qmp/qlist.h" |
d49b6836 | 48 | #include "qemu/error-report.h" |
5ff020b7 | 49 | #include "hw/acpi/cpu_hotplug.h" |
72c194f7 | 50 | #include "acpi-build.h" |
4b997690 | 51 | #include "hw/mem/nvdimm.h" |
03b39fcf | 52 | #include "hw/cxl/cxl_host.h" |
a310e653 | 53 | #include "hw/usb.h" |
60c5e104 | 54 | #include "hw/i386/intel_iommu.h" |
489983d6 | 55 | #include "hw/net/ne2000-isa.h" |
36efa250 | 56 | #include "hw/virtio/virtio-iommu.h" |
dbdf841b | 57 | #include "hw/virtio/virtio-md-pci.h" |
e21be724 | 58 | #include "hw/i386/kvm/xen_overlay.h" |
91cce756 | 59 | #include "hw/i386/kvm/xen_evtchn.h" |
a28b0fc0 | 60 | #include "hw/i386/kvm/xen_gnttab.h" |
c08f5d0e | 61 | #include "hw/i386/kvm/xen_xenstore.h" |
9a52aa40 | 62 | #include "hw/mem/memory-device.h" |
d6d059ca | 63 | #include "e820_memory_layout.h" |
4ca8dabd | 64 | #include "trace.h" |
2becc36a | 65 | #include CONFIG_DEVICES |
471fd342 | 66 | |
a78c54c4 DW |
67 | #ifdef CONFIG_XEN_EMU |
68 | #include "hw/xen/xen-legacy-backend.h" | |
69 | #include "hw/xen/xen-bus.h" | |
70 | #endif | |
71 | ||
fc5f8923 BB |
72 | /* |
73 | * Helper for setting model-id for CPU models that changed model-id | |
74 | * depending on QEMU versions up to QEMU 2.4. | |
75 | */ | |
76 | #define PC_CPU_MODEL_IDS(v) \ | |
77 | { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ | |
78 | { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ | |
79 | { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, | |
80 | ||
2b10a676 CH |
81 | GlobalProperty pc_compat_8_2[] = {}; |
82 | const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); | |
83 | ||
95f5c89e CH |
84 | GlobalProperty pc_compat_8_1[] = {}; |
85 | const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); | |
86 | ||
d5cef025 DH |
87 | GlobalProperty pc_compat_8_0[] = { |
88 | { "virtio-mem", "unplugged-inaccessible", "auto" }, | |
89 | }; | |
0259dd3e CH |
90 | const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); |
91 | ||
a6b6414f DB |
92 | GlobalProperty pc_compat_7_2[] = { |
93 | { "ICH9-LPC", "noreboot", "true" }, | |
94 | }; | |
db723c80 CH |
95 | const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); |
96 | ||
f514e147 CH |
97 | GlobalProperty pc_compat_7_1[] = {}; |
98 | const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); | |
99 | ||
0ca70366 CH |
100 | GlobalProperty pc_compat_7_0[] = {}; |
101 | const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); | |
102 | ||
60f1f77c DH |
103 | GlobalProperty pc_compat_6_2[] = { |
104 | { "virtio-mem", "unplugged-inaccessible", "off" }, | |
105 | }; | |
01854af2 CH |
106 | const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); |
107 | ||
f701ecec VK |
108 | GlobalProperty pc_compat_6_1[] = { |
109 | { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, | |
110 | { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, | |
111 | { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, | |
c318bef7 | 112 | { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, |
f701ecec | 113 | }; |
52e64f5b YW |
114 | const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); |
115 | ||
b7c29017 DB |
116 | GlobalProperty pc_compat_6_0[] = { |
117 | { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, | |
118 | { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, | |
119 | { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, | |
a7a0da84 | 120 | { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, |
aa29466b | 121 | { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, |
c318bef7 | 122 | { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, |
b7c29017 | 123 | }; |
da7e13c0 CH |
124 | const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); |
125 | ||
7ed3e1eb IM |
126 | GlobalProperty pc_compat_5_2[] = { |
127 | { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, | |
128 | }; | |
576a00bd CH |
129 | const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); |
130 | ||
00dc02d2 IM |
131 | GlobalProperty pc_compat_5_1[] = { |
132 | { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, | |
c1bb5418 | 133 | { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, |
00dc02d2 | 134 | }; |
3ff3c5d3 CH |
135 | const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); |
136 | ||
2ebc2121 HW |
137 | GlobalProperty pc_compat_5_0[] = { |
138 | }; | |
541aaa1d CH |
139 | const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); |
140 | ||
f404220e IM |
141 | GlobalProperty pc_compat_4_2[] = { |
142 | { "mch", "smbase-smram", "off" }, | |
143 | }; | |
3eb74d20 CH |
144 | const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); |
145 | ||
9aec2e52 CH |
146 | GlobalProperty pc_compat_4_1[] = {}; |
147 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
148 | ||
9bf2650b CH |
149 | GlobalProperty pc_compat_4_0[] = {}; |
150 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
151 | ||
abd93cc7 | 152 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 153 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
154 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
155 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
156 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
157 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 158 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
159 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
160 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
161 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
162 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
163 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
164 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
165 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
166 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
167 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
168 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
169 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
170 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
171 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 172 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 173 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
174 | }; |
175 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
176 | ||
ddb3235d | 177 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
178 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
179 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
180 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
181 | }; |
182 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
183 | ||
0d47310b | 184 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
185 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
186 | { TYPE_X86_CPU, "topoext", "off" }, | |
187 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
188 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
189 | }; |
190 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
191 | ||
43df70a9 | 192 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
193 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
194 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
195 | }; |
196 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
197 | ||
503224f4 | 198 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
199 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
200 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
201 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
202 | }; |
203 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
204 | ||
3e803152 | 205 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 206 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
207 | }; |
208 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
209 | ||
edc24ccd | 210 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
211 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
212 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
213 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
214 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
215 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
216 | }; |
217 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
218 | ||
5a995064 | 219 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
220 | { TYPE_X86_CPU, "l3-cache", "off" }, |
221 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
222 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
223 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
224 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
225 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
226 | }; |
227 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
228 | ||
ff8f261f | 229 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
230 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
231 | { "vmxnet3", "romfile", "" }, | |
232 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
233 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
234 | }; |
235 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
236 | ||
fe759610 MAL |
237 | GlobalProperty pc_compat_2_5[] = {}; |
238 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
239 | ||
2f99b9c2 MAL |
240 | GlobalProperty pc_compat_2_4[] = { |
241 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
242 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
243 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
244 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
245 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
246 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
247 | { TYPE_X86_CPU, "check", "off" }, | |
248 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
249 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
250 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
251 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
252 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
253 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
254 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
255 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
256 | }; |
257 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
258 | ||
8995dd90 MAL |
259 | GlobalProperty pc_compat_2_3[] = { |
260 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
261 | { TYPE_X86_CPU, "arat", "off" }, |
262 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
263 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
264 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
265 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
266 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
267 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
268 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
269 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
270 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
271 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
272 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
273 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
274 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
275 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
276 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
277 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
278 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
279 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
280 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
281 | }; |
282 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
283 | ||
1c30044e MAL |
284 | GlobalProperty pc_compat_2_2[] = { |
285 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
286 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
287 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
288 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
289 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
290 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
291 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
292 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
293 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
294 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
295 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
296 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
297 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
298 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
299 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
300 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
301 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
302 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
303 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
304 | }; |
305 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
306 | ||
c4fc5695 MAL |
307 | GlobalProperty pc_compat_2_1[] = { |
308 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
309 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
310 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
311 | }; |
312 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
313 | ||
a310e653 MAL |
314 | GlobalProperty pc_compat_2_0[] = { |
315 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
316 | { "virtio-scsi-pci", "any_layout", "off" }, |
317 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
318 | { "apic", "version", "0x11" }, | |
319 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
320 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
321 | { "pci-serial", "prog_if", "0" }, | |
322 | { "pci-serial-2x", "prog_if", "0" }, | |
323 | { "pci-serial-4x", "prog_if", "0" }, | |
324 | { "virtio-net-pci", "guest_announce", "off" }, | |
325 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
a310e653 MAL |
326 | }; |
327 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
328 | ||
417258f1 PMD |
329 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
330 | { | |
331 | GSIState *s; | |
332 | ||
333 | s = g_new0(GSIState, 1); | |
334 | if (kvm_ioapic_in_kernel()) { | |
335 | kvm_pc_setup_irq_routing(pci_enabled); | |
417258f1 | 336 | } |
e3e3a8ad | 337 | *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); |
417258f1 PMD |
338 | |
339 | return s; | |
340 | } | |
341 | ||
258711c6 JG |
342 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
343 | unsigned size) | |
80cabfad FB |
344 | { |
345 | } | |
346 | ||
c02e1eac JG |
347 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
348 | { | |
a6fc23e5 | 349 | return 0xffffffffffffffffULL; |
c02e1eac JG |
350 | } |
351 | ||
bad5cfcd | 352 | /* MS-DOS compatibility mode FPU exception support */ |
258711c6 JG |
353 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
354 | unsigned size) | |
f929aad6 | 355 | { |
6f529b75 | 356 | if (tcg_enabled()) { |
bf13bfab | 357 | cpu_set_ignne(); |
6f529b75 | 358 | } |
f929aad6 FB |
359 | } |
360 | ||
c02e1eac JG |
361 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
362 | { | |
a6fc23e5 | 363 | return 0xffffffffffffffffULL; |
c02e1eac JG |
364 | } |
365 | ||
b0a21b53 FB |
366 | /* PC cmos mappings */ |
367 | ||
80cabfad FB |
368 | #define REG_EQUIPMENT_BYTE 0x14 |
369 | ||
55c86cb8 | 370 | static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, |
9139046c | 371 | int16_t cylinders, int8_t heads, int8_t sectors) |
ba6c2377 | 372 | { |
2d4bd81e PMD |
373 | mc146818rtc_set_cmos_data(s, type_ofs, 47); |
374 | mc146818rtc_set_cmos_data(s, info_ofs, cylinders); | |
375 | mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); | |
376 | mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); | |
377 | mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); | |
378 | mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); | |
379 | mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
380 | mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); | |
381 | mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); | |
382 | mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); | |
ba6c2377 FB |
383 | } |
384 | ||
6ac0e82d AZ |
385 | /* convert boot_device letter to something recognizable by the bios */ |
386 | static int boot_device2nibble(char boot_device) | |
387 | { | |
388 | switch(boot_device) { | |
389 | case 'a': | |
390 | case 'b': | |
391 | return 0x01; /* floppy boot */ | |
392 | case 'c': | |
393 | return 0x02; /* hard drive boot */ | |
394 | case 'd': | |
395 | return 0x03; /* CD-ROM boot */ | |
396 | case 'n': | |
397 | return 0x04; /* Network boot */ | |
398 | } | |
399 | return 0; | |
400 | } | |
401 | ||
55c86cb8 PMD |
402 | static void set_boot_dev(MC146818RtcState *s, const char *boot_device, |
403 | Error **errp) | |
0ecdffbb AJ |
404 | { |
405 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
406 | int nbds, bds[3] = { 0, }; |
407 | int i; | |
408 | ||
409 | nbds = strlen(boot_device); | |
410 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
411 | error_setg(errp, "Too many boot devices for PC"); |
412 | return; | |
0ecdffbb AJ |
413 | } |
414 | for (i = 0; i < nbds; i++) { | |
415 | bds[i] = boot_device2nibble(boot_device[i]); | |
416 | if (bds[i] == 0) { | |
ddcd5531 GA |
417 | error_setg(errp, "Invalid boot device for PC: '%c'", |
418 | boot_device[i]); | |
419 | return; | |
0ecdffbb AJ |
420 | } |
421 | } | |
2d4bd81e PMD |
422 | mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); |
423 | mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
0ecdffbb AJ |
424 | } |
425 | ||
ddcd5531 | 426 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 427 | { |
ddcd5531 | 428 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
429 | } |
430 | ||
55c86cb8 | 431 | static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) |
7444ca4e LE |
432 | { |
433 | int val, nb, i; | |
2da44dd0 JS |
434 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
435 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
436 | |
437 | /* floppy type */ | |
438 | if (floppy) { | |
439 | for (i = 0; i < 2; i++) { | |
440 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
441 | } | |
442 | } | |
443 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
444 | cmos_get_fd_drive_type(fd_type[1]); | |
2d4bd81e | 445 | mc146818rtc_set_cmos_data(rtc_state, 0x10, val); |
7444ca4e | 446 | |
2d4bd81e | 447 | val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); |
7444ca4e | 448 | nb = 0; |
2da44dd0 | 449 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
450 | nb++; |
451 | } | |
2da44dd0 | 452 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
453 | nb++; |
454 | } | |
455 | switch (nb) { | |
456 | case 0: | |
457 | break; | |
458 | case 1: | |
459 | val |= 0x01; /* 1 drive, ready for boot */ | |
460 | break; | |
461 | case 2: | |
462 | val |= 0x41; /* 2 drives, ready for boot */ | |
463 | break; | |
464 | } | |
2d4bd81e | 465 | mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); |
7444ca4e LE |
466 | } |
467 | ||
c0897e0c | 468 | typedef struct pc_cmos_init_late_arg { |
55c86cb8 | 469 | MC146818RtcState *rtc_state; |
9139046c | 470 | BusState *idebus[2]; |
c0897e0c MA |
471 | } pc_cmos_init_late_arg; |
472 | ||
b86f4613 LE |
473 | typedef struct check_fdc_state { |
474 | ISADevice *floppy; | |
475 | bool multiple; | |
476 | } CheckFdcState; | |
477 | ||
478 | static int check_fdc(Object *obj, void *opaque) | |
479 | { | |
480 | CheckFdcState *state = opaque; | |
481 | Object *fdc; | |
482 | uint32_t iobase; | |
483 | Error *local_err = NULL; | |
484 | ||
485 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
486 | if (!fdc) { | |
487 | return 0; | |
488 | } | |
489 | ||
1ea1572a | 490 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
491 | if (local_err || iobase != 0x3f0) { |
492 | error_free(local_err); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | if (state->floppy) { | |
497 | state->multiple = true; | |
498 | } else { | |
499 | state->floppy = ISA_DEVICE(obj); | |
500 | } | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static const char * const fdc_container_path[] = { | |
505 | "/unattached", "/peripheral", "/peripheral-anon" | |
506 | }; | |
507 | ||
424e4a87 RK |
508 | /* |
509 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
510 | * and ACPI objects. | |
511 | */ | |
cb76321e | 512 | static ISADevice *pc_find_fdc0(void) |
424e4a87 RK |
513 | { |
514 | int i; | |
515 | Object *container; | |
516 | CheckFdcState state = { 0 }; | |
517 | ||
518 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
519 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
520 | object_child_foreach(container, check_fdc, &state); | |
521 | } | |
522 | ||
523 | if (state.multiple) { | |
3dc6f869 AF |
524 | warn_report("multiple floppy disk controllers with " |
525 | "iobase=0x3f0 have been found"); | |
433672b0 | 526 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 527 | "your intent"); |
424e4a87 RK |
528 | } |
529 | ||
530 | return state.floppy; | |
531 | } | |
532 | ||
c0897e0c MA |
533 | static void pc_cmos_init_late(void *opaque) |
534 | { | |
535 | pc_cmos_init_late_arg *arg = opaque; | |
55c86cb8 | 536 | MC146818RtcState *s = arg->rtc_state; |
9139046c MA |
537 | int16_t cylinders; |
538 | int8_t heads, sectors; | |
c0897e0c | 539 | int val; |
2adc99b2 | 540 | int i, trans; |
c0897e0c | 541 | |
9139046c | 542 | val = 0; |
272f0428 CP |
543 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
544 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
545 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
546 | val |= 0xf0; | |
547 | } | |
272f0428 CP |
548 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
549 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
550 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
551 | val |= 0x0f; | |
552 | } | |
2d4bd81e | 553 | mc146818rtc_set_cmos_data(s, 0x12, val); |
c0897e0c MA |
554 | |
555 | val = 0; | |
556 | for (i = 0; i < 4; i++) { | |
9139046c MA |
557 | /* NOTE: ide_get_geometry() returns the physical |
558 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
559 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
560 | geometry can be different if a translation is done. */ | |
272f0428 CP |
561 | if (arg->idebus[i / 2] && |
562 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 563 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
564 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
565 | assert((trans & ~3) == 0); | |
566 | val |= trans << (i * 2); | |
c0897e0c MA |
567 | } |
568 | } | |
2d4bd81e | 569 | mc146818rtc_set_cmos_data(s, 0x39, val); |
c0897e0c | 570 | |
424e4a87 | 571 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 572 | |
c0897e0c MA |
573 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
574 | } | |
575 | ||
23d30407 | 576 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 577 | BusState *idebus0, BusState *idebus1, |
55c86cb8 | 578 | ISADevice *rtc) |
80cabfad | 579 | { |
7444ca4e | 580 | int val; |
c0897e0c | 581 | static pc_cmos_init_late_arg arg; |
f0bb276b | 582 | X86MachineState *x86ms = X86_MACHINE(pcms); |
55c86cb8 | 583 | MC146818RtcState *s = MC146818_RTC(rtc); |
b0a21b53 | 584 | |
b0a21b53 | 585 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
586 | |
587 | /* memory size */ | |
e89001f7 | 588 | /* base memory (first MiB) */ |
f0bb276b | 589 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
2d4bd81e PMD |
590 | mc146818rtc_set_cmos_data(s, 0x15, val); |
591 | mc146818rtc_set_cmos_data(s, 0x16, val >> 8); | |
e89001f7 | 592 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
593 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
594 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
595 | } else { |
596 | val = 0; | |
597 | } | |
80cabfad FB |
598 | if (val > 65535) |
599 | val = 65535; | |
2d4bd81e PMD |
600 | mc146818rtc_set_cmos_data(s, 0x17, val); |
601 | mc146818rtc_set_cmos_data(s, 0x18, val >> 8); | |
602 | mc146818rtc_set_cmos_data(s, 0x30, val); | |
603 | mc146818rtc_set_cmos_data(s, 0x31, val >> 8); | |
e89001f7 | 604 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
605 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
606 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 607 | } else { |
9da98861 | 608 | val = 0; |
e89001f7 | 609 | } |
80cabfad FB |
610 | if (val > 65535) |
611 | val = 65535; | |
2d4bd81e PMD |
612 | mc146818rtc_set_cmos_data(s, 0x34, val); |
613 | mc146818rtc_set_cmos_data(s, 0x35, val >> 8); | |
e89001f7 | 614 | /* memory above 4GiB */ |
f0bb276b | 615 | val = x86ms->above_4g_mem_size / 65536; |
2d4bd81e PMD |
616 | mc146818rtc_set_cmos_data(s, 0x5b, val); |
617 | mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); | |
618 | mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); | |
3b46e624 | 619 | |
23d30407 | 620 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 621 | TYPE_ISA_DEVICE, |
f0bb276b | 622 | (Object **)&x86ms->rtc, |
2d996150 | 623 | object_property_allow_set_link, |
d2623129 | 624 | OBJ_PROP_LINK_STRONG); |
5325cc34 MA |
625 | object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), |
626 | &error_abort); | |
298e01b6 | 627 | |
97ec4d21 | 628 | set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); |
80cabfad | 629 | |
b0a21b53 | 630 | val = 0; |
b0a21b53 FB |
631 | val |= 0x02; /* FPU is there */ |
632 | val |= 0x04; /* PS/2 mouse installed */ | |
2d4bd81e | 633 | mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); |
b0a21b53 | 634 | |
b86f4613 | 635 | /* hard drives and FDC */ |
c0897e0c | 636 | arg.rtc_state = s; |
9139046c MA |
637 | arg.idebus[0] = idebus0; |
638 | arg.idebus[1] = idebus1; | |
c0897e0c | 639 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
640 | } |
641 | ||
956a3e6b | 642 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 643 | { |
cc36a7a2 | 644 | X86CPU *cpu = opaque; |
e1a23744 | 645 | |
956a3e6b | 646 | /* XXX: send to all CPUs ? */ |
4b78a802 | 647 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 648 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
649 | } |
650 | ||
b41a2cd1 FB |
651 | #define NE2000_NB_MAX 6 |
652 | ||
675d6f82 BS |
653 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
654 | 0x280, 0x380 }; | |
655 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 656 | |
cb76321e | 657 | static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
658 | { |
659 | static int nb_ne2k = 0; | |
660 | ||
661 | if (nb_ne2k == NE2000_NB_MAX) | |
662 | return; | |
48a18b3c | 663 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 664 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
665 | nb_ne2k++; |
666 | } | |
667 | ||
845773ab | 668 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 669 | { |
c3affe56 | 670 | X86CPU *cpu = opaque; |
53b67b30 BS |
671 | |
672 | if (level) { | |
c3affe56 | 673 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
674 | } |
675 | } | |
676 | ||
3459a625 | 677 | static |
9ebeed0c | 678 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 679 | { |
9ebeed0c EH |
680 | PCMachineState *pcms = container_of(notifier, |
681 | PCMachineState, machine_done); | |
f0bb276b | 682 | X86MachineState *x86ms = X86_MACHINE(pcms); |
dab390ff | 683 | |
1ebf9001 JC |
684 | cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, |
685 | &error_fatal); | |
686 | ||
687 | if (pcms->cxl_devices_state.is_enabled) { | |
688 | cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); | |
dab390ff | 689 | } |
2118196b | 690 | |
ba157b69 | 691 | /* set the number of CPUs */ |
0cca1a91 | 692 | x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 693 | |
0abd3888 | 694 | fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); |
2118196b | 695 | |
bb292f5a | 696 | acpi_setup(); |
f0bb276b PB |
697 | if (x86ms->fw_cfg) { |
698 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
699 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 700 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 701 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 702 | } |
3459a625 MT |
703 | } |
704 | ||
e4e8ba04 | 705 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 706 | { |
f0bb276b | 707 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 708 | |
eafa0868 | 709 | x86ms->apic_xrupt_override = true; |
9ebeed0c EH |
710 | pcms->machine_done.notify = pc_machine_done; |
711 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
712 | } |
713 | ||
83d08f26 | 714 | /* setup pci memory address space mapping into system address space */ |
09aa7be1 | 715 | void pc_pci_as_mapping_init(MemoryRegion *system_memory, |
83d08f26 | 716 | MemoryRegion *pci_address_space) |
39848901 | 717 | { |
83d08f26 MT |
718 | /* Set to lower priority than RAM */ |
719 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
720 | pci_address_space, -1); | |
39848901 IM |
721 | } |
722 | ||
7bc35e0f | 723 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
724 | { |
725 | int i; | |
726 | FWCfgState *fw_cfg; | |
703a548a | 727 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 728 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 729 | |
df1f79fd | 730 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 731 | |
305ae888 | 732 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 733 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
734 | rom_set_fw(fw_cfg); |
735 | ||
703a548a | 736 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
167f4873 | 737 | pcmc->pvh_enabled); |
b33a5bbf CL |
738 | for (i = 0; i < nb_option_roms; i++) { |
739 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 740 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 741 | !strcmp(option_rom[i].name, "pvh.bin") || |
3ca8ce72 PB |
742 | !strcmp(option_rom[i].name, "multiboot.bin") || |
743 | !strcmp(option_rom[i].name, "multiboot_dma.bin")); | |
b33a5bbf CL |
744 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
745 | } | |
f0bb276b | 746 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
747 | } |
748 | ||
72686c58 PMD |
749 | #define PC_ROM_MIN_VGA 0xc0000 |
750 | #define PC_ROM_MIN_OPTION 0xc8000 | |
751 | #define PC_ROM_MAX 0xe0000 | |
752 | #define PC_ROM_ALIGN 0x800 | |
753 | #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) | |
754 | ||
5ff62e2a JM |
755 | static hwaddr pc_above_4g_end(PCMachineState *pcms) |
756 | { | |
757 | X86MachineState *x86ms = X86_MACHINE(pcms); | |
758 | ||
759 | if (pcms->sgx_epc.size != 0) { | |
760 | return sgx_epc_above_4g_end(&pcms->sgx_epc); | |
761 | } | |
762 | ||
763 | return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; | |
764 | } | |
765 | ||
8288a828 JM |
766 | static void pc_get_device_memory_range(PCMachineState *pcms, |
767 | hwaddr *base, | |
768 | ram_addr_t *device_mem_size) | |
42bed071 JM |
769 | { |
770 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
771 | MachineState *machine = MACHINE(pcms); | |
8288a828 JM |
772 | ram_addr_t size; |
773 | hwaddr addr; | |
774 | ||
775 | size = machine->maxram_size - machine->ram_size; | |
776 | addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); | |
777 | ||
778 | if (pcmc->enforce_aligned_dimm) { | |
779 | /* size device region assuming 1G page max alignment per slot */ | |
780 | size += (1 * GiB) * machine->ram_slots; | |
781 | } | |
782 | ||
783 | *base = addr; | |
784 | *device_mem_size = size; | |
785 | } | |
786 | ||
787 | static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) | |
788 | { | |
789 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
4076bc86 | 790 | MachineState *ms = MACHINE(pcms); |
42bed071 | 791 | hwaddr cxl_base; |
8288a828 | 792 | ram_addr_t size; |
42bed071 | 793 | |
4076bc86 AS |
794 | if (pcmc->has_reserved_memory && |
795 | (ms->ram_size < ms->maxram_size)) { | |
8288a828 JM |
796 | pc_get_device_memory_range(pcms, &cxl_base, &size); |
797 | cxl_base += size; | |
42bed071 JM |
798 | } else { |
799 | cxl_base = pc_above_4g_end(pcms); | |
800 | } | |
801 | ||
802 | return cxl_base; | |
803 | } | |
804 | ||
55668e40 JM |
805 | static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) |
806 | { | |
1065b219 JM |
807 | uint64_t start = pc_get_cxl_range_start(pcms) + MiB; |
808 | ||
809 | if (pcms->cxl_devices_state.fixed_windows) { | |
810 | GList *it; | |
811 | ||
812 | start = ROUND_UP(start, 256 * MiB); | |
813 | for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { | |
814 | CXLFixedWindow *fw = it->data; | |
815 | start += fw->size; | |
55668e40 JM |
816 | } |
817 | } | |
818 | ||
819 | return start; | |
820 | } | |
821 | ||
1caab5cf JM |
822 | static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) |
823 | { | |
824 | X86CPU *cpu = X86_CPU(first_cpu); | |
cf038650 AS |
825 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
826 | MachineState *ms = MACHINE(pcms); | |
827 | ||
828 | if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { | |
829 | /* 64-bit systems */ | |
830 | return pc_pci_hole64_start() + pci_hole64_size - 1; | |
831 | } | |
1caab5cf | 832 | |
cf038650 AS |
833 | /* 32-bit systems */ |
834 | if (pcmc->broken_32bit_mem_addr_check) { | |
835 | /* old value for compatibility reasons */ | |
1caab5cf JM |
836 | return ((hwaddr)1 << cpu->phys_bits) - 1; |
837 | } | |
838 | ||
cf038650 AS |
839 | /* |
840 | * 32-bit systems don't have hole64 but they might have a region for | |
841 | * memory devices. Even if additional hotplugged memory devices might | |
842 | * not be usable by most guest OSes, we need to still consider them for | |
843 | * calculating the highest possible GPA so that we can properly report | |
844 | * if someone configures them on a CPU that cannot possibly address them. | |
845 | */ | |
846 | if (pcmc->has_reserved_memory && | |
847 | (ms->ram_size < ms->maxram_size)) { | |
848 | hwaddr devmem_start; | |
849 | ram_addr_t devmem_size; | |
850 | ||
851 | pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); | |
852 | devmem_start += devmem_size; | |
853 | return devmem_start - 1; | |
854 | } | |
855 | ||
856 | /* configuration without any memory hotplug */ | |
857 | return pc_above_4g_end(pcms) - 1; | |
1caab5cf JM |
858 | } |
859 | ||
8504f129 JM |
860 | /* |
861 | * AMD systems with an IOMMU have an additional hole close to the | |
862 | * 1Tb, which are special GPAs that cannot be DMA mapped. Depending | |
863 | * on kernel version, VFIO may or may not let you DMA map those ranges. | |
864 | * Starting Linux v5.4 we validate it, and can't create guests on AMD machines | |
865 | * with certain memory sizes. It's also wrong to use those IOVA ranges | |
866 | * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. | |
867 | * The ranges reserved for Hyper-Transport are: | |
868 | * | |
869 | * FD_0000_0000h - FF_FFFF_FFFFh | |
870 | * | |
871 | * The ranges represent the following: | |
872 | * | |
873 | * Base Address Top Address Use | |
874 | * | |
875 | * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space | |
876 | * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl | |
877 | * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK | |
878 | * FD_F910_0000h FD_F91F_FFFFh System Management | |
879 | * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables | |
880 | * FD_FB00_0000h FD_FBFF_FFFFh Address Translation | |
881 | * FD_FC00_0000h FD_FDFF_FFFFh I/O Space | |
882 | * FD_FE00_0000h FD_FFFF_FFFFh Configuration | |
883 | * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages | |
884 | * FE_2000_0000h FF_FFFF_FFFFh Reserved | |
885 | * | |
886 | * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", | |
887 | * Table 3: Special Address Controls (GPA) for more information. | |
888 | */ | |
889 | #define AMD_HT_START 0xfd00000000UL | |
890 | #define AMD_HT_END 0xffffffffffUL | |
891 | #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) | |
892 | #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) | |
893 | ||
5934e216 EH |
894 | void pc_memory_init(PCMachineState *pcms, |
895 | MemoryRegion *system_memory, | |
896 | MemoryRegion *rom_memory, | |
c48eb7a4 | 897 | uint64_t pci_hole64_size) |
80cabfad | 898 | { |
cbc5b5f3 | 899 | int linux_boot, i; |
bd457782 | 900 | MemoryRegion *option_rom_mr; |
00cb2a99 | 901 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 902 | FWCfgState *fw_cfg; |
62b160c0 | 903 | MachineState *machine = MACHINE(pcms); |
264b4857 | 904 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 905 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 906 | X86MachineState *x86ms = X86_MACHINE(pcms); |
1caab5cf | 907 | hwaddr maxphysaddr, maxusedaddr; |
6d302cf4 | 908 | hwaddr cxl_base, cxl_resv_end = 0; |
1caab5cf | 909 | X86CPU *cpu = X86_CPU(first_cpu); |
d592d303 | 910 | |
f0bb276b PB |
911 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
912 | x86ms->above_4g_mem_size); | |
9521d42b PB |
913 | |
914 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 915 | |
8504f129 JM |
916 | /* |
917 | * The HyperTransport range close to the 1T boundary is unique to AMD | |
918 | * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation | |
b3e6982b JM |
919 | * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in |
920 | * older machine types (<= 7.0) for compatibility purposes. | |
8504f129 | 921 | */ |
b3e6982b | 922 | if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { |
8504f129 JM |
923 | /* Bail out if max possible address does not cross HT range */ |
924 | if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { | |
925 | x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; | |
926 | } | |
927 | ||
928 | /* | |
929 | * Advertise the HT region if address space covers the reserved | |
930 | * region or if we relocate. | |
931 | */ | |
932 | if (cpu->phys_bits >= 40) { | |
933 | e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); | |
934 | } | |
935 | } | |
936 | ||
1caab5cf JM |
937 | /* |
938 | * phys-bits is required to be appropriately configured | |
939 | * to make sure max used GPA is reachable. | |
940 | */ | |
941 | maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); | |
942 | maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; | |
943 | if (maxphysaddr < maxusedaddr) { | |
944 | error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 | |
945 | " phys-bits too low (%u)", | |
946 | maxphysaddr, maxusedaddr, cpu->phys_bits); | |
947 | exit(EXIT_FAILURE); | |
948 | } | |
949 | ||
bd457782 IM |
950 | /* |
951 | * Split single memory region and use aliases to address portions of it, | |
952 | * done for backwards compatibility with older qemus. | |
00cb2a99 | 953 | */ |
7267c094 | 954 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
bd457782 | 955 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, |
f0bb276b | 956 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 957 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
958 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
959 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 960 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
bd457782 IM |
961 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", |
962 | machine->ram, | |
f0bb276b PB |
963 | x86ms->below_4g_mem_size, |
964 | x86ms->above_4g_mem_size); | |
4ab4c330 | 965 | memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, |
00cb2a99 | 966 | ram_above_4g); |
4ab4c330 JM |
967 | e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, |
968 | E820_RAM); | |
bbe80adf | 969 | } |
82b36dc3 | 970 | |
1ed1ccc5 SC |
971 | if (pcms->sgx_epc.size != 0) { |
972 | e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); | |
973 | } | |
974 | ||
bb292f5a | 975 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 976 | (machine->ram_slots || |
9521d42b | 977 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
978 | |
979 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
980 | mc->name); | |
981 | exit(EXIT_FAILURE); | |
982 | } | |
983 | ||
f2ffbe2b | 984 | /* initialize device memory address space */ |
bb292f5a | 985 | if (pcmc->has_reserved_memory && |
9521d42b | 986 | (machine->ram_size < machine->maxram_size)) { |
8288a828 | 987 | ram_addr_t device_mem_size; |
78732a76 | 988 | hwaddr device_mem_base; |
619d11e4 | 989 | |
a0cc8856 IM |
990 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
991 | error_report("unsupported amount of memory slots: %"PRIu64, | |
992 | machine->ram_slots); | |
993 | exit(EXIT_FAILURE); | |
994 | } | |
995 | ||
f2c38522 PK |
996 | if (QEMU_ALIGN_UP(machine->maxram_size, |
997 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
998 | error_report("maximum memory size must by aligned to multiple of " | |
999 | "%d bytes", TARGET_PAGE_SIZE); | |
1000 | exit(EXIT_FAILURE); | |
1001 | } | |
1002 | ||
78732a76 | 1003 | pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); |
085f8e88 | 1004 | |
78732a76 | 1005 | if (device_mem_base + device_mem_size < device_mem_size) { |
619d11e4 IM |
1006 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1007 | machine->maxram_size); | |
1008 | exit(EXIT_FAILURE); | |
1009 | } | |
78732a76 | 1010 | machine_memory_devices_init(machine, device_mem_base, device_mem_size); |
619d11e4 | 1011 | } |
cbc5b5f3 | 1012 | |
1ebf9001 JC |
1013 | if (pcms->cxl_devices_state.is_enabled) { |
1014 | MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; | |
6e4e3ae9 BW |
1015 | hwaddr cxl_size = MiB; |
1016 | ||
42bed071 | 1017 | cxl_base = pc_get_cxl_range_start(pcms); |
6e4e3ae9 BW |
1018 | memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); |
1019 | memory_region_add_subregion(system_memory, cxl_base, mr); | |
6d302cf4 | 1020 | cxl_resv_end = cxl_base + cxl_size; |
1ebf9001 | 1021 | if (pcms->cxl_devices_state.fixed_windows) { |
6d302cf4 JC |
1022 | hwaddr cxl_fmw_base; |
1023 | GList *it; | |
1024 | ||
1025 | cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); | |
1ebf9001 | 1026 | for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { |
6d302cf4 JC |
1027 | CXLFixedWindow *fw = it->data; |
1028 | ||
1029 | fw->base = cxl_fmw_base; | |
1030 | memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, | |
1031 | "cxl-fixed-memory-region", fw->size); | |
1032 | memory_region_add_subregion(system_memory, fw->base, &fw->mr); | |
6d302cf4 JC |
1033 | cxl_fmw_base += fw->size; |
1034 | cxl_resv_end = cxl_fmw_base; | |
1035 | } | |
1036 | } | |
6e4e3ae9 BW |
1037 | } |
1038 | ||
cbc5b5f3 | 1039 | /* Initialize PC system firmware */ |
5e640a9e | 1040 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 1041 | |
7267c094 | 1042 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1043 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1044 | &error_fatal); |
208fa0e4 IM |
1045 | if (pcmc->pci_enabled) { |
1046 | memory_region_set_readonly(option_rom_mr, true); | |
1047 | } | |
4463aee6 | 1048 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1049 | PC_ROM_MIN_VGA, |
1050 | option_rom_mr, | |
1051 | 1); | |
f753ff16 | 1052 | |
bd802bd9 | 1053 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 1054 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 1055 | |
8832cb80 | 1056 | rom_set_fw(fw_cfg); |
1d108d97 | 1057 | |
78732a76 | 1058 | if (machine->device_memory) { |
de268e13 | 1059 | uint64_t *val = g_malloc(sizeof(*val)); |
b0c14ec4 | 1060 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1061 | |
1062 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1063 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1064 | } |
6d302cf4 | 1065 | |
1ebf9001 | 1066 | if (pcms->cxl_devices_state.is_enabled) { |
6d302cf4 JC |
1067 | res_mem_end = cxl_resv_end; |
1068 | } | |
d471bf3e | 1069 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1070 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1071 | } | |
1072 | ||
f753ff16 | 1073 | if (linux_boot) { |
703a548a | 1074 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
167f4873 | 1075 | pcmc->pvh_enabled); |
f753ff16 PB |
1076 | } |
1077 | ||
1078 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1079 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1080 | } |
f0bb276b | 1081 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
1082 | |
1083 | /* Init default IOAPIC address space */ | |
f0bb276b | 1084 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
1085 | |
1086 | /* Init ACPI memory hotplug IO base address */ | |
1087 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
1088 | } |
1089 | ||
9fa99d25 MA |
1090 | /* |
1091 | * The 64bit pci hole starts after "above 4G RAM" and | |
1092 | * potentially the space reserved for memory hotplug. | |
1093 | */ | |
1094 | uint64_t pc_pci_hole64_start(void) | |
1095 | { | |
1096 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1097 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1098 | MachineState *ms = MACHINE(pcms); |
9fa99d25 | 1099 | uint64_t hole64_start = 0; |
8288a828 | 1100 | ram_addr_t size = 0; |
9fa99d25 | 1101 | |
55668e40 JM |
1102 | if (pcms->cxl_devices_state.is_enabled) { |
1103 | hole64_start = pc_get_cxl_range_end(pcms); | |
8288a828 JM |
1104 | } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { |
1105 | pc_get_device_memory_range(pcms, &hole64_start, &size); | |
9fa99d25 | 1106 | if (!pcmc->broken_reserved_end) { |
8288a828 | 1107 | hole64_start += size; |
9fa99d25 MA |
1108 | } |
1109 | } else { | |
5ff62e2a | 1110 | hole64_start = pc_above_4g_end(pcms); |
9fa99d25 MA |
1111 | } |
1112 | ||
d471bf3e | 1113 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1114 | } |
1115 | ||
48a18b3c | 1116 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1117 | { |
ad6d45fa AL |
1118 | DeviceState *dev = NULL; |
1119 | ||
bab47d9a | 1120 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1121 | if (pci_bus) { |
1122 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1123 | dev = pcidev ? &pcidev->qdev : NULL; | |
1124 | } else if (isa_bus) { | |
1125 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1126 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1127 | } |
bab47d9a | 1128 | rom_reset_order_override(); |
ad6d45fa | 1129 | return dev; |
765d7908 IY |
1130 | } |
1131 | ||
258711c6 JG |
1132 | static const MemoryRegionOps ioport80_io_ops = { |
1133 | .write = ioport80_write, | |
c02e1eac | 1134 | .read = ioport80_read, |
258711c6 JG |
1135 | .endianness = DEVICE_NATIVE_ENDIAN, |
1136 | .impl = { | |
1137 | .min_access_size = 1, | |
1138 | .max_access_size = 1, | |
1139 | }, | |
1140 | }; | |
1141 | ||
1142 | static const MemoryRegionOps ioportF0_io_ops = { | |
1143 | .write = ioportF0_write, | |
c02e1eac | 1144 | .read = ioportF0_read, |
258711c6 JG |
1145 | .endianness = DEVICE_NATIVE_ENDIAN, |
1146 | .impl = { | |
1147 | .min_access_size = 1, | |
1148 | .max_access_size = 1, | |
1149 | }, | |
1150 | }; | |
1151 | ||
4ccd5fe2 JD |
1152 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, |
1153 | bool create_i8042, bool no_vmport) | |
ac64273c PMD |
1154 | { |
1155 | int i; | |
1156 | DriveInfo *fd[MAX_FD]; | |
1157 | qemu_irq *a20_line; | |
fed2c173 | 1158 | ISADevice *fdc, *i8042, *port92, *vmmouse; |
ac64273c | 1159 | |
def337ff | 1160 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1161 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1162 | ||
1163 | for (i = 0; i < MAX_FD; i++) { | |
1164 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1165 | create_fdctrl |= !!fd[i]; | |
1166 | } | |
1167 | if (create_fdctrl) { | |
fed2c173 MA |
1168 | fdc = isa_new(TYPE_ISA_FDC); |
1169 | if (fdc) { | |
1170 | isa_realize_and_unref(fdc, isa_bus, &error_fatal); | |
1171 | isa_fdc_init_drives(fdc, fd); | |
1172 | } | |
ac64273c PMD |
1173 | } |
1174 | ||
4ccd5fe2 JD |
1175 | if (!create_i8042) { |
1176 | return; | |
1177 | } | |
1178 | ||
aa2e535c | 1179 | i8042 = isa_create_simple(isa_bus, TYPE_I8042); |
ac64273c | 1180 | if (!no_vmport) { |
b4fa79ea | 1181 | isa_create_simple(isa_bus, TYPE_VMPORT); |
c23e0561 | 1182 | vmmouse = isa_try_new("vmmouse"); |
ac64273c PMD |
1183 | } else { |
1184 | vmmouse = NULL; | |
1185 | } | |
1186 | if (vmmouse) { | |
aa2e535c | 1187 | object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), |
5325cc34 | 1188 | &error_abort); |
c23e0561 | 1189 | isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); |
ac64273c | 1190 | } |
9e5213c8 | 1191 | port92 = isa_create_simple(isa_bus, TYPE_PORT92); |
ac64273c PMD |
1192 | |
1193 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1194 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1820b70e PMD |
1195 | qdev_connect_gpio_out_named(DEVICE(port92), |
1196 | PORT92_A20_LINE, 0, a20_line[1]); | |
ac64273c PMD |
1197 | g_free(a20_line); |
1198 | } | |
1199 | ||
10e2483b GH |
1200 | void pc_basic_device_init(struct PCMachineState *pcms, |
1201 | ISABus *isa_bus, qemu_irq *gsi, | |
87af48a4 | 1202 | ISADevice *rtc_state, |
fd53c87c | 1203 | bool create_fdctrl, |
3a87d009 | 1204 | uint32_t hpet_irqs) |
ffe513da IY |
1205 | { |
1206 | int i; | |
ce967e2f JK |
1207 | DeviceState *hpet = NULL; |
1208 | int pit_isa_irq = 0; | |
1209 | qemu_irq pit_alt_irq = NULL; | |
ac64273c | 1210 | ISADevice *pit = NULL; |
258711c6 JG |
1211 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1212 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
9dee7e51 | 1213 | X86MachineState *x86ms = X86_MACHINE(pcms); |
ffe513da | 1214 | |
2c9b15ca | 1215 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1216 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1217 | |
2c9b15ca | 1218 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1219 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1220 | |
5d17c0d2 JK |
1221 | /* |
1222 | * Check if an HPET shall be created. | |
5d17c0d2 | 1223 | */ |
39dd3e1f | 1224 | if (pcms->hpet_enabled) { |
9c910511 BB |
1225 | qemu_irq rtc_irq; |
1226 | ||
df707969 | 1227 | hpet = qdev_try_new(TYPE_HPET); |
0259c78c EH |
1228 | if (!hpet) { |
1229 | error_report("couldn't create HPET device"); | |
1230 | exit(1); | |
1231 | } | |
54420332 | 1232 | /* |
ea985d23 PB |
1233 | * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, |
1234 | * use IRQ16~23, IRQ8 and IRQ2. If the user has already set | |
1235 | * the property, use whatever mask they specified. | |
54420332 | 1236 | */ |
0259c78c EH |
1237 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
1238 | HPET_INTCAP, NULL); | |
1239 | if (!compat) { | |
1240 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1241 | } | |
1242 | sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); | |
1243 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
7a10ef51 | 1244 | |
e3e3a8ad | 1245 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
0259c78c | 1246 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
822557eb | 1247 | } |
0259c78c EH |
1248 | pit_isa_irq = -1; |
1249 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1250 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
f0bc6bf7 | 1251 | |
56b1f50e | 1252 | /* overwrite connection created by south bridge */ |
87af48a4 | 1253 | qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); |
f0bc6bf7 | 1254 | } |
9c910511 | 1255 | |
87af48a4 | 1256 | object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), |
f0bc6bf7 | 1257 | "date"); |
7d932dfd | 1258 | |
ddf0fd9a DW |
1259 | #ifdef CONFIG_XEN_EMU |
1260 | if (xen_mode == XEN_EMULATE) { | |
eeedfe6c DW |
1261 | xen_overlay_create(); |
1262 | xen_evtchn_create(IOAPIC_NUM_PINS, gsi); | |
1263 | xen_gnttab_create(); | |
1264 | xen_xenstore_create(); | |
bdfdb748 DW |
1265 | if (pcms->bus) { |
1266 | pci_create_simple(pcms->bus, -1, "xen-platform"); | |
1267 | } | |
c10b4b3c | 1268 | pcms->xenbus = xen_bus_init(); |
a78c54c4 | 1269 | xen_be_init(); |
ddf0fd9a DW |
1270 | } |
1271 | #endif | |
1272 | ||
87af48a4 | 1273 | qemu_register_boot_set(pc_boot_set, rtc_state); |
7d932dfd | 1274 | |
9dee7e51 XL |
1275 | if (!xen_enabled() && |
1276 | (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { | |
15eafc2e | 1277 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1278 | pit = kvm_pit_init(isa_bus, 0x40); |
1279 | } else { | |
acf695ec | 1280 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1281 | } |
1282 | if (hpet) { | |
1283 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1284 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 | 1285 | } |
40f8214f PMD |
1286 | object_property_set_link(OBJECT(pcms->pcspk), "pit", |
1287 | OBJECT(pit), &error_fatal); | |
1288 | isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); | |
ce967e2f | 1289 | } |
ffe513da | 1290 | |
ac64273c | 1291 | /* Super I/O */ |
4ccd5fe2 JD |
1292 | pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, |
1293 | pcms->vmport != ON_OFF_AUTO_ON); | |
ffe513da IY |
1294 | } |
1295 | ||
c10b4b3c DW |
1296 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus, |
1297 | BusState *xen_bus) | |
9011a1a7 | 1298 | { |
01ecdaa4 | 1299 | MachineClass *mc = MACHINE_CLASS(pcmc); |
9011a1a7 IY |
1300 | int i; |
1301 | ||
bab47d9a | 1302 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1303 | for (i = 0; i < nb_nics; i++) { |
1304 | NICInfo *nd = &nd_table[i]; | |
01ecdaa4 | 1305 | const char *model = nd->model ? nd->model : mc->default_nic; |
9011a1a7 | 1306 | |
c10b4b3c DW |
1307 | if (xen_bus && (!nd->model || g_str_equal(model, "xen-net-device"))) { |
1308 | DeviceState *dev = qdev_new("xen-net-device"); | |
1309 | qdev_set_nic_properties(dev, nd); | |
1310 | qdev_realize_and_unref(dev, xen_bus, &error_fatal); | |
1311 | } else if (g_str_equal(model, "ne2k_isa")) { | |
9011a1a7 IY |
1312 | pc_init_ne2k_isa(isa_bus, nd); |
1313 | } else { | |
4b9c264b | 1314 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1315 | } |
1316 | } | |
bab47d9a | 1317 | rom_reset_order_override(); |
9011a1a7 IY |
1318 | } |
1319 | ||
4501d317 PMD |
1320 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1321 | { | |
1322 | qemu_irq *i8259; | |
1323 | ||
1324 | if (kvm_pic_in_kernel()) { | |
1325 | i8259 = kvm_i8259_init(isa_bus); | |
1326 | } else if (xen_enabled()) { | |
1327 | i8259 = xen_interrupt_controller_init(); | |
1328 | } else { | |
89a289c7 | 1329 | i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); |
4501d317 PMD |
1330 | } |
1331 | ||
1332 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1333 | i8259_irqs[i] = i8259[i]; | |
1334 | } | |
1335 | ||
1336 | g_free(i8259); | |
1337 | } | |
1338 | ||
d468115b DH |
1339 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1340 | Error **errp) | |
1341 | { | |
1342 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
50aef131 | 1343 | const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
b0e62443 | 1344 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1345 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1346 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1347 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1348 | Error *local_err = NULL; |
d468115b DH |
1349 | |
1350 | /* | |
1351 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1352 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1353 | * addition to cover this case. | |
1354 | */ | |
50aef131 | 1355 | if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { |
d468115b DH |
1356 | error_setg(errp, |
1357 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1358 | return; | |
1359 | } | |
1360 | ||
f6a0d06b | 1361 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1362 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1363 | return; | |
1364 | } | |
8f1ffe5b | 1365 | |
50aef131 | 1366 | hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); |
ae909496 TH |
1367 | if (local_err) { |
1368 | error_propagate(errp, local_err); | |
1369 | return; | |
1370 | } | |
1371 | ||
fd3416f5 | 1372 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1373 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1374 | } |
1375 | ||
bb6e2f7a DH |
1376 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1377 | DeviceState *dev, Error **errp) | |
95bee274 | 1378 | { |
95bee274 | 1379 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
50aef131 | 1380 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
f6a0d06b | 1381 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1382 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1383 | |
84fd5496 | 1384 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); |
b8865591 | 1385 | |
7f3cf2d6 | 1386 | if (is_nvdimm) { |
f6a0d06b | 1387 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1388 | } |
1389 | ||
50aef131 | 1390 | hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); |
95bee274 IM |
1391 | } |
1392 | ||
bb6e2f7a DH |
1393 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1394 | DeviceState *dev, Error **errp) | |
64fec58e | 1395 | { |
50aef131 | 1396 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
64fec58e | 1397 | |
8cd91ace HZ |
1398 | /* |
1399 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1400 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1401 | * addition to cover this case. | |
1402 | */ | |
50aef131 | 1403 | if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { |
dcfe4805 | 1404 | error_setg(errp, |
8cd91ace | 1405 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
dcfe4805 | 1406 | return; |
64fec58e TC |
1407 | } |
1408 | ||
b097cc52 | 1409 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
dcfe4805 MA |
1410 | error_setg(errp, "nvdimm device hot unplug is not supported yet."); |
1411 | return; | |
b097cc52 XG |
1412 | } |
1413 | ||
50aef131 | 1414 | hotplug_handler_unplug_request(x86ms->acpi_dev, dev, |
dcfe4805 | 1415 | errp); |
64fec58e TC |
1416 | } |
1417 | ||
bb6e2f7a DH |
1418 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1419 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1420 | { |
1421 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
50aef131 | 1422 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
f7d3e29d TC |
1423 | Error *local_err = NULL; |
1424 | ||
50aef131 | 1425 | hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); |
f7d3e29d TC |
1426 | if (local_err) { |
1427 | goto out; | |
1428 | } | |
1429 | ||
fd3416f5 | 1430 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
981c3dcd | 1431 | qdev_unrealize(dev); |
f7d3e29d TC |
1432 | out: |
1433 | error_propagate(errp, local_err); | |
1434 | } | |
1435 | ||
9a52aa40 MS |
1436 | static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, |
1437 | DeviceState *dev, Error **errp) | |
1438 | { | |
1439 | /* The vmbus handler has no hotplug handler; we should never end up here. */ | |
1440 | g_assert(!dev->hotplugged); | |
1441 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1442 | errp); | |
1443 | } | |
1444 | ||
1445 | static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, | |
1446 | DeviceState *dev, Error **errp) | |
1447 | { | |
1448 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1449 | } | |
1450 | ||
4ec60c76 IM |
1451 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1452 | DeviceState *dev, Error **errp) | |
1453 | { | |
d468115b DH |
1454 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1455 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1456 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
0cca1a91 | 1457 | x86_cpu_pre_plug(hotplug_dev, dev, errp); |
dbdf841b DH |
1458 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
1459 | virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
36efa250 JPB |
1460 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
1461 | /* Declare the APIC range as the reserved MSI region */ | |
1462 | char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", | |
1463 | VIRTIO_IOMMU_RESV_MEM_T_MSI); | |
33f0c061 KW |
1464 | QList *reserved_regions = qlist_new(); |
1465 | ||
1466 | qlist_append_str(reserved_regions, resv_prop_str); | |
1467 | qdev_prop_set_array(dev, "reserved-regions", reserved_regions); | |
36efa250 | 1468 | |
36efa250 JPB |
1469 | g_free(resv_prop_str); |
1470 | } | |
1471 | ||
1472 | if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || | |
1473 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | |
1b3bf138 JPB |
1474 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1475 | ||
1476 | if (pcms->iommu) { | |
1477 | error_setg(errp, "QEMU does not support multiple vIOMMUs " | |
1478 | "for x86 yet."); | |
1479 | return; | |
1480 | } | |
1481 | pcms->iommu = dev; | |
9a52aa40 MS |
1482 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { |
1483 | pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1484 | } |
1485 | } | |
1486 | ||
95bee274 IM |
1487 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1488 | DeviceState *dev, Error **errp) | |
1489 | { | |
1490 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1491 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e | 1492 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1493 | x86_cpu_plug(hotplug_dev, dev, errp); |
dbdf841b DH |
1494 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
1495 | virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
9a52aa40 MS |
1496 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { |
1497 | pc_hv_balloon_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1498 | } |
1499 | } | |
1500 | ||
d9c5c5b8 TC |
1501 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1502 | DeviceState *dev, Error **errp) | |
1503 | { | |
64fec58e | 1504 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1505 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a | 1506 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1507 | x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); |
dbdf841b DH |
1508 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
1509 | virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), | |
1510 | errp); | |
64fec58e TC |
1511 | } else { |
1512 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1513 | " type: %s", object_get_typename(OBJECT(dev))); | |
1514 | } | |
d9c5c5b8 TC |
1515 | } |
1516 | ||
232391c1 TC |
1517 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1518 | DeviceState *dev, Error **errp) | |
1519 | { | |
f7d3e29d | 1520 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1521 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a | 1522 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1523 | x86_cpu_unplug_cb(hotplug_dev, dev, errp); |
dbdf841b DH |
1524 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
1525 | virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
f7d3e29d TC |
1526 | } else { |
1527 | error_setg(errp, "acpi: device unplug for not supported device" | |
1528 | " type: %s", object_get_typename(OBJECT(dev))); | |
1529 | } | |
232391c1 TC |
1530 | } |
1531 | ||
285816d7 | 1532 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
1533 | DeviceState *dev) |
1534 | { | |
5279569e | 1535 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 | 1536 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
dbdf841b | 1537 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || |
36efa250 | 1538 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || |
9a52aa40 | 1539 | object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || |
1b3bf138 | 1540 | object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { |
95bee274 IM |
1541 | return HOTPLUG_HANDLER(machine); |
1542 | } | |
1543 | ||
38aefb57 | 1544 | return NULL; |
95bee274 IM |
1545 | } |
1546 | ||
d7bce999 EB |
1547 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
1548 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1549 | { |
1550 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 1551 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 1552 | |
51e72bc1 | 1553 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
1554 | } |
1555 | ||
d7bce999 EB |
1556 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
1557 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1558 | { |
1559 | PCMachineState *pcms = PC_MACHINE(obj); | |
1560 | ||
51e72bc1 | 1561 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
1562 | } |
1563 | ||
be232eb0 CP |
1564 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
1565 | { | |
1566 | PCMachineState *pcms = PC_MACHINE(obj); | |
1567 | ||
f5878b03 | 1568 | return pcms->smbus_enabled; |
be232eb0 CP |
1569 | } |
1570 | ||
1571 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
1572 | { | |
1573 | PCMachineState *pcms = PC_MACHINE(obj); | |
1574 | ||
f5878b03 | 1575 | pcms->smbus_enabled = value; |
be232eb0 CP |
1576 | } |
1577 | ||
272f0428 CP |
1578 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
1579 | { | |
1580 | PCMachineState *pcms = PC_MACHINE(obj); | |
1581 | ||
f5878b03 | 1582 | return pcms->sata_enabled; |
272f0428 CP |
1583 | } |
1584 | ||
1585 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
1586 | { | |
1587 | PCMachineState *pcms = PC_MACHINE(obj); | |
1588 | ||
f5878b03 | 1589 | pcms->sata_enabled = value; |
272f0428 CP |
1590 | } |
1591 | ||
0259c78c EH |
1592 | static bool pc_machine_get_hpet(Object *obj, Error **errp) |
1593 | { | |
1594 | PCMachineState *pcms = PC_MACHINE(obj); | |
1595 | ||
1596 | return pcms->hpet_enabled; | |
1597 | } | |
1598 | ||
1599 | static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) | |
1600 | { | |
1601 | PCMachineState *pcms = PC_MACHINE(obj); | |
1602 | ||
1603 | pcms->hpet_enabled = value; | |
1604 | } | |
1605 | ||
4ccd5fe2 JD |
1606 | static bool pc_machine_get_i8042(Object *obj, Error **errp) |
1607 | { | |
1608 | PCMachineState *pcms = PC_MACHINE(obj); | |
1609 | ||
1610 | return pcms->i8042_enabled; | |
1611 | } | |
1612 | ||
1613 | static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) | |
1614 | { | |
1615 | PCMachineState *pcms = PC_MACHINE(obj); | |
1616 | ||
1617 | pcms->i8042_enabled = value; | |
1618 | } | |
1619 | ||
c9e96b04 XW |
1620 | static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) |
1621 | { | |
1622 | PCMachineState *pcms = PC_MACHINE(obj); | |
1623 | ||
1624 | return pcms->default_bus_bypass_iommu; | |
1625 | } | |
1626 | ||
1627 | static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, | |
1628 | Error **errp) | |
1629 | { | |
1630 | PCMachineState *pcms = PC_MACHINE(obj); | |
1631 | ||
1632 | pcms->default_bus_bypass_iommu = value; | |
1633 | } | |
1634 | ||
0e4edb3b EH |
1635 | static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, |
1636 | void *opaque, Error **errp) | |
1637 | { | |
1638 | PCMachineState *pcms = PC_MACHINE(obj); | |
1639 | SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; | |
1640 | ||
1641 | visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); | |
1642 | } | |
1643 | ||
1644 | static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, | |
1645 | void *opaque, Error **errp) | |
1646 | { | |
1647 | PCMachineState *pcms = PC_MACHINE(obj); | |
1648 | ||
1649 | visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); | |
1650 | } | |
1651 | ||
9a45729d GH |
1652 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
1653 | const char *name, void *opaque, | |
1654 | Error **errp) | |
1655 | { | |
1656 | PCMachineState *pcms = PC_MACHINE(obj); | |
1657 | uint64_t value = pcms->max_ram_below_4g; | |
1658 | ||
1659 | visit_type_size(v, name, &value, errp); | |
1660 | } | |
1661 | ||
1662 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
1663 | const char *name, void *opaque, | |
1664 | Error **errp) | |
1665 | { | |
1666 | PCMachineState *pcms = PC_MACHINE(obj); | |
9a45729d GH |
1667 | uint64_t value; |
1668 | ||
668f62ec | 1669 | if (!visit_type_size(v, name, &value, errp)) { |
9a45729d GH |
1670 | return; |
1671 | } | |
1672 | if (value > 4 * GiB) { | |
dcfe4805 | 1673 | error_setg(errp, |
9a45729d GH |
1674 | "Machine option 'max-ram-below-4g=%"PRIu64 |
1675 | "' expects size less than or equal to 4G", value); | |
9a45729d GH |
1676 | return; |
1677 | } | |
1678 | ||
1679 | if (value < 1 * MiB) { | |
1680 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," | |
1681 | "BIOS may not work with less than 1MiB", value); | |
1682 | } | |
1683 | ||
1684 | pcms->max_ram_below_4g = value; | |
1685 | } | |
1686 | ||
0657c657 EM |
1687 | static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, |
1688 | const char *name, void *opaque, | |
1689 | Error **errp) | |
1690 | { | |
1691 | PCMachineState *pcms = PC_MACHINE(obj); | |
1692 | uint64_t value = pcms->max_fw_size; | |
1693 | ||
1694 | visit_type_size(v, name, &value, errp); | |
1695 | } | |
1696 | ||
1697 | static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, | |
1698 | const char *name, void *opaque, | |
1699 | Error **errp) | |
1700 | { | |
1701 | PCMachineState *pcms = PC_MACHINE(obj); | |
0657c657 EM |
1702 | uint64_t value; |
1703 | ||
d1c81c34 | 1704 | if (!visit_type_size(v, name, &value, errp)) { |
0657c657 EM |
1705 | return; |
1706 | } | |
1707 | ||
1708 | /* | |
306764ee LE |
1709 | * We don't have a theoretically justifiable exact lower bound on the base |
1710 | * address of any flash mapping. In practice, the IO-APIC MMIO range is | |
1711 | * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free | |
1712 | * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to | |
1713 | * 16MiB in size. | |
1714 | */ | |
0657c657 EM |
1715 | if (value > 16 * MiB) { |
1716 | error_setg(errp, | |
1717 | "User specified max allowed firmware size %" PRIu64 " is " | |
bad5cfcd | 1718 | "greater than 16MiB. If combined firmware size exceeds " |
0657c657 EM |
1719 | "16MiB the system may not boot, or experience intermittent" |
1720 | "stability issues.", | |
1721 | value); | |
1722 | return; | |
1723 | } | |
1724 | ||
1725 | pcms->max_fw_size = value; | |
1726 | } | |
1727 | ||
602b4582 | 1728 | |
bf1e8939 IM |
1729 | static void pc_machine_initfn(Object *obj) |
1730 | { | |
c87b1520 | 1731 | PCMachineState *pcms = PC_MACHINE(obj); |
bf376f30 | 1732 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
c87b1520 | 1733 | |
97fd1ea8 | 1734 | #ifdef CONFIG_VMPORT |
d1048bef | 1735 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
1736 | #else |
1737 | pcms->vmport = ON_OFF_AUTO_OFF; | |
1738 | #endif /* CONFIG_VMPORT */ | |
9a45729d | 1739 | pcms->max_ram_below_4g = 0; /* use default */ |
bf376f30 | 1740 | pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; |
aa0c9aec | 1741 | pcms->south_bridge = pcmc->default_south_bridge; |
0e4edb3b | 1742 | |
021746c1 | 1743 | /* acpi build is enabled by default if machine supports it */ |
abe10037 | 1744 | pcms->acpi_build_enabled = pcmc->has_acpi_build; |
f5878b03 CM |
1745 | pcms->smbus_enabled = true; |
1746 | pcms->sata_enabled = true; | |
4ccd5fe2 | 1747 | pcms->i8042_enabled = true; |
0657c657 | 1748 | pcms->max_fw_size = 8 * MiB; |
0259c78c EH |
1749 | #ifdef CONFIG_HPET |
1750 | pcms->hpet_enabled = true; | |
1751 | #endif | |
c9e96b04 | 1752 | pcms->default_bus_bypass_iommu = false; |
ebc29e1b MA |
1753 | |
1754 | pc_system_flash_create(pcms); | |
6b8d1416 | 1755 | pcms->pcspk = isa_new(TYPE_PC_SPEAKER); |
2e16ec05 GH |
1756 | object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", |
1757 | OBJECT(pcms->pcspk), "audiodev"); | |
1ebf9001 | 1758 | cxl_machine_init(obj, &pcms->cxl_devices_state); |
bf1e8939 IM |
1759 | } |
1760 | ||
e21be724 DW |
1761 | int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) |
1762 | { | |
e21be724 DW |
1763 | return 0; |
1764 | } | |
1765 | ||
7966d70f | 1766 | static void pc_machine_reset(MachineState *machine, ShutdownCause reason) |
ae50c55a ZG |
1767 | { |
1768 | CPUState *cs; | |
1769 | X86CPU *cpu; | |
1770 | ||
7966d70f | 1771 | qemu_devices_reset(reason); |
ae50c55a ZG |
1772 | |
1773 | /* Reset APIC after devices have been reset to cancel | |
1774 | * any changes that qemu_devices_reset() might have done. | |
1775 | */ | |
1776 | CPU_FOREACH(cs) { | |
1777 | cpu = X86_CPU(cs); | |
1778 | ||
ec19444a | 1779 | x86_cpu_after_reset(cpu); |
ae50c55a ZG |
1780 | } |
1781 | } | |
1782 | ||
c508bd12 NP |
1783 | static void pc_machine_wakeup(MachineState *machine) |
1784 | { | |
1785 | cpu_synchronize_all_states(); | |
7966d70f | 1786 | pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); |
c508bd12 NP |
1787 | cpu_synchronize_all_post_reset(); |
1788 | } | |
1789 | ||
c6cbc29d PX |
1790 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
1791 | { | |
1792 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
1793 | IntelIOMMUState *intel_iommu; | |
1794 | ||
1795 | if (iommu && | |
1796 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
1797 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
1798 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
1799 | if (!intel_iommu->caching_mode) { | |
1800 | error_setg(errp, "Device assignment is not allowed without " | |
1801 | "enabling caching-mode=on for Intel IOMMU."); | |
1802 | return false; | |
1803 | } | |
1804 | } | |
1805 | ||
1806 | return true; | |
1807 | } | |
1808 | ||
95bee274 IM |
1809 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1810 | { | |
1811 | MachineClass *mc = MACHINE_CLASS(oc); | |
1812 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1813 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1814 | ||
7102fa70 EH |
1815 | pcmc->pci_enabled = true; |
1816 | pcmc->has_acpi_build = true; | |
1817 | pcmc->rsdp_in_ram = true; | |
1818 | pcmc->smbios_defaults = true; | |
1819 | pcmc->smbios_uuid_encoded = true; | |
1820 | pcmc->gigabyte_align = true; | |
1821 | pcmc->has_reserved_memory = true; | |
1822 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 1823 | pcmc->enforce_aligned_dimm = true; |
b3e6982b | 1824 | pcmc->enforce_amd_1tb_hole = true; |
cd4040ec EH |
1825 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
1826 | * to be used at the moment, 32K should be enough for a while. */ | |
1827 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
fda672b5 | 1828 | pcmc->pvh_enabled = true; |
8700a984 | 1829 | pcmc->kvmclock_create_always = true; |
1af50775 | 1830 | pcmc->resizable_acpi_blob = true; |
debbdc00 | 1831 | assert(!mc->get_hotplug_handler); |
285816d7 | 1832 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 1833 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
1834 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
1835 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
1836 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 1837 | mc->auto_enable_numa_with_memhp = true; |
195784a0 | 1838 | mc->auto_enable_numa_with_memdev = true; |
c5514d0e | 1839 | mc->has_hotpluggable_cpus = true; |
41742767 | 1840 | mc->default_boot_order = "cad"; |
2059839b | 1841 | mc->block_default_type = IF_IDE; |
4458fb3a | 1842 | mc->max_cpus = 255; |
ae50c55a | 1843 | mc->reset = pc_machine_reset; |
c508bd12 | 1844 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 1845 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 1846 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 1847 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 1848 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 1849 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 1850 | mc->nvdimm_supported = true; |
e4a97a89 | 1851 | mc->smp_props.dies_supported = true; |
bd457782 | 1852 | mc->default_ram_id = "pc.ram"; |
bf376f30 | 1853 | pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; |
0efc257d | 1854 | |
9a45729d GH |
1855 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", |
1856 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
1857 | NULL, NULL); | |
1858 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
1859 | "Maximum ram below the 4G boundary (32bit boundary)"); | |
1860 | ||
0efc257d EH |
1861 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", |
1862 | pc_machine_get_vmport, pc_machine_set_vmport, | |
d2623129 | 1863 | NULL, NULL); |
0efc257d | 1864 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, |
7eecec7d | 1865 | "Enable vmport (pc & q35)"); |
0efc257d | 1866 | |
be232eb0 | 1867 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
d2623129 | 1868 | pc_machine_get_smbus, pc_machine_set_smbus); |
44bff376 TH |
1869 | object_class_property_set_description(oc, PC_MACHINE_SMBUS, |
1870 | "Enable/disable system management bus"); | |
272f0428 CP |
1871 | |
1872 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
d2623129 | 1873 | pc_machine_get_sata, pc_machine_set_sata); |
44bff376 TH |
1874 | object_class_property_set_description(oc, PC_MACHINE_SATA, |
1875 | "Enable/disable Serial ATA bus"); | |
feddd2fd | 1876 | |
0259c78c EH |
1877 | object_class_property_add_bool(oc, "hpet", |
1878 | pc_machine_get_hpet, pc_machine_set_hpet); | |
44bff376 TH |
1879 | object_class_property_set_description(oc, "hpet", |
1880 | "Enable/disable high precision event timer emulation"); | |
0657c657 | 1881 | |
4ccd5fe2 JD |
1882 | object_class_property_add_bool(oc, PC_MACHINE_I8042, |
1883 | pc_machine_get_i8042, pc_machine_set_i8042); | |
1884 | ||
739b3863 | 1885 | object_class_property_add_bool(oc, "default-bus-bypass-iommu", |
c9e96b04 XW |
1886 | pc_machine_get_default_bus_bypass_iommu, |
1887 | pc_machine_set_default_bus_bypass_iommu); | |
1888 | ||
0657c657 EM |
1889 | object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", |
1890 | pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, | |
1891 | NULL, NULL); | |
1892 | object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, | |
1893 | "Maximum combined firmware size"); | |
0e4edb3b EH |
1894 | |
1895 | object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", | |
1896 | pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, | |
1897 | NULL, NULL); | |
1898 | object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, | |
1899 | "SMBIOS Entry Point type [32, 64]"); | |
95bee274 IM |
1900 | } |
1901 | ||
d5747cac IM |
1902 | static const TypeInfo pc_machine_info = { |
1903 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 1904 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
1905 | .abstract = true, |
1906 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 1907 | .instance_init = pc_machine_initfn, |
d5747cac | 1908 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
1909 | .class_init = pc_machine_class_init, |
1910 | .interfaces = (InterfaceInfo[]) { | |
1911 | { TYPE_HOTPLUG_HANDLER }, | |
1912 | { } | |
1913 | }, | |
d5747cac IM |
1914 | }; |
1915 | ||
1916 | static void pc_machine_register_types(void) | |
1917 | { | |
1918 | type_register_static(&pc_machine_info); | |
1919 | } | |
1920 | ||
1921 | type_init(pc_machine_register_types) |