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vfio: Alphabetize migration section of VFIO trace-events file
[mirror_qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
549e984e 27#include "hw/i386/x86.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293 32#include "hw/i386/topology.h"
87abaa5d 33#include "hw/i386/fw_cfg.h"
d8f23d61 34#include "hw/i386/vmport.h"
54a40293 35#include "sysemu/cpus.h"
0d09e41a 36#include "hw/block/fdc.h"
83c9f4ca
PB		 37#include "hw/ide.h"
38#include "hw/pci/pci.h"
2118196b 39#include "hw/pci/pci_bus.h"
7bd1900b 40#include "hw/pci-bridge/pci_expander_bridge.h"
0d09e41a
PB		 41#include "hw/nvram/fw_cfg.h"
42#include "hw/timer/hpet.h"
a2eb5c0c 43#include "hw/firmware/smbios.h"
83c9f4ca 44#include "hw/loader.h"
ca20cf32 45#include "elf.h"
d6454270 46#include "migration/vmstate.h"
47b43a1f 47#include "multiboot.h"
bcdb9064 48#include "hw/rtc/mc146818rtc.h"
852c27e2 49#include "hw/intc/i8259.h"
0d09e41a 50#include "hw/timer/i8254.h"
47973a2d 51#include "hw/input/i8042.h"
64552b6b 52#include "hw/irq.h"
0d09e41a 53#include "hw/audio/pcspk.h"
83c9f4ca
PB		 54#include "hw/pci/msi.h"
55#include "hw/sysbus.h"
9c17d615 56#include "sysemu/sysemu.h"
14a48c1d 57#include "sysemu/tcg.h"
e35704ba 58#include "sysemu/numa.h"
9c17d615 59#include "sysemu/kvm.h"
da278d58 60#include "sysemu/xen.h"
71e8a915 61#include "sysemu/reset.h"
54d31236 62#include "sysemu/runstate.h"
a9dc68d9 63#include "kvm/kvm_i386.h"
0d09e41a 64#include "hw/xen/xen.h"
ab969087 65#include "hw/xen/start_info.h"
a19cbfb3 66#include "ui/qemu-spice.h"
022c62cb 67#include "exec/memory.h"
1de7afc9 68#include "qemu/bitmap.h"
0c764a9d 69#include "qemu/config-file.h"
d49b6836 70#include "qemu/error-report.h"
922a01a0 71#include "qemu/option.h"
133ef074 72#include "qemu/cutils.h"
0445259b 73#include "hw/acpi/acpi.h"
5ff020b7 74#include "hw/acpi/cpu_hotplug.h"
72c194f7 75#include "acpi-build.h"
95bee274 76#include "hw/mem/pc-dimm.h"
4b997690 77#include "hw/mem/nvdimm.h"
6e4e3ae9 78#include "hw/cxl/cxl.h"
03b39fcf 79#include "hw/cxl/cxl_host.h"
e688df6b 80#include "qapi/error.h"
9af23989 81#include "qapi/qapi-visit-common.h"
0e4edb3b 82#include "qapi/qapi-visit-machine.h"
bf1e8939 83#include "qapi/visitor.h"
2e5b09fd 84#include "hw/core/cpu.h"
a310e653 85#include "hw/usb.h"
60c5e104 86#include "hw/i386/intel_iommu.h"
489983d6 87#include "hw/net/ne2000-isa.h"
06e0259a 88#include "standard-headers/asm-x86/bootparam.h"
36efa250 89#include "hw/virtio/virtio-iommu.h"
a0a49813 90#include "hw/virtio/virtio-pmem-pci.h"
0ed48fd3 91#include "hw/virtio/virtio-mem-pci.h"
a0a49813 92#include "hw/mem/memory-device.h"
6f479566 93#include "sysemu/replay.h"
ec19444a 94#include "target/i386/cpu.h"
6f479566 95#include "qapi/qmp/qerror.h"
d6d059ca 96#include "e820_memory_layout.h"
149c50ca 97#include "fw_cfg.h"
4ca8dabd 98#include "trace.h"
2becc36a 99#include CONFIG_DEVICES
471fd342 100
fc5f8923
BB		 101/*
102 * Helper for setting model-id for CPU models that changed model-id
103 * depending on QEMU versions up to QEMU 2.4.
104 */
105#define PC_CPU_MODEL_IDS(v) \
106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
109
a6b6414f
DB		 110GlobalProperty pc_compat_7_2[] = {
111 { "ICH9-LPC", "noreboot", "true" },
112};
db723c80
CH		 113const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
114
f514e147
CH		 115GlobalProperty pc_compat_7_1[] = {};
116const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
117
0ca70366
CH		 118GlobalProperty pc_compat_7_0[] = {};
119const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
120
60f1f77c
DH		 121GlobalProperty pc_compat_6_2[] = {
122 { "virtio-mem", "unplugged-inaccessible", "off" },
123};
01854af2
CH		 124const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
125
f701ecec
VK		 126GlobalProperty pc_compat_6_1[] = {
127 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
128 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
129 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
c318bef7 130 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
f701ecec 131};
52e64f5b
YW		 132const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
133
b7c29017
DB		 134GlobalProperty pc_compat_6_0[] = {
135 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
136 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
137 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
a7a0da84 138 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
aa29466b 139 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
c318bef7 140 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
b7c29017 141};
da7e13c0
CH		 142const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
143
7ed3e1eb
IM		 144GlobalProperty pc_compat_5_2[] = {
145 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
146};
576a00bd
CH		 147const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
148
00dc02d2
IM		 149GlobalProperty pc_compat_5_1[] = {
150 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
c1bb5418 151 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
00dc02d2 152};
3ff3c5d3
CH		 153const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
154
2ebc2121
HW		 155GlobalProperty pc_compat_5_0[] = {
156};
541aaa1d
CH		 157const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
158
f404220e
IM		 159GlobalProperty pc_compat_4_2[] = {
160 { "mch", "smbase-smram", "off" },
161};
3eb74d20
CH		 162const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
163
9aec2e52
CH		 164GlobalProperty pc_compat_4_1[] = {};
165const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
166
9bf2650b
CH		 167GlobalProperty pc_compat_4_0[] = {};
168const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
169
abd93cc7 170GlobalProperty pc_compat_3_1[] = {
6c36bddf 171 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 172 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
173 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 174 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
175 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 176 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 177 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
178 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
179 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
180 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
182 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 183 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
184 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
185 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
186 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
187 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
188 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
189 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 190 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 191 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 192};
193const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
194
ddb3235d 195GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 196 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
197 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
198 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 199};
200const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
201
0d47310b 202GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 203 { TYPE_X86_CPU, "legacy-cache", "on" },
204 { TYPE_X86_CPU, "topoext", "off" },
205 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
206 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 207};
208const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
209
43df70a9 210GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 211 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
212 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 213};
214const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
215
503224f4 216GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 217 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
218 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
219 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 220};
221const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
222
3e803152 223GlobalProperty pc_compat_2_9[] = {
6c36bddf 224 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 225};
226const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
227
edc24ccd 228GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 229 { TYPE_X86_CPU, "tcg-cpuid", "off" },
230 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
231 { "ICH9-LPC", "x-smi-broadcast", "off" },
232 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
233 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 234};
235const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
236
5a995064 237GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 238 { TYPE_X86_CPU, "l3-cache", "off" },
239 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
240 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
241 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
242 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
243 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 244};
245const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
246
ff8f261f 247GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 248 { TYPE_X86_CPU, "cpuid-0xb", "off" },
249 { "vmxnet3", "romfile", "" },
250 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
251 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 252};
253const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
254
fe759610
MAL		 255GlobalProperty pc_compat_2_5[] = {};
256const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
257
2f99b9c2
MAL		 258GlobalProperty pc_compat_2_4[] = {
259 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 260 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
261 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
262 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
263 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
264 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
265 { TYPE_X86_CPU, "check", "off" },
266 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
267 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
268 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
269 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
270 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
271 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
272 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
273 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 274};
275const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
276
8995dd90
MAL		 277GlobalProperty pc_compat_2_3[] = {
278 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 279 { TYPE_X86_CPU, "arat", "off" },
280 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
281 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
282 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
283 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
284 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
285 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
286 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
287 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
291 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
292 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
293 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
294 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
295 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
296 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
297 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
298 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 299};
300const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
301
1c30044e
MAL		 302GlobalProperty pc_compat_2_2[] = {
303 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 304 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
305 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
306 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
307 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
308 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
309 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
310 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
311 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
312 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
313 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
314 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
315 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
316 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
317 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
318 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
319 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
320 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
321 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 322};
323const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
324
c4fc5695
MAL		 325GlobalProperty pc_compat_2_1[] = {
326 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 327 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
328 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 329};
330const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
331
a310e653
MAL		 332GlobalProperty pc_compat_2_0[] = {
333 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 334 { "virtio-scsi-pci", "any_layout", "off" },
335 { "PIIX4_PM", "memory-hotplug-support", "off" },
336 { "apic", "version", "0x11" },
337 { "nec-usb-xhci", "superspeed-ports-first", "off" },
338 { "nec-usb-xhci", "force-pcie-endcap", "on" },
339 { "pci-serial", "prog_if", "0" },
340 { "pci-serial-2x", "prog_if", "0" },
341 { "pci-serial-4x", "prog_if", "0" },
342 { "virtio-net-pci", "guest_announce", "off" },
343 { "ICH9-LPC", "memory-hotplug-support", "off" },
a310e653
MAL		 344};
345const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
346
347GlobalProperty pc_compat_1_7[] = {
348 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf 349 { TYPE_USB_DEVICE, "msos-desc", "no" },
aa29466b 350 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
6c36bddf 351 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 352};
353const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
354
355GlobalProperty pc_compat_1_6[] = {
356 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 357 { "e1000", "mitigation", "off" },
358 { "qemu64-" TYPE_X86_CPU, "model", "2" },
359 { "qemu32-" TYPE_X86_CPU, "model", "3" },
360 { "i440FX-pcihost", "short_root_bus", "1" },
361 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 362};
363const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
364
365GlobalProperty pc_compat_1_5[] = {
366 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 367 { "Conroe-" TYPE_X86_CPU, "model", "2" },
368 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
369 { "Penryn-" TYPE_X86_CPU, "model", "2" },
370 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
371 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
372 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
373 { "virtio-net-pci", "any_layout", "off" },
374 { TYPE_X86_CPU, "pmu", "on" },
375 { "i440FX-pcihost", "short_root_bus", "0" },
376 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 377};
378const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
379
380GlobalProperty pc_compat_1_4[] = {
381 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 382 { "scsi-hd", "discard_granularity", "0" },
383 { "scsi-cd", "discard_granularity", "0" },
6c36bddf
EH		 384 { "ide-hd", "discard_granularity", "0" },
385 { "ide-cd", "discard_granularity", "0" },
6c36bddf
EH		 386 { "virtio-blk-pci", "discard_granularity", "0" },
387 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
388 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
389 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
390 { "e1000", "romfile", "pxe-e1000.rom" },
391 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
392 { "pcnet", "romfile", "pxe-pcnet.rom" },
393 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
394 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
395 { "486-" TYPE_X86_CPU, "model", "0" },
396 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
397 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 398};
399const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
400
417258f1
PMD		 401GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
402{
403 GSIState *s;
404
405 s = g_new0(GSIState, 1);
406 if (kvm_ioapic_in_kernel()) {
407 kvm_pc_setup_irq_routing(pci_enabled);
417258f1 408 }
64c033ba 409 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
417258f1
PMD		 410
411 return s;
412}
413
258711c6
JG		 414static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
415 unsigned size)
80cabfad
FB		 416{
417}
418
c02e1eac
JG		 419static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
420{
a6fc23e5 421 return 0xffffffffffffffffULL;
c02e1eac
JG		 422}
423
f929aad6 424/* MSDOS compatibility mode FPU exception support */
258711c6
JG		 425static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
426 unsigned size)
f929aad6 427{
6f529b75 428 if (tcg_enabled()) {
bf13bfab 429 cpu_set_ignne();
6f529b75 430 }
f929aad6
FB		 431}
432
c02e1eac
JG		 433static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
434{
a6fc23e5 435 return 0xffffffffffffffffULL;
c02e1eac
JG		 436}
437
b0a21b53
FB		 438/* PC cmos mappings */
439
80cabfad
FB		 440#define REG_EQUIPMENT_BYTE 0x14
441
9139046c
MA		 442static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
443 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 444{
ba6c2377
FB		 445 rtc_set_memory(s, type_ofs, 47);
446 rtc_set_memory(s, info_ofs, cylinders);
447 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
448 rtc_set_memory(s, info_ofs + 2, heads);
449 rtc_set_memory(s, info_ofs + 3, 0xff);
450 rtc_set_memory(s, info_ofs + 4, 0xff);
451 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
452 rtc_set_memory(s, info_ofs + 6, cylinders);
453 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
454 rtc_set_memory(s, info_ofs + 8, sectors);
455}
456
6ac0e82d
AZ		 457/* convert boot_device letter to something recognizable by the bios */
458static int boot_device2nibble(char boot_device)
459{
460 switch(boot_device) {
461 case 'a':
462 case 'b':
463 return 0x01; /* floppy boot */
464 case 'c':
465 return 0x02; /* hard drive boot */
466 case 'd':
467 return 0x03; /* CD-ROM boot */
468 case 'n':
469 return 0x04; /* Network boot */
470 }
471 return 0;
472}
473
ddcd5531 474static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 475{
476#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 477 int nbds, bds[3] = { 0, };
478 int i;
479
480 nbds = strlen(boot_device);
481 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 482 error_setg(errp, "Too many boot devices for PC");
483 return;
0ecdffbb
AJ		 484 }
485 for (i = 0; i < nbds; i++) {
486 bds[i] = boot_device2nibble(boot_device[i]);
487 if (bds[i] == 0) {
ddcd5531
GA		 488 error_setg(errp, "Invalid boot device for PC: '%c'",
489 boot_device[i]);
490 return;
0ecdffbb
AJ		 491 }
492 }
493 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 494 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 495}
496
ddcd5531 497static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 498{
ddcd5531 499 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 500}
501
7444ca4e
LE		 502static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
503{
504 int val, nb, i;
2da44dd0
JS		 505 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
506 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 507
508 /* floppy type */
509 if (floppy) {
510 for (i = 0; i < 2; i++) {
511 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
512 }
513 }
514 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
515 cmos_get_fd_drive_type(fd_type[1]);
516 rtc_set_memory(rtc_state, 0x10, val);
517
518 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
519 nb = 0;
2da44dd0 520 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 521 nb++;
522 }
2da44dd0 523 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 524 nb++;
525 }
526 switch (nb) {
527 case 0:
528 break;
529 case 1:
530 val |= 0x01; /* 1 drive, ready for boot */
531 break;
532 case 2:
533 val |= 0x41; /* 2 drives, ready for boot */
534 break;
535 }
536 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
537}
538
c0897e0c
MA		 539typedef struct pc_cmos_init_late_arg {
540 ISADevice *rtc_state;
9139046c 541 BusState *idebus[2];
c0897e0c
MA		 542} pc_cmos_init_late_arg;
543
b86f4613
LE		 544typedef struct check_fdc_state {
545 ISADevice *floppy;
546 bool multiple;
547} CheckFdcState;
548
549static int check_fdc(Object *obj, void *opaque)
550{
551 CheckFdcState *state = opaque;
552 Object *fdc;
553 uint32_t iobase;
554 Error *local_err = NULL;
555
556 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
557 if (!fdc) {
558 return 0;
559 }
560
1ea1572a 561 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 562 if (local_err || iobase != 0x3f0) {
563 error_free(local_err);
564 return 0;
565 }
566
567 if (state->floppy) {
568 state->multiple = true;
569 } else {
570 state->floppy = ISA_DEVICE(obj);
571 }
572 return 0;
573}
574
575static const char * const fdc_container_path[] = {
576 "/unattached", "/peripheral", "/peripheral-anon"
577};
578
424e4a87
RK		 579/*
580 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
581 * and ACPI objects.
582 */
cb76321e 583static ISADevice *pc_find_fdc0(void)
424e4a87
RK		 584{
585 int i;
586 Object *container;
587 CheckFdcState state = { 0 };
588
589 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
590 container = container_get(qdev_get_machine(), fdc_container_path[i]);
591 object_child_foreach(container, check_fdc, &state);
592 }
593
594 if (state.multiple) {
3dc6f869
AF		 595 warn_report("multiple floppy disk controllers with "
596 "iobase=0x3f0 have been found");
433672b0 597 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 598 "your intent");
424e4a87
RK		 599 }
600
601 return state.floppy;
602}
603
c0897e0c
MA		 604static void pc_cmos_init_late(void *opaque)
605{
606 pc_cmos_init_late_arg *arg = opaque;
607 ISADevice *s = arg->rtc_state;
9139046c
MA		 608 int16_t cylinders;
609 int8_t heads, sectors;
c0897e0c 610 int val;
2adc99b2 611 int i, trans;
c0897e0c 612
9139046c 613 val = 0;
272f0428
CP		 614 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
615 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 616 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
617 val |= 0xf0;
618 }
272f0428
CP		 619 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
620 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 621 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
622 val |= 0x0f;
623 }
624 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 625
626 val = 0;
627 for (i = 0; i < 4; i++) {
9139046c
MA		 628 /* NOTE: ide_get_geometry() returns the physical
629 geometry. It is always such that: 1 <= sects <= 63, 1
630 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
631 geometry can be different if a translation is done. */
272f0428
CP		 632 if (arg->idebus[i / 2] &&
633 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 634 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 635 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
636 assert((trans & ~3) == 0);
637 val |= trans << (i * 2);
c0897e0c
MA		 638 }
639 }
640 rtc_set_memory(s, 0x39, val);
641
424e4a87 642 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 643
c0897e0c
MA		 644 qemu_unregister_reset(pc_cmos_init_late, opaque);
645}
646
23d30407 647void pc_cmos_init(PCMachineState *pcms,
220a8846 648 BusState *idebus0, BusState *idebus1,
63ffb564 649 ISADevice *s)
80cabfad 650{
7444ca4e 651 int val;
c0897e0c 652 static pc_cmos_init_late_arg arg;
f0bb276b 653 X86MachineState *x86ms = X86_MACHINE(pcms);
b0a21b53 654
b0a21b53 655 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 656
657 /* memory size */
e89001f7 658 /* base memory (first MiB) */
f0bb276b 659 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
333190eb
FB		 660 rtc_set_memory(s, 0x15, val);
661 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 662 /* extended memory (next 64MiB) */
f0bb276b
PB		 663 if (x86ms->below_4g_mem_size > 1 * MiB) {
664 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 665 } else {
666 val = 0;
667 }
80cabfad
FB		 668 if (val > 65535)
669 val = 65535;
b0a21b53
FB		 670 rtc_set_memory(s, 0x17, val);
671 rtc_set_memory(s, 0x18, val >> 8);
672 rtc_set_memory(s, 0x30, val);
673 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 674 /* memory between 16MiB and 4GiB */
f0bb276b
PB		 675 if (x86ms->below_4g_mem_size > 16 * MiB) {
676 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 677 } else {
9da98861 678 val = 0;
e89001f7 679 }
80cabfad
FB		 680 if (val > 65535)
681 val = 65535;
b0a21b53
FB		 682 rtc_set_memory(s, 0x34, val);
683 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 684 /* memory above 4GiB */
f0bb276b 685 val = x86ms->above_4g_mem_size / 65536;
e89001f7
MA		 686 rtc_set_memory(s, 0x5b, val);
687 rtc_set_memory(s, 0x5c, val >> 8);
688 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 689
23d30407 690 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 691 TYPE_ISA_DEVICE,
f0bb276b 692 (Object **)&x86ms->rtc,
2d996150 693 object_property_allow_set_link,
d2623129 694 OBJ_PROP_LINK_STRONG);
5325cc34
MA		 695 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
696 &error_abort);
298e01b6 697
97ec4d21 698 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
80cabfad 699
b0a21b53 700 val = 0;
b0a21b53
FB		 701 val |= 0x02; /* FPU is there */
702 val |= 0x04; /* PS/2 mouse installed */
703 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
704
b86f4613 705 /* hard drives and FDC */
c0897e0c 706 arg.rtc_state = s;
9139046c
MA		 707 arg.idebus[0] = idebus0;
708 arg.idebus[1] = idebus1;
c0897e0c 709 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 710}
711
956a3e6b 712static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 713{
cc36a7a2 714 X86CPU *cpu = opaque;
e1a23744 715
956a3e6b 716 /* XXX: send to all CPUs ? */
4b78a802 717 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 718 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 719}
720
b41a2cd1
FB		 721#define NE2000_NB_MAX 6
722
675d6f82
BS		 723static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
724 0x280, 0x380 };
725static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 726
cb76321e 727static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 728{
729 static int nb_ne2k = 0;
730
731 if (nb_ne2k == NE2000_NB_MAX)
732 return;
48a18b3c 733 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 734 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 735 nb_ne2k++;
736}
737
845773ab 738void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 739{
c3affe56 740 X86CPU *cpu = opaque;
53b67b30
BS		 741
742 if (level) {
c3affe56 743 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 744 }
745}
746
3459a625 747static
9ebeed0c 748void pc_machine_done(Notifier *notifier, void *data)
3459a625 749{
9ebeed0c
EH		 750 PCMachineState *pcms = container_of(notifier,
751 PCMachineState, machine_done);
f0bb276b 752 X86MachineState *x86ms = X86_MACHINE(pcms);
dab390ff 753
1ebf9001
JC		 754 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
755 &error_fatal);
756
757 if (pcms->cxl_devices_state.is_enabled) {
758 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
dab390ff 759 }
2118196b 760
ba157b69 761 /* set the number of CPUs */
0cca1a91 762 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
ba157b69 763
0abd3888 764 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
2118196b 765
bb292f5a 766 acpi_setup();
f0bb276b
PB		 767 if (x86ms->fw_cfg) {
768 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
769 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
e3cadac0 770 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
f0bb276b 771 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
6d42eefa 772 }
3459a625
MT		 773}
774
e4e8ba04 775void pc_guest_info_init(PCMachineState *pcms)
3459a625 776{
f0bb276b 777 X86MachineState *x86ms = X86_MACHINE(pcms);
b20c9bd5 778
eafa0868 779 x86ms->apic_xrupt_override = true;
9ebeed0c
EH		 780 pcms->machine_done.notify = pc_machine_done;
781 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 782}
783
83d08f26 784/* setup pci memory address space mapping into system address space */
09aa7be1 785void pc_pci_as_mapping_init(MemoryRegion *system_memory,
83d08f26 786 MemoryRegion *pci_address_space)
39848901 787{
83d08f26
MT		 788 /* Set to lower priority than RAM */
789 memory_region_add_subregion_overlap(system_memory, 0x0,
790 pci_address_space, -1);
39848901
IM		 791}
792
7bc35e0f 793void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 794{
795 int i;
796 FWCfgState *fw_cfg;
703a548a 797 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 798 X86MachineState *x86ms = X86_MACHINE(pcms);
b33a5bbf 799
df1f79fd 800 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 801
305ae888 802 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
f0bb276b 803 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
b33a5bbf
CL		 804 rom_set_fw(fw_cfg);
805
703a548a 806 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
67f7e426 807 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
b33a5bbf
CL		 808 for (i = 0; i < nb_option_roms; i++) {
809 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 810 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 811 !strcmp(option_rom[i].name, "pvh.bin") ||
3ca8ce72
PB		 812 !strcmp(option_rom[i].name, "multiboot.bin") ||
813 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
b33a5bbf
CL		 814 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
815 }
f0bb276b 816 x86ms->fw_cfg = fw_cfg;
b33a5bbf
CL		 817}
818
72686c58
PMD		 819#define PC_ROM_MIN_VGA 0xc0000
820#define PC_ROM_MIN_OPTION 0xc8000
821#define PC_ROM_MAX 0xe0000
822#define PC_ROM_ALIGN 0x800
823#define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
824
5ff62e2a
JM		 825static hwaddr pc_above_4g_end(PCMachineState *pcms)
826{
827 X86MachineState *x86ms = X86_MACHINE(pcms);
828
829 if (pcms->sgx_epc.size != 0) {
830 return sgx_epc_above_4g_end(&pcms->sgx_epc);
831 }
832
833 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
834}
835
8288a828
JM		 836static void pc_get_device_memory_range(PCMachineState *pcms,
837 hwaddr *base,
838 ram_addr_t *device_mem_size)
42bed071
JM		 839{
840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
841 MachineState *machine = MACHINE(pcms);
8288a828
JM		 842 ram_addr_t size;
843 hwaddr addr;
844
845 size = machine->maxram_size - machine->ram_size;
846 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
847
848 if (pcmc->enforce_aligned_dimm) {
849 /* size device region assuming 1G page max alignment per slot */
850 size += (1 * GiB) * machine->ram_slots;
851 }
852
853 *base = addr;
854 *device_mem_size = size;
855}
856
857static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
858{
859 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
42bed071 860 hwaddr cxl_base;
8288a828 861 ram_addr_t size;
42bed071 862
8288a828
JM		 863 if (pcmc->has_reserved_memory) {
864 pc_get_device_memory_range(pcms, &cxl_base, &size);
865 cxl_base += size;
42bed071
JM		 866 } else {
867 cxl_base = pc_above_4g_end(pcms);
868 }
869
870 return cxl_base;
871}
872
55668e40
JM		 873static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
874{
1065b219
JM		 875 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
876
877 if (pcms->cxl_devices_state.fixed_windows) {
878 GList *it;
879
880 start = ROUND_UP(start, 256 * MiB);
881 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
882 CXLFixedWindow *fw = it->data;
883 start += fw->size;
55668e40
JM		 884 }
885 }
886
887 return start;
888}
889
1caab5cf
JM		 890static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
891{
892 X86CPU *cpu = X86_CPU(first_cpu);
893
894 /* 32-bit systems don't have hole64 thus return max CPU address */
895 if (cpu->phys_bits <= 32) {
896 return ((hwaddr)1 << cpu->phys_bits) - 1;
897 }
898
899 return pc_pci_hole64_start() + pci_hole64_size - 1;
900}
901
8504f129
JM		 902/*
903 * AMD systems with an IOMMU have an additional hole close to the
904 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
905 * on kernel version, VFIO may or may not let you DMA map those ranges.
906 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
907 * with certain memory sizes. It's also wrong to use those IOVA ranges
908 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
909 * The ranges reserved for Hyper-Transport are:
910 *
911 * FD_0000_0000h - FF_FFFF_FFFFh
912 *
913 * The ranges represent the following:
914 *
915 * Base Address Top Address Use
916 *
917 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
918 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
919 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
920 * FD_F910_0000h FD_F91F_FFFFh System Management
921 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
922 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
923 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
924 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
925 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
926 * FE_2000_0000h FF_FFFF_FFFFh Reserved
927 *
928 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
929 * Table 3: Special Address Controls (GPA) for more information.
930 */
931#define AMD_HT_START 0xfd00000000UL
932#define AMD_HT_END 0xffffffffffUL
933#define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
934#define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
935
5934e216
EH		 936void pc_memory_init(PCMachineState *pcms,
937 MemoryRegion *system_memory,
938 MemoryRegion *rom_memory,
c48eb7a4
JM		 939 MemoryRegion **ram_memory,
940 uint64_t pci_hole64_size)
80cabfad 941{
cbc5b5f3 942 int linux_boot, i;
bd457782 943 MemoryRegion *option_rom_mr;
00cb2a99 944 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 945 FWCfgState *fw_cfg;
62b160c0 946 MachineState *machine = MACHINE(pcms);
264b4857 947 MachineClass *mc = MACHINE_GET_CLASS(machine);
16a9e8a5 948 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 949 X86MachineState *x86ms = X86_MACHINE(pcms);
1caab5cf 950 hwaddr maxphysaddr, maxusedaddr;
6d302cf4 951 hwaddr cxl_base, cxl_resv_end = 0;
1caab5cf 952 X86CPU *cpu = X86_CPU(first_cpu);
d592d303 953
f0bb276b
PB		 954 assert(machine->ram_size == x86ms->below_4g_mem_size +
955 x86ms->above_4g_mem_size);
9521d42b
PB		 956
957 linux_boot = (machine->kernel_filename != NULL);
80cabfad 958
8504f129
JM		 959 /*
960 * The HyperTransport range close to the 1T boundary is unique to AMD
961 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
b3e6982b
JM		 962 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
963 * older machine types (<= 7.0) for compatibility purposes.
8504f129 964 */
b3e6982b 965 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
8504f129
JM		 966 /* Bail out if max possible address does not cross HT range */
967 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
968 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
969 }
970
971 /*
972 * Advertise the HT region if address space covers the reserved
973 * region or if we relocate.
974 */
975 if (cpu->phys_bits >= 40) {
976 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
977 }
978 }
979
1caab5cf
JM		 980 /*
981 * phys-bits is required to be appropriately configured
982 * to make sure max used GPA is reachable.
983 */
984 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
985 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
986 if (maxphysaddr < maxusedaddr) {
987 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
988 " phys-bits too low (%u)",
989 maxphysaddr, maxusedaddr, cpu->phys_bits);
990 exit(EXIT_FAILURE);
991 }
992
bd457782
IM		 993 /*
994 * Split single memory region and use aliases to address portions of it,
995 * done for backwards compatibility with older qemus.
00cb2a99 996 */
bd457782 997 *ram_memory = machine->ram;
7267c094 998 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
bd457782 999 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
f0bb276b 1000 0, x86ms->below_4g_mem_size);
00cb2a99 1001 memory_region_add_subregion(system_memory, 0, ram_below_4g);
f0bb276b
PB		 1002 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1003 if (x86ms->above_4g_mem_size > 0) {
7267c094 1004 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
bd457782
IM		 1005 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1006 machine->ram,
f0bb276b
PB		 1007 x86ms->below_4g_mem_size,
1008 x86ms->above_4g_mem_size);
4ab4c330 1009 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
00cb2a99 1010 ram_above_4g);
4ab4c330
JM		 1011 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1012 E820_RAM);
bbe80adf 1013 }
82b36dc3 1014
1ed1ccc5
SC		 1015 if (pcms->sgx_epc.size != 0) {
1016 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1017 }
1018
bb292f5a 1019 if (!pcmc->has_reserved_memory &&
ca8336f3 1020 (machine->ram_slots ||
9521d42b 1021 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 1022
1023 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1024 mc->name);
1025 exit(EXIT_FAILURE);
1026 }
1027
b0c14ec4
DH		 1028 /* always allocate the device memory information */
1029 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1030
f2ffbe2b 1031 /* initialize device memory address space */
bb292f5a 1032 if (pcmc->has_reserved_memory &&
9521d42b 1033 (machine->ram_size < machine->maxram_size)) {
8288a828 1034 ram_addr_t device_mem_size;
619d11e4 1035
a0cc8856
IM		 1036 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1037 error_report("unsupported amount of memory slots: %"PRIu64,
1038 machine->ram_slots);
1039 exit(EXIT_FAILURE);
1040 }
1041
f2c38522
PK		 1042 if (QEMU_ALIGN_UP(machine->maxram_size,
1043 TARGET_PAGE_SIZE) != machine->maxram_size) {
1044 error_report("maximum memory size must by aligned to multiple of "
1045 "%d bytes", TARGET_PAGE_SIZE);
1046 exit(EXIT_FAILURE);
1047 }
1048
8288a828 1049 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
085f8e88 1050
f2ffbe2b
DH		 1051 if ((machine->device_memory->base + device_mem_size) <
1052 device_mem_size) {
619d11e4
IM		 1053 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1054 machine->maxram_size);
1055 exit(EXIT_FAILURE);
1056 }
1057
b0c14ec4 1058 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 1059 "device-memory", device_mem_size);
b0c14ec4
DH		 1060 memory_region_add_subregion(system_memory, machine->device_memory->base,
1061 &machine->device_memory->mr);
619d11e4 1062 }
cbc5b5f3 1063
1ebf9001
JC		 1064 if (pcms->cxl_devices_state.is_enabled) {
1065 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
6e4e3ae9
BW		 1066 hwaddr cxl_size = MiB;
1067
42bed071 1068 cxl_base = pc_get_cxl_range_start(pcms);
6e4e3ae9
BW		 1069 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1070 memory_region_add_subregion(system_memory, cxl_base, mr);
6d302cf4 1071 cxl_resv_end = cxl_base + cxl_size;
1ebf9001 1072 if (pcms->cxl_devices_state.fixed_windows) {
6d302cf4
JC		 1073 hwaddr cxl_fmw_base;
1074 GList *it;
1075
1076 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1ebf9001 1077 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
6d302cf4
JC		 1078 CXLFixedWindow *fw = it->data;
1079
1080 fw->base = cxl_fmw_base;
1081 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1082 "cxl-fixed-memory-region", fw->size);
1083 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
6d302cf4
JC		 1084 cxl_fmw_base += fw->size;
1085 cxl_resv_end = cxl_fmw_base;
1086 }
1087 }
6e4e3ae9
BW		 1088 }
1089
cbc5b5f3 1090 /* Initialize PC system firmware */
5e640a9e 1091 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 1092
7267c094 1093 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 1094 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 1095 &error_fatal);
208fa0e4
IM		 1096 if (pcmc->pci_enabled) {
1097 memory_region_set_readonly(option_rom_mr, true);
1098 }
4463aee6 1099 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 1100 PC_ROM_MIN_VGA,
1101 option_rom_mr,
1102 1);
f753ff16 1103
bd802bd9 1104 fw_cfg = fw_cfg_arch_create(machine,
f0bb276b 1105 x86ms->boot_cpus, x86ms->apic_id_limit);
c886fc4c 1106
8832cb80 1107 rom_set_fw(fw_cfg);
1d108d97 1108
b0c14ec4 1109 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 1110 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 1111 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1112 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 1113
1114 if (!pcmc->broken_reserved_end) {
b0c14ec4 1115 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 1116 }
6d302cf4 1117
1ebf9001 1118 if (pcms->cxl_devices_state.is_enabled) {
6d302cf4
JC		 1119 res_mem_end = cxl_resv_end;
1120 }
d471bf3e 1121 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 1122 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1123 }
1124
f753ff16 1125 if (linux_boot) {
703a548a 1126 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
67f7e426 1127 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
f753ff16
PB		 1128 }
1129
1130 for (i = 0; i < nb_option_roms; i++) {
2e55e842 1131 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 1132 }
f0bb276b 1133 x86ms->fw_cfg = fw_cfg;
cb135f59
PX		 1134
1135 /* Init default IOAPIC address space */
f0bb276b 1136 x86ms->ioapic_as = &address_space_memory;
091c466e
SK		 1137
1138 /* Init ACPI memory hotplug IO base address */
1139 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
3d53f5c3
IY		 1140}
1141
9fa99d25
MA		 1142/*
1143 * The 64bit pci hole starts after "above 4G RAM" and
1144 * potentially the space reserved for memory hotplug.
1145 */
1146uint64_t pc_pci_hole64_start(void)
1147{
1148 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1149 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1150 MachineState *ms = MACHINE(pcms);
9fa99d25 1151 uint64_t hole64_start = 0;
8288a828 1152 ram_addr_t size = 0;
9fa99d25 1153
55668e40
JM		 1154 if (pcms->cxl_devices_state.is_enabled) {
1155 hole64_start = pc_get_cxl_range_end(pcms);
8288a828
JM		 1156 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1157 pc_get_device_memory_range(pcms, &hole64_start, &size);
9fa99d25 1158 if (!pcmc->broken_reserved_end) {
8288a828 1159 hole64_start += size;
9fa99d25
MA		 1160 }
1161 } else {
5ff62e2a 1162 hole64_start = pc_above_4g_end(pcms);
9fa99d25
MA		 1163 }
1164
d471bf3e 1165 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1166}
1167
48a18b3c 1168DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1169{
ad6d45fa
AL		 1170 DeviceState *dev = NULL;
1171
bab47d9a 1172 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1173 if (pci_bus) {
1174 PCIDevice *pcidev = pci_vga_init(pci_bus);
1175 dev = pcidev ? &pcidev->qdev : NULL;
1176 } else if (isa_bus) {
1177 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1178 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1179 }
bab47d9a 1180 rom_reset_order_override();
ad6d45fa 1181 return dev;
765d7908
IY		 1182}
1183
258711c6
JG		 1184static const MemoryRegionOps ioport80_io_ops = {
1185 .write = ioport80_write,
c02e1eac 1186 .read = ioport80_read,
258711c6
JG		 1187 .endianness = DEVICE_NATIVE_ENDIAN,
1188 .impl = {
1189 .min_access_size = 1,
1190 .max_access_size = 1,
1191 },
1192};
1193
1194static const MemoryRegionOps ioportF0_io_ops = {
1195 .write = ioportF0_write,
c02e1eac 1196 .read = ioportF0_read,
258711c6
JG		 1197 .endianness = DEVICE_NATIVE_ENDIAN,
1198 .impl = {
1199 .min_access_size = 1,
1200 .max_access_size = 1,
1201 },
1202};
1203
4ccd5fe2
JD		 1204static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1205 bool create_i8042, bool no_vmport)
ac64273c
PMD		 1206{
1207 int i;
1208 DriveInfo *fd[MAX_FD];
1209 qemu_irq *a20_line;
fed2c173 1210 ISADevice *fdc, *i8042, *port92, *vmmouse;
ac64273c 1211
def337ff 1212 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1213 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1214
1215 for (i = 0; i < MAX_FD; i++) {
1216 fd[i] = drive_get(IF_FLOPPY, 0, i);
1217 create_fdctrl |= !!fd[i];
1218 }
1219 if (create_fdctrl) {
fed2c173
MA		 1220 fdc = isa_new(TYPE_ISA_FDC);
1221 if (fdc) {
1222 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1223 isa_fdc_init_drives(fdc, fd);
1224 }
ac64273c
PMD		 1225 }
1226
4ccd5fe2
JD		 1227 if (!create_i8042) {
1228 return;
1229 }
1230
aa2e535c 1231 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
ac64273c 1232 if (!no_vmport) {
b4fa79ea 1233 isa_create_simple(isa_bus, TYPE_VMPORT);
c23e0561 1234 vmmouse = isa_try_new("vmmouse");
ac64273c
PMD		 1235 } else {
1236 vmmouse = NULL;
1237 }
1238 if (vmmouse) {
aa2e535c 1239 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
5325cc34 1240 &error_abort);
c23e0561 1241 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
ac64273c 1242 }
9e5213c8 1243 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
ac64273c
PMD		 1244
1245 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1246 i8042_setup_a20_line(i8042, a20_line[0]);
1820b70e
PMD		 1247 qdev_connect_gpio_out_named(DEVICE(port92),
1248 PORT92_A20_LINE, 0, a20_line[1]);
ac64273c
PMD		 1249 g_free(a20_line);
1250}
1251
10e2483b
GH		 1252void pc_basic_device_init(struct PCMachineState *pcms,
1253 ISABus *isa_bus, qemu_irq *gsi,
1611977c 1254 ISADevice **rtc_state,
fd53c87c 1255 bool create_fdctrl,
3a87d009 1256 uint32_t hpet_irqs)
ffe513da
IY		 1257{
1258 int i;
ce967e2f
JK		 1259 DeviceState *hpet = NULL;
1260 int pit_isa_irq = 0;
1261 qemu_irq pit_alt_irq = NULL;
7d932dfd 1262 qemu_irq rtc_irq = NULL;
ac64273c 1263 ISADevice *pit = NULL;
258711c6
JG		 1264 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1265 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
9dee7e51 1266 X86MachineState *x86ms = X86_MACHINE(pcms);
ffe513da 1267
2c9b15ca 1268 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 1269 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 1270
2c9b15ca 1271 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 1272 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 1273
5d17c0d2
JK		 1274 /*
1275 * Check if an HPET shall be created.
1276 *
1277 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1278 * when the HPET wants to take over. Thus we have to disable the latter.
1279 */
0259c78c
EH		 1280 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1281 kvm_has_pit_state2())) {
df707969 1282 hpet = qdev_try_new(TYPE_HPET);
0259c78c
EH		 1283 if (!hpet) {
1284 error_report("couldn't create HPET device");
1285 exit(1);
1286 }
54420332
MT		 1287 /*
1288 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1289 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1290 * IRQ2.
1291 */
0259c78c
EH		 1292 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1293 HPET_INTCAP, NULL);
1294 if (!compat) {
1295 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1296 }
1297 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1298 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
7a10ef51 1299
0259c78c
EH		 1300 for (i = 0; i < GSI_NUM_PINS; i++) {
1301 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
822557eb 1302 }
0259c78c
EH		 1303 pit_isa_irq = -1;
1304 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1305 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
ffe513da 1306 }
6c646a11 1307 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 1308
1309 qemu_register_boot_set(pc_boot_set, *rtc_state);
1310
9dee7e51
XL		 1311 if (!xen_enabled() &&
1312 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
15eafc2e 1313 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 1314 pit = kvm_pit_init(isa_bus, 0x40);
1315 } else {
acf695ec 1316 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 1317 }
1318 if (hpet) {
1319 /* connect PIT to output control line of the HPET */
4a17cc4f 1320 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311 1321 }
6b8d1416 1322 pcspk_init(pcms->pcspk, isa_bus, pit);
ce967e2f 1323 }
ffe513da 1324
ac64273c 1325 /* Super I/O */
4ccd5fe2
JD		 1326 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1327 pcms->vmport != ON_OFF_AUTO_ON);
ffe513da
IY		 1328}
1329
4b9c264b 1330void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 1331{
1332 int i;
1333
bab47d9a 1334 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 1335 for (i = 0; i < nb_nics; i++) {
1336 NICInfo *nd = &nd_table[i];
4b9c264b 1337 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 1338
4b9c264b 1339 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 1340 pc_init_ne2k_isa(isa_bus, nd);
1341 } else {
4b9c264b 1342 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 1343 }
1344 }
bab47d9a 1345 rom_reset_order_override();
9011a1a7
IY		 1346}
1347
4501d317
PMD		 1348void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1349{
1350 qemu_irq *i8259;
1351
1352 if (kvm_pic_in_kernel()) {
1353 i8259 = kvm_i8259_init(isa_bus);
1354 } else if (xen_enabled()) {
1355 i8259 = xen_interrupt_controller_init();
1356 } else {
89a289c7 1357 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
4501d317
PMD		 1358 }
1359
1360 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1361 i8259_irqs[i] = i8259[i];
1362 }
1363
1364 g_free(i8259);
1365}
1366
d468115b
DH		 1367static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1368 Error **errp)
1369{
1370 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1371 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
b0e62443 1372 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 1373 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 1374 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 1375 const uint64_t legacy_align = TARGET_PAGE_SIZE;
ae909496 1376 Error *local_err = NULL;
d468115b
DH		 1377
1378 /*
1379 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1380 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1381 * addition to cover this case.
1382 */
50aef131 1383 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
d468115b
DH		 1384 error_setg(errp,
1385 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1386 return;
1387 }
1388
f6a0d06b 1389 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 1390 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1391 return;
1392 }
8f1ffe5b 1393
50aef131 1394 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
ae909496
TH		 1395 if (local_err) {
1396 error_propagate(errp, local_err);
1397 return;
1398 }
1399
fd3416f5 1400 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 1401 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 1402}
1403
bb6e2f7a
DH		 1404static void pc_memory_plug(HotplugHandler *hotplug_dev,
1405 DeviceState *dev, Error **errp)
95bee274 1406{
95bee274 1407 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1408 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f6a0d06b 1409 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 1410 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 1411
84fd5496 1412 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
b8865591 1413
7f3cf2d6 1414 if (is_nvdimm) {
f6a0d06b 1415 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 1416 }
1417
50aef131 1418 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
95bee274
IM		 1419}
1420
bb6e2f7a
DH		 1421static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1422 DeviceState *dev, Error **errp)
64fec58e 1423{
50aef131 1424 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
64fec58e 1425
8cd91ace
HZ		 1426 /*
1427 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1428 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1429 * addition to cover this case.
1430 */
50aef131 1431 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
dcfe4805 1432 error_setg(errp,
8cd91ace 1433 "memory hotplug is not enabled: missing acpi device or acpi disabled");
dcfe4805 1434 return;
64fec58e
TC		 1435 }
1436
b097cc52 1437 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
dcfe4805
MA		 1438 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1439 return;
b097cc52
XG		 1440 }
1441
50aef131 1442 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
dcfe4805 1443 errp);
64fec58e
TC		 1444}
1445
bb6e2f7a
DH		 1446static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1447 DeviceState *dev, Error **errp)
f7d3e29d
TC		 1448{
1449 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1450 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f7d3e29d
TC		 1451 Error *local_err = NULL;
1452
50aef131 1453 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
f7d3e29d
TC		 1454 if (local_err) {
1455 goto out;
1456 }
1457
fd3416f5 1458 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
981c3dcd 1459 qdev_unrealize(dev);
f7d3e29d
TC		 1460 out:
1461 error_propagate(errp, local_err);
1462}
1463
0ed48fd3
DH		 1464static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1465 DeviceState *dev, Error **errp)
a0a49813
DH		 1466{
1467 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1468 Error *local_err = NULL;
1469
af1d039f 1470 if (!hotplug_dev2 && dev->hotplugged) {
a0a49813
DH		 1471 /*
1472 * Without a bus hotplug handler, we cannot control the plug/unplug
af1d039f
DH		 1473 * order. We should never reach this point when hotplugging on x86,
1474 * however, better add a safety net.
a0a49813 1475 */
0ed48fd3
DH		 1476 error_setg(errp, "hotplug of virtio based memory devices not supported"
1477 " on this bus.");
a0a49813
DH		 1478 return;
1479 }
1480 /*
1481 * First, see if we can plug this memory device at all. If that
1482 * succeeds, branch of to the actual hotplug handler.
1483 */
1484 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1485 &local_err);
af1d039f 1486 if (!local_err && hotplug_dev2) {
a0a49813
DH		 1487 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1488 }
1489 error_propagate(errp, local_err);
1490}
1491
0ed48fd3
DH		 1492static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1493 DeviceState *dev, Error **errp)
a0a49813
DH		 1494{
1495 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1496 Error *local_err = NULL;
1497
1498 /*
1499 * Plug the memory device first and then branch off to the actual
1500 * hotplug handler. If that one fails, we can easily undo the memory
1501 * device bits.
1502 */
1503 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
af1d039f
DH		 1504 if (hotplug_dev2) {
1505 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1506 if (local_err) {
1507 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1508 }
a0a49813
DH		 1509 }
1510 error_propagate(errp, local_err);
1511}
1512
0ed48fd3
DH		 1513static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1514 DeviceState *dev, Error **errp)
a0a49813 1515{
0ed48fd3
DH		 1516 /* We don't support hot unplug of virtio based memory devices */
1517 error_setg(errp, "virtio based memory devices cannot be unplugged.");
a0a49813
DH		 1518}
1519
0ed48fd3
DH		 1520static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1521 DeviceState *dev, Error **errp)
a0a49813 1522{
0ed48fd3 1523 /* We don't support hot unplug of virtio based memory devices */
a0a49813
DH		 1524}
1525
4ec60c76
IM		 1526static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1527 DeviceState *dev, Error **errp)
1528{
d468115b
DH		 1529 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1530 pc_memory_pre_plug(hotplug_dev, dev, errp);
1531 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1532 x86_cpu_pre_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1533 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1534 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1535 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
36efa250
JPB		 1536 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1537 /* Declare the APIC range as the reserved MSI region */
1538 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1539 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1540
1541 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1542 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1543 resv_prop_str, errp);
1544 g_free(resv_prop_str);
1545 }
1546
1547 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1548 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1b3bf138
JPB		 1549 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1550
1551 if (pcms->iommu) {
1552 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1553 "for x86 yet.");
1554 return;
1555 }
1556 pcms->iommu = dev;
4ec60c76
IM		 1557 }
1558}
1559
95bee274
IM		 1560static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1561 DeviceState *dev, Error **errp)
1562{
1563 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1564 pc_memory_plug(hotplug_dev, dev, errp);
5279569e 1565 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1566 x86_cpu_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1567 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1568 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1569 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
95bee274
IM		 1570 }
1571}
1572
d9c5c5b8
TC		 1573static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1574 DeviceState *dev, Error **errp)
1575{
64fec58e 1576 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1577 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a 1578 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1579 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1580 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1581 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1582 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
64fec58e
TC		 1583 } else {
1584 error_setg(errp, "acpi: device unplug request for not supported device"
1585 " type: %s", object_get_typename(OBJECT(dev)));
1586 }
d9c5c5b8
TC		 1587}
1588
232391c1
TC		 1589static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1590 DeviceState *dev, Error **errp)
1591{
f7d3e29d 1592 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1593 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a 1594 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1595 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1596 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1597 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1598 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
f7d3e29d
TC		 1599 } else {
1600 error_setg(errp, "acpi: device unplug for not supported device"
1601 " type: %s", object_get_typename(OBJECT(dev)));
1602 }
232391c1
TC		 1603}
1604
285816d7 1605static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 1606 DeviceState *dev)
1607{
5279569e 1608 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
a0a49813 1609 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
0ed48fd3 1610 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1b3bf138 1611 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
36efa250 1612 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1b3bf138 1613 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
95bee274
IM		 1614 return HOTPLUG_HANDLER(machine);
1615 }
1616
38aefb57 1617 return NULL;
95bee274
IM		 1618}
1619
bf1e8939 1620static void
f2ffbe2b
DH		 1621pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1622 const char *name, void *opaque,
1623 Error **errp)
bf1e8939 1624{
b0c14ec4 1625 MachineState *ms = MACHINE(obj);
fc3b77e2
IM		 1626 int64_t value = 0;
1627
1628 if (ms->device_memory) {
1629 value = memory_region_size(&ms->device_memory->mr);
1630 }
bf1e8939 1631
51e72bc1 1632 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 1633}
1634
d7bce999
EB		 1635static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1636 void *opaque, Error **errp)
9b23cfb7
DDAG		 1637{
1638 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 1639 OnOffAuto vmport = pcms->vmport;
9b23cfb7 1640
51e72bc1 1641 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 1642}
1643
d7bce999
EB		 1644static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1645 void *opaque, Error **errp)
9b23cfb7
DDAG		 1646{
1647 PCMachineState *pcms = PC_MACHINE(obj);
1648
51e72bc1 1649 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 1650}
1651
be232eb0
CP		 1652static bool pc_machine_get_smbus(Object *obj, Error **errp)
1653{
1654 PCMachineState *pcms = PC_MACHINE(obj);
1655
f5878b03 1656 return pcms->smbus_enabled;
be232eb0
CP		 1657}
1658
1659static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1660{
1661 PCMachineState *pcms = PC_MACHINE(obj);
1662
f5878b03 1663 pcms->smbus_enabled = value;
be232eb0
CP		 1664}
1665
272f0428
CP		 1666static bool pc_machine_get_sata(Object *obj, Error **errp)
1667{
1668 PCMachineState *pcms = PC_MACHINE(obj);
1669
f5878b03 1670 return pcms->sata_enabled;
272f0428
CP		 1671}
1672
1673static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1674{
1675 PCMachineState *pcms = PC_MACHINE(obj);
1676
f5878b03 1677 pcms->sata_enabled = value;
272f0428
CP		 1678}
1679
0259c78c
EH		 1680static bool pc_machine_get_hpet(Object *obj, Error **errp)
1681{
1682 PCMachineState *pcms = PC_MACHINE(obj);
1683
1684 return pcms->hpet_enabled;
1685}
1686
1687static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1688{
1689 PCMachineState *pcms = PC_MACHINE(obj);
1690
1691 pcms->hpet_enabled = value;
1692}
1693
4ccd5fe2
JD		 1694static bool pc_machine_get_i8042(Object *obj, Error **errp)
1695{
1696 PCMachineState *pcms = PC_MACHINE(obj);
1697
1698 return pcms->i8042_enabled;
1699}
1700
1701static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1702{
1703 PCMachineState *pcms = PC_MACHINE(obj);
1704
1705 pcms->i8042_enabled = value;
1706}
1707
c9e96b04
XW		 1708static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1709{
1710 PCMachineState *pcms = PC_MACHINE(obj);
1711
1712 return pcms->default_bus_bypass_iommu;
1713}
1714
1715static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1716 Error **errp)
1717{
1718 PCMachineState *pcms = PC_MACHINE(obj);
1719
1720 pcms->default_bus_bypass_iommu = value;
1721}
1722
0e4edb3b
EH		 1723static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1724 void *opaque, Error **errp)
1725{
1726 PCMachineState *pcms = PC_MACHINE(obj);
1727 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1728
1729 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1730}
1731
1732static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1733 void *opaque, Error **errp)
1734{
1735 PCMachineState *pcms = PC_MACHINE(obj);
1736
1737 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1738}
1739
9a45729d
GH		 1740static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1741 const char *name, void *opaque,
1742 Error **errp)
1743{
1744 PCMachineState *pcms = PC_MACHINE(obj);
1745 uint64_t value = pcms->max_ram_below_4g;
1746
1747 visit_type_size(v, name, &value, errp);
1748}
1749
1750static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1751 const char *name, void *opaque,
1752 Error **errp)
1753{
1754 PCMachineState *pcms = PC_MACHINE(obj);
9a45729d
GH		 1755 uint64_t value;
1756
668f62ec 1757 if (!visit_type_size(v, name, &value, errp)) {
9a45729d
GH		 1758 return;
1759 }
1760 if (value > 4 * GiB) {
dcfe4805 1761 error_setg(errp,
9a45729d
GH		 1762 "Machine option 'max-ram-below-4g=%"PRIu64
1763 "' expects size less than or equal to 4G", value);
9a45729d
GH		 1764 return;
1765 }
1766
1767 if (value < 1 * MiB) {
1768 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1769 "BIOS may not work with less than 1MiB", value);
1770 }
1771
1772 pcms->max_ram_below_4g = value;
1773}
1774
0657c657
EM		 1775static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1776 const char *name, void *opaque,
1777 Error **errp)
1778{
1779 PCMachineState *pcms = PC_MACHINE(obj);
1780 uint64_t value = pcms->max_fw_size;
1781
1782 visit_type_size(v, name, &value, errp);
1783}
1784
1785static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1786 const char *name, void *opaque,
1787 Error **errp)
1788{
1789 PCMachineState *pcms = PC_MACHINE(obj);
0657c657
EM		 1790 uint64_t value;
1791
d1c81c34 1792 if (!visit_type_size(v, name, &value, errp)) {
0657c657
EM		 1793 return;
1794 }
1795
1796 /*
1797 * We don't have a theoretically justifiable exact lower bound on the base
1798 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1799 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1800 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1801 * size.
1802 */
1803 if (value > 16 * MiB) {
1804 error_setg(errp,
1805 "User specified max allowed firmware size %" PRIu64 " is "
1806 "greater than 16MiB. If combined firwmare size exceeds "
1807 "16MiB the system may not boot, or experience intermittent"
1808 "stability issues.",
1809 value);
1810 return;
1811 }
1812
1813 pcms->max_fw_size = value;
1814}
1815
602b4582 1816
bf1e8939
IM		 1817static void pc_machine_initfn(Object *obj)
1818{
c87b1520
DS		 1819 PCMachineState *pcms = PC_MACHINE(obj);
1820
97fd1ea8 1821#ifdef CONFIG_VMPORT
d1048bef 1822 pcms->vmport = ON_OFF_AUTO_AUTO;
97fd1ea8
JM		 1823#else
1824 pcms->vmport = ON_OFF_AUTO_OFF;
1825#endif /* CONFIG_VMPORT */
9a45729d 1826 pcms->max_ram_below_4g = 0; /* use default */
0e4edb3b
EH		 1827 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1828
021746c1
WL		 1829 /* acpi build is enabled by default if machine supports it */
1830 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 1831 pcms->smbus_enabled = true;
1832 pcms->sata_enabled = true;
4ccd5fe2 1833 pcms->i8042_enabled = true;
0657c657 1834 pcms->max_fw_size = 8 * MiB;
0259c78c
EH		 1835#ifdef CONFIG_HPET
1836 pcms->hpet_enabled = true;
1837#endif
c9e96b04 1838 pcms->default_bus_bypass_iommu = false;
ebc29e1b
MA		 1839
1840 pc_system_flash_create(pcms);
6b8d1416 1841 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
2e16ec05
GH		 1842 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1843 OBJECT(pcms->pcspk), "audiodev");
1ebf9001 1844 cxl_machine_init(obj, &pcms->cxl_devices_state);
bf1e8939
IM		 1845}
1846
7966d70f 1847static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
ae50c55a
ZG		 1848{
1849 CPUState *cs;
1850 X86CPU *cpu;
1851
7966d70f 1852 qemu_devices_reset(reason);
ae50c55a
ZG		 1853
1854 /* Reset APIC after devices have been reset to cancel
1855 * any changes that qemu_devices_reset() might have done.
1856 */
1857 CPU_FOREACH(cs) {
1858 cpu = X86_CPU(cs);
1859
ec19444a 1860 x86_cpu_after_reset(cpu);
ae50c55a
ZG		 1861 }
1862}
1863
c508bd12
NP		 1864static void pc_machine_wakeup(MachineState *machine)
1865{
1866 cpu_synchronize_all_states();
7966d70f 1867 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
c508bd12
NP		 1868 cpu_synchronize_all_post_reset();
1869}
1870
c6cbc29d
PX		 1871static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1872{
1873 X86IOMMUState *iommu = x86_iommu_get_default();
1874 IntelIOMMUState *intel_iommu;
1875
1876 if (iommu &&
1877 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1878 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1879 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1880 if (!intel_iommu->caching_mode) {
1881 error_setg(errp, "Device assignment is not allowed without "
1882 "enabling caching-mode=on for Intel IOMMU.");
1883 return false;
1884 }
1885 }
1886
1887 return true;
1888}
1889
95bee274
IM		 1890static void pc_machine_class_init(ObjectClass *oc, void *data)
1891{
1892 MachineClass *mc = MACHINE_CLASS(oc);
1893 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1894 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1895
7102fa70
EH		 1896 pcmc->pci_enabled = true;
1897 pcmc->has_acpi_build = true;
1898 pcmc->rsdp_in_ram = true;
1899 pcmc->smbios_defaults = true;
1900 pcmc->smbios_uuid_encoded = true;
1901 pcmc->gigabyte_align = true;
1902 pcmc->has_reserved_memory = true;
1903 pcmc->kvmclock_enabled = true;
16a9e8a5 1904 pcmc->enforce_aligned_dimm = true;
b3e6982b 1905 pcmc->enforce_amd_1tb_hole = true;
cd4040ec
EH		 1906 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1907 * to be used at the moment, 32K should be enough for a while. */
1908 pcmc->acpi_data_size = 0x20000 + 0x8000;
fda672b5 1909 pcmc->pvh_enabled = true;
8700a984 1910 pcmc->kvmclock_create_always = true;
debbdc00 1911 assert(!mc->get_hotplug_handler);
285816d7 1912 mc->get_hotplug_handler = pc_get_hotplug_handler;
c6cbc29d 1913 mc->hotplug_allowed = pc_hotplug_allowed;
81ef68e4
SL		 1914 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1915 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1916 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
7b8be49d 1917 mc->auto_enable_numa_with_memhp = true;
195784a0 1918 mc->auto_enable_numa_with_memdev = true;
c5514d0e 1919 mc->has_hotpluggable_cpus = true;
41742767 1920 mc->default_boot_order = "cad";
2059839b 1921 mc->block_default_type = IF_IDE;
4458fb3a 1922 mc->max_cpus = 255;
ae50c55a 1923 mc->reset = pc_machine_reset;
c508bd12 1924 mc->wakeup = pc_machine_wakeup;
4ec60c76 1925 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 1926 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 1927 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 1928 hc->unplug = pc_machine_device_unplug_cb;
311ca98d 1929 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 1930 mc->nvdimm_supported = true;
e4a97a89 1931 mc->smp_props.dies_supported = true;
bd457782 1932 mc->default_ram_id = "pc.ram";
0efc257d 1933
9a45729d
GH		 1934 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1935 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1936 NULL, NULL);
1937 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1938 "Maximum ram below the 4G boundary (32bit boundary)");
1939
f2ffbe2b
DH		 1940 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1941 pc_machine_get_device_memory_region_size, NULL,
d2623129 1942 NULL, NULL);
0efc257d 1943
0efc257d
EH		 1944 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1945 pc_machine_get_vmport, pc_machine_set_vmport,
d2623129 1946 NULL, NULL);
0efc257d 1947 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
7eecec7d 1948 "Enable vmport (pc & q35)");
0efc257d 1949
be232eb0 1950 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
d2623129 1951 pc_machine_get_smbus, pc_machine_set_smbus);
44bff376
TH		 1952 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1953 "Enable/disable system management bus");
272f0428
CP		 1954
1955 object_class_property_add_bool(oc, PC_MACHINE_SATA,
d2623129 1956 pc_machine_get_sata, pc_machine_set_sata);
44bff376
TH		 1957 object_class_property_set_description(oc, PC_MACHINE_SATA,
1958 "Enable/disable Serial ATA bus");
feddd2fd 1959
0259c78c
EH		 1960 object_class_property_add_bool(oc, "hpet",
1961 pc_machine_get_hpet, pc_machine_set_hpet);
44bff376
TH		 1962 object_class_property_set_description(oc, "hpet",
1963 "Enable/disable high precision event timer emulation");
0657c657 1964
4ccd5fe2
JD		 1965 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1966 pc_machine_get_i8042, pc_machine_set_i8042);
1967
739b3863 1968 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
c9e96b04
XW		 1969 pc_machine_get_default_bus_bypass_iommu,
1970 pc_machine_set_default_bus_bypass_iommu);
1971
0657c657
EM		 1972 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1973 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1974 NULL, NULL);
1975 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1976 "Maximum combined firmware size");
0e4edb3b
EH		 1977
1978 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1979 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1980 NULL, NULL);
1981 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1982 "SMBIOS Entry Point type [32, 64]");
95bee274
IM		 1983}
1984
d5747cac
IM		 1985static const TypeInfo pc_machine_info = {
1986 .name = TYPE_PC_MACHINE,
f0bb276b 1987 .parent = TYPE_X86_MACHINE,
d5747cac
IM		 1988 .abstract = true,
1989 .instance_size = sizeof(PCMachineState),
bf1e8939 1990 .instance_init = pc_machine_initfn,
d5747cac 1991 .class_size = sizeof(PCMachineClass),
95bee274
IM		 1992 .class_init = pc_machine_class_init,
1993 .interfaces = (InterfaceInfo[]) {
1994 { TYPE_HOTPLUG_HANDLER },
1995 { }
1996 },
d5747cac
IM		 1997};
1998
1999static void pc_machine_register_types(void)
2000{
2001 type_register_static(&pc_machine_info);
2002}
2003
2004type_init(pc_machine_register_types)
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