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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
549e984e | 27 | #include "hw/i386/x86.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 | 32 | #include "hw/i386/topology.h" |
87abaa5d | 33 | #include "hw/i386/fw_cfg.h" |
d8f23d61 | 34 | #include "hw/i386/vmport.h" |
54a40293 | 35 | #include "sysemu/cpus.h" |
0d09e41a | 36 | #include "hw/block/fdc.h" |
83c9f4ca PB |
37 | #include "hw/ide.h" |
38 | #include "hw/pci/pci.h" | |
2118196b | 39 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
40 | #include "hw/nvram/fw_cfg.h" |
41 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 42 | #include "hw/firmware/smbios.h" |
83c9f4ca | 43 | #include "hw/loader.h" |
ca20cf32 | 44 | #include "elf.h" |
d6454270 | 45 | #include "migration/vmstate.h" |
47b43a1f | 46 | #include "multiboot.h" |
bcdb9064 | 47 | #include "hw/rtc/mc146818rtc.h" |
852c27e2 | 48 | #include "hw/intc/i8259.h" |
55f613ac | 49 | #include "hw/dma/i8257.h" |
0d09e41a | 50 | #include "hw/timer/i8254.h" |
47973a2d | 51 | #include "hw/input/i8042.h" |
64552b6b | 52 | #include "hw/irq.h" |
0d09e41a | 53 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
54 | #include "hw/pci/msi.h" |
55 | #include "hw/sysbus.h" | |
9c17d615 | 56 | #include "sysemu/sysemu.h" |
14a48c1d | 57 | #include "sysemu/tcg.h" |
e35704ba | 58 | #include "sysemu/numa.h" |
9c17d615 | 59 | #include "sysemu/kvm.h" |
da278d58 | 60 | #include "sysemu/xen.h" |
71e8a915 | 61 | #include "sysemu/reset.h" |
54d31236 | 62 | #include "sysemu/runstate.h" |
a9dc68d9 | 63 | #include "kvm/kvm_i386.h" |
0d09e41a | 64 | #include "hw/xen/xen.h" |
ab969087 | 65 | #include "hw/xen/start_info.h" |
a19cbfb3 | 66 | #include "ui/qemu-spice.h" |
022c62cb | 67 | #include "exec/memory.h" |
1de7afc9 | 68 | #include "qemu/bitmap.h" |
0c764a9d | 69 | #include "qemu/config-file.h" |
d49b6836 | 70 | #include "qemu/error-report.h" |
922a01a0 | 71 | #include "qemu/option.h" |
133ef074 | 72 | #include "qemu/cutils.h" |
0445259b | 73 | #include "hw/acpi/acpi.h" |
5ff020b7 | 74 | #include "hw/acpi/cpu_hotplug.h" |
72c194f7 | 75 | #include "acpi-build.h" |
95bee274 | 76 | #include "hw/mem/pc-dimm.h" |
4b997690 | 77 | #include "hw/mem/nvdimm.h" |
e688df6b | 78 | #include "qapi/error.h" |
9af23989 | 79 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 80 | #include "qapi/visitor.h" |
2e5b09fd | 81 | #include "hw/core/cpu.h" |
a310e653 | 82 | #include "hw/usb.h" |
60c5e104 | 83 | #include "hw/i386/intel_iommu.h" |
489983d6 | 84 | #include "hw/net/ne2000-isa.h" |
06e0259a | 85 | #include "standard-headers/asm-x86/bootparam.h" |
a0a49813 | 86 | #include "hw/virtio/virtio-pmem-pci.h" |
0ed48fd3 | 87 | #include "hw/virtio/virtio-mem-pci.h" |
a0a49813 | 88 | #include "hw/mem/memory-device.h" |
6f479566 LX |
89 | #include "sysemu/replay.h" |
90 | #include "qapi/qmp/qerror.h" | |
d6d059ca | 91 | #include "e820_memory_layout.h" |
149c50ca | 92 | #include "fw_cfg.h" |
4ca8dabd | 93 | #include "trace.h" |
2becc36a | 94 | #include CONFIG_DEVICES |
471fd342 | 95 | |
f701ecec VK |
96 | GlobalProperty pc_compat_6_1[] = { |
97 | { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, | |
98 | { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, | |
99 | { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, | |
100 | }; | |
52e64f5b YW |
101 | const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); |
102 | ||
b7c29017 DB |
103 | GlobalProperty pc_compat_6_0[] = { |
104 | { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, | |
105 | { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, | |
106 | { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, | |
a7a0da84 | 107 | { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, |
aa29466b | 108 | { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, |
b7c29017 | 109 | }; |
da7e13c0 CH |
110 | const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); |
111 | ||
7ed3e1eb IM |
112 | GlobalProperty pc_compat_5_2[] = { |
113 | { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, | |
114 | }; | |
576a00bd CH |
115 | const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); |
116 | ||
00dc02d2 IM |
117 | GlobalProperty pc_compat_5_1[] = { |
118 | { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, | |
c1bb5418 | 119 | { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, |
00dc02d2 | 120 | }; |
3ff3c5d3 CH |
121 | const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); |
122 | ||
2ebc2121 HW |
123 | GlobalProperty pc_compat_5_0[] = { |
124 | }; | |
541aaa1d CH |
125 | const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); |
126 | ||
f404220e IM |
127 | GlobalProperty pc_compat_4_2[] = { |
128 | { "mch", "smbase-smram", "off" }, | |
129 | }; | |
3eb74d20 CH |
130 | const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); |
131 | ||
9aec2e52 CH |
132 | GlobalProperty pc_compat_4_1[] = {}; |
133 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
134 | ||
9bf2650b CH |
135 | GlobalProperty pc_compat_4_0[] = {}; |
136 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
137 | ||
abd93cc7 | 138 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 139 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
140 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
141 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
142 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
143 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 144 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
145 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
146 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
147 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
148 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
149 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
150 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
151 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
152 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
153 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
154 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
155 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
156 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
157 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 158 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 159 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
160 | }; |
161 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
162 | ||
ddb3235d | 163 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
164 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
165 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
166 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
167 | }; |
168 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
169 | ||
0d47310b | 170 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
171 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
172 | { TYPE_X86_CPU, "topoext", "off" }, | |
173 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
174 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
175 | }; |
176 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
177 | ||
43df70a9 | 178 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
179 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
180 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
181 | }; |
182 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
183 | ||
503224f4 | 184 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
185 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
186 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
187 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
188 | }; |
189 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
190 | ||
3e803152 | 191 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 192 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
193 | }; |
194 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
195 | ||
edc24ccd | 196 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
197 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
198 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
199 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
200 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
201 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
202 | }; |
203 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
204 | ||
5a995064 | 205 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
206 | { TYPE_X86_CPU, "l3-cache", "off" }, |
207 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
208 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
209 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
210 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
211 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
212 | }; |
213 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
214 | ||
ff8f261f | 215 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
216 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
217 | { "vmxnet3", "romfile", "" }, | |
218 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
219 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
220 | }; |
221 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
222 | ||
fe759610 MAL |
223 | GlobalProperty pc_compat_2_5[] = {}; |
224 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
225 | ||
2f99b9c2 MAL |
226 | GlobalProperty pc_compat_2_4[] = { |
227 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
228 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
229 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
230 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
231 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
232 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
233 | { TYPE_X86_CPU, "check", "off" }, | |
234 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
235 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
236 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
237 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
238 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
239 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
240 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
241 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
242 | }; |
243 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
244 | ||
8995dd90 MAL |
245 | GlobalProperty pc_compat_2_3[] = { |
246 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
247 | { TYPE_X86_CPU, "arat", "off" }, |
248 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
249 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
250 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
251 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
252 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
253 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
254 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
255 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
256 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
257 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
258 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
259 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
260 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
261 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
262 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
263 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
264 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
265 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
266 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
267 | }; |
268 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
269 | ||
1c30044e MAL |
270 | GlobalProperty pc_compat_2_2[] = { |
271 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
272 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
273 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
274 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
275 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
276 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
277 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
278 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
279 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
280 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
281 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
282 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
283 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
284 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
285 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
286 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
287 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
288 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
289 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
290 | }; |
291 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
292 | ||
c4fc5695 MAL |
293 | GlobalProperty pc_compat_2_1[] = { |
294 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
295 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
296 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
297 | }; |
298 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
299 | ||
a310e653 MAL |
300 | GlobalProperty pc_compat_2_0[] = { |
301 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
302 | { "virtio-scsi-pci", "any_layout", "off" }, |
303 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
304 | { "apic", "version", "0x11" }, | |
305 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
306 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
307 | { "pci-serial", "prog_if", "0" }, | |
308 | { "pci-serial-2x", "prog_if", "0" }, | |
309 | { "pci-serial-4x", "prog_if", "0" }, | |
310 | { "virtio-net-pci", "guest_announce", "off" }, | |
311 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
312 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
313 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
a310e653 MAL |
314 | }; |
315 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
316 | ||
317 | GlobalProperty pc_compat_1_7[] = { | |
318 | PC_CPU_MODEL_IDS("1.7.0") | |
6c36bddf | 319 | { TYPE_USB_DEVICE, "msos-desc", "no" }, |
aa29466b | 320 | { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, |
6c36bddf | 321 | { "hpet", HPET_INTCAP, "4" }, |
a310e653 MAL |
322 | }; |
323 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
324 | ||
325 | GlobalProperty pc_compat_1_6[] = { | |
326 | PC_CPU_MODEL_IDS("1.6.0") | |
6c36bddf EH |
327 | { "e1000", "mitigation", "off" }, |
328 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
329 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
330 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
331 | { "q35-pcihost", "short_root_bus", "1" }, | |
a310e653 MAL |
332 | }; |
333 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
334 | ||
335 | GlobalProperty pc_compat_1_5[] = { | |
336 | PC_CPU_MODEL_IDS("1.5.0") | |
6c36bddf EH |
337 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, |
338 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
339 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
340 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
341 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
342 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
343 | { "virtio-net-pci", "any_layout", "off" }, | |
344 | { TYPE_X86_CPU, "pmu", "on" }, | |
345 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
346 | { "q35-pcihost", "short_root_bus", "0" }, | |
a310e653 MAL |
347 | }; |
348 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
349 | ||
350 | GlobalProperty pc_compat_1_4[] = { | |
351 | PC_CPU_MODEL_IDS("1.4.0") | |
6c36bddf EH |
352 | { "scsi-hd", "discard_granularity", "0" }, |
353 | { "scsi-cd", "discard_granularity", "0" }, | |
6c36bddf EH |
354 | { "ide-hd", "discard_granularity", "0" }, |
355 | { "ide-cd", "discard_granularity", "0" }, | |
6c36bddf EH |
356 | { "virtio-blk-pci", "discard_granularity", "0" }, |
357 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
358 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
359 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
360 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
361 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
362 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
363 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
364 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
365 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
366 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
367 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
a310e653 MAL |
368 | }; |
369 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
370 | ||
417258f1 PMD |
371 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
372 | { | |
373 | GSIState *s; | |
374 | ||
375 | s = g_new0(GSIState, 1); | |
376 | if (kvm_ioapic_in_kernel()) { | |
377 | kvm_pc_setup_irq_routing(pci_enabled); | |
417258f1 | 378 | } |
64c033ba | 379 | *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); |
417258f1 PMD |
380 | |
381 | return s; | |
382 | } | |
383 | ||
258711c6 JG |
384 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
385 | unsigned size) | |
80cabfad FB |
386 | { |
387 | } | |
388 | ||
c02e1eac JG |
389 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
390 | { | |
a6fc23e5 | 391 | return 0xffffffffffffffffULL; |
c02e1eac JG |
392 | } |
393 | ||
f929aad6 | 394 | /* MSDOS compatibility mode FPU exception support */ |
258711c6 JG |
395 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
396 | unsigned size) | |
f929aad6 | 397 | { |
6f529b75 | 398 | if (tcg_enabled()) { |
bf13bfab | 399 | cpu_set_ignne(); |
6f529b75 | 400 | } |
f929aad6 FB |
401 | } |
402 | ||
c02e1eac JG |
403 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
404 | { | |
a6fc23e5 | 405 | return 0xffffffffffffffffULL; |
c02e1eac JG |
406 | } |
407 | ||
b0a21b53 FB |
408 | /* PC cmos mappings */ |
409 | ||
80cabfad FB |
410 | #define REG_EQUIPMENT_BYTE 0x14 |
411 | ||
9139046c MA |
412 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
413 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 414 | { |
ba6c2377 FB |
415 | rtc_set_memory(s, type_ofs, 47); |
416 | rtc_set_memory(s, info_ofs, cylinders); | |
417 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
418 | rtc_set_memory(s, info_ofs + 2, heads); | |
419 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
420 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
421 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
422 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
423 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
424 | rtc_set_memory(s, info_ofs + 8, sectors); | |
425 | } | |
426 | ||
6ac0e82d AZ |
427 | /* convert boot_device letter to something recognizable by the bios */ |
428 | static int boot_device2nibble(char boot_device) | |
429 | { | |
430 | switch(boot_device) { | |
431 | case 'a': | |
432 | case 'b': | |
433 | return 0x01; /* floppy boot */ | |
434 | case 'c': | |
435 | return 0x02; /* hard drive boot */ | |
436 | case 'd': | |
437 | return 0x03; /* CD-ROM boot */ | |
438 | case 'n': | |
439 | return 0x04; /* Network boot */ | |
440 | } | |
441 | return 0; | |
442 | } | |
443 | ||
ddcd5531 | 444 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
445 | { |
446 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
447 | int nbds, bds[3] = { 0, }; |
448 | int i; | |
449 | ||
450 | nbds = strlen(boot_device); | |
451 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
452 | error_setg(errp, "Too many boot devices for PC"); |
453 | return; | |
0ecdffbb AJ |
454 | } |
455 | for (i = 0; i < nbds; i++) { | |
456 | bds[i] = boot_device2nibble(boot_device[i]); | |
457 | if (bds[i] == 0) { | |
ddcd5531 GA |
458 | error_setg(errp, "Invalid boot device for PC: '%c'", |
459 | boot_device[i]); | |
460 | return; | |
0ecdffbb AJ |
461 | } |
462 | } | |
463 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 464 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
465 | } |
466 | ||
ddcd5531 | 467 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 468 | { |
ddcd5531 | 469 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
470 | } |
471 | ||
7444ca4e LE |
472 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
473 | { | |
474 | int val, nb, i; | |
2da44dd0 JS |
475 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
476 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
477 | |
478 | /* floppy type */ | |
479 | if (floppy) { | |
480 | for (i = 0; i < 2; i++) { | |
481 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
482 | } | |
483 | } | |
484 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
485 | cmos_get_fd_drive_type(fd_type[1]); | |
486 | rtc_set_memory(rtc_state, 0x10, val); | |
487 | ||
488 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
489 | nb = 0; | |
2da44dd0 | 490 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
491 | nb++; |
492 | } | |
2da44dd0 | 493 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
494 | nb++; |
495 | } | |
496 | switch (nb) { | |
497 | case 0: | |
498 | break; | |
499 | case 1: | |
500 | val |= 0x01; /* 1 drive, ready for boot */ | |
501 | break; | |
502 | case 2: | |
503 | val |= 0x41; /* 2 drives, ready for boot */ | |
504 | break; | |
505 | } | |
506 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
507 | } | |
508 | ||
c0897e0c MA |
509 | typedef struct pc_cmos_init_late_arg { |
510 | ISADevice *rtc_state; | |
9139046c | 511 | BusState *idebus[2]; |
c0897e0c MA |
512 | } pc_cmos_init_late_arg; |
513 | ||
b86f4613 LE |
514 | typedef struct check_fdc_state { |
515 | ISADevice *floppy; | |
516 | bool multiple; | |
517 | } CheckFdcState; | |
518 | ||
519 | static int check_fdc(Object *obj, void *opaque) | |
520 | { | |
521 | CheckFdcState *state = opaque; | |
522 | Object *fdc; | |
523 | uint32_t iobase; | |
524 | Error *local_err = NULL; | |
525 | ||
526 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
527 | if (!fdc) { | |
528 | return 0; | |
529 | } | |
530 | ||
1ea1572a | 531 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
532 | if (local_err || iobase != 0x3f0) { |
533 | error_free(local_err); | |
534 | return 0; | |
535 | } | |
536 | ||
537 | if (state->floppy) { | |
538 | state->multiple = true; | |
539 | } else { | |
540 | state->floppy = ISA_DEVICE(obj); | |
541 | } | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static const char * const fdc_container_path[] = { | |
546 | "/unattached", "/peripheral", "/peripheral-anon" | |
547 | }; | |
548 | ||
424e4a87 RK |
549 | /* |
550 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
551 | * and ACPI objects. | |
552 | */ | |
553 | ISADevice *pc_find_fdc0(void) | |
554 | { | |
555 | int i; | |
556 | Object *container; | |
557 | CheckFdcState state = { 0 }; | |
558 | ||
559 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
560 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
561 | object_child_foreach(container, check_fdc, &state); | |
562 | } | |
563 | ||
564 | if (state.multiple) { | |
3dc6f869 AF |
565 | warn_report("multiple floppy disk controllers with " |
566 | "iobase=0x3f0 have been found"); | |
433672b0 | 567 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 568 | "your intent"); |
424e4a87 RK |
569 | } |
570 | ||
571 | return state.floppy; | |
572 | } | |
573 | ||
c0897e0c MA |
574 | static void pc_cmos_init_late(void *opaque) |
575 | { | |
576 | pc_cmos_init_late_arg *arg = opaque; | |
577 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
578 | int16_t cylinders; |
579 | int8_t heads, sectors; | |
c0897e0c | 580 | int val; |
2adc99b2 | 581 | int i, trans; |
c0897e0c | 582 | |
9139046c | 583 | val = 0; |
272f0428 CP |
584 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
585 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
586 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
587 | val |= 0xf0; | |
588 | } | |
272f0428 CP |
589 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
590 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
591 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
592 | val |= 0x0f; | |
593 | } | |
594 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
595 | |
596 | val = 0; | |
597 | for (i = 0; i < 4; i++) { | |
9139046c MA |
598 | /* NOTE: ide_get_geometry() returns the physical |
599 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
600 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
601 | geometry can be different if a translation is done. */ | |
272f0428 CP |
602 | if (arg->idebus[i / 2] && |
603 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 604 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
605 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
606 | assert((trans & ~3) == 0); | |
607 | val |= trans << (i * 2); | |
c0897e0c MA |
608 | } |
609 | } | |
610 | rtc_set_memory(s, 0x39, val); | |
611 | ||
424e4a87 | 612 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 613 | |
c0897e0c MA |
614 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
615 | } | |
616 | ||
23d30407 | 617 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 618 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 619 | ISADevice *s) |
80cabfad | 620 | { |
7444ca4e | 621 | int val; |
c0897e0c | 622 | static pc_cmos_init_late_arg arg; |
f0bb276b | 623 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b0a21b53 | 624 | |
b0a21b53 | 625 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
626 | |
627 | /* memory size */ | |
e89001f7 | 628 | /* base memory (first MiB) */ |
f0bb276b | 629 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
333190eb FB |
630 | rtc_set_memory(s, 0x15, val); |
631 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 632 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
633 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
634 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
635 | } else { |
636 | val = 0; | |
637 | } | |
80cabfad FB |
638 | if (val > 65535) |
639 | val = 65535; | |
b0a21b53 FB |
640 | rtc_set_memory(s, 0x17, val); |
641 | rtc_set_memory(s, 0x18, val >> 8); | |
642 | rtc_set_memory(s, 0x30, val); | |
643 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 644 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
645 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
646 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 647 | } else { |
9da98861 | 648 | val = 0; |
e89001f7 | 649 | } |
80cabfad FB |
650 | if (val > 65535) |
651 | val = 65535; | |
b0a21b53 FB |
652 | rtc_set_memory(s, 0x34, val); |
653 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 654 | /* memory above 4GiB */ |
f0bb276b | 655 | val = x86ms->above_4g_mem_size / 65536; |
e89001f7 MA |
656 | rtc_set_memory(s, 0x5b, val); |
657 | rtc_set_memory(s, 0x5c, val >> 8); | |
658 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 659 | |
23d30407 | 660 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 661 | TYPE_ISA_DEVICE, |
f0bb276b | 662 | (Object **)&x86ms->rtc, |
2d996150 | 663 | object_property_allow_set_link, |
d2623129 | 664 | OBJ_PROP_LINK_STRONG); |
5325cc34 MA |
665 | object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), |
666 | &error_abort); | |
298e01b6 | 667 | |
007b0657 | 668 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 669 | |
b0a21b53 | 670 | val = 0; |
b0a21b53 FB |
671 | val |= 0x02; /* FPU is there */ |
672 | val |= 0x04; /* PS/2 mouse installed */ | |
673 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
674 | ||
b86f4613 | 675 | /* hard drives and FDC */ |
c0897e0c | 676 | arg.rtc_state = s; |
9139046c MA |
677 | arg.idebus[0] = idebus0; |
678 | arg.idebus[1] = idebus1; | |
c0897e0c | 679 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
680 | } |
681 | ||
956a3e6b | 682 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 683 | { |
cc36a7a2 | 684 | X86CPU *cpu = opaque; |
e1a23744 | 685 | |
956a3e6b | 686 | /* XXX: send to all CPUs ? */ |
4b78a802 | 687 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 688 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
689 | } |
690 | ||
b41a2cd1 FB |
691 | #define NE2000_NB_MAX 6 |
692 | ||
675d6f82 BS |
693 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
694 | 0x280, 0x380 }; | |
695 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 696 | |
48a18b3c | 697 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
698 | { |
699 | static int nb_ne2k = 0; | |
700 | ||
701 | if (nb_ne2k == NE2000_NB_MAX) | |
702 | return; | |
48a18b3c | 703 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 704 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
705 | nb_ne2k++; |
706 | } | |
707 | ||
845773ab | 708 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 709 | { |
c3affe56 | 710 | X86CPU *cpu = opaque; |
53b67b30 BS |
711 | |
712 | if (level) { | |
c3affe56 | 713 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
714 | } |
715 | } | |
716 | ||
3459a625 | 717 | static |
9ebeed0c | 718 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 719 | { |
9ebeed0c EH |
720 | PCMachineState *pcms = container_of(notifier, |
721 | PCMachineState, machine_done); | |
f0bb276b | 722 | X86MachineState *x86ms = X86_MACHINE(pcms); |
2118196b | 723 | |
ba157b69 | 724 | /* set the number of CPUs */ |
0cca1a91 | 725 | x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 726 | |
0abd3888 | 727 | fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); |
2118196b | 728 | |
bb292f5a | 729 | acpi_setup(); |
f0bb276b PB |
730 | if (x86ms->fw_cfg) { |
731 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
732 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 733 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 734 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 735 | } |
60c5e104 | 736 | |
60c5e104 | 737 | |
c1bb5418 DW |
738 | if (x86ms->apic_id_limit > 255 && !xen_enabled() && |
739 | !kvm_irqchip_in_kernel()) { | |
740 | error_report("current -smp configuration requires kernel " | |
741 | "irqchip support."); | |
742 | exit(EXIT_FAILURE); | |
60c5e104 | 743 | } |
3459a625 MT |
744 | } |
745 | ||
e4e8ba04 | 746 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 747 | { |
f0bb276b | 748 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 749 | |
eafa0868 | 750 | x86ms->apic_xrupt_override = true; |
9ebeed0c EH |
751 | pcms->machine_done.notify = pc_machine_done; |
752 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
753 | } |
754 | ||
83d08f26 MT |
755 | /* setup pci memory address space mapping into system address space */ |
756 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
757 | MemoryRegion *pci_address_space) | |
39848901 | 758 | { |
83d08f26 MT |
759 | /* Set to lower priority than RAM */ |
760 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
761 | pci_address_space, -1); | |
39848901 IM |
762 | } |
763 | ||
7bc35e0f | 764 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
765 | { |
766 | int i; | |
767 | FWCfgState *fw_cfg; | |
703a548a | 768 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 769 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 770 | |
df1f79fd | 771 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 772 | |
305ae888 | 773 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 774 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
775 | rom_set_fw(fw_cfg); |
776 | ||
703a548a | 777 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
f014c974 | 778 | pcmc->pvh_enabled); |
b33a5bbf CL |
779 | for (i = 0; i < nb_option_roms; i++) { |
780 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 781 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 782 | !strcmp(option_rom[i].name, "pvh.bin") || |
b33a5bbf CL |
783 | !strcmp(option_rom[i].name, "multiboot.bin")); |
784 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
785 | } | |
f0bb276b | 786 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
787 | } |
788 | ||
72686c58 PMD |
789 | #define PC_ROM_MIN_VGA 0xc0000 |
790 | #define PC_ROM_MIN_OPTION 0xc8000 | |
791 | #define PC_ROM_MAX 0xe0000 | |
792 | #define PC_ROM_ALIGN 0x800 | |
793 | #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) | |
794 | ||
5934e216 EH |
795 | void pc_memory_init(PCMachineState *pcms, |
796 | MemoryRegion *system_memory, | |
797 | MemoryRegion *rom_memory, | |
798 | MemoryRegion **ram_memory) | |
80cabfad | 799 | { |
cbc5b5f3 | 800 | int linux_boot, i; |
bd457782 | 801 | MemoryRegion *option_rom_mr; |
00cb2a99 | 802 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 803 | FWCfgState *fw_cfg; |
62b160c0 | 804 | MachineState *machine = MACHINE(pcms); |
264b4857 | 805 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 806 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 807 | X86MachineState *x86ms = X86_MACHINE(pcms); |
d592d303 | 808 | |
f0bb276b PB |
809 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
810 | x86ms->above_4g_mem_size); | |
9521d42b PB |
811 | |
812 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 813 | |
bd457782 IM |
814 | /* |
815 | * Split single memory region and use aliases to address portions of it, | |
816 | * done for backwards compatibility with older qemus. | |
00cb2a99 | 817 | */ |
bd457782 | 818 | *ram_memory = machine->ram; |
7267c094 | 819 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
bd457782 | 820 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, |
f0bb276b | 821 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 822 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
823 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
824 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 825 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
bd457782 IM |
826 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", |
827 | machine->ram, | |
f0bb276b PB |
828 | x86ms->below_4g_mem_size, |
829 | x86ms->above_4g_mem_size); | |
00cb2a99 AK |
830 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
831 | ram_above_4g); | |
f0bb276b | 832 | e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); |
bbe80adf | 833 | } |
82b36dc3 | 834 | |
1ed1ccc5 SC |
835 | if (pcms->sgx_epc.size != 0) { |
836 | e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); | |
837 | } | |
838 | ||
bb292f5a | 839 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 840 | (machine->ram_slots || |
9521d42b | 841 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
842 | |
843 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
844 | mc->name); | |
845 | exit(EXIT_FAILURE); | |
846 | } | |
847 | ||
b0c14ec4 DH |
848 | /* always allocate the device memory information */ |
849 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
850 | ||
f2ffbe2b | 851 | /* initialize device memory address space */ |
bb292f5a | 852 | if (pcmc->has_reserved_memory && |
9521d42b | 853 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 854 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 855 | |
a0cc8856 IM |
856 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
857 | error_report("unsupported amount of memory slots: %"PRIu64, | |
858 | machine->ram_slots); | |
859 | exit(EXIT_FAILURE); | |
860 | } | |
861 | ||
f2c38522 PK |
862 | if (QEMU_ALIGN_UP(machine->maxram_size, |
863 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
864 | error_report("maximum memory size must by aligned to multiple of " | |
865 | "%d bytes", TARGET_PAGE_SIZE); | |
866 | exit(EXIT_FAILURE); | |
867 | } | |
868 | ||
0cf4ce00 SC |
869 | if (pcms->sgx_epc.size != 0) { |
870 | machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); | |
871 | } else { | |
872 | machine->device_memory->base = | |
873 | 0x100000000ULL + x86ms->above_4g_mem_size; | |
874 | } | |
875 | ||
b0c14ec4 | 876 | machine->device_memory->base = |
0cf4ce00 | 877 | ROUND_UP(machine->device_memory->base, 1 * GiB); |
619d11e4 | 878 | |
16a9e8a5 | 879 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 880 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 881 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
882 | } |
883 | ||
f2ffbe2b DH |
884 | if ((machine->device_memory->base + device_mem_size) < |
885 | device_mem_size) { | |
619d11e4 IM |
886 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
887 | machine->maxram_size); | |
888 | exit(EXIT_FAILURE); | |
889 | } | |
890 | ||
b0c14ec4 | 891 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 892 | "device-memory", device_mem_size); |
b0c14ec4 DH |
893 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
894 | &machine->device_memory->mr); | |
619d11e4 | 895 | } |
cbc5b5f3 JJ |
896 | |
897 | /* Initialize PC system firmware */ | |
5e640a9e | 898 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 899 | |
7267c094 | 900 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 901 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 902 | &error_fatal); |
208fa0e4 IM |
903 | if (pcmc->pci_enabled) { |
904 | memory_region_set_readonly(option_rom_mr, true); | |
905 | } | |
4463aee6 | 906 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
907 | PC_ROM_MIN_VGA, |
908 | option_rom_mr, | |
909 | 1); | |
f753ff16 | 910 | |
bd802bd9 | 911 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 912 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 913 | |
8832cb80 | 914 | rom_set_fw(fw_cfg); |
1d108d97 | 915 | |
b0c14ec4 | 916 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 917 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 918 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 919 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
920 | |
921 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 922 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 923 | } |
d471bf3e | 924 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
925 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
926 | } | |
927 | ||
f753ff16 | 928 | if (linux_boot) { |
703a548a | 929 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
f014c974 | 930 | pcmc->pvh_enabled); |
f753ff16 PB |
931 | } |
932 | ||
933 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 934 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 935 | } |
f0bb276b | 936 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
937 | |
938 | /* Init default IOAPIC address space */ | |
f0bb276b | 939 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
940 | |
941 | /* Init ACPI memory hotplug IO base address */ | |
942 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
943 | } |
944 | ||
9fa99d25 MA |
945 | /* |
946 | * The 64bit pci hole starts after "above 4G RAM" and | |
947 | * potentially the space reserved for memory hotplug. | |
948 | */ | |
949 | uint64_t pc_pci_hole64_start(void) | |
950 | { | |
951 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
952 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 953 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 954 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9fa99d25 MA |
955 | uint64_t hole64_start = 0; |
956 | ||
b0c14ec4 DH |
957 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
958 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 959 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 960 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 | 961 | } |
0cf4ce00 SC |
962 | } else if (pcms->sgx_epc.size != 0) { |
963 | hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); | |
9fa99d25 | 964 | } else { |
f0bb276b | 965 | hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; |
9fa99d25 MA |
966 | } |
967 | ||
d471bf3e | 968 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
969 | } |
970 | ||
48a18b3c | 971 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 972 | { |
ad6d45fa AL |
973 | DeviceState *dev = NULL; |
974 | ||
bab47d9a | 975 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
976 | if (pci_bus) { |
977 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
978 | dev = pcidev ? &pcidev->qdev : NULL; | |
979 | } else if (isa_bus) { | |
980 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 981 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 982 | } |
bab47d9a | 983 | rom_reset_order_override(); |
ad6d45fa | 984 | return dev; |
765d7908 IY |
985 | } |
986 | ||
258711c6 JG |
987 | static const MemoryRegionOps ioport80_io_ops = { |
988 | .write = ioport80_write, | |
c02e1eac | 989 | .read = ioport80_read, |
258711c6 JG |
990 | .endianness = DEVICE_NATIVE_ENDIAN, |
991 | .impl = { | |
992 | .min_access_size = 1, | |
993 | .max_access_size = 1, | |
994 | }, | |
995 | }; | |
996 | ||
997 | static const MemoryRegionOps ioportF0_io_ops = { | |
998 | .write = ioportF0_write, | |
c02e1eac | 999 | .read = ioportF0_read, |
258711c6 JG |
1000 | .endianness = DEVICE_NATIVE_ENDIAN, |
1001 | .impl = { | |
1002 | .min_access_size = 1, | |
1003 | .max_access_size = 1, | |
1004 | }, | |
1005 | }; | |
1006 | ||
ac64273c PMD |
1007 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1008 | { | |
1009 | int i; | |
1010 | DriveInfo *fd[MAX_FD]; | |
1011 | qemu_irq *a20_line; | |
fed2c173 | 1012 | ISADevice *fdc, *i8042, *port92, *vmmouse; |
ac64273c | 1013 | |
def337ff | 1014 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1015 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1016 | ||
1017 | for (i = 0; i < MAX_FD; i++) { | |
1018 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1019 | create_fdctrl |= !!fd[i]; | |
1020 | } | |
1021 | if (create_fdctrl) { | |
fed2c173 MA |
1022 | fdc = isa_new(TYPE_ISA_FDC); |
1023 | if (fdc) { | |
1024 | isa_realize_and_unref(fdc, isa_bus, &error_fatal); | |
1025 | isa_fdc_init_drives(fdc, fd); | |
1026 | } | |
ac64273c PMD |
1027 | } |
1028 | ||
1029 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1030 | if (!no_vmport) { | |
b4fa79ea | 1031 | isa_create_simple(isa_bus, TYPE_VMPORT); |
c23e0561 | 1032 | vmmouse = isa_try_new("vmmouse"); |
ac64273c PMD |
1033 | } else { |
1034 | vmmouse = NULL; | |
1035 | } | |
1036 | if (vmmouse) { | |
5325cc34 MA |
1037 | object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), |
1038 | &error_abort); | |
c23e0561 | 1039 | isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); |
ac64273c | 1040 | } |
9e5213c8 | 1041 | port92 = isa_create_simple(isa_bus, TYPE_PORT92); |
ac64273c PMD |
1042 | |
1043 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1044 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1820b70e PMD |
1045 | qdev_connect_gpio_out_named(DEVICE(port92), |
1046 | PORT92_A20_LINE, 0, a20_line[1]); | |
ac64273c PMD |
1047 | g_free(a20_line); |
1048 | } | |
1049 | ||
10e2483b GH |
1050 | void pc_basic_device_init(struct PCMachineState *pcms, |
1051 | ISABus *isa_bus, qemu_irq *gsi, | |
1611977c | 1052 | ISADevice **rtc_state, |
fd53c87c | 1053 | bool create_fdctrl, |
3a87d009 | 1054 | uint32_t hpet_irqs) |
ffe513da IY |
1055 | { |
1056 | int i; | |
ce967e2f JK |
1057 | DeviceState *hpet = NULL; |
1058 | int pit_isa_irq = 0; | |
1059 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1060 | qemu_irq rtc_irq = NULL; |
ac64273c | 1061 | ISADevice *pit = NULL; |
258711c6 JG |
1062 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1063 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1064 | |
2c9b15ca | 1065 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1066 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1067 | |
2c9b15ca | 1068 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1069 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1070 | |
5d17c0d2 JK |
1071 | /* |
1072 | * Check if an HPET shall be created. | |
1073 | * | |
1074 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1075 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1076 | */ | |
0259c78c EH |
1077 | if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || |
1078 | kvm_has_pit_state2())) { | |
df707969 | 1079 | hpet = qdev_try_new(TYPE_HPET); |
0259c78c EH |
1080 | if (!hpet) { |
1081 | error_report("couldn't create HPET device"); | |
1082 | exit(1); | |
1083 | } | |
54420332 MT |
1084 | /* |
1085 | * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and | |
1086 | * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and | |
1087 | * IRQ2. | |
1088 | */ | |
0259c78c EH |
1089 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
1090 | HPET_INTCAP, NULL); | |
1091 | if (!compat) { | |
1092 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1093 | } | |
1094 | sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); | |
1095 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
7a10ef51 | 1096 | |
0259c78c EH |
1097 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1098 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); | |
822557eb | 1099 | } |
0259c78c EH |
1100 | pit_isa_irq = -1; |
1101 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1102 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
ffe513da | 1103 | } |
6c646a11 | 1104 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1105 | |
1106 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1107 | ||
c52e7bbb | 1108 | if (!xen_enabled() && pcms->pit_enabled) { |
15eafc2e | 1109 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1110 | pit = kvm_pit_init(isa_bus, 0x40); |
1111 | } else { | |
acf695ec | 1112 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1113 | } |
1114 | if (hpet) { | |
1115 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1116 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 | 1117 | } |
6b8d1416 | 1118 | pcspk_init(pcms->pcspk, isa_bus, pit); |
ce967e2f | 1119 | } |
ffe513da | 1120 | |
55f613ac | 1121 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1122 | |
ac64273c | 1123 | /* Super I/O */ |
8859f072 | 1124 | pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); |
ffe513da IY |
1125 | } |
1126 | ||
4b9c264b | 1127 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1128 | { |
1129 | int i; | |
1130 | ||
bab47d9a | 1131 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1132 | for (i = 0; i < nb_nics; i++) { |
1133 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1134 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1135 | |
4b9c264b | 1136 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1137 | pc_init_ne2k_isa(isa_bus, nd); |
1138 | } else { | |
4b9c264b | 1139 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1140 | } |
1141 | } | |
bab47d9a | 1142 | rom_reset_order_override(); |
9011a1a7 IY |
1143 | } |
1144 | ||
4501d317 PMD |
1145 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1146 | { | |
1147 | qemu_irq *i8259; | |
1148 | ||
1149 | if (kvm_pic_in_kernel()) { | |
1150 | i8259 = kvm_i8259_init(isa_bus); | |
1151 | } else if (xen_enabled()) { | |
1152 | i8259 = xen_interrupt_controller_init(); | |
1153 | } else { | |
89a289c7 | 1154 | i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); |
4501d317 PMD |
1155 | } |
1156 | ||
1157 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1158 | i8259_irqs[i] = i8259[i]; | |
1159 | } | |
1160 | ||
1161 | g_free(i8259); | |
1162 | } | |
1163 | ||
d468115b DH |
1164 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1165 | Error **errp) | |
1166 | { | |
1167 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
50aef131 | 1168 | const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
b0e62443 | 1169 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1170 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1171 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1172 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1173 | Error *local_err = NULL; |
d468115b DH |
1174 | |
1175 | /* | |
1176 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1177 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1178 | * addition to cover this case. | |
1179 | */ | |
50aef131 | 1180 | if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { |
d468115b DH |
1181 | error_setg(errp, |
1182 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1183 | return; | |
1184 | } | |
1185 | ||
f6a0d06b | 1186 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1187 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1188 | return; | |
1189 | } | |
8f1ffe5b | 1190 | |
50aef131 | 1191 | hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); |
ae909496 TH |
1192 | if (local_err) { |
1193 | error_propagate(errp, local_err); | |
1194 | return; | |
1195 | } | |
1196 | ||
fd3416f5 | 1197 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1198 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1199 | } |
1200 | ||
bb6e2f7a DH |
1201 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1202 | DeviceState *dev, Error **errp) | |
95bee274 | 1203 | { |
95bee274 | 1204 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
50aef131 | 1205 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
f6a0d06b | 1206 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1207 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1208 | |
84fd5496 | 1209 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); |
b8865591 | 1210 | |
7f3cf2d6 | 1211 | if (is_nvdimm) { |
f6a0d06b | 1212 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1213 | } |
1214 | ||
50aef131 | 1215 | hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); |
95bee274 IM |
1216 | } |
1217 | ||
bb6e2f7a DH |
1218 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1219 | DeviceState *dev, Error **errp) | |
64fec58e | 1220 | { |
50aef131 | 1221 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
64fec58e | 1222 | |
8cd91ace HZ |
1223 | /* |
1224 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1225 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1226 | * addition to cover this case. | |
1227 | */ | |
50aef131 | 1228 | if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { |
dcfe4805 | 1229 | error_setg(errp, |
8cd91ace | 1230 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
dcfe4805 | 1231 | return; |
64fec58e TC |
1232 | } |
1233 | ||
b097cc52 | 1234 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
dcfe4805 MA |
1235 | error_setg(errp, "nvdimm device hot unplug is not supported yet."); |
1236 | return; | |
b097cc52 XG |
1237 | } |
1238 | ||
50aef131 | 1239 | hotplug_handler_unplug_request(x86ms->acpi_dev, dev, |
dcfe4805 | 1240 | errp); |
64fec58e TC |
1241 | } |
1242 | ||
bb6e2f7a DH |
1243 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1244 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1245 | { |
1246 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
50aef131 | 1247 | X86MachineState *x86ms = X86_MACHINE(hotplug_dev); |
f7d3e29d TC |
1248 | Error *local_err = NULL; |
1249 | ||
50aef131 | 1250 | hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); |
f7d3e29d TC |
1251 | if (local_err) { |
1252 | goto out; | |
1253 | } | |
1254 | ||
fd3416f5 | 1255 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
981c3dcd | 1256 | qdev_unrealize(dev); |
f7d3e29d TC |
1257 | out: |
1258 | error_propagate(errp, local_err); | |
1259 | } | |
1260 | ||
0ed48fd3 DH |
1261 | static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, |
1262 | DeviceState *dev, Error **errp) | |
a0a49813 DH |
1263 | { |
1264 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1265 | Error *local_err = NULL; | |
1266 | ||
af1d039f | 1267 | if (!hotplug_dev2 && dev->hotplugged) { |
a0a49813 DH |
1268 | /* |
1269 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
af1d039f DH |
1270 | * order. We should never reach this point when hotplugging on x86, |
1271 | * however, better add a safety net. | |
a0a49813 | 1272 | */ |
0ed48fd3 DH |
1273 | error_setg(errp, "hotplug of virtio based memory devices not supported" |
1274 | " on this bus."); | |
a0a49813 DH |
1275 | return; |
1276 | } | |
1277 | /* | |
1278 | * First, see if we can plug this memory device at all. If that | |
1279 | * succeeds, branch of to the actual hotplug handler. | |
1280 | */ | |
1281 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1282 | &local_err); | |
af1d039f | 1283 | if (!local_err && hotplug_dev2) { |
a0a49813 DH |
1284 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); |
1285 | } | |
1286 | error_propagate(errp, local_err); | |
1287 | } | |
1288 | ||
0ed48fd3 DH |
1289 | static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, |
1290 | DeviceState *dev, Error **errp) | |
a0a49813 DH |
1291 | { |
1292 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1293 | Error *local_err = NULL; | |
1294 | ||
1295 | /* | |
1296 | * Plug the memory device first and then branch off to the actual | |
1297 | * hotplug handler. If that one fails, we can easily undo the memory | |
1298 | * device bits. | |
1299 | */ | |
1300 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
af1d039f DH |
1301 | if (hotplug_dev2) { |
1302 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
1303 | if (local_err) { | |
1304 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1305 | } | |
a0a49813 DH |
1306 | } |
1307 | error_propagate(errp, local_err); | |
1308 | } | |
1309 | ||
0ed48fd3 DH |
1310 | static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, |
1311 | DeviceState *dev, Error **errp) | |
a0a49813 | 1312 | { |
0ed48fd3 DH |
1313 | /* We don't support hot unplug of virtio based memory devices */ |
1314 | error_setg(errp, "virtio based memory devices cannot be unplugged."); | |
a0a49813 DH |
1315 | } |
1316 | ||
0ed48fd3 DH |
1317 | static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, |
1318 | DeviceState *dev, Error **errp) | |
a0a49813 | 1319 | { |
0ed48fd3 | 1320 | /* We don't support hot unplug of virtio based memory devices */ |
a0a49813 DH |
1321 | } |
1322 | ||
4ec60c76 IM |
1323 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1324 | DeviceState *dev, Error **errp) | |
1325 | { | |
d468115b DH |
1326 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1327 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1328 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
0cca1a91 | 1329 | x86_cpu_pre_plug(hotplug_dev, dev, errp); |
0ed48fd3 DH |
1330 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || |
1331 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { | |
1332 | pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1333 | } |
1334 | } | |
1335 | ||
95bee274 IM |
1336 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1337 | DeviceState *dev, Error **errp) | |
1338 | { | |
1339 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1340 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e | 1341 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1342 | x86_cpu_plug(hotplug_dev, dev, errp); |
0ed48fd3 DH |
1343 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || |
1344 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { | |
1345 | pc_virtio_md_pci_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1346 | } |
1347 | } | |
1348 | ||
d9c5c5b8 TC |
1349 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1350 | DeviceState *dev, Error **errp) | |
1351 | { | |
64fec58e | 1352 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1353 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a | 1354 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1355 | x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); |
0ed48fd3 DH |
1356 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || |
1357 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { | |
1358 | pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); | |
64fec58e TC |
1359 | } else { |
1360 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1361 | " type: %s", object_get_typename(OBJECT(dev))); | |
1362 | } | |
d9c5c5b8 TC |
1363 | } |
1364 | ||
232391c1 TC |
1365 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1366 | DeviceState *dev, Error **errp) | |
1367 | { | |
f7d3e29d | 1368 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1369 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a | 1370 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
0cca1a91 | 1371 | x86_cpu_unplug_cb(hotplug_dev, dev, errp); |
0ed48fd3 DH |
1372 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || |
1373 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { | |
1374 | pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); | |
f7d3e29d TC |
1375 | } else { |
1376 | error_setg(errp, "acpi: device unplug for not supported device" | |
1377 | " type: %s", object_get_typename(OBJECT(dev))); | |
1378 | } | |
232391c1 TC |
1379 | } |
1380 | ||
285816d7 | 1381 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
1382 | DeviceState *dev) |
1383 | { | |
5279569e | 1384 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 | 1385 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
0ed48fd3 DH |
1386 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || |
1387 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { | |
95bee274 IM |
1388 | return HOTPLUG_HANDLER(machine); |
1389 | } | |
1390 | ||
38aefb57 | 1391 | return NULL; |
95bee274 IM |
1392 | } |
1393 | ||
bf1e8939 | 1394 | static void |
f2ffbe2b DH |
1395 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
1396 | const char *name, void *opaque, | |
1397 | Error **errp) | |
bf1e8939 | 1398 | { |
b0c14ec4 | 1399 | MachineState *ms = MACHINE(obj); |
fc3b77e2 IM |
1400 | int64_t value = 0; |
1401 | ||
1402 | if (ms->device_memory) { | |
1403 | value = memory_region_size(&ms->device_memory->mr); | |
1404 | } | |
bf1e8939 | 1405 | |
51e72bc1 | 1406 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
1407 | } |
1408 | ||
d7bce999 EB |
1409 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
1410 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1411 | { |
1412 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 1413 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 1414 | |
51e72bc1 | 1415 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
1416 | } |
1417 | ||
d7bce999 EB |
1418 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
1419 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1420 | { |
1421 | PCMachineState *pcms = PC_MACHINE(obj); | |
1422 | ||
51e72bc1 | 1423 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
1424 | } |
1425 | ||
be232eb0 CP |
1426 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
1427 | { | |
1428 | PCMachineState *pcms = PC_MACHINE(obj); | |
1429 | ||
f5878b03 | 1430 | return pcms->smbus_enabled; |
be232eb0 CP |
1431 | } |
1432 | ||
1433 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
1434 | { | |
1435 | PCMachineState *pcms = PC_MACHINE(obj); | |
1436 | ||
f5878b03 | 1437 | pcms->smbus_enabled = value; |
be232eb0 CP |
1438 | } |
1439 | ||
272f0428 CP |
1440 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
1441 | { | |
1442 | PCMachineState *pcms = PC_MACHINE(obj); | |
1443 | ||
f5878b03 | 1444 | return pcms->sata_enabled; |
272f0428 CP |
1445 | } |
1446 | ||
1447 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
1448 | { | |
1449 | PCMachineState *pcms = PC_MACHINE(obj); | |
1450 | ||
f5878b03 | 1451 | pcms->sata_enabled = value; |
272f0428 CP |
1452 | } |
1453 | ||
feddd2fd CP |
1454 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
1455 | { | |
1456 | PCMachineState *pcms = PC_MACHINE(obj); | |
1457 | ||
f5878b03 | 1458 | return pcms->pit_enabled; |
feddd2fd CP |
1459 | } |
1460 | ||
1461 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
1462 | { | |
1463 | PCMachineState *pcms = PC_MACHINE(obj); | |
1464 | ||
f5878b03 | 1465 | pcms->pit_enabled = value; |
feddd2fd CP |
1466 | } |
1467 | ||
0259c78c EH |
1468 | static bool pc_machine_get_hpet(Object *obj, Error **errp) |
1469 | { | |
1470 | PCMachineState *pcms = PC_MACHINE(obj); | |
1471 | ||
1472 | return pcms->hpet_enabled; | |
1473 | } | |
1474 | ||
1475 | static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) | |
1476 | { | |
1477 | PCMachineState *pcms = PC_MACHINE(obj); | |
1478 | ||
1479 | pcms->hpet_enabled = value; | |
1480 | } | |
1481 | ||
c9e96b04 XW |
1482 | static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) |
1483 | { | |
1484 | PCMachineState *pcms = PC_MACHINE(obj); | |
1485 | ||
1486 | return pcms->default_bus_bypass_iommu; | |
1487 | } | |
1488 | ||
1489 | static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, | |
1490 | Error **errp) | |
1491 | { | |
1492 | PCMachineState *pcms = PC_MACHINE(obj); | |
1493 | ||
1494 | pcms->default_bus_bypass_iommu = value; | |
1495 | } | |
1496 | ||
9a45729d GH |
1497 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
1498 | const char *name, void *opaque, | |
1499 | Error **errp) | |
1500 | { | |
1501 | PCMachineState *pcms = PC_MACHINE(obj); | |
1502 | uint64_t value = pcms->max_ram_below_4g; | |
1503 | ||
1504 | visit_type_size(v, name, &value, errp); | |
1505 | } | |
1506 | ||
1507 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
1508 | const char *name, void *opaque, | |
1509 | Error **errp) | |
1510 | { | |
1511 | PCMachineState *pcms = PC_MACHINE(obj); | |
9a45729d GH |
1512 | uint64_t value; |
1513 | ||
668f62ec | 1514 | if (!visit_type_size(v, name, &value, errp)) { |
9a45729d GH |
1515 | return; |
1516 | } | |
1517 | if (value > 4 * GiB) { | |
dcfe4805 | 1518 | error_setg(errp, |
9a45729d GH |
1519 | "Machine option 'max-ram-below-4g=%"PRIu64 |
1520 | "' expects size less than or equal to 4G", value); | |
9a45729d GH |
1521 | return; |
1522 | } | |
1523 | ||
1524 | if (value < 1 * MiB) { | |
1525 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," | |
1526 | "BIOS may not work with less than 1MiB", value); | |
1527 | } | |
1528 | ||
1529 | pcms->max_ram_below_4g = value; | |
1530 | } | |
1531 | ||
0657c657 EM |
1532 | static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, |
1533 | const char *name, void *opaque, | |
1534 | Error **errp) | |
1535 | { | |
1536 | PCMachineState *pcms = PC_MACHINE(obj); | |
1537 | uint64_t value = pcms->max_fw_size; | |
1538 | ||
1539 | visit_type_size(v, name, &value, errp); | |
1540 | } | |
1541 | ||
1542 | static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, | |
1543 | const char *name, void *opaque, | |
1544 | Error **errp) | |
1545 | { | |
1546 | PCMachineState *pcms = PC_MACHINE(obj); | |
1547 | Error *error = NULL; | |
1548 | uint64_t value; | |
1549 | ||
1550 | visit_type_size(v, name, &value, &error); | |
1551 | if (error) { | |
1552 | error_propagate(errp, error); | |
1553 | return; | |
1554 | } | |
1555 | ||
1556 | /* | |
1557 | * We don't have a theoretically justifiable exact lower bound on the base | |
1558 | * address of any flash mapping. In practice, the IO-APIC MMIO range is | |
1559 | * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free | |
1560 | * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in | |
1561 | * size. | |
1562 | */ | |
1563 | if (value > 16 * MiB) { | |
1564 | error_setg(errp, | |
1565 | "User specified max allowed firmware size %" PRIu64 " is " | |
1566 | "greater than 16MiB. If combined firwmare size exceeds " | |
1567 | "16MiB the system may not boot, or experience intermittent" | |
1568 | "stability issues.", | |
1569 | value); | |
1570 | return; | |
1571 | } | |
1572 | ||
1573 | pcms->max_fw_size = value; | |
1574 | } | |
1575 | ||
602b4582 | 1576 | |
bf1e8939 IM |
1577 | static void pc_machine_initfn(Object *obj) |
1578 | { | |
c87b1520 DS |
1579 | PCMachineState *pcms = PC_MACHINE(obj); |
1580 | ||
97fd1ea8 | 1581 | #ifdef CONFIG_VMPORT |
d1048bef | 1582 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
1583 | #else |
1584 | pcms->vmport = ON_OFF_AUTO_OFF; | |
1585 | #endif /* CONFIG_VMPORT */ | |
9a45729d | 1586 | pcms->max_ram_below_4g = 0; /* use default */ |
021746c1 WL |
1587 | /* acpi build is enabled by default if machine supports it */ |
1588 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
1589 | pcms->smbus_enabled = true; |
1590 | pcms->sata_enabled = true; | |
1591 | pcms->pit_enabled = true; | |
0657c657 | 1592 | pcms->max_fw_size = 8 * MiB; |
0259c78c EH |
1593 | #ifdef CONFIG_HPET |
1594 | pcms->hpet_enabled = true; | |
1595 | #endif | |
c9e96b04 | 1596 | pcms->default_bus_bypass_iommu = false; |
ebc29e1b MA |
1597 | |
1598 | pc_system_flash_create(pcms); | |
6b8d1416 | 1599 | pcms->pcspk = isa_new(TYPE_PC_SPEAKER); |
2e16ec05 GH |
1600 | object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", |
1601 | OBJECT(pcms->pcspk), "audiodev"); | |
bf1e8939 IM |
1602 | } |
1603 | ||
a0628599 | 1604 | static void pc_machine_reset(MachineState *machine) |
ae50c55a ZG |
1605 | { |
1606 | CPUState *cs; | |
1607 | X86CPU *cpu; | |
1608 | ||
1609 | qemu_devices_reset(); | |
1610 | ||
1611 | /* Reset APIC after devices have been reset to cancel | |
1612 | * any changes that qemu_devices_reset() might have done. | |
1613 | */ | |
1614 | CPU_FOREACH(cs) { | |
1615 | cpu = X86_CPU(cs); | |
1616 | ||
1617 | if (cpu->apic_state) { | |
f703a04c | 1618 | device_legacy_reset(cpu->apic_state); |
ae50c55a ZG |
1619 | } |
1620 | } | |
1621 | } | |
1622 | ||
c508bd12 NP |
1623 | static void pc_machine_wakeup(MachineState *machine) |
1624 | { | |
1625 | cpu_synchronize_all_states(); | |
1626 | pc_machine_reset(machine); | |
1627 | cpu_synchronize_all_post_reset(); | |
1628 | } | |
1629 | ||
c6cbc29d PX |
1630 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
1631 | { | |
1632 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
1633 | IntelIOMMUState *intel_iommu; | |
1634 | ||
1635 | if (iommu && | |
1636 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
1637 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
1638 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
1639 | if (!intel_iommu->caching_mode) { | |
1640 | error_setg(errp, "Device assignment is not allowed without " | |
1641 | "enabling caching-mode=on for Intel IOMMU."); | |
1642 | return false; | |
1643 | } | |
1644 | } | |
1645 | ||
1646 | return true; | |
1647 | } | |
1648 | ||
95bee274 IM |
1649 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1650 | { | |
1651 | MachineClass *mc = MACHINE_CLASS(oc); | |
1652 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1653 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1654 | ||
7102fa70 EH |
1655 | pcmc->pci_enabled = true; |
1656 | pcmc->has_acpi_build = true; | |
1657 | pcmc->rsdp_in_ram = true; | |
1658 | pcmc->smbios_defaults = true; | |
1659 | pcmc->smbios_uuid_encoded = true; | |
1660 | pcmc->gigabyte_align = true; | |
1661 | pcmc->has_reserved_memory = true; | |
1662 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 1663 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
1664 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
1665 | * to be used at the moment, 32K should be enough for a while. */ | |
1666 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
fda672b5 | 1667 | pcmc->pvh_enabled = true; |
8700a984 | 1668 | pcmc->kvmclock_create_always = true; |
debbdc00 | 1669 | assert(!mc->get_hotplug_handler); |
285816d7 | 1670 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 1671 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
1672 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
1673 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
1674 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 1675 | mc->auto_enable_numa_with_memhp = true; |
195784a0 | 1676 | mc->auto_enable_numa_with_memdev = true; |
c5514d0e | 1677 | mc->has_hotpluggable_cpus = true; |
41742767 | 1678 | mc->default_boot_order = "cad"; |
2059839b | 1679 | mc->block_default_type = IF_IDE; |
4458fb3a | 1680 | mc->max_cpus = 255; |
ae50c55a | 1681 | mc->reset = pc_machine_reset; |
c508bd12 | 1682 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 1683 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 1684 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 1685 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 1686 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 1687 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 1688 | mc->nvdimm_supported = true; |
e4a97a89 | 1689 | mc->smp_props.dies_supported = true; |
bd457782 | 1690 | mc->default_ram_id = "pc.ram"; |
0efc257d | 1691 | |
9a45729d GH |
1692 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", |
1693 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
1694 | NULL, NULL); | |
1695 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
1696 | "Maximum ram below the 4G boundary (32bit boundary)"); | |
1697 | ||
f2ffbe2b DH |
1698 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
1699 | pc_machine_get_device_memory_region_size, NULL, | |
d2623129 | 1700 | NULL, NULL); |
0efc257d | 1701 | |
0efc257d EH |
1702 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", |
1703 | pc_machine_get_vmport, pc_machine_set_vmport, | |
d2623129 | 1704 | NULL, NULL); |
0efc257d | 1705 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, |
7eecec7d | 1706 | "Enable vmport (pc & q35)"); |
0efc257d | 1707 | |
be232eb0 | 1708 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
d2623129 | 1709 | pc_machine_get_smbus, pc_machine_set_smbus); |
272f0428 CP |
1710 | |
1711 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
d2623129 | 1712 | pc_machine_get_sata, pc_machine_set_sata); |
feddd2fd CP |
1713 | |
1714 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
d2623129 | 1715 | pc_machine_get_pit, pc_machine_set_pit); |
0259c78c EH |
1716 | |
1717 | object_class_property_add_bool(oc, "hpet", | |
1718 | pc_machine_get_hpet, pc_machine_set_hpet); | |
0657c657 | 1719 | |
c9e96b04 XW |
1720 | object_class_property_add_bool(oc, "default_bus_bypass_iommu", |
1721 | pc_machine_get_default_bus_bypass_iommu, | |
1722 | pc_machine_set_default_bus_bypass_iommu); | |
1723 | ||
0657c657 EM |
1724 | object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", |
1725 | pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, | |
1726 | NULL, NULL); | |
1727 | object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, | |
1728 | "Maximum combined firmware size"); | |
95bee274 IM |
1729 | } |
1730 | ||
d5747cac IM |
1731 | static const TypeInfo pc_machine_info = { |
1732 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 1733 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
1734 | .abstract = true, |
1735 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 1736 | .instance_init = pc_machine_initfn, |
d5747cac | 1737 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
1738 | .class_init = pc_machine_class_init, |
1739 | .interfaces = (InterfaceInfo[]) { | |
1740 | { TYPE_HOTPLUG_HANDLER }, | |
1741 | { } | |
1742 | }, | |
d5747cac IM |
1743 | }; |
1744 | ||
1745 | static void pc_machine_register_types(void) | |
1746 | { | |
1747 | type_register_static(&pc_machine_info); | |
1748 | } | |
1749 | ||
1750 | type_init(pc_machine_register_types) |