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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
549e984e | 27 | #include "hw/i386/x86.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 | 32 | #include "hw/i386/topology.h" |
87abaa5d | 33 | #include "hw/i386/fw_cfg.h" |
54a40293 | 34 | #include "sysemu/cpus.h" |
0d09e41a | 35 | #include "hw/block/fdc.h" |
83c9f4ca PB |
36 | #include "hw/ide.h" |
37 | #include "hw/pci/pci.h" | |
2118196b | 38 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
39 | #include "hw/nvram/fw_cfg.h" |
40 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 41 | #include "hw/firmware/smbios.h" |
83c9f4ca | 42 | #include "hw/loader.h" |
ca20cf32 | 43 | #include "elf.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
47b43a1f | 45 | #include "multiboot.h" |
bcdb9064 | 46 | #include "hw/rtc/mc146818rtc.h" |
852c27e2 | 47 | #include "hw/intc/i8259.h" |
55f613ac | 48 | #include "hw/dma/i8257.h" |
0d09e41a | 49 | #include "hw/timer/i8254.h" |
47973a2d | 50 | #include "hw/input/i8042.h" |
64552b6b | 51 | #include "hw/irq.h" |
0d09e41a | 52 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
53 | #include "hw/pci/msi.h" |
54 | #include "hw/sysbus.h" | |
9c17d615 | 55 | #include "sysemu/sysemu.h" |
14a48c1d | 56 | #include "sysemu/tcg.h" |
e35704ba | 57 | #include "sysemu/numa.h" |
9c17d615 | 58 | #include "sysemu/kvm.h" |
b1c12027 | 59 | #include "sysemu/qtest.h" |
71e8a915 | 60 | #include "sysemu/reset.h" |
54d31236 | 61 | #include "sysemu/runstate.h" |
1d31f66b | 62 | #include "kvm_i386.h" |
0d09e41a | 63 | #include "hw/xen/xen.h" |
ab969087 | 64 | #include "hw/xen/start_info.h" |
a19cbfb3 | 65 | #include "ui/qemu-spice.h" |
022c62cb PB |
66 | #include "exec/memory.h" |
67 | #include "exec/address-spaces.h" | |
9c17d615 | 68 | #include "sysemu/arch_init.h" |
1de7afc9 | 69 | #include "qemu/bitmap.h" |
0c764a9d | 70 | #include "qemu/config-file.h" |
d49b6836 | 71 | #include "qemu/error-report.h" |
922a01a0 | 72 | #include "qemu/option.h" |
133ef074 | 73 | #include "qemu/cutils.h" |
0445259b | 74 | #include "hw/acpi/acpi.h" |
5ff020b7 | 75 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 76 | #include "hw/boards.h" |
72c194f7 | 77 | #include "acpi-build.h" |
95bee274 | 78 | #include "hw/mem/pc-dimm.h" |
e688df6b | 79 | #include "qapi/error.h" |
9af23989 | 80 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 81 | #include "qapi/visitor.h" |
2e5b09fd | 82 | #include "hw/core/cpu.h" |
a310e653 | 83 | #include "hw/usb.h" |
60c5e104 | 84 | #include "hw/i386/intel_iommu.h" |
489983d6 | 85 | #include "hw/net/ne2000-isa.h" |
06e0259a | 86 | #include "standard-headers/asm-x86/bootparam.h" |
a0a49813 DH |
87 | #include "hw/virtio/virtio-pmem-pci.h" |
88 | #include "hw/mem/memory-device.h" | |
6f479566 LX |
89 | #include "sysemu/replay.h" |
90 | #include "qapi/qmp/qerror.h" | |
97fd1ea8 | 91 | #include "config-devices.h" |
d6d059ca | 92 | #include "e820_memory_layout.h" |
149c50ca | 93 | #include "fw_cfg.h" |
4ca8dabd | 94 | #include "trace.h" |
471fd342 | 95 | |
3eb74d20 CH |
96 | GlobalProperty pc_compat_4_2[] = {}; |
97 | const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); | |
98 | ||
9aec2e52 CH |
99 | GlobalProperty pc_compat_4_1[] = {}; |
100 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
101 | ||
9bf2650b CH |
102 | GlobalProperty pc_compat_4_0[] = {}; |
103 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
104 | ||
abd93cc7 | 105 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 106 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
107 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
108 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
109 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
110 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 111 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
112 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
113 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
114 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
115 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
116 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
117 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
118 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
119 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
120 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
121 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
122 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
123 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
124 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 125 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 126 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
127 | }; |
128 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
129 | ||
ddb3235d | 130 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
131 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
132 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
133 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
134 | }; |
135 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
136 | ||
0d47310b | 137 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
138 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
139 | { TYPE_X86_CPU, "topoext", "off" }, | |
140 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
141 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
142 | }; |
143 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
144 | ||
43df70a9 | 145 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
146 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
147 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
148 | }; |
149 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
150 | ||
503224f4 | 151 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
152 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
153 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
154 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
155 | }; |
156 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
157 | ||
3e803152 | 158 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 159 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
160 | }; |
161 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
162 | ||
edc24ccd | 163 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
164 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
165 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
166 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
167 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
168 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
169 | }; |
170 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
171 | ||
5a995064 | 172 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
173 | { TYPE_X86_CPU, "l3-cache", "off" }, |
174 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
175 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
176 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
177 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
178 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
179 | }; |
180 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
181 | ||
ff8f261f | 182 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
183 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
184 | { "vmxnet3", "romfile", "" }, | |
185 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
186 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
187 | }; |
188 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
189 | ||
fe759610 MAL |
190 | GlobalProperty pc_compat_2_5[] = {}; |
191 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
192 | ||
2f99b9c2 MAL |
193 | GlobalProperty pc_compat_2_4[] = { |
194 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
195 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
196 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
197 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
198 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
199 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
200 | { TYPE_X86_CPU, "check", "off" }, | |
201 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
202 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
203 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
204 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
205 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
206 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
207 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
208 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
209 | }; |
210 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
211 | ||
8995dd90 MAL |
212 | GlobalProperty pc_compat_2_3[] = { |
213 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
214 | { TYPE_X86_CPU, "arat", "off" }, |
215 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
216 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
217 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
218 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
219 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
220 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
221 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
222 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
223 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
224 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
225 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
226 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
227 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
228 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
229 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
230 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
231 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
232 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
233 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
234 | }; |
235 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
236 | ||
1c30044e MAL |
237 | GlobalProperty pc_compat_2_2[] = { |
238 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
239 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
240 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
241 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
242 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
243 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
244 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
245 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
246 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
247 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
248 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
249 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
250 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
251 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
252 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
253 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
254 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
255 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
256 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
257 | }; |
258 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
259 | ||
c4fc5695 MAL |
260 | GlobalProperty pc_compat_2_1[] = { |
261 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
262 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
263 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
264 | }; |
265 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
266 | ||
a310e653 MAL |
267 | GlobalProperty pc_compat_2_0[] = { |
268 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
269 | { "virtio-scsi-pci", "any_layout", "off" }, |
270 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
271 | { "apic", "version", "0x11" }, | |
272 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
273 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
274 | { "pci-serial", "prog_if", "0" }, | |
275 | { "pci-serial-2x", "prog_if", "0" }, | |
276 | { "pci-serial-4x", "prog_if", "0" }, | |
277 | { "virtio-net-pci", "guest_announce", "off" }, | |
278 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
279 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
280 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
a310e653 MAL |
281 | }; |
282 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
283 | ||
284 | GlobalProperty pc_compat_1_7[] = { | |
285 | PC_CPU_MODEL_IDS("1.7.0") | |
6c36bddf EH |
286 | { TYPE_USB_DEVICE, "msos-desc", "no" }, |
287 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
288 | { "hpet", HPET_INTCAP, "4" }, | |
a310e653 MAL |
289 | }; |
290 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
291 | ||
292 | GlobalProperty pc_compat_1_6[] = { | |
293 | PC_CPU_MODEL_IDS("1.6.0") | |
6c36bddf EH |
294 | { "e1000", "mitigation", "off" }, |
295 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
296 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
297 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
298 | { "q35-pcihost", "short_root_bus", "1" }, | |
a310e653 MAL |
299 | }; |
300 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
301 | ||
302 | GlobalProperty pc_compat_1_5[] = { | |
303 | PC_CPU_MODEL_IDS("1.5.0") | |
6c36bddf EH |
304 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, |
305 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
306 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
307 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
308 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
309 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
310 | { "virtio-net-pci", "any_layout", "off" }, | |
311 | { TYPE_X86_CPU, "pmu", "on" }, | |
312 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
313 | { "q35-pcihost", "short_root_bus", "0" }, | |
a310e653 MAL |
314 | }; |
315 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
316 | ||
317 | GlobalProperty pc_compat_1_4[] = { | |
318 | PC_CPU_MODEL_IDS("1.4.0") | |
6c36bddf EH |
319 | { "scsi-hd", "discard_granularity", "0" }, |
320 | { "scsi-cd", "discard_granularity", "0" }, | |
321 | { "scsi-disk", "discard_granularity", "0" }, | |
322 | { "ide-hd", "discard_granularity", "0" }, | |
323 | { "ide-cd", "discard_granularity", "0" }, | |
324 | { "ide-drive", "discard_granularity", "0" }, | |
325 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
326 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
327 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
328 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
329 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
330 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
331 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
332 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
333 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
334 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
335 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
336 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
a310e653 MAL |
337 | }; |
338 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
339 | ||
b881fbe9 | 340 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 341 | { |
b881fbe9 | 342 | GSIState *s = opaque; |
1452411b | 343 | |
4ca8dabd | 344 | trace_pc_gsi_interrupt(n, level); |
b881fbe9 JK |
345 | if (n < ISA_NUM_IRQS) { |
346 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 347 | } |
b881fbe9 | 348 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 349 | } |
1452411b | 350 | |
417258f1 PMD |
351 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
352 | { | |
353 | GSIState *s; | |
354 | ||
355 | s = g_new0(GSIState, 1); | |
356 | if (kvm_ioapic_in_kernel()) { | |
357 | kvm_pc_setup_irq_routing(pci_enabled); | |
358 | *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS); | |
359 | } else { | |
360 | *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); | |
361 | } | |
362 | ||
363 | return s; | |
364 | } | |
365 | ||
258711c6 JG |
366 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
367 | unsigned size) | |
80cabfad FB |
368 | { |
369 | } | |
370 | ||
c02e1eac JG |
371 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
372 | { | |
a6fc23e5 | 373 | return 0xffffffffffffffffULL; |
c02e1eac JG |
374 | } |
375 | ||
f929aad6 | 376 | /* MSDOS compatibility mode FPU exception support */ |
258711c6 JG |
377 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
378 | unsigned size) | |
f929aad6 | 379 | { |
6f529b75 | 380 | if (tcg_enabled()) { |
bf13bfab | 381 | cpu_set_ignne(); |
6f529b75 | 382 | } |
f929aad6 FB |
383 | } |
384 | ||
c02e1eac JG |
385 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
386 | { | |
a6fc23e5 | 387 | return 0xffffffffffffffffULL; |
c02e1eac JG |
388 | } |
389 | ||
28ab0e2e | 390 | /* TSC handling */ |
28ab0e2e FB |
391 | uint64_t cpu_get_tsc(CPUX86State *env) |
392 | { | |
4a1418e0 | 393 | return cpu_get_ticks(); |
28ab0e2e FB |
394 | } |
395 | ||
3de388f6 | 396 | /* IRQ handling */ |
4a8fa5dc | 397 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 398 | { |
6aa9e42f | 399 | X86CPU *cpu = env_archcpu(env); |
3de388f6 FB |
400 | int intno; |
401 | ||
bb93e099 WL |
402 | if (!kvm_irqchip_in_kernel()) { |
403 | intno = apic_get_interrupt(cpu->apic_state); | |
404 | if (intno >= 0) { | |
405 | return intno; | |
406 | } | |
407 | /* read the irq from the PIC */ | |
408 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
409 | return -1; | |
410 | } | |
cf6d64bf | 411 | } |
0e21e12b | 412 | |
3de388f6 FB |
413 | intno = pic_read_irq(isa_pic); |
414 | return intno; | |
415 | } | |
416 | ||
d537cf6c | 417 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 418 | { |
182735ef AF |
419 | CPUState *cs = first_cpu; |
420 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 421 | |
4ca8dabd | 422 | trace_pc_pic_interrupt(irq, level); |
bb93e099 | 423 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 424 | CPU_FOREACH(cs) { |
182735ef | 425 | cpu = X86_CPU(cs); |
02e51483 CF |
426 | if (apic_accept_pic_intr(cpu->apic_state)) { |
427 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 428 | } |
d5529471 AJ |
429 | } |
430 | } else { | |
d8ed887b | 431 | if (level) { |
c3affe56 | 432 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
433 | } else { |
434 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
435 | } | |
a5b38b51 | 436 | } |
3de388f6 FB |
437 | } |
438 | ||
b0a21b53 FB |
439 | /* PC cmos mappings */ |
440 | ||
80cabfad FB |
441 | #define REG_EQUIPMENT_BYTE 0x14 |
442 | ||
bda05509 | 443 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
444 | { |
445 | int val; | |
446 | ||
447 | switch (fd0) { | |
2da44dd0 | 448 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
449 | /* 1.44 Mb 3"5 drive */ |
450 | val = 4; | |
451 | break; | |
2da44dd0 | 452 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
453 | /* 2.88 Mb 3"5 drive */ |
454 | val = 5; | |
455 | break; | |
2da44dd0 | 456 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
457 | /* 1.2 Mb 5"5 drive */ |
458 | val = 2; | |
459 | break; | |
2da44dd0 | 460 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
461 | default: |
462 | val = 0; | |
463 | break; | |
464 | } | |
465 | return val; | |
466 | } | |
467 | ||
9139046c MA |
468 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
469 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 470 | { |
ba6c2377 FB |
471 | rtc_set_memory(s, type_ofs, 47); |
472 | rtc_set_memory(s, info_ofs, cylinders); | |
473 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
474 | rtc_set_memory(s, info_ofs + 2, heads); | |
475 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
476 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
477 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
478 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
479 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
480 | rtc_set_memory(s, info_ofs + 8, sectors); | |
481 | } | |
482 | ||
6ac0e82d AZ |
483 | /* convert boot_device letter to something recognizable by the bios */ |
484 | static int boot_device2nibble(char boot_device) | |
485 | { | |
486 | switch(boot_device) { | |
487 | case 'a': | |
488 | case 'b': | |
489 | return 0x01; /* floppy boot */ | |
490 | case 'c': | |
491 | return 0x02; /* hard drive boot */ | |
492 | case 'd': | |
493 | return 0x03; /* CD-ROM boot */ | |
494 | case 'n': | |
495 | return 0x04; /* Network boot */ | |
496 | } | |
497 | return 0; | |
498 | } | |
499 | ||
ddcd5531 | 500 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
501 | { |
502 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
503 | int nbds, bds[3] = { 0, }; |
504 | int i; | |
505 | ||
506 | nbds = strlen(boot_device); | |
507 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
508 | error_setg(errp, "Too many boot devices for PC"); |
509 | return; | |
0ecdffbb AJ |
510 | } |
511 | for (i = 0; i < nbds; i++) { | |
512 | bds[i] = boot_device2nibble(boot_device[i]); | |
513 | if (bds[i] == 0) { | |
ddcd5531 GA |
514 | error_setg(errp, "Invalid boot device for PC: '%c'", |
515 | boot_device[i]); | |
516 | return; | |
0ecdffbb AJ |
517 | } |
518 | } | |
519 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 520 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
521 | } |
522 | ||
ddcd5531 | 523 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 524 | { |
ddcd5531 | 525 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
526 | } |
527 | ||
7444ca4e LE |
528 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
529 | { | |
530 | int val, nb, i; | |
2da44dd0 JS |
531 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
532 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
533 | |
534 | /* floppy type */ | |
535 | if (floppy) { | |
536 | for (i = 0; i < 2; i++) { | |
537 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
538 | } | |
539 | } | |
540 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
541 | cmos_get_fd_drive_type(fd_type[1]); | |
542 | rtc_set_memory(rtc_state, 0x10, val); | |
543 | ||
544 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
545 | nb = 0; | |
2da44dd0 | 546 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
547 | nb++; |
548 | } | |
2da44dd0 | 549 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
550 | nb++; |
551 | } | |
552 | switch (nb) { | |
553 | case 0: | |
554 | break; | |
555 | case 1: | |
556 | val |= 0x01; /* 1 drive, ready for boot */ | |
557 | break; | |
558 | case 2: | |
559 | val |= 0x41; /* 2 drives, ready for boot */ | |
560 | break; | |
561 | } | |
562 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
563 | } | |
564 | ||
c0897e0c MA |
565 | typedef struct pc_cmos_init_late_arg { |
566 | ISADevice *rtc_state; | |
9139046c | 567 | BusState *idebus[2]; |
c0897e0c MA |
568 | } pc_cmos_init_late_arg; |
569 | ||
b86f4613 LE |
570 | typedef struct check_fdc_state { |
571 | ISADevice *floppy; | |
572 | bool multiple; | |
573 | } CheckFdcState; | |
574 | ||
575 | static int check_fdc(Object *obj, void *opaque) | |
576 | { | |
577 | CheckFdcState *state = opaque; | |
578 | Object *fdc; | |
579 | uint32_t iobase; | |
580 | Error *local_err = NULL; | |
581 | ||
582 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
583 | if (!fdc) { | |
584 | return 0; | |
585 | } | |
586 | ||
1ea1572a | 587 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
588 | if (local_err || iobase != 0x3f0) { |
589 | error_free(local_err); | |
590 | return 0; | |
591 | } | |
592 | ||
593 | if (state->floppy) { | |
594 | state->multiple = true; | |
595 | } else { | |
596 | state->floppy = ISA_DEVICE(obj); | |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
601 | static const char * const fdc_container_path[] = { | |
602 | "/unattached", "/peripheral", "/peripheral-anon" | |
603 | }; | |
604 | ||
424e4a87 RK |
605 | /* |
606 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
607 | * and ACPI objects. | |
608 | */ | |
609 | ISADevice *pc_find_fdc0(void) | |
610 | { | |
611 | int i; | |
612 | Object *container; | |
613 | CheckFdcState state = { 0 }; | |
614 | ||
615 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
616 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
617 | object_child_foreach(container, check_fdc, &state); | |
618 | } | |
619 | ||
620 | if (state.multiple) { | |
3dc6f869 AF |
621 | warn_report("multiple floppy disk controllers with " |
622 | "iobase=0x3f0 have been found"); | |
433672b0 | 623 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 624 | "your intent"); |
424e4a87 RK |
625 | } |
626 | ||
627 | return state.floppy; | |
628 | } | |
629 | ||
c0897e0c MA |
630 | static void pc_cmos_init_late(void *opaque) |
631 | { | |
632 | pc_cmos_init_late_arg *arg = opaque; | |
633 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
634 | int16_t cylinders; |
635 | int8_t heads, sectors; | |
c0897e0c | 636 | int val; |
2adc99b2 | 637 | int i, trans; |
c0897e0c | 638 | |
9139046c | 639 | val = 0; |
272f0428 CP |
640 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
641 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
642 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
643 | val |= 0xf0; | |
644 | } | |
272f0428 CP |
645 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
646 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
647 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
648 | val |= 0x0f; | |
649 | } | |
650 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
651 | |
652 | val = 0; | |
653 | for (i = 0; i < 4; i++) { | |
9139046c MA |
654 | /* NOTE: ide_get_geometry() returns the physical |
655 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
656 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
657 | geometry can be different if a translation is done. */ | |
272f0428 CP |
658 | if (arg->idebus[i / 2] && |
659 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 660 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
661 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
662 | assert((trans & ~3) == 0); | |
663 | val |= trans << (i * 2); | |
c0897e0c MA |
664 | } |
665 | } | |
666 | rtc_set_memory(s, 0x39, val); | |
667 | ||
424e4a87 | 668 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 669 | |
c0897e0c MA |
670 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
671 | } | |
672 | ||
23d30407 | 673 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 674 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 675 | ISADevice *s) |
80cabfad | 676 | { |
7444ca4e | 677 | int val; |
c0897e0c | 678 | static pc_cmos_init_late_arg arg; |
f0bb276b | 679 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b0a21b53 | 680 | |
b0a21b53 | 681 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
682 | |
683 | /* memory size */ | |
e89001f7 | 684 | /* base memory (first MiB) */ |
f0bb276b | 685 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
333190eb FB |
686 | rtc_set_memory(s, 0x15, val); |
687 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 688 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
689 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
690 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
691 | } else { |
692 | val = 0; | |
693 | } | |
80cabfad FB |
694 | if (val > 65535) |
695 | val = 65535; | |
b0a21b53 FB |
696 | rtc_set_memory(s, 0x17, val); |
697 | rtc_set_memory(s, 0x18, val >> 8); | |
698 | rtc_set_memory(s, 0x30, val); | |
699 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 700 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
701 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
702 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 703 | } else { |
9da98861 | 704 | val = 0; |
e89001f7 | 705 | } |
80cabfad FB |
706 | if (val > 65535) |
707 | val = 65535; | |
b0a21b53 FB |
708 | rtc_set_memory(s, 0x34, val); |
709 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 710 | /* memory above 4GiB */ |
f0bb276b | 711 | val = x86ms->above_4g_mem_size / 65536; |
e89001f7 MA |
712 | rtc_set_memory(s, 0x5b, val); |
713 | rtc_set_memory(s, 0x5c, val >> 8); | |
714 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 715 | |
23d30407 | 716 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 717 | TYPE_ISA_DEVICE, |
f0bb276b | 718 | (Object **)&x86ms->rtc, |
2d996150 | 719 | object_property_allow_set_link, |
265b578c | 720 | OBJ_PROP_LINK_STRONG, &error_abort); |
23d30407 | 721 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 722 | "rtc_state", &error_abort); |
298e01b6 | 723 | |
007b0657 | 724 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 725 | |
b0a21b53 | 726 | val = 0; |
b0a21b53 FB |
727 | val |= 0x02; /* FPU is there */ |
728 | val |= 0x04; /* PS/2 mouse installed */ | |
729 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
730 | ||
b86f4613 | 731 | /* hard drives and FDC */ |
c0897e0c | 732 | arg.rtc_state = s; |
9139046c MA |
733 | arg.idebus[0] = idebus0; |
734 | arg.idebus[1] = idebus1; | |
c0897e0c | 735 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
736 | } |
737 | ||
a0881c64 AF |
738 | #define TYPE_PORT92 "port92" |
739 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
740 | ||
4b78a802 BS |
741 | /* port 92 stuff: could be split off */ |
742 | typedef struct Port92State { | |
a0881c64 AF |
743 | ISADevice parent_obj; |
744 | ||
23af670e | 745 | MemoryRegion io; |
4b78a802 | 746 | uint8_t outport; |
d812b3d6 | 747 | qemu_irq a20_out; |
4b78a802 BS |
748 | } Port92State; |
749 | ||
93ef4192 AG |
750 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
751 | unsigned size) | |
4b78a802 BS |
752 | { |
753 | Port92State *s = opaque; | |
4700a316 | 754 | int oldval = s->outport; |
4b78a802 | 755 | |
4ca8dabd | 756 | trace_port92_write(val); |
4b78a802 | 757 | s->outport = val; |
d812b3d6 | 758 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 759 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 760 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
761 | } |
762 | } | |
763 | ||
93ef4192 AG |
764 | static uint64_t port92_read(void *opaque, hwaddr addr, |
765 | unsigned size) | |
4b78a802 BS |
766 | { |
767 | Port92State *s = opaque; | |
768 | uint32_t ret; | |
769 | ||
770 | ret = s->outport; | |
4ca8dabd | 771 | trace_port92_read(ret); |
4b78a802 BS |
772 | return ret; |
773 | } | |
774 | ||
d80fe99d | 775 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 776 | { |
d80fe99d | 777 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
778 | } |
779 | ||
780 | static const VMStateDescription vmstate_port92_isa = { | |
781 | .name = "port92", | |
782 | .version_id = 1, | |
783 | .minimum_version_id = 1, | |
d49805ae | 784 | .fields = (VMStateField[]) { |
4b78a802 BS |
785 | VMSTATE_UINT8(outport, Port92State), |
786 | VMSTATE_END_OF_LIST() | |
787 | } | |
788 | }; | |
789 | ||
790 | static void port92_reset(DeviceState *d) | |
791 | { | |
a0881c64 | 792 | Port92State *s = PORT92(d); |
4b78a802 BS |
793 | |
794 | s->outport &= ~1; | |
795 | } | |
796 | ||
23af670e | 797 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
798 | .read = port92_read, |
799 | .write = port92_write, | |
800 | .impl = { | |
801 | .min_access_size = 1, | |
802 | .max_access_size = 1, | |
803 | }, | |
804 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
805 | }; |
806 | ||
db895a1e | 807 | static void port92_initfn(Object *obj) |
4b78a802 | 808 | { |
db895a1e | 809 | Port92State *s = PORT92(obj); |
4b78a802 | 810 | |
1437c94b | 811 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 812 | |
4b78a802 | 813 | s->outport = 0; |
d812b3d6 EV |
814 | |
815 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
816 | } |
817 | ||
818 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
819 | { | |
820 | ISADevice *isadev = ISA_DEVICE(dev); | |
821 | Port92State *s = PORT92(dev); | |
822 | ||
823 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
824 | } |
825 | ||
8f04ee08 AL |
826 | static void port92_class_initfn(ObjectClass *klass, void *data) |
827 | { | |
39bffca2 | 828 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 829 | |
db895a1e | 830 | dc->realize = port92_realizefn; |
39bffca2 AL |
831 | dc->reset = port92_reset; |
832 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
833 | /* |
834 | * Reason: unlike ordinary ISA devices, this one needs additional | |
835 | * wiring: its A20 output line needs to be wired up by | |
836 | * port92_init(). | |
837 | */ | |
e90f2a8c | 838 | dc->user_creatable = false; |
8f04ee08 AL |
839 | } |
840 | ||
8c43a6f0 | 841 | static const TypeInfo port92_info = { |
a0881c64 | 842 | .name = TYPE_PORT92, |
39bffca2 AL |
843 | .parent = TYPE_ISA_DEVICE, |
844 | .instance_size = sizeof(Port92State), | |
db895a1e | 845 | .instance_init = port92_initfn, |
39bffca2 | 846 | .class_init = port92_class_initfn, |
4b78a802 BS |
847 | }; |
848 | ||
83f7d43a | 849 | static void port92_register_types(void) |
4b78a802 | 850 | { |
39bffca2 | 851 | type_register_static(&port92_info); |
4b78a802 | 852 | } |
83f7d43a AF |
853 | |
854 | type_init(port92_register_types) | |
4b78a802 | 855 | |
956a3e6b | 856 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 857 | { |
cc36a7a2 | 858 | X86CPU *cpu = opaque; |
e1a23744 | 859 | |
956a3e6b | 860 | /* XXX: send to all CPUs ? */ |
4b78a802 | 861 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 862 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
863 | } |
864 | ||
b41a2cd1 FB |
865 | #define NE2000_NB_MAX 6 |
866 | ||
675d6f82 BS |
867 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
868 | 0x280, 0x380 }; | |
869 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 870 | |
48a18b3c | 871 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
872 | { |
873 | static int nb_ne2k = 0; | |
874 | ||
875 | if (nb_ne2k == NE2000_NB_MAX) | |
876 | return; | |
48a18b3c | 877 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 878 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
879 | nb_ne2k++; |
880 | } | |
881 | ||
92a16d7a | 882 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 883 | { |
4917cf44 AF |
884 | if (current_cpu) { |
885 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 886 | return cpu->apic_state; |
0e26b7b8 BS |
887 | } else { |
888 | return NULL; | |
889 | } | |
890 | } | |
891 | ||
845773ab | 892 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 893 | { |
c3affe56 | 894 | X86CPU *cpu = opaque; |
53b67b30 BS |
895 | |
896 | if (level) { | |
c3affe56 | 897 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
898 | } |
899 | } | |
900 | ||
6f479566 LX |
901 | /* |
902 | * This function is very similar to smp_parse() | |
903 | * in hw/core/machine.c but includes CPU die support. | |
904 | */ | |
905 | void pc_smp_parse(MachineState *ms, QemuOpts *opts) | |
906 | { | |
f0bb276b | 907 | X86MachineState *x86ms = X86_MACHINE(ms); |
1b458422 | 908 | |
6f479566 LX |
909 | if (opts) { |
910 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
911 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
1b458422 | 912 | unsigned dies = qemu_opt_get_number(opts, "dies", 1); |
6f479566 LX |
913 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); |
914 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
915 | ||
916 | /* compute missing values, prefer sockets over cores over threads */ | |
917 | if (cpus == 0 || sockets == 0) { | |
918 | cores = cores > 0 ? cores : 1; | |
919 | threads = threads > 0 ? threads : 1; | |
920 | if (cpus == 0) { | |
921 | sockets = sockets > 0 ? sockets : 1; | |
1b458422 | 922 | cpus = cores * threads * dies * sockets; |
6f479566 LX |
923 | } else { |
924 | ms->smp.max_cpus = | |
925 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1b458422 | 926 | sockets = ms->smp.max_cpus / (cores * threads * dies); |
6f479566 LX |
927 | } |
928 | } else if (cores == 0) { | |
929 | threads = threads > 0 ? threads : 1; | |
1b458422 | 930 | cores = cpus / (sockets * dies * threads); |
6f479566 LX |
931 | cores = cores > 0 ? cores : 1; |
932 | } else if (threads == 0) { | |
1b458422 | 933 | threads = cpus / (cores * dies * sockets); |
6f479566 | 934 | threads = threads > 0 ? threads : 1; |
1b458422 | 935 | } else if (sockets * dies * cores * threads < cpus) { |
6f479566 | 936 | error_report("cpu topology: " |
1b458422 | 937 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " |
6f479566 | 938 | "smp_cpus (%u)", |
1b458422 | 939 | sockets, dies, cores, threads, cpus); |
6f479566 LX |
940 | exit(1); |
941 | } | |
942 | ||
943 | ms->smp.max_cpus = | |
944 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
945 | ||
946 | if (ms->smp.max_cpus < cpus) { | |
947 | error_report("maxcpus must be equal to or greater than smp"); | |
948 | exit(1); | |
949 | } | |
950 | ||
1b458422 | 951 | if (sockets * dies * cores * threads > ms->smp.max_cpus) { |
6f479566 | 952 | error_report("cpu topology: " |
1b458422 | 953 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " |
6f479566 | 954 | "maxcpus (%u)", |
1b458422 | 955 | sockets, dies, cores, threads, |
6f479566 LX |
956 | ms->smp.max_cpus); |
957 | exit(1); | |
958 | } | |
959 | ||
1b458422 | 960 | if (sockets * dies * cores * threads != ms->smp.max_cpus) { |
6f479566 | 961 | warn_report("Invalid CPU topology deprecated: " |
1b458422 | 962 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " |
6f479566 | 963 | "!= maxcpus (%u)", |
1b458422 | 964 | sockets, dies, cores, threads, |
6f479566 LX |
965 | ms->smp.max_cpus); |
966 | } | |
967 | ||
968 | ms->smp.cpus = cpus; | |
969 | ms->smp.cores = cores; | |
970 | ms->smp.threads = threads; | |
f0bb276b | 971 | x86ms->smp_dies = dies; |
6f479566 LX |
972 | } |
973 | ||
974 | if (ms->smp.cpus > 1) { | |
975 | Error *blocker = NULL; | |
976 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
977 | replay_add_blocker(blocker); | |
978 | } | |
979 | } | |
980 | ||
a0628599 | 981 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) |
c649983b | 982 | { |
703a548a SL |
983 | X86MachineState *x86ms = X86_MACHINE(ms); |
984 | int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); | |
0e3bd562 | 985 | Error *local_err = NULL; |
c649983b | 986 | |
8de433cb IM |
987 | if (id < 0) { |
988 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
989 | return; | |
990 | } | |
991 | ||
5ff020b7 EH |
992 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
993 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
994 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
995 | id, apic_id); | |
996 | return; | |
997 | } | |
998 | ||
703a548a SL |
999 | |
1000 | x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); | |
0e3bd562 AF |
1001 | if (local_err) { |
1002 | error_propagate(errp, local_err); | |
1003 | return; | |
1004 | } | |
c649983b IM |
1005 | } |
1006 | ||
e3cadac0 IM |
1007 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1008 | { | |
1009 | if (cpus_count > 0xff) { | |
1010 | /* If the number of CPUs can't be represented in 8 bits, the | |
1011 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1012 | * to make old BIOSes fail more predictably. | |
1013 | */ | |
1014 | rtc_set_memory(rtc, 0x5f, 0); | |
1015 | } else { | |
1016 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1017 | } | |
1018 | } | |
1019 | ||
3459a625 | 1020 | static |
9ebeed0c | 1021 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1022 | { |
9ebeed0c EH |
1023 | PCMachineState *pcms = container_of(notifier, |
1024 | PCMachineState, machine_done); | |
f0bb276b | 1025 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9ebeed0c | 1026 | PCIBus *bus = pcms->bus; |
2118196b | 1027 | |
ba157b69 | 1028 | /* set the number of CPUs */ |
f0bb276b | 1029 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 1030 | |
2118196b MA |
1031 | if (bus) { |
1032 | int extra_hosts = 0; | |
1033 | ||
1034 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1035 | /* look for expander root buses */ | |
1036 | if (pci_bus_is_root(bus)) { | |
1037 | extra_hosts++; | |
1038 | } | |
1039 | } | |
f0bb276b | 1040 | if (extra_hosts && x86ms->fw_cfg) { |
2118196b MA |
1041 | uint64_t *val = g_malloc(sizeof(*val)); |
1042 | *val = cpu_to_le64(extra_hosts); | |
f0bb276b | 1043 | fw_cfg_add_file(x86ms->fw_cfg, |
2118196b MA |
1044 | "etc/extra-pci-roots", val, sizeof(*val)); |
1045 | } | |
1046 | } | |
1047 | ||
bb292f5a | 1048 | acpi_setup(); |
f0bb276b PB |
1049 | if (x86ms->fw_cfg) { |
1050 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
1051 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 1052 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 1053 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 1054 | } |
60c5e104 | 1055 | |
f0bb276b | 1056 | if (x86ms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
1057 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
1058 | ||
a924b3d8 | 1059 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || |
60c5e104 IM |
1060 | iommu->intr_eim != ON_OFF_AUTO_ON) { |
1061 | error_report("current -smp configuration requires " | |
1062 | "Extended Interrupt Mode enabled. " | |
1063 | "You can add an IOMMU using: " | |
1064 | "-device intel-iommu,intremap=on,eim=on"); | |
1065 | exit(EXIT_FAILURE); | |
1066 | } | |
1067 | } | |
3459a625 MT |
1068 | } |
1069 | ||
e4e8ba04 | 1070 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1071 | { |
1f3aba37 | 1072 | int i; |
aa570207 | 1073 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1074 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 1075 | |
f0bb276b | 1076 | x86ms->apic_xrupt_override = kvm_allows_irq0_override(); |
aa570207 | 1077 | pcms->numa_nodes = ms->numa_state->num_nodes; |
dd4c2f01 EH |
1078 | pcms->node_mem = g_malloc0(pcms->numa_nodes * |
1079 | sizeof *pcms->node_mem); | |
aa570207 | 1080 | for (i = 0; i < ms->numa_state->num_nodes; i++) { |
7e721e7b | 1081 | pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; |
8c85901e WG |
1082 | } |
1083 | ||
9ebeed0c EH |
1084 | pcms->machine_done.notify = pc_machine_done; |
1085 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1086 | } |
1087 | ||
83d08f26 MT |
1088 | /* setup pci memory address space mapping into system address space */ |
1089 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1090 | MemoryRegion *pci_address_space) | |
39848901 | 1091 | { |
83d08f26 MT |
1092 | /* Set to lower priority than RAM */ |
1093 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1094 | pci_address_space, -1); | |
39848901 IM |
1095 | } |
1096 | ||
7bc35e0f | 1097 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1098 | { |
1099 | int i; | |
1100 | FWCfgState *fw_cfg; | |
703a548a | 1101 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1102 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 1103 | |
df1f79fd | 1104 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1105 | |
305ae888 | 1106 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 1107 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
1108 | rom_set_fw(fw_cfg); |
1109 | ||
703a548a SL |
1110 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1111 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
b33a5bbf CL |
1112 | for (i = 0; i < nb_option_roms; i++) { |
1113 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1114 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 1115 | !strcmp(option_rom[i].name, "pvh.bin") || |
b33a5bbf CL |
1116 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1117 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1118 | } | |
f0bb276b | 1119 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1120 | } |
1121 | ||
5934e216 EH |
1122 | void pc_memory_init(PCMachineState *pcms, |
1123 | MemoryRegion *system_memory, | |
1124 | MemoryRegion *rom_memory, | |
1125 | MemoryRegion **ram_memory) | |
80cabfad | 1126 | { |
cbc5b5f3 JJ |
1127 | int linux_boot, i; |
1128 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1129 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1130 | FWCfgState *fw_cfg; |
62b160c0 | 1131 | MachineState *machine = MACHINE(pcms); |
264b4857 | 1132 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 1133 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1134 | X86MachineState *x86ms = X86_MACHINE(pcms); |
d592d303 | 1135 | |
f0bb276b PB |
1136 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
1137 | x86ms->above_4g_mem_size); | |
9521d42b PB |
1138 | |
1139 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1140 | |
00cb2a99 | 1141 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1142 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1143 | * with older qemus that used qemu_ram_alloc(). |
1144 | */ | |
7267c094 | 1145 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1146 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1147 | machine->ram_size); | |
ae0a5466 | 1148 | *ram_memory = ram; |
7267c094 | 1149 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1150 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
f0bb276b | 1151 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 1152 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
1153 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
1154 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 1155 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1156 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
f0bb276b PB |
1157 | x86ms->below_4g_mem_size, |
1158 | x86ms->above_4g_mem_size); | |
00cb2a99 AK |
1159 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1160 | ram_above_4g); | |
f0bb276b | 1161 | e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1162 | } |
82b36dc3 | 1163 | |
bb292f5a | 1164 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1165 | (machine->ram_slots || |
9521d42b | 1166 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1167 | |
1168 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1169 | mc->name); | |
1170 | exit(EXIT_FAILURE); | |
1171 | } | |
1172 | ||
b0c14ec4 DH |
1173 | /* always allocate the device memory information */ |
1174 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1175 | ||
f2ffbe2b | 1176 | /* initialize device memory address space */ |
bb292f5a | 1177 | if (pcmc->has_reserved_memory && |
9521d42b | 1178 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 1179 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 1180 | |
a0cc8856 IM |
1181 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1182 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1183 | machine->ram_slots); | |
1184 | exit(EXIT_FAILURE); | |
1185 | } | |
1186 | ||
f2c38522 PK |
1187 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1188 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1189 | error_report("maximum memory size must by aligned to multiple of " | |
1190 | "%d bytes", TARGET_PAGE_SIZE); | |
1191 | exit(EXIT_FAILURE); | |
1192 | } | |
1193 | ||
b0c14ec4 | 1194 | machine->device_memory->base = |
f0bb276b | 1195 | ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); |
619d11e4 | 1196 | |
16a9e8a5 | 1197 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 1198 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 1199 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
1200 | } |
1201 | ||
f2ffbe2b DH |
1202 | if ((machine->device_memory->base + device_mem_size) < |
1203 | device_mem_size) { | |
619d11e4 IM |
1204 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1205 | machine->maxram_size); | |
1206 | exit(EXIT_FAILURE); | |
1207 | } | |
1208 | ||
b0c14ec4 | 1209 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 1210 | "device-memory", device_mem_size); |
b0c14ec4 DH |
1211 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
1212 | &machine->device_memory->mr); | |
619d11e4 | 1213 | } |
cbc5b5f3 JJ |
1214 | |
1215 | /* Initialize PC system firmware */ | |
5e640a9e | 1216 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 1217 | |
7267c094 | 1218 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1219 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1220 | &error_fatal); |
208fa0e4 IM |
1221 | if (pcmc->pci_enabled) { |
1222 | memory_region_set_readonly(option_rom_mr, true); | |
1223 | } | |
4463aee6 | 1224 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1225 | PC_ROM_MIN_VGA, |
1226 | option_rom_mr, | |
1227 | 1); | |
f753ff16 | 1228 | |
bd802bd9 | 1229 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 1230 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 1231 | |
8832cb80 | 1232 | rom_set_fw(fw_cfg); |
1d108d97 | 1233 | |
b0c14ec4 | 1234 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 1235 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 1236 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 1237 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1238 | |
1239 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1240 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1241 | } |
d471bf3e | 1242 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1243 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1244 | } | |
1245 | ||
f753ff16 | 1246 | if (linux_boot) { |
703a548a SL |
1247 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1248 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
f753ff16 PB |
1249 | } |
1250 | ||
1251 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1252 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1253 | } |
f0bb276b | 1254 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
1255 | |
1256 | /* Init default IOAPIC address space */ | |
f0bb276b | 1257 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
1258 | |
1259 | /* Init ACPI memory hotplug IO base address */ | |
1260 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
1261 | } |
1262 | ||
9fa99d25 MA |
1263 | /* |
1264 | * The 64bit pci hole starts after "above 4G RAM" and | |
1265 | * potentially the space reserved for memory hotplug. | |
1266 | */ | |
1267 | uint64_t pc_pci_hole64_start(void) | |
1268 | { | |
1269 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1270 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1271 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1272 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9fa99d25 MA |
1273 | uint64_t hole64_start = 0; |
1274 | ||
b0c14ec4 DH |
1275 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
1276 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 1277 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 1278 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 MA |
1279 | } |
1280 | } else { | |
f0bb276b | 1281 | hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; |
9fa99d25 MA |
1282 | } |
1283 | ||
d471bf3e | 1284 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1285 | } |
1286 | ||
0b0cc076 | 1287 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1288 | { |
0b0cc076 | 1289 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1290 | } |
1291 | ||
48a18b3c | 1292 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1293 | { |
ad6d45fa AL |
1294 | DeviceState *dev = NULL; |
1295 | ||
bab47d9a | 1296 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1297 | if (pci_bus) { |
1298 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1299 | dev = pcidev ? &pcidev->qdev : NULL; | |
1300 | } else if (isa_bus) { | |
1301 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1302 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1303 | } |
bab47d9a | 1304 | rom_reset_order_override(); |
ad6d45fa | 1305 | return dev; |
765d7908 IY |
1306 | } |
1307 | ||
258711c6 JG |
1308 | static const MemoryRegionOps ioport80_io_ops = { |
1309 | .write = ioport80_write, | |
c02e1eac | 1310 | .read = ioport80_read, |
258711c6 JG |
1311 | .endianness = DEVICE_NATIVE_ENDIAN, |
1312 | .impl = { | |
1313 | .min_access_size = 1, | |
1314 | .max_access_size = 1, | |
1315 | }, | |
1316 | }; | |
1317 | ||
1318 | static const MemoryRegionOps ioportF0_io_ops = { | |
1319 | .write = ioportF0_write, | |
c02e1eac | 1320 | .read = ioportF0_read, |
258711c6 JG |
1321 | .endianness = DEVICE_NATIVE_ENDIAN, |
1322 | .impl = { | |
1323 | .min_access_size = 1, | |
1324 | .max_access_size = 1, | |
1325 | }, | |
1326 | }; | |
1327 | ||
ac64273c PMD |
1328 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1329 | { | |
1330 | int i; | |
1331 | DriveInfo *fd[MAX_FD]; | |
1332 | qemu_irq *a20_line; | |
1333 | ISADevice *i8042, *port92, *vmmouse; | |
1334 | ||
def337ff | 1335 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1336 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1337 | ||
1338 | for (i = 0; i < MAX_FD; i++) { | |
1339 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1340 | create_fdctrl |= !!fd[i]; | |
1341 | } | |
1342 | if (create_fdctrl) { | |
1343 | fdctrl_init_isa(isa_bus, fd); | |
1344 | } | |
1345 | ||
1346 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1347 | if (!no_vmport) { | |
1348 | vmport_init(isa_bus); | |
1349 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1350 | } else { | |
1351 | vmmouse = NULL; | |
1352 | } | |
1353 | if (vmmouse) { | |
1354 | DeviceState *dev = DEVICE(vmmouse); | |
1355 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1356 | qdev_init_nofail(dev); | |
1357 | } | |
1358 | port92 = isa_create_simple(isa_bus, "port92"); | |
1359 | ||
1360 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1361 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1362 | port92_init(port92, a20_line[1]); | |
1363 | g_free(a20_line); | |
1364 | } | |
1365 | ||
48a18b3c | 1366 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1367 | ISADevice **rtc_state, |
fd53c87c | 1368 | bool create_fdctrl, |
7a10ef51 | 1369 | bool no_vmport, |
feddd2fd | 1370 | bool has_pit, |
3a87d009 | 1371 | uint32_t hpet_irqs) |
ffe513da IY |
1372 | { |
1373 | int i; | |
ce967e2f JK |
1374 | DeviceState *hpet = NULL; |
1375 | int pit_isa_irq = 0; | |
1376 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1377 | qemu_irq rtc_irq = NULL; |
ac64273c | 1378 | ISADevice *pit = NULL; |
258711c6 JG |
1379 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1380 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1381 | |
2c9b15ca | 1382 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1383 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1384 | |
2c9b15ca | 1385 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1386 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1387 | |
5d17c0d2 JK |
1388 | /* |
1389 | * Check if an HPET shall be created. | |
1390 | * | |
1391 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1392 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1393 | */ | |
1394 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1395 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1396 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1397 | if (hpet) { |
7a10ef51 LPF |
1398 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1399 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1400 | * IRQ8 and IRQ2. | |
1401 | */ | |
5d7fb0f2 | 1402 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1403 | HPET_INTCAP, NULL); |
1404 | if (!compat) { | |
1405 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1406 | } | |
1407 | qdev_init_nofail(hpet); | |
1408 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1409 | ||
b881fbe9 | 1410 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1411 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1412 | } |
ce967e2f JK |
1413 | pit_isa_irq = -1; |
1414 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1415 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1416 | } |
ffe513da | 1417 | } |
6c646a11 | 1418 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1419 | |
1420 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1421 | ||
feddd2fd | 1422 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1423 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1424 | pit = kvm_pit_init(isa_bus, 0x40); |
1425 | } else { | |
acf695ec | 1426 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1427 | } |
1428 | if (hpet) { | |
1429 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1430 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1431 | } |
1432 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1433 | } |
ffe513da | 1434 | |
55f613ac | 1435 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1436 | |
ac64273c PMD |
1437 | /* Super I/O */ |
1438 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
ffe513da IY |
1439 | } |
1440 | ||
4b9c264b | 1441 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1442 | { |
1443 | int i; | |
1444 | ||
bab47d9a | 1445 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1446 | for (i = 0; i < nb_nics; i++) { |
1447 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1448 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1449 | |
4b9c264b | 1450 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1451 | pc_init_ne2k_isa(isa_bus, nd); |
1452 | } else { | |
4b9c264b | 1453 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1454 | } |
1455 | } | |
bab47d9a | 1456 | rom_reset_order_override(); |
9011a1a7 IY |
1457 | } |
1458 | ||
4501d317 PMD |
1459 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1460 | { | |
1461 | qemu_irq *i8259; | |
1462 | ||
1463 | if (kvm_pic_in_kernel()) { | |
1464 | i8259 = kvm_i8259_init(isa_bus); | |
1465 | } else if (xen_enabled()) { | |
1466 | i8259 = xen_interrupt_controller_init(); | |
1467 | } else { | |
1468 | i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); | |
1469 | } | |
1470 | ||
1471 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1472 | i8259_irqs[i] = i8259[i]; | |
1473 | } | |
1474 | ||
1475 | g_free(i8259); | |
1476 | } | |
1477 | ||
a39e3564 JB |
1478 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) |
1479 | { | |
1480 | DeviceState *dev; | |
1481 | SysBusDevice *d; | |
1482 | unsigned int i; | |
1483 | ||
15eafc2e | 1484 | if (kvm_ioapic_in_kernel()) { |
34bec7a8 | 1485 | dev = qdev_create(NULL, TYPE_KVM_IOAPIC); |
a39e3564 | 1486 | } else { |
34bec7a8 | 1487 | dev = qdev_create(NULL, TYPE_IOAPIC); |
a39e3564 JB |
1488 | } |
1489 | if (parent_name) { | |
1490 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1491 | "ioapic", OBJECT(dev), NULL); | |
1492 | } | |
1493 | qdev_init_nofail(dev); | |
1356b98d | 1494 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1495 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1496 | |
1497 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1498 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1499 | } | |
1500 | } | |
d5747cac | 1501 | |
d468115b DH |
1502 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1503 | Error **errp) | |
1504 | { | |
1505 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
b0e62443 | 1506 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1507 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1508 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1509 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1510 | Error *local_err = NULL; |
d468115b DH |
1511 | |
1512 | /* | |
1513 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1514 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1515 | * addition to cover this case. | |
1516 | */ | |
1517 | if (!pcms->acpi_dev || !acpi_enabled) { | |
1518 | error_setg(errp, | |
1519 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1520 | return; | |
1521 | } | |
1522 | ||
f6a0d06b | 1523 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1524 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1525 | return; | |
1526 | } | |
8f1ffe5b | 1527 | |
ae909496 TH |
1528 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); |
1529 | if (local_err) { | |
1530 | error_propagate(errp, local_err); | |
1531 | return; | |
1532 | } | |
1533 | ||
fd3416f5 | 1534 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1535 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1536 | } |
1537 | ||
bb6e2f7a DH |
1538 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1539 | DeviceState *dev, Error **errp) | |
95bee274 IM |
1540 | { |
1541 | Error *local_err = NULL; | |
1542 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f6a0d06b | 1543 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1544 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1545 | |
fd3416f5 | 1546 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); |
43bbb49e | 1547 | if (local_err) { |
b8865591 IM |
1548 | goto out; |
1549 | } | |
1550 | ||
7f3cf2d6 | 1551 | if (is_nvdimm) { |
f6a0d06b | 1552 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1553 | } |
1554 | ||
473ac567 | 1555 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1556 | out: |
1557 | error_propagate(errp, local_err); | |
1558 | } | |
1559 | ||
bb6e2f7a DH |
1560 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1561 | DeviceState *dev, Error **errp) | |
64fec58e | 1562 | { |
64fec58e TC |
1563 | Error *local_err = NULL; |
1564 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1565 | ||
8cd91ace HZ |
1566 | /* |
1567 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1568 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1569 | * addition to cover this case. | |
1570 | */ | |
1571 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1572 | error_setg(&local_err, |
8cd91ace | 1573 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1574 | goto out; |
1575 | } | |
1576 | ||
b097cc52 XG |
1577 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1578 | error_setg(&local_err, | |
1579 | "nvdimm device hot unplug is not supported yet."); | |
1580 | goto out; | |
1581 | } | |
1582 | ||
473ac567 DH |
1583 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1584 | &local_err); | |
64fec58e TC |
1585 | out: |
1586 | error_propagate(errp, local_err); | |
1587 | } | |
1588 | ||
bb6e2f7a DH |
1589 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1590 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1591 | { |
1592 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f7d3e29d TC |
1593 | Error *local_err = NULL; |
1594 | ||
473ac567 | 1595 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
f7d3e29d TC |
1596 | if (local_err) { |
1597 | goto out; | |
1598 | } | |
1599 | ||
fd3416f5 | 1600 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
07578b0a | 1601 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
f7d3e29d TC |
1602 | out: |
1603 | error_propagate(errp, local_err); | |
1604 | } | |
1605 | ||
3811ef14 IM |
1606 | static int pc_apic_cmp(const void *a, const void *b) |
1607 | { | |
1608 | CPUArchId *apic_a = (CPUArchId *)a; | |
1609 | CPUArchId *apic_b = (CPUArchId *)b; | |
1610 | ||
1611 | return apic_a->arch_id - apic_b->arch_id; | |
1612 | } | |
1613 | ||
7baef5cf | 1614 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1615 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1616 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1617 | */ |
1ea69c0e | 1618 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1619 | { |
7baef5cf IM |
1620 | CPUArchId apic_id, *found_cpu; |
1621 | ||
1ea69c0e | 1622 | apic_id.arch_id = id; |
38690a1c IM |
1623 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1624 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1625 | pc_apic_cmp); |
1626 | if (found_cpu && idx) { | |
38690a1c | 1627 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1628 | } |
1629 | return found_cpu; | |
1630 | } | |
1631 | ||
5279569e GZ |
1632 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1633 | DeviceState *dev, Error **errp) | |
1634 | { | |
7baef5cf | 1635 | CPUArchId *found_cpu; |
5279569e | 1636 | Error *local_err = NULL; |
1ea69c0e | 1637 | X86CPU *cpu = X86_CPU(dev); |
5279569e | 1638 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1639 | X86MachineState *x86ms = X86_MACHINE(pcms); |
5279569e | 1640 | |
a44a49db | 1641 | if (pcms->acpi_dev) { |
473ac567 | 1642 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
a44a49db IM |
1643 | if (local_err) { |
1644 | goto out; | |
1645 | } | |
5279569e GZ |
1646 | } |
1647 | ||
e3cadac0 | 1648 | /* increment the number of CPUs */ |
f0bb276b PB |
1649 | x86ms->boot_cpus++; |
1650 | if (x86ms->rtc) { | |
1651 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); | |
26ef65be | 1652 | } |
f0bb276b PB |
1653 | if (x86ms->fw_cfg) { |
1654 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
2d996150 GZ |
1655 | } |
1656 | ||
1ea69c0e | 1657 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1658 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1659 | out: |
1660 | error_propagate(errp, local_err); | |
1661 | } | |
8872c25a IM |
1662 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1663 | DeviceState *dev, Error **errp) | |
1664 | { | |
73360e27 | 1665 | int idx = -1; |
8872c25a | 1666 | Error *local_err = NULL; |
1ea69c0e | 1667 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1668 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1669 | ||
75ba2ddb IM |
1670 | if (!pcms->acpi_dev) { |
1671 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
1672 | goto out; | |
1673 | } | |
1674 | ||
1ea69c0e | 1675 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1676 | assert(idx != -1); |
1677 | if (idx == 0) { | |
1678 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1679 | goto out; | |
1680 | } | |
1681 | ||
473ac567 DH |
1682 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1683 | &local_err); | |
8872c25a IM |
1684 | if (local_err) { |
1685 | goto out; | |
1686 | } | |
1687 | ||
1688 | out: | |
1689 | error_propagate(errp, local_err); | |
1690 | ||
1691 | } | |
1692 | ||
1693 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1694 | DeviceState *dev, Error **errp) | |
1695 | { | |
8fe6374e | 1696 | CPUArchId *found_cpu; |
8872c25a | 1697 | Error *local_err = NULL; |
1ea69c0e | 1698 | X86CPU *cpu = X86_CPU(dev); |
8872c25a | 1699 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1700 | X86MachineState *x86ms = X86_MACHINE(pcms); |
8872c25a | 1701 | |
473ac567 | 1702 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
8872c25a IM |
1703 | if (local_err) { |
1704 | goto out; | |
1705 | } | |
1706 | ||
1ea69c0e | 1707 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e | 1708 | found_cpu->cpu = NULL; |
07578b0a | 1709 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
8872c25a | 1710 | |
e3cadac0 | 1711 | /* decrement the number of CPUs */ |
f0bb276b | 1712 | x86ms->boot_cpus--; |
e3cadac0 | 1713 | /* Update the number of CPUs in CMOS */ |
f0bb276b PB |
1714 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
1715 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
8872c25a IM |
1716 | out: |
1717 | error_propagate(errp, local_err); | |
1718 | } | |
5279569e | 1719 | |
4ec60c76 IM |
1720 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1721 | DeviceState *dev, Error **errp) | |
1722 | { | |
1723 | int idx; | |
a15d2728 | 1724 | CPUState *cs; |
e8f7b83e | 1725 | CPUArchId *cpu_slot; |
d89c2b8b | 1726 | X86CPUTopoInfo topo; |
4ec60c76 | 1727 | X86CPU *cpu = X86_CPU(dev); |
cabea7dc | 1728 | CPUX86State *env = &cpu->env; |
6970c5ff | 1729 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 1730 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1731 | X86MachineState *x86ms = X86_MACHINE(pcms); |
0e11fc69 LX |
1732 | unsigned int smp_cores = ms->smp.cores; |
1733 | unsigned int smp_threads = ms->smp.threads; | |
4ec60c76 | 1734 | |
6970c5ff IM |
1735 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
1736 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
1737 | ms->cpu_type); | |
1738 | return; | |
1739 | } | |
1740 | ||
f0bb276b | 1741 | env->nr_dies = x86ms->smp_dies; |
cabea7dc | 1742 | |
c26ae610 LX |
1743 | /* |
1744 | * If APIC ID is not set, | |
1745 | * set it based on socket/die/core/thread properties. | |
1746 | */ | |
e8f7b83e | 1747 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { |
c26ae610 | 1748 | int max_socket = (ms->smp.max_cpus - 1) / |
f0bb276b | 1749 | smp_threads / smp_cores / x86ms->smp_dies; |
e8f7b83e | 1750 | |
fea374e7 EH |
1751 | /* |
1752 | * die-id was optional in QEMU 4.0 and older, so keep it optional | |
1753 | * if there's only one die per socket. | |
1754 | */ | |
f0bb276b | 1755 | if (cpu->die_id < 0 && x86ms->smp_dies == 1) { |
fea374e7 EH |
1756 | cpu->die_id = 0; |
1757 | } | |
1758 | ||
e8f7b83e IM |
1759 | if (cpu->socket_id < 0) { |
1760 | error_setg(errp, "CPU socket-id is not set"); | |
1761 | return; | |
1762 | } else if (cpu->socket_id > max_socket) { | |
1763 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1764 | cpu->socket_id, max_socket); | |
1765 | return; | |
23d9cff4 EH |
1766 | } |
1767 | if (cpu->die_id < 0) { | |
1768 | error_setg(errp, "CPU die-id is not set"); | |
1769 | return; | |
f0bb276b | 1770 | } else if (cpu->die_id > x86ms->smp_dies - 1) { |
176d2cda | 1771 | error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", |
f0bb276b | 1772 | cpu->die_id, x86ms->smp_dies - 1); |
176d2cda | 1773 | return; |
e8f7b83e IM |
1774 | } |
1775 | if (cpu->core_id < 0) { | |
1776 | error_setg(errp, "CPU core-id is not set"); | |
1777 | return; | |
1778 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1779 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1780 | cpu->core_id, smp_cores - 1); | |
1781 | return; | |
1782 | } | |
1783 | if (cpu->thread_id < 0) { | |
1784 | error_setg(errp, "CPU thread-id is not set"); | |
1785 | return; | |
1786 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1787 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1788 | cpu->thread_id, smp_threads - 1); | |
1789 | return; | |
1790 | } | |
1791 | ||
1792 | topo.pkg_id = cpu->socket_id; | |
176d2cda | 1793 | topo.die_id = cpu->die_id; |
e8f7b83e IM |
1794 | topo.core_id = cpu->core_id; |
1795 | topo.smt_id = cpu->thread_id; | |
f0bb276b | 1796 | cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, |
d65af288 | 1797 | smp_threads, &topo); |
e8f7b83e IM |
1798 | } |
1799 | ||
1ea69c0e | 1800 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1801 | if (!cpu_slot) { |
38690a1c IM |
1802 | MachineState *ms = MACHINE(pcms); |
1803 | ||
f0bb276b | 1804 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 LX |
1805 | smp_cores, smp_threads, &topo); |
1806 | error_setg(errp, | |
1807 | "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" | |
1808 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1809 | topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, | |
1810 | cpu->apic_id, ms->possible_cpus->len - 1); | |
4ec60c76 IM |
1811 | return; |
1812 | } | |
1813 | ||
1814 | if (cpu_slot->cpu) { | |
1815 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1816 | idx, cpu->apic_id); | |
1817 | return; | |
1818 | } | |
d89c2b8b IM |
1819 | |
1820 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1821 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1822 | */ |
1823 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1824 | * once -smp refactoring is complete and there will be CPU private | |
1825 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
f0bb276b | 1826 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 | 1827 | smp_cores, smp_threads, &topo); |
d89c2b8b IM |
1828 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { |
1829 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1830 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1831 | return; | |
1832 | } | |
1833 | cpu->socket_id = topo.pkg_id; | |
1834 | ||
176d2cda LX |
1835 | if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { |
1836 | error_setg(errp, "property die-id: %u doesn't match set apic-id:" | |
1837 | " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); | |
1838 | return; | |
1839 | } | |
1840 | cpu->die_id = topo.die_id; | |
1841 | ||
d89c2b8b IM |
1842 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { |
1843 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1844 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1845 | return; | |
1846 | } | |
1847 | cpu->core_id = topo.core_id; | |
1848 | ||
1849 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1850 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1851 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1852 | return; | |
1853 | } | |
1854 | cpu->thread_id = topo.smt_id; | |
a15d2728 | 1855 | |
2d384d7c VK |
1856 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && |
1857 | !kvm_hv_vpindex_settable()) { | |
e9688fab RK |
1858 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); |
1859 | return; | |
1860 | } | |
1861 | ||
a15d2728 IM |
1862 | cs = CPU(cpu); |
1863 | cs->cpu_index = idx; | |
93b2a8cb | 1864 | |
a0ceb640 | 1865 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
1866 | } |
1867 | ||
a0a49813 DH |
1868 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, |
1869 | DeviceState *dev, Error **errp) | |
1870 | { | |
1871 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1872 | Error *local_err = NULL; | |
1873 | ||
1874 | if (!hotplug_dev2) { | |
1875 | /* | |
1876 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
1877 | * order. This should never be the case on x86, however better add | |
1878 | * a safety net. | |
1879 | */ | |
1880 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
1881 | return; | |
1882 | } | |
1883 | /* | |
1884 | * First, see if we can plug this memory device at all. If that | |
1885 | * succeeds, branch of to the actual hotplug handler. | |
1886 | */ | |
1887 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1888 | &local_err); | |
1889 | if (!local_err) { | |
1890 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
1891 | } | |
1892 | error_propagate(errp, local_err); | |
1893 | } | |
1894 | ||
1895 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
1896 | DeviceState *dev, Error **errp) | |
1897 | { | |
1898 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1899 | Error *local_err = NULL; | |
1900 | ||
1901 | /* | |
1902 | * Plug the memory device first and then branch off to the actual | |
1903 | * hotplug handler. If that one fails, we can easily undo the memory | |
1904 | * device bits. | |
1905 | */ | |
1906 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1907 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
1908 | if (local_err) { | |
1909 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1910 | } | |
1911 | error_propagate(errp, local_err); | |
1912 | } | |
1913 | ||
1914 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
1915 | DeviceState *dev, Error **errp) | |
1916 | { | |
1917 | /* We don't support virtio pmem hot unplug */ | |
1918 | error_setg(errp, "virtio pmem device unplug not supported."); | |
1919 | } | |
1920 | ||
1921 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
1922 | DeviceState *dev, Error **errp) | |
1923 | { | |
1924 | /* We don't support virtio pmem hot unplug */ | |
1925 | } | |
1926 | ||
4ec60c76 IM |
1927 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1928 | DeviceState *dev, Error **errp) | |
1929 | { | |
d468115b DH |
1930 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1931 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1932 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
4ec60c76 | 1933 | pc_cpu_pre_plug(hotplug_dev, dev, errp); |
a0a49813 DH |
1934 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1935 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1936 | } |
1937 | } | |
1938 | ||
95bee274 IM |
1939 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1940 | DeviceState *dev, Error **errp) | |
1941 | { | |
1942 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1943 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e GZ |
1944 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1945 | pc_cpu_plug(hotplug_dev, dev, errp); | |
a0a49813 DH |
1946 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1947 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1948 | } |
1949 | } | |
1950 | ||
d9c5c5b8 TC |
1951 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1952 | DeviceState *dev, Error **errp) | |
1953 | { | |
64fec58e | 1954 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1955 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a IM |
1956 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1957 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1958 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1959 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
64fec58e TC |
1960 | } else { |
1961 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1962 | " type: %s", object_get_typename(OBJECT(dev))); | |
1963 | } | |
d9c5c5b8 TC |
1964 | } |
1965 | ||
232391c1 TC |
1966 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1967 | DeviceState *dev, Error **errp) | |
1968 | { | |
f7d3e29d | 1969 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1970 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a IM |
1971 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1972 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1973 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1974 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
f7d3e29d TC |
1975 | } else { |
1976 | error_setg(errp, "acpi: device unplug for not supported device" | |
1977 | " type: %s", object_get_typename(OBJECT(dev))); | |
1978 | } | |
232391c1 TC |
1979 | } |
1980 | ||
285816d7 | 1981 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
1982 | DeviceState *dev) |
1983 | { | |
5279569e | 1984 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 DH |
1985 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
1986 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
95bee274 IM |
1987 | return HOTPLUG_HANDLER(machine); |
1988 | } | |
1989 | ||
38aefb57 | 1990 | return NULL; |
95bee274 IM |
1991 | } |
1992 | ||
bf1e8939 | 1993 | static void |
f2ffbe2b DH |
1994 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
1995 | const char *name, void *opaque, | |
1996 | Error **errp) | |
bf1e8939 | 1997 | { |
b0c14ec4 | 1998 | MachineState *ms = MACHINE(obj); |
fc3b77e2 IM |
1999 | int64_t value = 0; |
2000 | ||
2001 | if (ms->device_memory) { | |
2002 | value = memory_region_size(&ms->device_memory->mr); | |
2003 | } | |
bf1e8939 | 2004 | |
51e72bc1 | 2005 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2006 | } |
2007 | ||
d7bce999 EB |
2008 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2009 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2010 | { |
2011 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2012 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2013 | |
51e72bc1 | 2014 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2015 | } |
2016 | ||
d7bce999 EB |
2017 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2018 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2019 | { |
2020 | PCMachineState *pcms = PC_MACHINE(obj); | |
2021 | ||
51e72bc1 | 2022 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2023 | } |
2024 | ||
be232eb0 CP |
2025 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2026 | { | |
2027 | PCMachineState *pcms = PC_MACHINE(obj); | |
2028 | ||
f5878b03 | 2029 | return pcms->smbus_enabled; |
be232eb0 CP |
2030 | } |
2031 | ||
2032 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2033 | { | |
2034 | PCMachineState *pcms = PC_MACHINE(obj); | |
2035 | ||
f5878b03 | 2036 | pcms->smbus_enabled = value; |
be232eb0 CP |
2037 | } |
2038 | ||
272f0428 CP |
2039 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2040 | { | |
2041 | PCMachineState *pcms = PC_MACHINE(obj); | |
2042 | ||
f5878b03 | 2043 | return pcms->sata_enabled; |
272f0428 CP |
2044 | } |
2045 | ||
2046 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2047 | { | |
2048 | PCMachineState *pcms = PC_MACHINE(obj); | |
2049 | ||
f5878b03 | 2050 | pcms->sata_enabled = value; |
272f0428 CP |
2051 | } |
2052 | ||
feddd2fd CP |
2053 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2054 | { | |
2055 | PCMachineState *pcms = PC_MACHINE(obj); | |
2056 | ||
f5878b03 | 2057 | return pcms->pit_enabled; |
feddd2fd CP |
2058 | } |
2059 | ||
2060 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2061 | { | |
2062 | PCMachineState *pcms = PC_MACHINE(obj); | |
2063 | ||
f5878b03 | 2064 | pcms->pit_enabled = value; |
feddd2fd CP |
2065 | } |
2066 | ||
bf1e8939 IM |
2067 | static void pc_machine_initfn(Object *obj) |
2068 | { | |
c87b1520 DS |
2069 | PCMachineState *pcms = PC_MACHINE(obj); |
2070 | ||
97fd1ea8 | 2071 | #ifdef CONFIG_VMPORT |
d1048bef | 2072 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
2073 | #else |
2074 | pcms->vmport = ON_OFF_AUTO_OFF; | |
2075 | #endif /* CONFIG_VMPORT */ | |
021746c1 WL |
2076 | /* acpi build is enabled by default if machine supports it */ |
2077 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
2078 | pcms->smbus_enabled = true; |
2079 | pcms->sata_enabled = true; | |
2080 | pcms->pit_enabled = true; | |
ebc29e1b MA |
2081 | |
2082 | pc_system_flash_create(pcms); | |
bf1e8939 IM |
2083 | } |
2084 | ||
a0628599 | 2085 | static void pc_machine_reset(MachineState *machine) |
ae50c55a ZG |
2086 | { |
2087 | CPUState *cs; | |
2088 | X86CPU *cpu; | |
2089 | ||
2090 | qemu_devices_reset(); | |
2091 | ||
2092 | /* Reset APIC after devices have been reset to cancel | |
2093 | * any changes that qemu_devices_reset() might have done. | |
2094 | */ | |
2095 | CPU_FOREACH(cs) { | |
2096 | cpu = X86_CPU(cs); | |
2097 | ||
2098 | if (cpu->apic_state) { | |
2099 | device_reset(cpu->apic_state); | |
2100 | } | |
2101 | } | |
2102 | } | |
2103 | ||
c508bd12 NP |
2104 | static void pc_machine_wakeup(MachineState *machine) |
2105 | { | |
2106 | cpu_synchronize_all_states(); | |
2107 | pc_machine_reset(machine); | |
2108 | cpu_synchronize_all_post_reset(); | |
2109 | } | |
2110 | ||
c6cbc29d PX |
2111 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
2112 | { | |
2113 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
2114 | IntelIOMMUState *intel_iommu; | |
2115 | ||
2116 | if (iommu && | |
2117 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
2118 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
2119 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
2120 | if (!intel_iommu->caching_mode) { | |
2121 | error_setg(errp, "Device assignment is not allowed without " | |
2122 | "enabling caching-mode=on for Intel IOMMU."); | |
2123 | return false; | |
2124 | } | |
2125 | } | |
2126 | ||
2127 | return true; | |
2128 | } | |
2129 | ||
95bee274 IM |
2130 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2131 | { | |
2132 | MachineClass *mc = MACHINE_CLASS(oc); | |
2133 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2134 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2135 | ||
7102fa70 EH |
2136 | pcmc->pci_enabled = true; |
2137 | pcmc->has_acpi_build = true; | |
2138 | pcmc->rsdp_in_ram = true; | |
2139 | pcmc->smbios_defaults = true; | |
2140 | pcmc->smbios_uuid_encoded = true; | |
2141 | pcmc->gigabyte_align = true; | |
2142 | pcmc->has_reserved_memory = true; | |
2143 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2144 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2145 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2146 | * to be used at the moment, 32K should be enough for a while. */ | |
2147 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
98e753a6 | 2148 | pcmc->linuxboot_dma_enabled = true; |
fda672b5 | 2149 | pcmc->pvh_enabled = true; |
debbdc00 | 2150 | assert(!mc->get_hotplug_handler); |
285816d7 | 2151 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 2152 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
2153 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
2154 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
2155 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 2156 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 2157 | mc->has_hotpluggable_cpus = true; |
41742767 | 2158 | mc->default_boot_order = "cad"; |
4458fb3a | 2159 | mc->hot_add_cpu = pc_hot_add_cpu; |
6f479566 | 2160 | mc->smp_parse = pc_smp_parse; |
2059839b | 2161 | mc->block_default_type = IF_IDE; |
4458fb3a | 2162 | mc->max_cpus = 255; |
ae50c55a | 2163 | mc->reset = pc_machine_reset; |
c508bd12 | 2164 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 2165 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2166 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2167 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2168 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 2169 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 2170 | mc->nvdimm_supported = true; |
cd5ff833 | 2171 | mc->numa_mem_supported = true; |
0efc257d | 2172 | |
f2ffbe2b DH |
2173 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
2174 | pc_machine_get_device_memory_region_size, NULL, | |
0efc257d EH |
2175 | NULL, NULL, &error_abort); |
2176 | ||
0efc257d EH |
2177 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", |
2178 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2179 | NULL, NULL, &error_abort); | |
2180 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2181 | "Enable vmport (pc & q35)", &error_abort); | |
2182 | ||
be232eb0 CP |
2183 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
2184 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2185 | |
2186 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2187 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2188 | |
2189 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2190 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2191 | } |
2192 | ||
d5747cac IM |
2193 | static const TypeInfo pc_machine_info = { |
2194 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 2195 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
2196 | .abstract = true, |
2197 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2198 | .instance_init = pc_machine_initfn, |
d5747cac | 2199 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2200 | .class_init = pc_machine_class_init, |
2201 | .interfaces = (InterfaceInfo[]) { | |
2202 | { TYPE_HOTPLUG_HANDLER }, | |
2203 | { } | |
2204 | }, | |
d5747cac IM |
2205 | }; |
2206 | ||
2207 | static void pc_machine_register_types(void) | |
2208 | { | |
2209 | type_register_static(&pc_machine_info); | |
2210 | } | |
2211 | ||
2212 | type_init(pc_machine_register_types) |