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pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
[mirror_qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
549e984e 27#include "hw/i386/x86.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293 32#include "hw/i386/topology.h"
87abaa5d 33#include "hw/i386/fw_cfg.h"
d8f23d61 34#include "hw/i386/vmport.h"
54a40293 35#include "sysemu/cpus.h"
0d09e41a 36#include "hw/block/fdc.h"
83c9f4ca
PB		 37#include "hw/ide.h"
38#include "hw/pci/pci.h"
2118196b 39#include "hw/pci/pci_bus.h"
7bd1900b 40#include "hw/pci-bridge/pci_expander_bridge.h"
0d09e41a
PB		 41#include "hw/nvram/fw_cfg.h"
42#include "hw/timer/hpet.h"
a2eb5c0c 43#include "hw/firmware/smbios.h"
83c9f4ca 44#include "hw/loader.h"
ca20cf32 45#include "elf.h"
d6454270 46#include "migration/vmstate.h"
47b43a1f 47#include "multiboot.h"
bcdb9064 48#include "hw/rtc/mc146818rtc.h"
852c27e2 49#include "hw/intc/i8259.h"
55f613ac 50#include "hw/dma/i8257.h"
0d09e41a 51#include "hw/timer/i8254.h"
47973a2d 52#include "hw/input/i8042.h"
64552b6b 53#include "hw/irq.h"
0d09e41a 54#include "hw/audio/pcspk.h"
83c9f4ca
PB		 55#include "hw/pci/msi.h"
56#include "hw/sysbus.h"
9c17d615 57#include "sysemu/sysemu.h"
14a48c1d 58#include "sysemu/tcg.h"
e35704ba 59#include "sysemu/numa.h"
9c17d615 60#include "sysemu/kvm.h"
da278d58 61#include "sysemu/xen.h"
71e8a915 62#include "sysemu/reset.h"
54d31236 63#include "sysemu/runstate.h"
a9dc68d9 64#include "kvm/kvm_i386.h"
0d09e41a 65#include "hw/xen/xen.h"
ab969087 66#include "hw/xen/start_info.h"
a19cbfb3 67#include "ui/qemu-spice.h"
022c62cb 68#include "exec/memory.h"
1de7afc9 69#include "qemu/bitmap.h"
0c764a9d 70#include "qemu/config-file.h"
d49b6836 71#include "qemu/error-report.h"
922a01a0 72#include "qemu/option.h"
133ef074 73#include "qemu/cutils.h"
0445259b 74#include "hw/acpi/acpi.h"
5ff020b7 75#include "hw/acpi/cpu_hotplug.h"
72c194f7 76#include "acpi-build.h"
95bee274 77#include "hw/mem/pc-dimm.h"
4b997690 78#include "hw/mem/nvdimm.h"
6e4e3ae9 79#include "hw/cxl/cxl.h"
03b39fcf 80#include "hw/cxl/cxl_host.h"
e688df6b 81#include "qapi/error.h"
9af23989 82#include "qapi/qapi-visit-common.h"
0e4edb3b 83#include "qapi/qapi-visit-machine.h"
bf1e8939 84#include "qapi/visitor.h"
2e5b09fd 85#include "hw/core/cpu.h"
a310e653 86#include "hw/usb.h"
60c5e104 87#include "hw/i386/intel_iommu.h"
489983d6 88#include "hw/net/ne2000-isa.h"
06e0259a 89#include "standard-headers/asm-x86/bootparam.h"
36efa250 90#include "hw/virtio/virtio-iommu.h"
a0a49813 91#include "hw/virtio/virtio-pmem-pci.h"
0ed48fd3 92#include "hw/virtio/virtio-mem-pci.h"
a0a49813 93#include "hw/mem/memory-device.h"
6f479566
LX		 94#include "sysemu/replay.h"
95#include "qapi/qmp/qerror.h"
d6d059ca 96#include "e820_memory_layout.h"
149c50ca 97#include "fw_cfg.h"
4ca8dabd 98#include "trace.h"
2becc36a 99#include CONFIG_DEVICES
471fd342 100
0ca70366
CH		 101GlobalProperty pc_compat_7_0[] = {};
102const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
103
60f1f77c
DH		 104GlobalProperty pc_compat_6_2[] = {
105 { "virtio-mem", "unplugged-inaccessible", "off" },
106};
01854af2
CH		 107const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
108
f701ecec
VK		 109GlobalProperty pc_compat_6_1[] = {
110 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
111 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
112 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
c318bef7 113 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
f701ecec 114};
52e64f5b
YW		 115const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
116
b7c29017
DB		 117GlobalProperty pc_compat_6_0[] = {
118 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
119 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
120 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
a7a0da84 121 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
aa29466b 122 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
c318bef7 123 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
b7c29017 124};
da7e13c0
CH		 125const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
126
7ed3e1eb
IM		 127GlobalProperty pc_compat_5_2[] = {
128 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
129};
576a00bd
CH		 130const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
131
00dc02d2
IM		 132GlobalProperty pc_compat_5_1[] = {
133 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
c1bb5418 134 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
00dc02d2 135};
3ff3c5d3
CH		 136const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
137
2ebc2121
HW		 138GlobalProperty pc_compat_5_0[] = {
139};
541aaa1d
CH		 140const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
141
f404220e
IM		 142GlobalProperty pc_compat_4_2[] = {
143 { "mch", "smbase-smram", "off" },
144};
3eb74d20
CH		 145const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
146
9aec2e52
CH		 147GlobalProperty pc_compat_4_1[] = {};
148const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
149
9bf2650b
CH		 150GlobalProperty pc_compat_4_0[] = {};
151const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
152
abd93cc7 153GlobalProperty pc_compat_3_1[] = {
6c36bddf 154 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 155 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
156 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 157 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
158 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 159 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 160 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
161 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
162 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
163 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
165 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 166 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
168 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
169 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
170 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
171 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
172 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 173 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 174 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 175};
176const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
177
ddb3235d 178GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 179 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
180 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
181 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 182};
183const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
184
0d47310b 185GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 186 { TYPE_X86_CPU, "legacy-cache", "on" },
187 { TYPE_X86_CPU, "topoext", "off" },
188 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
189 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 190};
191const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
192
43df70a9 193GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 194 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
195 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 196};
197const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
198
503224f4 199GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 200 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
201 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
202 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 203};
204const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
205
3e803152 206GlobalProperty pc_compat_2_9[] = {
6c36bddf 207 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 208};
209const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
210
edc24ccd 211GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 212 { TYPE_X86_CPU, "tcg-cpuid", "off" },
213 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
214 { "ICH9-LPC", "x-smi-broadcast", "off" },
215 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
216 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 217};
218const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
219
5a995064 220GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 221 { TYPE_X86_CPU, "l3-cache", "off" },
222 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
223 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
224 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
225 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
226 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 227};
228const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
229
ff8f261f 230GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 231 { TYPE_X86_CPU, "cpuid-0xb", "off" },
232 { "vmxnet3", "romfile", "" },
233 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
234 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 235};
236const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
237
fe759610
MAL		 238GlobalProperty pc_compat_2_5[] = {};
239const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
240
2f99b9c2
MAL		 241GlobalProperty pc_compat_2_4[] = {
242 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 243 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
244 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
245 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
246 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
247 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
248 { TYPE_X86_CPU, "check", "off" },
249 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
250 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
251 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
252 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
253 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
254 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
255 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
256 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 257};
258const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
259
8995dd90
MAL		 260GlobalProperty pc_compat_2_3[] = {
261 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 262 { TYPE_X86_CPU, "arat", "off" },
263 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
264 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
265 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
266 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
267 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
268 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
269 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
270 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
276 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
277 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
278 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
279 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
280 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
281 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 282};
283const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
284
1c30044e
MAL		 285GlobalProperty pc_compat_2_2[] = {
286 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 287 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
288 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
293 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
297 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
298 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
299 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
300 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
301 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
302 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
303 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
304 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 305};
306const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
307
c4fc5695
MAL		 308GlobalProperty pc_compat_2_1[] = {
309 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 310 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
311 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 312};
313const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
314
a310e653
MAL		 315GlobalProperty pc_compat_2_0[] = {
316 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 317 { "virtio-scsi-pci", "any_layout", "off" },
318 { "PIIX4_PM", "memory-hotplug-support", "off" },
319 { "apic", "version", "0x11" },
320 { "nec-usb-xhci", "superspeed-ports-first", "off" },
321 { "nec-usb-xhci", "force-pcie-endcap", "on" },
322 { "pci-serial", "prog_if", "0" },
323 { "pci-serial-2x", "prog_if", "0" },
324 { "pci-serial-4x", "prog_if", "0" },
325 { "virtio-net-pci", "guest_announce", "off" },
326 { "ICH9-LPC", "memory-hotplug-support", "off" },
a310e653
MAL		 327};
328const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
329
330GlobalProperty pc_compat_1_7[] = {
331 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf 332 { TYPE_USB_DEVICE, "msos-desc", "no" },
aa29466b 333 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
6c36bddf 334 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 335};
336const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
337
338GlobalProperty pc_compat_1_6[] = {
339 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 340 { "e1000", "mitigation", "off" },
341 { "qemu64-" TYPE_X86_CPU, "model", "2" },
342 { "qemu32-" TYPE_X86_CPU, "model", "3" },
343 { "i440FX-pcihost", "short_root_bus", "1" },
344 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 345};
346const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
347
348GlobalProperty pc_compat_1_5[] = {
349 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 350 { "Conroe-" TYPE_X86_CPU, "model", "2" },
351 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
352 { "Penryn-" TYPE_X86_CPU, "model", "2" },
353 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
354 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
355 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
356 { "virtio-net-pci", "any_layout", "off" },
357 { TYPE_X86_CPU, "pmu", "on" },
358 { "i440FX-pcihost", "short_root_bus", "0" },
359 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 360};
361const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
362
363GlobalProperty pc_compat_1_4[] = {
364 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 365 { "scsi-hd", "discard_granularity", "0" },
366 { "scsi-cd", "discard_granularity", "0" },
6c36bddf
EH		 367 { "ide-hd", "discard_granularity", "0" },
368 { "ide-cd", "discard_granularity", "0" },
6c36bddf
EH		 369 { "virtio-blk-pci", "discard_granularity", "0" },
370 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
371 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
372 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
373 { "e1000", "romfile", "pxe-e1000.rom" },
374 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
375 { "pcnet", "romfile", "pxe-pcnet.rom" },
376 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
377 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
378 { "486-" TYPE_X86_CPU, "model", "0" },
379 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
380 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 381};
382const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
383
417258f1
PMD		 384GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
385{
386 GSIState *s;
387
388 s = g_new0(GSIState, 1);
389 if (kvm_ioapic_in_kernel()) {
390 kvm_pc_setup_irq_routing(pci_enabled);
417258f1 391 }
64c033ba 392 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
417258f1
PMD		 393
394 return s;
395}
396
258711c6
JG		 397static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
398 unsigned size)
80cabfad
FB		 399{
400}
401
c02e1eac
JG		 402static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
403{
a6fc23e5 404 return 0xffffffffffffffffULL;
c02e1eac
JG		 405}
406
f929aad6 407/* MSDOS compatibility mode FPU exception support */
258711c6
JG		 408static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
409 unsigned size)
f929aad6 410{
6f529b75 411 if (tcg_enabled()) {
bf13bfab 412 cpu_set_ignne();
6f529b75 413 }
f929aad6
FB		 414}
415
c02e1eac
JG		 416static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
417{
a6fc23e5 418 return 0xffffffffffffffffULL;
c02e1eac
JG		 419}
420
b0a21b53
FB		 421/* PC cmos mappings */
422
80cabfad
FB		 423#define REG_EQUIPMENT_BYTE 0x14
424
9139046c
MA		 425static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
426 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 427{
ba6c2377
FB		 428 rtc_set_memory(s, type_ofs, 47);
429 rtc_set_memory(s, info_ofs, cylinders);
430 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
431 rtc_set_memory(s, info_ofs + 2, heads);
432 rtc_set_memory(s, info_ofs + 3, 0xff);
433 rtc_set_memory(s, info_ofs + 4, 0xff);
434 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
435 rtc_set_memory(s, info_ofs + 6, cylinders);
436 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
437 rtc_set_memory(s, info_ofs + 8, sectors);
438}
439
6ac0e82d
AZ		 440/* convert boot_device letter to something recognizable by the bios */
441static int boot_device2nibble(char boot_device)
442{
443 switch(boot_device) {
444 case 'a':
445 case 'b':
446 return 0x01; /* floppy boot */
447 case 'c':
448 return 0x02; /* hard drive boot */
449 case 'd':
450 return 0x03; /* CD-ROM boot */
451 case 'n':
452 return 0x04; /* Network boot */
453 }
454 return 0;
455}
456
ddcd5531 457static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 458{
459#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 460 int nbds, bds[3] = { 0, };
461 int i;
462
463 nbds = strlen(boot_device);
464 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 465 error_setg(errp, "Too many boot devices for PC");
466 return;
0ecdffbb
AJ		 467 }
468 for (i = 0; i < nbds; i++) {
469 bds[i] = boot_device2nibble(boot_device[i]);
470 if (bds[i] == 0) {
ddcd5531
GA		 471 error_setg(errp, "Invalid boot device for PC: '%c'",
472 boot_device[i]);
473 return;
0ecdffbb
AJ		 474 }
475 }
476 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 477 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 478}
479
ddcd5531 480static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 481{
ddcd5531 482 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 483}
484
7444ca4e
LE		 485static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
486{
487 int val, nb, i;
2da44dd0
JS		 488 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
489 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 490
491 /* floppy type */
492 if (floppy) {
493 for (i = 0; i < 2; i++) {
494 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
495 }
496 }
497 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
498 cmos_get_fd_drive_type(fd_type[1]);
499 rtc_set_memory(rtc_state, 0x10, val);
500
501 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
502 nb = 0;
2da44dd0 503 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 504 nb++;
505 }
2da44dd0 506 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 507 nb++;
508 }
509 switch (nb) {
510 case 0:
511 break;
512 case 1:
513 val |= 0x01; /* 1 drive, ready for boot */
514 break;
515 case 2:
516 val |= 0x41; /* 2 drives, ready for boot */
517 break;
518 }
519 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
520}
521
c0897e0c
MA		 522typedef struct pc_cmos_init_late_arg {
523 ISADevice *rtc_state;
9139046c 524 BusState *idebus[2];
c0897e0c
MA		 525} pc_cmos_init_late_arg;
526
b86f4613
LE		 527typedef struct check_fdc_state {
528 ISADevice *floppy;
529 bool multiple;
530} CheckFdcState;
531
532static int check_fdc(Object *obj, void *opaque)
533{
534 CheckFdcState *state = opaque;
535 Object *fdc;
536 uint32_t iobase;
537 Error *local_err = NULL;
538
539 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
540 if (!fdc) {
541 return 0;
542 }
543
1ea1572a 544 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 545 if (local_err || iobase != 0x3f0) {
546 error_free(local_err);
547 return 0;
548 }
549
550 if (state->floppy) {
551 state->multiple = true;
552 } else {
553 state->floppy = ISA_DEVICE(obj);
554 }
555 return 0;
556}
557
558static const char * const fdc_container_path[] = {
559 "/unattached", "/peripheral", "/peripheral-anon"
560};
561
424e4a87
RK		 562/*
563 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
564 * and ACPI objects.
565 */
566ISADevice *pc_find_fdc0(void)
567{
568 int i;
569 Object *container;
570 CheckFdcState state = { 0 };
571
572 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
573 container = container_get(qdev_get_machine(), fdc_container_path[i]);
574 object_child_foreach(container, check_fdc, &state);
575 }
576
577 if (state.multiple) {
3dc6f869
AF		 578 warn_report("multiple floppy disk controllers with "
579 "iobase=0x3f0 have been found");
433672b0 580 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 581 "your intent");
424e4a87
RK		 582 }
583
584 return state.floppy;
585}
586
c0897e0c
MA		 587static void pc_cmos_init_late(void *opaque)
588{
589 pc_cmos_init_late_arg *arg = opaque;
590 ISADevice *s = arg->rtc_state;
9139046c
MA		 591 int16_t cylinders;
592 int8_t heads, sectors;
c0897e0c 593 int val;
2adc99b2 594 int i, trans;
c0897e0c 595
9139046c 596 val = 0;
272f0428
CP		 597 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
598 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 599 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
600 val |= 0xf0;
601 }
272f0428
CP		 602 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
603 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 604 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
605 val |= 0x0f;
606 }
607 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 608
609 val = 0;
610 for (i = 0; i < 4; i++) {
9139046c
MA		 611 /* NOTE: ide_get_geometry() returns the physical
612 geometry. It is always such that: 1 <= sects <= 63, 1
613 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
614 geometry can be different if a translation is done. */
272f0428
CP		 615 if (arg->idebus[i / 2] &&
616 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 617 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 618 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
619 assert((trans & ~3) == 0);
620 val |= trans << (i * 2);
c0897e0c
MA		 621 }
622 }
623 rtc_set_memory(s, 0x39, val);
624
424e4a87 625 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 626
c0897e0c
MA		 627 qemu_unregister_reset(pc_cmos_init_late, opaque);
628}
629
23d30407 630void pc_cmos_init(PCMachineState *pcms,
220a8846 631 BusState *idebus0, BusState *idebus1,
63ffb564 632 ISADevice *s)
80cabfad 633{
7444ca4e 634 int val;
c0897e0c 635 static pc_cmos_init_late_arg arg;
f0bb276b 636 X86MachineState *x86ms = X86_MACHINE(pcms);
b0a21b53 637
b0a21b53 638 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 639
640 /* memory size */
e89001f7 641 /* base memory (first MiB) */
f0bb276b 642 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
333190eb
FB		 643 rtc_set_memory(s, 0x15, val);
644 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 645 /* extended memory (next 64MiB) */
f0bb276b
PB		 646 if (x86ms->below_4g_mem_size > 1 * MiB) {
647 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 648 } else {
649 val = 0;
650 }
80cabfad
FB		 651 if (val > 65535)
652 val = 65535;
b0a21b53
FB		 653 rtc_set_memory(s, 0x17, val);
654 rtc_set_memory(s, 0x18, val >> 8);
655 rtc_set_memory(s, 0x30, val);
656 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 657 /* memory between 16MiB and 4GiB */
f0bb276b
PB		 658 if (x86ms->below_4g_mem_size > 16 * MiB) {
659 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 660 } else {
9da98861 661 val = 0;
e89001f7 662 }
80cabfad
FB		 663 if (val > 65535)
664 val = 65535;
b0a21b53
FB		 665 rtc_set_memory(s, 0x34, val);
666 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 667 /* memory above 4GiB */
f0bb276b 668 val = x86ms->above_4g_mem_size / 65536;
e89001f7
MA		 669 rtc_set_memory(s, 0x5b, val);
670 rtc_set_memory(s, 0x5c, val >> 8);
671 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 672
23d30407 673 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 674 TYPE_ISA_DEVICE,
f0bb276b 675 (Object **)&x86ms->rtc,
2d996150 676 object_property_allow_set_link,
d2623129 677 OBJ_PROP_LINK_STRONG);
5325cc34
MA		 678 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
679 &error_abort);
298e01b6 680
97ec4d21 681 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
80cabfad 682
b0a21b53 683 val = 0;
b0a21b53
FB		 684 val |= 0x02; /* FPU is there */
685 val |= 0x04; /* PS/2 mouse installed */
686 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
687
b86f4613 688 /* hard drives and FDC */
c0897e0c 689 arg.rtc_state = s;
9139046c
MA		 690 arg.idebus[0] = idebus0;
691 arg.idebus[1] = idebus1;
c0897e0c 692 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 693}
694
956a3e6b 695static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 696{
cc36a7a2 697 X86CPU *cpu = opaque;
e1a23744 698
956a3e6b 699 /* XXX: send to all CPUs ? */
4b78a802 700 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 701 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 702}
703
b41a2cd1
FB		 704#define NE2000_NB_MAX 6
705
675d6f82
BS		 706static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
707 0x280, 0x380 };
708static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 709
48a18b3c 710void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 711{
712 static int nb_ne2k = 0;
713
714 if (nb_ne2k == NE2000_NB_MAX)
715 return;
48a18b3c 716 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 717 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 718 nb_ne2k++;
719}
720
845773ab 721void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 722{
c3affe56 723 X86CPU *cpu = opaque;
53b67b30
BS		 724
725 if (level) {
c3affe56 726 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 727 }
728}
729
3459a625 730static
9ebeed0c 731void pc_machine_done(Notifier *notifier, void *data)
3459a625 732{
9ebeed0c
EH		 733 PCMachineState *pcms = container_of(notifier,
734 PCMachineState, machine_done);
f0bb276b 735 X86MachineState *x86ms = X86_MACHINE(pcms);
dab390ff
JC		 736 MachineState *ms = MACHINE(pcms);
737
738 if (ms->cxl_devices_state) {
7bd1900b
JC		 739 cxl_hook_up_pxb_registers(pcms->bus, ms->cxl_devices_state,
740 &error_fatal);
dab390ff
JC		 741 cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
742 }
2118196b 743
ba157b69 744 /* set the number of CPUs */
0cca1a91 745 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
ba157b69 746
0abd3888 747 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
2118196b 748
bb292f5a 749 acpi_setup();
f0bb276b
PB		 750 if (x86ms->fw_cfg) {
751 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
752 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
e3cadac0 753 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
f0bb276b 754 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
6d42eefa 755 }
3459a625
MT		 756}
757
e4e8ba04 758void pc_guest_info_init(PCMachineState *pcms)
3459a625 759{
f0bb276b 760 X86MachineState *x86ms = X86_MACHINE(pcms);
b20c9bd5 761
eafa0868 762 x86ms->apic_xrupt_override = true;
9ebeed0c
EH		 763 pcms->machine_done.notify = pc_machine_done;
764 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 765}
766
83d08f26
MT		 767/* setup pci memory address space mapping into system address space */
768void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
769 MemoryRegion *pci_address_space)
39848901 770{
83d08f26
MT		 771 /* Set to lower priority than RAM */
772 memory_region_add_subregion_overlap(system_memory, 0x0,
773 pci_address_space, -1);
39848901
IM		 774}
775
7bc35e0f 776void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 777{
778 int i;
779 FWCfgState *fw_cfg;
703a548a 780 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 781 X86MachineState *x86ms = X86_MACHINE(pcms);
b33a5bbf 782
df1f79fd 783 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 784
305ae888 785 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
f0bb276b 786 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
b33a5bbf
CL		 787 rom_set_fw(fw_cfg);
788
703a548a 789 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
f014c974 790 pcmc->pvh_enabled);
b33a5bbf
CL		 791 for (i = 0; i < nb_option_roms; i++) {
792 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 793 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 794 !strcmp(option_rom[i].name, "pvh.bin") ||
3ca8ce72
PB		 795 !strcmp(option_rom[i].name, "multiboot.bin") ||
796 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
b33a5bbf
CL		 797 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
798 }
f0bb276b 799 x86ms->fw_cfg = fw_cfg;
b33a5bbf
CL		 800}
801
72686c58
PMD		 802#define PC_ROM_MIN_VGA 0xc0000
803#define PC_ROM_MIN_OPTION 0xc8000
804#define PC_ROM_MAX 0xe0000
805#define PC_ROM_ALIGN 0x800
806#define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
807
5934e216
EH		 808void pc_memory_init(PCMachineState *pcms,
809 MemoryRegion *system_memory,
810 MemoryRegion *rom_memory,
811 MemoryRegion **ram_memory)
80cabfad 812{
cbc5b5f3 813 int linux_boot, i;
bd457782 814 MemoryRegion *option_rom_mr;
00cb2a99 815 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 816 FWCfgState *fw_cfg;
62b160c0 817 MachineState *machine = MACHINE(pcms);
264b4857 818 MachineClass *mc = MACHINE_GET_CLASS(machine);
16a9e8a5 819 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 820 X86MachineState *x86ms = X86_MACHINE(pcms);
6d302cf4 821 hwaddr cxl_base, cxl_resv_end = 0;
d592d303 822
f0bb276b
PB		 823 assert(machine->ram_size == x86ms->below_4g_mem_size +
824 x86ms->above_4g_mem_size);
9521d42b
PB		 825
826 linux_boot = (machine->kernel_filename != NULL);
80cabfad 827
bd457782
IM		 828 /*
829 * Split single memory region and use aliases to address portions of it,
830 * done for backwards compatibility with older qemus.
00cb2a99 831 */
bd457782 832 *ram_memory = machine->ram;
7267c094 833 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
bd457782 834 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
f0bb276b 835 0, x86ms->below_4g_mem_size);
00cb2a99 836 memory_region_add_subregion(system_memory, 0, ram_below_4g);
f0bb276b
PB		 837 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
838 if (x86ms->above_4g_mem_size > 0) {
7267c094 839 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
bd457782
IM		 840 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
841 machine->ram,
f0bb276b
PB		 842 x86ms->below_4g_mem_size,
843 x86ms->above_4g_mem_size);
00cb2a99
AK		 844 memory_region_add_subregion(system_memory, 0x100000000ULL,
845 ram_above_4g);
f0bb276b 846 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
bbe80adf 847 }
82b36dc3 848
1ed1ccc5
SC		 849 if (pcms->sgx_epc.size != 0) {
850 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
851 }
852
bb292f5a 853 if (!pcmc->has_reserved_memory &&
ca8336f3 854 (machine->ram_slots ||
9521d42b 855 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 856
857 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
858 mc->name);
859 exit(EXIT_FAILURE);
860 }
861
b0c14ec4
DH		 862 /* always allocate the device memory information */
863 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
864
f2ffbe2b 865 /* initialize device memory address space */
bb292f5a 866 if (pcmc->has_reserved_memory &&
9521d42b 867 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 868 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 869
a0cc8856
IM		 870 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
871 error_report("unsupported amount of memory slots: %"PRIu64,
872 machine->ram_slots);
873 exit(EXIT_FAILURE);
874 }
875
f2c38522
PK		 876 if (QEMU_ALIGN_UP(machine->maxram_size,
877 TARGET_PAGE_SIZE) != machine->maxram_size) {
878 error_report("maximum memory size must by aligned to multiple of "
879 "%d bytes", TARGET_PAGE_SIZE);
880 exit(EXIT_FAILURE);
881 }
882
0cf4ce00
SC		 883 if (pcms->sgx_epc.size != 0) {
884 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc);
885 } else {
886 machine->device_memory->base =
887 0x100000000ULL + x86ms->above_4g_mem_size;
888 }
889
b0c14ec4 890 machine->device_memory->base =
0cf4ce00 891 ROUND_UP(machine->device_memory->base, 1 * GiB);
619d11e4 892
16a9e8a5 893 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 894 /* size device region assuming 1G page max alignment per slot */
d471bf3e 895 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 896 }
897
f2ffbe2b
DH		 898 if ((machine->device_memory->base + device_mem_size) <
899 device_mem_size) {
619d11e4
IM		 900 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
901 machine->maxram_size);
902 exit(EXIT_FAILURE);
903 }
904
b0c14ec4 905 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 906 "device-memory", device_mem_size);
b0c14ec4
DH		 907 memory_region_add_subregion(system_memory, machine->device_memory->base,
908 &machine->device_memory->mr);
619d11e4 909 }
cbc5b5f3 910
6e4e3ae9
BW		 911 if (machine->cxl_devices_state->is_enabled) {
912 MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
913 hwaddr cxl_size = MiB;
914
915 if (pcmc->has_reserved_memory && machine->device_memory->base) {
916 cxl_base = machine->device_memory->base;
917 if (!pcmc->broken_reserved_end) {
918 cxl_base += memory_region_size(&machine->device_memory->mr);
919 }
920 } else if (pcms->sgx_epc.size != 0) {
921 cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc);
922 } else {
923 cxl_base = 0x100000000ULL + x86ms->above_4g_mem_size;
924 }
925
926 e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
927 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
928 memory_region_add_subregion(system_memory, cxl_base, mr);
6d302cf4
JC		 929 cxl_resv_end = cxl_base + cxl_size;
930 if (machine->cxl_devices_state->fixed_windows) {
931 hwaddr cxl_fmw_base;
932 GList *it;
933
934 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
935 for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) {
936 CXLFixedWindow *fw = it->data;
937
938 fw->base = cxl_fmw_base;
939 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
940 "cxl-fixed-memory-region", fw->size);
941 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
942 e820_add_entry(fw->base, fw->size, E820_RESERVED);
943 cxl_fmw_base += fw->size;
944 cxl_resv_end = cxl_fmw_base;
945 }
946 }
6e4e3ae9
BW		 947 }
948
cbc5b5f3 949 /* Initialize PC system firmware */
5e640a9e 950 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 951
7267c094 952 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 953 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 954 &error_fatal);
208fa0e4
IM		 955 if (pcmc->pci_enabled) {
956 memory_region_set_readonly(option_rom_mr, true);
957 }
4463aee6 958 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 959 PC_ROM_MIN_VGA,
960 option_rom_mr,
961 1);
f753ff16 962
bd802bd9 963 fw_cfg = fw_cfg_arch_create(machine,
f0bb276b 964 x86ms->boot_cpus, x86ms->apic_id_limit);
c886fc4c 965
8832cb80 966 rom_set_fw(fw_cfg);
1d108d97 967
b0c14ec4 968 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 969 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 970 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 971 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 972
973 if (!pcmc->broken_reserved_end) {
b0c14ec4 974 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 975 }
6d302cf4
JC		 976
977 if (machine->cxl_devices_state->is_enabled) {
978 res_mem_end = cxl_resv_end;
979 }
d471bf3e 980 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 981 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
982 }
983
f753ff16 984 if (linux_boot) {
703a548a 985 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
f014c974 986 pcmc->pvh_enabled);
f753ff16
PB		 987 }
988
989 for (i = 0; i < nb_option_roms; i++) {
2e55e842 990 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 991 }
f0bb276b 992 x86ms->fw_cfg = fw_cfg;
cb135f59
PX		 993
994 /* Init default IOAPIC address space */
f0bb276b 995 x86ms->ioapic_as = &address_space_memory;
091c466e
SK		 996
997 /* Init ACPI memory hotplug IO base address */
998 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
3d53f5c3
IY		 999}
1000
9fa99d25
MA		 1001/*
1002 * The 64bit pci hole starts after "above 4G RAM" and
1003 * potentially the space reserved for memory hotplug.
1004 */
1005uint64_t pc_pci_hole64_start(void)
1006{
1007 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1008 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1009 MachineState *ms = MACHINE(pcms);
f0bb276b 1010 X86MachineState *x86ms = X86_MACHINE(pcms);
9fa99d25
MA		 1011 uint64_t hole64_start = 0;
1012
6e4e3ae9
BW		 1013 if (ms->cxl_devices_state->host_mr.addr) {
1014 hole64_start = ms->cxl_devices_state->host_mr.addr +
1015 memory_region_size(&ms->cxl_devices_state->host_mr);
6d302cf4
JC		 1016 if (ms->cxl_devices_state->fixed_windows) {
1017 GList *it;
1018 for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
1019 CXLFixedWindow *fw = it->data;
1020 hole64_start = fw->mr.addr + memory_region_size(&fw->mr);
1021 }
1022 }
6e4e3ae9 1023 } else if (pcmc->has_reserved_memory && ms->device_memory->base) {
b0c14ec4 1024 hole64_start = ms->device_memory->base;
9fa99d25 1025 if (!pcmc->broken_reserved_end) {
b0c14ec4 1026 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25 1027 }
0cf4ce00
SC		 1028 } else if (pcms->sgx_epc.size != 0) {
1029 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc);
9fa99d25 1030 } else {
f0bb276b 1031 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
9fa99d25
MA		 1032 }
1033
d471bf3e 1034 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1035}
1036
48a18b3c 1037DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1038{
ad6d45fa
AL		 1039 DeviceState *dev = NULL;
1040
bab47d9a 1041 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1042 if (pci_bus) {
1043 PCIDevice *pcidev = pci_vga_init(pci_bus);
1044 dev = pcidev ? &pcidev->qdev : NULL;
1045 } else if (isa_bus) {
1046 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1047 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1048 }
bab47d9a 1049 rom_reset_order_override();
ad6d45fa 1050 return dev;
765d7908
IY		 1051}
1052
258711c6
JG		 1053static const MemoryRegionOps ioport80_io_ops = {
1054 .write = ioport80_write,
c02e1eac 1055 .read = ioport80_read,
258711c6
JG		 1056 .endianness = DEVICE_NATIVE_ENDIAN,
1057 .impl = {
1058 .min_access_size = 1,
1059 .max_access_size = 1,
1060 },
1061};
1062
1063static const MemoryRegionOps ioportF0_io_ops = {
1064 .write = ioportF0_write,
c02e1eac 1065 .read = ioportF0_read,
258711c6
JG		 1066 .endianness = DEVICE_NATIVE_ENDIAN,
1067 .impl = {
1068 .min_access_size = 1,
1069 .max_access_size = 1,
1070 },
1071};
1072
4ccd5fe2
JD		 1073static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1074 bool create_i8042, bool no_vmport)
ac64273c
PMD		 1075{
1076 int i;
1077 DriveInfo *fd[MAX_FD];
1078 qemu_irq *a20_line;
fed2c173 1079 ISADevice *fdc, *i8042, *port92, *vmmouse;
ac64273c 1080
def337ff 1081 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1082 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1083
1084 for (i = 0; i < MAX_FD; i++) {
1085 fd[i] = drive_get(IF_FLOPPY, 0, i);
1086 create_fdctrl |= !!fd[i];
1087 }
1088 if (create_fdctrl) {
fed2c173
MA		 1089 fdc = isa_new(TYPE_ISA_FDC);
1090 if (fdc) {
1091 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1092 isa_fdc_init_drives(fdc, fd);
1093 }
ac64273c
PMD		 1094 }
1095
4ccd5fe2
JD		 1096 if (!create_i8042) {
1097 return;
1098 }
1099
ac64273c
PMD		 1100 i8042 = isa_create_simple(isa_bus, "i8042");
1101 if (!no_vmport) {
b4fa79ea 1102 isa_create_simple(isa_bus, TYPE_VMPORT);
c23e0561 1103 vmmouse = isa_try_new("vmmouse");
ac64273c
PMD		 1104 } else {
1105 vmmouse = NULL;
1106 }
1107 if (vmmouse) {
5325cc34
MA		 1108 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1109 &error_abort);
c23e0561 1110 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
ac64273c 1111 }
9e5213c8 1112 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
ac64273c
PMD		 1113
1114 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1115 i8042_setup_a20_line(i8042, a20_line[0]);
1820b70e
PMD		 1116 qdev_connect_gpio_out_named(DEVICE(port92),
1117 PORT92_A20_LINE, 0, a20_line[1]);
ac64273c
PMD		 1118 g_free(a20_line);
1119}
1120
10e2483b
GH		 1121void pc_basic_device_init(struct PCMachineState *pcms,
1122 ISABus *isa_bus, qemu_irq *gsi,
1611977c 1123 ISADevice **rtc_state,
fd53c87c 1124 bool create_fdctrl,
3a87d009 1125 uint32_t hpet_irqs)
ffe513da
IY		 1126{
1127 int i;
ce967e2f
JK		 1128 DeviceState *hpet = NULL;
1129 int pit_isa_irq = 0;
1130 qemu_irq pit_alt_irq = NULL;
7d932dfd 1131 qemu_irq rtc_irq = NULL;
ac64273c 1132 ISADevice *pit = NULL;
258711c6
JG		 1133 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1134 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
9dee7e51 1135 X86MachineState *x86ms = X86_MACHINE(pcms);
ffe513da 1136
2c9b15ca 1137 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 1138 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 1139
2c9b15ca 1140 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 1141 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 1142
5d17c0d2
JK		 1143 /*
1144 * Check if an HPET shall be created.
1145 *
1146 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1147 * when the HPET wants to take over. Thus we have to disable the latter.
1148 */
0259c78c
EH		 1149 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1150 kvm_has_pit_state2())) {
df707969 1151 hpet = qdev_try_new(TYPE_HPET);
0259c78c
EH		 1152 if (!hpet) {
1153 error_report("couldn't create HPET device");
1154 exit(1);
1155 }
54420332
MT		 1156 /*
1157 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1158 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1159 * IRQ2.
1160 */
0259c78c
EH		 1161 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1162 HPET_INTCAP, NULL);
1163 if (!compat) {
1164 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1165 }
1166 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1167 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
7a10ef51 1168
0259c78c
EH		 1169 for (i = 0; i < GSI_NUM_PINS; i++) {
1170 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
822557eb 1171 }
0259c78c
EH		 1172 pit_isa_irq = -1;
1173 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1174 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
ffe513da 1175 }
6c646a11 1176 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 1177
1178 qemu_register_boot_set(pc_boot_set, *rtc_state);
1179
9dee7e51
XL		 1180 if (!xen_enabled() &&
1181 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
15eafc2e 1182 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 1183 pit = kvm_pit_init(isa_bus, 0x40);
1184 } else {
acf695ec 1185 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 1186 }
1187 if (hpet) {
1188 /* connect PIT to output control line of the HPET */
4a17cc4f 1189 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311 1190 }
6b8d1416 1191 pcspk_init(pcms->pcspk, isa_bus, pit);
ce967e2f 1192 }
ffe513da 1193
55f613ac 1194 i8257_dma_init(isa_bus, 0);
ffe513da 1195
ac64273c 1196 /* Super I/O */
4ccd5fe2
JD		 1197 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1198 pcms->vmport != ON_OFF_AUTO_ON);
ffe513da
IY		 1199}
1200
4b9c264b 1201void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 1202{
1203 int i;
1204
bab47d9a 1205 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 1206 for (i = 0; i < nb_nics; i++) {
1207 NICInfo *nd = &nd_table[i];
4b9c264b 1208 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 1209
4b9c264b 1210 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 1211 pc_init_ne2k_isa(isa_bus, nd);
1212 } else {
4b9c264b 1213 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 1214 }
1215 }
bab47d9a 1216 rom_reset_order_override();
9011a1a7
IY		 1217}
1218
4501d317
PMD		 1219void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1220{
1221 qemu_irq *i8259;
1222
1223 if (kvm_pic_in_kernel()) {
1224 i8259 = kvm_i8259_init(isa_bus);
1225 } else if (xen_enabled()) {
1226 i8259 = xen_interrupt_controller_init();
1227 } else {
89a289c7 1228 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
4501d317
PMD		 1229 }
1230
1231 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1232 i8259_irqs[i] = i8259[i];
1233 }
1234
1235 g_free(i8259);
1236}
1237
d468115b
DH		 1238static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1239 Error **errp)
1240{
1241 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1242 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
b0e62443 1243 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 1244 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 1245 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 1246 const uint64_t legacy_align = TARGET_PAGE_SIZE;
ae909496 1247 Error *local_err = NULL;
d468115b
DH		 1248
1249 /*
1250 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1251 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1252 * addition to cover this case.
1253 */
50aef131 1254 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
d468115b
DH		 1255 error_setg(errp,
1256 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1257 return;
1258 }
1259
f6a0d06b 1260 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 1261 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1262 return;
1263 }
8f1ffe5b 1264
50aef131 1265 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
ae909496
TH		 1266 if (local_err) {
1267 error_propagate(errp, local_err);
1268 return;
1269 }
1270
fd3416f5 1271 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 1272 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 1273}
1274
bb6e2f7a
DH		 1275static void pc_memory_plug(HotplugHandler *hotplug_dev,
1276 DeviceState *dev, Error **errp)
95bee274 1277{
95bee274 1278 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1279 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f6a0d06b 1280 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 1281 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 1282
84fd5496 1283 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
b8865591 1284
7f3cf2d6 1285 if (is_nvdimm) {
f6a0d06b 1286 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 1287 }
1288
50aef131 1289 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
95bee274
IM		 1290}
1291
bb6e2f7a
DH		 1292static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1293 DeviceState *dev, Error **errp)
64fec58e 1294{
50aef131 1295 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
64fec58e 1296
8cd91ace
HZ		 1297 /*
1298 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1299 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1300 * addition to cover this case.
1301 */
50aef131 1302 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
dcfe4805 1303 error_setg(errp,
8cd91ace 1304 "memory hotplug is not enabled: missing acpi device or acpi disabled");
dcfe4805 1305 return;
64fec58e
TC		 1306 }
1307
b097cc52 1308 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
dcfe4805
MA		 1309 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1310 return;
b097cc52
XG		 1311 }
1312
50aef131 1313 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
dcfe4805 1314 errp);
64fec58e
TC		 1315}
1316
bb6e2f7a
DH		 1317static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1318 DeviceState *dev, Error **errp)
f7d3e29d
TC		 1319{
1320 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1321 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f7d3e29d
TC		 1322 Error *local_err = NULL;
1323
50aef131 1324 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
f7d3e29d
TC		 1325 if (local_err) {
1326 goto out;
1327 }
1328
fd3416f5 1329 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
981c3dcd 1330 qdev_unrealize(dev);
f7d3e29d
TC		 1331 out:
1332 error_propagate(errp, local_err);
1333}
1334
0ed48fd3
DH		 1335static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1336 DeviceState *dev, Error **errp)
a0a49813
DH		 1337{
1338 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1339 Error *local_err = NULL;
1340
af1d039f 1341 if (!hotplug_dev2 && dev->hotplugged) {
a0a49813
DH		 1342 /*
1343 * Without a bus hotplug handler, we cannot control the plug/unplug
af1d039f
DH		 1344 * order. We should never reach this point when hotplugging on x86,
1345 * however, better add a safety net.
a0a49813 1346 */
0ed48fd3
DH		 1347 error_setg(errp, "hotplug of virtio based memory devices not supported"
1348 " on this bus.");
a0a49813
DH		 1349 return;
1350 }
1351 /*
1352 * First, see if we can plug this memory device at all. If that
1353 * succeeds, branch of to the actual hotplug handler.
1354 */
1355 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1356 &local_err);
af1d039f 1357 if (!local_err && hotplug_dev2) {
a0a49813
DH		 1358 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1359 }
1360 error_propagate(errp, local_err);
1361}
1362
0ed48fd3
DH		 1363static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1364 DeviceState *dev, Error **errp)
a0a49813
DH		 1365{
1366 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1367 Error *local_err = NULL;
1368
1369 /*
1370 * Plug the memory device first and then branch off to the actual
1371 * hotplug handler. If that one fails, we can easily undo the memory
1372 * device bits.
1373 */
1374 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
af1d039f
DH		 1375 if (hotplug_dev2) {
1376 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1377 if (local_err) {
1378 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1379 }
a0a49813
DH		 1380 }
1381 error_propagate(errp, local_err);
1382}
1383
0ed48fd3
DH		 1384static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1385 DeviceState *dev, Error **errp)
a0a49813 1386{
0ed48fd3
DH		 1387 /* We don't support hot unplug of virtio based memory devices */
1388 error_setg(errp, "virtio based memory devices cannot be unplugged.");
a0a49813
DH		 1389}
1390
0ed48fd3
DH		 1391static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1392 DeviceState *dev, Error **errp)
a0a49813 1393{
0ed48fd3 1394 /* We don't support hot unplug of virtio based memory devices */
a0a49813
DH		 1395}
1396
4ec60c76
IM		 1397static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1398 DeviceState *dev, Error **errp)
1399{
d468115b
DH		 1400 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1401 pc_memory_pre_plug(hotplug_dev, dev, errp);
1402 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1403 x86_cpu_pre_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1404 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1405 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1406 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
36efa250
JPB		 1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1408 /* Declare the APIC range as the reserved MSI region */
1409 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1410 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1411
1412 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1413 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1414 resv_prop_str, errp);
1415 g_free(resv_prop_str);
1416 }
1417
1418 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1419 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1b3bf138
JPB		 1420 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1421
1422 if (pcms->iommu) {
1423 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1424 "for x86 yet.");
1425 return;
1426 }
1427 pcms->iommu = dev;
4ec60c76
IM		 1428 }
1429}
1430
95bee274
IM		 1431static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1432 DeviceState *dev, Error **errp)
1433{
1434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1435 pc_memory_plug(hotplug_dev, dev, errp);
5279569e 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1437 x86_cpu_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1439 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1440 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
95bee274
IM		 1441 }
1442}
1443
d9c5c5b8
TC		 1444static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1445 DeviceState *dev, Error **errp)
1446{
64fec58e 1447 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1448 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a 1449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1450 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1452 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1453 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
64fec58e
TC		 1454 } else {
1455 error_setg(errp, "acpi: device unplug request for not supported device"
1456 " type: %s", object_get_typename(OBJECT(dev)));
1457 }
d9c5c5b8
TC		 1458}
1459
232391c1
TC		 1460static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1461 DeviceState *dev, Error **errp)
1462{
f7d3e29d 1463 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1464 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a 1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1466 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1467 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1468 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1469 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
f7d3e29d
TC		 1470 } else {
1471 error_setg(errp, "acpi: device unplug for not supported device"
1472 " type: %s", object_get_typename(OBJECT(dev)));
1473 }
232391c1
TC		 1474}
1475
285816d7 1476static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 1477 DeviceState *dev)
1478{
5279569e 1479 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
a0a49813 1480 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
0ed48fd3 1481 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1b3bf138 1482 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
36efa250 1483 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1b3bf138 1484 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
95bee274
IM		 1485 return HOTPLUG_HANDLER(machine);
1486 }
1487
38aefb57 1488 return NULL;
95bee274
IM		 1489}
1490
bf1e8939 1491static void
f2ffbe2b
DH		 1492pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1493 const char *name, void *opaque,
1494 Error **errp)
bf1e8939 1495{
b0c14ec4 1496 MachineState *ms = MACHINE(obj);
fc3b77e2
IM		 1497 int64_t value = 0;
1498
1499 if (ms->device_memory) {
1500 value = memory_region_size(&ms->device_memory->mr);
1501 }
bf1e8939 1502
51e72bc1 1503 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 1504}
1505
d7bce999
EB		 1506static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1507 void *opaque, Error **errp)
9b23cfb7
DDAG		 1508{
1509 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 1510 OnOffAuto vmport = pcms->vmport;
9b23cfb7 1511
51e72bc1 1512 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 1513}
1514
d7bce999
EB		 1515static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1516 void *opaque, Error **errp)
9b23cfb7
DDAG		 1517{
1518 PCMachineState *pcms = PC_MACHINE(obj);
1519
51e72bc1 1520 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 1521}
1522
be232eb0
CP		 1523static bool pc_machine_get_smbus(Object *obj, Error **errp)
1524{
1525 PCMachineState *pcms = PC_MACHINE(obj);
1526
f5878b03 1527 return pcms->smbus_enabled;
be232eb0
CP		 1528}
1529
1530static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1531{
1532 PCMachineState *pcms = PC_MACHINE(obj);
1533
f5878b03 1534 pcms->smbus_enabled = value;
be232eb0
CP		 1535}
1536
272f0428
CP		 1537static bool pc_machine_get_sata(Object *obj, Error **errp)
1538{
1539 PCMachineState *pcms = PC_MACHINE(obj);
1540
f5878b03 1541 return pcms->sata_enabled;
272f0428
CP		 1542}
1543
1544static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1545{
1546 PCMachineState *pcms = PC_MACHINE(obj);
1547
f5878b03 1548 pcms->sata_enabled = value;
272f0428
CP		 1549}
1550
0259c78c
EH		 1551static bool pc_machine_get_hpet(Object *obj, Error **errp)
1552{
1553 PCMachineState *pcms = PC_MACHINE(obj);
1554
1555 return pcms->hpet_enabled;
1556}
1557
1558static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1559{
1560 PCMachineState *pcms = PC_MACHINE(obj);
1561
1562 pcms->hpet_enabled = value;
1563}
1564
4ccd5fe2
JD		 1565static bool pc_machine_get_i8042(Object *obj, Error **errp)
1566{
1567 PCMachineState *pcms = PC_MACHINE(obj);
1568
1569 return pcms->i8042_enabled;
1570}
1571
1572static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1573{
1574 PCMachineState *pcms = PC_MACHINE(obj);
1575
1576 pcms->i8042_enabled = value;
1577}
1578
c9e96b04
XW		 1579static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1580{
1581 PCMachineState *pcms = PC_MACHINE(obj);
1582
1583 return pcms->default_bus_bypass_iommu;
1584}
1585
1586static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1587 Error **errp)
1588{
1589 PCMachineState *pcms = PC_MACHINE(obj);
1590
1591 pcms->default_bus_bypass_iommu = value;
1592}
1593
0e4edb3b
EH		 1594static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1595 void *opaque, Error **errp)
1596{
1597 PCMachineState *pcms = PC_MACHINE(obj);
1598 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1599
1600 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1601}
1602
1603static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1604 void *opaque, Error **errp)
1605{
1606 PCMachineState *pcms = PC_MACHINE(obj);
1607
1608 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1609}
1610
9a45729d
GH		 1611static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1612 const char *name, void *opaque,
1613 Error **errp)
1614{
1615 PCMachineState *pcms = PC_MACHINE(obj);
1616 uint64_t value = pcms->max_ram_below_4g;
1617
1618 visit_type_size(v, name, &value, errp);
1619}
1620
1621static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1622 const char *name, void *opaque,
1623 Error **errp)
1624{
1625 PCMachineState *pcms = PC_MACHINE(obj);
9a45729d
GH		 1626 uint64_t value;
1627
668f62ec 1628 if (!visit_type_size(v, name, &value, errp)) {
9a45729d
GH		 1629 return;
1630 }
1631 if (value > 4 * GiB) {
dcfe4805 1632 error_setg(errp,
9a45729d
GH		 1633 "Machine option 'max-ram-below-4g=%"PRIu64
1634 "' expects size less than or equal to 4G", value);
9a45729d
GH		 1635 return;
1636 }
1637
1638 if (value < 1 * MiB) {
1639 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1640 "BIOS may not work with less than 1MiB", value);
1641 }
1642
1643 pcms->max_ram_below_4g = value;
1644}
1645
0657c657
EM		 1646static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1647 const char *name, void *opaque,
1648 Error **errp)
1649{
1650 PCMachineState *pcms = PC_MACHINE(obj);
1651 uint64_t value = pcms->max_fw_size;
1652
1653 visit_type_size(v, name, &value, errp);
1654}
1655
1656static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1657 const char *name, void *opaque,
1658 Error **errp)
1659{
1660 PCMachineState *pcms = PC_MACHINE(obj);
1661 Error *error = NULL;
1662 uint64_t value;
1663
1664 visit_type_size(v, name, &value, &error);
1665 if (error) {
1666 error_propagate(errp, error);
1667 return;
1668 }
1669
1670 /*
1671 * We don't have a theoretically justifiable exact lower bound on the base
1672 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1673 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1674 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1675 * size.
1676 */
1677 if (value > 16 * MiB) {
1678 error_setg(errp,
1679 "User specified max allowed firmware size %" PRIu64 " is "
1680 "greater than 16MiB. If combined firwmare size exceeds "
1681 "16MiB the system may not boot, or experience intermittent"
1682 "stability issues.",
1683 value);
1684 return;
1685 }
1686
1687 pcms->max_fw_size = value;
1688}
1689
602b4582 1690
bf1e8939
IM		 1691static void pc_machine_initfn(Object *obj)
1692{
c87b1520 1693 PCMachineState *pcms = PC_MACHINE(obj);
03b39fcf 1694 MachineState *ms = MACHINE(obj);
c87b1520 1695
97fd1ea8 1696#ifdef CONFIG_VMPORT
d1048bef 1697 pcms->vmport = ON_OFF_AUTO_AUTO;
97fd1ea8
JM		 1698#else
1699 pcms->vmport = ON_OFF_AUTO_OFF;
1700#endif /* CONFIG_VMPORT */
9a45729d 1701 pcms->max_ram_below_4g = 0; /* use default */
0e4edb3b
EH		 1702 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1703
021746c1
WL		 1704 /* acpi build is enabled by default if machine supports it */
1705 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 1706 pcms->smbus_enabled = true;
1707 pcms->sata_enabled = true;
4ccd5fe2 1708 pcms->i8042_enabled = true;
0657c657 1709 pcms->max_fw_size = 8 * MiB;
0259c78c
EH		 1710#ifdef CONFIG_HPET
1711 pcms->hpet_enabled = true;
1712#endif
c9e96b04 1713 pcms->default_bus_bypass_iommu = false;
ebc29e1b
MA		 1714
1715 pc_system_flash_create(pcms);
6b8d1416 1716 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
2e16ec05
GH		 1717 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1718 OBJECT(pcms->pcspk), "audiodev");
03b39fcf 1719 cxl_machine_init(obj, ms->cxl_devices_state);
bf1e8939
IM		 1720}
1721
a0628599 1722static void pc_machine_reset(MachineState *machine)
ae50c55a
ZG		 1723{
1724 CPUState *cs;
1725 X86CPU *cpu;
1726
1727 qemu_devices_reset();
1728
1729 /* Reset APIC after devices have been reset to cancel
1730 * any changes that qemu_devices_reset() might have done.
1731 */
1732 CPU_FOREACH(cs) {
1733 cpu = X86_CPU(cs);
1734
1735 if (cpu->apic_state) {
f703a04c 1736 device_legacy_reset(cpu->apic_state);
ae50c55a
ZG		 1737 }
1738 }
1739}
1740
c508bd12
NP		 1741static void pc_machine_wakeup(MachineState *machine)
1742{
1743 cpu_synchronize_all_states();
1744 pc_machine_reset(machine);
1745 cpu_synchronize_all_post_reset();
1746}
1747
c6cbc29d
PX		 1748static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1749{
1750 X86IOMMUState *iommu = x86_iommu_get_default();
1751 IntelIOMMUState *intel_iommu;
1752
1753 if (iommu &&
1754 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1755 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1756 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1757 if (!intel_iommu->caching_mode) {
1758 error_setg(errp, "Device assignment is not allowed without "
1759 "enabling caching-mode=on for Intel IOMMU.");
1760 return false;
1761 }
1762 }
1763
1764 return true;
1765}
1766
95bee274
IM		 1767static void pc_machine_class_init(ObjectClass *oc, void *data)
1768{
1769 MachineClass *mc = MACHINE_CLASS(oc);
1770 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1771 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1772
7102fa70
EH		 1773 pcmc->pci_enabled = true;
1774 pcmc->has_acpi_build = true;
1775 pcmc->rsdp_in_ram = true;
1776 pcmc->smbios_defaults = true;
1777 pcmc->smbios_uuid_encoded = true;
1778 pcmc->gigabyte_align = true;
1779 pcmc->has_reserved_memory = true;
1780 pcmc->kvmclock_enabled = true;
16a9e8a5 1781 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 1782 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1783 * to be used at the moment, 32K should be enough for a while. */
1784 pcmc->acpi_data_size = 0x20000 + 0x8000;
fda672b5 1785 pcmc->pvh_enabled = true;
8700a984 1786 pcmc->kvmclock_create_always = true;
debbdc00 1787 assert(!mc->get_hotplug_handler);
285816d7 1788 mc->get_hotplug_handler = pc_get_hotplug_handler;
c6cbc29d 1789 mc->hotplug_allowed = pc_hotplug_allowed;
81ef68e4
SL		 1790 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1791 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1792 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
7b8be49d 1793 mc->auto_enable_numa_with_memhp = true;
195784a0 1794 mc->auto_enable_numa_with_memdev = true;
c5514d0e 1795 mc->has_hotpluggable_cpus = true;
41742767 1796 mc->default_boot_order = "cad";
2059839b 1797 mc->block_default_type = IF_IDE;
4458fb3a 1798 mc->max_cpus = 255;
ae50c55a 1799 mc->reset = pc_machine_reset;
c508bd12 1800 mc->wakeup = pc_machine_wakeup;
4ec60c76 1801 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 1802 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 1803 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 1804 hc->unplug = pc_machine_device_unplug_cb;
311ca98d 1805 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 1806 mc->nvdimm_supported = true;
e4a97a89 1807 mc->smp_props.dies_supported = true;
abb3009b 1808 mc->cxl_supported = true;
bd457782 1809 mc->default_ram_id = "pc.ram";
0efc257d 1810
9a45729d
GH		 1811 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1812 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1813 NULL, NULL);
1814 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1815 "Maximum ram below the 4G boundary (32bit boundary)");
1816
f2ffbe2b
DH		 1817 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1818 pc_machine_get_device_memory_region_size, NULL,
d2623129 1819 NULL, NULL);
0efc257d 1820
0efc257d
EH		 1821 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1822 pc_machine_get_vmport, pc_machine_set_vmport,
d2623129 1823 NULL, NULL);
0efc257d 1824 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
7eecec7d 1825 "Enable vmport (pc & q35)");
0efc257d 1826
be232eb0 1827 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
d2623129 1828 pc_machine_get_smbus, pc_machine_set_smbus);
44bff376
TH		 1829 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1830 "Enable/disable system management bus");
272f0428
CP		 1831
1832 object_class_property_add_bool(oc, PC_MACHINE_SATA,
d2623129 1833 pc_machine_get_sata, pc_machine_set_sata);
44bff376
TH		 1834 object_class_property_set_description(oc, PC_MACHINE_SATA,
1835 "Enable/disable Serial ATA bus");
feddd2fd 1836
0259c78c
EH		 1837 object_class_property_add_bool(oc, "hpet",
1838 pc_machine_get_hpet, pc_machine_set_hpet);
44bff376
TH		 1839 object_class_property_set_description(oc, "hpet",
1840 "Enable/disable high precision event timer emulation");
0657c657 1841
4ccd5fe2
JD		 1842 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1843 pc_machine_get_i8042, pc_machine_set_i8042);
1844
739b3863 1845 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
c9e96b04
XW		 1846 pc_machine_get_default_bus_bypass_iommu,
1847 pc_machine_set_default_bus_bypass_iommu);
1848
0657c657
EM		 1849 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1850 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1851 NULL, NULL);
1852 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1853 "Maximum combined firmware size");
0e4edb3b
EH		 1854
1855 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1856 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1857 NULL, NULL);
1858 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1859 "SMBIOS Entry Point type [32, 64]");
95bee274
IM		 1860}
1861
d5747cac
IM		 1862static const TypeInfo pc_machine_info = {
1863 .name = TYPE_PC_MACHINE,
f0bb276b 1864 .parent = TYPE_X86_MACHINE,
d5747cac
IM		 1865 .abstract = true,
1866 .instance_size = sizeof(PCMachineState),
bf1e8939 1867 .instance_init = pc_machine_initfn,
d5747cac 1868 .class_size = sizeof(PCMachineClass),
95bee274
IM		 1869 .class_init = pc_machine_class_init,
1870 .interfaces = (InterfaceInfo[]) {
1871 { TYPE_HOTPLUG_HANDLER },
1872 { }
1873 },
d5747cac
IM		 1874};
1875
1876static void pc_machine_register_types(void)
1877{
1878 type_register_static(&pc_machine_info);
1879}
1880
1881type_init(pc_machine_register_types)
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