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hw/i386: Make pit a property of common x86 base machine type
[mirror_qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
549e984e 27#include "hw/i386/x86.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293 32#include "hw/i386/topology.h"
87abaa5d 33#include "hw/i386/fw_cfg.h"
d8f23d61 34#include "hw/i386/vmport.h"
54a40293 35#include "sysemu/cpus.h"
0d09e41a 36#include "hw/block/fdc.h"
83c9f4ca
PB		 37#include "hw/ide.h"
38#include "hw/pci/pci.h"
2118196b 39#include "hw/pci/pci_bus.h"
0d09e41a
PB		 40#include "hw/nvram/fw_cfg.h"
41#include "hw/timer/hpet.h"
a2eb5c0c 42#include "hw/firmware/smbios.h"
83c9f4ca 43#include "hw/loader.h"
ca20cf32 44#include "elf.h"
d6454270 45#include "migration/vmstate.h"
47b43a1f 46#include "multiboot.h"
bcdb9064 47#include "hw/rtc/mc146818rtc.h"
852c27e2 48#include "hw/intc/i8259.h"
55f613ac 49#include "hw/dma/i8257.h"
0d09e41a 50#include "hw/timer/i8254.h"
47973a2d 51#include "hw/input/i8042.h"
64552b6b 52#include "hw/irq.h"
0d09e41a 53#include "hw/audio/pcspk.h"
83c9f4ca
PB		 54#include "hw/pci/msi.h"
55#include "hw/sysbus.h"
9c17d615 56#include "sysemu/sysemu.h"
14a48c1d 57#include "sysemu/tcg.h"
e35704ba 58#include "sysemu/numa.h"
9c17d615 59#include "sysemu/kvm.h"
da278d58 60#include "sysemu/xen.h"
71e8a915 61#include "sysemu/reset.h"
54d31236 62#include "sysemu/runstate.h"
a9dc68d9 63#include "kvm/kvm_i386.h"
0d09e41a 64#include "hw/xen/xen.h"
ab969087 65#include "hw/xen/start_info.h"
a19cbfb3 66#include "ui/qemu-spice.h"
022c62cb 67#include "exec/memory.h"
1de7afc9 68#include "qemu/bitmap.h"
0c764a9d 69#include "qemu/config-file.h"
d49b6836 70#include "qemu/error-report.h"
922a01a0 71#include "qemu/option.h"
133ef074 72#include "qemu/cutils.h"
0445259b 73#include "hw/acpi/acpi.h"
5ff020b7 74#include "hw/acpi/cpu_hotplug.h"
72c194f7 75#include "acpi-build.h"
95bee274 76#include "hw/mem/pc-dimm.h"
4b997690 77#include "hw/mem/nvdimm.h"
6e4e3ae9 78#include "hw/cxl/cxl.h"
e688df6b 79#include "qapi/error.h"
9af23989 80#include "qapi/qapi-visit-common.h"
0e4edb3b 81#include "qapi/qapi-visit-machine.h"
bf1e8939 82#include "qapi/visitor.h"
2e5b09fd 83#include "hw/core/cpu.h"
a310e653 84#include "hw/usb.h"
60c5e104 85#include "hw/i386/intel_iommu.h"
489983d6 86#include "hw/net/ne2000-isa.h"
06e0259a 87#include "standard-headers/asm-x86/bootparam.h"
36efa250 88#include "hw/virtio/virtio-iommu.h"
a0a49813 89#include "hw/virtio/virtio-pmem-pci.h"
0ed48fd3 90#include "hw/virtio/virtio-mem-pci.h"
a0a49813 91#include "hw/mem/memory-device.h"
6f479566
LX		 92#include "sysemu/replay.h"
93#include "qapi/qmp/qerror.h"
d6d059ca 94#include "e820_memory_layout.h"
149c50ca 95#include "fw_cfg.h"
4ca8dabd 96#include "trace.h"
2becc36a 97#include CONFIG_DEVICES
471fd342 98
0ca70366
CH		 99GlobalProperty pc_compat_7_0[] = {};
100const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
101
60f1f77c
DH		 102GlobalProperty pc_compat_6_2[] = {
103 { "virtio-mem", "unplugged-inaccessible", "off" },
104};
01854af2
CH		 105const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
106
f701ecec
VK		 107GlobalProperty pc_compat_6_1[] = {
108 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
109 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
110 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
c318bef7 111 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
f701ecec 112};
52e64f5b
YW		 113const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
114
b7c29017
DB		 115GlobalProperty pc_compat_6_0[] = {
116 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
117 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
118 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
a7a0da84 119 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
aa29466b 120 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
c318bef7 121 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
b7c29017 122};
da7e13c0
CH		 123const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
124
7ed3e1eb
IM		 125GlobalProperty pc_compat_5_2[] = {
126 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
127};
576a00bd
CH		 128const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
129
00dc02d2
IM		 130GlobalProperty pc_compat_5_1[] = {
131 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
c1bb5418 132 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
00dc02d2 133};
3ff3c5d3
CH		 134const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
135
2ebc2121
HW		 136GlobalProperty pc_compat_5_0[] = {
137};
541aaa1d
CH		 138const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
139
f404220e
IM		 140GlobalProperty pc_compat_4_2[] = {
141 { "mch", "smbase-smram", "off" },
142};
3eb74d20
CH		 143const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
144
9aec2e52
CH		 145GlobalProperty pc_compat_4_1[] = {};
146const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
147
9bf2650b
CH		 148GlobalProperty pc_compat_4_0[] = {};
149const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
150
abd93cc7 151GlobalProperty pc_compat_3_1[] = {
6c36bddf 152 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 153 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
154 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 155 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
156 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 157 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 158 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
159 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
160 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
161 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
162 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 164 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
165 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
168 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
169 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
170 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 171 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 172 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 173};
174const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
175
ddb3235d 176GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 177 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
178 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
179 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 180};
181const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
182
0d47310b 183GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 184 { TYPE_X86_CPU, "legacy-cache", "on" },
185 { TYPE_X86_CPU, "topoext", "off" },
186 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
187 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 188};
189const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
190
43df70a9 191GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 192 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
193 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 194};
195const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
196
503224f4 197GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 198 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
199 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
200 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 201};
202const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
203
3e803152 204GlobalProperty pc_compat_2_9[] = {
6c36bddf 205 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 206};
207const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
208
edc24ccd 209GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 210 { TYPE_X86_CPU, "tcg-cpuid", "off" },
211 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
212 { "ICH9-LPC", "x-smi-broadcast", "off" },
213 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
214 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 215};
216const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
217
5a995064 218GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 219 { TYPE_X86_CPU, "l3-cache", "off" },
220 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
221 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
222 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
223 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
224 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 225};
226const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
227
ff8f261f 228GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 229 { TYPE_X86_CPU, "cpuid-0xb", "off" },
230 { "vmxnet3", "romfile", "" },
231 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
232 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 233};
234const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
235
fe759610
MAL		 236GlobalProperty pc_compat_2_5[] = {};
237const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
238
2f99b9c2
MAL		 239GlobalProperty pc_compat_2_4[] = {
240 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 241 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
242 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
243 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
244 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
245 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
246 { TYPE_X86_CPU, "check", "off" },
247 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
248 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
249 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
250 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
251 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
252 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
253 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
254 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 255};
256const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
257
8995dd90
MAL		 258GlobalProperty pc_compat_2_3[] = {
259 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 260 { TYPE_X86_CPU, "arat", "off" },
261 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
262 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
263 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
264 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
265 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
266 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
267 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
268 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
276 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
277 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
278 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
279 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 280};
281const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
282
1c30044e
MAL		 283GlobalProperty pc_compat_2_2[] = {
284 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 285 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
286 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
287 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
288 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
291 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
292 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
297 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
298 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
299 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
300 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
301 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
302 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 303};
304const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
305
c4fc5695
MAL		 306GlobalProperty pc_compat_2_1[] = {
307 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 308 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
309 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 310};
311const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
312
a310e653
MAL		 313GlobalProperty pc_compat_2_0[] = {
314 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 315 { "virtio-scsi-pci", "any_layout", "off" },
316 { "PIIX4_PM", "memory-hotplug-support", "off" },
317 { "apic", "version", "0x11" },
318 { "nec-usb-xhci", "superspeed-ports-first", "off" },
319 { "nec-usb-xhci", "force-pcie-endcap", "on" },
320 { "pci-serial", "prog_if", "0" },
321 { "pci-serial-2x", "prog_if", "0" },
322 { "pci-serial-4x", "prog_if", "0" },
323 { "virtio-net-pci", "guest_announce", "off" },
324 { "ICH9-LPC", "memory-hotplug-support", "off" },
a310e653
MAL		 325};
326const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
327
328GlobalProperty pc_compat_1_7[] = {
329 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf 330 { TYPE_USB_DEVICE, "msos-desc", "no" },
aa29466b 331 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
6c36bddf 332 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 333};
334const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
335
336GlobalProperty pc_compat_1_6[] = {
337 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 338 { "e1000", "mitigation", "off" },
339 { "qemu64-" TYPE_X86_CPU, "model", "2" },
340 { "qemu32-" TYPE_X86_CPU, "model", "3" },
341 { "i440FX-pcihost", "short_root_bus", "1" },
342 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 343};
344const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
345
346GlobalProperty pc_compat_1_5[] = {
347 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 348 { "Conroe-" TYPE_X86_CPU, "model", "2" },
349 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
350 { "Penryn-" TYPE_X86_CPU, "model", "2" },
351 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
352 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
353 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
354 { "virtio-net-pci", "any_layout", "off" },
355 { TYPE_X86_CPU, "pmu", "on" },
356 { "i440FX-pcihost", "short_root_bus", "0" },
357 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 358};
359const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
360
361GlobalProperty pc_compat_1_4[] = {
362 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 363 { "scsi-hd", "discard_granularity", "0" },
364 { "scsi-cd", "discard_granularity", "0" },
6c36bddf
EH		 365 { "ide-hd", "discard_granularity", "0" },
366 { "ide-cd", "discard_granularity", "0" },
6c36bddf
EH		 367 { "virtio-blk-pci", "discard_granularity", "0" },
368 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
369 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
370 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
371 { "e1000", "romfile", "pxe-e1000.rom" },
372 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
373 { "pcnet", "romfile", "pxe-pcnet.rom" },
374 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
375 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
376 { "486-" TYPE_X86_CPU, "model", "0" },
377 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
378 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 379};
380const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
381
417258f1
PMD		 382GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
383{
384 GSIState *s;
385
386 s = g_new0(GSIState, 1);
387 if (kvm_ioapic_in_kernel()) {
388 kvm_pc_setup_irq_routing(pci_enabled);
417258f1 389 }
64c033ba 390 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
417258f1
PMD		 391
392 return s;
393}
394
258711c6
JG		 395static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
396 unsigned size)
80cabfad
FB		 397{
398}
399
c02e1eac
JG		 400static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
401{
a6fc23e5 402 return 0xffffffffffffffffULL;
c02e1eac
JG		 403}
404
f929aad6 405/* MSDOS compatibility mode FPU exception support */
258711c6
JG		 406static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
407 unsigned size)
f929aad6 408{
6f529b75 409 if (tcg_enabled()) {
bf13bfab 410 cpu_set_ignne();
6f529b75 411 }
f929aad6
FB		 412}
413
c02e1eac
JG		 414static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
415{
a6fc23e5 416 return 0xffffffffffffffffULL;
c02e1eac
JG		 417}
418
b0a21b53
FB		 419/* PC cmos mappings */
420
80cabfad
FB		 421#define REG_EQUIPMENT_BYTE 0x14
422
9139046c
MA		 423static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
424 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 425{
ba6c2377
FB		 426 rtc_set_memory(s, type_ofs, 47);
427 rtc_set_memory(s, info_ofs, cylinders);
428 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
429 rtc_set_memory(s, info_ofs + 2, heads);
430 rtc_set_memory(s, info_ofs + 3, 0xff);
431 rtc_set_memory(s, info_ofs + 4, 0xff);
432 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
433 rtc_set_memory(s, info_ofs + 6, cylinders);
434 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
435 rtc_set_memory(s, info_ofs + 8, sectors);
436}
437
6ac0e82d
AZ		 438/* convert boot_device letter to something recognizable by the bios */
439static int boot_device2nibble(char boot_device)
440{
441 switch(boot_device) {
442 case 'a':
443 case 'b':
444 return 0x01; /* floppy boot */
445 case 'c':
446 return 0x02; /* hard drive boot */
447 case 'd':
448 return 0x03; /* CD-ROM boot */
449 case 'n':
450 return 0x04; /* Network boot */
451 }
452 return 0;
453}
454
ddcd5531 455static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 456{
457#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 458 int nbds, bds[3] = { 0, };
459 int i;
460
461 nbds = strlen(boot_device);
462 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 463 error_setg(errp, "Too many boot devices for PC");
464 return;
0ecdffbb
AJ		 465 }
466 for (i = 0; i < nbds; i++) {
467 bds[i] = boot_device2nibble(boot_device[i]);
468 if (bds[i] == 0) {
ddcd5531
GA		 469 error_setg(errp, "Invalid boot device for PC: '%c'",
470 boot_device[i]);
471 return;
0ecdffbb
AJ		 472 }
473 }
474 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 475 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 476}
477
ddcd5531 478static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 479{
ddcd5531 480 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 481}
482
7444ca4e
LE		 483static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
484{
485 int val, nb, i;
2da44dd0
JS		 486 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
487 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 488
489 /* floppy type */
490 if (floppy) {
491 for (i = 0; i < 2; i++) {
492 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
493 }
494 }
495 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
496 cmos_get_fd_drive_type(fd_type[1]);
497 rtc_set_memory(rtc_state, 0x10, val);
498
499 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
500 nb = 0;
2da44dd0 501 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 502 nb++;
503 }
2da44dd0 504 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 505 nb++;
506 }
507 switch (nb) {
508 case 0:
509 break;
510 case 1:
511 val |= 0x01; /* 1 drive, ready for boot */
512 break;
513 case 2:
514 val |= 0x41; /* 2 drives, ready for boot */
515 break;
516 }
517 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
518}
519
c0897e0c
MA		 520typedef struct pc_cmos_init_late_arg {
521 ISADevice *rtc_state;
9139046c 522 BusState *idebus[2];
c0897e0c
MA		 523} pc_cmos_init_late_arg;
524
b86f4613
LE		 525typedef struct check_fdc_state {
526 ISADevice *floppy;
527 bool multiple;
528} CheckFdcState;
529
530static int check_fdc(Object *obj, void *opaque)
531{
532 CheckFdcState *state = opaque;
533 Object *fdc;
534 uint32_t iobase;
535 Error *local_err = NULL;
536
537 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
538 if (!fdc) {
539 return 0;
540 }
541
1ea1572a 542 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 543 if (local_err || iobase != 0x3f0) {
544 error_free(local_err);
545 return 0;
546 }
547
548 if (state->floppy) {
549 state->multiple = true;
550 } else {
551 state->floppy = ISA_DEVICE(obj);
552 }
553 return 0;
554}
555
556static const char * const fdc_container_path[] = {
557 "/unattached", "/peripheral", "/peripheral-anon"
558};
559
424e4a87
RK		 560/*
561 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
562 * and ACPI objects.
563 */
564ISADevice *pc_find_fdc0(void)
565{
566 int i;
567 Object *container;
568 CheckFdcState state = { 0 };
569
570 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
571 container = container_get(qdev_get_machine(), fdc_container_path[i]);
572 object_child_foreach(container, check_fdc, &state);
573 }
574
575 if (state.multiple) {
3dc6f869
AF		 576 warn_report("multiple floppy disk controllers with "
577 "iobase=0x3f0 have been found");
433672b0 578 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 579 "your intent");
424e4a87
RK		 580 }
581
582 return state.floppy;
583}
584
c0897e0c
MA		 585static void pc_cmos_init_late(void *opaque)
586{
587 pc_cmos_init_late_arg *arg = opaque;
588 ISADevice *s = arg->rtc_state;
9139046c
MA		 589 int16_t cylinders;
590 int8_t heads, sectors;
c0897e0c 591 int val;
2adc99b2 592 int i, trans;
c0897e0c 593
9139046c 594 val = 0;
272f0428
CP		 595 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
596 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 597 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
598 val |= 0xf0;
599 }
272f0428
CP		 600 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
601 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 602 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
603 val |= 0x0f;
604 }
605 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 606
607 val = 0;
608 for (i = 0; i < 4; i++) {
9139046c
MA		 609 /* NOTE: ide_get_geometry() returns the physical
610 geometry. It is always such that: 1 <= sects <= 63, 1
611 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
612 geometry can be different if a translation is done. */
272f0428
CP		 613 if (arg->idebus[i / 2] &&
614 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 615 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 616 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
617 assert((trans & ~3) == 0);
618 val |= trans << (i * 2);
c0897e0c
MA		 619 }
620 }
621 rtc_set_memory(s, 0x39, val);
622
424e4a87 623 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 624
c0897e0c
MA		 625 qemu_unregister_reset(pc_cmos_init_late, opaque);
626}
627
23d30407 628void pc_cmos_init(PCMachineState *pcms,
220a8846 629 BusState *idebus0, BusState *idebus1,
63ffb564 630 ISADevice *s)
80cabfad 631{
7444ca4e 632 int val;
c0897e0c 633 static pc_cmos_init_late_arg arg;
f0bb276b 634 X86MachineState *x86ms = X86_MACHINE(pcms);
b0a21b53 635
b0a21b53 636 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 637
638 /* memory size */
e89001f7 639 /* base memory (first MiB) */
f0bb276b 640 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
333190eb
FB		 641 rtc_set_memory(s, 0x15, val);
642 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 643 /* extended memory (next 64MiB) */
f0bb276b
PB		 644 if (x86ms->below_4g_mem_size > 1 * MiB) {
645 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 646 } else {
647 val = 0;
648 }
80cabfad
FB		 649 if (val > 65535)
650 val = 65535;
b0a21b53
FB		 651 rtc_set_memory(s, 0x17, val);
652 rtc_set_memory(s, 0x18, val >> 8);
653 rtc_set_memory(s, 0x30, val);
654 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 655 /* memory between 16MiB and 4GiB */
f0bb276b
PB		 656 if (x86ms->below_4g_mem_size > 16 * MiB) {
657 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 658 } else {
9da98861 659 val = 0;
e89001f7 660 }
80cabfad
FB		 661 if (val > 65535)
662 val = 65535;
b0a21b53
FB		 663 rtc_set_memory(s, 0x34, val);
664 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 665 /* memory above 4GiB */
f0bb276b 666 val = x86ms->above_4g_mem_size / 65536;
e89001f7
MA		 667 rtc_set_memory(s, 0x5b, val);
668 rtc_set_memory(s, 0x5c, val >> 8);
669 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 670
23d30407 671 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 672 TYPE_ISA_DEVICE,
f0bb276b 673 (Object **)&x86ms->rtc,
2d996150 674 object_property_allow_set_link,
d2623129 675 OBJ_PROP_LINK_STRONG);
5325cc34
MA		 676 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
677 &error_abort);
298e01b6 678
97ec4d21 679 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
80cabfad 680
b0a21b53 681 val = 0;
b0a21b53
FB		 682 val |= 0x02; /* FPU is there */
683 val |= 0x04; /* PS/2 mouse installed */
684 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
685
b86f4613 686 /* hard drives and FDC */
c0897e0c 687 arg.rtc_state = s;
9139046c
MA		 688 arg.idebus[0] = idebus0;
689 arg.idebus[1] = idebus1;
c0897e0c 690 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 691}
692
956a3e6b 693static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 694{
cc36a7a2 695 X86CPU *cpu = opaque;
e1a23744 696
956a3e6b 697 /* XXX: send to all CPUs ? */
4b78a802 698 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 699 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 700}
701
b41a2cd1
FB		 702#define NE2000_NB_MAX 6
703
675d6f82
BS		 704static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
705 0x280, 0x380 };
706static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 707
48a18b3c 708void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 709{
710 static int nb_ne2k = 0;
711
712 if (nb_ne2k == NE2000_NB_MAX)
713 return;
48a18b3c 714 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 715 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 716 nb_ne2k++;
717}
718
845773ab 719void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 720{
c3affe56 721 X86CPU *cpu = opaque;
53b67b30
BS		 722
723 if (level) {
c3affe56 724 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 725 }
726}
727
3459a625 728static
9ebeed0c 729void pc_machine_done(Notifier *notifier, void *data)
3459a625 730{
9ebeed0c
EH		 731 PCMachineState *pcms = container_of(notifier,
732 PCMachineState, machine_done);
f0bb276b 733 X86MachineState *x86ms = X86_MACHINE(pcms);
2118196b 734
ba157b69 735 /* set the number of CPUs */
0cca1a91 736 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
ba157b69 737
0abd3888 738 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
2118196b 739
bb292f5a 740 acpi_setup();
f0bb276b
PB		 741 if (x86ms->fw_cfg) {
742 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
743 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
e3cadac0 744 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
f0bb276b 745 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
6d42eefa 746 }
3459a625
MT		 747}
748
e4e8ba04 749void pc_guest_info_init(PCMachineState *pcms)
3459a625 750{
f0bb276b 751 X86MachineState *x86ms = X86_MACHINE(pcms);
b20c9bd5 752
eafa0868 753 x86ms->apic_xrupt_override = true;
9ebeed0c
EH		 754 pcms->machine_done.notify = pc_machine_done;
755 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 756}
757
83d08f26
MT		 758/* setup pci memory address space mapping into system address space */
759void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
760 MemoryRegion *pci_address_space)
39848901 761{
83d08f26
MT		 762 /* Set to lower priority than RAM */
763 memory_region_add_subregion_overlap(system_memory, 0x0,
764 pci_address_space, -1);
39848901
IM		 765}
766
7bc35e0f 767void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 768{
769 int i;
770 FWCfgState *fw_cfg;
703a548a 771 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 772 X86MachineState *x86ms = X86_MACHINE(pcms);
b33a5bbf 773
df1f79fd 774 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 775
305ae888 776 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
f0bb276b 777 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
b33a5bbf
CL		 778 rom_set_fw(fw_cfg);
779
703a548a 780 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
f014c974 781 pcmc->pvh_enabled);
b33a5bbf
CL		 782 for (i = 0; i < nb_option_roms; i++) {
783 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 784 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 785 !strcmp(option_rom[i].name, "pvh.bin") ||
3ca8ce72
PB		 786 !strcmp(option_rom[i].name, "multiboot.bin") ||
787 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
b33a5bbf
CL		 788 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
789 }
f0bb276b 790 x86ms->fw_cfg = fw_cfg;
b33a5bbf
CL		 791}
792
72686c58
PMD		 793#define PC_ROM_MIN_VGA 0xc0000
794#define PC_ROM_MIN_OPTION 0xc8000
795#define PC_ROM_MAX 0xe0000
796#define PC_ROM_ALIGN 0x800
797#define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
798
5934e216
EH		 799void pc_memory_init(PCMachineState *pcms,
800 MemoryRegion *system_memory,
801 MemoryRegion *rom_memory,
802 MemoryRegion **ram_memory)
80cabfad 803{
cbc5b5f3 804 int linux_boot, i;
bd457782 805 MemoryRegion *option_rom_mr;
00cb2a99 806 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 807 FWCfgState *fw_cfg;
62b160c0 808 MachineState *machine = MACHINE(pcms);
264b4857 809 MachineClass *mc = MACHINE_GET_CLASS(machine);
16a9e8a5 810 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 811 X86MachineState *x86ms = X86_MACHINE(pcms);
6d302cf4 812 hwaddr cxl_base, cxl_resv_end = 0;
d592d303 813
f0bb276b
PB		 814 assert(machine->ram_size == x86ms->below_4g_mem_size +
815 x86ms->above_4g_mem_size);
9521d42b
PB		 816
817 linux_boot = (machine->kernel_filename != NULL);
80cabfad 818
bd457782
IM		 819 /*
820 * Split single memory region and use aliases to address portions of it,
821 * done for backwards compatibility with older qemus.
00cb2a99 822 */
bd457782 823 *ram_memory = machine->ram;
7267c094 824 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
bd457782 825 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
f0bb276b 826 0, x86ms->below_4g_mem_size);
00cb2a99 827 memory_region_add_subregion(system_memory, 0, ram_below_4g);
f0bb276b
PB		 828 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
829 if (x86ms->above_4g_mem_size > 0) {
7267c094 830 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
bd457782
IM		 831 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
832 machine->ram,
f0bb276b
PB		 833 x86ms->below_4g_mem_size,
834 x86ms->above_4g_mem_size);
00cb2a99
AK		 835 memory_region_add_subregion(system_memory, 0x100000000ULL,
836 ram_above_4g);
f0bb276b 837 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
bbe80adf 838 }
82b36dc3 839
1ed1ccc5
SC		 840 if (pcms->sgx_epc.size != 0) {
841 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
842 }
843
bb292f5a 844 if (!pcmc->has_reserved_memory &&
ca8336f3 845 (machine->ram_slots ||
9521d42b 846 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 847
848 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
849 mc->name);
850 exit(EXIT_FAILURE);
851 }
852
b0c14ec4
DH		 853 /* always allocate the device memory information */
854 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
855
f2ffbe2b 856 /* initialize device memory address space */
bb292f5a 857 if (pcmc->has_reserved_memory &&
9521d42b 858 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 859 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 860
a0cc8856
IM		 861 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
862 error_report("unsupported amount of memory slots: %"PRIu64,
863 machine->ram_slots);
864 exit(EXIT_FAILURE);
865 }
866
f2c38522
PK		 867 if (QEMU_ALIGN_UP(machine->maxram_size,
868 TARGET_PAGE_SIZE) != machine->maxram_size) {
869 error_report("maximum memory size must by aligned to multiple of "
870 "%d bytes", TARGET_PAGE_SIZE);
871 exit(EXIT_FAILURE);
872 }
873
0cf4ce00
SC		 874 if (pcms->sgx_epc.size != 0) {
875 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc);
876 } else {
877 machine->device_memory->base =
878 0x100000000ULL + x86ms->above_4g_mem_size;
879 }
880
b0c14ec4 881 machine->device_memory->base =
0cf4ce00 882 ROUND_UP(machine->device_memory->base, 1 * GiB);
619d11e4 883
16a9e8a5 884 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 885 /* size device region assuming 1G page max alignment per slot */
d471bf3e 886 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 887 }
888
f2ffbe2b
DH		 889 if ((machine->device_memory->base + device_mem_size) <
890 device_mem_size) {
619d11e4
IM		 891 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
892 machine->maxram_size);
893 exit(EXIT_FAILURE);
894 }
895
b0c14ec4 896 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 897 "device-memory", device_mem_size);
b0c14ec4
DH		 898 memory_region_add_subregion(system_memory, machine->device_memory->base,
899 &machine->device_memory->mr);
619d11e4 900 }
cbc5b5f3 901
6e4e3ae9
BW		 902 if (machine->cxl_devices_state->is_enabled) {
903 MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
904 hwaddr cxl_size = MiB;
905
906 if (pcmc->has_reserved_memory && machine->device_memory->base) {
907 cxl_base = machine->device_memory->base;
908 if (!pcmc->broken_reserved_end) {
909 cxl_base += memory_region_size(&machine->device_memory->mr);
910 }
911 } else if (pcms->sgx_epc.size != 0) {
912 cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc);
913 } else {
914 cxl_base = 0x100000000ULL + x86ms->above_4g_mem_size;
915 }
916
917 e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
918 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
919 memory_region_add_subregion(system_memory, cxl_base, mr);
6d302cf4
JC		 920 cxl_resv_end = cxl_base + cxl_size;
921 if (machine->cxl_devices_state->fixed_windows) {
922 hwaddr cxl_fmw_base;
923 GList *it;
924
925 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
926 for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) {
927 CXLFixedWindow *fw = it->data;
928
929 fw->base = cxl_fmw_base;
930 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
931 "cxl-fixed-memory-region", fw->size);
932 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
933 e820_add_entry(fw->base, fw->size, E820_RESERVED);
934 cxl_fmw_base += fw->size;
935 cxl_resv_end = cxl_fmw_base;
936 }
937 }
6e4e3ae9
BW		 938 }
939
cbc5b5f3 940 /* Initialize PC system firmware */
5e640a9e 941 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 942
7267c094 943 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 944 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 945 &error_fatal);
208fa0e4
IM		 946 if (pcmc->pci_enabled) {
947 memory_region_set_readonly(option_rom_mr, true);
948 }
4463aee6 949 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 950 PC_ROM_MIN_VGA,
951 option_rom_mr,
952 1);
f753ff16 953
bd802bd9 954 fw_cfg = fw_cfg_arch_create(machine,
f0bb276b 955 x86ms->boot_cpus, x86ms->apic_id_limit);
c886fc4c 956
8832cb80 957 rom_set_fw(fw_cfg);
1d108d97 958
b0c14ec4 959 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 960 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 961 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 962 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 963
964 if (!pcmc->broken_reserved_end) {
b0c14ec4 965 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 966 }
6d302cf4
JC		 967
968 if (machine->cxl_devices_state->is_enabled) {
969 res_mem_end = cxl_resv_end;
970 }
d471bf3e 971 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 972 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
973 }
974
f753ff16 975 if (linux_boot) {
703a548a 976 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
f014c974 977 pcmc->pvh_enabled);
f753ff16
PB		 978 }
979
980 for (i = 0; i < nb_option_roms; i++) {
2e55e842 981 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 982 }
f0bb276b 983 x86ms->fw_cfg = fw_cfg;
cb135f59
PX		 984
985 /* Init default IOAPIC address space */
f0bb276b 986 x86ms->ioapic_as = &address_space_memory;
091c466e
SK		 987
988 /* Init ACPI memory hotplug IO base address */
989 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
3d53f5c3
IY		 990}
991
9fa99d25
MA		 992/*
993 * The 64bit pci hole starts after "above 4G RAM" and
994 * potentially the space reserved for memory hotplug.
995 */
996uint64_t pc_pci_hole64_start(void)
997{
998 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
999 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1000 MachineState *ms = MACHINE(pcms);
f0bb276b 1001 X86MachineState *x86ms = X86_MACHINE(pcms);
9fa99d25
MA		 1002 uint64_t hole64_start = 0;
1003
6e4e3ae9
BW		 1004 if (ms->cxl_devices_state->host_mr.addr) {
1005 hole64_start = ms->cxl_devices_state->host_mr.addr +
1006 memory_region_size(&ms->cxl_devices_state->host_mr);
6d302cf4
JC		 1007 if (ms->cxl_devices_state->fixed_windows) {
1008 GList *it;
1009 for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
1010 CXLFixedWindow *fw = it->data;
1011 hole64_start = fw->mr.addr + memory_region_size(&fw->mr);
1012 }
1013 }
6e4e3ae9 1014 } else if (pcmc->has_reserved_memory && ms->device_memory->base) {
b0c14ec4 1015 hole64_start = ms->device_memory->base;
9fa99d25 1016 if (!pcmc->broken_reserved_end) {
b0c14ec4 1017 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25 1018 }
0cf4ce00
SC		 1019 } else if (pcms->sgx_epc.size != 0) {
1020 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc);
9fa99d25 1021 } else {
f0bb276b 1022 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
9fa99d25
MA		 1023 }
1024
d471bf3e 1025 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1026}
1027
48a18b3c 1028DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1029{
ad6d45fa
AL		 1030 DeviceState *dev = NULL;
1031
bab47d9a 1032 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1033 if (pci_bus) {
1034 PCIDevice *pcidev = pci_vga_init(pci_bus);
1035 dev = pcidev ? &pcidev->qdev : NULL;
1036 } else if (isa_bus) {
1037 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1038 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1039 }
bab47d9a 1040 rom_reset_order_override();
ad6d45fa 1041 return dev;
765d7908
IY		 1042}
1043
258711c6
JG		 1044static const MemoryRegionOps ioport80_io_ops = {
1045 .write = ioport80_write,
c02e1eac 1046 .read = ioport80_read,
258711c6
JG		 1047 .endianness = DEVICE_NATIVE_ENDIAN,
1048 .impl = {
1049 .min_access_size = 1,
1050 .max_access_size = 1,
1051 },
1052};
1053
1054static const MemoryRegionOps ioportF0_io_ops = {
1055 .write = ioportF0_write,
c02e1eac 1056 .read = ioportF0_read,
258711c6
JG		 1057 .endianness = DEVICE_NATIVE_ENDIAN,
1058 .impl = {
1059 .min_access_size = 1,
1060 .max_access_size = 1,
1061 },
1062};
1063
4ccd5fe2
JD		 1064static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1065 bool create_i8042, bool no_vmport)
ac64273c
PMD		 1066{
1067 int i;
1068 DriveInfo *fd[MAX_FD];
1069 qemu_irq *a20_line;
fed2c173 1070 ISADevice *fdc, *i8042, *port92, *vmmouse;
ac64273c 1071
def337ff 1072 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1073 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1074
1075 for (i = 0; i < MAX_FD; i++) {
1076 fd[i] = drive_get(IF_FLOPPY, 0, i);
1077 create_fdctrl |= !!fd[i];
1078 }
1079 if (create_fdctrl) {
fed2c173
MA		 1080 fdc = isa_new(TYPE_ISA_FDC);
1081 if (fdc) {
1082 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1083 isa_fdc_init_drives(fdc, fd);
1084 }
ac64273c
PMD		 1085 }
1086
4ccd5fe2
JD		 1087 if (!create_i8042) {
1088 return;
1089 }
1090
ac64273c
PMD		 1091 i8042 = isa_create_simple(isa_bus, "i8042");
1092 if (!no_vmport) {
b4fa79ea 1093 isa_create_simple(isa_bus, TYPE_VMPORT);
c23e0561 1094 vmmouse = isa_try_new("vmmouse");
ac64273c
PMD		 1095 } else {
1096 vmmouse = NULL;
1097 }
1098 if (vmmouse) {
5325cc34
MA		 1099 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1100 &error_abort);
c23e0561 1101 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
ac64273c 1102 }
9e5213c8 1103 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
ac64273c
PMD		 1104
1105 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1106 i8042_setup_a20_line(i8042, a20_line[0]);
1820b70e
PMD		 1107 qdev_connect_gpio_out_named(DEVICE(port92),
1108 PORT92_A20_LINE, 0, a20_line[1]);
ac64273c
PMD		 1109 g_free(a20_line);
1110}
1111
10e2483b
GH		 1112void pc_basic_device_init(struct PCMachineState *pcms,
1113 ISABus *isa_bus, qemu_irq *gsi,
1611977c 1114 ISADevice **rtc_state,
fd53c87c 1115 bool create_fdctrl,
3a87d009 1116 uint32_t hpet_irqs)
ffe513da
IY		 1117{
1118 int i;
ce967e2f
JK		 1119 DeviceState *hpet = NULL;
1120 int pit_isa_irq = 0;
1121 qemu_irq pit_alt_irq = NULL;
7d932dfd 1122 qemu_irq rtc_irq = NULL;
ac64273c 1123 ISADevice *pit = NULL;
258711c6
JG		 1124 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1125 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
9dee7e51 1126 X86MachineState *x86ms = X86_MACHINE(pcms);
ffe513da 1127
2c9b15ca 1128 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 1129 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 1130
2c9b15ca 1131 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 1132 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 1133
5d17c0d2
JK		 1134 /*
1135 * Check if an HPET shall be created.
1136 *
1137 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1138 * when the HPET wants to take over. Thus we have to disable the latter.
1139 */
0259c78c
EH		 1140 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1141 kvm_has_pit_state2())) {
df707969 1142 hpet = qdev_try_new(TYPE_HPET);
0259c78c
EH		 1143 if (!hpet) {
1144 error_report("couldn't create HPET device");
1145 exit(1);
1146 }
54420332
MT		 1147 /*
1148 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1149 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1150 * IRQ2.
1151 */
0259c78c
EH		 1152 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1153 HPET_INTCAP, NULL);
1154 if (!compat) {
1155 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1156 }
1157 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1158 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
7a10ef51 1159
0259c78c
EH		 1160 for (i = 0; i < GSI_NUM_PINS; i++) {
1161 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
822557eb 1162 }
0259c78c
EH		 1163 pit_isa_irq = -1;
1164 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1165 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
ffe513da 1166 }
6c646a11 1167 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 1168
1169 qemu_register_boot_set(pc_boot_set, *rtc_state);
1170
9dee7e51
XL		 1171 if (!xen_enabled() &&
1172 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
15eafc2e 1173 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 1174 pit = kvm_pit_init(isa_bus, 0x40);
1175 } else {
acf695ec 1176 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 1177 }
1178 if (hpet) {
1179 /* connect PIT to output control line of the HPET */
4a17cc4f 1180 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311 1181 }
6b8d1416 1182 pcspk_init(pcms->pcspk, isa_bus, pit);
ce967e2f 1183 }
ffe513da 1184
55f613ac 1185 i8257_dma_init(isa_bus, 0);
ffe513da 1186
ac64273c 1187 /* Super I/O */
4ccd5fe2
JD		 1188 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1189 pcms->vmport != ON_OFF_AUTO_ON);
ffe513da
IY		 1190}
1191
4b9c264b 1192void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 1193{
1194 int i;
1195
bab47d9a 1196 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 1197 for (i = 0; i < nb_nics; i++) {
1198 NICInfo *nd = &nd_table[i];
4b9c264b 1199 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 1200
4b9c264b 1201 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 1202 pc_init_ne2k_isa(isa_bus, nd);
1203 } else {
4b9c264b 1204 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 1205 }
1206 }
bab47d9a 1207 rom_reset_order_override();
9011a1a7
IY		 1208}
1209
4501d317
PMD		 1210void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1211{
1212 qemu_irq *i8259;
1213
1214 if (kvm_pic_in_kernel()) {
1215 i8259 = kvm_i8259_init(isa_bus);
1216 } else if (xen_enabled()) {
1217 i8259 = xen_interrupt_controller_init();
1218 } else {
89a289c7 1219 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
4501d317
PMD		 1220 }
1221
1222 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1223 i8259_irqs[i] = i8259[i];
1224 }
1225
1226 g_free(i8259);
1227}
1228
d468115b
DH		 1229static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1230 Error **errp)
1231{
1232 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1233 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
b0e62443 1234 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 1235 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 1236 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 1237 const uint64_t legacy_align = TARGET_PAGE_SIZE;
ae909496 1238 Error *local_err = NULL;
d468115b
DH		 1239
1240 /*
1241 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1242 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1243 * addition to cover this case.
1244 */
50aef131 1245 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
d468115b
DH		 1246 error_setg(errp,
1247 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1248 return;
1249 }
1250
f6a0d06b 1251 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 1252 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1253 return;
1254 }
8f1ffe5b 1255
50aef131 1256 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
ae909496
TH		 1257 if (local_err) {
1258 error_propagate(errp, local_err);
1259 return;
1260 }
1261
fd3416f5 1262 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 1263 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 1264}
1265
bb6e2f7a
DH		 1266static void pc_memory_plug(HotplugHandler *hotplug_dev,
1267 DeviceState *dev, Error **errp)
95bee274 1268{
95bee274 1269 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1270 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f6a0d06b 1271 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 1272 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 1273
84fd5496 1274 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
b8865591 1275
7f3cf2d6 1276 if (is_nvdimm) {
f6a0d06b 1277 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 1278 }
1279
50aef131 1280 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
95bee274
IM		 1281}
1282
bb6e2f7a
DH		 1283static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1284 DeviceState *dev, Error **errp)
64fec58e 1285{
50aef131 1286 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
64fec58e 1287
8cd91ace
HZ		 1288 /*
1289 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1290 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1291 * addition to cover this case.
1292 */
50aef131 1293 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
dcfe4805 1294 error_setg(errp,
8cd91ace 1295 "memory hotplug is not enabled: missing acpi device or acpi disabled");
dcfe4805 1296 return;
64fec58e
TC		 1297 }
1298
b097cc52 1299 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
dcfe4805
MA		 1300 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1301 return;
b097cc52
XG		 1302 }
1303
50aef131 1304 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
dcfe4805 1305 errp);
64fec58e
TC		 1306}
1307
bb6e2f7a
DH		 1308static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1309 DeviceState *dev, Error **errp)
f7d3e29d
TC		 1310{
1311 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
50aef131 1312 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
f7d3e29d
TC		 1313 Error *local_err = NULL;
1314
50aef131 1315 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
f7d3e29d
TC		 1316 if (local_err) {
1317 goto out;
1318 }
1319
fd3416f5 1320 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
981c3dcd 1321 qdev_unrealize(dev);
f7d3e29d
TC		 1322 out:
1323 error_propagate(errp, local_err);
1324}
1325
0ed48fd3
DH		 1326static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1327 DeviceState *dev, Error **errp)
a0a49813
DH		 1328{
1329 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1330 Error *local_err = NULL;
1331
af1d039f 1332 if (!hotplug_dev2 && dev->hotplugged) {
a0a49813
DH		 1333 /*
1334 * Without a bus hotplug handler, we cannot control the plug/unplug
af1d039f
DH		 1335 * order. We should never reach this point when hotplugging on x86,
1336 * however, better add a safety net.
a0a49813 1337 */
0ed48fd3
DH		 1338 error_setg(errp, "hotplug of virtio based memory devices not supported"
1339 " on this bus.");
a0a49813
DH		 1340 return;
1341 }
1342 /*
1343 * First, see if we can plug this memory device at all. If that
1344 * succeeds, branch of to the actual hotplug handler.
1345 */
1346 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1347 &local_err);
af1d039f 1348 if (!local_err && hotplug_dev2) {
a0a49813
DH		 1349 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1350 }
1351 error_propagate(errp, local_err);
1352}
1353
0ed48fd3
DH		 1354static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1355 DeviceState *dev, Error **errp)
a0a49813
DH		 1356{
1357 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1358 Error *local_err = NULL;
1359
1360 /*
1361 * Plug the memory device first and then branch off to the actual
1362 * hotplug handler. If that one fails, we can easily undo the memory
1363 * device bits.
1364 */
1365 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
af1d039f
DH		 1366 if (hotplug_dev2) {
1367 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1368 if (local_err) {
1369 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1370 }
a0a49813
DH		 1371 }
1372 error_propagate(errp, local_err);
1373}
1374
0ed48fd3
DH		 1375static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1376 DeviceState *dev, Error **errp)
a0a49813 1377{
0ed48fd3
DH		 1378 /* We don't support hot unplug of virtio based memory devices */
1379 error_setg(errp, "virtio based memory devices cannot be unplugged.");
a0a49813
DH		 1380}
1381
0ed48fd3
DH		 1382static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1383 DeviceState *dev, Error **errp)
a0a49813 1384{
0ed48fd3 1385 /* We don't support hot unplug of virtio based memory devices */
a0a49813
DH		 1386}
1387
4ec60c76
IM		 1388static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1389 DeviceState *dev, Error **errp)
1390{
d468115b
DH		 1391 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1392 pc_memory_pre_plug(hotplug_dev, dev, errp);
1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1394 x86_cpu_pre_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1396 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1397 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
36efa250
JPB		 1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1399 /* Declare the APIC range as the reserved MSI region */
1400 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1401 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1402
1403 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1404 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1405 resv_prop_str, errp);
1406 g_free(resv_prop_str);
1407 }
1408
1409 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1410 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1b3bf138
JPB		 1411 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1412
1413 if (pcms->iommu) {
1414 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1415 "for x86 yet.");
1416 return;
1417 }
1418 pcms->iommu = dev;
4ec60c76
IM		 1419 }
1420}
1421
95bee274
IM		 1422static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1423 DeviceState *dev, Error **errp)
1424{
1425 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1426 pc_memory_plug(hotplug_dev, dev, errp);
5279569e 1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1428 x86_cpu_plug(hotplug_dev, dev, errp);
0ed48fd3
DH		 1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1430 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1431 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
95bee274
IM		 1432 }
1433}
1434
d9c5c5b8
TC		 1435static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1436 DeviceState *dev, Error **errp)
1437{
64fec58e 1438 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1439 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1441 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1443 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1444 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
64fec58e
TC		 1445 } else {
1446 error_setg(errp, "acpi: device unplug request for not supported device"
1447 " type: %s", object_get_typename(OBJECT(dev)));
1448 }
d9c5c5b8
TC		 1449}
1450
232391c1
TC		 1451static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1452 DeviceState *dev, Error **errp)
1453{
f7d3e29d 1454 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 1455 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
0cca1a91 1457 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
0ed48fd3
DH		 1458 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1459 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1460 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
f7d3e29d
TC		 1461 } else {
1462 error_setg(errp, "acpi: device unplug for not supported device"
1463 " type: %s", object_get_typename(OBJECT(dev)));
1464 }
232391c1
TC		 1465}
1466
285816d7 1467static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 1468 DeviceState *dev)
1469{
5279569e 1470 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
a0a49813 1471 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
0ed48fd3 1472 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1b3bf138 1473 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
36efa250 1474 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1b3bf138 1475 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
95bee274
IM		 1476 return HOTPLUG_HANDLER(machine);
1477 }
1478
38aefb57 1479 return NULL;
95bee274
IM		 1480}
1481
bf1e8939 1482static void
f2ffbe2b
DH		 1483pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1484 const char *name, void *opaque,
1485 Error **errp)
bf1e8939 1486{
b0c14ec4 1487 MachineState *ms = MACHINE(obj);
fc3b77e2
IM		 1488 int64_t value = 0;
1489
1490 if (ms->device_memory) {
1491 value = memory_region_size(&ms->device_memory->mr);
1492 }
bf1e8939 1493
51e72bc1 1494 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 1495}
1496
d7bce999
EB		 1497static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1498 void *opaque, Error **errp)
9b23cfb7
DDAG		 1499{
1500 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 1501 OnOffAuto vmport = pcms->vmport;
9b23cfb7 1502
51e72bc1 1503 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 1504}
1505
d7bce999
EB		 1506static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1507 void *opaque, Error **errp)
9b23cfb7
DDAG		 1508{
1509 PCMachineState *pcms = PC_MACHINE(obj);
1510
51e72bc1 1511 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 1512}
1513
be232eb0
CP		 1514static bool pc_machine_get_smbus(Object *obj, Error **errp)
1515{
1516 PCMachineState *pcms = PC_MACHINE(obj);
1517
f5878b03 1518 return pcms->smbus_enabled;
be232eb0
CP		 1519}
1520
1521static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1522{
1523 PCMachineState *pcms = PC_MACHINE(obj);
1524
f5878b03 1525 pcms->smbus_enabled = value;
be232eb0
CP		 1526}
1527
272f0428
CP		 1528static bool pc_machine_get_sata(Object *obj, Error **errp)
1529{
1530 PCMachineState *pcms = PC_MACHINE(obj);
1531
f5878b03 1532 return pcms->sata_enabled;
272f0428
CP		 1533}
1534
1535static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1536{
1537 PCMachineState *pcms = PC_MACHINE(obj);
1538
f5878b03 1539 pcms->sata_enabled = value;
272f0428
CP		 1540}
1541
0259c78c
EH		 1542static bool pc_machine_get_hpet(Object *obj, Error **errp)
1543{
1544 PCMachineState *pcms = PC_MACHINE(obj);
1545
1546 return pcms->hpet_enabled;
1547}
1548
1549static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1550{
1551 PCMachineState *pcms = PC_MACHINE(obj);
1552
1553 pcms->hpet_enabled = value;
1554}
1555
4ccd5fe2
JD		 1556static bool pc_machine_get_i8042(Object *obj, Error **errp)
1557{
1558 PCMachineState *pcms = PC_MACHINE(obj);
1559
1560 return pcms->i8042_enabled;
1561}
1562
1563static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1564{
1565 PCMachineState *pcms = PC_MACHINE(obj);
1566
1567 pcms->i8042_enabled = value;
1568}
1569
c9e96b04
XW		 1570static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1571{
1572 PCMachineState *pcms = PC_MACHINE(obj);
1573
1574 return pcms->default_bus_bypass_iommu;
1575}
1576
1577static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1578 Error **errp)
1579{
1580 PCMachineState *pcms = PC_MACHINE(obj);
1581
1582 pcms->default_bus_bypass_iommu = value;
1583}
1584
0e4edb3b
EH		 1585static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1586 void *opaque, Error **errp)
1587{
1588 PCMachineState *pcms = PC_MACHINE(obj);
1589 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1590
1591 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1592}
1593
1594static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1595 void *opaque, Error **errp)
1596{
1597 PCMachineState *pcms = PC_MACHINE(obj);
1598
1599 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1600}
1601
9a45729d
GH		 1602static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1603 const char *name, void *opaque,
1604 Error **errp)
1605{
1606 PCMachineState *pcms = PC_MACHINE(obj);
1607 uint64_t value = pcms->max_ram_below_4g;
1608
1609 visit_type_size(v, name, &value, errp);
1610}
1611
1612static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1613 const char *name, void *opaque,
1614 Error **errp)
1615{
1616 PCMachineState *pcms = PC_MACHINE(obj);
9a45729d
GH		 1617 uint64_t value;
1618
668f62ec 1619 if (!visit_type_size(v, name, &value, errp)) {
9a45729d
GH		 1620 return;
1621 }
1622 if (value > 4 * GiB) {
dcfe4805 1623 error_setg(errp,
9a45729d
GH		 1624 "Machine option 'max-ram-below-4g=%"PRIu64
1625 "' expects size less than or equal to 4G", value);
9a45729d
GH		 1626 return;
1627 }
1628
1629 if (value < 1 * MiB) {
1630 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1631 "BIOS may not work with less than 1MiB", value);
1632 }
1633
1634 pcms->max_ram_below_4g = value;
1635}
1636
0657c657
EM		 1637static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1638 const char *name, void *opaque,
1639 Error **errp)
1640{
1641 PCMachineState *pcms = PC_MACHINE(obj);
1642 uint64_t value = pcms->max_fw_size;
1643
1644 visit_type_size(v, name, &value, errp);
1645}
1646
1647static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1648 const char *name, void *opaque,
1649 Error **errp)
1650{
1651 PCMachineState *pcms = PC_MACHINE(obj);
1652 Error *error = NULL;
1653 uint64_t value;
1654
1655 visit_type_size(v, name, &value, &error);
1656 if (error) {
1657 error_propagate(errp, error);
1658 return;
1659 }
1660
1661 /*
1662 * We don't have a theoretically justifiable exact lower bound on the base
1663 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1664 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1665 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1666 * size.
1667 */
1668 if (value > 16 * MiB) {
1669 error_setg(errp,
1670 "User specified max allowed firmware size %" PRIu64 " is "
1671 "greater than 16MiB. If combined firwmare size exceeds "
1672 "16MiB the system may not boot, or experience intermittent"
1673 "stability issues.",
1674 value);
1675 return;
1676 }
1677
1678 pcms->max_fw_size = value;
1679}
1680
602b4582 1681
bf1e8939
IM		 1682static void pc_machine_initfn(Object *obj)
1683{
c87b1520
DS		 1684 PCMachineState *pcms = PC_MACHINE(obj);
1685
97fd1ea8 1686#ifdef CONFIG_VMPORT
d1048bef 1687 pcms->vmport = ON_OFF_AUTO_AUTO;
97fd1ea8
JM		 1688#else
1689 pcms->vmport = ON_OFF_AUTO_OFF;
1690#endif /* CONFIG_VMPORT */
9a45729d 1691 pcms->max_ram_below_4g = 0; /* use default */
0e4edb3b
EH		 1692 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1693
021746c1
WL		 1694 /* acpi build is enabled by default if machine supports it */
1695 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 1696 pcms->smbus_enabled = true;
1697 pcms->sata_enabled = true;
4ccd5fe2 1698 pcms->i8042_enabled = true;
0657c657 1699 pcms->max_fw_size = 8 * MiB;
0259c78c
EH		 1700#ifdef CONFIG_HPET
1701 pcms->hpet_enabled = true;
1702#endif
c9e96b04 1703 pcms->default_bus_bypass_iommu = false;
ebc29e1b
MA		 1704
1705 pc_system_flash_create(pcms);
6b8d1416 1706 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
2e16ec05
GH		 1707 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1708 OBJECT(pcms->pcspk), "audiodev");
bf1e8939
IM		 1709}
1710
a0628599 1711static void pc_machine_reset(MachineState *machine)
ae50c55a
ZG		 1712{
1713 CPUState *cs;
1714 X86CPU *cpu;
1715
1716 qemu_devices_reset();
1717
1718 /* Reset APIC after devices have been reset to cancel
1719 * any changes that qemu_devices_reset() might have done.
1720 */
1721 CPU_FOREACH(cs) {
1722 cpu = X86_CPU(cs);
1723
1724 if (cpu->apic_state) {
f703a04c 1725 device_legacy_reset(cpu->apic_state);
ae50c55a
ZG		 1726 }
1727 }
1728}
1729
c508bd12
NP		 1730static void pc_machine_wakeup(MachineState *machine)
1731{
1732 cpu_synchronize_all_states();
1733 pc_machine_reset(machine);
1734 cpu_synchronize_all_post_reset();
1735}
1736
c6cbc29d
PX		 1737static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1738{
1739 X86IOMMUState *iommu = x86_iommu_get_default();
1740 IntelIOMMUState *intel_iommu;
1741
1742 if (iommu &&
1743 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1744 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1745 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1746 if (!intel_iommu->caching_mode) {
1747 error_setg(errp, "Device assignment is not allowed without "
1748 "enabling caching-mode=on for Intel IOMMU.");
1749 return false;
1750 }
1751 }
1752
1753 return true;
1754}
1755
95bee274
IM		 1756static void pc_machine_class_init(ObjectClass *oc, void *data)
1757{
1758 MachineClass *mc = MACHINE_CLASS(oc);
1759 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1760 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1761
7102fa70
EH		 1762 pcmc->pci_enabled = true;
1763 pcmc->has_acpi_build = true;
1764 pcmc->rsdp_in_ram = true;
1765 pcmc->smbios_defaults = true;
1766 pcmc->smbios_uuid_encoded = true;
1767 pcmc->gigabyte_align = true;
1768 pcmc->has_reserved_memory = true;
1769 pcmc->kvmclock_enabled = true;
16a9e8a5 1770 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 1771 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1772 * to be used at the moment, 32K should be enough for a while. */
1773 pcmc->acpi_data_size = 0x20000 + 0x8000;
fda672b5 1774 pcmc->pvh_enabled = true;
8700a984 1775 pcmc->kvmclock_create_always = true;
debbdc00 1776 assert(!mc->get_hotplug_handler);
285816d7 1777 mc->get_hotplug_handler = pc_get_hotplug_handler;
c6cbc29d 1778 mc->hotplug_allowed = pc_hotplug_allowed;
81ef68e4
SL		 1779 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1780 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1781 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
7b8be49d 1782 mc->auto_enable_numa_with_memhp = true;
195784a0 1783 mc->auto_enable_numa_with_memdev = true;
c5514d0e 1784 mc->has_hotpluggable_cpus = true;
41742767 1785 mc->default_boot_order = "cad";
2059839b 1786 mc->block_default_type = IF_IDE;
4458fb3a 1787 mc->max_cpus = 255;
ae50c55a 1788 mc->reset = pc_machine_reset;
c508bd12 1789 mc->wakeup = pc_machine_wakeup;
4ec60c76 1790 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 1791 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 1792 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 1793 hc->unplug = pc_machine_device_unplug_cb;
311ca98d 1794 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 1795 mc->nvdimm_supported = true;
e4a97a89 1796 mc->smp_props.dies_supported = true;
abb3009b 1797 mc->cxl_supported = true;
bd457782 1798 mc->default_ram_id = "pc.ram";
0efc257d 1799
9a45729d
GH		 1800 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1801 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1802 NULL, NULL);
1803 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1804 "Maximum ram below the 4G boundary (32bit boundary)");
1805
f2ffbe2b
DH		 1806 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1807 pc_machine_get_device_memory_region_size, NULL,
d2623129 1808 NULL, NULL);
0efc257d 1809
0efc257d
EH		 1810 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1811 pc_machine_get_vmport, pc_machine_set_vmport,
d2623129 1812 NULL, NULL);
0efc257d 1813 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
7eecec7d 1814 "Enable vmport (pc & q35)");
0efc257d 1815
be232eb0 1816 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
d2623129 1817 pc_machine_get_smbus, pc_machine_set_smbus);
44bff376
TH		 1818 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1819 "Enable/disable system management bus");
272f0428
CP		 1820
1821 object_class_property_add_bool(oc, PC_MACHINE_SATA,
d2623129 1822 pc_machine_get_sata, pc_machine_set_sata);
44bff376
TH		 1823 object_class_property_set_description(oc, PC_MACHINE_SATA,
1824 "Enable/disable Serial ATA bus");
feddd2fd 1825
0259c78c
EH		 1826 object_class_property_add_bool(oc, "hpet",
1827 pc_machine_get_hpet, pc_machine_set_hpet);
44bff376
TH		 1828 object_class_property_set_description(oc, "hpet",
1829 "Enable/disable high precision event timer emulation");
0657c657 1830
4ccd5fe2
JD		 1831 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1832 pc_machine_get_i8042, pc_machine_set_i8042);
1833
739b3863 1834 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
c9e96b04
XW		 1835 pc_machine_get_default_bus_bypass_iommu,
1836 pc_machine_set_default_bus_bypass_iommu);
1837
0657c657
EM		 1838 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1839 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1840 NULL, NULL);
1841 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1842 "Maximum combined firmware size");
0e4edb3b
EH		 1843
1844 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1845 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1846 NULL, NULL);
1847 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1848 "SMBIOS Entry Point type [32, 64]");
95bee274
IM		 1849}
1850
d5747cac
IM		 1851static const TypeInfo pc_machine_info = {
1852 .name = TYPE_PC_MACHINE,
f0bb276b 1853 .parent = TYPE_X86_MACHINE,
d5747cac
IM		 1854 .abstract = true,
1855 .instance_size = sizeof(PCMachineState),
bf1e8939 1856 .instance_init = pc_machine_initfn,
d5747cac 1857 .class_size = sizeof(PCMachineClass),
95bee274
IM		 1858 .class_init = pc_machine_class_init,
1859 .interfaces = (InterfaceInfo[]) {
1860 { TYPE_HOTPLUG_HANDLER },
1861 { }
1862 },
d5747cac
IM		 1863};
1864
1865static void pc_machine_register_types(void)
1866{
1867 type_register_static(&pc_machine_info);
1868}
1869
1870type_init(pc_machine_register_types)
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