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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
549e984e | 27 | #include "hw/i386/x86.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 | 32 | #include "hw/i386/topology.h" |
87abaa5d | 33 | #include "hw/i386/fw_cfg.h" |
54a40293 | 34 | #include "sysemu/cpus.h" |
0d09e41a | 35 | #include "hw/block/fdc.h" |
83c9f4ca PB |
36 | #include "hw/ide.h" |
37 | #include "hw/pci/pci.h" | |
2118196b | 38 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
39 | #include "hw/nvram/fw_cfg.h" |
40 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 41 | #include "hw/firmware/smbios.h" |
83c9f4ca | 42 | #include "hw/loader.h" |
ca20cf32 | 43 | #include "elf.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
47b43a1f | 45 | #include "multiboot.h" |
bcdb9064 | 46 | #include "hw/rtc/mc146818rtc.h" |
852c27e2 | 47 | #include "hw/intc/i8259.h" |
55f613ac | 48 | #include "hw/dma/i8257.h" |
0d09e41a | 49 | #include "hw/timer/i8254.h" |
47973a2d | 50 | #include "hw/input/i8042.h" |
64552b6b | 51 | #include "hw/irq.h" |
0d09e41a | 52 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
53 | #include "hw/pci/msi.h" |
54 | #include "hw/sysbus.h" | |
9c17d615 | 55 | #include "sysemu/sysemu.h" |
14a48c1d | 56 | #include "sysemu/tcg.h" |
e35704ba | 57 | #include "sysemu/numa.h" |
9c17d615 | 58 | #include "sysemu/kvm.h" |
b1c12027 | 59 | #include "sysemu/qtest.h" |
71e8a915 | 60 | #include "sysemu/reset.h" |
54d31236 | 61 | #include "sysemu/runstate.h" |
1d31f66b | 62 | #include "kvm_i386.h" |
0d09e41a | 63 | #include "hw/xen/xen.h" |
ab969087 | 64 | #include "hw/xen/start_info.h" |
a19cbfb3 | 65 | #include "ui/qemu-spice.h" |
022c62cb PB |
66 | #include "exec/memory.h" |
67 | #include "exec/address-spaces.h" | |
9c17d615 | 68 | #include "sysemu/arch_init.h" |
1de7afc9 | 69 | #include "qemu/bitmap.h" |
0c764a9d | 70 | #include "qemu/config-file.h" |
d49b6836 | 71 | #include "qemu/error-report.h" |
922a01a0 | 72 | #include "qemu/option.h" |
133ef074 | 73 | #include "qemu/cutils.h" |
0445259b | 74 | #include "hw/acpi/acpi.h" |
5ff020b7 | 75 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 76 | #include "hw/boards.h" |
72c194f7 | 77 | #include "acpi-build.h" |
95bee274 | 78 | #include "hw/mem/pc-dimm.h" |
e688df6b | 79 | #include "qapi/error.h" |
9af23989 | 80 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 81 | #include "qapi/visitor.h" |
2e5b09fd | 82 | #include "hw/core/cpu.h" |
a310e653 | 83 | #include "hw/usb.h" |
60c5e104 | 84 | #include "hw/i386/intel_iommu.h" |
489983d6 | 85 | #include "hw/net/ne2000-isa.h" |
06e0259a | 86 | #include "standard-headers/asm-x86/bootparam.h" |
a0a49813 DH |
87 | #include "hw/virtio/virtio-pmem-pci.h" |
88 | #include "hw/mem/memory-device.h" | |
6f479566 LX |
89 | #include "sysemu/replay.h" |
90 | #include "qapi/qmp/qerror.h" | |
97fd1ea8 | 91 | #include "config-devices.h" |
d6d059ca | 92 | #include "e820_memory_layout.h" |
149c50ca | 93 | #include "fw_cfg.h" |
80cabfad | 94 | |
471fd342 BS |
95 | /* debug PC/ISA interrupts */ |
96 | //#define DEBUG_IRQ | |
97 | ||
98 | #ifdef DEBUG_IRQ | |
99 | #define DPRINTF(fmt, ...) \ | |
100 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
101 | #else | |
102 | #define DPRINTF(fmt, ...) | |
103 | #endif | |
104 | ||
3eb74d20 CH |
105 | GlobalProperty pc_compat_4_2[] = {}; |
106 | const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); | |
107 | ||
9aec2e52 CH |
108 | GlobalProperty pc_compat_4_1[] = {}; |
109 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
110 | ||
9bf2650b CH |
111 | GlobalProperty pc_compat_4_0[] = {}; |
112 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
113 | ||
abd93cc7 | 114 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 115 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
116 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
117 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
118 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
119 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 120 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
121 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
122 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
123 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
124 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
125 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
126 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
127 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
128 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
129 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
130 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
131 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
132 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
133 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 134 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 135 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
136 | }; |
137 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
138 | ||
ddb3235d | 139 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
140 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
141 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
142 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
143 | }; |
144 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
145 | ||
0d47310b | 146 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
147 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
148 | { TYPE_X86_CPU, "topoext", "off" }, | |
149 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
150 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
151 | }; |
152 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
153 | ||
43df70a9 | 154 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
155 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
156 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
157 | }; |
158 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
159 | ||
503224f4 | 160 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
161 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
162 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
163 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
164 | }; |
165 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
166 | ||
3e803152 | 167 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 168 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
169 | }; |
170 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
171 | ||
edc24ccd | 172 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
173 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
174 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
175 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
176 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
177 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
178 | }; |
179 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
180 | ||
5a995064 | 181 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
182 | { TYPE_X86_CPU, "l3-cache", "off" }, |
183 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
184 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
185 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
186 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
187 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
188 | }; |
189 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
190 | ||
ff8f261f | 191 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
192 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
193 | { "vmxnet3", "romfile", "" }, | |
194 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
195 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
196 | }; |
197 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
198 | ||
fe759610 MAL |
199 | GlobalProperty pc_compat_2_5[] = {}; |
200 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
201 | ||
2f99b9c2 MAL |
202 | GlobalProperty pc_compat_2_4[] = { |
203 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
204 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
205 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
206 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
207 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
208 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
209 | { TYPE_X86_CPU, "check", "off" }, | |
210 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
211 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
212 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
213 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
214 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
215 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
216 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
217 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
218 | }; |
219 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
220 | ||
8995dd90 MAL |
221 | GlobalProperty pc_compat_2_3[] = { |
222 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
223 | { TYPE_X86_CPU, "arat", "off" }, |
224 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
225 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
226 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
227 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
228 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
229 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
230 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
231 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
232 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
233 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
234 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
235 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
236 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
237 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
238 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
239 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
240 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
241 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
242 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
243 | }; |
244 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
245 | ||
1c30044e MAL |
246 | GlobalProperty pc_compat_2_2[] = { |
247 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
248 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
249 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
250 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
251 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
252 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
253 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
254 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
255 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
256 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
257 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
258 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
259 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
260 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
261 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
262 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
263 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
264 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
265 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
266 | }; |
267 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
268 | ||
c4fc5695 MAL |
269 | GlobalProperty pc_compat_2_1[] = { |
270 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
271 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
272 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
273 | }; |
274 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
275 | ||
a310e653 MAL |
276 | GlobalProperty pc_compat_2_0[] = { |
277 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
278 | { "virtio-scsi-pci", "any_layout", "off" }, |
279 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
280 | { "apic", "version", "0x11" }, | |
281 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
282 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
283 | { "pci-serial", "prog_if", "0" }, | |
284 | { "pci-serial-2x", "prog_if", "0" }, | |
285 | { "pci-serial-4x", "prog_if", "0" }, | |
286 | { "virtio-net-pci", "guest_announce", "off" }, | |
287 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
288 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
289 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
a310e653 MAL |
290 | }; |
291 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
292 | ||
293 | GlobalProperty pc_compat_1_7[] = { | |
294 | PC_CPU_MODEL_IDS("1.7.0") | |
6c36bddf EH |
295 | { TYPE_USB_DEVICE, "msos-desc", "no" }, |
296 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
297 | { "hpet", HPET_INTCAP, "4" }, | |
a310e653 MAL |
298 | }; |
299 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
300 | ||
301 | GlobalProperty pc_compat_1_6[] = { | |
302 | PC_CPU_MODEL_IDS("1.6.0") | |
6c36bddf EH |
303 | { "e1000", "mitigation", "off" }, |
304 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
305 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
306 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
307 | { "q35-pcihost", "short_root_bus", "1" }, | |
a310e653 MAL |
308 | }; |
309 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
310 | ||
311 | GlobalProperty pc_compat_1_5[] = { | |
312 | PC_CPU_MODEL_IDS("1.5.0") | |
6c36bddf EH |
313 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, |
314 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
315 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
316 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
317 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
318 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
319 | { "virtio-net-pci", "any_layout", "off" }, | |
320 | { TYPE_X86_CPU, "pmu", "on" }, | |
321 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
322 | { "q35-pcihost", "short_root_bus", "0" }, | |
a310e653 MAL |
323 | }; |
324 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
325 | ||
326 | GlobalProperty pc_compat_1_4[] = { | |
327 | PC_CPU_MODEL_IDS("1.4.0") | |
6c36bddf EH |
328 | { "scsi-hd", "discard_granularity", "0" }, |
329 | { "scsi-cd", "discard_granularity", "0" }, | |
330 | { "scsi-disk", "discard_granularity", "0" }, | |
331 | { "ide-hd", "discard_granularity", "0" }, | |
332 | { "ide-cd", "discard_granularity", "0" }, | |
333 | { "ide-drive", "discard_granularity", "0" }, | |
334 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
335 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
336 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
337 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
338 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
339 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
340 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
341 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
342 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
343 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
344 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
345 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
a310e653 MAL |
346 | }; |
347 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
348 | ||
b881fbe9 | 349 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 350 | { |
b881fbe9 | 351 | GSIState *s = opaque; |
1452411b | 352 | |
b881fbe9 JK |
353 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
354 | if (n < ISA_NUM_IRQS) { | |
355 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 356 | } |
b881fbe9 | 357 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 358 | } |
1452411b | 359 | |
417258f1 PMD |
360 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
361 | { | |
362 | GSIState *s; | |
363 | ||
364 | s = g_new0(GSIState, 1); | |
365 | if (kvm_ioapic_in_kernel()) { | |
366 | kvm_pc_setup_irq_routing(pci_enabled); | |
367 | *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS); | |
368 | } else { | |
369 | *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); | |
370 | } | |
371 | ||
372 | return s; | |
373 | } | |
374 | ||
258711c6 JG |
375 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
376 | unsigned size) | |
80cabfad FB |
377 | { |
378 | } | |
379 | ||
c02e1eac JG |
380 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
381 | { | |
a6fc23e5 | 382 | return 0xffffffffffffffffULL; |
c02e1eac JG |
383 | } |
384 | ||
f929aad6 | 385 | /* MSDOS compatibility mode FPU exception support */ |
258711c6 JG |
386 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
387 | unsigned size) | |
f929aad6 | 388 | { |
6f529b75 | 389 | if (tcg_enabled()) { |
bf13bfab | 390 | cpu_set_ignne(); |
6f529b75 | 391 | } |
f929aad6 FB |
392 | } |
393 | ||
c02e1eac JG |
394 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
395 | { | |
a6fc23e5 | 396 | return 0xffffffffffffffffULL; |
c02e1eac JG |
397 | } |
398 | ||
28ab0e2e | 399 | /* TSC handling */ |
28ab0e2e FB |
400 | uint64_t cpu_get_tsc(CPUX86State *env) |
401 | { | |
4a1418e0 | 402 | return cpu_get_ticks(); |
28ab0e2e FB |
403 | } |
404 | ||
3de388f6 | 405 | /* IRQ handling */ |
4a8fa5dc | 406 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 407 | { |
6aa9e42f | 408 | X86CPU *cpu = env_archcpu(env); |
3de388f6 FB |
409 | int intno; |
410 | ||
bb93e099 WL |
411 | if (!kvm_irqchip_in_kernel()) { |
412 | intno = apic_get_interrupt(cpu->apic_state); | |
413 | if (intno >= 0) { | |
414 | return intno; | |
415 | } | |
416 | /* read the irq from the PIC */ | |
417 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
418 | return -1; | |
419 | } | |
cf6d64bf | 420 | } |
0e21e12b | 421 | |
3de388f6 FB |
422 | intno = pic_read_irq(isa_pic); |
423 | return intno; | |
424 | } | |
425 | ||
d537cf6c | 426 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 427 | { |
182735ef AF |
428 | CPUState *cs = first_cpu; |
429 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 430 | |
471fd342 | 431 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 432 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 433 | CPU_FOREACH(cs) { |
182735ef | 434 | cpu = X86_CPU(cs); |
02e51483 CF |
435 | if (apic_accept_pic_intr(cpu->apic_state)) { |
436 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 437 | } |
d5529471 AJ |
438 | } |
439 | } else { | |
d8ed887b | 440 | if (level) { |
c3affe56 | 441 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
442 | } else { |
443 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
444 | } | |
a5b38b51 | 445 | } |
3de388f6 FB |
446 | } |
447 | ||
b0a21b53 FB |
448 | /* PC cmos mappings */ |
449 | ||
80cabfad FB |
450 | #define REG_EQUIPMENT_BYTE 0x14 |
451 | ||
bda05509 | 452 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
453 | { |
454 | int val; | |
455 | ||
456 | switch (fd0) { | |
2da44dd0 | 457 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
458 | /* 1.44 Mb 3"5 drive */ |
459 | val = 4; | |
460 | break; | |
2da44dd0 | 461 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
462 | /* 2.88 Mb 3"5 drive */ |
463 | val = 5; | |
464 | break; | |
2da44dd0 | 465 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
466 | /* 1.2 Mb 5"5 drive */ |
467 | val = 2; | |
468 | break; | |
2da44dd0 | 469 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
470 | default: |
471 | val = 0; | |
472 | break; | |
473 | } | |
474 | return val; | |
475 | } | |
476 | ||
9139046c MA |
477 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
478 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 479 | { |
ba6c2377 FB |
480 | rtc_set_memory(s, type_ofs, 47); |
481 | rtc_set_memory(s, info_ofs, cylinders); | |
482 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
483 | rtc_set_memory(s, info_ofs + 2, heads); | |
484 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
485 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
486 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
487 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
488 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
489 | rtc_set_memory(s, info_ofs + 8, sectors); | |
490 | } | |
491 | ||
6ac0e82d AZ |
492 | /* convert boot_device letter to something recognizable by the bios */ |
493 | static int boot_device2nibble(char boot_device) | |
494 | { | |
495 | switch(boot_device) { | |
496 | case 'a': | |
497 | case 'b': | |
498 | return 0x01; /* floppy boot */ | |
499 | case 'c': | |
500 | return 0x02; /* hard drive boot */ | |
501 | case 'd': | |
502 | return 0x03; /* CD-ROM boot */ | |
503 | case 'n': | |
504 | return 0x04; /* Network boot */ | |
505 | } | |
506 | return 0; | |
507 | } | |
508 | ||
ddcd5531 | 509 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
510 | { |
511 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
512 | int nbds, bds[3] = { 0, }; |
513 | int i; | |
514 | ||
515 | nbds = strlen(boot_device); | |
516 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
517 | error_setg(errp, "Too many boot devices for PC"); |
518 | return; | |
0ecdffbb AJ |
519 | } |
520 | for (i = 0; i < nbds; i++) { | |
521 | bds[i] = boot_device2nibble(boot_device[i]); | |
522 | if (bds[i] == 0) { | |
ddcd5531 GA |
523 | error_setg(errp, "Invalid boot device for PC: '%c'", |
524 | boot_device[i]); | |
525 | return; | |
0ecdffbb AJ |
526 | } |
527 | } | |
528 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 529 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
530 | } |
531 | ||
ddcd5531 | 532 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 533 | { |
ddcd5531 | 534 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
535 | } |
536 | ||
7444ca4e LE |
537 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
538 | { | |
539 | int val, nb, i; | |
2da44dd0 JS |
540 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
541 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
542 | |
543 | /* floppy type */ | |
544 | if (floppy) { | |
545 | for (i = 0; i < 2; i++) { | |
546 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
547 | } | |
548 | } | |
549 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
550 | cmos_get_fd_drive_type(fd_type[1]); | |
551 | rtc_set_memory(rtc_state, 0x10, val); | |
552 | ||
553 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
554 | nb = 0; | |
2da44dd0 | 555 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
556 | nb++; |
557 | } | |
2da44dd0 | 558 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
559 | nb++; |
560 | } | |
561 | switch (nb) { | |
562 | case 0: | |
563 | break; | |
564 | case 1: | |
565 | val |= 0x01; /* 1 drive, ready for boot */ | |
566 | break; | |
567 | case 2: | |
568 | val |= 0x41; /* 2 drives, ready for boot */ | |
569 | break; | |
570 | } | |
571 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
572 | } | |
573 | ||
c0897e0c MA |
574 | typedef struct pc_cmos_init_late_arg { |
575 | ISADevice *rtc_state; | |
9139046c | 576 | BusState *idebus[2]; |
c0897e0c MA |
577 | } pc_cmos_init_late_arg; |
578 | ||
b86f4613 LE |
579 | typedef struct check_fdc_state { |
580 | ISADevice *floppy; | |
581 | bool multiple; | |
582 | } CheckFdcState; | |
583 | ||
584 | static int check_fdc(Object *obj, void *opaque) | |
585 | { | |
586 | CheckFdcState *state = opaque; | |
587 | Object *fdc; | |
588 | uint32_t iobase; | |
589 | Error *local_err = NULL; | |
590 | ||
591 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
592 | if (!fdc) { | |
593 | return 0; | |
594 | } | |
595 | ||
1ea1572a | 596 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
597 | if (local_err || iobase != 0x3f0) { |
598 | error_free(local_err); | |
599 | return 0; | |
600 | } | |
601 | ||
602 | if (state->floppy) { | |
603 | state->multiple = true; | |
604 | } else { | |
605 | state->floppy = ISA_DEVICE(obj); | |
606 | } | |
607 | return 0; | |
608 | } | |
609 | ||
610 | static const char * const fdc_container_path[] = { | |
611 | "/unattached", "/peripheral", "/peripheral-anon" | |
612 | }; | |
613 | ||
424e4a87 RK |
614 | /* |
615 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
616 | * and ACPI objects. | |
617 | */ | |
618 | ISADevice *pc_find_fdc0(void) | |
619 | { | |
620 | int i; | |
621 | Object *container; | |
622 | CheckFdcState state = { 0 }; | |
623 | ||
624 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
625 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
626 | object_child_foreach(container, check_fdc, &state); | |
627 | } | |
628 | ||
629 | if (state.multiple) { | |
3dc6f869 AF |
630 | warn_report("multiple floppy disk controllers with " |
631 | "iobase=0x3f0 have been found"); | |
433672b0 | 632 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 633 | "your intent"); |
424e4a87 RK |
634 | } |
635 | ||
636 | return state.floppy; | |
637 | } | |
638 | ||
c0897e0c MA |
639 | static void pc_cmos_init_late(void *opaque) |
640 | { | |
641 | pc_cmos_init_late_arg *arg = opaque; | |
642 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
643 | int16_t cylinders; |
644 | int8_t heads, sectors; | |
c0897e0c | 645 | int val; |
2adc99b2 | 646 | int i, trans; |
c0897e0c | 647 | |
9139046c | 648 | val = 0; |
272f0428 CP |
649 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
650 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
651 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
652 | val |= 0xf0; | |
653 | } | |
272f0428 CP |
654 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
655 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
656 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
657 | val |= 0x0f; | |
658 | } | |
659 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
660 | |
661 | val = 0; | |
662 | for (i = 0; i < 4; i++) { | |
9139046c MA |
663 | /* NOTE: ide_get_geometry() returns the physical |
664 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
665 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
666 | geometry can be different if a translation is done. */ | |
272f0428 CP |
667 | if (arg->idebus[i / 2] && |
668 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 669 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
670 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
671 | assert((trans & ~3) == 0); | |
672 | val |= trans << (i * 2); | |
c0897e0c MA |
673 | } |
674 | } | |
675 | rtc_set_memory(s, 0x39, val); | |
676 | ||
424e4a87 | 677 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 678 | |
c0897e0c MA |
679 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
680 | } | |
681 | ||
23d30407 | 682 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 683 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 684 | ISADevice *s) |
80cabfad | 685 | { |
7444ca4e | 686 | int val; |
c0897e0c | 687 | static pc_cmos_init_late_arg arg; |
f0bb276b | 688 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b0a21b53 | 689 | |
b0a21b53 | 690 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
691 | |
692 | /* memory size */ | |
e89001f7 | 693 | /* base memory (first MiB) */ |
f0bb276b | 694 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
333190eb FB |
695 | rtc_set_memory(s, 0x15, val); |
696 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 697 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
698 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
699 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
700 | } else { |
701 | val = 0; | |
702 | } | |
80cabfad FB |
703 | if (val > 65535) |
704 | val = 65535; | |
b0a21b53 FB |
705 | rtc_set_memory(s, 0x17, val); |
706 | rtc_set_memory(s, 0x18, val >> 8); | |
707 | rtc_set_memory(s, 0x30, val); | |
708 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 709 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
710 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
711 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 712 | } else { |
9da98861 | 713 | val = 0; |
e89001f7 | 714 | } |
80cabfad FB |
715 | if (val > 65535) |
716 | val = 65535; | |
b0a21b53 FB |
717 | rtc_set_memory(s, 0x34, val); |
718 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 719 | /* memory above 4GiB */ |
f0bb276b | 720 | val = x86ms->above_4g_mem_size / 65536; |
e89001f7 MA |
721 | rtc_set_memory(s, 0x5b, val); |
722 | rtc_set_memory(s, 0x5c, val >> 8); | |
723 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 724 | |
23d30407 | 725 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 726 | TYPE_ISA_DEVICE, |
f0bb276b | 727 | (Object **)&x86ms->rtc, |
2d996150 | 728 | object_property_allow_set_link, |
265b578c | 729 | OBJ_PROP_LINK_STRONG, &error_abort); |
23d30407 | 730 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 731 | "rtc_state", &error_abort); |
298e01b6 | 732 | |
007b0657 | 733 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 734 | |
b0a21b53 | 735 | val = 0; |
b0a21b53 FB |
736 | val |= 0x02; /* FPU is there */ |
737 | val |= 0x04; /* PS/2 mouse installed */ | |
738 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
739 | ||
b86f4613 | 740 | /* hard drives and FDC */ |
c0897e0c | 741 | arg.rtc_state = s; |
9139046c MA |
742 | arg.idebus[0] = idebus0; |
743 | arg.idebus[1] = idebus1; | |
c0897e0c | 744 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
745 | } |
746 | ||
a0881c64 AF |
747 | #define TYPE_PORT92 "port92" |
748 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
749 | ||
4b78a802 BS |
750 | /* port 92 stuff: could be split off */ |
751 | typedef struct Port92State { | |
a0881c64 AF |
752 | ISADevice parent_obj; |
753 | ||
23af670e | 754 | MemoryRegion io; |
4b78a802 | 755 | uint8_t outport; |
d812b3d6 | 756 | qemu_irq a20_out; |
4b78a802 BS |
757 | } Port92State; |
758 | ||
93ef4192 AG |
759 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
760 | unsigned size) | |
4b78a802 BS |
761 | { |
762 | Port92State *s = opaque; | |
4700a316 | 763 | int oldval = s->outport; |
4b78a802 | 764 | |
c5539cb4 | 765 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 766 | s->outport = val; |
d812b3d6 | 767 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 768 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 769 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
770 | } |
771 | } | |
772 | ||
93ef4192 AG |
773 | static uint64_t port92_read(void *opaque, hwaddr addr, |
774 | unsigned size) | |
4b78a802 BS |
775 | { |
776 | Port92State *s = opaque; | |
777 | uint32_t ret; | |
778 | ||
779 | ret = s->outport; | |
780 | DPRINTF("port92: read 0x%02x\n", ret); | |
781 | return ret; | |
782 | } | |
783 | ||
d80fe99d | 784 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 785 | { |
d80fe99d | 786 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
787 | } |
788 | ||
789 | static const VMStateDescription vmstate_port92_isa = { | |
790 | .name = "port92", | |
791 | .version_id = 1, | |
792 | .minimum_version_id = 1, | |
d49805ae | 793 | .fields = (VMStateField[]) { |
4b78a802 BS |
794 | VMSTATE_UINT8(outport, Port92State), |
795 | VMSTATE_END_OF_LIST() | |
796 | } | |
797 | }; | |
798 | ||
799 | static void port92_reset(DeviceState *d) | |
800 | { | |
a0881c64 | 801 | Port92State *s = PORT92(d); |
4b78a802 BS |
802 | |
803 | s->outport &= ~1; | |
804 | } | |
805 | ||
23af670e | 806 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
807 | .read = port92_read, |
808 | .write = port92_write, | |
809 | .impl = { | |
810 | .min_access_size = 1, | |
811 | .max_access_size = 1, | |
812 | }, | |
813 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
814 | }; |
815 | ||
db895a1e | 816 | static void port92_initfn(Object *obj) |
4b78a802 | 817 | { |
db895a1e | 818 | Port92State *s = PORT92(obj); |
4b78a802 | 819 | |
1437c94b | 820 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 821 | |
4b78a802 | 822 | s->outport = 0; |
d812b3d6 EV |
823 | |
824 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
825 | } |
826 | ||
827 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
828 | { | |
829 | ISADevice *isadev = ISA_DEVICE(dev); | |
830 | Port92State *s = PORT92(dev); | |
831 | ||
832 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
833 | } |
834 | ||
8f04ee08 AL |
835 | static void port92_class_initfn(ObjectClass *klass, void *data) |
836 | { | |
39bffca2 | 837 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 838 | |
db895a1e | 839 | dc->realize = port92_realizefn; |
39bffca2 AL |
840 | dc->reset = port92_reset; |
841 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
842 | /* |
843 | * Reason: unlike ordinary ISA devices, this one needs additional | |
844 | * wiring: its A20 output line needs to be wired up by | |
845 | * port92_init(). | |
846 | */ | |
e90f2a8c | 847 | dc->user_creatable = false; |
8f04ee08 AL |
848 | } |
849 | ||
8c43a6f0 | 850 | static const TypeInfo port92_info = { |
a0881c64 | 851 | .name = TYPE_PORT92, |
39bffca2 AL |
852 | .parent = TYPE_ISA_DEVICE, |
853 | .instance_size = sizeof(Port92State), | |
db895a1e | 854 | .instance_init = port92_initfn, |
39bffca2 | 855 | .class_init = port92_class_initfn, |
4b78a802 BS |
856 | }; |
857 | ||
83f7d43a | 858 | static void port92_register_types(void) |
4b78a802 | 859 | { |
39bffca2 | 860 | type_register_static(&port92_info); |
4b78a802 | 861 | } |
83f7d43a AF |
862 | |
863 | type_init(port92_register_types) | |
4b78a802 | 864 | |
956a3e6b | 865 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 866 | { |
cc36a7a2 | 867 | X86CPU *cpu = opaque; |
e1a23744 | 868 | |
956a3e6b | 869 | /* XXX: send to all CPUs ? */ |
4b78a802 | 870 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 871 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
872 | } |
873 | ||
b41a2cd1 FB |
874 | #define NE2000_NB_MAX 6 |
875 | ||
675d6f82 BS |
876 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
877 | 0x280, 0x380 }; | |
878 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 879 | |
48a18b3c | 880 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
881 | { |
882 | static int nb_ne2k = 0; | |
883 | ||
884 | if (nb_ne2k == NE2000_NB_MAX) | |
885 | return; | |
48a18b3c | 886 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 887 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
888 | nb_ne2k++; |
889 | } | |
890 | ||
92a16d7a | 891 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 892 | { |
4917cf44 AF |
893 | if (current_cpu) { |
894 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 895 | return cpu->apic_state; |
0e26b7b8 BS |
896 | } else { |
897 | return NULL; | |
898 | } | |
899 | } | |
900 | ||
845773ab | 901 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 902 | { |
c3affe56 | 903 | X86CPU *cpu = opaque; |
53b67b30 BS |
904 | |
905 | if (level) { | |
c3affe56 | 906 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
907 | } |
908 | } | |
909 | ||
6f479566 LX |
910 | /* |
911 | * This function is very similar to smp_parse() | |
912 | * in hw/core/machine.c but includes CPU die support. | |
913 | */ | |
914 | void pc_smp_parse(MachineState *ms, QemuOpts *opts) | |
915 | { | |
f0bb276b | 916 | X86MachineState *x86ms = X86_MACHINE(ms); |
1b458422 | 917 | |
6f479566 LX |
918 | if (opts) { |
919 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
920 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
1b458422 | 921 | unsigned dies = qemu_opt_get_number(opts, "dies", 1); |
6f479566 LX |
922 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); |
923 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
924 | ||
925 | /* compute missing values, prefer sockets over cores over threads */ | |
926 | if (cpus == 0 || sockets == 0) { | |
927 | cores = cores > 0 ? cores : 1; | |
928 | threads = threads > 0 ? threads : 1; | |
929 | if (cpus == 0) { | |
930 | sockets = sockets > 0 ? sockets : 1; | |
1b458422 | 931 | cpus = cores * threads * dies * sockets; |
6f479566 LX |
932 | } else { |
933 | ms->smp.max_cpus = | |
934 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1b458422 | 935 | sockets = ms->smp.max_cpus / (cores * threads * dies); |
6f479566 LX |
936 | } |
937 | } else if (cores == 0) { | |
938 | threads = threads > 0 ? threads : 1; | |
1b458422 | 939 | cores = cpus / (sockets * dies * threads); |
6f479566 LX |
940 | cores = cores > 0 ? cores : 1; |
941 | } else if (threads == 0) { | |
1b458422 | 942 | threads = cpus / (cores * dies * sockets); |
6f479566 | 943 | threads = threads > 0 ? threads : 1; |
1b458422 | 944 | } else if (sockets * dies * cores * threads < cpus) { |
6f479566 | 945 | error_report("cpu topology: " |
1b458422 | 946 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " |
6f479566 | 947 | "smp_cpus (%u)", |
1b458422 | 948 | sockets, dies, cores, threads, cpus); |
6f479566 LX |
949 | exit(1); |
950 | } | |
951 | ||
952 | ms->smp.max_cpus = | |
953 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
954 | ||
955 | if (ms->smp.max_cpus < cpus) { | |
956 | error_report("maxcpus must be equal to or greater than smp"); | |
957 | exit(1); | |
958 | } | |
959 | ||
1b458422 | 960 | if (sockets * dies * cores * threads > ms->smp.max_cpus) { |
6f479566 | 961 | error_report("cpu topology: " |
1b458422 | 962 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " |
6f479566 | 963 | "maxcpus (%u)", |
1b458422 | 964 | sockets, dies, cores, threads, |
6f479566 LX |
965 | ms->smp.max_cpus); |
966 | exit(1); | |
967 | } | |
968 | ||
1b458422 | 969 | if (sockets * dies * cores * threads != ms->smp.max_cpus) { |
6f479566 | 970 | warn_report("Invalid CPU topology deprecated: " |
1b458422 | 971 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " |
6f479566 | 972 | "!= maxcpus (%u)", |
1b458422 | 973 | sockets, dies, cores, threads, |
6f479566 LX |
974 | ms->smp.max_cpus); |
975 | } | |
976 | ||
977 | ms->smp.cpus = cpus; | |
978 | ms->smp.cores = cores; | |
979 | ms->smp.threads = threads; | |
f0bb276b | 980 | x86ms->smp_dies = dies; |
6f479566 LX |
981 | } |
982 | ||
983 | if (ms->smp.cpus > 1) { | |
984 | Error *blocker = NULL; | |
985 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
986 | replay_add_blocker(blocker); | |
987 | } | |
988 | } | |
989 | ||
a0628599 | 990 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) |
c649983b | 991 | { |
703a548a SL |
992 | X86MachineState *x86ms = X86_MACHINE(ms); |
993 | int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); | |
0e3bd562 | 994 | Error *local_err = NULL; |
c649983b | 995 | |
8de433cb IM |
996 | if (id < 0) { |
997 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
998 | return; | |
999 | } | |
1000 | ||
5ff020b7 EH |
1001 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1002 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1003 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1004 | id, apic_id); | |
1005 | return; | |
1006 | } | |
1007 | ||
703a548a SL |
1008 | |
1009 | x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); | |
0e3bd562 AF |
1010 | if (local_err) { |
1011 | error_propagate(errp, local_err); | |
1012 | return; | |
1013 | } | |
c649983b IM |
1014 | } |
1015 | ||
e3cadac0 IM |
1016 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1017 | { | |
1018 | if (cpus_count > 0xff) { | |
1019 | /* If the number of CPUs can't be represented in 8 bits, the | |
1020 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1021 | * to make old BIOSes fail more predictably. | |
1022 | */ | |
1023 | rtc_set_memory(rtc, 0x5f, 0); | |
1024 | } else { | |
1025 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1026 | } | |
1027 | } | |
1028 | ||
3459a625 | 1029 | static |
9ebeed0c | 1030 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1031 | { |
9ebeed0c EH |
1032 | PCMachineState *pcms = container_of(notifier, |
1033 | PCMachineState, machine_done); | |
f0bb276b | 1034 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9ebeed0c | 1035 | PCIBus *bus = pcms->bus; |
2118196b | 1036 | |
ba157b69 | 1037 | /* set the number of CPUs */ |
f0bb276b | 1038 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 1039 | |
2118196b MA |
1040 | if (bus) { |
1041 | int extra_hosts = 0; | |
1042 | ||
1043 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1044 | /* look for expander root buses */ | |
1045 | if (pci_bus_is_root(bus)) { | |
1046 | extra_hosts++; | |
1047 | } | |
1048 | } | |
f0bb276b | 1049 | if (extra_hosts && x86ms->fw_cfg) { |
2118196b MA |
1050 | uint64_t *val = g_malloc(sizeof(*val)); |
1051 | *val = cpu_to_le64(extra_hosts); | |
f0bb276b | 1052 | fw_cfg_add_file(x86ms->fw_cfg, |
2118196b MA |
1053 | "etc/extra-pci-roots", val, sizeof(*val)); |
1054 | } | |
1055 | } | |
1056 | ||
bb292f5a | 1057 | acpi_setup(); |
f0bb276b PB |
1058 | if (x86ms->fw_cfg) { |
1059 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
1060 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 1061 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 1062 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 1063 | } |
60c5e104 | 1064 | |
f0bb276b | 1065 | if (x86ms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
1066 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
1067 | ||
a924b3d8 | 1068 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || |
60c5e104 IM |
1069 | iommu->intr_eim != ON_OFF_AUTO_ON) { |
1070 | error_report("current -smp configuration requires " | |
1071 | "Extended Interrupt Mode enabled. " | |
1072 | "You can add an IOMMU using: " | |
1073 | "-device intel-iommu,intremap=on,eim=on"); | |
1074 | exit(EXIT_FAILURE); | |
1075 | } | |
1076 | } | |
3459a625 MT |
1077 | } |
1078 | ||
e4e8ba04 | 1079 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1080 | { |
1f3aba37 | 1081 | int i; |
aa570207 | 1082 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1083 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 1084 | |
f0bb276b | 1085 | x86ms->apic_xrupt_override = kvm_allows_irq0_override(); |
aa570207 | 1086 | pcms->numa_nodes = ms->numa_state->num_nodes; |
dd4c2f01 EH |
1087 | pcms->node_mem = g_malloc0(pcms->numa_nodes * |
1088 | sizeof *pcms->node_mem); | |
aa570207 | 1089 | for (i = 0; i < ms->numa_state->num_nodes; i++) { |
7e721e7b | 1090 | pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; |
8c85901e WG |
1091 | } |
1092 | ||
9ebeed0c EH |
1093 | pcms->machine_done.notify = pc_machine_done; |
1094 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1095 | } |
1096 | ||
83d08f26 MT |
1097 | /* setup pci memory address space mapping into system address space */ |
1098 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1099 | MemoryRegion *pci_address_space) | |
39848901 | 1100 | { |
83d08f26 MT |
1101 | /* Set to lower priority than RAM */ |
1102 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1103 | pci_address_space, -1); | |
39848901 IM |
1104 | } |
1105 | ||
7bc35e0f | 1106 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1107 | { |
1108 | int i; | |
1109 | FWCfgState *fw_cfg; | |
703a548a | 1110 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1111 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 1112 | |
df1f79fd | 1113 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1114 | |
305ae888 | 1115 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 1116 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
1117 | rom_set_fw(fw_cfg); |
1118 | ||
703a548a SL |
1119 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1120 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
b33a5bbf CL |
1121 | for (i = 0; i < nb_option_roms; i++) { |
1122 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1123 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 1124 | !strcmp(option_rom[i].name, "pvh.bin") || |
b33a5bbf CL |
1125 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1126 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1127 | } | |
f0bb276b | 1128 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1129 | } |
1130 | ||
5934e216 EH |
1131 | void pc_memory_init(PCMachineState *pcms, |
1132 | MemoryRegion *system_memory, | |
1133 | MemoryRegion *rom_memory, | |
1134 | MemoryRegion **ram_memory) | |
80cabfad | 1135 | { |
cbc5b5f3 JJ |
1136 | int linux_boot, i; |
1137 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1138 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1139 | FWCfgState *fw_cfg; |
62b160c0 | 1140 | MachineState *machine = MACHINE(pcms); |
264b4857 | 1141 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 1142 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 1143 | X86MachineState *x86ms = X86_MACHINE(pcms); |
d592d303 | 1144 | |
f0bb276b PB |
1145 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
1146 | x86ms->above_4g_mem_size); | |
9521d42b PB |
1147 | |
1148 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1149 | |
00cb2a99 | 1150 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1151 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1152 | * with older qemus that used qemu_ram_alloc(). |
1153 | */ | |
7267c094 | 1154 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1155 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1156 | machine->ram_size); | |
ae0a5466 | 1157 | *ram_memory = ram; |
7267c094 | 1158 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1159 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
f0bb276b | 1160 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 1161 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
1162 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
1163 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 1164 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1165 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
f0bb276b PB |
1166 | x86ms->below_4g_mem_size, |
1167 | x86ms->above_4g_mem_size); | |
00cb2a99 AK |
1168 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1169 | ram_above_4g); | |
f0bb276b | 1170 | e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1171 | } |
82b36dc3 | 1172 | |
bb292f5a | 1173 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1174 | (machine->ram_slots || |
9521d42b | 1175 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1176 | |
1177 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1178 | mc->name); | |
1179 | exit(EXIT_FAILURE); | |
1180 | } | |
1181 | ||
b0c14ec4 DH |
1182 | /* always allocate the device memory information */ |
1183 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1184 | ||
f2ffbe2b | 1185 | /* initialize device memory address space */ |
bb292f5a | 1186 | if (pcmc->has_reserved_memory && |
9521d42b | 1187 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 1188 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 1189 | |
a0cc8856 IM |
1190 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1191 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1192 | machine->ram_slots); | |
1193 | exit(EXIT_FAILURE); | |
1194 | } | |
1195 | ||
f2c38522 PK |
1196 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1197 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1198 | error_report("maximum memory size must by aligned to multiple of " | |
1199 | "%d bytes", TARGET_PAGE_SIZE); | |
1200 | exit(EXIT_FAILURE); | |
1201 | } | |
1202 | ||
b0c14ec4 | 1203 | machine->device_memory->base = |
f0bb276b | 1204 | ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); |
619d11e4 | 1205 | |
16a9e8a5 | 1206 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 1207 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 1208 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
1209 | } |
1210 | ||
f2ffbe2b DH |
1211 | if ((machine->device_memory->base + device_mem_size) < |
1212 | device_mem_size) { | |
619d11e4 IM |
1213 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1214 | machine->maxram_size); | |
1215 | exit(EXIT_FAILURE); | |
1216 | } | |
1217 | ||
b0c14ec4 | 1218 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 1219 | "device-memory", device_mem_size); |
b0c14ec4 DH |
1220 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
1221 | &machine->device_memory->mr); | |
619d11e4 | 1222 | } |
cbc5b5f3 JJ |
1223 | |
1224 | /* Initialize PC system firmware */ | |
5e640a9e | 1225 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 1226 | |
7267c094 | 1227 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1228 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1229 | &error_fatal); |
208fa0e4 IM |
1230 | if (pcmc->pci_enabled) { |
1231 | memory_region_set_readonly(option_rom_mr, true); | |
1232 | } | |
4463aee6 | 1233 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1234 | PC_ROM_MIN_VGA, |
1235 | option_rom_mr, | |
1236 | 1); | |
f753ff16 | 1237 | |
bd802bd9 | 1238 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 1239 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 1240 | |
8832cb80 | 1241 | rom_set_fw(fw_cfg); |
1d108d97 | 1242 | |
b0c14ec4 | 1243 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 1244 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 1245 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 1246 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1247 | |
1248 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1249 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1250 | } |
d471bf3e | 1251 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1252 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1253 | } | |
1254 | ||
f753ff16 | 1255 | if (linux_boot) { |
703a548a SL |
1256 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1257 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
f753ff16 PB |
1258 | } |
1259 | ||
1260 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1261 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1262 | } |
f0bb276b | 1263 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
1264 | |
1265 | /* Init default IOAPIC address space */ | |
f0bb276b | 1266 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
1267 | |
1268 | /* Init ACPI memory hotplug IO base address */ | |
1269 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
1270 | } |
1271 | ||
9fa99d25 MA |
1272 | /* |
1273 | * The 64bit pci hole starts after "above 4G RAM" and | |
1274 | * potentially the space reserved for memory hotplug. | |
1275 | */ | |
1276 | uint64_t pc_pci_hole64_start(void) | |
1277 | { | |
1278 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1279 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1280 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1281 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9fa99d25 MA |
1282 | uint64_t hole64_start = 0; |
1283 | ||
b0c14ec4 DH |
1284 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
1285 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 1286 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 1287 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 MA |
1288 | } |
1289 | } else { | |
f0bb276b | 1290 | hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; |
9fa99d25 MA |
1291 | } |
1292 | ||
d471bf3e | 1293 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1294 | } |
1295 | ||
0b0cc076 | 1296 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1297 | { |
0b0cc076 | 1298 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1299 | } |
1300 | ||
48a18b3c | 1301 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1302 | { |
ad6d45fa AL |
1303 | DeviceState *dev = NULL; |
1304 | ||
bab47d9a | 1305 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1306 | if (pci_bus) { |
1307 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1308 | dev = pcidev ? &pcidev->qdev : NULL; | |
1309 | } else if (isa_bus) { | |
1310 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1311 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1312 | } |
bab47d9a | 1313 | rom_reset_order_override(); |
ad6d45fa | 1314 | return dev; |
765d7908 IY |
1315 | } |
1316 | ||
258711c6 JG |
1317 | static const MemoryRegionOps ioport80_io_ops = { |
1318 | .write = ioport80_write, | |
c02e1eac | 1319 | .read = ioport80_read, |
258711c6 JG |
1320 | .endianness = DEVICE_NATIVE_ENDIAN, |
1321 | .impl = { | |
1322 | .min_access_size = 1, | |
1323 | .max_access_size = 1, | |
1324 | }, | |
1325 | }; | |
1326 | ||
1327 | static const MemoryRegionOps ioportF0_io_ops = { | |
1328 | .write = ioportF0_write, | |
c02e1eac | 1329 | .read = ioportF0_read, |
258711c6 JG |
1330 | .endianness = DEVICE_NATIVE_ENDIAN, |
1331 | .impl = { | |
1332 | .min_access_size = 1, | |
1333 | .max_access_size = 1, | |
1334 | }, | |
1335 | }; | |
1336 | ||
ac64273c PMD |
1337 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1338 | { | |
1339 | int i; | |
1340 | DriveInfo *fd[MAX_FD]; | |
1341 | qemu_irq *a20_line; | |
1342 | ISADevice *i8042, *port92, *vmmouse; | |
1343 | ||
def337ff | 1344 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1345 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1346 | ||
1347 | for (i = 0; i < MAX_FD; i++) { | |
1348 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1349 | create_fdctrl |= !!fd[i]; | |
1350 | } | |
1351 | if (create_fdctrl) { | |
1352 | fdctrl_init_isa(isa_bus, fd); | |
1353 | } | |
1354 | ||
1355 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1356 | if (!no_vmport) { | |
1357 | vmport_init(isa_bus); | |
1358 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1359 | } else { | |
1360 | vmmouse = NULL; | |
1361 | } | |
1362 | if (vmmouse) { | |
1363 | DeviceState *dev = DEVICE(vmmouse); | |
1364 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1365 | qdev_init_nofail(dev); | |
1366 | } | |
1367 | port92 = isa_create_simple(isa_bus, "port92"); | |
1368 | ||
1369 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1370 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1371 | port92_init(port92, a20_line[1]); | |
1372 | g_free(a20_line); | |
1373 | } | |
1374 | ||
48a18b3c | 1375 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1376 | ISADevice **rtc_state, |
fd53c87c | 1377 | bool create_fdctrl, |
7a10ef51 | 1378 | bool no_vmport, |
feddd2fd | 1379 | bool has_pit, |
3a87d009 | 1380 | uint32_t hpet_irqs) |
ffe513da IY |
1381 | { |
1382 | int i; | |
ce967e2f JK |
1383 | DeviceState *hpet = NULL; |
1384 | int pit_isa_irq = 0; | |
1385 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1386 | qemu_irq rtc_irq = NULL; |
ac64273c | 1387 | ISADevice *pit = NULL; |
258711c6 JG |
1388 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1389 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1390 | |
2c9b15ca | 1391 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1392 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1393 | |
2c9b15ca | 1394 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1395 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1396 | |
5d17c0d2 JK |
1397 | /* |
1398 | * Check if an HPET shall be created. | |
1399 | * | |
1400 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1401 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1402 | */ | |
1403 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1404 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1405 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1406 | if (hpet) { |
7a10ef51 LPF |
1407 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1408 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1409 | * IRQ8 and IRQ2. | |
1410 | */ | |
5d7fb0f2 | 1411 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1412 | HPET_INTCAP, NULL); |
1413 | if (!compat) { | |
1414 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1415 | } | |
1416 | qdev_init_nofail(hpet); | |
1417 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1418 | ||
b881fbe9 | 1419 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1420 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1421 | } |
ce967e2f JK |
1422 | pit_isa_irq = -1; |
1423 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1424 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1425 | } |
ffe513da | 1426 | } |
6c646a11 | 1427 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1428 | |
1429 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1430 | ||
feddd2fd | 1431 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1432 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1433 | pit = kvm_pit_init(isa_bus, 0x40); |
1434 | } else { | |
acf695ec | 1435 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1436 | } |
1437 | if (hpet) { | |
1438 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1439 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1440 | } |
1441 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1442 | } |
ffe513da | 1443 | |
55f613ac | 1444 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1445 | |
ac64273c PMD |
1446 | /* Super I/O */ |
1447 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
ffe513da IY |
1448 | } |
1449 | ||
4b9c264b | 1450 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1451 | { |
1452 | int i; | |
1453 | ||
bab47d9a | 1454 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1455 | for (i = 0; i < nb_nics; i++) { |
1456 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1457 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1458 | |
4b9c264b | 1459 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1460 | pc_init_ne2k_isa(isa_bus, nd); |
1461 | } else { | |
4b9c264b | 1462 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1463 | } |
1464 | } | |
bab47d9a | 1465 | rom_reset_order_override(); |
9011a1a7 IY |
1466 | } |
1467 | ||
4501d317 PMD |
1468 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1469 | { | |
1470 | qemu_irq *i8259; | |
1471 | ||
1472 | if (kvm_pic_in_kernel()) { | |
1473 | i8259 = kvm_i8259_init(isa_bus); | |
1474 | } else if (xen_enabled()) { | |
1475 | i8259 = xen_interrupt_controller_init(); | |
1476 | } else { | |
1477 | i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); | |
1478 | } | |
1479 | ||
1480 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1481 | i8259_irqs[i] = i8259[i]; | |
1482 | } | |
1483 | ||
1484 | g_free(i8259); | |
1485 | } | |
1486 | ||
a39e3564 JB |
1487 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) |
1488 | { | |
1489 | DeviceState *dev; | |
1490 | SysBusDevice *d; | |
1491 | unsigned int i; | |
1492 | ||
15eafc2e | 1493 | if (kvm_ioapic_in_kernel()) { |
34bec7a8 | 1494 | dev = qdev_create(NULL, TYPE_KVM_IOAPIC); |
a39e3564 | 1495 | } else { |
34bec7a8 | 1496 | dev = qdev_create(NULL, TYPE_IOAPIC); |
a39e3564 JB |
1497 | } |
1498 | if (parent_name) { | |
1499 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1500 | "ioapic", OBJECT(dev), NULL); | |
1501 | } | |
1502 | qdev_init_nofail(dev); | |
1356b98d | 1503 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1504 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1505 | |
1506 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1507 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1508 | } | |
1509 | } | |
d5747cac | 1510 | |
d468115b DH |
1511 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1512 | Error **errp) | |
1513 | { | |
1514 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
b0e62443 | 1515 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1516 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1517 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1518 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1519 | Error *local_err = NULL; |
d468115b DH |
1520 | |
1521 | /* | |
1522 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1523 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1524 | * addition to cover this case. | |
1525 | */ | |
1526 | if (!pcms->acpi_dev || !acpi_enabled) { | |
1527 | error_setg(errp, | |
1528 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1529 | return; | |
1530 | } | |
1531 | ||
f6a0d06b | 1532 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1533 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1534 | return; | |
1535 | } | |
8f1ffe5b | 1536 | |
ae909496 TH |
1537 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); |
1538 | if (local_err) { | |
1539 | error_propagate(errp, local_err); | |
1540 | return; | |
1541 | } | |
1542 | ||
fd3416f5 | 1543 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1544 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1545 | } |
1546 | ||
bb6e2f7a DH |
1547 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1548 | DeviceState *dev, Error **errp) | |
95bee274 IM |
1549 | { |
1550 | Error *local_err = NULL; | |
1551 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f6a0d06b | 1552 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1553 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1554 | |
fd3416f5 | 1555 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); |
43bbb49e | 1556 | if (local_err) { |
b8865591 IM |
1557 | goto out; |
1558 | } | |
1559 | ||
7f3cf2d6 | 1560 | if (is_nvdimm) { |
f6a0d06b | 1561 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1562 | } |
1563 | ||
473ac567 | 1564 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1565 | out: |
1566 | error_propagate(errp, local_err); | |
1567 | } | |
1568 | ||
bb6e2f7a DH |
1569 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1570 | DeviceState *dev, Error **errp) | |
64fec58e | 1571 | { |
64fec58e TC |
1572 | Error *local_err = NULL; |
1573 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1574 | ||
8cd91ace HZ |
1575 | /* |
1576 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1577 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1578 | * addition to cover this case. | |
1579 | */ | |
1580 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1581 | error_setg(&local_err, |
8cd91ace | 1582 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1583 | goto out; |
1584 | } | |
1585 | ||
b097cc52 XG |
1586 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1587 | error_setg(&local_err, | |
1588 | "nvdimm device hot unplug is not supported yet."); | |
1589 | goto out; | |
1590 | } | |
1591 | ||
473ac567 DH |
1592 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1593 | &local_err); | |
64fec58e TC |
1594 | out: |
1595 | error_propagate(errp, local_err); | |
1596 | } | |
1597 | ||
bb6e2f7a DH |
1598 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1599 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1600 | { |
1601 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f7d3e29d TC |
1602 | Error *local_err = NULL; |
1603 | ||
473ac567 | 1604 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
f7d3e29d TC |
1605 | if (local_err) { |
1606 | goto out; | |
1607 | } | |
1608 | ||
fd3416f5 | 1609 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
07578b0a | 1610 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
f7d3e29d TC |
1611 | out: |
1612 | error_propagate(errp, local_err); | |
1613 | } | |
1614 | ||
3811ef14 IM |
1615 | static int pc_apic_cmp(const void *a, const void *b) |
1616 | { | |
1617 | CPUArchId *apic_a = (CPUArchId *)a; | |
1618 | CPUArchId *apic_b = (CPUArchId *)b; | |
1619 | ||
1620 | return apic_a->arch_id - apic_b->arch_id; | |
1621 | } | |
1622 | ||
7baef5cf | 1623 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1624 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1625 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1626 | */ |
1ea69c0e | 1627 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1628 | { |
7baef5cf IM |
1629 | CPUArchId apic_id, *found_cpu; |
1630 | ||
1ea69c0e | 1631 | apic_id.arch_id = id; |
38690a1c IM |
1632 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1633 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1634 | pc_apic_cmp); |
1635 | if (found_cpu && idx) { | |
38690a1c | 1636 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1637 | } |
1638 | return found_cpu; | |
1639 | } | |
1640 | ||
5279569e GZ |
1641 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1642 | DeviceState *dev, Error **errp) | |
1643 | { | |
7baef5cf | 1644 | CPUArchId *found_cpu; |
5279569e | 1645 | Error *local_err = NULL; |
1ea69c0e | 1646 | X86CPU *cpu = X86_CPU(dev); |
5279569e | 1647 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1648 | X86MachineState *x86ms = X86_MACHINE(pcms); |
5279569e | 1649 | |
a44a49db | 1650 | if (pcms->acpi_dev) { |
473ac567 | 1651 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
a44a49db IM |
1652 | if (local_err) { |
1653 | goto out; | |
1654 | } | |
5279569e GZ |
1655 | } |
1656 | ||
e3cadac0 | 1657 | /* increment the number of CPUs */ |
f0bb276b PB |
1658 | x86ms->boot_cpus++; |
1659 | if (x86ms->rtc) { | |
1660 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); | |
26ef65be | 1661 | } |
f0bb276b PB |
1662 | if (x86ms->fw_cfg) { |
1663 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
2d996150 GZ |
1664 | } |
1665 | ||
1ea69c0e | 1666 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1667 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1668 | out: |
1669 | error_propagate(errp, local_err); | |
1670 | } | |
8872c25a IM |
1671 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1672 | DeviceState *dev, Error **errp) | |
1673 | { | |
73360e27 | 1674 | int idx = -1; |
8872c25a | 1675 | Error *local_err = NULL; |
1ea69c0e | 1676 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1677 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1678 | ||
75ba2ddb IM |
1679 | if (!pcms->acpi_dev) { |
1680 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
1681 | goto out; | |
1682 | } | |
1683 | ||
1ea69c0e | 1684 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1685 | assert(idx != -1); |
1686 | if (idx == 0) { | |
1687 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1688 | goto out; | |
1689 | } | |
1690 | ||
473ac567 DH |
1691 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1692 | &local_err); | |
8872c25a IM |
1693 | if (local_err) { |
1694 | goto out; | |
1695 | } | |
1696 | ||
1697 | out: | |
1698 | error_propagate(errp, local_err); | |
1699 | ||
1700 | } | |
1701 | ||
1702 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1703 | DeviceState *dev, Error **errp) | |
1704 | { | |
8fe6374e | 1705 | CPUArchId *found_cpu; |
8872c25a | 1706 | Error *local_err = NULL; |
1ea69c0e | 1707 | X86CPU *cpu = X86_CPU(dev); |
8872c25a | 1708 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1709 | X86MachineState *x86ms = X86_MACHINE(pcms); |
8872c25a | 1710 | |
473ac567 | 1711 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
8872c25a IM |
1712 | if (local_err) { |
1713 | goto out; | |
1714 | } | |
1715 | ||
1ea69c0e | 1716 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e | 1717 | found_cpu->cpu = NULL; |
07578b0a | 1718 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
8872c25a | 1719 | |
e3cadac0 | 1720 | /* decrement the number of CPUs */ |
f0bb276b | 1721 | x86ms->boot_cpus--; |
e3cadac0 | 1722 | /* Update the number of CPUs in CMOS */ |
f0bb276b PB |
1723 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
1724 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
8872c25a IM |
1725 | out: |
1726 | error_propagate(errp, local_err); | |
1727 | } | |
5279569e | 1728 | |
4ec60c76 IM |
1729 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1730 | DeviceState *dev, Error **errp) | |
1731 | { | |
1732 | int idx; | |
a15d2728 | 1733 | CPUState *cs; |
e8f7b83e | 1734 | CPUArchId *cpu_slot; |
d89c2b8b | 1735 | X86CPUTopoInfo topo; |
4ec60c76 | 1736 | X86CPU *cpu = X86_CPU(dev); |
cabea7dc | 1737 | CPUX86State *env = &cpu->env; |
6970c5ff | 1738 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 1739 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1740 | X86MachineState *x86ms = X86_MACHINE(pcms); |
0e11fc69 LX |
1741 | unsigned int smp_cores = ms->smp.cores; |
1742 | unsigned int smp_threads = ms->smp.threads; | |
4ec60c76 | 1743 | |
6970c5ff IM |
1744 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
1745 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
1746 | ms->cpu_type); | |
1747 | return; | |
1748 | } | |
1749 | ||
f0bb276b | 1750 | env->nr_dies = x86ms->smp_dies; |
cabea7dc | 1751 | |
c26ae610 LX |
1752 | /* |
1753 | * If APIC ID is not set, | |
1754 | * set it based on socket/die/core/thread properties. | |
1755 | */ | |
e8f7b83e | 1756 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { |
c26ae610 | 1757 | int max_socket = (ms->smp.max_cpus - 1) / |
f0bb276b | 1758 | smp_threads / smp_cores / x86ms->smp_dies; |
e8f7b83e | 1759 | |
fea374e7 EH |
1760 | /* |
1761 | * die-id was optional in QEMU 4.0 and older, so keep it optional | |
1762 | * if there's only one die per socket. | |
1763 | */ | |
f0bb276b | 1764 | if (cpu->die_id < 0 && x86ms->smp_dies == 1) { |
fea374e7 EH |
1765 | cpu->die_id = 0; |
1766 | } | |
1767 | ||
e8f7b83e IM |
1768 | if (cpu->socket_id < 0) { |
1769 | error_setg(errp, "CPU socket-id is not set"); | |
1770 | return; | |
1771 | } else if (cpu->socket_id > max_socket) { | |
1772 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1773 | cpu->socket_id, max_socket); | |
1774 | return; | |
23d9cff4 EH |
1775 | } |
1776 | if (cpu->die_id < 0) { | |
1777 | error_setg(errp, "CPU die-id is not set"); | |
1778 | return; | |
f0bb276b | 1779 | } else if (cpu->die_id > x86ms->smp_dies - 1) { |
176d2cda | 1780 | error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", |
f0bb276b | 1781 | cpu->die_id, x86ms->smp_dies - 1); |
176d2cda | 1782 | return; |
e8f7b83e IM |
1783 | } |
1784 | if (cpu->core_id < 0) { | |
1785 | error_setg(errp, "CPU core-id is not set"); | |
1786 | return; | |
1787 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1788 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1789 | cpu->core_id, smp_cores - 1); | |
1790 | return; | |
1791 | } | |
1792 | if (cpu->thread_id < 0) { | |
1793 | error_setg(errp, "CPU thread-id is not set"); | |
1794 | return; | |
1795 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1796 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1797 | cpu->thread_id, smp_threads - 1); | |
1798 | return; | |
1799 | } | |
1800 | ||
1801 | topo.pkg_id = cpu->socket_id; | |
176d2cda | 1802 | topo.die_id = cpu->die_id; |
e8f7b83e IM |
1803 | topo.core_id = cpu->core_id; |
1804 | topo.smt_id = cpu->thread_id; | |
f0bb276b | 1805 | cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, |
d65af288 | 1806 | smp_threads, &topo); |
e8f7b83e IM |
1807 | } |
1808 | ||
1ea69c0e | 1809 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1810 | if (!cpu_slot) { |
38690a1c IM |
1811 | MachineState *ms = MACHINE(pcms); |
1812 | ||
f0bb276b | 1813 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 LX |
1814 | smp_cores, smp_threads, &topo); |
1815 | error_setg(errp, | |
1816 | "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" | |
1817 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1818 | topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, | |
1819 | cpu->apic_id, ms->possible_cpus->len - 1); | |
4ec60c76 IM |
1820 | return; |
1821 | } | |
1822 | ||
1823 | if (cpu_slot->cpu) { | |
1824 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1825 | idx, cpu->apic_id); | |
1826 | return; | |
1827 | } | |
d89c2b8b IM |
1828 | |
1829 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1830 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1831 | */ |
1832 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1833 | * once -smp refactoring is complete and there will be CPU private | |
1834 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
f0bb276b | 1835 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
d65af288 | 1836 | smp_cores, smp_threads, &topo); |
d89c2b8b IM |
1837 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { |
1838 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1839 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1840 | return; | |
1841 | } | |
1842 | cpu->socket_id = topo.pkg_id; | |
1843 | ||
176d2cda LX |
1844 | if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { |
1845 | error_setg(errp, "property die-id: %u doesn't match set apic-id:" | |
1846 | " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); | |
1847 | return; | |
1848 | } | |
1849 | cpu->die_id = topo.die_id; | |
1850 | ||
d89c2b8b IM |
1851 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { |
1852 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1853 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1854 | return; | |
1855 | } | |
1856 | cpu->core_id = topo.core_id; | |
1857 | ||
1858 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1859 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1860 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1861 | return; | |
1862 | } | |
1863 | cpu->thread_id = topo.smt_id; | |
a15d2728 | 1864 | |
2d384d7c VK |
1865 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && |
1866 | !kvm_hv_vpindex_settable()) { | |
e9688fab RK |
1867 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); |
1868 | return; | |
1869 | } | |
1870 | ||
a15d2728 IM |
1871 | cs = CPU(cpu); |
1872 | cs->cpu_index = idx; | |
93b2a8cb | 1873 | |
a0ceb640 | 1874 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
1875 | } |
1876 | ||
a0a49813 DH |
1877 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, |
1878 | DeviceState *dev, Error **errp) | |
1879 | { | |
1880 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1881 | Error *local_err = NULL; | |
1882 | ||
1883 | if (!hotplug_dev2) { | |
1884 | /* | |
1885 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
1886 | * order. This should never be the case on x86, however better add | |
1887 | * a safety net. | |
1888 | */ | |
1889 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
1890 | return; | |
1891 | } | |
1892 | /* | |
1893 | * First, see if we can plug this memory device at all. If that | |
1894 | * succeeds, branch of to the actual hotplug handler. | |
1895 | */ | |
1896 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1897 | &local_err); | |
1898 | if (!local_err) { | |
1899 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
1900 | } | |
1901 | error_propagate(errp, local_err); | |
1902 | } | |
1903 | ||
1904 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
1905 | DeviceState *dev, Error **errp) | |
1906 | { | |
1907 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1908 | Error *local_err = NULL; | |
1909 | ||
1910 | /* | |
1911 | * Plug the memory device first and then branch off to the actual | |
1912 | * hotplug handler. If that one fails, we can easily undo the memory | |
1913 | * device bits. | |
1914 | */ | |
1915 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1916 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
1917 | if (local_err) { | |
1918 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1919 | } | |
1920 | error_propagate(errp, local_err); | |
1921 | } | |
1922 | ||
1923 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
1924 | DeviceState *dev, Error **errp) | |
1925 | { | |
1926 | /* We don't support virtio pmem hot unplug */ | |
1927 | error_setg(errp, "virtio pmem device unplug not supported."); | |
1928 | } | |
1929 | ||
1930 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
1931 | DeviceState *dev, Error **errp) | |
1932 | { | |
1933 | /* We don't support virtio pmem hot unplug */ | |
1934 | } | |
1935 | ||
4ec60c76 IM |
1936 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1937 | DeviceState *dev, Error **errp) | |
1938 | { | |
d468115b DH |
1939 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1940 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1941 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
4ec60c76 | 1942 | pc_cpu_pre_plug(hotplug_dev, dev, errp); |
a0a49813 DH |
1943 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1944 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1945 | } |
1946 | } | |
1947 | ||
95bee274 IM |
1948 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1949 | DeviceState *dev, Error **errp) | |
1950 | { | |
1951 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1952 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e GZ |
1953 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1954 | pc_cpu_plug(hotplug_dev, dev, errp); | |
a0a49813 DH |
1955 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1956 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1957 | } |
1958 | } | |
1959 | ||
d9c5c5b8 TC |
1960 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1961 | DeviceState *dev, Error **errp) | |
1962 | { | |
64fec58e | 1963 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1964 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a IM |
1965 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1966 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1967 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1968 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
64fec58e TC |
1969 | } else { |
1970 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1971 | " type: %s", object_get_typename(OBJECT(dev))); | |
1972 | } | |
d9c5c5b8 TC |
1973 | } |
1974 | ||
232391c1 TC |
1975 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1976 | DeviceState *dev, Error **errp) | |
1977 | { | |
f7d3e29d | 1978 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1979 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a IM |
1980 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1981 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1982 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1983 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
f7d3e29d TC |
1984 | } else { |
1985 | error_setg(errp, "acpi: device unplug for not supported device" | |
1986 | " type: %s", object_get_typename(OBJECT(dev))); | |
1987 | } | |
232391c1 TC |
1988 | } |
1989 | ||
285816d7 | 1990 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
1991 | DeviceState *dev) |
1992 | { | |
5279569e | 1993 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 DH |
1994 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
1995 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
95bee274 IM |
1996 | return HOTPLUG_HANDLER(machine); |
1997 | } | |
1998 | ||
38aefb57 | 1999 | return NULL; |
95bee274 IM |
2000 | } |
2001 | ||
bf1e8939 | 2002 | static void |
f2ffbe2b DH |
2003 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
2004 | const char *name, void *opaque, | |
2005 | Error **errp) | |
bf1e8939 | 2006 | { |
b0c14ec4 | 2007 | MachineState *ms = MACHINE(obj); |
fc3b77e2 IM |
2008 | int64_t value = 0; |
2009 | ||
2010 | if (ms->device_memory) { | |
2011 | value = memory_region_size(&ms->device_memory->mr); | |
2012 | } | |
bf1e8939 | 2013 | |
51e72bc1 | 2014 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2015 | } |
2016 | ||
d7bce999 EB |
2017 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2018 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2019 | { |
2020 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2021 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2022 | |
51e72bc1 | 2023 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2024 | } |
2025 | ||
d7bce999 EB |
2026 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2027 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2028 | { |
2029 | PCMachineState *pcms = PC_MACHINE(obj); | |
2030 | ||
51e72bc1 | 2031 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2032 | } |
2033 | ||
be232eb0 CP |
2034 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2035 | { | |
2036 | PCMachineState *pcms = PC_MACHINE(obj); | |
2037 | ||
f5878b03 | 2038 | return pcms->smbus_enabled; |
be232eb0 CP |
2039 | } |
2040 | ||
2041 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2042 | { | |
2043 | PCMachineState *pcms = PC_MACHINE(obj); | |
2044 | ||
f5878b03 | 2045 | pcms->smbus_enabled = value; |
be232eb0 CP |
2046 | } |
2047 | ||
272f0428 CP |
2048 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2049 | { | |
2050 | PCMachineState *pcms = PC_MACHINE(obj); | |
2051 | ||
f5878b03 | 2052 | return pcms->sata_enabled; |
272f0428 CP |
2053 | } |
2054 | ||
2055 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2056 | { | |
2057 | PCMachineState *pcms = PC_MACHINE(obj); | |
2058 | ||
f5878b03 | 2059 | pcms->sata_enabled = value; |
272f0428 CP |
2060 | } |
2061 | ||
feddd2fd CP |
2062 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2063 | { | |
2064 | PCMachineState *pcms = PC_MACHINE(obj); | |
2065 | ||
f5878b03 | 2066 | return pcms->pit_enabled; |
feddd2fd CP |
2067 | } |
2068 | ||
2069 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2070 | { | |
2071 | PCMachineState *pcms = PC_MACHINE(obj); | |
2072 | ||
f5878b03 | 2073 | pcms->pit_enabled = value; |
feddd2fd CP |
2074 | } |
2075 | ||
bf1e8939 IM |
2076 | static void pc_machine_initfn(Object *obj) |
2077 | { | |
c87b1520 DS |
2078 | PCMachineState *pcms = PC_MACHINE(obj); |
2079 | ||
97fd1ea8 | 2080 | #ifdef CONFIG_VMPORT |
d1048bef | 2081 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
2082 | #else |
2083 | pcms->vmport = ON_OFF_AUTO_OFF; | |
2084 | #endif /* CONFIG_VMPORT */ | |
021746c1 WL |
2085 | /* acpi build is enabled by default if machine supports it */ |
2086 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
2087 | pcms->smbus_enabled = true; |
2088 | pcms->sata_enabled = true; | |
2089 | pcms->pit_enabled = true; | |
ebc29e1b MA |
2090 | |
2091 | pc_system_flash_create(pcms); | |
bf1e8939 IM |
2092 | } |
2093 | ||
a0628599 | 2094 | static void pc_machine_reset(MachineState *machine) |
ae50c55a ZG |
2095 | { |
2096 | CPUState *cs; | |
2097 | X86CPU *cpu; | |
2098 | ||
2099 | qemu_devices_reset(); | |
2100 | ||
2101 | /* Reset APIC after devices have been reset to cancel | |
2102 | * any changes that qemu_devices_reset() might have done. | |
2103 | */ | |
2104 | CPU_FOREACH(cs) { | |
2105 | cpu = X86_CPU(cs); | |
2106 | ||
2107 | if (cpu->apic_state) { | |
2108 | device_reset(cpu->apic_state); | |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | ||
c508bd12 NP |
2113 | static void pc_machine_wakeup(MachineState *machine) |
2114 | { | |
2115 | cpu_synchronize_all_states(); | |
2116 | pc_machine_reset(machine); | |
2117 | cpu_synchronize_all_post_reset(); | |
2118 | } | |
2119 | ||
c6cbc29d PX |
2120 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
2121 | { | |
2122 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
2123 | IntelIOMMUState *intel_iommu; | |
2124 | ||
2125 | if (iommu && | |
2126 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
2127 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
2128 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
2129 | if (!intel_iommu->caching_mode) { | |
2130 | error_setg(errp, "Device assignment is not allowed without " | |
2131 | "enabling caching-mode=on for Intel IOMMU."); | |
2132 | return false; | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | return true; | |
2137 | } | |
2138 | ||
95bee274 IM |
2139 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2140 | { | |
2141 | MachineClass *mc = MACHINE_CLASS(oc); | |
2142 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2143 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2144 | ||
7102fa70 EH |
2145 | pcmc->pci_enabled = true; |
2146 | pcmc->has_acpi_build = true; | |
2147 | pcmc->rsdp_in_ram = true; | |
2148 | pcmc->smbios_defaults = true; | |
2149 | pcmc->smbios_uuid_encoded = true; | |
2150 | pcmc->gigabyte_align = true; | |
2151 | pcmc->has_reserved_memory = true; | |
2152 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2153 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2154 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2155 | * to be used at the moment, 32K should be enough for a while. */ | |
2156 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
98e753a6 | 2157 | pcmc->linuxboot_dma_enabled = true; |
fda672b5 | 2158 | pcmc->pvh_enabled = true; |
debbdc00 | 2159 | assert(!mc->get_hotplug_handler); |
285816d7 | 2160 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 2161 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
2162 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
2163 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
2164 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 2165 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 2166 | mc->has_hotpluggable_cpus = true; |
41742767 | 2167 | mc->default_boot_order = "cad"; |
4458fb3a | 2168 | mc->hot_add_cpu = pc_hot_add_cpu; |
6f479566 | 2169 | mc->smp_parse = pc_smp_parse; |
2059839b | 2170 | mc->block_default_type = IF_IDE; |
4458fb3a | 2171 | mc->max_cpus = 255; |
ae50c55a | 2172 | mc->reset = pc_machine_reset; |
c508bd12 | 2173 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 2174 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2175 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2176 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2177 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 2178 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 2179 | mc->nvdimm_supported = true; |
cd5ff833 | 2180 | mc->numa_mem_supported = true; |
0efc257d | 2181 | |
f2ffbe2b DH |
2182 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
2183 | pc_machine_get_device_memory_region_size, NULL, | |
0efc257d EH |
2184 | NULL, NULL, &error_abort); |
2185 | ||
0efc257d EH |
2186 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", |
2187 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2188 | NULL, NULL, &error_abort); | |
2189 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2190 | "Enable vmport (pc & q35)", &error_abort); | |
2191 | ||
be232eb0 CP |
2192 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
2193 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2194 | |
2195 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2196 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2197 | |
2198 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2199 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2200 | } |
2201 | ||
d5747cac IM |
2202 | static const TypeInfo pc_machine_info = { |
2203 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 2204 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
2205 | .abstract = true, |
2206 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2207 | .instance_init = pc_machine_initfn, |
d5747cac | 2208 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2209 | .class_init = pc_machine_class_init, |
2210 | .interfaces = (InterfaceInfo[]) { | |
2211 | { TYPE_HOTPLUG_HANDLER }, | |
2212 | { } | |
2213 | }, | |
d5747cac IM |
2214 | }; |
2215 | ||
2216 | static void pc_machine_register_types(void) | |
2217 | { | |
2218 | type_register_static(&pc_machine_info); | |
2219 | } | |
2220 | ||
2221 | type_init(pc_machine_register_types) |