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0200db65
MF
1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
09aae23d 28#include "qemu/osdep.h"
b941329d 29#include "qemu/units.h"
da34e65c 30#include "qapi/error.h"
4771d756 31#include "cpu.h"
9c17d615 32#include "sysemu/sysemu.h"
83c9f4ca
PB
33#include "hw/boards.h"
34#include "hw/loader.h"
a27bd6c7 35#include "hw/qdev-properties.h"
0200db65 36#include "elf.h"
022c62cb 37#include "exec/memory.h"
0d09e41a 38#include "hw/char/serial.h"
1422e32d 39#include "net/net.h"
83c9f4ca 40#include "hw/sysbus.h"
0d09e41a 41#include "hw/block/flash.h"
8228e353 42#include "chardev/char.h"
996dfe98 43#include "sysemu/device_tree.h"
71e8a915 44#include "sysemu/reset.h"
54d31236 45#include "sysemu/runstate.h"
8488ab02 46#include "qemu/error-report.h"
922a01a0 47#include "qemu/option.h"
b707ab75 48#include "bootparam.h"
e53fa62c 49#include "xtensa_memory.h"
1acd90bf 50#include "hw/xtensa/mx_pic.h"
d6454270 51#include "migration/vmstate.h"
82b25dc8 52
740ad9f7
MF
53typedef struct XtfpgaFlashDesc {
54 hwaddr base;
55 size_t size;
56 size_t boot_base;
57 size_t sector_size;
58} XtfpgaFlashDesc;
59
188ce01d 60typedef struct XtfpgaBoardDesc {
740ad9f7 61 const XtfpgaFlashDesc *flash;
82b25dc8 62 size_t sram_size;
85e2d8d5 63 const hwaddr *io;
188ce01d 64} XtfpgaBoardDesc;
0200db65 65
188ce01d 66typedef struct XtfpgaFpgaState {
0200db65 67 MemoryRegion iomem;
fff7bf14 68 uint32_t freq;
0200db65
MF
69 uint32_t leds;
70 uint32_t switches;
188ce01d 71} XtfpgaFpgaState;
0200db65 72
188ce01d 73static void xtfpga_fpga_reset(void *opaque)
0200db65 74{
188ce01d 75 XtfpgaFpgaState *s = opaque;
0200db65
MF
76
77 s->leds = 0;
78 s->switches = 0;
79}
80
188ce01d 81static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
0200db65
MF
82 unsigned size)
83{
188ce01d 84 XtfpgaFpgaState *s = opaque;
0200db65
MF
85
86 switch (addr) {
87 case 0x0: /*build date code*/
556ba668 88 return 0x09272011;
0200db65
MF
89
90 case 0x4: /*processor clock frequency, Hz*/
fff7bf14 91 return s->freq;
0200db65
MF
92
93 case 0x8: /*LEDs (off = 0, on = 1)*/
94 return s->leds;
95
96 case 0xc: /*DIP switches (off = 0, on = 1)*/
97 return s->switches;
98 }
99 return 0;
100}
101
188ce01d 102static void xtfpga_fpga_write(void *opaque, hwaddr addr,
0200db65
MF
103 uint64_t val, unsigned size)
104{
188ce01d 105 XtfpgaFpgaState *s = opaque;
0200db65
MF
106
107 switch (addr) {
108 case 0x8: /*LEDs (off = 0, on = 1)*/
109 s->leds = val;
110 break;
111
112 case 0x10: /*board reset*/
113 if (val == 0xdead) {
cf83f140 114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
0200db65
MF
115 }
116 break;
117 }
118}
119
188ce01d
MF
120static const MemoryRegionOps xtfpga_fpga_ops = {
121 .read = xtfpga_fpga_read,
122 .write = xtfpga_fpga_write,
0200db65
MF
123 .endianness = DEVICE_NATIVE_ENDIAN,
124};
125
188ce01d 126static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
fff7bf14 127 hwaddr base, uint32_t freq)
0200db65 128{
b21e2380 129 XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1);
0200db65 130
188ce01d 131 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
fff7bf14 132 "xtfpga.fpga", 0x10000);
0200db65 133 memory_region_add_subregion(address_space, base, &s->iomem);
fff7bf14 134 s->freq = freq;
188ce01d
MF
135 xtfpga_fpga_reset(s);
136 qemu_register_reset(xtfpga_fpga_reset, s);
0200db65
MF
137 return s;
138}
139
188ce01d 140static void xtfpga_net_init(MemoryRegion *address_space,
a8170e5e
AK
141 hwaddr base,
142 hwaddr descriptors,
143 hwaddr buffers,
7db00af6 144 qemu_irq irq)
0200db65
MF
145{
146 DeviceState *dev;
147 SysBusDevice *s;
148 MemoryRegion *ram;
149
7db00af6
DW
150 dev = qemu_create_nic_device("open_eth", true, NULL);
151 if (!dev) {
152 return;
153 }
0200db65 154
1356b98d 155 s = SYS_BUS_DEVICE(dev);
3c6ef471 156 sysbus_realize_and_unref(s, &error_fatal);
0200db65
MF
157 sysbus_connect_irq(s, 0, irq);
158 memory_region_add_subregion(address_space, base,
159 sysbus_mmio_get_region(s, 0));
160 memory_region_add_subregion(address_space, descriptors,
161 sysbus_mmio_get_region(s, 1));
162
163 ram = g_malloc(sizeof(*ram));
b941329d 164 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
f8ed85ac 165 &error_fatal);
c5705a77 166 vmstate_register_ram_global(ram);
0200db65
MF
167 memory_region_add_subregion(address_space, buffers, ram);
168}
169
16434065
MA
170static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
171 const XtfpgaBoardDesc *board,
172 DriveInfo *dinfo, int be)
68931a40
MF
173{
174 SysBusDevice *s;
3e80f690 175 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
68931a40 176
934df912 177 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
68931a40 178 qdev_prop_set_uint32(dev, "num-blocks",
740ad9f7
MF
179 board->flash->size / board->flash->sector_size);
180 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
f9a555e4 181 qdev_prop_set_uint8(dev, "width", 2);
68931a40 182 qdev_prop_set_bit(dev, "big-endian", be);
188ce01d 183 qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
68931a40 184 s = SYS_BUS_DEVICE(dev);
3c6ef471 185 sysbus_realize_and_unref(s, &error_fatal);
740ad9f7 186 memory_region_add_subregion(address_space, board->flash->base,
68931a40 187 sysbus_mmio_get_region(s, 0));
81c7db72 188 return PFLASH_CFI01(dev);
68931a40
MF
189}
190
00b941e5 191static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
0200db65 192{
00b941e5
AF
193 XtensaCPU *cpu = opaque;
194
195 return cpu_get_phys_page_debug(CPU(cpu), addr);
0200db65
MF
196}
197
188ce01d 198static void xtfpga_reset(void *opaque)
0200db65 199{
eded1267 200 XtensaCPU *cpu = opaque;
1bba0dc9 201
eded1267 202 cpu_reset(CPU(cpu));
0200db65
MF
203}
204
188ce01d 205static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
8bb3b575
MF
206 unsigned size)
207{
208 return 0;
209}
210
188ce01d 211static void xtfpga_io_write(void *opaque, hwaddr addr,
8bb3b575
MF
212 uint64_t val, unsigned size)
213{
214}
215
188ce01d
MF
216static const MemoryRegionOps xtfpga_io_ops = {
217 .read = xtfpga_io_read,
218 .write = xtfpga_io_write,
8bb3b575
MF
219 .endianness = DEVICE_NATIVE_ENDIAN,
220};
221
188ce01d 222static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
0200db65 223{
0200db65 224 MemoryRegion *system_memory = get_system_memory();
adbb0f75 225 XtensaCPU *cpu = NULL;
5bfcb36e 226 CPUXtensaState *env = NULL;
e53fa62c 227 MemoryRegion *system_io;
1acd90bf 228 XtensaMxPic *mx_pic = NULL;
66f03d7e 229 qemu_irq *extints;
82b25dc8 230 DriveInfo *dinfo;
16434065 231 PFlashCFI01 *flash = NULL;
f2ce39b4
PB
232 const char *kernel_filename = machine->kernel_filename;
233 const char *kernel_cmdline = machine->kernel_cmdline;
234 const char *dtb_filename = machine->dtb;
235 const char *initrd_filename = machine->initrd_filename;
b941329d 236 const unsigned system_io_size = 224 * MiB;
fff7bf14 237 uint32_t freq = 10000000;
0200db65 238 int n;
33decbd2 239 unsigned int smp_cpus = machine->smp.cpus;
0200db65 240
1acd90bf
MF
241 if (smp_cpus > 1) {
242 mx_pic = xtensa_mx_pic_init(31);
243 qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
244 }
0200db65 245 for (n = 0; n < smp_cpus; n++) {
288a3f2e
MF
246 CPUXtensaState *cenv = NULL;
247
f83eb10d 248 cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
288a3f2e
MF
249 cenv = &cpu->env;
250 if (!env) {
251 env = cenv;
fff7bf14 252 freq = env->config->clock_freq_khz * 1000;
288a3f2e 253 }
adbb0f75 254
1acd90bf
MF
255 if (mx_pic) {
256 MemoryRegion *mx_eri;
257
258 mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
259 xtensa_get_extints(cenv),
260 xtensa_get_runstall(cenv));
261 memory_region_add_subregion(xtensa_get_er_region(cenv),
262 0, mx_eri);
263 }
288a3f2e 264 cenv->sregs[PRID] = n;
1acd90bf 265 xtensa_select_static_vectors(cenv, n != 0);
188ce01d 266 qemu_register_reset(xtfpga_reset, cpu);
0200db65
MF
267 /* Need MMU initialized prior to ELF loading,
268 * so that ELF gets loaded into virtual addresses
269 */
adbb0f75 270 cpu_reset(CPU(cpu));
0200db65 271 }
1acd90bf
MF
272 if (smp_cpus > 1) {
273 extints = xtensa_mx_pic_get_extints(mx_pic);
274 } else {
275 extints = xtensa_get_extints(env);
276 }
0200db65 277
e53fa62c
MF
278 if (env) {
279 XtensaMemory sysram = env->config->sysram;
280
281 sysram.location[0].size = machine->ram_size;
282 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
283 system_memory);
284 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
285 system_memory);
286 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
287 system_memory);
288 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
289 system_memory);
290 xtensa_create_memory_regions(&sysram, "xtensa.sysram",
291 system_memory);
292 }
0200db65 293
0200db65 294 system_io = g_malloc(sizeof(*system_io));
188ce01d 295 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
85e2d8d5
MF
296 system_io_size);
297 memory_region_add_subregion(system_memory, board->io[0], system_io);
298 if (board->io[1]) {
299 MemoryRegion *io = g_malloc(sizeof(*io));
300
301 memory_region_init_alias(io, NULL, "xtfpga.io.cached",
302 system_io, 0, system_io_size);
303 memory_region_add_subregion(system_memory, board->io[1], io);
304 }
fff7bf14 305 xtfpga_fpga_init(system_io, 0x0d020000, freq);
7db00af6 306 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]);
0200db65 307
66f03d7e
MF
308 serial_mm_init(system_io, 0x0d050020, 2, extints[0],
309 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
0200db65 310
82b25dc8
MF
311 dinfo = drive_get(IF_PFLASH, 0, 0);
312 if (dinfo) {
ded625e7 313 flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN);
82b25dc8
MF
314 }
315
316 /* Use presence of kernel file name as 'boot from SRAM' switch. */
0200db65 317 if (kernel_filename) {
364d4802 318 uint32_t entry_point = env->pc;
b6edea8b 319 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
e53fa62c
MF
320 uint32_t tagptr = env->config->sysrom.location[0].addr +
321 board->sram_size;
a9a28591 322 uint32_t cur_tagptr;
b6edea8b
MF
323 BpMemInfo memory_location = {
324 .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
e53fa62c
MF
325 .start = tswap32(env->config->sysram.location[0].addr),
326 .end = tswap32(env->config->sysram.location[0].addr +
327 machine->ram_size),
b6edea8b 328 };
996dfe98
MF
329 uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
330 machine->ram_size : 0x08000000;
331 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
a9a28591 332
e53fa62c
MF
333 lowmem_end += env->config->sysram.location[0].addr;
334 cur_lowmem += env->config->sysram.location[0].addr;
335
336 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
337 system_memory);
292627bb 338
a9a28591
MF
339 if (kernel_cmdline) {
340 bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
341 }
996dfe98
MF
342 if (dtb_filename) {
343 bp_size += get_tag_size(sizeof(uint32_t));
344 }
f55b32e7
MF
345 if (initrd_filename) {
346 bp_size += get_tag_size(sizeof(BpMemInfo));
347 }
a9a28591 348
292627bb 349 /* Put kernel bootparameters to the end of that SRAM */
a9a28591
MF
350 tagptr = (tagptr - bp_size) & ~0xff;
351 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
b6edea8b
MF
352 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
353 sizeof(memory_location), &memory_location);
a9a28591 354
292627bb 355 if (kernel_cmdline) {
a9a28591
MF
356 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
357 strlen(kernel_cmdline) + 1, kernel_cmdline);
292627bb 358 }
996dfe98
MF
359 if (dtb_filename) {
360 int fdt_size;
361 void *fdt = load_device_tree(dtb_filename, &fdt_size);
362 uint32_t dtb_addr = tswap32(cur_lowmem);
363
364 if (!fdt) {
ebbb419a 365 error_report("could not load DTB '%s'", dtb_filename);
996dfe98
MF
366 exit(EXIT_FAILURE);
367 }
368
369 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
370 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
371 sizeof(dtb_addr), &dtb_addr);
b941329d 372 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
d1cb6784 373 g_free(fdt);
996dfe98 374 }
f55b32e7
MF
375 if (initrd_filename) {
376 BpMemInfo initrd_location = { 0 };
377 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
378 lowmem_end - cur_lowmem);
379
380 if (initrd_size < 0) {
381 initrd_size = load_image_targphys(initrd_filename,
382 cur_lowmem,
383 lowmem_end - cur_lowmem);
384 }
385 if (initrd_size < 0) {
ebbb419a 386 error_report("could not load initrd '%s'", initrd_filename);
f55b32e7
MF
387 exit(EXIT_FAILURE);
388 }
389 initrd_location.start = tswap32(cur_lowmem);
390 initrd_location.end = tswap32(cur_lowmem + initrd_size);
391 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
392 sizeof(initrd_location), &initrd_location);
b941329d 393 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
f55b32e7 394 }
a9a28591
MF
395 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
396 env->regs[2] = tagptr;
397
0200db65 398 uint64_t elf_entry;
4366e1db 399 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
ded625e7
TH
400 &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
401 EM_XTENSA, 0, 0);
0200db65 402 if (success > 0) {
364d4802
MF
403 entry_point = elf_entry;
404 } else {
405 hwaddr ep;
406 int is_linux;
25bda50a 407 success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
6d2e4530 408 translate_phys_addr, cpu);
364d4802
MF
409 if (success > 0 && is_linux) {
410 entry_point = ep;
411 } else {
ebbb419a 412 error_report("could not load kernel '%s'",
364d4802
MF
413 kernel_filename);
414 exit(EXIT_FAILURE);
415 }
416 }
417 if (entry_point != env->pc) {
339ef8fb 418 uint8_t boot[] = {
ee3eb3a7 419#if TARGET_BIG_ENDIAN
339ef8fb
MF
420 0x60, 0x00, 0x08, /* j 1f */
421 0x00, /* .literal_position */
422 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
423 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
424 /* 1: */
425 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
426 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
427 0x0a, 0x00, 0x00, /* jx a0 */
364d4802 428#else
339ef8fb
MF
429 0x06, 0x02, 0x00, /* j 1f */
430 0x00, /* .literal_position */
431 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
432 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
433 /* 1: */
434 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
435 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
436 0xa0, 0x00, 0x00, /* jx a0 */
364d4802
MF
437#endif
438 };
339ef8fb
MF
439 uint32_t entry_pc = tswap32(entry_point);
440 uint32_t entry_a2 = tswap32(tagptr);
441
442 memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
443 memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
444 cpu_physical_memory_write(env->pc, boot, sizeof(boot));
0200db65 445 }
82b25dc8
MF
446 } else {
447 if (flash) {
448 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
449 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
e53fa62c
MF
450 uint32_t size = env->config->sysrom.location[0].size;
451
740ad9f7
MF
452 if (board->flash->size - board->flash->boot_base < size) {
453 size = board->flash->size - board->flash->boot_base;
e53fa62c 454 }
82b25dc8 455
188ce01d 456 memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
740ad9f7 457 flash_mr, board->flash->boot_base, size);
e53fa62c
MF
458 memory_region_add_subregion(system_memory,
459 env->config->sysrom.location[0].addr,
460 flash_io);
461 } else {
462 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
463 system_memory);
82b25dc8 464 }
0200db65
MF
465 }
466}
467
59b5e9bb
MF
468#define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
469
85e2d8d5
MF
470static const hwaddr xtfpga_mmu_io[2] = {
471 0xf0000000,
472};
473
474static const hwaddr xtfpga_nommu_io[2] = {
475 0x90000000,
476 0x70000000,
477};
478
740ad9f7
MF
479static const XtfpgaFlashDesc lx60_flash = {
480 .base = 0x08000000,
481 .size = 0x00400000,
482 .sector_size = 0x10000,
483};
484
188ce01d 485static void xtfpga_lx60_init(MachineState *machine)
0200db65 486{
188ce01d 487 static const XtfpgaBoardDesc lx60_board = {
740ad9f7 488 .flash = &lx60_flash,
82b25dc8 489 .sram_size = 0x20000,
85e2d8d5
MF
490 .io = xtfpga_mmu_io,
491 };
492 xtfpga_init(&lx60_board, machine);
493}
494
495static void xtfpga_lx60_nommu_init(MachineState *machine)
496{
497 static const XtfpgaBoardDesc lx60_board = {
498 .flash = &lx60_flash,
499 .sram_size = 0x20000,
500 .io = xtfpga_nommu_io,
82b25dc8 501 };
188ce01d 502 xtfpga_init(&lx60_board, machine);
82b25dc8
MF
503}
504
740ad9f7
MF
505static const XtfpgaFlashDesc lx200_flash = {
506 .base = 0x08000000,
507 .size = 0x01000000,
508 .sector_size = 0x20000,
509};
510
188ce01d 511static void xtfpga_lx200_init(MachineState *machine)
82b25dc8 512{
188ce01d 513 static const XtfpgaBoardDesc lx200_board = {
740ad9f7 514 .flash = &lx200_flash,
82b25dc8 515 .sram_size = 0x2000000,
85e2d8d5
MF
516 .io = xtfpga_mmu_io,
517 };
518 xtfpga_init(&lx200_board, machine);
519}
520
521static void xtfpga_lx200_nommu_init(MachineState *machine)
522{
523 static const XtfpgaBoardDesc lx200_board = {
524 .flash = &lx200_flash,
525 .sram_size = 0x2000000,
526 .io = xtfpga_nommu_io,
82b25dc8 527 };
188ce01d 528 xtfpga_init(&lx200_board, machine);
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529}
530
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531static const XtfpgaFlashDesc ml605_flash = {
532 .base = 0x08000000,
533 .size = 0x01000000,
534 .sector_size = 0x20000,
535};
536
188ce01d 537static void xtfpga_ml605_init(MachineState *machine)
e0db904d 538{
188ce01d 539 static const XtfpgaBoardDesc ml605_board = {
740ad9f7 540 .flash = &ml605_flash,
e0db904d 541 .sram_size = 0x2000000,
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542 .io = xtfpga_mmu_io,
543 };
544 xtfpga_init(&ml605_board, machine);
545}
546
547static void xtfpga_ml605_nommu_init(MachineState *machine)
548{
549 static const XtfpgaBoardDesc ml605_board = {
550 .flash = &ml605_flash,
551 .sram_size = 0x2000000,
552 .io = xtfpga_nommu_io,
e0db904d 553 };
188ce01d 554 xtfpga_init(&ml605_board, machine);
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555}
556
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557static const XtfpgaFlashDesc kc705_flash = {
558 .base = 0x00000000,
559 .size = 0x08000000,
560 .boot_base = 0x06000000,
561 .sector_size = 0x20000,
562};
563
188ce01d 564static void xtfpga_kc705_init(MachineState *machine)
e0db904d 565{
188ce01d 566 static const XtfpgaBoardDesc kc705_board = {
740ad9f7 567 .flash = &kc705_flash,
e0db904d 568 .sram_size = 0x2000000,
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569 .io = xtfpga_mmu_io,
570 };
571 xtfpga_init(&kc705_board, machine);
572}
573
574static void xtfpga_kc705_nommu_init(MachineState *machine)
575{
576 static const XtfpgaBoardDesc kc705_board = {
577 .flash = &kc705_flash,
578 .sram_size = 0x2000000,
579 .io = xtfpga_nommu_io,
e0db904d 580 };
188ce01d 581 xtfpga_init(&kc705_board, machine);
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582}
583
188ce01d 584static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
e264d29d 585{
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586 MachineClass *mc = MACHINE_CLASS(oc);
587
e264d29d 588 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
188ce01d 589 mc->init = xtfpga_lx60_init;
174e09b7 590 mc->max_cpus = 32;
f83eb10d 591 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
59b5e9bb 592 mc->default_ram_size = 64 * MiB;
e264d29d 593}
0200db65 594
188ce01d 595static const TypeInfo xtfpga_lx60_type = {
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596 .name = MACHINE_TYPE_NAME("lx60"),
597 .parent = TYPE_MACHINE,
188ce01d 598 .class_init = xtfpga_lx60_class_init,
8a661aea 599};
82b25dc8 600
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601static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
602{
603 MachineClass *mc = MACHINE_CLASS(oc);
604
a3c5e49d 605 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
85e2d8d5 606 mc->init = xtfpga_lx60_nommu_init;
174e09b7 607 mc->max_cpus = 32;
a3c5e49d 608 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
59b5e9bb 609 mc->default_ram_size = 64 * MiB;
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610}
611
612static const TypeInfo xtfpga_lx60_nommu_type = {
613 .name = MACHINE_TYPE_NAME("lx60-nommu"),
614 .parent = TYPE_MACHINE,
615 .class_init = xtfpga_lx60_nommu_class_init,
616};
617
188ce01d 618static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
e264d29d 619{
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620 MachineClass *mc = MACHINE_CLASS(oc);
621
e264d29d 622 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
188ce01d 623 mc->init = xtfpga_lx200_init;
174e09b7 624 mc->max_cpus = 32;
f83eb10d 625 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
59b5e9bb 626 mc->default_ram_size = 96 * MiB;
e264d29d 627}
e0db904d 628
188ce01d 629static const TypeInfo xtfpga_lx200_type = {
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630 .name = MACHINE_TYPE_NAME("lx200"),
631 .parent = TYPE_MACHINE,
188ce01d 632 .class_init = xtfpga_lx200_class_init,
8a661aea 633};
e264d29d 634
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635static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
636{
637 MachineClass *mc = MACHINE_CLASS(oc);
638
a3c5e49d 639 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
85e2d8d5 640 mc->init = xtfpga_lx200_nommu_init;
174e09b7 641 mc->max_cpus = 32;
a3c5e49d 642 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
59b5e9bb 643 mc->default_ram_size = 96 * MiB;
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644}
645
646static const TypeInfo xtfpga_lx200_nommu_type = {
647 .name = MACHINE_TYPE_NAME("lx200-nommu"),
648 .parent = TYPE_MACHINE,
649 .class_init = xtfpga_lx200_nommu_class_init,
650};
651
188ce01d 652static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
e264d29d 653{
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654 MachineClass *mc = MACHINE_CLASS(oc);
655
e264d29d 656 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
188ce01d 657 mc->init = xtfpga_ml605_init;
174e09b7 658 mc->max_cpus = 32;
f83eb10d 659 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
59b5e9bb 660 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
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661}
662
188ce01d 663static const TypeInfo xtfpga_ml605_type = {
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664 .name = MACHINE_TYPE_NAME("ml605"),
665 .parent = TYPE_MACHINE,
188ce01d 666 .class_init = xtfpga_ml605_class_init,
8a661aea 667};
e0db904d 668
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669static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
670{
671 MachineClass *mc = MACHINE_CLASS(oc);
672
a3c5e49d 673 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
85e2d8d5 674 mc->init = xtfpga_ml605_nommu_init;
174e09b7 675 mc->max_cpus = 32;
a3c5e49d 676 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
59b5e9bb 677 mc->default_ram_size = 256 * MiB;
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678}
679
680static const TypeInfo xtfpga_ml605_nommu_type = {
681 .name = MACHINE_TYPE_NAME("ml605-nommu"),
682 .parent = TYPE_MACHINE,
683 .class_init = xtfpga_ml605_nommu_class_init,
684};
685
188ce01d 686static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
0200db65 687{
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688 MachineClass *mc = MACHINE_CLASS(oc);
689
e264d29d 690 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
188ce01d 691 mc->init = xtfpga_kc705_init;
174e09b7 692 mc->max_cpus = 32;
f83eb10d 693 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
59b5e9bb 694 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
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695}
696
188ce01d 697static const TypeInfo xtfpga_kc705_type = {
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698 .name = MACHINE_TYPE_NAME("kc705"),
699 .parent = TYPE_MACHINE,
188ce01d 700 .class_init = xtfpga_kc705_class_init,
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701};
702
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703static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
704{
705 MachineClass *mc = MACHINE_CLASS(oc);
706
a3c5e49d 707 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
85e2d8d5 708 mc->init = xtfpga_kc705_nommu_init;
174e09b7 709 mc->max_cpus = 32;
a3c5e49d 710 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
59b5e9bb 711 mc->default_ram_size = 256 * MiB;
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712}
713
714static const TypeInfo xtfpga_kc705_nommu_type = {
715 .name = MACHINE_TYPE_NAME("kc705-nommu"),
716 .parent = TYPE_MACHINE,
717 .class_init = xtfpga_kc705_nommu_class_init,
718};
719
188ce01d 720static void xtfpga_machines_init(void)
8a661aea 721{
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MF
722 type_register_static(&xtfpga_lx60_type);
723 type_register_static(&xtfpga_lx200_type);
724 type_register_static(&xtfpga_ml605_type);
725 type_register_static(&xtfpga_kc705_type);
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726 type_register_static(&xtfpga_lx60_nommu_type);
727 type_register_static(&xtfpga_lx200_nommu_type);
728 type_register_static(&xtfpga_ml605_nommu_type);
729 type_register_static(&xtfpga_kc705_nommu_type);
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730}
731
188ce01d 732type_init(xtfpga_machines_init)