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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
b941329d | 29 | #include "qemu/units.h" |
da34e65c | 30 | #include "qapi/error.h" |
4771d756 | 31 | #include "cpu.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
a27bd6c7 | 35 | #include "hw/qdev-properties.h" |
0200db65 | 36 | #include "elf.h" |
022c62cb PB |
37 | #include "exec/memory.h" |
38 | #include "exec/address-spaces.h" | |
0d09e41a | 39 | #include "hw/char/serial.h" |
1422e32d | 40 | #include "net/net.h" |
83c9f4ca | 41 | #include "hw/sysbus.h" |
0d09e41a | 42 | #include "hw/block/flash.h" |
8228e353 | 43 | #include "chardev/char.h" |
996dfe98 | 44 | #include "sysemu/device_tree.h" |
71e8a915 | 45 | #include "sysemu/reset.h" |
54d31236 | 46 | #include "sysemu/runstate.h" |
8488ab02 | 47 | #include "qemu/error-report.h" |
922a01a0 | 48 | #include "qemu/option.h" |
b707ab75 | 49 | #include "bootparam.h" |
e53fa62c | 50 | #include "xtensa_memory.h" |
1acd90bf | 51 | #include "hw/xtensa/mx_pic.h" |
d6454270 | 52 | #include "migration/vmstate.h" |
82b25dc8 | 53 | |
740ad9f7 MF |
54 | typedef struct XtfpgaFlashDesc { |
55 | hwaddr base; | |
56 | size_t size; | |
57 | size_t boot_base; | |
58 | size_t sector_size; | |
59 | } XtfpgaFlashDesc; | |
60 | ||
188ce01d | 61 | typedef struct XtfpgaBoardDesc { |
740ad9f7 | 62 | const XtfpgaFlashDesc *flash; |
82b25dc8 | 63 | size_t sram_size; |
85e2d8d5 | 64 | const hwaddr *io; |
188ce01d | 65 | } XtfpgaBoardDesc; |
0200db65 | 66 | |
188ce01d | 67 | typedef struct XtfpgaFpgaState { |
0200db65 | 68 | MemoryRegion iomem; |
fff7bf14 | 69 | uint32_t freq; |
0200db65 MF |
70 | uint32_t leds; |
71 | uint32_t switches; | |
188ce01d | 72 | } XtfpgaFpgaState; |
0200db65 | 73 | |
188ce01d | 74 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 75 | { |
188ce01d | 76 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
77 | |
78 | s->leds = 0; | |
79 | s->switches = 0; | |
80 | } | |
81 | ||
188ce01d | 82 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
83 | unsigned size) |
84 | { | |
188ce01d | 85 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
86 | |
87 | switch (addr) { | |
88 | case 0x0: /*build date code*/ | |
556ba668 | 89 | return 0x09272011; |
0200db65 MF |
90 | |
91 | case 0x4: /*processor clock frequency, Hz*/ | |
fff7bf14 | 92 | return s->freq; |
0200db65 MF |
93 | |
94 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
95 | return s->leds; | |
96 | ||
97 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
98 | return s->switches; | |
99 | } | |
100 | return 0; | |
101 | } | |
102 | ||
188ce01d | 103 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
104 | uint64_t val, unsigned size) |
105 | { | |
188ce01d | 106 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
107 | |
108 | switch (addr) { | |
109 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
110 | s->leds = val; | |
111 | break; | |
112 | ||
113 | case 0x10: /*board reset*/ | |
114 | if (val == 0xdead) { | |
cf83f140 | 115 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
116 | } |
117 | break; | |
118 | } | |
119 | } | |
120 | ||
188ce01d MF |
121 | static const MemoryRegionOps xtfpga_fpga_ops = { |
122 | .read = xtfpga_fpga_read, | |
123 | .write = xtfpga_fpga_write, | |
0200db65 MF |
124 | .endianness = DEVICE_NATIVE_ENDIAN, |
125 | }; | |
126 | ||
188ce01d | 127 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
fff7bf14 | 128 | hwaddr base, uint32_t freq) |
0200db65 | 129 | { |
188ce01d | 130 | XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); |
0200db65 | 131 | |
188ce01d | 132 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
fff7bf14 | 133 | "xtfpga.fpga", 0x10000); |
0200db65 | 134 | memory_region_add_subregion(address_space, base, &s->iomem); |
fff7bf14 | 135 | s->freq = freq; |
188ce01d MF |
136 | xtfpga_fpga_reset(s); |
137 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
138 | return s; |
139 | } | |
140 | ||
188ce01d | 141 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
142 | hwaddr base, |
143 | hwaddr descriptors, | |
144 | hwaddr buffers, | |
0200db65 MF |
145 | qemu_irq irq, NICInfo *nd) |
146 | { | |
147 | DeviceState *dev; | |
148 | SysBusDevice *s; | |
149 | MemoryRegion *ram; | |
150 | ||
3e80f690 | 151 | dev = qdev_new("open_eth"); |
0200db65 | 152 | qdev_set_nic_properties(dev, nd); |
0200db65 | 153 | |
1356b98d | 154 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 155 | sysbus_realize_and_unref(s, &error_fatal); |
0200db65 MF |
156 | sysbus_connect_irq(s, 0, irq); |
157 | memory_region_add_subregion(address_space, base, | |
158 | sysbus_mmio_get_region(s, 0)); | |
159 | memory_region_add_subregion(address_space, descriptors, | |
160 | sysbus_mmio_get_region(s, 1)); | |
161 | ||
162 | ram = g_malloc(sizeof(*ram)); | |
b941329d | 163 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, |
f8ed85ac | 164 | &error_fatal); |
c5705a77 | 165 | vmstate_register_ram_global(ram); |
0200db65 MF |
166 | memory_region_add_subregion(address_space, buffers, ram); |
167 | } | |
168 | ||
16434065 MA |
169 | static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, |
170 | const XtfpgaBoardDesc *board, | |
171 | DriveInfo *dinfo, int be) | |
68931a40 MF |
172 | { |
173 | SysBusDevice *s; | |
3e80f690 | 174 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
68931a40 | 175 | |
934df912 | 176 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
68931a40 | 177 | qdev_prop_set_uint32(dev, "num-blocks", |
740ad9f7 MF |
178 | board->flash->size / board->flash->sector_size); |
179 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); | |
f9a555e4 | 180 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 181 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 182 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 | 183 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 184 | sysbus_realize_and_unref(s, &error_fatal); |
740ad9f7 | 185 | memory_region_add_subregion(address_space, board->flash->base, |
68931a40 | 186 | sysbus_mmio_get_region(s, 0)); |
81c7db72 | 187 | return PFLASH_CFI01(dev); |
68931a40 MF |
188 | } |
189 | ||
00b941e5 | 190 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 191 | { |
00b941e5 AF |
192 | XtensaCPU *cpu = opaque; |
193 | ||
194 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
195 | } |
196 | ||
188ce01d | 197 | static void xtfpga_reset(void *opaque) |
0200db65 | 198 | { |
eded1267 | 199 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 200 | |
eded1267 | 201 | cpu_reset(CPU(cpu)); |
0200db65 MF |
202 | } |
203 | ||
188ce01d | 204 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
205 | unsigned size) |
206 | { | |
207 | return 0; | |
208 | } | |
209 | ||
188ce01d | 210 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
211 | uint64_t val, unsigned size) |
212 | { | |
213 | } | |
214 | ||
188ce01d MF |
215 | static const MemoryRegionOps xtfpga_io_ops = { |
216 | .read = xtfpga_io_read, | |
217 | .write = xtfpga_io_write, | |
8bb3b575 MF |
218 | .endianness = DEVICE_NATIVE_ENDIAN, |
219 | }; | |
220 | ||
188ce01d | 221 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 MF |
222 | { |
223 | #ifdef TARGET_WORDS_BIGENDIAN | |
224 | int be = 1; | |
225 | #else | |
226 | int be = 0; | |
227 | #endif | |
228 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 229 | XtensaCPU *cpu = NULL; |
5bfcb36e | 230 | CPUXtensaState *env = NULL; |
e53fa62c | 231 | MemoryRegion *system_io; |
1acd90bf | 232 | XtensaMxPic *mx_pic = NULL; |
66f03d7e | 233 | qemu_irq *extints; |
82b25dc8 | 234 | DriveInfo *dinfo; |
16434065 | 235 | PFlashCFI01 *flash = NULL; |
37b259d0 | 236 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
37b259d0 MF |
237 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
238 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 239 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 240 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
b941329d | 241 | const unsigned system_io_size = 224 * MiB; |
fff7bf14 | 242 | uint32_t freq = 10000000; |
0200db65 | 243 | int n; |
33decbd2 | 244 | unsigned int smp_cpus = machine->smp.cpus; |
0200db65 | 245 | |
1acd90bf MF |
246 | if (smp_cpus > 1) { |
247 | mx_pic = xtensa_mx_pic_init(31); | |
248 | qemu_register_reset(xtensa_mx_pic_reset, mx_pic); | |
249 | } | |
0200db65 | 250 | for (n = 0; n < smp_cpus; n++) { |
288a3f2e MF |
251 | CPUXtensaState *cenv = NULL; |
252 | ||
f83eb10d | 253 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
288a3f2e MF |
254 | cenv = &cpu->env; |
255 | if (!env) { | |
256 | env = cenv; | |
fff7bf14 | 257 | freq = env->config->clock_freq_khz * 1000; |
288a3f2e | 258 | } |
adbb0f75 | 259 | |
1acd90bf MF |
260 | if (mx_pic) { |
261 | MemoryRegion *mx_eri; | |
262 | ||
263 | mx_eri = xtensa_mx_pic_register_cpu(mx_pic, | |
264 | xtensa_get_extints(cenv), | |
265 | xtensa_get_runstall(cenv)); | |
266 | memory_region_add_subregion(xtensa_get_er_region(cenv), | |
267 | 0, mx_eri); | |
268 | } | |
288a3f2e | 269 | cenv->sregs[PRID] = n; |
1acd90bf | 270 | xtensa_select_static_vectors(cenv, n != 0); |
188ce01d | 271 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
272 | /* Need MMU initialized prior to ELF loading, |
273 | * so that ELF gets loaded into virtual addresses | |
274 | */ | |
adbb0f75 | 275 | cpu_reset(CPU(cpu)); |
0200db65 | 276 | } |
1acd90bf MF |
277 | if (smp_cpus > 1) { |
278 | extints = xtensa_mx_pic_get_extints(mx_pic); | |
279 | } else { | |
280 | extints = xtensa_get_extints(env); | |
281 | } | |
0200db65 | 282 | |
e53fa62c MF |
283 | if (env) { |
284 | XtensaMemory sysram = env->config->sysram; | |
285 | ||
286 | sysram.location[0].size = machine->ram_size; | |
287 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
288 | system_memory); | |
289 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
290 | system_memory); | |
291 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
292 | system_memory); | |
293 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
294 | system_memory); | |
295 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
296 | system_memory); | |
297 | } | |
0200db65 | 298 | |
0200db65 | 299 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 300 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
85e2d8d5 MF |
301 | system_io_size); |
302 | memory_region_add_subregion(system_memory, board->io[0], system_io); | |
303 | if (board->io[1]) { | |
304 | MemoryRegion *io = g_malloc(sizeof(*io)); | |
305 | ||
306 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", | |
307 | system_io, 0, system_io_size); | |
308 | memory_region_add_subregion(system_memory, board->io[1], io); | |
309 | } | |
fff7bf14 | 310 | xtfpga_fpga_init(system_io, 0x0d020000, freq); |
a005d073 | 311 | if (nd_table[0].used) { |
188ce01d | 312 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
66f03d7e | 313 | extints[1], nd_table); |
0200db65 MF |
314 | } |
315 | ||
66f03d7e MF |
316 | serial_mm_init(system_io, 0x0d050020, 2, extints[0], |
317 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); | |
0200db65 | 318 | |
82b25dc8 MF |
319 | dinfo = drive_get(IF_PFLASH, 0, 0); |
320 | if (dinfo) { | |
68931a40 | 321 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
322 | } |
323 | ||
324 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 325 | if (kernel_filename) { |
364d4802 | 326 | uint32_t entry_point = env->pc; |
b6edea8b | 327 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
328 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
329 | board->sram_size; | |
a9a28591 | 330 | uint32_t cur_tagptr; |
b6edea8b MF |
331 | BpMemInfo memory_location = { |
332 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
333 | .start = tswap32(env->config->sysram.location[0].addr), |
334 | .end = tswap32(env->config->sysram.location[0].addr + | |
335 | machine->ram_size), | |
b6edea8b | 336 | }; |
996dfe98 MF |
337 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
338 | machine->ram_size : 0x08000000; | |
339 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 340 | |
e53fa62c MF |
341 | lowmem_end += env->config->sysram.location[0].addr; |
342 | cur_lowmem += env->config->sysram.location[0].addr; | |
343 | ||
344 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
345 | system_memory); | |
292627bb | 346 | |
a9a28591 MF |
347 | if (kernel_cmdline) { |
348 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
349 | } | |
996dfe98 MF |
350 | if (dtb_filename) { |
351 | bp_size += get_tag_size(sizeof(uint32_t)); | |
352 | } | |
f55b32e7 MF |
353 | if (initrd_filename) { |
354 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
355 | } | |
a9a28591 | 356 | |
292627bb | 357 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
358 | tagptr = (tagptr - bp_size) & ~0xff; |
359 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
360 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
361 | sizeof(memory_location), &memory_location); | |
a9a28591 | 362 | |
292627bb | 363 | if (kernel_cmdline) { |
a9a28591 MF |
364 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
365 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 366 | } |
0e80359e | 367 | #ifdef CONFIG_FDT |
996dfe98 MF |
368 | if (dtb_filename) { |
369 | int fdt_size; | |
370 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
371 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
372 | ||
373 | if (!fdt) { | |
ebbb419a | 374 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
375 | exit(EXIT_FAILURE); |
376 | } | |
377 | ||
378 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
379 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
380 | sizeof(dtb_addr), &dtb_addr); | |
b941329d | 381 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); |
d1cb6784 | 382 | g_free(fdt); |
996dfe98 | 383 | } |
0e80359e MF |
384 | #else |
385 | if (dtb_filename) { | |
386 | error_report("could not load DTB '%s': " | |
387 | "FDT support is not configured in QEMU", | |
388 | dtb_filename); | |
389 | exit(EXIT_FAILURE); | |
390 | } | |
391 | #endif | |
f55b32e7 MF |
392 | if (initrd_filename) { |
393 | BpMemInfo initrd_location = { 0 }; | |
394 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
395 | lowmem_end - cur_lowmem); | |
396 | ||
397 | if (initrd_size < 0) { | |
398 | initrd_size = load_image_targphys(initrd_filename, | |
399 | cur_lowmem, | |
400 | lowmem_end - cur_lowmem); | |
401 | } | |
402 | if (initrd_size < 0) { | |
ebbb419a | 403 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
404 | exit(EXIT_FAILURE); |
405 | } | |
406 | initrd_location.start = tswap32(cur_lowmem); | |
407 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
408 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
409 | sizeof(initrd_location), &initrd_location); | |
b941329d | 410 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); |
f55b32e7 | 411 | } |
a9a28591 MF |
412 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
413 | env->regs[2] = tagptr; | |
414 | ||
0200db65 | 415 | uint64_t elf_entry; |
4366e1db | 416 | int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, |
617160c9 | 417 | &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); |
0200db65 | 418 | if (success > 0) { |
364d4802 MF |
419 | entry_point = elf_entry; |
420 | } else { | |
421 | hwaddr ep; | |
422 | int is_linux; | |
25bda50a | 423 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 424 | translate_phys_addr, cpu); |
364d4802 MF |
425 | if (success > 0 && is_linux) { |
426 | entry_point = ep; | |
427 | } else { | |
ebbb419a | 428 | error_report("could not load kernel '%s'", |
364d4802 MF |
429 | kernel_filename); |
430 | exit(EXIT_FAILURE); | |
431 | } | |
432 | } | |
433 | if (entry_point != env->pc) { | |
339ef8fb | 434 | uint8_t boot[] = { |
364d4802 | 435 | #ifdef TARGET_WORDS_BIGENDIAN |
339ef8fb MF |
436 | 0x60, 0x00, 0x08, /* j 1f */ |
437 | 0x00, /* .literal_position */ | |
438 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
439 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
440 | /* 1: */ | |
441 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
442 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
443 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 444 | #else |
339ef8fb MF |
445 | 0x06, 0x02, 0x00, /* j 1f */ |
446 | 0x00, /* .literal_position */ | |
447 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
448 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
449 | /* 1: */ | |
450 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
451 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
452 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
453 | #endif |
454 | }; | |
339ef8fb MF |
455 | uint32_t entry_pc = tswap32(entry_point); |
456 | uint32_t entry_a2 = tswap32(tagptr); | |
457 | ||
458 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
459 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
460 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 461 | } |
82b25dc8 MF |
462 | } else { |
463 | if (flash) { | |
464 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
465 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
466 | uint32_t size = env->config->sysrom.location[0].size; |
467 | ||
740ad9f7 MF |
468 | if (board->flash->size - board->flash->boot_base < size) { |
469 | size = board->flash->size - board->flash->boot_base; | |
e53fa62c | 470 | } |
82b25dc8 | 471 | |
188ce01d | 472 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
740ad9f7 | 473 | flash_mr, board->flash->boot_base, size); |
e53fa62c MF |
474 | memory_region_add_subregion(system_memory, |
475 | env->config->sysrom.location[0].addr, | |
476 | flash_io); | |
477 | } else { | |
478 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
479 | system_memory); | |
82b25dc8 | 480 | } |
0200db65 MF |
481 | } |
482 | } | |
483 | ||
59b5e9bb MF |
484 | #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) |
485 | ||
85e2d8d5 MF |
486 | static const hwaddr xtfpga_mmu_io[2] = { |
487 | 0xf0000000, | |
488 | }; | |
489 | ||
490 | static const hwaddr xtfpga_nommu_io[2] = { | |
491 | 0x90000000, | |
492 | 0x70000000, | |
493 | }; | |
494 | ||
740ad9f7 MF |
495 | static const XtfpgaFlashDesc lx60_flash = { |
496 | .base = 0x08000000, | |
497 | .size = 0x00400000, | |
498 | .sector_size = 0x10000, | |
499 | }; | |
500 | ||
188ce01d | 501 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 502 | { |
188ce01d | 503 | static const XtfpgaBoardDesc lx60_board = { |
740ad9f7 | 504 | .flash = &lx60_flash, |
82b25dc8 | 505 | .sram_size = 0x20000, |
85e2d8d5 MF |
506 | .io = xtfpga_mmu_io, |
507 | }; | |
508 | xtfpga_init(&lx60_board, machine); | |
509 | } | |
510 | ||
511 | static void xtfpga_lx60_nommu_init(MachineState *machine) | |
512 | { | |
513 | static const XtfpgaBoardDesc lx60_board = { | |
514 | .flash = &lx60_flash, | |
515 | .sram_size = 0x20000, | |
516 | .io = xtfpga_nommu_io, | |
82b25dc8 | 517 | }; |
188ce01d | 518 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
519 | } |
520 | ||
740ad9f7 MF |
521 | static const XtfpgaFlashDesc lx200_flash = { |
522 | .base = 0x08000000, | |
523 | .size = 0x01000000, | |
524 | .sector_size = 0x20000, | |
525 | }; | |
526 | ||
188ce01d | 527 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 528 | { |
188ce01d | 529 | static const XtfpgaBoardDesc lx200_board = { |
740ad9f7 | 530 | .flash = &lx200_flash, |
82b25dc8 | 531 | .sram_size = 0x2000000, |
85e2d8d5 MF |
532 | .io = xtfpga_mmu_io, |
533 | }; | |
534 | xtfpga_init(&lx200_board, machine); | |
535 | } | |
536 | ||
537 | static void xtfpga_lx200_nommu_init(MachineState *machine) | |
538 | { | |
539 | static const XtfpgaBoardDesc lx200_board = { | |
540 | .flash = &lx200_flash, | |
541 | .sram_size = 0x2000000, | |
542 | .io = xtfpga_nommu_io, | |
82b25dc8 | 543 | }; |
188ce01d | 544 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
545 | } |
546 | ||
740ad9f7 MF |
547 | static const XtfpgaFlashDesc ml605_flash = { |
548 | .base = 0x08000000, | |
549 | .size = 0x01000000, | |
550 | .sector_size = 0x20000, | |
551 | }; | |
552 | ||
188ce01d | 553 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 554 | { |
188ce01d | 555 | static const XtfpgaBoardDesc ml605_board = { |
740ad9f7 | 556 | .flash = &ml605_flash, |
e0db904d | 557 | .sram_size = 0x2000000, |
85e2d8d5 MF |
558 | .io = xtfpga_mmu_io, |
559 | }; | |
560 | xtfpga_init(&ml605_board, machine); | |
561 | } | |
562 | ||
563 | static void xtfpga_ml605_nommu_init(MachineState *machine) | |
564 | { | |
565 | static const XtfpgaBoardDesc ml605_board = { | |
566 | .flash = &ml605_flash, | |
567 | .sram_size = 0x2000000, | |
568 | .io = xtfpga_nommu_io, | |
e0db904d | 569 | }; |
188ce01d | 570 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
571 | } |
572 | ||
740ad9f7 MF |
573 | static const XtfpgaFlashDesc kc705_flash = { |
574 | .base = 0x00000000, | |
575 | .size = 0x08000000, | |
576 | .boot_base = 0x06000000, | |
577 | .sector_size = 0x20000, | |
578 | }; | |
579 | ||
188ce01d | 580 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 581 | { |
188ce01d | 582 | static const XtfpgaBoardDesc kc705_board = { |
740ad9f7 | 583 | .flash = &kc705_flash, |
e0db904d | 584 | .sram_size = 0x2000000, |
85e2d8d5 MF |
585 | .io = xtfpga_mmu_io, |
586 | }; | |
587 | xtfpga_init(&kc705_board, machine); | |
588 | } | |
589 | ||
590 | static void xtfpga_kc705_nommu_init(MachineState *machine) | |
591 | { | |
592 | static const XtfpgaBoardDesc kc705_board = { | |
593 | .flash = &kc705_flash, | |
594 | .sram_size = 0x2000000, | |
595 | .io = xtfpga_nommu_io, | |
e0db904d | 596 | }; |
188ce01d | 597 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
598 | } |
599 | ||
188ce01d | 600 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 601 | { |
8a661aea AF |
602 | MachineClass *mc = MACHINE_CLASS(oc); |
603 | ||
e264d29d | 604 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 605 | mc->init = xtfpga_lx60_init; |
174e09b7 | 606 | mc->max_cpus = 32; |
f83eb10d | 607 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 608 | mc->default_ram_size = 64 * MiB; |
e264d29d | 609 | } |
0200db65 | 610 | |
188ce01d | 611 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
612 | .name = MACHINE_TYPE_NAME("lx60"), |
613 | .parent = TYPE_MACHINE, | |
188ce01d | 614 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 615 | }; |
82b25dc8 | 616 | |
85e2d8d5 MF |
617 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) |
618 | { | |
619 | MachineClass *mc = MACHINE_CLASS(oc); | |
620 | ||
a3c5e49d | 621 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 622 | mc->init = xtfpga_lx60_nommu_init; |
174e09b7 | 623 | mc->max_cpus = 32; |
a3c5e49d | 624 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 625 | mc->default_ram_size = 64 * MiB; |
85e2d8d5 MF |
626 | } |
627 | ||
628 | static const TypeInfo xtfpga_lx60_nommu_type = { | |
629 | .name = MACHINE_TYPE_NAME("lx60-nommu"), | |
630 | .parent = TYPE_MACHINE, | |
631 | .class_init = xtfpga_lx60_nommu_class_init, | |
632 | }; | |
633 | ||
188ce01d | 634 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 635 | { |
8a661aea AF |
636 | MachineClass *mc = MACHINE_CLASS(oc); |
637 | ||
e264d29d | 638 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 639 | mc->init = xtfpga_lx200_init; |
174e09b7 | 640 | mc->max_cpus = 32; |
f83eb10d | 641 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 642 | mc->default_ram_size = 96 * MiB; |
e264d29d | 643 | } |
e0db904d | 644 | |
188ce01d | 645 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
646 | .name = MACHINE_TYPE_NAME("lx200"), |
647 | .parent = TYPE_MACHINE, | |
188ce01d | 648 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 649 | }; |
e264d29d | 650 | |
85e2d8d5 MF |
651 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) |
652 | { | |
653 | MachineClass *mc = MACHINE_CLASS(oc); | |
654 | ||
a3c5e49d | 655 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 656 | mc->init = xtfpga_lx200_nommu_init; |
174e09b7 | 657 | mc->max_cpus = 32; |
a3c5e49d | 658 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 659 | mc->default_ram_size = 96 * MiB; |
85e2d8d5 MF |
660 | } |
661 | ||
662 | static const TypeInfo xtfpga_lx200_nommu_type = { | |
663 | .name = MACHINE_TYPE_NAME("lx200-nommu"), | |
664 | .parent = TYPE_MACHINE, | |
665 | .class_init = xtfpga_lx200_nommu_class_init, | |
666 | }; | |
667 | ||
188ce01d | 668 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 669 | { |
8a661aea AF |
670 | MachineClass *mc = MACHINE_CLASS(oc); |
671 | ||
e264d29d | 672 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 673 | mc->init = xtfpga_ml605_init; |
174e09b7 | 674 | mc->max_cpus = 32; |
f83eb10d | 675 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 676 | mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
e264d29d EH |
677 | } |
678 | ||
188ce01d | 679 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
680 | .name = MACHINE_TYPE_NAME("ml605"), |
681 | .parent = TYPE_MACHINE, | |
188ce01d | 682 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 683 | }; |
e0db904d | 684 | |
85e2d8d5 MF |
685 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) |
686 | { | |
687 | MachineClass *mc = MACHINE_CLASS(oc); | |
688 | ||
a3c5e49d | 689 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 690 | mc->init = xtfpga_ml605_nommu_init; |
174e09b7 | 691 | mc->max_cpus = 32; |
a3c5e49d | 692 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 693 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
694 | } |
695 | ||
696 | static const TypeInfo xtfpga_ml605_nommu_type = { | |
697 | .name = MACHINE_TYPE_NAME("ml605-nommu"), | |
698 | .parent = TYPE_MACHINE, | |
699 | .class_init = xtfpga_ml605_nommu_class_init, | |
700 | }; | |
701 | ||
188ce01d | 702 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 703 | { |
8a661aea AF |
704 | MachineClass *mc = MACHINE_CLASS(oc); |
705 | ||
e264d29d | 706 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 707 | mc->init = xtfpga_kc705_init; |
174e09b7 | 708 | mc->max_cpus = 32; |
f83eb10d | 709 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 710 | mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
0200db65 MF |
711 | } |
712 | ||
188ce01d | 713 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
714 | .name = MACHINE_TYPE_NAME("kc705"), |
715 | .parent = TYPE_MACHINE, | |
188ce01d | 716 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
717 | }; |
718 | ||
85e2d8d5 MF |
719 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) |
720 | { | |
721 | MachineClass *mc = MACHINE_CLASS(oc); | |
722 | ||
a3c5e49d | 723 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 724 | mc->init = xtfpga_kc705_nommu_init; |
174e09b7 | 725 | mc->max_cpus = 32; |
a3c5e49d | 726 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 727 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
728 | } |
729 | ||
730 | static const TypeInfo xtfpga_kc705_nommu_type = { | |
731 | .name = MACHINE_TYPE_NAME("kc705-nommu"), | |
732 | .parent = TYPE_MACHINE, | |
733 | .class_init = xtfpga_kc705_nommu_class_init, | |
734 | }; | |
735 | ||
188ce01d | 736 | static void xtfpga_machines_init(void) |
8a661aea | 737 | { |
188ce01d MF |
738 | type_register_static(&xtfpga_lx60_type); |
739 | type_register_static(&xtfpga_lx200_type); | |
740 | type_register_static(&xtfpga_ml605_type); | |
741 | type_register_static(&xtfpga_kc705_type); | |
85e2d8d5 MF |
742 | type_register_static(&xtfpga_lx60_nommu_type); |
743 | type_register_static(&xtfpga_lx200_nommu_type); | |
744 | type_register_static(&xtfpga_ml605_nommu_type); | |
745 | type_register_static(&xtfpga_kc705_nommu_type); | |
8a661aea AF |
746 | } |
747 | ||
188ce01d | 748 | type_init(xtfpga_machines_init) |