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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
b941329d | 29 | #include "qemu/units.h" |
da34e65c | 30 | #include "qapi/error.h" |
4771d756 | 31 | #include "cpu.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
a27bd6c7 | 35 | #include "hw/qdev-properties.h" |
0200db65 | 36 | #include "elf.h" |
022c62cb | 37 | #include "exec/memory.h" |
0d09e41a | 38 | #include "hw/char/serial.h" |
1422e32d | 39 | #include "net/net.h" |
83c9f4ca | 40 | #include "hw/sysbus.h" |
0d09e41a | 41 | #include "hw/block/flash.h" |
8228e353 | 42 | #include "chardev/char.h" |
996dfe98 | 43 | #include "sysemu/device_tree.h" |
71e8a915 | 44 | #include "sysemu/reset.h" |
54d31236 | 45 | #include "sysemu/runstate.h" |
8488ab02 | 46 | #include "qemu/error-report.h" |
922a01a0 | 47 | #include "qemu/option.h" |
b707ab75 | 48 | #include "bootparam.h" |
e53fa62c | 49 | #include "xtensa_memory.h" |
1acd90bf | 50 | #include "hw/xtensa/mx_pic.h" |
d6454270 | 51 | #include "migration/vmstate.h" |
82b25dc8 | 52 | |
740ad9f7 MF |
53 | typedef struct XtfpgaFlashDesc { |
54 | hwaddr base; | |
55 | size_t size; | |
56 | size_t boot_base; | |
57 | size_t sector_size; | |
58 | } XtfpgaFlashDesc; | |
59 | ||
188ce01d | 60 | typedef struct XtfpgaBoardDesc { |
740ad9f7 | 61 | const XtfpgaFlashDesc *flash; |
82b25dc8 | 62 | size_t sram_size; |
85e2d8d5 | 63 | const hwaddr *io; |
188ce01d | 64 | } XtfpgaBoardDesc; |
0200db65 | 65 | |
188ce01d | 66 | typedef struct XtfpgaFpgaState { |
0200db65 | 67 | MemoryRegion iomem; |
fff7bf14 | 68 | uint32_t freq; |
0200db65 MF |
69 | uint32_t leds; |
70 | uint32_t switches; | |
188ce01d | 71 | } XtfpgaFpgaState; |
0200db65 | 72 | |
188ce01d | 73 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 74 | { |
188ce01d | 75 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
76 | |
77 | s->leds = 0; | |
78 | s->switches = 0; | |
79 | } | |
80 | ||
188ce01d | 81 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
82 | unsigned size) |
83 | { | |
188ce01d | 84 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
85 | |
86 | switch (addr) { | |
87 | case 0x0: /*build date code*/ | |
556ba668 | 88 | return 0x09272011; |
0200db65 MF |
89 | |
90 | case 0x4: /*processor clock frequency, Hz*/ | |
fff7bf14 | 91 | return s->freq; |
0200db65 MF |
92 | |
93 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
94 | return s->leds; | |
95 | ||
96 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
97 | return s->switches; | |
98 | } | |
99 | return 0; | |
100 | } | |
101 | ||
188ce01d | 102 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
103 | uint64_t val, unsigned size) |
104 | { | |
188ce01d | 105 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
106 | |
107 | switch (addr) { | |
108 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
109 | s->leds = val; | |
110 | break; | |
111 | ||
112 | case 0x10: /*board reset*/ | |
113 | if (val == 0xdead) { | |
cf83f140 | 114 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
115 | } |
116 | break; | |
117 | } | |
118 | } | |
119 | ||
188ce01d MF |
120 | static const MemoryRegionOps xtfpga_fpga_ops = { |
121 | .read = xtfpga_fpga_read, | |
122 | .write = xtfpga_fpga_write, | |
0200db65 MF |
123 | .endianness = DEVICE_NATIVE_ENDIAN, |
124 | }; | |
125 | ||
188ce01d | 126 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
fff7bf14 | 127 | hwaddr base, uint32_t freq) |
0200db65 | 128 | { |
b21e2380 | 129 | XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); |
0200db65 | 130 | |
188ce01d | 131 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
fff7bf14 | 132 | "xtfpga.fpga", 0x10000); |
0200db65 | 133 | memory_region_add_subregion(address_space, base, &s->iomem); |
fff7bf14 | 134 | s->freq = freq; |
188ce01d MF |
135 | xtfpga_fpga_reset(s); |
136 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
137 | return s; |
138 | } | |
139 | ||
188ce01d | 140 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
141 | hwaddr base, |
142 | hwaddr descriptors, | |
143 | hwaddr buffers, | |
7db00af6 | 144 | qemu_irq irq) |
0200db65 MF |
145 | { |
146 | DeviceState *dev; | |
147 | SysBusDevice *s; | |
148 | MemoryRegion *ram; | |
149 | ||
7db00af6 DW |
150 | dev = qemu_create_nic_device("open_eth", true, NULL); |
151 | if (!dev) { | |
152 | return; | |
153 | } | |
0200db65 | 154 | |
1356b98d | 155 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 156 | sysbus_realize_and_unref(s, &error_fatal); |
0200db65 MF |
157 | sysbus_connect_irq(s, 0, irq); |
158 | memory_region_add_subregion(address_space, base, | |
159 | sysbus_mmio_get_region(s, 0)); | |
160 | memory_region_add_subregion(address_space, descriptors, | |
161 | sysbus_mmio_get_region(s, 1)); | |
162 | ||
163 | ram = g_malloc(sizeof(*ram)); | |
b941329d | 164 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, |
f8ed85ac | 165 | &error_fatal); |
c5705a77 | 166 | vmstate_register_ram_global(ram); |
0200db65 MF |
167 | memory_region_add_subregion(address_space, buffers, ram); |
168 | } | |
169 | ||
16434065 MA |
170 | static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, |
171 | const XtfpgaBoardDesc *board, | |
172 | DriveInfo *dinfo, int be) | |
68931a40 MF |
173 | { |
174 | SysBusDevice *s; | |
3e80f690 | 175 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
68931a40 | 176 | |
934df912 | 177 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
68931a40 | 178 | qdev_prop_set_uint32(dev, "num-blocks", |
740ad9f7 MF |
179 | board->flash->size / board->flash->sector_size); |
180 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); | |
f9a555e4 | 181 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 182 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 183 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 | 184 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 185 | sysbus_realize_and_unref(s, &error_fatal); |
740ad9f7 | 186 | memory_region_add_subregion(address_space, board->flash->base, |
68931a40 | 187 | sysbus_mmio_get_region(s, 0)); |
81c7db72 | 188 | return PFLASH_CFI01(dev); |
68931a40 MF |
189 | } |
190 | ||
00b941e5 | 191 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 192 | { |
00b941e5 AF |
193 | XtensaCPU *cpu = opaque; |
194 | ||
195 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
196 | } |
197 | ||
188ce01d | 198 | static void xtfpga_reset(void *opaque) |
0200db65 | 199 | { |
eded1267 | 200 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 201 | |
eded1267 | 202 | cpu_reset(CPU(cpu)); |
0200db65 MF |
203 | } |
204 | ||
188ce01d | 205 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
206 | unsigned size) |
207 | { | |
208 | return 0; | |
209 | } | |
210 | ||
188ce01d | 211 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
212 | uint64_t val, unsigned size) |
213 | { | |
214 | } | |
215 | ||
188ce01d MF |
216 | static const MemoryRegionOps xtfpga_io_ops = { |
217 | .read = xtfpga_io_read, | |
218 | .write = xtfpga_io_write, | |
8bb3b575 MF |
219 | .endianness = DEVICE_NATIVE_ENDIAN, |
220 | }; | |
221 | ||
188ce01d | 222 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 | 223 | { |
0200db65 | 224 | MemoryRegion *system_memory = get_system_memory(); |
adbb0f75 | 225 | XtensaCPU *cpu = NULL; |
5bfcb36e | 226 | CPUXtensaState *env = NULL; |
e53fa62c | 227 | MemoryRegion *system_io; |
1acd90bf | 228 | XtensaMxPic *mx_pic = NULL; |
66f03d7e | 229 | qemu_irq *extints; |
82b25dc8 | 230 | DriveInfo *dinfo; |
16434065 | 231 | PFlashCFI01 *flash = NULL; |
f2ce39b4 PB |
232 | const char *kernel_filename = machine->kernel_filename; |
233 | const char *kernel_cmdline = machine->kernel_cmdline; | |
234 | const char *dtb_filename = machine->dtb; | |
235 | const char *initrd_filename = machine->initrd_filename; | |
b941329d | 236 | const unsigned system_io_size = 224 * MiB; |
fff7bf14 | 237 | uint32_t freq = 10000000; |
0200db65 | 238 | int n; |
33decbd2 | 239 | unsigned int smp_cpus = machine->smp.cpus; |
0200db65 | 240 | |
1acd90bf MF |
241 | if (smp_cpus > 1) { |
242 | mx_pic = xtensa_mx_pic_init(31); | |
243 | qemu_register_reset(xtensa_mx_pic_reset, mx_pic); | |
244 | } | |
0200db65 | 245 | for (n = 0; n < smp_cpus; n++) { |
288a3f2e MF |
246 | CPUXtensaState *cenv = NULL; |
247 | ||
f83eb10d | 248 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
288a3f2e MF |
249 | cenv = &cpu->env; |
250 | if (!env) { | |
251 | env = cenv; | |
fff7bf14 | 252 | freq = env->config->clock_freq_khz * 1000; |
288a3f2e | 253 | } |
adbb0f75 | 254 | |
1acd90bf MF |
255 | if (mx_pic) { |
256 | MemoryRegion *mx_eri; | |
257 | ||
258 | mx_eri = xtensa_mx_pic_register_cpu(mx_pic, | |
259 | xtensa_get_extints(cenv), | |
260 | xtensa_get_runstall(cenv)); | |
261 | memory_region_add_subregion(xtensa_get_er_region(cenv), | |
262 | 0, mx_eri); | |
263 | } | |
288a3f2e | 264 | cenv->sregs[PRID] = n; |
1acd90bf | 265 | xtensa_select_static_vectors(cenv, n != 0); |
188ce01d | 266 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
267 | /* Need MMU initialized prior to ELF loading, |
268 | * so that ELF gets loaded into virtual addresses | |
269 | */ | |
adbb0f75 | 270 | cpu_reset(CPU(cpu)); |
0200db65 | 271 | } |
1acd90bf MF |
272 | if (smp_cpus > 1) { |
273 | extints = xtensa_mx_pic_get_extints(mx_pic); | |
274 | } else { | |
275 | extints = xtensa_get_extints(env); | |
276 | } | |
0200db65 | 277 | |
e53fa62c MF |
278 | if (env) { |
279 | XtensaMemory sysram = env->config->sysram; | |
280 | ||
281 | sysram.location[0].size = machine->ram_size; | |
282 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
283 | system_memory); | |
284 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
285 | system_memory); | |
286 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
287 | system_memory); | |
288 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
289 | system_memory); | |
290 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
291 | system_memory); | |
292 | } | |
0200db65 | 293 | |
0200db65 | 294 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 295 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
85e2d8d5 MF |
296 | system_io_size); |
297 | memory_region_add_subregion(system_memory, board->io[0], system_io); | |
298 | if (board->io[1]) { | |
299 | MemoryRegion *io = g_malloc(sizeof(*io)); | |
300 | ||
301 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", | |
302 | system_io, 0, system_io_size); | |
303 | memory_region_add_subregion(system_memory, board->io[1], io); | |
304 | } | |
fff7bf14 | 305 | xtfpga_fpga_init(system_io, 0x0d020000, freq); |
7db00af6 | 306 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]); |
0200db65 | 307 | |
66f03d7e MF |
308 | serial_mm_init(system_io, 0x0d050020, 2, extints[0], |
309 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); | |
0200db65 | 310 | |
82b25dc8 MF |
311 | dinfo = drive_get(IF_PFLASH, 0, 0); |
312 | if (dinfo) { | |
ded625e7 | 313 | flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); |
82b25dc8 MF |
314 | } |
315 | ||
316 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 317 | if (kernel_filename) { |
364d4802 | 318 | uint32_t entry_point = env->pc; |
b6edea8b | 319 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
320 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
321 | board->sram_size; | |
a9a28591 | 322 | uint32_t cur_tagptr; |
b6edea8b MF |
323 | BpMemInfo memory_location = { |
324 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
325 | .start = tswap32(env->config->sysram.location[0].addr), |
326 | .end = tswap32(env->config->sysram.location[0].addr + | |
327 | machine->ram_size), | |
b6edea8b | 328 | }; |
996dfe98 MF |
329 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
330 | machine->ram_size : 0x08000000; | |
331 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 332 | |
e53fa62c MF |
333 | lowmem_end += env->config->sysram.location[0].addr; |
334 | cur_lowmem += env->config->sysram.location[0].addr; | |
335 | ||
336 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
337 | system_memory); | |
292627bb | 338 | |
a9a28591 MF |
339 | if (kernel_cmdline) { |
340 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
341 | } | |
996dfe98 MF |
342 | if (dtb_filename) { |
343 | bp_size += get_tag_size(sizeof(uint32_t)); | |
344 | } | |
f55b32e7 MF |
345 | if (initrd_filename) { |
346 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
347 | } | |
a9a28591 | 348 | |
292627bb | 349 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
350 | tagptr = (tagptr - bp_size) & ~0xff; |
351 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
352 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
353 | sizeof(memory_location), &memory_location); | |
a9a28591 | 354 | |
292627bb | 355 | if (kernel_cmdline) { |
a9a28591 MF |
356 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
357 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 358 | } |
0e80359e | 359 | #ifdef CONFIG_FDT |
996dfe98 MF |
360 | if (dtb_filename) { |
361 | int fdt_size; | |
362 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
363 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
364 | ||
365 | if (!fdt) { | |
ebbb419a | 366 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
367 | exit(EXIT_FAILURE); |
368 | } | |
369 | ||
370 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
371 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
372 | sizeof(dtb_addr), &dtb_addr); | |
b941329d | 373 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); |
d1cb6784 | 374 | g_free(fdt); |
996dfe98 | 375 | } |
0e80359e MF |
376 | #else |
377 | if (dtb_filename) { | |
378 | error_report("could not load DTB '%s': " | |
379 | "FDT support is not configured in QEMU", | |
380 | dtb_filename); | |
381 | exit(EXIT_FAILURE); | |
382 | } | |
383 | #endif | |
f55b32e7 MF |
384 | if (initrd_filename) { |
385 | BpMemInfo initrd_location = { 0 }; | |
386 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
387 | lowmem_end - cur_lowmem); | |
388 | ||
389 | if (initrd_size < 0) { | |
390 | initrd_size = load_image_targphys(initrd_filename, | |
391 | cur_lowmem, | |
392 | lowmem_end - cur_lowmem); | |
393 | } | |
394 | if (initrd_size < 0) { | |
ebbb419a | 395 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
396 | exit(EXIT_FAILURE); |
397 | } | |
398 | initrd_location.start = tswap32(cur_lowmem); | |
399 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
400 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
401 | sizeof(initrd_location), &initrd_location); | |
b941329d | 402 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); |
f55b32e7 | 403 | } |
a9a28591 MF |
404 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
405 | env->regs[2] = tagptr; | |
406 | ||
0200db65 | 407 | uint64_t elf_entry; |
4366e1db | 408 | int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, |
ded625e7 TH |
409 | &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN, |
410 | EM_XTENSA, 0, 0); | |
0200db65 | 411 | if (success > 0) { |
364d4802 MF |
412 | entry_point = elf_entry; |
413 | } else { | |
414 | hwaddr ep; | |
415 | int is_linux; | |
25bda50a | 416 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 417 | translate_phys_addr, cpu); |
364d4802 MF |
418 | if (success > 0 && is_linux) { |
419 | entry_point = ep; | |
420 | } else { | |
ebbb419a | 421 | error_report("could not load kernel '%s'", |
364d4802 MF |
422 | kernel_filename); |
423 | exit(EXIT_FAILURE); | |
424 | } | |
425 | } | |
426 | if (entry_point != env->pc) { | |
339ef8fb | 427 | uint8_t boot[] = { |
ee3eb3a7 | 428 | #if TARGET_BIG_ENDIAN |
339ef8fb MF |
429 | 0x60, 0x00, 0x08, /* j 1f */ |
430 | 0x00, /* .literal_position */ | |
431 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
432 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
433 | /* 1: */ | |
434 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
435 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
436 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 437 | #else |
339ef8fb MF |
438 | 0x06, 0x02, 0x00, /* j 1f */ |
439 | 0x00, /* .literal_position */ | |
440 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
441 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
442 | /* 1: */ | |
443 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
444 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
445 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
446 | #endif |
447 | }; | |
339ef8fb MF |
448 | uint32_t entry_pc = tswap32(entry_point); |
449 | uint32_t entry_a2 = tswap32(tagptr); | |
450 | ||
451 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
452 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
453 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 454 | } |
82b25dc8 MF |
455 | } else { |
456 | if (flash) { | |
457 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
458 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
459 | uint32_t size = env->config->sysrom.location[0].size; |
460 | ||
740ad9f7 MF |
461 | if (board->flash->size - board->flash->boot_base < size) { |
462 | size = board->flash->size - board->flash->boot_base; | |
e53fa62c | 463 | } |
82b25dc8 | 464 | |
188ce01d | 465 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
740ad9f7 | 466 | flash_mr, board->flash->boot_base, size); |
e53fa62c MF |
467 | memory_region_add_subregion(system_memory, |
468 | env->config->sysrom.location[0].addr, | |
469 | flash_io); | |
470 | } else { | |
471 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
472 | system_memory); | |
82b25dc8 | 473 | } |
0200db65 MF |
474 | } |
475 | } | |
476 | ||
59b5e9bb MF |
477 | #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) |
478 | ||
85e2d8d5 MF |
479 | static const hwaddr xtfpga_mmu_io[2] = { |
480 | 0xf0000000, | |
481 | }; | |
482 | ||
483 | static const hwaddr xtfpga_nommu_io[2] = { | |
484 | 0x90000000, | |
485 | 0x70000000, | |
486 | }; | |
487 | ||
740ad9f7 MF |
488 | static const XtfpgaFlashDesc lx60_flash = { |
489 | .base = 0x08000000, | |
490 | .size = 0x00400000, | |
491 | .sector_size = 0x10000, | |
492 | }; | |
493 | ||
188ce01d | 494 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 495 | { |
188ce01d | 496 | static const XtfpgaBoardDesc lx60_board = { |
740ad9f7 | 497 | .flash = &lx60_flash, |
82b25dc8 | 498 | .sram_size = 0x20000, |
85e2d8d5 MF |
499 | .io = xtfpga_mmu_io, |
500 | }; | |
501 | xtfpga_init(&lx60_board, machine); | |
502 | } | |
503 | ||
504 | static void xtfpga_lx60_nommu_init(MachineState *machine) | |
505 | { | |
506 | static const XtfpgaBoardDesc lx60_board = { | |
507 | .flash = &lx60_flash, | |
508 | .sram_size = 0x20000, | |
509 | .io = xtfpga_nommu_io, | |
82b25dc8 | 510 | }; |
188ce01d | 511 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
512 | } |
513 | ||
740ad9f7 MF |
514 | static const XtfpgaFlashDesc lx200_flash = { |
515 | .base = 0x08000000, | |
516 | .size = 0x01000000, | |
517 | .sector_size = 0x20000, | |
518 | }; | |
519 | ||
188ce01d | 520 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 521 | { |
188ce01d | 522 | static const XtfpgaBoardDesc lx200_board = { |
740ad9f7 | 523 | .flash = &lx200_flash, |
82b25dc8 | 524 | .sram_size = 0x2000000, |
85e2d8d5 MF |
525 | .io = xtfpga_mmu_io, |
526 | }; | |
527 | xtfpga_init(&lx200_board, machine); | |
528 | } | |
529 | ||
530 | static void xtfpga_lx200_nommu_init(MachineState *machine) | |
531 | { | |
532 | static const XtfpgaBoardDesc lx200_board = { | |
533 | .flash = &lx200_flash, | |
534 | .sram_size = 0x2000000, | |
535 | .io = xtfpga_nommu_io, | |
82b25dc8 | 536 | }; |
188ce01d | 537 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
538 | } |
539 | ||
740ad9f7 MF |
540 | static const XtfpgaFlashDesc ml605_flash = { |
541 | .base = 0x08000000, | |
542 | .size = 0x01000000, | |
543 | .sector_size = 0x20000, | |
544 | }; | |
545 | ||
188ce01d | 546 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 547 | { |
188ce01d | 548 | static const XtfpgaBoardDesc ml605_board = { |
740ad9f7 | 549 | .flash = &ml605_flash, |
e0db904d | 550 | .sram_size = 0x2000000, |
85e2d8d5 MF |
551 | .io = xtfpga_mmu_io, |
552 | }; | |
553 | xtfpga_init(&ml605_board, machine); | |
554 | } | |
555 | ||
556 | static void xtfpga_ml605_nommu_init(MachineState *machine) | |
557 | { | |
558 | static const XtfpgaBoardDesc ml605_board = { | |
559 | .flash = &ml605_flash, | |
560 | .sram_size = 0x2000000, | |
561 | .io = xtfpga_nommu_io, | |
e0db904d | 562 | }; |
188ce01d | 563 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
564 | } |
565 | ||
740ad9f7 MF |
566 | static const XtfpgaFlashDesc kc705_flash = { |
567 | .base = 0x00000000, | |
568 | .size = 0x08000000, | |
569 | .boot_base = 0x06000000, | |
570 | .sector_size = 0x20000, | |
571 | }; | |
572 | ||
188ce01d | 573 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 574 | { |
188ce01d | 575 | static const XtfpgaBoardDesc kc705_board = { |
740ad9f7 | 576 | .flash = &kc705_flash, |
e0db904d | 577 | .sram_size = 0x2000000, |
85e2d8d5 MF |
578 | .io = xtfpga_mmu_io, |
579 | }; | |
580 | xtfpga_init(&kc705_board, machine); | |
581 | } | |
582 | ||
583 | static void xtfpga_kc705_nommu_init(MachineState *machine) | |
584 | { | |
585 | static const XtfpgaBoardDesc kc705_board = { | |
586 | .flash = &kc705_flash, | |
587 | .sram_size = 0x2000000, | |
588 | .io = xtfpga_nommu_io, | |
e0db904d | 589 | }; |
188ce01d | 590 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
591 | } |
592 | ||
188ce01d | 593 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 594 | { |
8a661aea AF |
595 | MachineClass *mc = MACHINE_CLASS(oc); |
596 | ||
e264d29d | 597 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 598 | mc->init = xtfpga_lx60_init; |
174e09b7 | 599 | mc->max_cpus = 32; |
f83eb10d | 600 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 601 | mc->default_ram_size = 64 * MiB; |
e264d29d | 602 | } |
0200db65 | 603 | |
188ce01d | 604 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
605 | .name = MACHINE_TYPE_NAME("lx60"), |
606 | .parent = TYPE_MACHINE, | |
188ce01d | 607 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 608 | }; |
82b25dc8 | 609 | |
85e2d8d5 MF |
610 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) |
611 | { | |
612 | MachineClass *mc = MACHINE_CLASS(oc); | |
613 | ||
a3c5e49d | 614 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 615 | mc->init = xtfpga_lx60_nommu_init; |
174e09b7 | 616 | mc->max_cpus = 32; |
a3c5e49d | 617 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 618 | mc->default_ram_size = 64 * MiB; |
85e2d8d5 MF |
619 | } |
620 | ||
621 | static const TypeInfo xtfpga_lx60_nommu_type = { | |
622 | .name = MACHINE_TYPE_NAME("lx60-nommu"), | |
623 | .parent = TYPE_MACHINE, | |
624 | .class_init = xtfpga_lx60_nommu_class_init, | |
625 | }; | |
626 | ||
188ce01d | 627 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 628 | { |
8a661aea AF |
629 | MachineClass *mc = MACHINE_CLASS(oc); |
630 | ||
e264d29d | 631 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 632 | mc->init = xtfpga_lx200_init; |
174e09b7 | 633 | mc->max_cpus = 32; |
f83eb10d | 634 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 635 | mc->default_ram_size = 96 * MiB; |
e264d29d | 636 | } |
e0db904d | 637 | |
188ce01d | 638 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
639 | .name = MACHINE_TYPE_NAME("lx200"), |
640 | .parent = TYPE_MACHINE, | |
188ce01d | 641 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 642 | }; |
e264d29d | 643 | |
85e2d8d5 MF |
644 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) |
645 | { | |
646 | MachineClass *mc = MACHINE_CLASS(oc); | |
647 | ||
a3c5e49d | 648 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 649 | mc->init = xtfpga_lx200_nommu_init; |
174e09b7 | 650 | mc->max_cpus = 32; |
a3c5e49d | 651 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 652 | mc->default_ram_size = 96 * MiB; |
85e2d8d5 MF |
653 | } |
654 | ||
655 | static const TypeInfo xtfpga_lx200_nommu_type = { | |
656 | .name = MACHINE_TYPE_NAME("lx200-nommu"), | |
657 | .parent = TYPE_MACHINE, | |
658 | .class_init = xtfpga_lx200_nommu_class_init, | |
659 | }; | |
660 | ||
188ce01d | 661 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 662 | { |
8a661aea AF |
663 | MachineClass *mc = MACHINE_CLASS(oc); |
664 | ||
e264d29d | 665 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 666 | mc->init = xtfpga_ml605_init; |
174e09b7 | 667 | mc->max_cpus = 32; |
f83eb10d | 668 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 669 | mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
e264d29d EH |
670 | } |
671 | ||
188ce01d | 672 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
673 | .name = MACHINE_TYPE_NAME("ml605"), |
674 | .parent = TYPE_MACHINE, | |
188ce01d | 675 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 676 | }; |
e0db904d | 677 | |
85e2d8d5 MF |
678 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) |
679 | { | |
680 | MachineClass *mc = MACHINE_CLASS(oc); | |
681 | ||
a3c5e49d | 682 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 683 | mc->init = xtfpga_ml605_nommu_init; |
174e09b7 | 684 | mc->max_cpus = 32; |
a3c5e49d | 685 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 686 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
687 | } |
688 | ||
689 | static const TypeInfo xtfpga_ml605_nommu_type = { | |
690 | .name = MACHINE_TYPE_NAME("ml605-nommu"), | |
691 | .parent = TYPE_MACHINE, | |
692 | .class_init = xtfpga_ml605_nommu_class_init, | |
693 | }; | |
694 | ||
188ce01d | 695 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 696 | { |
8a661aea AF |
697 | MachineClass *mc = MACHINE_CLASS(oc); |
698 | ||
e264d29d | 699 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 700 | mc->init = xtfpga_kc705_init; |
174e09b7 | 701 | mc->max_cpus = 32; |
f83eb10d | 702 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 703 | mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
0200db65 MF |
704 | } |
705 | ||
188ce01d | 706 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
707 | .name = MACHINE_TYPE_NAME("kc705"), |
708 | .parent = TYPE_MACHINE, | |
188ce01d | 709 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
710 | }; |
711 | ||
85e2d8d5 MF |
712 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) |
713 | { | |
714 | MachineClass *mc = MACHINE_CLASS(oc); | |
715 | ||
a3c5e49d | 716 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 717 | mc->init = xtfpga_kc705_nommu_init; |
174e09b7 | 718 | mc->max_cpus = 32; |
a3c5e49d | 719 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 720 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
721 | } |
722 | ||
723 | static const TypeInfo xtfpga_kc705_nommu_type = { | |
724 | .name = MACHINE_TYPE_NAME("kc705-nommu"), | |
725 | .parent = TYPE_MACHINE, | |
726 | .class_init = xtfpga_kc705_nommu_class_init, | |
727 | }; | |
728 | ||
188ce01d | 729 | static void xtfpga_machines_init(void) |
8a661aea | 730 | { |
188ce01d MF |
731 | type_register_static(&xtfpga_lx60_type); |
732 | type_register_static(&xtfpga_lx200_type); | |
733 | type_register_static(&xtfpga_ml605_type); | |
734 | type_register_static(&xtfpga_kc705_type); | |
85e2d8d5 MF |
735 | type_register_static(&xtfpga_lx60_nommu_type); |
736 | type_register_static(&xtfpga_lx200_nommu_type); | |
737 | type_register_static(&xtfpga_ml605_nommu_type); | |
738 | type_register_static(&xtfpga_kc705_nommu_type); | |
8a661aea AF |
739 | } |
740 | ||
188ce01d | 741 | type_init(xtfpga_machines_init) |