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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
b941329d | 29 | #include "qemu/units.h" |
da34e65c | 30 | #include "qapi/error.h" |
4771d756 | 31 | #include "cpu.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
0200db65 | 35 | #include "elf.h" |
022c62cb PB |
36 | #include "exec/memory.h" |
37 | #include "exec/address-spaces.h" | |
0d09e41a | 38 | #include "hw/char/serial.h" |
1422e32d | 39 | #include "net/net.h" |
83c9f4ca | 40 | #include "hw/sysbus.h" |
0d09e41a | 41 | #include "hw/block/flash.h" |
8228e353 | 42 | #include "chardev/char.h" |
996dfe98 | 43 | #include "sysemu/device_tree.h" |
71e8a915 | 44 | #include "sysemu/reset.h" |
8488ab02 | 45 | #include "qemu/error-report.h" |
922a01a0 | 46 | #include "qemu/option.h" |
b707ab75 | 47 | #include "bootparam.h" |
e53fa62c | 48 | #include "xtensa_memory.h" |
1acd90bf | 49 | #include "hw/xtensa/mx_pic.h" |
d6454270 | 50 | #include "migration/vmstate.h" |
82b25dc8 | 51 | |
740ad9f7 MF |
52 | typedef struct XtfpgaFlashDesc { |
53 | hwaddr base; | |
54 | size_t size; | |
55 | size_t boot_base; | |
56 | size_t sector_size; | |
57 | } XtfpgaFlashDesc; | |
58 | ||
188ce01d | 59 | typedef struct XtfpgaBoardDesc { |
740ad9f7 | 60 | const XtfpgaFlashDesc *flash; |
82b25dc8 | 61 | size_t sram_size; |
85e2d8d5 | 62 | const hwaddr *io; |
188ce01d | 63 | } XtfpgaBoardDesc; |
0200db65 | 64 | |
188ce01d | 65 | typedef struct XtfpgaFpgaState { |
0200db65 | 66 | MemoryRegion iomem; |
fff7bf14 | 67 | uint32_t freq; |
0200db65 MF |
68 | uint32_t leds; |
69 | uint32_t switches; | |
188ce01d | 70 | } XtfpgaFpgaState; |
0200db65 | 71 | |
188ce01d | 72 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 73 | { |
188ce01d | 74 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
75 | |
76 | s->leds = 0; | |
77 | s->switches = 0; | |
78 | } | |
79 | ||
188ce01d | 80 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
81 | unsigned size) |
82 | { | |
188ce01d | 83 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
84 | |
85 | switch (addr) { | |
86 | case 0x0: /*build date code*/ | |
556ba668 | 87 | return 0x09272011; |
0200db65 MF |
88 | |
89 | case 0x4: /*processor clock frequency, Hz*/ | |
fff7bf14 | 90 | return s->freq; |
0200db65 MF |
91 | |
92 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
93 | return s->leds; | |
94 | ||
95 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
96 | return s->switches; | |
97 | } | |
98 | return 0; | |
99 | } | |
100 | ||
188ce01d | 101 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
102 | uint64_t val, unsigned size) |
103 | { | |
188ce01d | 104 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
105 | |
106 | switch (addr) { | |
107 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
108 | s->leds = val; | |
109 | break; | |
110 | ||
111 | case 0x10: /*board reset*/ | |
112 | if (val == 0xdead) { | |
cf83f140 | 113 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
114 | } |
115 | break; | |
116 | } | |
117 | } | |
118 | ||
188ce01d MF |
119 | static const MemoryRegionOps xtfpga_fpga_ops = { |
120 | .read = xtfpga_fpga_read, | |
121 | .write = xtfpga_fpga_write, | |
0200db65 MF |
122 | .endianness = DEVICE_NATIVE_ENDIAN, |
123 | }; | |
124 | ||
188ce01d | 125 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
fff7bf14 | 126 | hwaddr base, uint32_t freq) |
0200db65 | 127 | { |
188ce01d | 128 | XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); |
0200db65 | 129 | |
188ce01d | 130 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
fff7bf14 | 131 | "xtfpga.fpga", 0x10000); |
0200db65 | 132 | memory_region_add_subregion(address_space, base, &s->iomem); |
fff7bf14 | 133 | s->freq = freq; |
188ce01d MF |
134 | xtfpga_fpga_reset(s); |
135 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
136 | return s; |
137 | } | |
138 | ||
188ce01d | 139 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
140 | hwaddr base, |
141 | hwaddr descriptors, | |
142 | hwaddr buffers, | |
0200db65 MF |
143 | qemu_irq irq, NICInfo *nd) |
144 | { | |
145 | DeviceState *dev; | |
146 | SysBusDevice *s; | |
147 | MemoryRegion *ram; | |
148 | ||
149 | dev = qdev_create(NULL, "open_eth"); | |
150 | qdev_set_nic_properties(dev, nd); | |
151 | qdev_init_nofail(dev); | |
152 | ||
1356b98d | 153 | s = SYS_BUS_DEVICE(dev); |
0200db65 MF |
154 | sysbus_connect_irq(s, 0, irq); |
155 | memory_region_add_subregion(address_space, base, | |
156 | sysbus_mmio_get_region(s, 0)); | |
157 | memory_region_add_subregion(address_space, descriptors, | |
158 | sysbus_mmio_get_region(s, 1)); | |
159 | ||
160 | ram = g_malloc(sizeof(*ram)); | |
b941329d | 161 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, |
f8ed85ac | 162 | &error_fatal); |
c5705a77 | 163 | vmstate_register_ram_global(ram); |
0200db65 MF |
164 | memory_region_add_subregion(address_space, buffers, ram); |
165 | } | |
166 | ||
16434065 MA |
167 | static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, |
168 | const XtfpgaBoardDesc *board, | |
169 | DriveInfo *dinfo, int be) | |
68931a40 MF |
170 | { |
171 | SysBusDevice *s; | |
81c7db72 | 172 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); |
68931a40 MF |
173 | |
174 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
175 | &error_abort); | |
176 | qdev_prop_set_uint32(dev, "num-blocks", | |
740ad9f7 MF |
177 | board->flash->size / board->flash->sector_size); |
178 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); | |
f9a555e4 | 179 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 180 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 181 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 MF |
182 | qdev_init_nofail(dev); |
183 | s = SYS_BUS_DEVICE(dev); | |
740ad9f7 | 184 | memory_region_add_subregion(address_space, board->flash->base, |
68931a40 | 185 | sysbus_mmio_get_region(s, 0)); |
81c7db72 | 186 | return PFLASH_CFI01(dev); |
68931a40 MF |
187 | } |
188 | ||
00b941e5 | 189 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 190 | { |
00b941e5 AF |
191 | XtensaCPU *cpu = opaque; |
192 | ||
193 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
194 | } |
195 | ||
188ce01d | 196 | static void xtfpga_reset(void *opaque) |
0200db65 | 197 | { |
eded1267 | 198 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 199 | |
eded1267 | 200 | cpu_reset(CPU(cpu)); |
0200db65 MF |
201 | } |
202 | ||
188ce01d | 203 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
204 | unsigned size) |
205 | { | |
206 | return 0; | |
207 | } | |
208 | ||
188ce01d | 209 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
210 | uint64_t val, unsigned size) |
211 | { | |
212 | } | |
213 | ||
188ce01d MF |
214 | static const MemoryRegionOps xtfpga_io_ops = { |
215 | .read = xtfpga_io_read, | |
216 | .write = xtfpga_io_write, | |
8bb3b575 MF |
217 | .endianness = DEVICE_NATIVE_ENDIAN, |
218 | }; | |
219 | ||
188ce01d | 220 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 MF |
221 | { |
222 | #ifdef TARGET_WORDS_BIGENDIAN | |
223 | int be = 1; | |
224 | #else | |
225 | int be = 0; | |
226 | #endif | |
227 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 228 | XtensaCPU *cpu = NULL; |
5bfcb36e | 229 | CPUXtensaState *env = NULL; |
e53fa62c | 230 | MemoryRegion *system_io; |
1acd90bf | 231 | XtensaMxPic *mx_pic = NULL; |
66f03d7e | 232 | qemu_irq *extints; |
82b25dc8 | 233 | DriveInfo *dinfo; |
16434065 | 234 | PFlashCFI01 *flash = NULL; |
37b259d0 | 235 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
37b259d0 MF |
236 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
237 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 238 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 239 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
b941329d | 240 | const unsigned system_io_size = 224 * MiB; |
fff7bf14 | 241 | uint32_t freq = 10000000; |
0200db65 | 242 | int n; |
33decbd2 | 243 | unsigned int smp_cpus = machine->smp.cpus; |
0200db65 | 244 | |
1acd90bf MF |
245 | if (smp_cpus > 1) { |
246 | mx_pic = xtensa_mx_pic_init(31); | |
247 | qemu_register_reset(xtensa_mx_pic_reset, mx_pic); | |
248 | } | |
0200db65 | 249 | for (n = 0; n < smp_cpus; n++) { |
288a3f2e MF |
250 | CPUXtensaState *cenv = NULL; |
251 | ||
f83eb10d | 252 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
288a3f2e MF |
253 | cenv = &cpu->env; |
254 | if (!env) { | |
255 | env = cenv; | |
fff7bf14 | 256 | freq = env->config->clock_freq_khz * 1000; |
288a3f2e | 257 | } |
adbb0f75 | 258 | |
1acd90bf MF |
259 | if (mx_pic) { |
260 | MemoryRegion *mx_eri; | |
261 | ||
262 | mx_eri = xtensa_mx_pic_register_cpu(mx_pic, | |
263 | xtensa_get_extints(cenv), | |
264 | xtensa_get_runstall(cenv)); | |
265 | memory_region_add_subregion(xtensa_get_er_region(cenv), | |
266 | 0, mx_eri); | |
267 | } | |
288a3f2e | 268 | cenv->sregs[PRID] = n; |
1acd90bf | 269 | xtensa_select_static_vectors(cenv, n != 0); |
188ce01d | 270 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
271 | /* Need MMU initialized prior to ELF loading, |
272 | * so that ELF gets loaded into virtual addresses | |
273 | */ | |
adbb0f75 | 274 | cpu_reset(CPU(cpu)); |
0200db65 | 275 | } |
1acd90bf MF |
276 | if (smp_cpus > 1) { |
277 | extints = xtensa_mx_pic_get_extints(mx_pic); | |
278 | } else { | |
279 | extints = xtensa_get_extints(env); | |
280 | } | |
0200db65 | 281 | |
e53fa62c MF |
282 | if (env) { |
283 | XtensaMemory sysram = env->config->sysram; | |
284 | ||
285 | sysram.location[0].size = machine->ram_size; | |
286 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
287 | system_memory); | |
288 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
289 | system_memory); | |
290 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
291 | system_memory); | |
292 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
293 | system_memory); | |
294 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
295 | system_memory); | |
296 | } | |
0200db65 | 297 | |
0200db65 | 298 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 299 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
85e2d8d5 MF |
300 | system_io_size); |
301 | memory_region_add_subregion(system_memory, board->io[0], system_io); | |
302 | if (board->io[1]) { | |
303 | MemoryRegion *io = g_malloc(sizeof(*io)); | |
304 | ||
305 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", | |
306 | system_io, 0, system_io_size); | |
307 | memory_region_add_subregion(system_memory, board->io[1], io); | |
308 | } | |
fff7bf14 | 309 | xtfpga_fpga_init(system_io, 0x0d020000, freq); |
a005d073 | 310 | if (nd_table[0].used) { |
188ce01d | 311 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
66f03d7e | 312 | extints[1], nd_table); |
0200db65 MF |
313 | } |
314 | ||
66f03d7e MF |
315 | serial_mm_init(system_io, 0x0d050020, 2, extints[0], |
316 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); | |
0200db65 | 317 | |
82b25dc8 MF |
318 | dinfo = drive_get(IF_PFLASH, 0, 0); |
319 | if (dinfo) { | |
68931a40 | 320 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
321 | } |
322 | ||
323 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 324 | if (kernel_filename) { |
364d4802 | 325 | uint32_t entry_point = env->pc; |
b6edea8b | 326 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
327 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
328 | board->sram_size; | |
a9a28591 | 329 | uint32_t cur_tagptr; |
b6edea8b MF |
330 | BpMemInfo memory_location = { |
331 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
332 | .start = tswap32(env->config->sysram.location[0].addr), |
333 | .end = tswap32(env->config->sysram.location[0].addr + | |
334 | machine->ram_size), | |
b6edea8b | 335 | }; |
996dfe98 MF |
336 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
337 | machine->ram_size : 0x08000000; | |
338 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 339 | |
e53fa62c MF |
340 | lowmem_end += env->config->sysram.location[0].addr; |
341 | cur_lowmem += env->config->sysram.location[0].addr; | |
342 | ||
343 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
344 | system_memory); | |
292627bb | 345 | |
a9a28591 MF |
346 | if (kernel_cmdline) { |
347 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
348 | } | |
996dfe98 MF |
349 | if (dtb_filename) { |
350 | bp_size += get_tag_size(sizeof(uint32_t)); | |
351 | } | |
f55b32e7 MF |
352 | if (initrd_filename) { |
353 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
354 | } | |
a9a28591 | 355 | |
292627bb | 356 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
357 | tagptr = (tagptr - bp_size) & ~0xff; |
358 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
359 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
360 | sizeof(memory_location), &memory_location); | |
a9a28591 | 361 | |
292627bb | 362 | if (kernel_cmdline) { |
a9a28591 MF |
363 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
364 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 365 | } |
0e80359e | 366 | #ifdef CONFIG_FDT |
996dfe98 MF |
367 | if (dtb_filename) { |
368 | int fdt_size; | |
369 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
370 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
371 | ||
372 | if (!fdt) { | |
ebbb419a | 373 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
374 | exit(EXIT_FAILURE); |
375 | } | |
376 | ||
377 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
378 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
379 | sizeof(dtb_addr), &dtb_addr); | |
b941329d | 380 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); |
996dfe98 | 381 | } |
0e80359e MF |
382 | #else |
383 | if (dtb_filename) { | |
384 | error_report("could not load DTB '%s': " | |
385 | "FDT support is not configured in QEMU", | |
386 | dtb_filename); | |
387 | exit(EXIT_FAILURE); | |
388 | } | |
389 | #endif | |
f55b32e7 MF |
390 | if (initrd_filename) { |
391 | BpMemInfo initrd_location = { 0 }; | |
392 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
393 | lowmem_end - cur_lowmem); | |
394 | ||
395 | if (initrd_size < 0) { | |
396 | initrd_size = load_image_targphys(initrd_filename, | |
397 | cur_lowmem, | |
398 | lowmem_end - cur_lowmem); | |
399 | } | |
400 | if (initrd_size < 0) { | |
ebbb419a | 401 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
402 | exit(EXIT_FAILURE); |
403 | } | |
404 | initrd_location.start = tswap32(cur_lowmem); | |
405 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
406 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
407 | sizeof(initrd_location), &initrd_location); | |
b941329d | 408 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); |
f55b32e7 | 409 | } |
a9a28591 MF |
410 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
411 | env->regs[2] = tagptr; | |
412 | ||
0200db65 MF |
413 | uint64_t elf_entry; |
414 | uint64_t elf_lowaddr; | |
4366e1db | 415 | int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, |
7ef295ea | 416 | &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); |
0200db65 | 417 | if (success > 0) { |
364d4802 MF |
418 | entry_point = elf_entry; |
419 | } else { | |
420 | hwaddr ep; | |
421 | int is_linux; | |
25bda50a | 422 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 423 | translate_phys_addr, cpu); |
364d4802 MF |
424 | if (success > 0 && is_linux) { |
425 | entry_point = ep; | |
426 | } else { | |
ebbb419a | 427 | error_report("could not load kernel '%s'", |
364d4802 MF |
428 | kernel_filename); |
429 | exit(EXIT_FAILURE); | |
430 | } | |
431 | } | |
432 | if (entry_point != env->pc) { | |
339ef8fb | 433 | uint8_t boot[] = { |
364d4802 | 434 | #ifdef TARGET_WORDS_BIGENDIAN |
339ef8fb MF |
435 | 0x60, 0x00, 0x08, /* j 1f */ |
436 | 0x00, /* .literal_position */ | |
437 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
438 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
439 | /* 1: */ | |
440 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
441 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
442 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 443 | #else |
339ef8fb MF |
444 | 0x06, 0x02, 0x00, /* j 1f */ |
445 | 0x00, /* .literal_position */ | |
446 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
447 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
448 | /* 1: */ | |
449 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
450 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
451 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
452 | #endif |
453 | }; | |
339ef8fb MF |
454 | uint32_t entry_pc = tswap32(entry_point); |
455 | uint32_t entry_a2 = tswap32(tagptr); | |
456 | ||
457 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
458 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
459 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 460 | } |
82b25dc8 MF |
461 | } else { |
462 | if (flash) { | |
463 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
464 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
465 | uint32_t size = env->config->sysrom.location[0].size; |
466 | ||
740ad9f7 MF |
467 | if (board->flash->size - board->flash->boot_base < size) { |
468 | size = board->flash->size - board->flash->boot_base; | |
e53fa62c | 469 | } |
82b25dc8 | 470 | |
188ce01d | 471 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
740ad9f7 | 472 | flash_mr, board->flash->boot_base, size); |
e53fa62c MF |
473 | memory_region_add_subregion(system_memory, |
474 | env->config->sysrom.location[0].addr, | |
475 | flash_io); | |
476 | } else { | |
477 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
478 | system_memory); | |
82b25dc8 | 479 | } |
0200db65 MF |
480 | } |
481 | } | |
482 | ||
59b5e9bb MF |
483 | #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) |
484 | ||
85e2d8d5 MF |
485 | static const hwaddr xtfpga_mmu_io[2] = { |
486 | 0xf0000000, | |
487 | }; | |
488 | ||
489 | static const hwaddr xtfpga_nommu_io[2] = { | |
490 | 0x90000000, | |
491 | 0x70000000, | |
492 | }; | |
493 | ||
740ad9f7 MF |
494 | static const XtfpgaFlashDesc lx60_flash = { |
495 | .base = 0x08000000, | |
496 | .size = 0x00400000, | |
497 | .sector_size = 0x10000, | |
498 | }; | |
499 | ||
188ce01d | 500 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 501 | { |
188ce01d | 502 | static const XtfpgaBoardDesc lx60_board = { |
740ad9f7 | 503 | .flash = &lx60_flash, |
82b25dc8 | 504 | .sram_size = 0x20000, |
85e2d8d5 MF |
505 | .io = xtfpga_mmu_io, |
506 | }; | |
507 | xtfpga_init(&lx60_board, machine); | |
508 | } | |
509 | ||
510 | static void xtfpga_lx60_nommu_init(MachineState *machine) | |
511 | { | |
512 | static const XtfpgaBoardDesc lx60_board = { | |
513 | .flash = &lx60_flash, | |
514 | .sram_size = 0x20000, | |
515 | .io = xtfpga_nommu_io, | |
82b25dc8 | 516 | }; |
188ce01d | 517 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
518 | } |
519 | ||
740ad9f7 MF |
520 | static const XtfpgaFlashDesc lx200_flash = { |
521 | .base = 0x08000000, | |
522 | .size = 0x01000000, | |
523 | .sector_size = 0x20000, | |
524 | }; | |
525 | ||
188ce01d | 526 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 527 | { |
188ce01d | 528 | static const XtfpgaBoardDesc lx200_board = { |
740ad9f7 | 529 | .flash = &lx200_flash, |
82b25dc8 | 530 | .sram_size = 0x2000000, |
85e2d8d5 MF |
531 | .io = xtfpga_mmu_io, |
532 | }; | |
533 | xtfpga_init(&lx200_board, machine); | |
534 | } | |
535 | ||
536 | static void xtfpga_lx200_nommu_init(MachineState *machine) | |
537 | { | |
538 | static const XtfpgaBoardDesc lx200_board = { | |
539 | .flash = &lx200_flash, | |
540 | .sram_size = 0x2000000, | |
541 | .io = xtfpga_nommu_io, | |
82b25dc8 | 542 | }; |
188ce01d | 543 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
544 | } |
545 | ||
740ad9f7 MF |
546 | static const XtfpgaFlashDesc ml605_flash = { |
547 | .base = 0x08000000, | |
548 | .size = 0x01000000, | |
549 | .sector_size = 0x20000, | |
550 | }; | |
551 | ||
188ce01d | 552 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 553 | { |
188ce01d | 554 | static const XtfpgaBoardDesc ml605_board = { |
740ad9f7 | 555 | .flash = &ml605_flash, |
e0db904d | 556 | .sram_size = 0x2000000, |
85e2d8d5 MF |
557 | .io = xtfpga_mmu_io, |
558 | }; | |
559 | xtfpga_init(&ml605_board, machine); | |
560 | } | |
561 | ||
562 | static void xtfpga_ml605_nommu_init(MachineState *machine) | |
563 | { | |
564 | static const XtfpgaBoardDesc ml605_board = { | |
565 | .flash = &ml605_flash, | |
566 | .sram_size = 0x2000000, | |
567 | .io = xtfpga_nommu_io, | |
e0db904d | 568 | }; |
188ce01d | 569 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
570 | } |
571 | ||
740ad9f7 MF |
572 | static const XtfpgaFlashDesc kc705_flash = { |
573 | .base = 0x00000000, | |
574 | .size = 0x08000000, | |
575 | .boot_base = 0x06000000, | |
576 | .sector_size = 0x20000, | |
577 | }; | |
578 | ||
188ce01d | 579 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 580 | { |
188ce01d | 581 | static const XtfpgaBoardDesc kc705_board = { |
740ad9f7 | 582 | .flash = &kc705_flash, |
e0db904d | 583 | .sram_size = 0x2000000, |
85e2d8d5 MF |
584 | .io = xtfpga_mmu_io, |
585 | }; | |
586 | xtfpga_init(&kc705_board, machine); | |
587 | } | |
588 | ||
589 | static void xtfpga_kc705_nommu_init(MachineState *machine) | |
590 | { | |
591 | static const XtfpgaBoardDesc kc705_board = { | |
592 | .flash = &kc705_flash, | |
593 | .sram_size = 0x2000000, | |
594 | .io = xtfpga_nommu_io, | |
e0db904d | 595 | }; |
188ce01d | 596 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
597 | } |
598 | ||
188ce01d | 599 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 600 | { |
8a661aea AF |
601 | MachineClass *mc = MACHINE_CLASS(oc); |
602 | ||
e264d29d | 603 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 604 | mc->init = xtfpga_lx60_init; |
174e09b7 | 605 | mc->max_cpus = 32; |
f83eb10d | 606 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 607 | mc->default_ram_size = 64 * MiB; |
e264d29d | 608 | } |
0200db65 | 609 | |
188ce01d | 610 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
611 | .name = MACHINE_TYPE_NAME("lx60"), |
612 | .parent = TYPE_MACHINE, | |
188ce01d | 613 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 614 | }; |
82b25dc8 | 615 | |
85e2d8d5 MF |
616 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) |
617 | { | |
618 | MachineClass *mc = MACHINE_CLASS(oc); | |
619 | ||
a3c5e49d | 620 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 621 | mc->init = xtfpga_lx60_nommu_init; |
174e09b7 | 622 | mc->max_cpus = 32; |
a3c5e49d | 623 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 624 | mc->default_ram_size = 64 * MiB; |
85e2d8d5 MF |
625 | } |
626 | ||
627 | static const TypeInfo xtfpga_lx60_nommu_type = { | |
628 | .name = MACHINE_TYPE_NAME("lx60-nommu"), | |
629 | .parent = TYPE_MACHINE, | |
630 | .class_init = xtfpga_lx60_nommu_class_init, | |
631 | }; | |
632 | ||
188ce01d | 633 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 634 | { |
8a661aea AF |
635 | MachineClass *mc = MACHINE_CLASS(oc); |
636 | ||
e264d29d | 637 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 638 | mc->init = xtfpga_lx200_init; |
174e09b7 | 639 | mc->max_cpus = 32; |
f83eb10d | 640 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 641 | mc->default_ram_size = 96 * MiB; |
e264d29d | 642 | } |
e0db904d | 643 | |
188ce01d | 644 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
645 | .name = MACHINE_TYPE_NAME("lx200"), |
646 | .parent = TYPE_MACHINE, | |
188ce01d | 647 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 648 | }; |
e264d29d | 649 | |
85e2d8d5 MF |
650 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) |
651 | { | |
652 | MachineClass *mc = MACHINE_CLASS(oc); | |
653 | ||
a3c5e49d | 654 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 655 | mc->init = xtfpga_lx200_nommu_init; |
174e09b7 | 656 | mc->max_cpus = 32; |
a3c5e49d | 657 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 658 | mc->default_ram_size = 96 * MiB; |
85e2d8d5 MF |
659 | } |
660 | ||
661 | static const TypeInfo xtfpga_lx200_nommu_type = { | |
662 | .name = MACHINE_TYPE_NAME("lx200-nommu"), | |
663 | .parent = TYPE_MACHINE, | |
664 | .class_init = xtfpga_lx200_nommu_class_init, | |
665 | }; | |
666 | ||
188ce01d | 667 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 668 | { |
8a661aea AF |
669 | MachineClass *mc = MACHINE_CLASS(oc); |
670 | ||
e264d29d | 671 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 672 | mc->init = xtfpga_ml605_init; |
174e09b7 | 673 | mc->max_cpus = 32; |
f83eb10d | 674 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 675 | mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
e264d29d EH |
676 | } |
677 | ||
188ce01d | 678 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
679 | .name = MACHINE_TYPE_NAME("ml605"), |
680 | .parent = TYPE_MACHINE, | |
188ce01d | 681 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 682 | }; |
e0db904d | 683 | |
85e2d8d5 MF |
684 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) |
685 | { | |
686 | MachineClass *mc = MACHINE_CLASS(oc); | |
687 | ||
a3c5e49d | 688 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 689 | mc->init = xtfpga_ml605_nommu_init; |
174e09b7 | 690 | mc->max_cpus = 32; |
a3c5e49d | 691 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 692 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
693 | } |
694 | ||
695 | static const TypeInfo xtfpga_ml605_nommu_type = { | |
696 | .name = MACHINE_TYPE_NAME("ml605-nommu"), | |
697 | .parent = TYPE_MACHINE, | |
698 | .class_init = xtfpga_ml605_nommu_class_init, | |
699 | }; | |
700 | ||
188ce01d | 701 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 702 | { |
8a661aea AF |
703 | MachineClass *mc = MACHINE_CLASS(oc); |
704 | ||
e264d29d | 705 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 706 | mc->init = xtfpga_kc705_init; |
174e09b7 | 707 | mc->max_cpus = 32; |
f83eb10d | 708 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
59b5e9bb | 709 | mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
0200db65 MF |
710 | } |
711 | ||
188ce01d | 712 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
713 | .name = MACHINE_TYPE_NAME("kc705"), |
714 | .parent = TYPE_MACHINE, | |
188ce01d | 715 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
716 | }; |
717 | ||
85e2d8d5 MF |
718 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) |
719 | { | |
720 | MachineClass *mc = MACHINE_CLASS(oc); | |
721 | ||
a3c5e49d | 722 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 | 723 | mc->init = xtfpga_kc705_nommu_init; |
174e09b7 | 724 | mc->max_cpus = 32; |
a3c5e49d | 725 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
59b5e9bb | 726 | mc->default_ram_size = 256 * MiB; |
85e2d8d5 MF |
727 | } |
728 | ||
729 | static const TypeInfo xtfpga_kc705_nommu_type = { | |
730 | .name = MACHINE_TYPE_NAME("kc705-nommu"), | |
731 | .parent = TYPE_MACHINE, | |
732 | .class_init = xtfpga_kc705_nommu_class_init, | |
733 | }; | |
734 | ||
188ce01d | 735 | static void xtfpga_machines_init(void) |
8a661aea | 736 | { |
188ce01d MF |
737 | type_register_static(&xtfpga_lx60_type); |
738 | type_register_static(&xtfpga_lx200_type); | |
739 | type_register_static(&xtfpga_ml605_type); | |
740 | type_register_static(&xtfpga_kc705_type); | |
85e2d8d5 MF |
741 | type_register_static(&xtfpga_lx60_nommu_type); |
742 | type_register_static(&xtfpga_lx200_nommu_type); | |
743 | type_register_static(&xtfpga_ml605_nommu_type); | |
744 | type_register_static(&xtfpga_kc705_nommu_type); | |
8a661aea AF |
745 | } |
746 | ||
188ce01d | 747 | type_init(xtfpga_machines_init) |