]> git.proxmox.com Git - mirror_qemu.git/blame - memory.c
memory: Fix up memory_region_{add|del}_coalescing
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879 18#include "cpu.h"
022c62cb
PB
19#include "exec/memory.h"
20#include "exec/address-spaces.h"
409ddd01 21#include "qapi/visitor.h"
1de7afc9 22#include "qemu/bitops.h"
8c56c1a5 23#include "qemu/error-report.h"
db725815 24#include "qemu/main-loop.h"
b6b71cb5 25#include "qemu/qemu-print.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
54d31236 32#include "sysemu/runstate.h"
14a48c1d 33#include "sysemu/tcg.h"
8072aae3 34#include "sysemu/accel.h"
8072aae3 35#include "hw/boards.h"
b08199c6 36#include "migration/vmstate.h"
67d95c15 37
d197063f
PB
38//#define DEBUG_UNASSIGNED
39
22bde714
JK
40static unsigned memory_region_transaction_depth;
41static bool memory_region_update_pending;
4dc56152 42static bool ioeventfd_update_pending;
ae7a2bca 43bool global_dirty_log;
7664e80c 44
eae3eb3e 45static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 47
0d673e36
AK
48static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
967dc9b1
AK
51static GHashTable *flat_views;
52
093bc2cd
AK
53typedef struct AddrRange AddrRange;
54
8417cebf 55/*
c9cdaa3a 56 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
57 * (large MemoryRegion::alias_offset).
58 */
093bc2cd 59struct AddrRange {
08dafab4
AK
60 Int128 start;
61 Int128 size;
093bc2cd
AK
62};
63
08dafab4 64static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
65{
66 return (AddrRange) { start, size };
67}
68
69static bool addrrange_equal(AddrRange r1, AddrRange r2)
70{
08dafab4 71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
72}
73
08dafab4 74static Int128 addrrange_end(AddrRange r)
093bc2cd 75{
08dafab4 76 return int128_add(r.start, r.size);
093bc2cd
AK
77}
78
08dafab4 79static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 80{
08dafab4 81 int128_addto(&range.start, delta);
093bc2cd
AK
82 return range;
83}
84
08dafab4
AK
85static bool addrrange_contains(AddrRange range, Int128 addr)
86{
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89}
90
093bc2cd
AK
91static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92{
08dafab4
AK
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
093bc2cd
AK
95}
96
97static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98{
08dafab4
AK
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
102}
103
0e0d36b4
AK
104enum ListenerDirection { Forward, Reverse };
105
7376e582 106#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
0e0d36b4
AK
116 } \
117 break; \
118 case Reverse: \
eae3eb3e 119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
eae3eb3e 136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 137 if (_listener->_callback) { \
7376e582
AK
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
eae3eb3e 143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 144 if (_listener->_callback) { \
7376e582
AK
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
093bc2cd
AK
162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK
167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK
172};
173
73bb753d
TB
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
3e9d69e7 176{
73bb753d 177 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 178 return true;
73bb753d 179 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 180 return false;
73bb753d 181 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 182 return true;
73bb753d 183 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 184 return false;
73bb753d 185 } else if (a->match_data < b->match_data) {
3e9d69e7 186 return true;
73bb753d 187 } else if (a->match_data > b->match_data) {
3e9d69e7 188 return false;
73bb753d
TB
189 } else if (a->match_data) {
190 if (a->data < b->data) {
3e9d69e7 191 return true;
73bb753d 192 } else if (a->data > b->data) {
3e9d69e7
AK
193 return false;
194 }
195 }
73bb753d 196 if (a->e < b->e) {
3e9d69e7 197 return true;
73bb753d 198 } else if (a->e > b->e) {
3e9d69e7
AK
199 return false;
200 }
201 return false;
202}
203
73bb753d
TB
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
3e9d69e7
AK
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd
AK
211/* Range of memory in the global map. Addresses are absolute. */
212struct FlatRange {
213 MemoryRegion *mr;
a8170e5e 214 hwaddr offset_in_region;
093bc2cd 215 AddrRange addr;
5a583347 216 uint8_t dirty_log_mask;
b138e654 217 bool romd_mode;
fb1cd6f9 218 bool readonly;
c26763f8 219 bool nonvolatile;
093bc2cd
AK
220};
221
093bc2cd
AK
222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
c26763f8 235 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
236 };
237}
238
093bc2cd
AK
239static bool flatrange_equal(FlatRange *a, FlatRange *b)
240{
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 243 && a->offset_in_region == b->offset_in_region
b138e654 244 && a->romd_mode == b->romd_mode
c26763f8
MAL
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
247}
248
89c177bb 249static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 250{
cc94cd6d
AK
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
856d7245 254 view->ref = 1;
89c177bb
AK
255 view->root = mr_root;
256 memory_region_ref(mr_root);
02d9651d 257 trace_flatview_new(view, mr_root);
cc94cd6d
AK
258
259 return view;
093bc2cd
AK
260}
261
262/* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266{
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 269 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
dfde4e6e 275 memory_region_ref(range->mr);
093bc2cd
AK
276 ++view->nr;
277}
278
279static void flatview_destroy(FlatView *view)
280{
dfde4e6e
PB
281 int i;
282
02d9651d 283 trace_flatview_destroy(view, view->root);
66a6df1d
AK
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
dfde4e6e
PB
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
7267c094 290 g_free(view->ranges);
89c177bb 291 memory_region_unref(view->root);
a9a0c06d 292 g_free(view);
093bc2cd
AK
293}
294
447b0d0b 295static bool flatview_ref(FlatView *view)
856d7245 296{
447b0d0b 297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
298}
299
48564041 300void flatview_unref(FlatView *view)
856d7245
PB
301{
302 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 303 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 304 assert(view->root);
66a6df1d 305 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
306 }
307}
308
3d8e6bf9
AK
309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
320}
321
8508e024 322/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
323static void flatview_simplify(FlatView *view)
324{
838ec117 325 unsigned i, j, k;
3d8e6bf9
AK
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
333 ++j;
334 }
335 ++i;
838ec117
KW
336 for (k = i; k < j; k++) {
337 memory_region_unref(view->ranges[k].mr);
338 }
3d8e6bf9
AK
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343}
344
e7342aa3
PB
345static bool memory_region_big_endian(MemoryRegion *mr)
346{
347#ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349#else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351#endif
352}
353
e11ef3d1
PB
354static bool memory_region_wrong_endianness(MemoryRegion *mr)
355{
356#ifdef TARGET_WORDS_BIGENDIAN
357 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
358#else
359 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
360#endif
361}
362
363static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
364{
365 if (memory_region_wrong_endianness(mr)) {
366 switch (size) {
367 case 1:
368 break;
369 case 2:
370 *data = bswap16(*data);
371 break;
372 case 4:
373 *data = bswap32(*data);
374 break;
375 case 8:
376 *data = bswap64(*data);
377 break;
378 default:
379 abort();
380 }
381 }
382}
383
3c754a93 384static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 385 signed shift,
3c754a93
PMD
386 uint64_t mask,
387 uint64_t tmp)
388{
98f52cdb
PMD
389 if (shift >= 0) {
390 *value |= (tmp & mask) << shift;
391 } else {
392 *value |= (tmp & mask) >> -shift;
393 }
3c754a93
PMD
394}
395
396static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 397 signed shift,
3c754a93
PMD
398 uint64_t mask)
399{
98f52cdb
PMD
400 uint64_t tmp;
401
402 if (shift >= 0) {
403 tmp = (*value >> shift) & mask;
404 } else {
405 tmp = (*value << -shift) & mask;
406 }
407
408 return tmp;
3c754a93
PMD
409}
410
4779dc1d
HB
411static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
412{
413 MemoryRegion *root;
414 hwaddr abs_addr = offset;
415
416 abs_addr += mr->addr;
417 for (root = mr; root->container; ) {
418 root = root->container;
419 abs_addr += root->addr;
420 }
421
422 return abs_addr;
423}
424
5a68be94
HB
425static int get_cpu_index(void)
426{
427 if (current_cpu) {
428 return current_cpu->cpu_index;
429 }
430 return -1;
431}
432
cc05c43a 433static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
434 hwaddr addr,
435 uint64_t *value,
436 unsigned size,
98f52cdb 437 signed shift,
cc05c43a
PM
438 uint64_t mask,
439 MemTxAttrs attrs)
ce5d2f33 440{
ce5d2f33
PB
441 uint64_t tmp;
442
cc05c43a 443 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 444 if (mr->subpage) {
5a68be94 445 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
446 } else if (mr == &io_mem_notdirty) {
447 /* Accesses to code which has previously been translated into a TB show
448 * up in the MMIO path, as accesses to the io_mem_notdirty
449 * MemoryRegion. */
450 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
451 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
452 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 453 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 454 }
3c754a93 455 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 456 return MEMTX_OK;
ce5d2f33
PB
457}
458
cc05c43a
PM
459static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
460 hwaddr addr,
461 uint64_t *value,
462 unsigned size,
98f52cdb 463 signed shift,
cc05c43a
PM
464 uint64_t mask,
465 MemTxAttrs attrs)
164a4dcd 466{
cc05c43a
PM
467 uint64_t tmp = 0;
468 MemTxResult r;
164a4dcd 469
cc05c43a 470 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 471 if (mr->subpage) {
5a68be94 472 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
473 } else if (mr == &io_mem_notdirty) {
474 /* Accesses to code which has previously been translated into a TB show
475 * up in the MMIO path, as accesses to the io_mem_notdirty
476 * MemoryRegion. */
477 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
478 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
479 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 480 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 481 }
3c754a93 482 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 483 return r;
164a4dcd
AK
484}
485
cc05c43a
PM
486static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
487 hwaddr addr,
488 uint64_t *value,
489 unsigned size,
98f52cdb 490 signed shift,
cc05c43a
PM
491 uint64_t mask,
492 MemTxAttrs attrs)
164a4dcd 493{
3c754a93 494 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 495
23d92d68 496 if (mr->subpage) {
5a68be94 497 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
498 } else if (mr == &io_mem_notdirty) {
499 /* Accesses to code which has previously been translated into a TB show
500 * up in the MMIO path, as accesses to the io_mem_notdirty
501 * MemoryRegion. */
502 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
503 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
504 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 505 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 506 }
164a4dcd 507 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 508 return MEMTX_OK;
164a4dcd
AK
509}
510
cc05c43a
PM
511static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
512 hwaddr addr,
513 uint64_t *value,
514 unsigned size,
98f52cdb 515 signed shift,
cc05c43a
PM
516 uint64_t mask,
517 MemTxAttrs attrs)
518{
3c754a93 519 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 520
23d92d68 521 if (mr->subpage) {
5a68be94 522 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
523 } else if (mr == &io_mem_notdirty) {
524 /* Accesses to code which has previously been translated into a TB show
525 * up in the MMIO path, as accesses to the io_mem_notdirty
526 * MemoryRegion. */
527 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
528 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
529 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 530 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 531 }
cc05c43a
PM
532 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
533}
534
535static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
536 uint64_t *value,
537 unsigned size,
538 unsigned access_size_min,
539 unsigned access_size_max,
05e015f7
KF
540 MemTxResult (*access_fn)
541 (MemoryRegion *mr,
542 hwaddr addr,
543 uint64_t *value,
544 unsigned size,
98f52cdb 545 signed shift,
05e015f7
KF
546 uint64_t mask,
547 MemTxAttrs attrs),
cc05c43a
PM
548 MemoryRegion *mr,
549 MemTxAttrs attrs)
164a4dcd
AK
550{
551 uint64_t access_mask;
552 unsigned access_size;
553 unsigned i;
cc05c43a 554 MemTxResult r = MEMTX_OK;
164a4dcd
AK
555
556 if (!access_size_min) {
557 access_size_min = 1;
558 }
559 if (!access_size_max) {
560 access_size_max = 4;
561 }
ce5d2f33
PB
562
563 /* FIXME: support unaligned access? */
164a4dcd 564 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 565 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
566 if (memory_region_big_endian(mr)) {
567 for (i = 0; i < size; i += access_size) {
05e015f7 568 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 569 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
570 }
571 } else {
572 for (i = 0; i < size; i += access_size) {
05e015f7 573 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 574 access_mask, attrs);
e7342aa3 575 }
164a4dcd 576 }
cc05c43a 577 return r;
164a4dcd
AK
578}
579
e2177955
AK
580static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
581{
0d673e36
AK
582 AddressSpace *as;
583
feca4ac1
PB
584 while (mr->container) {
585 mr = mr->container;
e2177955 586 }
0d673e36
AK
587 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
588 if (mr == as->root) {
589 return as;
590 }
e2177955 591 }
eed2bacf 592 return NULL;
e2177955
AK
593}
594
093bc2cd
AK
595/* Render a memory region into the global view. Ranges in @view obscure
596 * ranges in @mr.
597 */
598static void render_memory_region(FlatView *view,
599 MemoryRegion *mr,
08dafab4 600 Int128 base,
fb1cd6f9 601 AddrRange clip,
c26763f8
MAL
602 bool readonly,
603 bool nonvolatile)
093bc2cd
AK
604{
605 MemoryRegion *subregion;
606 unsigned i;
a8170e5e 607 hwaddr offset_in_region;
08dafab4
AK
608 Int128 remain;
609 Int128 now;
093bc2cd
AK
610 FlatRange fr;
611 AddrRange tmp;
612
6bba19ba
AK
613 if (!mr->enabled) {
614 return;
615 }
616
08dafab4 617 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 618 readonly |= mr->readonly;
c26763f8 619 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
620
621 tmp = addrrange_make(base, mr->size);
622
623 if (!addrrange_intersects(tmp, clip)) {
624 return;
625 }
626
627 clip = addrrange_intersection(tmp, clip);
628
629 if (mr->alias) {
08dafab4
AK
630 int128_subfrom(&base, int128_make64(mr->alias->addr));
631 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
632 render_memory_region(view, mr->alias, base, clip,
633 readonly, nonvolatile);
093bc2cd
AK
634 return;
635 }
636
637 /* Render subregions in priority order. */
638 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
639 render_memory_region(view, subregion, base, clip,
640 readonly, nonvolatile);
093bc2cd
AK
641 }
642
14a3c10a 643 if (!mr->terminates) {
093bc2cd
AK
644 return;
645 }
646
08dafab4 647 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
648 base = clip.start;
649 remain = clip.size;
650
2eb74e1a 651 fr.mr = mr;
6f6a5ef3 652 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 653 fr.romd_mode = mr->romd_mode;
2eb74e1a 654 fr.readonly = readonly;
c26763f8 655 fr.nonvolatile = nonvolatile;
2eb74e1a 656
093bc2cd 657 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
658 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
659 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
660 continue;
661 }
08dafab4
AK
662 if (int128_lt(base, view->ranges[i].addr.start)) {
663 now = int128_min(remain,
664 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
665 fr.offset_in_region = offset_in_region;
666 fr.addr = addrrange_make(base, now);
667 flatview_insert(view, i, &fr);
668 ++i;
08dafab4
AK
669 int128_addto(&base, now);
670 offset_in_region += int128_get64(now);
671 int128_subfrom(&remain, now);
093bc2cd 672 }
d26a8cae
AK
673 now = int128_sub(int128_min(int128_add(base, remain),
674 addrrange_end(view->ranges[i].addr)),
675 base);
676 int128_addto(&base, now);
677 offset_in_region += int128_get64(now);
678 int128_subfrom(&remain, now);
093bc2cd 679 }
08dafab4 680 if (int128_nz(remain)) {
093bc2cd
AK
681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, remain);
683 flatview_insert(view, i, &fr);
684 }
685}
686
89c177bb
AK
687static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
688{
e673ba9a
PB
689 while (mr->enabled) {
690 if (mr->alias) {
691 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
692 /* The alias is included in its entirety. Use it as
693 * the "real" root, so that we can share more FlatViews.
694 */
695 mr = mr->alias;
696 continue;
697 }
698 } else if (!mr->terminates) {
699 unsigned int found = 0;
700 MemoryRegion *child, *next = NULL;
701 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
702 if (child->enabled) {
703 if (++found > 1) {
704 next = NULL;
705 break;
706 }
707 if (!child->addr && int128_ge(mr->size, child->size)) {
708 /* A child is included in its entirety. If it's the only
709 * enabled one, use it in the hope of finding an alias down the
710 * way. This will also let us share FlatViews.
711 */
712 next = child;
713 }
714 }
715 }
092aa2fc
AK
716 if (found == 0) {
717 return NULL;
718 }
e673ba9a
PB
719 if (next) {
720 mr = next;
721 continue;
722 }
723 }
724
092aa2fc 725 return mr;
89c177bb
AK
726 }
727
092aa2fc 728 return NULL;
89c177bb
AK
729}
730
093bc2cd 731/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 732static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 733{
9bf561e3 734 int i;
a9a0c06d 735 FlatView *view;
093bc2cd 736
89c177bb 737 view = flatview_new(mr);
093bc2cd 738
83f3c251 739 if (mr) {
a9a0c06d 740 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
741 addrrange_make(int128_zero(), int128_2_64()),
742 false, false);
83f3c251 743 }
a9a0c06d 744 flatview_simplify(view);
093bc2cd 745
9bf561e3
AK
746 view->dispatch = address_space_dispatch_new(view);
747 for (i = 0; i < view->nr; i++) {
748 MemoryRegionSection mrs =
749 section_from_flat_range(&view->ranges[i], view);
750 flatview_add_to_dispatch(view, &mrs);
751 }
752 address_space_dispatch_compact(view->dispatch);
967dc9b1 753 g_hash_table_replace(flat_views, mr, view);
9bf561e3 754
093bc2cd
AK
755 return view;
756}
757
3e9d69e7
AK
758static void address_space_add_del_ioeventfds(AddressSpace *as,
759 MemoryRegionIoeventfd *fds_new,
760 unsigned fds_new_nb,
761 MemoryRegionIoeventfd *fds_old,
762 unsigned fds_old_nb)
763{
764 unsigned iold, inew;
80a1ea37
AK
765 MemoryRegionIoeventfd *fd;
766 MemoryRegionSection section;
3e9d69e7
AK
767
768 /* Generate a symmetric difference of the old and new fd sets, adding
769 * and deleting as necessary.
770 */
771
772 iold = inew = 0;
773 while (iold < fds_old_nb || inew < fds_new_nb) {
774 if (iold < fds_old_nb
775 && (inew == fds_new_nb
73bb753d
TB
776 || memory_region_ioeventfd_before(&fds_old[iold],
777 &fds_new[inew]))) {
80a1ea37
AK
778 fd = &fds_old[iold];
779 section = (MemoryRegionSection) {
16620684 780 .fv = address_space_to_flatview(as),
80a1ea37 781 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 782 .size = fd->addr.size,
80a1ea37 783 };
9a54635d 784 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 785 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
786 ++iold;
787 } else if (inew < fds_new_nb
788 && (iold == fds_old_nb
73bb753d
TB
789 || memory_region_ioeventfd_before(&fds_new[inew],
790 &fds_old[iold]))) {
80a1ea37
AK
791 fd = &fds_new[inew];
792 section = (MemoryRegionSection) {
16620684 793 .fv = address_space_to_flatview(as),
80a1ea37 794 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 795 .size = fd->addr.size,
80a1ea37 796 };
9a54635d 797 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 798 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
799 ++inew;
800 } else {
801 ++iold;
802 ++inew;
803 }
804 }
805}
806
48564041 807FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
808{
809 FlatView *view;
810
374f2981 811 rcu_read_lock();
447b0d0b 812 do {
16620684 813 view = address_space_to_flatview(as);
447b0d0b
PB
814 /* If somebody has replaced as->current_map concurrently,
815 * flatview_ref returns false.
816 */
817 } while (!flatview_ref(view));
374f2981 818 rcu_read_unlock();
856d7245
PB
819 return view;
820}
821
3e9d69e7
AK
822static void address_space_update_ioeventfds(AddressSpace *as)
823{
99e86347 824 FlatView *view;
3e9d69e7
AK
825 FlatRange *fr;
826 unsigned ioeventfd_nb = 0;
827 MemoryRegionIoeventfd *ioeventfds = NULL;
828 AddrRange tmp;
829 unsigned i;
830
856d7245 831 view = address_space_get_flatview(as);
99e86347 832 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
833 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
834 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
835 int128_sub(fr->addr.start,
836 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
837 if (addrrange_intersects(fr->addr, tmp)) {
838 ++ioeventfd_nb;
7267c094 839 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
840 ioeventfd_nb * sizeof(*ioeventfds));
841 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
842 ioeventfds[ioeventfd_nb-1].addr = tmp;
843 }
844 }
845 }
846
847 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
848 as->ioeventfds, as->ioeventfd_nb);
849
7267c094 850 g_free(as->ioeventfds);
3e9d69e7
AK
851 as->ioeventfds = ioeventfds;
852 as->ioeventfd_nb = ioeventfd_nb;
856d7245 853 flatview_unref(view);
3e9d69e7
AK
854}
855
23f1174a
PX
856/*
857 * Notify the memory listeners about the coalesced IO change events of
858 * range `cmr'. Only the part that has intersection of the specified
859 * FlatRange will be sent.
860 */
861static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
862 CoalescedMemoryRange *cmr, bool add)
863{
864 AddrRange tmp;
865
866 tmp = addrrange_shift(cmr->addr,
867 int128_sub(fr->addr.start,
868 int128_make64(fr->offset_in_region)));
869 if (!addrrange_intersects(tmp, fr->addr)) {
870 return;
871 }
872 tmp = addrrange_intersection(tmp, fr->addr);
873
874 if (add) {
875 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
876 int128_get64(tmp.start),
877 int128_get64(tmp.size));
878 } else {
879 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
880 int128_get64(tmp.start),
881 int128_get64(tmp.size));
882 }
883}
884
909bf763
PB
885static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
886{
23f1174a
PX
887 CoalescedMemoryRange *cmr;
888
23f1174a
PX
889 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
890 flat_range_coalesced_io_notify(fr, as, cmr, false);
891 }
909bf763
PB
892}
893
894static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
895{
896 MemoryRegion *mr = fr->mr;
897 CoalescedMemoryRange *cmr;
909bf763 898
1f7af804
PB
899 if (QTAILQ_EMPTY(&mr->coalesced)) {
900 return;
901 }
902
909bf763 903 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
23f1174a 904 flat_range_coalesced_io_notify(fr, as, cmr, true);
909bf763
PB
905 }
906}
907
b8af1afb 908static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
909 const FlatView *old_view,
910 const FlatView *new_view,
b8af1afb 911 bool adding)
093bc2cd 912{
093bc2cd
AK
913 unsigned iold, inew;
914 FlatRange *frold, *frnew;
093bc2cd
AK
915
916 /* Generate a symmetric difference of the old and new memory maps.
917 * Kill ranges in the old map, and instantiate ranges in the new map.
918 */
919 iold = inew = 0;
a9a0c06d
PB
920 while (iold < old_view->nr || inew < new_view->nr) {
921 if (iold < old_view->nr) {
922 frold = &old_view->ranges[iold];
093bc2cd
AK
923 } else {
924 frold = NULL;
925 }
a9a0c06d
PB
926 if (inew < new_view->nr) {
927 frnew = &new_view->ranges[inew];
093bc2cd
AK
928 } else {
929 frnew = NULL;
930 }
931
932 if (frold
933 && (!frnew
08dafab4
AK
934 || int128_lt(frold->addr.start, frnew->addr.start)
935 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 936 && !flatrange_equal(frold, frnew)))) {
41a6e477 937 /* In old but not in new, or in both but attributes changed. */
093bc2cd 938
b8af1afb 939 if (!adding) {
3ac7d43a 940 flat_range_coalesced_io_del(frold, as);
72e22d2f 941 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
942 }
943
093bc2cd
AK
944 ++iold;
945 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 946 /* In both and unchanged (except logging may have changed) */
093bc2cd 947
4f826024 948 if (adding) {
50c1e149 949 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
950 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
951 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
952 frold->dirty_log_mask,
953 frnew->dirty_log_mask);
954 }
955 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
956 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
957 frold->dirty_log_mask,
958 frnew->dirty_log_mask);
b8af1afb 959 }
5a583347
AK
960 }
961
093bc2cd
AK
962 ++iold;
963 ++inew;
093bc2cd
AK
964 } else {
965 /* In new */
966
b8af1afb 967 if (adding) {
72e22d2f 968 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 969 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK
970 }
971
093bc2cd
AK
972 ++inew;
973 }
974 }
b8af1afb
AK
975}
976
967dc9b1
AK
977static void flatviews_init(void)
978{
092aa2fc
AK
979 static FlatView *empty_view;
980
967dc9b1
AK
981 if (flat_views) {
982 return;
983 }
984
985 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
986 (GDestroyNotify) flatview_unref);
092aa2fc
AK
987 if (!empty_view) {
988 empty_view = generate_memory_topology(NULL);
989 /* We keep it alive forever in the global variable. */
990 flatview_ref(empty_view);
991 } else {
992 g_hash_table_replace(flat_views, NULL, empty_view);
993 flatview_ref(empty_view);
994 }
967dc9b1
AK
995}
996
997static void flatviews_reset(void)
998{
999 AddressSpace *as;
1000
1001 if (flat_views) {
1002 g_hash_table_unref(flat_views);
1003 flat_views = NULL;
1004 }
1005 flatviews_init();
1006
1007 /* Render unique FVs */
1008 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1009 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1010
1011 if (g_hash_table_lookup(flat_views, physmr)) {
1012 continue;
1013 }
1014
1015 generate_memory_topology(physmr);
1016 }
1017}
1018
1019static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1020{
67ace39b 1021 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1022 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1023 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1024
1025 assert(new_view);
1026
67ace39b
AK
1027 if (old_view == new_view) {
1028 return;
1029 }
1030
1031 if (old_view) {
1032 flatview_ref(old_view);
1033 }
1034
967dc9b1 1035 flatview_ref(new_view);
9a62e24f
AK
1036
1037 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1038 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1039
1040 if (!old_view2) {
1041 old_view2 = &tmpview;
1042 }
1043 address_space_update_topology_pass(as, old_view2, new_view, false);
1044 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1045 }
b8af1afb 1046
374f2981
PB
1047 /* Writes are protected by the BQL. */
1048 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1049 if (old_view) {
1050 flatview_unref(old_view);
1051 }
856d7245
PB
1052
1053 /* Note that all the old MemoryRegions are still alive up to this
1054 * point. This relieves most MemoryListeners from the need to
1055 * ref/unref the MemoryRegions they get---unless they use them
1056 * outside the iothread mutex, in which case precise reference
1057 * counting is necessary.
1058 */
67ace39b
AK
1059 if (old_view) {
1060 flatview_unref(old_view);
1061 }
093bc2cd
AK
1062}
1063
202fc01b
AK
1064static void address_space_update_topology(AddressSpace *as)
1065{
1066 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1067
1068 flatviews_init();
1069 if (!g_hash_table_lookup(flat_views, physmr)) {
1070 generate_memory_topology(physmr);
1071 }
1072 address_space_set_flatview(as);
1073}
1074
4ef4db86
AK
1075void memory_region_transaction_begin(void)
1076{
bb880ded 1077 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1078 ++memory_region_transaction_depth;
1079}
1080
1081void memory_region_transaction_commit(void)
1082{
0d673e36
AK
1083 AddressSpace *as;
1084
4ef4db86 1085 assert(memory_region_transaction_depth);
8d04fb55
JK
1086 assert(qemu_mutex_iothread_locked());
1087
4ef4db86 1088 --memory_region_transaction_depth;
4dc56152
GA
1089 if (!memory_region_transaction_depth) {
1090 if (memory_region_update_pending) {
967dc9b1
AK
1091 flatviews_reset();
1092
4dc56152 1093 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1094
4dc56152 1095 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1096 address_space_set_flatview(as);
02218487 1097 address_space_update_ioeventfds(as);
4dc56152 1098 }
ade9c1aa 1099 memory_region_update_pending = false;
0b152095 1100 ioeventfd_update_pending = false;
4dc56152
GA
1101 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1102 } else if (ioeventfd_update_pending) {
1103 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1104 address_space_update_ioeventfds(as);
1105 }
ade9c1aa 1106 ioeventfd_update_pending = false;
4dc56152 1107 }
4dc56152 1108 }
4ef4db86
AK
1109}
1110
545e92e0
AK
1111static void memory_region_destructor_none(MemoryRegion *mr)
1112{
1113}
1114
1115static void memory_region_destructor_ram(MemoryRegion *mr)
1116{
f1060c55 1117 qemu_ram_free(mr->ram_block);
545e92e0
AK
1118}
1119
b4fefef9
PC
1120static bool memory_region_need_escape(char c)
1121{
1122 return c == '/' || c == '[' || c == '\\' || c == ']';
1123}
1124
1125static char *memory_region_escape_name(const char *name)
1126{
1127 const char *p;
1128 char *escaped, *q;
1129 uint8_t c;
1130 size_t bytes = 0;
1131
1132 for (p = name; *p; p++) {
1133 bytes += memory_region_need_escape(*p) ? 4 : 1;
1134 }
1135 if (bytes == p - name) {
1136 return g_memdup(name, bytes + 1);
1137 }
1138
1139 escaped = g_malloc(bytes + 1);
1140 for (p = name, q = escaped; *p; p++) {
1141 c = *p;
1142 if (unlikely(memory_region_need_escape(c))) {
1143 *q++ = '\\';
1144 *q++ = 'x';
1145 *q++ = "0123456789abcdef"[c >> 4];
1146 c = "0123456789abcdef"[c & 15];
1147 }
1148 *q++ = c;
1149 }
1150 *q = 0;
1151 return escaped;
1152}
1153
3df9d748
AK
1154static void memory_region_do_init(MemoryRegion *mr,
1155 Object *owner,
1156 const char *name,
1157 uint64_t size)
093bc2cd 1158{
08dafab4
AK
1159 mr->size = int128_make64(size);
1160 if (size == UINT64_MAX) {
1161 mr->size = int128_2_64();
1162 }
302fa283 1163 mr->name = g_strdup(name);
612263cf 1164 mr->owner = owner;
58eaa217 1165 mr->ram_block = NULL;
b4fefef9
PC
1166
1167 if (name) {
843ef73a
PC
1168 char *escaped_name = memory_region_escape_name(name);
1169 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1170
1171 if (!owner) {
1172 owner = container_get(qdev_get_machine(), "/unattached");
1173 }
1174
843ef73a 1175 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1176 object_unref(OBJECT(mr));
843ef73a
PC
1177 g_free(name_array);
1178 g_free(escaped_name);
b4fefef9
PC
1179 }
1180}
1181
3df9d748
AK
1182void memory_region_init(MemoryRegion *mr,
1183 Object *owner,
1184 const char *name,
1185 uint64_t size)
1186{
1187 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1188 memory_region_do_init(mr, owner, name, size);
1189}
1190
d7bce999
EB
1191static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1192 void *opaque, Error **errp)
409ddd01
PC
1193{
1194 MemoryRegion *mr = MEMORY_REGION(obj);
1195 uint64_t value = mr->addr;
1196
51e72bc1 1197 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1198}
1199
d7bce999
EB
1200static void memory_region_get_container(Object *obj, Visitor *v,
1201 const char *name, void *opaque,
1202 Error **errp)
409ddd01
PC
1203{
1204 MemoryRegion *mr = MEMORY_REGION(obj);
1205 gchar *path = (gchar *)"";
1206
1207 if (mr->container) {
1208 path = object_get_canonical_path(OBJECT(mr->container));
1209 }
51e72bc1 1210 visit_type_str(v, name, &path, errp);
409ddd01
PC
1211 if (mr->container) {
1212 g_free(path);
1213 }
1214}
1215
1216static Object *memory_region_resolve_container(Object *obj, void *opaque,
1217 const char *part)
1218{
1219 MemoryRegion *mr = MEMORY_REGION(obj);
1220
1221 return OBJECT(mr->container);
1222}
1223
d7bce999
EB
1224static void memory_region_get_priority(Object *obj, Visitor *v,
1225 const char *name, void *opaque,
1226 Error **errp)
d33382da
PC
1227{
1228 MemoryRegion *mr = MEMORY_REGION(obj);
1229 int32_t value = mr->priority;
1230
51e72bc1 1231 visit_type_int32(v, name, &value, errp);
d33382da
PC
1232}
1233
d7bce999
EB
1234static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1235 void *opaque, Error **errp)
52aef7bb
PC
1236{
1237 MemoryRegion *mr = MEMORY_REGION(obj);
1238 uint64_t value = memory_region_size(mr);
1239
51e72bc1 1240 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1241}
1242
b4fefef9
PC
1243static void memory_region_initfn(Object *obj)
1244{
1245 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1246 ObjectProperty *op;
b4fefef9
PC
1247
1248 mr->ops = &unassigned_mem_ops;
6bba19ba 1249 mr->enabled = true;
5f9a5ea1 1250 mr->romd_mode = true;
196ea131 1251 mr->global_locking = true;
545e92e0 1252 mr->destructor = memory_region_destructor_none;
093bc2cd 1253 QTAILQ_INIT(&mr->subregions);
093bc2cd 1254 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1255
1256 op = object_property_add(OBJECT(mr), "container",
1257 "link<" TYPE_MEMORY_REGION ">",
1258 memory_region_get_container,
1259 NULL, /* memory_region_set_container */
1260 NULL, NULL, &error_abort);
1261 op->resolve = memory_region_resolve_container;
1262
1263 object_property_add(OBJECT(mr), "addr", "uint64",
1264 memory_region_get_addr,
1265 NULL, /* memory_region_set_addr */
1266 NULL, NULL, &error_abort);
d33382da
PC
1267 object_property_add(OBJECT(mr), "priority", "uint32",
1268 memory_region_get_priority,
1269 NULL, /* memory_region_set_priority */
1270 NULL, NULL, &error_abort);
52aef7bb
PC
1271 object_property_add(OBJECT(mr), "size", "uint64",
1272 memory_region_get_size,
1273 NULL, /* memory_region_set_size, */
1274 NULL, NULL, &error_abort);
093bc2cd
AK
1275}
1276
3df9d748
AK
1277static void iommu_memory_region_initfn(Object *obj)
1278{
1279 MemoryRegion *mr = MEMORY_REGION(obj);
1280
1281 mr->is_iommu = true;
1282}
1283
b018ddf6
PB
1284static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1285 unsigned size)
1286{
1287#ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1289#endif
4917cf44 1290 if (current_cpu != NULL) {
dbea78a4
PM
1291 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1292 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
c658b94f 1293 }
68a7439a 1294 return 0;
b018ddf6
PB
1295}
1296
1297static void unassigned_mem_write(void *opaque, hwaddr addr,
1298 uint64_t val, unsigned size)
1299{
1300#ifdef DEBUG_UNASSIGNED
1301 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1302#endif
4917cf44
AF
1303 if (current_cpu != NULL) {
1304 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1305 }
b018ddf6
PB
1306}
1307
d197063f 1308static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1309 unsigned size, bool is_write,
1310 MemTxAttrs attrs)
d197063f
PB
1311{
1312 return false;
1313}
1314
1315const MemoryRegionOps unassigned_mem_ops = {
1316 .valid.accepts = unassigned_mem_accepts,
1317 .endianness = DEVICE_NATIVE_ENDIAN,
1318};
1319
4a2e242b
AW
1320static uint64_t memory_region_ram_device_read(void *opaque,
1321 hwaddr addr, unsigned size)
1322{
1323 MemoryRegion *mr = opaque;
1324 uint64_t data = (uint64_t)~0;
1325
1326 switch (size) {
1327 case 1:
1328 data = *(uint8_t *)(mr->ram_block->host + addr);
1329 break;
1330 case 2:
1331 data = *(uint16_t *)(mr->ram_block->host + addr);
1332 break;
1333 case 4:
1334 data = *(uint32_t *)(mr->ram_block->host + addr);
1335 break;
1336 case 8:
1337 data = *(uint64_t *)(mr->ram_block->host + addr);
1338 break;
1339 }
1340
1341 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1342
1343 return data;
1344}
1345
1346static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1347 uint64_t data, unsigned size)
1348{
1349 MemoryRegion *mr = opaque;
1350
1351 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1352
1353 switch (size) {
1354 case 1:
1355 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1356 break;
1357 case 2:
1358 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1359 break;
1360 case 4:
1361 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1362 break;
1363 case 8:
1364 *(uint64_t *)(mr->ram_block->host + addr) = data;
1365 break;
1366 }
1367}
1368
1369static const MemoryRegionOps ram_device_mem_ops = {
1370 .read = memory_region_ram_device_read,
1371 .write = memory_region_ram_device_write,
c99a29e7 1372 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1373 .valid = {
1374 .min_access_size = 1,
1375 .max_access_size = 8,
1376 .unaligned = true,
1377 },
1378 .impl = {
1379 .min_access_size = 1,
1380 .max_access_size = 8,
1381 .unaligned = true,
1382 },
1383};
1384
d2702032
PB
1385bool memory_region_access_valid(MemoryRegion *mr,
1386 hwaddr addr,
1387 unsigned size,
6d7b9a6c
PM
1388 bool is_write,
1389 MemTxAttrs attrs)
093bc2cd 1390{
a014ed07
PB
1391 int access_size_min, access_size_max;
1392 int access_size, i;
897fa7cf 1393
093bc2cd
AK
1394 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1395 return false;
1396 }
1397
a014ed07 1398 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1399 return true;
1400 }
1401
a014ed07
PB
1402 access_size_min = mr->ops->valid.min_access_size;
1403 if (!mr->ops->valid.min_access_size) {
1404 access_size_min = 1;
1405 }
1406
1407 access_size_max = mr->ops->valid.max_access_size;
1408 if (!mr->ops->valid.max_access_size) {
1409 access_size_max = 4;
1410 }
1411
1412 access_size = MAX(MIN(size, access_size_max), access_size_min);
1413 for (i = 0; i < size; i += access_size) {
1414 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1415 is_write, attrs)) {
a014ed07
PB
1416 return false;
1417 }
093bc2cd 1418 }
a014ed07 1419
093bc2cd
AK
1420 return true;
1421}
1422
cc05c43a
PM
1423static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1424 hwaddr addr,
1425 uint64_t *pval,
1426 unsigned size,
1427 MemTxAttrs attrs)
093bc2cd 1428{
cc05c43a 1429 *pval = 0;
093bc2cd 1430
ce5d2f33 1431 if (mr->ops->read) {
cc05c43a
PM
1432 return access_with_adjusted_size(addr, pval, size,
1433 mr->ops->impl.min_access_size,
1434 mr->ops->impl.max_access_size,
1435 memory_region_read_accessor,
1436 mr, attrs);
62a0db94 1437 } else {
cc05c43a
PM
1438 return access_with_adjusted_size(addr, pval, size,
1439 mr->ops->impl.min_access_size,
1440 mr->ops->impl.max_access_size,
1441 memory_region_read_with_attrs_accessor,
1442 mr, attrs);
74901c3b 1443 }
093bc2cd
AK
1444}
1445
3b643495
PM
1446MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1447 hwaddr addr,
1448 uint64_t *pval,
1449 unsigned size,
1450 MemTxAttrs attrs)
a621f38d 1451{
cc05c43a
PM
1452 MemTxResult r;
1453
6d7b9a6c 1454 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1455 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1456 return MEMTX_DECODE_ERROR;
791af8c8 1457 }
a621f38d 1458
cc05c43a 1459 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1460 adjust_endianness(mr, pval, size);
cc05c43a 1461 return r;
a621f38d 1462}
093bc2cd 1463
8c56c1a5
PF
1464/* Return true if an eventfd was signalled */
1465static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1466 hwaddr addr,
1467 uint64_t data,
1468 unsigned size,
1469 MemTxAttrs attrs)
1470{
1471 MemoryRegionIoeventfd ioeventfd = {
1472 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1473 .data = data,
1474 };
1475 unsigned i;
1476
1477 for (i = 0; i < mr->ioeventfd_nb; i++) {
1478 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1479 ioeventfd.e = mr->ioeventfds[i].e;
1480
73bb753d 1481 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1482 event_notifier_set(ioeventfd.e);
1483 return true;
1484 }
1485 }
1486
1487 return false;
1488}
1489
3b643495
PM
1490MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1491 hwaddr addr,
1492 uint64_t data,
1493 unsigned size,
1494 MemTxAttrs attrs)
a621f38d 1495{
6d7b9a6c 1496 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1497 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1498 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1499 }
1500
a621f38d
AK
1501 adjust_endianness(mr, &data, size);
1502
8c56c1a5
PF
1503 if ((!kvm_eventfds_enabled()) &&
1504 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1505 return MEMTX_OK;
1506 }
1507
ce5d2f33 1508 if (mr->ops->write) {
cc05c43a
PM
1509 return access_with_adjusted_size(addr, &data, size,
1510 mr->ops->impl.min_access_size,
1511 mr->ops->impl.max_access_size,
1512 memory_region_write_accessor, mr,
1513 attrs);
62a0db94 1514 } else {
cc05c43a
PM
1515 return
1516 access_with_adjusted_size(addr, &data, size,
1517 mr->ops->impl.min_access_size,
1518 mr->ops->impl.max_access_size,
1519 memory_region_write_with_attrs_accessor,
1520 mr, attrs);
74901c3b 1521 }
093bc2cd
AK
1522}
1523
093bc2cd 1524void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1525 Object *owner,
093bc2cd
AK
1526 const MemoryRegionOps *ops,
1527 void *opaque,
1528 const char *name,
1529 uint64_t size)
1530{
2c9b15ca 1531 memory_region_init(mr, owner, name, size);
6d6d2abf 1532 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1533 mr->opaque = opaque;
14a3c10a 1534 mr->terminates = true;
093bc2cd
AK
1535}
1536
1cfe48c1
PM
1537void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1538 Object *owner,
1539 const char *name,
1540 uint64_t size,
1541 Error **errp)
06329cce
MA
1542{
1543 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1544}
1545
1546void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1547 Object *owner,
1548 const char *name,
1549 uint64_t size,
1550 bool share,
1551 Error **errp)
093bc2cd 1552{
1cd3d492 1553 Error *err = NULL;
2c9b15ca 1554 memory_region_init(mr, owner, name, size);
8ea9252a 1555 mr->ram = true;
14a3c10a 1556 mr->terminates = true;
545e92e0 1557 mr->destructor = memory_region_destructor_ram;
1cd3d492 1558 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
677e7805 1559 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1560 if (err) {
1561 mr->size = int128_zero();
1562 object_unparent(OBJECT(mr));
1563 error_propagate(errp, err);
1564 }
0b183fc8
PB
1565}
1566
60786ef3
MT
1567void memory_region_init_resizeable_ram(MemoryRegion *mr,
1568 Object *owner,
1569 const char *name,
1570 uint64_t size,
1571 uint64_t max_size,
1572 void (*resized)(const char*,
1573 uint64_t length,
1574 void *host),
1575 Error **errp)
1576{
1cd3d492 1577 Error *err = NULL;
60786ef3
MT
1578 memory_region_init(mr, owner, name, size);
1579 mr->ram = true;
1580 mr->terminates = true;
1581 mr->destructor = memory_region_destructor_ram;
8e41fb63 1582 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1583 mr, &err);
677e7805 1584 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1585 if (err) {
1586 mr->size = int128_zero();
1587 object_unparent(OBJECT(mr));
1588 error_propagate(errp, err);
1589 }
60786ef3
MT
1590}
1591
d5dbde46 1592#ifdef CONFIG_POSIX
0b183fc8
PB
1593void memory_region_init_ram_from_file(MemoryRegion *mr,
1594 struct Object *owner,
1595 const char *name,
1596 uint64_t size,
98376843 1597 uint64_t align,
cbfc0171 1598 uint32_t ram_flags,
7f56e740
PB
1599 const char *path,
1600 Error **errp)
0b183fc8 1601{
1cd3d492 1602 Error *err = NULL;
0b183fc8
PB
1603 memory_region_init(mr, owner, name, size);
1604 mr->ram = true;
1605 mr->terminates = true;
1606 mr->destructor = memory_region_destructor_ram;
98376843 1607 mr->align = align;
1cd3d492 1608 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
677e7805 1609 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1610 if (err) {
1611 mr->size = int128_zero();
1612 object_unparent(OBJECT(mr));
1613 error_propagate(errp, err);
1614 }
093bc2cd 1615}
fea617c5
MAL
1616
1617void memory_region_init_ram_from_fd(MemoryRegion *mr,
1618 struct Object *owner,
1619 const char *name,
1620 uint64_t size,
1621 bool share,
1622 int fd,
1623 Error **errp)
1624{
1cd3d492 1625 Error *err = NULL;
fea617c5
MAL
1626 memory_region_init(mr, owner, name, size);
1627 mr->ram = true;
1628 mr->terminates = true;
1629 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1630 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1631 share ? RAM_SHARED : 0,
1cd3d492 1632 fd, &err);
fea617c5 1633 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1634 if (err) {
1635 mr->size = int128_zero();
1636 object_unparent(OBJECT(mr));
1637 error_propagate(errp, err);
1638 }
fea617c5 1639}
0b183fc8 1640#endif
093bc2cd
AK
1641
1642void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1643 Object *owner,
093bc2cd
AK
1644 const char *name,
1645 uint64_t size,
1646 void *ptr)
1647{
2c9b15ca 1648 memory_region_init(mr, owner, name, size);
8ea9252a 1649 mr->ram = true;
14a3c10a 1650 mr->terminates = true;
fc3e7665 1651 mr->destructor = memory_region_destructor_ram;
677e7805 1652 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1653
1654 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1655 assert(ptr != NULL);
8e41fb63 1656 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1657}
1658
21e00fa5
AW
1659void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1660 Object *owner,
1661 const char *name,
1662 uint64_t size,
1663 void *ptr)
e4dc3f59 1664{
2ddb89b0
BS
1665 memory_region_init(mr, owner, name, size);
1666 mr->ram = true;
1667 mr->terminates = true;
21e00fa5 1668 mr->ram_device = true;
4a2e242b
AW
1669 mr->ops = &ram_device_mem_ops;
1670 mr->opaque = mr;
2ddb89b0
BS
1671 mr->destructor = memory_region_destructor_ram;
1672 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1673 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1674 assert(ptr != NULL);
1675 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND
1676}
1677
093bc2cd 1678void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1679 Object *owner,
093bc2cd
AK
1680 const char *name,
1681 MemoryRegion *orig,
a8170e5e 1682 hwaddr offset,
093bc2cd
AK
1683 uint64_t size)
1684{
2c9b15ca 1685 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1686 mr->alias = orig;
1687 mr->alias_offset = offset;
1688}
1689
b59821a9
PM
1690void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1691 struct Object *owner,
1692 const char *name,
1693 uint64_t size,
1694 Error **errp)
a1777f7f 1695{
1cd3d492 1696 Error *err = NULL;
a1777f7f
PM
1697 memory_region_init(mr, owner, name, size);
1698 mr->ram = true;
1699 mr->readonly = true;
1700 mr->terminates = true;
1701 mr->destructor = memory_region_destructor_ram;
1cd3d492 1702 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
a1777f7f 1703 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1704 if (err) {
1705 mr->size = int128_zero();
1706 object_unparent(OBJECT(mr));
1707 error_propagate(errp, err);
1708 }
a1777f7f
PM
1709}
1710
b59821a9
PM
1711void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1712 Object *owner,
1713 const MemoryRegionOps *ops,
1714 void *opaque,
1715 const char *name,
1716 uint64_t size,
1717 Error **errp)
d0a9b5bc 1718{
1cd3d492 1719 Error *err = NULL;
39e0b03d 1720 assert(ops);
2c9b15ca 1721 memory_region_init(mr, owner, name, size);
7bc2b9cd 1722 mr->ops = ops;
75f5941c 1723 mr->opaque = opaque;
d0a9b5bc 1724 mr->terminates = true;
75c578dc 1725 mr->rom_device = true;
58268c8d 1726 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1727 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1728 if (err) {
1729 mr->size = int128_zero();
1730 object_unparent(OBJECT(mr));
1731 error_propagate(errp, err);
1732 }
d0a9b5bc
AK
1733}
1734
1221a474
AK
1735void memory_region_init_iommu(void *_iommu_mr,
1736 size_t instance_size,
1737 const char *mrtypename,
2c9b15ca 1738 Object *owner,
30951157
AK
1739 const char *name,
1740 uint64_t size)
1741{
1221a474 1742 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1743 struct MemoryRegion *mr;
1744
1221a474
AK
1745 object_initialize(_iommu_mr, instance_size, mrtypename);
1746 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1747 memory_region_do_init(mr, owner, name, size);
1748 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1749 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1750 QLIST_INIT(&iommu_mr->iommu_notify);
1751 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1752}
1753
b4fefef9 1754static void memory_region_finalize(Object *obj)
093bc2cd 1755{
b4fefef9
PC
1756 MemoryRegion *mr = MEMORY_REGION(obj);
1757
2e2b8eb7
PB
1758 assert(!mr->container);
1759
1760 /* We know the region is not visible in any address space (it
1761 * does not have a container and cannot be a root either because
1762 * it has no references, so we can blindly clear mr->enabled.
1763 * memory_region_set_enabled instead could trigger a transaction
1764 * and cause an infinite loop.
1765 */
1766 mr->enabled = false;
1767 memory_region_transaction_begin();
1768 while (!QTAILQ_EMPTY(&mr->subregions)) {
1769 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1770 memory_region_del_subregion(mr, subregion);
1771 }
1772 memory_region_transaction_commit();
1773
545e92e0 1774 mr->destructor(mr);
093bc2cd 1775 memory_region_clear_coalescing(mr);
302fa283 1776 g_free((char *)mr->name);
7267c094 1777 g_free(mr->ioeventfds);
093bc2cd
AK
1778}
1779
803c0816
PB
1780Object *memory_region_owner(MemoryRegion *mr)
1781{
22a893e4
PB
1782 Object *obj = OBJECT(mr);
1783 return obj->parent;
803c0816
PB
1784}
1785
46637be2
PB
1786void memory_region_ref(MemoryRegion *mr)
1787{
22a893e4
PB
1788 /* MMIO callbacks most likely will access data that belongs
1789 * to the owner, hence the need to ref/unref the owner whenever
1790 * the memory region is in use.
1791 *
1792 * The memory region is a child of its owner. As long as the
1793 * owner doesn't call unparent itself on the memory region,
1794 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1795 * Memory regions without an owner are supposed to never go away;
1796 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1797 */
612263cf
PB
1798 if (mr && mr->owner) {
1799 object_ref(mr->owner);
46637be2
PB
1800 }
1801}
1802
1803void memory_region_unref(MemoryRegion *mr)
1804{
612263cf
PB
1805 if (mr && mr->owner) {
1806 object_unref(mr->owner);
46637be2
PB
1807 }
1808}
1809
093bc2cd
AK
1810uint64_t memory_region_size(MemoryRegion *mr)
1811{
08dafab4
AK
1812 if (int128_eq(mr->size, int128_2_64())) {
1813 return UINT64_MAX;
1814 }
1815 return int128_get64(mr->size);
093bc2cd
AK
1816}
1817
5d546d4b 1818const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1819{
d1dd32af
PC
1820 if (!mr->name) {
1821 ((MemoryRegion *)mr)->name =
1822 object_get_canonical_path_component(OBJECT(mr));
1823 }
302fa283 1824 return mr->name;
8991c79b
AK
1825}
1826
21e00fa5 1827bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1828{
21e00fa5 1829 return mr->ram_device;
e4dc3f59
ND
1830}
1831
2d1a35be 1832uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1833{
6f6a5ef3 1834 uint8_t mask = mr->dirty_log_mask;
adaad61c 1835 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1836 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1837 }
1838 return mask;
55043ba3
AK
1839}
1840
2d1a35be
PB
1841bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1842{
1843 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1844}
1845
3df9d748 1846static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1847{
1848 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1849 IOMMUNotifier *iommu_notifier;
1221a474 1850 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1851
3df9d748 1852 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1853 flags |= iommu_notifier->notifier_flags;
1854 }
1855
1221a474
AK
1856 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1857 imrc->notify_flag_changed(iommu_mr,
1858 iommu_mr->iommu_notify_flags,
1859 flags);
5bf3d319
PX
1860 }
1861
3df9d748 1862 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1863}
1864
cdb30812
PX
1865void memory_region_register_iommu_notifier(MemoryRegion *mr,
1866 IOMMUNotifier *n)
06866575 1867{
3df9d748
AK
1868 IOMMUMemoryRegion *iommu_mr;
1869
efcd38c5
JW
1870 if (mr->alias) {
1871 memory_region_register_iommu_notifier(mr->alias, n);
1872 return;
1873 }
1874
cdb30812 1875 /* We need to register for at least one bitfield */
3df9d748 1876 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1877 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1878 assert(n->start <= n->end);
cb1efcf4
PM
1879 assert(n->iommu_idx >= 0 &&
1880 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1881
3df9d748
AK
1882 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1883 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1884}
1885
3df9d748 1886uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1887{
1221a474
AK
1888 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1889
1890 if (imrc->get_min_page_size) {
1891 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1892 }
1893 return TARGET_PAGE_SIZE;
1894}
1895
3df9d748 1896void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1897{
3df9d748 1898 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1899 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1900 hwaddr addr, granularity;
a788f227
DG
1901 IOMMUTLBEntry iotlb;
1902
faa362e3 1903 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1904 if (imrc->replay) {
1905 imrc->replay(iommu_mr, n);
faa362e3
PX
1906 return;
1907 }
1908
3df9d748 1909 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1910
a788f227 1911 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1912 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1913 if (iotlb.perm != IOMMU_NONE) {
1914 n->notify(n, &iotlb);
1915 }
1916
1917 /* if (2^64 - MR size) < granularity, it's possible to get an
1918 * infinite loop here. This should catch such a wraparound */
1919 if ((addr + granularity) < addr) {
1920 break;
1921 }
1922 }
1923}
1924
3df9d748 1925void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1926{
1927 IOMMUNotifier *notifier;
1928
3df9d748
AK
1929 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1930 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1931 }
1932}
1933
cdb30812
PX
1934void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1935 IOMMUNotifier *n)
06866575 1936{
3df9d748
AK
1937 IOMMUMemoryRegion *iommu_mr;
1938
efcd38c5
JW
1939 if (mr->alias) {
1940 memory_region_unregister_iommu_notifier(mr->alias, n);
1941 return;
1942 }
cdb30812 1943 QLIST_REMOVE(n, node);
3df9d748
AK
1944 iommu_mr = IOMMU_MEMORY_REGION(mr);
1945 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1946}
1947
bd2bfa4c
PX
1948void memory_region_notify_one(IOMMUNotifier *notifier,
1949 IOMMUTLBEntry *entry)
06866575 1950{
cdb30812 1951 IOMMUNotifierFlag request_flags;
03c7140c 1952 hwaddr entry_end = entry->iova + entry->addr_mask;
cdb30812 1953
bd2bfa4c
PX
1954 /*
1955 * Skip the notification if the notification does not overlap
1956 * with registered range.
1957 */
03c7140c 1958 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX
1959 return;
1960 }
cdb30812 1961
03c7140c
YZ
1962 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1963
bd2bfa4c 1964 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1965 request_flags = IOMMU_NOTIFIER_MAP;
1966 } else {
1967 request_flags = IOMMU_NOTIFIER_UNMAP;
1968 }
1969
bd2bfa4c
PX
1970 if (notifier->notifier_flags & request_flags) {
1971 notifier->notify(notifier, entry);
1972 }
1973}
1974
3df9d748 1975void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1976 int iommu_idx,
bd2bfa4c
PX
1977 IOMMUTLBEntry entry)
1978{
1979 IOMMUNotifier *iommu_notifier;
1980
3df9d748 1981 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1982
3df9d748 1983 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM
1984 if (iommu_notifier->iommu_idx == iommu_idx) {
1985 memory_region_notify_one(iommu_notifier, &entry);
1986 }
cdb30812 1987 }
06866575
DG
1988}
1989
f1334de6
AK
1990int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1991 enum IOMMUMemoryRegionAttr attr,
1992 void *data)
1993{
1994 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1995
1996 if (!imrc->get_attr) {
1997 return -EINVAL;
1998 }
1999
2000 return imrc->get_attr(iommu_mr, attr, data);
2001}
2002
21f40209
PM
2003int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2004 MemTxAttrs attrs)
2005{
2006 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2007
2008 if (!imrc->attrs_to_index) {
2009 return 0;
2010 }
2011
2012 return imrc->attrs_to_index(iommu_mr, attrs);
2013}
2014
2015int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2016{
2017 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2018
2019 if (!imrc->num_indexes) {
2020 return 1;
2021 }
2022
2023 return imrc->num_indexes(iommu_mr);
2024}
2025
093bc2cd
AK
2026void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2027{
5a583347 2028 uint8_t mask = 1 << client;
deb809ed 2029 uint8_t old_logging;
5a583347 2030
dbddac6d 2031 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
2032 old_logging = mr->vga_logging_count;
2033 mr->vga_logging_count += log ? 1 : -1;
2034 if (!!old_logging == !!mr->vga_logging_count) {
2035 return;
2036 }
2037
59023ef4 2038 memory_region_transaction_begin();
5a583347 2039 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2040 memory_region_update_pending |= mr->enabled;
59023ef4 2041 memory_region_transaction_commit();
093bc2cd
AK
2042}
2043
a8170e5e
AK
2044void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2045 hwaddr size)
093bc2cd 2046{
8e41fb63
FZ
2047 assert(mr->ram_block);
2048 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2049 size,
58d2707e 2050 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2051}
2052
0fe1eca7 2053static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2054{
0a752eee 2055 MemoryListener *listener;
0d673e36 2056 AddressSpace *as;
0a752eee 2057 FlatView *view;
5a583347
AK
2058 FlatRange *fr;
2059
0a752eee
PB
2060 /* If the same address space has multiple log_sync listeners, we
2061 * visit that address space's FlatView multiple times. But because
2062 * log_sync listeners are rare, it's still cheaper than walking each
2063 * address space once.
2064 */
2065 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2066 if (!listener->log_sync) {
2067 continue;
2068 }
2069 as = listener->address_space;
2070 view = address_space_get_flatview(as);
99e86347 2071 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2072 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2073 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2074 listener->log_sync(listener, &mrs);
0d673e36 2075 }
5a583347 2076 }
856d7245 2077 flatview_unref(view);
5a583347 2078 }
093bc2cd
AK
2079}
2080
077874e0
PX
2081void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2082 hwaddr len)
2083{
2084 MemoryRegionSection mrs;
2085 MemoryListener *listener;
2086 AddressSpace *as;
2087 FlatView *view;
2088 FlatRange *fr;
2089 hwaddr sec_start, sec_end, sec_size;
2090
2091 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2092 if (!listener->log_clear) {
2093 continue;
2094 }
2095 as = listener->address_space;
2096 view = address_space_get_flatview(as);
2097 FOR_EACH_FLAT_RANGE(fr, view) {
2098 if (!fr->dirty_log_mask || fr->mr != mr) {
2099 /*
2100 * Clear dirty bitmap operation only applies to those
2101 * regions whose dirty logging is at least enabled
2102 */
2103 continue;
2104 }
2105
2106 mrs = section_from_flat_range(fr, view);
2107
2108 sec_start = MAX(mrs.offset_within_region, start);
2109 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2110 sec_end = MIN(sec_end, start + len);
2111
2112 if (sec_start >= sec_end) {
2113 /*
2114 * If this memory region section has no intersection
2115 * with the requested range, skip.
2116 */
2117 continue;
2118 }
2119
2120 /* Valid case; shrink the section if needed */
2121 mrs.offset_within_address_space +=
2122 sec_start - mrs.offset_within_region;
2123 mrs.offset_within_region = sec_start;
2124 sec_size = sec_end - sec_start;
2125 mrs.size = int128_make64(sec_size);
2126 listener->log_clear(listener, &mrs);
2127 }
2128 flatview_unref(view);
2129 }
2130}
2131
0fe1eca7
PB
2132DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2133 hwaddr addr,
2134 hwaddr size,
2135 unsigned client)
2136{
9458a9a1 2137 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB
2138 assert(mr->ram_block);
2139 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB
2140 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2141 memory_global_after_dirty_log_sync();
2142 return snapshot;
0fe1eca7
PB
2143}
2144
2145bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2146 hwaddr addr, hwaddr size)
2147{
2148 assert(mr->ram_block);
2149 return cpu_physical_memory_snapshot_get_dirty(snap,
2150 memory_region_get_ram_addr(mr) + addr, size);
2151}
2152
093bc2cd
AK
2153void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2154{
fb1cd6f9 2155 if (mr->readonly != readonly) {
59023ef4 2156 memory_region_transaction_begin();
fb1cd6f9 2157 mr->readonly = readonly;
22bde714 2158 memory_region_update_pending |= mr->enabled;
59023ef4 2159 memory_region_transaction_commit();
fb1cd6f9 2160 }
093bc2cd
AK
2161}
2162
c26763f8
MAL
2163void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2164{
2165 if (mr->nonvolatile != nonvolatile) {
2166 memory_region_transaction_begin();
2167 mr->nonvolatile = nonvolatile;
2168 memory_region_update_pending |= mr->enabled;
2169 memory_region_transaction_commit();
2170 }
2171}
2172
5f9a5ea1 2173void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2174{
5f9a5ea1 2175 if (mr->romd_mode != romd_mode) {
59023ef4 2176 memory_region_transaction_begin();
5f9a5ea1 2177 mr->romd_mode = romd_mode;
22bde714 2178 memory_region_update_pending |= mr->enabled;
59023ef4 2179 memory_region_transaction_commit();
d0a9b5bc
AK
2180 }
2181}
2182
a8170e5e
AK
2183void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2184 hwaddr size, unsigned client)
093bc2cd 2185{
8e41fb63
FZ
2186 assert(mr->ram_block);
2187 cpu_physical_memory_test_and_clear_dirty(
2188 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2189}
2190
a35ba7be
PB
2191int memory_region_get_fd(MemoryRegion *mr)
2192{
4ff87573
PB
2193 int fd;
2194
2195 rcu_read_lock();
2196 while (mr->alias) {
2197 mr = mr->alias;
a35ba7be 2198 }
4ff87573
PB
2199 fd = mr->ram_block->fd;
2200 rcu_read_unlock();
a35ba7be 2201
4ff87573
PB
2202 return fd;
2203}
a35ba7be 2204
093bc2cd
AK
2205void *memory_region_get_ram_ptr(MemoryRegion *mr)
2206{
49b24afc
PB
2207 void *ptr;
2208 uint64_t offset = 0;
093bc2cd 2209
49b24afc
PB
2210 rcu_read_lock();
2211 while (mr->alias) {
2212 offset += mr->alias_offset;
2213 mr = mr->alias;
2214 }
8e41fb63 2215 assert(mr->ram_block);
0878d0e1 2216 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2217 rcu_read_unlock();
093bc2cd 2218
0878d0e1 2219 return ptr;
093bc2cd
AK
2220}
2221
07bdaa41
PB
2222MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2223{
2224 RAMBlock *block;
2225
2226 block = qemu_ram_block_from_host(ptr, false, offset);
2227 if (!block) {
2228 return NULL;
2229 }
2230
2231 return block->mr;
2232}
2233
7ebb2745
FZ
2234ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2235{
2236 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2237}
2238
37d7c084
PB
2239void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2240{
8e41fb63 2241 assert(mr->ram_block);
37d7c084 2242
fa53a0e5 2243 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2244}
2245
b960fc17
PX
2246/*
2247 * Call proper memory listeners about the change on the newly
2248 * added/removed CoalescedMemoryRange.
2249 */
2250static void memory_region_update_coalesced_range(MemoryRegion *mr,
2251 CoalescedMemoryRange *cmr,
2252 bool add)
093bc2cd 2253{
b960fc17 2254 AddressSpace *as;
99e86347 2255 FlatView *view;
093bc2cd 2256 FlatRange *fr;
093bc2cd 2257
0d673e36 2258 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b960fc17
PX
2259 view = address_space_get_flatview(as);
2260 FOR_EACH_FLAT_RANGE(fr, view) {
2261 if (fr->mr == mr) {
2262 flat_range_coalesced_io_notify(fr, as, cmr, add);
2263 }
2264 }
2265 flatview_unref(view);
0d673e36
AK
2266 }
2267}
2268
093bc2cd
AK
2269void memory_region_set_coalescing(MemoryRegion *mr)
2270{
2271 memory_region_clear_coalescing(mr);
08dafab4 2272 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2273}
2274
2275void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2276 hwaddr offset,
093bc2cd
AK
2277 uint64_t size)
2278{
7267c094 2279 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2280
08dafab4 2281 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd 2282 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
b960fc17 2283 memory_region_update_coalesced_range(mr, cmr, true);
d410515e 2284 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2285}
2286
2287void memory_region_clear_coalescing(MemoryRegion *mr)
2288{
2289 CoalescedMemoryRange *cmr;
9c1aa1c2
PX
2290
2291 if (QTAILQ_EMPTY(&mr->coalesced)) {
2292 return;
2293 }
093bc2cd 2294
d410515e
JK
2295 qemu_flush_coalesced_mmio_buffer();
2296 mr->flush_coalesced_mmio = false;
2297
093bc2cd
AK
2298 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2299 cmr = QTAILQ_FIRST(&mr->coalesced);
2300 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
b960fc17 2301 memory_region_update_coalesced_range(mr, cmr, false);
7267c094 2302 g_free(cmr);
ab5b3db5 2303 }
093bc2cd
AK
2304}
2305
d410515e
JK
2306void memory_region_set_flush_coalesced(MemoryRegion *mr)
2307{
2308 mr->flush_coalesced_mmio = true;
2309}
2310
2311void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2312{
2313 qemu_flush_coalesced_mmio_buffer();
2314 if (QTAILQ_EMPTY(&mr->coalesced)) {
2315 mr->flush_coalesced_mmio = false;
2316 }
2317}
2318
196ea131
JK
2319void memory_region_clear_global_locking(MemoryRegion *mr)
2320{
2321 mr->global_locking = false;
2322}
2323
8c56c1a5
PF
2324static bool userspace_eventfd_warning;
2325
3e9d69e7 2326void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2327 hwaddr addr,
3e9d69e7
AK
2328 unsigned size,
2329 bool match_data,
2330 uint64_t data,
753d5e14 2331 EventNotifier *e)
3e9d69e7
AK
2332{
2333 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2334 .addr.start = int128_make64(addr),
2335 .addr.size = int128_make64(size),
3e9d69e7
AK
2336 .match_data = match_data,
2337 .data = data,
753d5e14 2338 .e = e,
3e9d69e7
AK
2339 };
2340 unsigned i;
2341
8c56c1a5
PF
2342 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2343 userspace_eventfd_warning))) {
2344 userspace_eventfd_warning = true;
2345 error_report("Using eventfd without MMIO binding in KVM. "
2346 "Suboptimal performance expected");
2347 }
2348
b8aecea2
JW
2349 if (size) {
2350 adjust_endianness(mr, &mrfd.data, size);
2351 }
59023ef4 2352 memory_region_transaction_begin();
3e9d69e7 2353 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2354 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2355 break;
2356 }
2357 }
2358 ++mr->ioeventfd_nb;
7267c094 2359 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2360 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2361 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2362 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2363 mr->ioeventfds[i] = mrfd;
4dc56152 2364 ioeventfd_update_pending |= mr->enabled;
59023ef4 2365 memory_region_transaction_commit();
3e9d69e7
AK
2366}
2367
2368void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2369 hwaddr addr,
3e9d69e7
AK
2370 unsigned size,
2371 bool match_data,
2372 uint64_t data,
753d5e14 2373 EventNotifier *e)
3e9d69e7
AK
2374{
2375 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2376 .addr.start = int128_make64(addr),
2377 .addr.size = int128_make64(size),
3e9d69e7
AK
2378 .match_data = match_data,
2379 .data = data,
753d5e14 2380 .e = e,
3e9d69e7
AK
2381 };
2382 unsigned i;
2383
b8aecea2
JW
2384 if (size) {
2385 adjust_endianness(mr, &mrfd.data, size);
2386 }
59023ef4 2387 memory_region_transaction_begin();
3e9d69e7 2388 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2389 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2390 break;
2391 }
2392 }
2393 assert(i != mr->ioeventfd_nb);
2394 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2395 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2396 --mr->ioeventfd_nb;
7267c094 2397 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2398 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2399 ioeventfd_update_pending |= mr->enabled;
59023ef4 2400 memory_region_transaction_commit();
3e9d69e7
AK
2401}
2402
feca4ac1 2403static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2404{
feca4ac1 2405 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2406 MemoryRegion *other;
2407
59023ef4
JK
2408 memory_region_transaction_begin();
2409
dfde4e6e 2410 memory_region_ref(subregion);
093bc2cd
AK
2411 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2412 if (subregion->priority >= other->priority) {
2413 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2414 goto done;
2415 }
2416 }
2417 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2418done:
22bde714 2419 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2420 memory_region_transaction_commit();
093bc2cd
AK
2421}
2422
0598701a
PC
2423static void memory_region_add_subregion_common(MemoryRegion *mr,
2424 hwaddr offset,
2425 MemoryRegion *subregion)
2426{
feca4ac1
PB
2427 assert(!subregion->container);
2428 subregion->container = mr;
0598701a 2429 subregion->addr = offset;
feca4ac1 2430 memory_region_update_container_subregions(subregion);
0598701a 2431}
093bc2cd
AK
2432
2433void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2434 hwaddr offset,
093bc2cd
AK
2435 MemoryRegion *subregion)
2436{
093bc2cd
AK
2437 subregion->priority = 0;
2438 memory_region_add_subregion_common(mr, offset, subregion);
2439}
2440
2441void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2442 hwaddr offset,
093bc2cd 2443 MemoryRegion *subregion,
a1ff8ae0 2444 int priority)
093bc2cd 2445{
093bc2cd
AK
2446 subregion->priority = priority;
2447 memory_region_add_subregion_common(mr, offset, subregion);
2448}
2449
2450void memory_region_del_subregion(MemoryRegion *mr,
2451 MemoryRegion *subregion)
2452{
59023ef4 2453 memory_region_transaction_begin();
feca4ac1
PB
2454 assert(subregion->container == mr);
2455 subregion->container = NULL;
093bc2cd 2456 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2457 memory_region_unref(subregion);
22bde714 2458 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2459 memory_region_transaction_commit();
6bba19ba
AK
2460}
2461
2462void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2463{
2464 if (enabled == mr->enabled) {
2465 return;
2466 }
59023ef4 2467 memory_region_transaction_begin();
6bba19ba 2468 mr->enabled = enabled;
22bde714 2469 memory_region_update_pending = true;
59023ef4 2470 memory_region_transaction_commit();
093bc2cd 2471}
1c0ffa58 2472
e7af4c67
MT
2473void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2474{
2475 Int128 s = int128_make64(size);
2476
2477 if (size == UINT64_MAX) {
2478 s = int128_2_64();
2479 }
2480 if (int128_eq(s, mr->size)) {
2481 return;
2482 }
2483 memory_region_transaction_begin();
2484 mr->size = s;
2485 memory_region_update_pending = true;
2486 memory_region_transaction_commit();
2487}
2488
67891b8a 2489static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2490{
feca4ac1 2491 MemoryRegion *container = mr->container;
2282e1af 2492
feca4ac1 2493 if (container) {
67891b8a
PC
2494 memory_region_transaction_begin();
2495 memory_region_ref(mr);
feca4ac1
PB
2496 memory_region_del_subregion(container, mr);
2497 mr->container = container;
2498 memory_region_update_container_subregions(mr);
67891b8a
PC
2499 memory_region_unref(mr);
2500 memory_region_transaction_commit();
2282e1af 2501 }
67891b8a 2502}
2282e1af 2503
67891b8a
PC
2504void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2505{
2506 if (addr != mr->addr) {
2507 mr->addr = addr;
2508 memory_region_readd_subregion(mr);
2509 }
2282e1af
AK
2510}
2511
a8170e5e 2512void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2513{
4703359e 2514 assert(mr->alias);
4703359e 2515
59023ef4 2516 if (offset == mr->alias_offset) {
4703359e
AK
2517 return;
2518 }
2519
59023ef4
JK
2520 memory_region_transaction_begin();
2521 mr->alias_offset = offset;
22bde714 2522 memory_region_update_pending |= mr->enabled;
59023ef4 2523 memory_region_transaction_commit();
4703359e
AK
2524}
2525
a2b257d6
IM
2526uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2527{
2528 return mr->align;
2529}
2530
e2177955
AK
2531static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2532{
2533 const AddrRange *addr = addr_;
2534 const FlatRange *fr = fr_;
2535
2536 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2537 return -1;
2538 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2539 return 1;
2540 }
2541 return 0;
2542}
2543
99e86347 2544static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2545{
99e86347 2546 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2547 sizeof(FlatRange), cmp_flatrange_addr);
2548}
2549
eed2bacf
IM
2550bool memory_region_is_mapped(MemoryRegion *mr)
2551{
2552 return mr->container ? true : false;
2553}
2554
c6742b14
PB
2555/* Same as memory_region_find, but it does not add a reference to the
2556 * returned region. It must be called from an RCU critical section.
2557 */
2558static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2559 hwaddr addr, uint64_t size)
e2177955 2560{
052e87b0 2561 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2562 MemoryRegion *root;
2563 AddressSpace *as;
2564 AddrRange range;
99e86347 2565 FlatView *view;
73034e9e
PB
2566 FlatRange *fr;
2567
2568 addr += mr->addr;
feca4ac1
PB
2569 for (root = mr; root->container; ) {
2570 root = root->container;
73034e9e
PB
2571 addr += root->addr;
2572 }
e2177955 2573
73034e9e 2574 as = memory_region_to_address_space(root);
eed2bacf
IM
2575 if (!as) {
2576 return ret;
2577 }
73034e9e 2578 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2579
16620684 2580 view = address_space_to_flatview(as);
99e86347 2581 fr = flatview_lookup(view, range);
e2177955 2582 if (!fr) {
c6742b14 2583 return ret;
e2177955
AK
2584 }
2585
99e86347 2586 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2587 --fr;
2588 }
2589
2590 ret.mr = fr->mr;
16620684 2591 ret.fv = view;
e2177955
AK
2592 range = addrrange_intersection(range, fr->addr);
2593 ret.offset_within_region = fr->offset_in_region;
2594 ret.offset_within_region += int128_get64(int128_sub(range.start,
2595 fr->addr.start));
052e87b0 2596 ret.size = range.size;
e2177955 2597 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2598 ret.readonly = fr->readonly;
c26763f8 2599 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2600 return ret;
2601}
2602
2603MemoryRegionSection memory_region_find(MemoryRegion *mr,
2604 hwaddr addr, uint64_t size)
2605{
2606 MemoryRegionSection ret;
2607 rcu_read_lock();
2608 ret = memory_region_find_rcu(mr, addr, size);
2609 if (ret.mr) {
2610 memory_region_ref(ret.mr);
2611 }
2b647668 2612 rcu_read_unlock();
e2177955
AK
2613 return ret;
2614}
2615
c6742b14
PB
2616bool memory_region_present(MemoryRegion *container, hwaddr addr)
2617{
2618 MemoryRegion *mr;
2619
2620 rcu_read_lock();
2621 mr = memory_region_find_rcu(container, addr, 1).mr;
2622 rcu_read_unlock();
2623 return mr && mr != container;
2624}
2625
9c1f8f44 2626void memory_global_dirty_log_sync(void)
86e775c6 2627{
3ebb1817 2628 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2629}
2630
9458a9a1
PB
2631void memory_global_after_dirty_log_sync(void)
2632{
2633 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2634}
2635
19310760
JZ
2636static VMChangeStateEntry *vmstate_change;
2637
7664e80c
AK
2638void memory_global_dirty_log_start(void)
2639{
19310760
JZ
2640 if (vmstate_change) {
2641 qemu_del_vm_change_state_handler(vmstate_change);
2642 vmstate_change = NULL;
2643 }
2644
7664e80c 2645 global_dirty_log = true;
6f6a5ef3 2646
7376e582 2647 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3 2648
39adb536 2649 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2650 memory_region_transaction_begin();
2651 memory_region_update_pending = true;
2652 memory_region_transaction_commit();
7664e80c
AK
2653}
2654
19310760 2655static void memory_global_dirty_log_do_stop(void)
7664e80c 2656{
7664e80c 2657 global_dirty_log = false;
6f6a5ef3 2658
39adb536 2659 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2660 memory_region_transaction_begin();
2661 memory_region_update_pending = true;
2662 memory_region_transaction_commit();
2663
7376e582 2664 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2665}
2666
19310760
JZ
2667static void memory_vm_change_state_handler(void *opaque, int running,
2668 RunState state)
2669{
2670 if (running) {
2671 memory_global_dirty_log_do_stop();
2672
2673 if (vmstate_change) {
2674 qemu_del_vm_change_state_handler(vmstate_change);
2675 vmstate_change = NULL;
2676 }
2677 }
2678}
2679
2680void memory_global_dirty_log_stop(void)
2681{
2682 if (!runstate_is_running()) {
2683 if (vmstate_change) {
2684 return;
2685 }
2686 vmstate_change = qemu_add_vm_change_state_handler(
2687 memory_vm_change_state_handler, NULL);
2688 return;
2689 }
2690
2691 memory_global_dirty_log_do_stop();
2692}
2693
7664e80c
AK
2694static void listener_add_address_space(MemoryListener *listener,
2695 AddressSpace *as)
2696{
99e86347 2697 FlatView *view;
7664e80c
AK
2698 FlatRange *fr;
2699
680a4783
PB
2700 if (listener->begin) {
2701 listener->begin(listener);
2702 }
7664e80c 2703 if (global_dirty_log) {
975aefe0
AK
2704 if (listener->log_global_start) {
2705 listener->log_global_start(listener);
2706 }
7664e80c 2707 }
975aefe0 2708
856d7245 2709 view = address_space_get_flatview(as);
99e86347 2710 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2711 MemoryRegionSection section = section_from_flat_range(fr, view);
2712
975aefe0
AK
2713 if (listener->region_add) {
2714 listener->region_add(listener, &section);
2715 }
ae990e6c
DH
2716 if (fr->dirty_log_mask && listener->log_start) {
2717 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2718 }
7664e80c 2719 }
680a4783
PB
2720 if (listener->commit) {
2721 listener->commit(listener);
2722 }
856d7245 2723 flatview_unref(view);
7664e80c
AK
2724}
2725
d25836ca
PX
2726static void listener_del_address_space(MemoryListener *listener,
2727 AddressSpace *as)
2728{
2729 FlatView *view;
2730 FlatRange *fr;
2731
2732 if (listener->begin) {
2733 listener->begin(listener);
2734 }
2735 view = address_space_get_flatview(as);
2736 FOR_EACH_FLAT_RANGE(fr, view) {
2737 MemoryRegionSection section = section_from_flat_range(fr, view);
2738
2739 if (fr->dirty_log_mask && listener->log_stop) {
2740 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2741 }
2742 if (listener->region_del) {
2743 listener->region_del(listener, &section);
2744 }
2745 }
2746 if (listener->commit) {
2747 listener->commit(listener);
2748 }
2749 flatview_unref(view);
2750}
2751
d45fa784 2752void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2753{
72e22d2f
AK
2754 MemoryListener *other = NULL;
2755
d45fa784 2756 listener->address_space = as;
72e22d2f 2757 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2758 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK
2759 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2760 } else {
2761 QTAILQ_FOREACH(other, &memory_listeners, link) {
2762 if (listener->priority < other->priority) {
2763 break;
2764 }
2765 }
2766 QTAILQ_INSERT_BEFORE(other, listener, link);
2767 }
0d673e36 2768
9a54635d 2769 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2770 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB
2771 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2772 } else {
2773 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2774 if (listener->priority < other->priority) {
2775 break;
2776 }
2777 }
2778 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2779 }
2780
d45fa784 2781 listener_add_address_space(listener, as);
7664e80c
AK
2782}
2783
2784void memory_listener_unregister(MemoryListener *listener)
2785{
1d8280c1
PB
2786 if (!listener->address_space) {
2787 return;
2788 }
2789
d25836ca 2790 listener_del_address_space(listener, listener->address_space);
72e22d2f 2791 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2792 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2793 listener->address_space = NULL;
86e775c6 2794}
e2177955 2795
a2166410
GK
2796void address_space_remove_listeners(AddressSpace *as)
2797{
2798 while (!QTAILQ_EMPTY(&as->listeners)) {
2799 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2800 }
2801}
2802
7dca8043 2803void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2804{
ac95190e 2805 memory_region_ref(root);
8786db7c 2806 as->root = root;
67ace39b 2807 as->current_map = NULL;
4c19eb72
AK
2808 as->ioeventfd_nb = 0;
2809 as->ioeventfds = NULL;
9a54635d 2810 QTAILQ_INIT(&as->listeners);
0d673e36 2811 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2812 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2813 address_space_update_topology(as);
2814 address_space_update_ioeventfds(as);
1c0ffa58 2815}
658b2224 2816
374f2981 2817static void do_address_space_destroy(AddressSpace *as)
83f3c251 2818{
9a54635d 2819 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2820
856d7245 2821 flatview_unref(as->current_map);
7dca8043 2822 g_free(as->name);
4c19eb72 2823 g_free(as->ioeventfds);
ac95190e 2824 memory_region_unref(as->root);
83f3c251
AK
2825}
2826
374f2981
PB
2827void address_space_destroy(AddressSpace *as)
2828{
ac95190e
PB
2829 MemoryRegion *root = as->root;
2830
374f2981
PB
2831 /* Flush out anything from MemoryListeners listening in on this */
2832 memory_region_transaction_begin();
2833 as->root = NULL;
2834 memory_region_transaction_commit();
2835 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2836
2837 /* At this point, as->dispatch and as->current_map are dummy
2838 * entries that the guest should never use. Wait for the old
2839 * values to expire before freeing the data.
2840 */
ac95190e 2841 as->root = root;
374f2981
PB
2842 call_rcu(as, do_address_space_destroy, rcu);
2843}
2844
4e831901
PX
2845static const char *memory_region_type(MemoryRegion *mr)
2846{
2847 if (memory_region_is_ram_device(mr)) {
2848 return "ramd";
2849 } else if (memory_region_is_romd(mr)) {
2850 return "romd";
2851 } else if (memory_region_is_rom(mr)) {
2852 return "rom";
2853 } else if (memory_region_is_ram(mr)) {
2854 return "ram";
2855 } else {
2856 return "i/o";
2857 }
2858}
2859
314e2987
BS
2860typedef struct MemoryRegionList MemoryRegionList;
2861
2862struct MemoryRegionList {
2863 const MemoryRegion *mr;
a16878d2 2864 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2865};
2866
b58deb34 2867typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 2868
4e831901
PX
2869#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2870 int128_sub((size), int128_one())) : 0)
2871#define MTREE_INDENT " "
2872
b6b71cb5 2873static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK
2874{
2875 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2876
b6b71cb5 2877 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 2878 if (dev && dev->id) {
b6b71cb5 2879 qemu_printf(" id=%s", dev->id);
fc051ae6
AK
2880 } else {
2881 gchar *canonical_path = object_get_canonical_path(obj);
2882 if (canonical_path) {
b6b71cb5 2883 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK
2884 g_free(canonical_path);
2885 } else {
b6b71cb5 2886 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK
2887 }
2888 }
b6b71cb5 2889 qemu_printf("}");
fc051ae6
AK
2890}
2891
b6b71cb5 2892static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK
2893{
2894 Object *owner = mr->owner;
2895 Object *parent = memory_region_owner((MemoryRegion *)mr);
2896
2897 if (!owner && !parent) {
b6b71cb5 2898 qemu_printf(" orphan");
fc051ae6
AK
2899 return;
2900 }
2901 if (owner) {
b6b71cb5 2902 mtree_expand_owner("owner", owner);
fc051ae6
AK
2903 }
2904 if (parent && parent != owner) {
b6b71cb5 2905 mtree_expand_owner("parent", parent);
fc051ae6
AK
2906 }
2907}
2908
b6b71cb5 2909static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 2910 hwaddr base,
fc051ae6
AK
2911 MemoryRegionListHead *alias_print_queue,
2912 bool owner)
314e2987 2913{
9479c57a
JK
2914 MemoryRegionList *new_ml, *ml, *next_ml;
2915 MemoryRegionListHead submr_print_queue;
314e2987
BS
2916 const MemoryRegion *submr;
2917 unsigned int i;
b31f8412 2918 hwaddr cur_start, cur_end;
314e2987 2919
f8a9f720 2920 if (!mr) {
314e2987
BS
2921 return;
2922 }
2923
2924 for (i = 0; i < level; i++) {
b6b71cb5 2925 qemu_printf(MTREE_INDENT);
314e2987
BS
2926 }
2927
b31f8412
PX
2928 cur_start = base + mr->addr;
2929 cur_end = cur_start + MR_SIZE(mr->size);
2930
2931 /*
2932 * Try to detect overflow of memory region. This should never
2933 * happen normally. When it happens, we dump something to warn the
2934 * user who is observing this.
2935 */
2936 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 2937 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX
2938 }
2939
314e2987
BS
2940 if (mr->alias) {
2941 MemoryRegionList *ml;
2942 bool found = false;
2943
2944 /* check if the alias is already in the queue */
a16878d2 2945 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2946 if (ml->mr == mr->alias) {
314e2987
BS
2947 found = true;
2948 }
2949 }
2950
2951 if (!found) {
2952 ml = g_new(MemoryRegionList, 1);
2953 ml->mr = mr->alias;
a16878d2 2954 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2955 }
b6b71cb5
MA
2956 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2957 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2958 "-" TARGET_FMT_plx "%s",
2959 cur_start, cur_end,
2960 mr->priority,
2961 mr->nonvolatile ? "nv-" : "",
2962 memory_region_type((MemoryRegion *)mr),
2963 memory_region_name(mr),
2964 memory_region_name(mr->alias),
2965 mr->alias_offset,
2966 mr->alias_offset + MR_SIZE(mr->size),
2967 mr->enabled ? "" : " [disabled]");
fc051ae6 2968 if (owner) {
b6b71cb5 2969 mtree_print_mr_owner(mr);
fc051ae6 2970 }
314e2987 2971 } else {
b6b71cb5
MA
2972 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2973 " (prio %d, %s%s): %s%s",
2974 cur_start, cur_end,
2975 mr->priority,
2976 mr->nonvolatile ? "nv-" : "",
2977 memory_region_type((MemoryRegion *)mr),
2978 memory_region_name(mr),
2979 mr->enabled ? "" : " [disabled]");
fc051ae6 2980 if (owner) {
b6b71cb5 2981 mtree_print_mr_owner(mr);
fc051ae6 2982 }
314e2987 2983 }
b6b71cb5 2984 qemu_printf("\n");
9479c57a
JK
2985
2986 QTAILQ_INIT(&submr_print_queue);
2987
314e2987 2988 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2989 new_ml = g_new(MemoryRegionList, 1);
2990 new_ml->mr = submr;
a16878d2 2991 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2992 if (new_ml->mr->addr < ml->mr->addr ||
2993 (new_ml->mr->addr == ml->mr->addr &&
2994 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2995 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2996 new_ml = NULL;
2997 break;
2998 }
2999 }
3000 if (new_ml) {
a16878d2 3001 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
3002 }
3003 }
3004
a16878d2 3005 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 3006 mtree_print_mr(ml->mr, level + 1, cur_start,
fc051ae6 3007 alias_print_queue, owner);
9479c57a
JK
3008 }
3009
a16878d2 3010 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 3011 g_free(ml);
314e2987
BS
3012 }
3013}
3014
5e8fd947 3015struct FlatViewInfo {
5e8fd947
AK
3016 int counter;
3017 bool dispatch_tree;
fc051ae6 3018 bool owner;
8072aae3
AK
3019 AccelClass *ac;
3020 const char *ac_name;
5e8fd947
AK
3021};
3022
3023static void mtree_print_flatview(gpointer key, gpointer value,
3024 gpointer user_data)
57bb40c9 3025{
5e8fd947
AK
3026 FlatView *view = key;
3027 GArray *fv_address_spaces = value;
3028 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX
3029 FlatRange *range = &view->ranges[0];
3030 MemoryRegion *mr;
3031 int n = view->nr;
5e8fd947
AK
3032 int i;
3033 AddressSpace *as;
3034
b6b71cb5 3035 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK
3036 ++fvi->counter;
3037
3038 for (i = 0; i < fv_address_spaces->len; ++i) {
3039 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA
3040 qemu_printf(" AS \"%s\", root: %s",
3041 as->name, memory_region_name(as->root));
5e8fd947 3042 if (as->root->alias) {
b6b71cb5 3043 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3044 }
b6b71cb5 3045 qemu_printf("\n");
5e8fd947
AK
3046 }
3047
b6b71cb5 3048 qemu_printf(" Root memory region: %s\n",
5e8fd947 3049 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
3050
3051 if (n <= 0) {
b6b71cb5 3052 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
3053 return;
3054 }
3055
3056 while (n--) {
3057 mr = range->mr;
377a07aa 3058 if (range->offset_in_region) {
b6b71cb5
MA
3059 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3060 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3061 int128_get64(range->addr.start),
3062 int128_get64(range->addr.start)
3063 + MR_SIZE(range->addr.size),
3064 mr->priority,
3065 range->nonvolatile ? "nv-" : "",
3066 range->readonly ? "rom" : memory_region_type(mr),
3067 memory_region_name(mr),
3068 range->offset_in_region);
377a07aa 3069 } else {
b6b71cb5
MA
3070 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3071 " (prio %d, %s%s): %s",
3072 int128_get64(range->addr.start),
3073 int128_get64(range->addr.start)
3074 + MR_SIZE(range->addr.size),
3075 mr->priority,
3076 range->nonvolatile ? "nv-" : "",
3077 range->readonly ? "rom" : memory_region_type(mr),
3078 memory_region_name(mr));
377a07aa 3079 }
fc051ae6 3080 if (fvi->owner) {
b6b71cb5 3081 mtree_print_mr_owner(mr);
fc051ae6 3082 }
8072aae3
AK
3083
3084 if (fvi->ac) {
3085 for (i = 0; i < fv_address_spaces->len; ++i) {
3086 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3087 if (fvi->ac->has_memory(current_machine, as,
3088 int128_get64(range->addr.start),
3089 MR_SIZE(range->addr.size) + 1)) {
3090 qemu_printf(" %s", fvi->ac_name);
3091 }
3092 }
3093 }
b6b71cb5 3094 qemu_printf("\n");
57bb40c9
PX
3095 range++;
3096 }
3097
5e8fd947
AK
3098#if !defined(CONFIG_USER_ONLY)
3099 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3100 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK
3101 }
3102#endif
3103
b6b71cb5 3104 qemu_printf("\n");
5e8fd947
AK
3105}
3106
3107static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3108 gpointer user_data)
3109{
3110 FlatView *view = key;
3111 GArray *fv_address_spaces = value;
3112
3113 g_array_unref(fv_address_spaces);
57bb40c9 3114 flatview_unref(view);
5e8fd947
AK
3115
3116 return true;
57bb40c9
PX
3117}
3118
b6b71cb5 3119void mtree_info(bool flatview, bool dispatch_tree, bool owner)
314e2987
BS
3120{
3121 MemoryRegionListHead ml_head;
3122 MemoryRegionList *ml, *ml2;
0d673e36 3123 AddressSpace *as;
314e2987 3124
57bb40c9 3125 if (flatview) {
5e8fd947
AK
3126 FlatView *view;
3127 struct FlatViewInfo fvi = {
5e8fd947 3128 .counter = 0,
fc051ae6
AK
3129 .dispatch_tree = dispatch_tree,
3130 .owner = owner,
5e8fd947
AK
3131 };
3132 GArray *fv_address_spaces;
3133 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
8072aae3
AK
3134 AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator);
3135
3136 if (ac->has_memory) {
3137 fvi.ac = ac;
3138 fvi.ac_name = current_machine->accel ? current_machine->accel :
3139 object_class_get_name(OBJECT_CLASS(ac));
3140 }
5e8fd947
AK
3141
3142 /* Gather all FVs in one table */
57bb40c9 3143 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3144 view = address_space_get_flatview(as);
3145
3146 fv_address_spaces = g_hash_table_lookup(views, view);
3147 if (!fv_address_spaces) {
3148 fv_address_spaces = g_array_new(false, false, sizeof(as));
3149 g_hash_table_insert(views, view, fv_address_spaces);
3150 }
3151
3152 g_array_append_val(fv_address_spaces, as);
57bb40c9 3153 }
5e8fd947
AK
3154
3155 /* Print */
3156 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3157
3158 /* Free */
3159 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3160 g_hash_table_unref(views);
3161
57bb40c9
PX
3162 return;
3163 }
3164
314e2987
BS
3165 QTAILQ_INIT(&ml_head);
3166
0d673e36 3167 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b6b71cb5
MA
3168 qemu_printf("address-space: %s\n", as->name);
3169 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3170 qemu_printf("\n");
b9f9be88
BS
3171 }
3172
314e2987 3173 /* print aliased regions */
a16878d2 3174 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5
MA
3175 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3176 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3177 qemu_printf("\n");
314e2987
BS
3178 }
3179
a16878d2 3180 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3181 g_free(ml);
314e2987 3182 }
314e2987 3183}
b4fefef9 3184
b08199c6
PM
3185void memory_region_init_ram(MemoryRegion *mr,
3186 struct Object *owner,
3187 const char *name,
3188 uint64_t size,
3189 Error **errp)
3190{
3191 DeviceState *owner_dev;
3192 Error *err = NULL;
3193
3194 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3195 if (err) {
3196 error_propagate(errp, err);
3197 return;
3198 }
3199 /* This will assert if owner is neither NULL nor a DeviceState.
3200 * We only want the owner here for the purposes of defining a
3201 * unique name for migration. TODO: Ideally we should implement
3202 * a naming scheme for Objects which are not DeviceStates, in
3203 * which case we can relax this restriction.
3204 */
3205 owner_dev = DEVICE(owner);
3206 vmstate_register_ram(mr, owner_dev);
3207}
3208
3209void memory_region_init_rom(MemoryRegion *mr,
3210 struct Object *owner,
3211 const char *name,
3212 uint64_t size,
3213 Error **errp)
3214{
3215 DeviceState *owner_dev;
3216 Error *err = NULL;
3217
3218 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3219 if (err) {
3220 error_propagate(errp, err);
3221 return;
3222 }
3223 /* This will assert if owner is neither NULL nor a DeviceState.
3224 * We only want the owner here for the purposes of defining a
3225 * unique name for migration. TODO: Ideally we should implement
3226 * a naming scheme for Objects which are not DeviceStates, in
3227 * which case we can relax this restriction.
3228 */
3229 owner_dev = DEVICE(owner);
3230 vmstate_register_ram(mr, owner_dev);
3231}
3232
3233void memory_region_init_rom_device(MemoryRegion *mr,
3234 struct Object *owner,
3235 const MemoryRegionOps *ops,
3236 void *opaque,
3237 const char *name,
3238 uint64_t size,
3239 Error **errp)
3240{
3241 DeviceState *owner_dev;
3242 Error *err = NULL;
3243
3244 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3245 name, size, &err);
3246 if (err) {
3247 error_propagate(errp, err);
3248 return;
3249 }
3250 /* This will assert if owner is neither NULL nor a DeviceState.
3251 * We only want the owner here for the purposes of defining a
3252 * unique name for migration. TODO: Ideally we should implement
3253 * a naming scheme for Objects which are not DeviceStates, in
3254 * which case we can relax this restriction.
3255 */
3256 owner_dev = DEVICE(owner);
3257 vmstate_register_ram(mr, owner_dev);
3258}
3259
b4fefef9
PC
3260static const TypeInfo memory_region_info = {
3261 .parent = TYPE_OBJECT,
3262 .name = TYPE_MEMORY_REGION,
1b53ecd9 3263 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC
3264 .instance_size = sizeof(MemoryRegion),
3265 .instance_init = memory_region_initfn,
3266 .instance_finalize = memory_region_finalize,
3267};
3268
3df9d748
AK
3269static const TypeInfo iommu_memory_region_info = {
3270 .parent = TYPE_MEMORY_REGION,
3271 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3272 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3273 .instance_size = sizeof(IOMMUMemoryRegion),
3274 .instance_init = iommu_memory_region_initfn,
1221a474 3275 .abstract = true,
3df9d748
AK
3276};
3277
b4fefef9
PC
3278static void memory_register_types(void)
3279{
3280 type_register_static(&memory_region_info);
3df9d748 3281 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3282}
3283
3284type_init(memory_register_types)